./Ultimate.py --spec ../../sv-benchmarks/c/properties/termination.prp --file ../../sv-benchmarks/c/systemc/transmitter.02.cil.c --full-output --architecture 32bit -------------------------------------------------------------------------------- Checking for termination Using default analysis Version e7bb482b Calling Ultimate with: /usr/lib/jvm/java-1.11.0-openjdk-amd64/bin/java -Dosgi.configuration.area=/tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_69caa52f-ede6-4d44-b7cb-879a059aaf8c/bin/uautomizer-verify-WvqO1wxjHP/data/config -Xmx15G -Xms4m -jar /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_69caa52f-ede6-4d44-b7cb-879a059aaf8c/bin/uautomizer-verify-WvqO1wxjHP/plugins/org.eclipse.equinox.launcher_1.5.800.v20200727-1323.jar -data @noDefault -ultimatedata /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_69caa52f-ede6-4d44-b7cb-879a059aaf8c/bin/uautomizer-verify-WvqO1wxjHP/data -tc /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_69caa52f-ede6-4d44-b7cb-879a059aaf8c/bin/uautomizer-verify-WvqO1wxjHP/config/AutomizerTermination.xml -i ../../sv-benchmarks/c/systemc/transmitter.02.cil.c -s /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_69caa52f-ede6-4d44-b7cb-879a059aaf8c/bin/uautomizer-verify-WvqO1wxjHP/config/svcomp-Termination-32bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_69caa52f-ede6-4d44-b7cb-879a059aaf8c/bin/uautomizer-verify-WvqO1wxjHP --witnessprinter.witness.filename witness.graphml --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(F end) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 32bit --witnessprinter.graph.data.programhash 2cbfaf31aa56f767af01fea9a12ccb47d60ab19076d72b85e8ca46d6ff778e4c --- Real Ultimate output --- This is Ultimate 0.2.3-dev-e7bb482 [2023-11-06 23:09:09,809 INFO L188 SettingsManager]: Resetting all preferences to default values... [2023-11-06 23:09:09,926 INFO L114 SettingsManager]: Loading settings from /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_69caa52f-ede6-4d44-b7cb-879a059aaf8c/bin/uautomizer-verify-WvqO1wxjHP/config/svcomp-Termination-32bit-Automizer_Default.epf [2023-11-06 23:09:09,938 WARN L101 SettingsManager]: Preference file contains the following unknown settings: [2023-11-06 23:09:09,939 WARN L103 SettingsManager]: * de.uni_freiburg.informatik.ultimate.core.Log level for class [2023-11-06 23:09:09,976 INFO L130 SettingsManager]: Preferences different from defaults after loading the file: [2023-11-06 23:09:09,978 INFO L151 SettingsManager]: Preferences of UltimateCore differ from their defaults: [2023-11-06 23:09:09,979 INFO L153 SettingsManager]: * Log level for class=de.uni_freiburg.informatik.ultimate.lib.smtlibutils.quantifier.QuantifierPusher=ERROR; [2023-11-06 23:09:09,980 INFO L151 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2023-11-06 23:09:09,985 INFO L153 SettingsManager]: * Create parallel compositions if possible=false [2023-11-06 23:09:09,986 INFO L153 SettingsManager]: * Use SBE=true [2023-11-06 23:09:09,987 INFO L151 SettingsManager]: Preferences of BuchiAutomizer differ from their defaults: [2023-11-06 23:09:09,987 INFO L153 SettingsManager]: * NCSB implementation=INTSET_LAZY3 [2023-11-06 23:09:09,989 INFO L153 SettingsManager]: * Use old map elimination=false [2023-11-06 23:09:09,990 INFO L153 SettingsManager]: * Use external solver (rank synthesis)=false [2023-11-06 23:09:09,990 INFO L153 SettingsManager]: * Use only trivial implications for array writes=true [2023-11-06 23:09:09,990 INFO L153 SettingsManager]: * Rank analysis=LINEAR_WITH_GUESSES [2023-11-06 23:09:09,991 INFO L151 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2023-11-06 23:09:09,992 INFO L153 SettingsManager]: * Pointer base address is valid at dereference=ASSUME [2023-11-06 23:09:09,992 INFO L153 SettingsManager]: * sizeof long=4 [2023-11-06 23:09:09,993 INFO L153 SettingsManager]: * Overapproximate operations on floating types=true [2023-11-06 23:09:09,993 INFO L153 SettingsManager]: * sizeof POINTER=4 [2023-11-06 23:09:09,994 INFO L153 SettingsManager]: * Check division by zero=IGNORE [2023-11-06 23:09:09,994 INFO L153 SettingsManager]: * Pointer to allocated memory at dereference=ASSUME [2023-11-06 23:09:09,994 INFO L153 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=ASSUME [2023-11-06 23:09:09,995 INFO L153 SettingsManager]: * Check array bounds for arrays that are off heap=ASSUME [2023-11-06 23:09:09,995 INFO L153 SettingsManager]: * Check unreachability of reach_error function=false [2023-11-06 23:09:09,995 INFO L153 SettingsManager]: * sizeof long double=12 [2023-11-06 23:09:09,996 INFO L153 SettingsManager]: * Check if freed pointer was valid=false [2023-11-06 23:09:09,996 INFO L153 SettingsManager]: * Assume nondeterminstic values are in range=false [2023-11-06 23:09:09,998 INFO L153 SettingsManager]: * Use constant arrays=true [2023-11-06 23:09:09,998 INFO L151 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2023-11-06 23:09:09,998 INFO L153 SettingsManager]: * Size of a code block=SequenceOfStatements [2023-11-06 23:09:09,998 INFO L151 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2023-11-06 23:09:09,999 INFO L153 SettingsManager]: * Trace refinement strategy=CAMEL [2023-11-06 23:09:09,999 INFO L151 SettingsManager]: Preferences of IcfgTransformer differ from their defaults: [2023-11-06 23:09:10,000 INFO L153 SettingsManager]: * TransformationType=MODULO_NEIGHBOR WARNING: An illegal reflective access operation has occurred WARNING: Illegal reflective access by com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 (file:/tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_69caa52f-ede6-4d44-b7cb-879a059aaf8c/bin/uautomizer-verify-WvqO1wxjHP/plugins/com.sun.xml.bind_2.2.0.v201505121915.jar) to method java.lang.ClassLoader.defineClass(java.lang.String,byte[],int,int) WARNING: Please consider reporting this to the maintainers of com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 WARNING: Use --illegal-access=warn to enable warnings of further illegal reflective access operations WARNING: All illegal access operations will be denied in a future release Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_69caa52f-ede6-4d44-b7cb-879a059aaf8c/bin/uautomizer-verify-WvqO1wxjHP Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness.graphml Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(F end) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 32bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> 2cbfaf31aa56f767af01fea9a12ccb47d60ab19076d72b85e8ca46d6ff778e4c [2023-11-06 23:09:10,300 INFO L75 nceAwareModelManager]: Repository-Root is: /tmp [2023-11-06 23:09:10,330 INFO L261 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2023-11-06 23:09:10,334 INFO L217 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2023-11-06 23:09:10,335 INFO L270 PluginConnector]: Initializing CDTParser... [2023-11-06 23:09:10,336 INFO L274 PluginConnector]: CDTParser initialized [2023-11-06 23:09:10,337 INFO L431 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_69caa52f-ede6-4d44-b7cb-879a059aaf8c/bin/uautomizer-verify-WvqO1wxjHP/../../sv-benchmarks/c/systemc/transmitter.02.cil.c [2023-11-06 23:09:13,466 INFO L533 CDTParser]: Created temporary CDT project at NULL [2023-11-06 23:09:13,650 INFO L384 CDTParser]: Found 1 translation units. [2023-11-06 23:09:13,650 INFO L180 CDTParser]: Scanning /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_69caa52f-ede6-4d44-b7cb-879a059aaf8c/sv-benchmarks/c/systemc/transmitter.02.cil.c [2023-11-06 23:09:13,661 INFO L427 CDTParser]: About to delete temporary CDT project at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_69caa52f-ede6-4d44-b7cb-879a059aaf8c/bin/uautomizer-verify-WvqO1wxjHP/data/b8a2df54d/e3d752ef585f4e9b9f221c467138ace7/FLAG021943ef5 [2023-11-06 23:09:13,676 INFO L435 CDTParser]: Successfully deleted /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_69caa52f-ede6-4d44-b7cb-879a059aaf8c/bin/uautomizer-verify-WvqO1wxjHP/data/b8a2df54d/e3d752ef585f4e9b9f221c467138ace7 [2023-11-06 23:09:13,679 INFO L299 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2023-11-06 23:09:13,681 INFO L133 ToolchainWalker]: Walking toolchain with 6 elements. [2023-11-06 23:09:13,682 INFO L112 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2023-11-06 23:09:13,682 INFO L270 PluginConnector]: Initializing CACSL2BoogieTranslator... [2023-11-06 23:09:13,688 INFO L274 PluginConnector]: CACSL2BoogieTranslator initialized [2023-11-06 23:09:13,688 INFO L184 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 06.11 11:09:13" (1/1) ... [2023-11-06 23:09:13,690 INFO L204 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@20a7d732 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.11 11:09:13, skipping insertion in model container [2023-11-06 23:09:13,690 INFO L184 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 06.11 11:09:13" (1/1) ... [2023-11-06 23:09:13,726 INFO L177 MainTranslator]: Built tables and reachable declarations [2023-11-06 23:09:13,941 INFO L209 PostProcessor]: Analyzing one entry point: main [2023-11-06 23:09:13,954 INFO L202 MainTranslator]: Completed pre-run [2023-11-06 23:09:13,993 INFO L209 PostProcessor]: Analyzing one entry point: main [2023-11-06 23:09:14,011 INFO L206 MainTranslator]: Completed translation [2023-11-06 23:09:14,012 INFO L201 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.11 11:09:14 WrapperNode [2023-11-06 23:09:14,012 INFO L131 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2023-11-06 23:09:14,013 INFO L112 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2023-11-06 23:09:14,013 INFO L270 PluginConnector]: Initializing Boogie Procedure Inliner... [2023-11-06 23:09:14,013 INFO L274 PluginConnector]: Boogie Procedure Inliner initialized [2023-11-06 23:09:14,021 INFO L184 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.11 11:09:14" (1/1) ... [2023-11-06 23:09:14,030 INFO L184 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.11 11:09:14" (1/1) ... [2023-11-06 23:09:14,067 INFO L138 Inliner]: procedures = 32, calls = 37, calls flagged for inlining = 32, calls inlined = 45, statements flattened = 536 [2023-11-06 23:09:14,067 INFO L131 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2023-11-06 23:09:14,068 INFO L112 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2023-11-06 23:09:14,068 INFO L270 PluginConnector]: Initializing Boogie Preprocessor... [2023-11-06 23:09:14,068 INFO L274 PluginConnector]: Boogie Preprocessor initialized [2023-11-06 23:09:14,077 INFO L184 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.11 11:09:14" (1/1) ... [2023-11-06 23:09:14,077 INFO L184 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.11 11:09:14" (1/1) ... [2023-11-06 23:09:14,082 INFO L184 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.11 11:09:14" (1/1) ... [2023-11-06 23:09:14,083 INFO L184 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.11 11:09:14" (1/1) ... [2023-11-06 23:09:14,093 INFO L184 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.11 11:09:14" (1/1) ... [2023-11-06 23:09:14,102 INFO L184 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.11 11:09:14" (1/1) ... [2023-11-06 23:09:14,105 INFO L184 PluginConnector]: Executing the observer LTLStepAnnotator from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.11 11:09:14" (1/1) ... [2023-11-06 23:09:14,107 INFO L184 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.11 11:09:14" (1/1) ... [2023-11-06 23:09:14,113 INFO L131 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2023-11-06 23:09:14,114 INFO L112 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2023-11-06 23:09:14,114 INFO L270 PluginConnector]: Initializing RCFGBuilder... [2023-11-06 23:09:14,115 INFO L274 PluginConnector]: RCFGBuilder initialized [2023-11-06 23:09:14,116 INFO L184 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.11 11:09:14" (1/1) ... [2023-11-06 23:09:14,122 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2023-11-06 23:09:14,138 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_69caa52f-ede6-4d44-b7cb-879a059aaf8c/bin/uautomizer-verify-WvqO1wxjHP/z3 [2023-11-06 23:09:14,165 INFO L229 MonitoredProcess]: Starting monitored process 1 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_69caa52f-ede6-4d44-b7cb-879a059aaf8c/bin/uautomizer-verify-WvqO1wxjHP/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2023-11-06 23:09:14,201 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_69caa52f-ede6-4d44-b7cb-879a059aaf8c/bin/uautomizer-verify-WvqO1wxjHP/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (1)] Waiting until timeout for monitored process [2023-11-06 23:09:14,221 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocInit [2023-11-06 23:09:14,221 INFO L130 BoogieDeclarations]: Found specification of procedure write~init~int [2023-11-06 23:09:14,222 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2023-11-06 23:09:14,222 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2023-11-06 23:09:14,305 INFO L236 CfgBuilder]: Building ICFG [2023-11-06 23:09:14,307 INFO L262 CfgBuilder]: Building CFG for each procedure with an implementation [2023-11-06 23:09:15,001 INFO L277 CfgBuilder]: Performing block encoding [2023-11-06 23:09:15,010 INFO L297 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2023-11-06 23:09:15,011 INFO L302 CfgBuilder]: Removed 6 assume(true) statements. [2023-11-06 23:09:15,013 INFO L201 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 06.11 11:09:15 BoogieIcfgContainer [2023-11-06 23:09:15,013 INFO L131 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2023-11-06 23:09:15,014 INFO L112 PluginConnector]: ------------------------BuchiAutomizer---------------------------- [2023-11-06 23:09:15,015 INFO L270 PluginConnector]: Initializing BuchiAutomizer... [2023-11-06 23:09:15,018 INFO L274 PluginConnector]: BuchiAutomizer initialized [2023-11-06 23:09:15,028 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2023-11-06 23:09:15,028 INFO L184 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "CDTParser AST 06.11 11:09:13" (1/3) ... [2023-11-06 23:09:15,029 INFO L204 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@7568bb6a and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 06.11 11:09:15, skipping insertion in model container [2023-11-06 23:09:15,029 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2023-11-06 23:09:15,030 INFO L184 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.11 11:09:14" (2/3) ... [2023-11-06 23:09:15,030 INFO L204 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@7568bb6a and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 06.11 11:09:15, skipping insertion in model container [2023-11-06 23:09:15,030 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2023-11-06 23:09:15,030 INFO L184 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 06.11 11:09:15" (3/3) ... [2023-11-06 23:09:15,032 INFO L332 chiAutomizerObserver]: Analyzing ICFG transmitter.02.cil.c [2023-11-06 23:09:15,095 INFO L303 stractBuchiCegarLoop]: Interprodecural is true [2023-11-06 23:09:15,095 INFO L304 stractBuchiCegarLoop]: Hoare is false [2023-11-06 23:09:15,095 INFO L305 stractBuchiCegarLoop]: Compute interpolants for ForwardPredicates [2023-11-06 23:09:15,095 INFO L306 stractBuchiCegarLoop]: Backedges is STRAIGHT_LINE [2023-11-06 23:09:15,095 INFO L307 stractBuchiCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2023-11-06 23:09:15,095 INFO L308 stractBuchiCegarLoop]: Difference is false [2023-11-06 23:09:15,095 INFO L309 stractBuchiCegarLoop]: Minimize is MINIMIZE_SEVPA [2023-11-06 23:09:15,096 INFO L313 stractBuchiCegarLoop]: ======== Iteration 0 == of CEGAR loop == BuchiAutomatonCegarLoop ======== [2023-11-06 23:09:15,100 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 209 states, 208 states have (on average 1.5288461538461537) internal successors, (318), 208 states have internal predecessors, (318), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-06 23:09:15,132 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 164 [2023-11-06 23:09:15,132 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-06 23:09:15,132 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-06 23:09:15,144 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-06 23:09:15,144 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-06 23:09:15,145 INFO L335 stractBuchiCegarLoop]: ======== Iteration 1 ============ [2023-11-06 23:09:15,149 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 209 states, 208 states have (on average 1.5288461538461537) internal successors, (318), 208 states have internal predecessors, (318), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-06 23:09:15,165 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 164 [2023-11-06 23:09:15,166 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-06 23:09:15,166 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-06 23:09:15,172 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-06 23:09:15,172 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-06 23:09:15,180 INFO L748 eck$LassoCheckResult]: Stem: 147#$Ultimate##0true assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2; 158#L-1true assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~4#1;havoc main_~__retres1~4#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1; 205#init_model_returnLabel#1true assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret12#1, start_simulation_#t~ret13#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 155#update_channels_returnLabel#1true assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 182#L221true assume !(1 == ~m_i~0);~m_st~0 := 2; 60#L221-2true assume 1 == ~t1_i~0;~t1_st~0 := 0; 42#L226-1true assume !(1 == ~t2_i~0);~t2_st~0 := 2; 162#L231-1true assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 33#L334true assume !(0 == ~M_E~0); 169#L334-2true assume !(0 == ~T1_E~0); 113#L339-1true assume !(0 == ~T2_E~0); 108#L344-1true assume 0 == ~E_1~0;~E_1~0 := 1; 143#L349-1true assume !(0 == ~E_2~0); 41#L354-1true assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret8#1, activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 117#L156true assume !(1 == ~m_pc~0); 154#L156-2true is_master_triggered_~__retres1~0#1 := 0; 136#L167true is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 128#is_master_triggered_returnLabel#1true activate_threads_#t~ret8#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 78#L405true assume !(0 != activate_threads_~tmp~1#1); 63#L405-2true assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 126#L175true assume 1 == ~t1_pc~0; 161#L176true assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 64#L186true is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 39#is_transmit1_triggered_returnLabel#1true activate_threads_#t~ret9#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 115#L413true assume !(0 != activate_threads_~tmp___0~0#1); 185#L413-2true assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 187#L194true assume !(1 == ~t2_pc~0); 203#L194-2true is_transmit2_triggered_~__retres1~2#1 := 0; 70#L205true is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 209#is_transmit2_triggered_returnLabel#1true activate_threads_#t~ret10#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 27#L421true assume !(0 != activate_threads_~tmp___1~0#1); 85#L421-2true havoc activate_threads_#t~ret8#1, activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 12#L367true assume !(1 == ~M_E~0); 186#L367-2true assume !(1 == ~T1_E~0); 130#L372-1true assume 1 == ~T2_E~0;~T2_E~0 := 2; 132#L377-1true assume !(1 == ~E_1~0); 25#L382-1true assume !(1 == ~E_2~0); 80#L387-1true assume { :end_inline_reset_delta_events } true; 107#L528-2true [2023-11-06 23:09:15,182 INFO L750 eck$LassoCheckResult]: Loop: 107#L528-2true assume !false; 88#L529true start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 17#L309-1true assume false; 82#eval_returnLabel#1true havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 112#update_channels_returnLabel#2true assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 207#L334-3true assume 0 == ~M_E~0;~M_E~0 := 1; 159#L334-5true assume 0 == ~T1_E~0;~T1_E~0 := 1; 116#L339-3true assume 0 == ~T2_E~0;~T2_E~0 := 1; 183#L344-3true assume 0 == ~E_1~0;~E_1~0 := 1; 76#L349-3true assume !(0 == ~E_2~0); 32#L354-3true assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret8#1, activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 101#L156-9true assume !(1 == ~m_pc~0); 4#L156-11true is_master_triggered_~__retres1~0#1 := 0; 57#L167-3true is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 135#is_master_triggered_returnLabel#4true activate_threads_#t~ret8#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 118#L405-9true assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 21#L405-11true assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 192#L175-9true assume !(1 == ~t1_pc~0); 141#L175-11true is_transmit1_triggered_~__retres1~1#1 := 0; 14#L186-3true is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 201#is_transmit1_triggered_returnLabel#4true activate_threads_#t~ret9#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 153#L413-9true assume !(0 != activate_threads_~tmp___0~0#1); 146#L413-11true assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 190#L194-9true assume !(1 == ~t2_pc~0); 28#L194-11true is_transmit2_triggered_~__retres1~2#1 := 0; 196#L205-3true is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 5#is_transmit2_triggered_returnLabel#4true activate_threads_#t~ret10#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 110#L421-9true assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 144#L421-11true havoc activate_threads_#t~ret8#1, activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 54#L367-3true assume 1 == ~M_E~0;~M_E~0 := 2; 7#L367-5true assume 1 == ~T1_E~0;~T1_E~0 := 2; 34#L372-3true assume 1 == ~T2_E~0;~T2_E~0 := 2; 18#L377-3true assume !(1 == ~E_1~0); 30#L382-3true assume 1 == ~E_2~0;~E_2~0 := 2; 111#L387-3true assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 145#L244-1true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 180#L261-1true exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 188#exists_runnable_thread_returnLabel#2true start_simulation_#t~ret12#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret12#1;havoc start_simulation_#t~ret12#1; 152#L547true assume !(0 == start_simulation_~tmp~3#1); 166#L547-2true assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret11#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 149#L244-2true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 52#L261-2true exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 37#exists_runnable_thread_returnLabel#3true stop_simulation_#t~ret11#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret11#1;havoc stop_simulation_#t~ret11#1; 40#L502true assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 49#L509true stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 122#stop_simulation_returnLabel#1true start_simulation_#t~ret13#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret11#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret13#1;havoc start_simulation_#t~ret13#1; 20#L560true assume !(0 != start_simulation_~tmp___0~1#1); 107#L528-2true [2023-11-06 23:09:15,188 INFO L145 PredicateUnifier]: Initialized classic predicate unifier [2023-11-06 23:09:15,188 INFO L85 PathProgramCache]: Analyzing trace with hash -886407522, now seen corresponding path program 1 times [2023-11-06 23:09:15,199 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-06 23:09:15,199 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1349879317] [2023-11-06 23:09:15,200 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-06 23:09:15,200 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-06 23:09:15,320 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-06 23:09:15,455 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-06 23:09:15,455 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-06 23:09:15,456 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1349879317] [2023-11-06 23:09:15,457 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1349879317] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-06 23:09:15,457 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-06 23:09:15,457 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-06 23:09:15,459 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1288905845] [2023-11-06 23:09:15,459 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-06 23:09:15,465 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-06 23:09:15,466 INFO L145 PredicateUnifier]: Initialized classic predicate unifier [2023-11-06 23:09:15,466 INFO L85 PathProgramCache]: Analyzing trace with hash -294698413, now seen corresponding path program 1 times [2023-11-06 23:09:15,467 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-06 23:09:15,467 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1154462988] [2023-11-06 23:09:15,467 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-06 23:09:15,467 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-06 23:09:15,492 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-06 23:09:15,533 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-06 23:09:15,539 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-06 23:09:15,540 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1154462988] [2023-11-06 23:09:15,540 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1154462988] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-06 23:09:15,540 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-06 23:09:15,541 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2023-11-06 23:09:15,541 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1266162797] [2023-11-06 23:09:15,541 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-06 23:09:15,542 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-06 23:09:15,545 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-06 23:09:15,584 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-06 23:09:15,585 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-06 23:09:15,587 INFO L87 Difference]: Start difference. First operand has 209 states, 208 states have (on average 1.5288461538461537) internal successors, (318), 208 states have internal predecessors, (318), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand has 3 states, 3 states have (on average 12.666666666666666) internal successors, (38), 3 states have internal predecessors, (38), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-06 23:09:15,639 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-06 23:09:15,639 INFO L93 Difference]: Finished difference Result 207 states and 302 transitions. [2023-11-06 23:09:15,641 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 207 states and 302 transitions. [2023-11-06 23:09:15,646 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 160 [2023-11-06 23:09:15,661 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 207 states to 201 states and 296 transitions. [2023-11-06 23:09:15,663 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 201 [2023-11-06 23:09:15,663 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 201 [2023-11-06 23:09:15,664 INFO L73 IsDeterministic]: Start isDeterministic. Operand 201 states and 296 transitions. [2023-11-06 23:09:15,665 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-06 23:09:15,665 INFO L218 hiAutomatonCegarLoop]: Abstraction has 201 states and 296 transitions. [2023-11-06 23:09:15,682 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 201 states and 296 transitions. [2023-11-06 23:09:15,704 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 201 to 201. [2023-11-06 23:09:15,706 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 201 states, 201 states have (on average 1.472636815920398) internal successors, (296), 200 states have internal predecessors, (296), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-06 23:09:15,707 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 201 states to 201 states and 296 transitions. [2023-11-06 23:09:15,708 INFO L240 hiAutomatonCegarLoop]: Abstraction has 201 states and 296 transitions. [2023-11-06 23:09:15,709 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-06 23:09:15,714 INFO L428 stractBuchiCegarLoop]: Abstraction has 201 states and 296 transitions. [2023-11-06 23:09:15,715 INFO L335 stractBuchiCegarLoop]: ======== Iteration 2 ============ [2023-11-06 23:09:15,715 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 201 states and 296 transitions. [2023-11-06 23:09:15,725 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 160 [2023-11-06 23:09:15,725 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-06 23:09:15,725 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-06 23:09:15,729 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-06 23:09:15,729 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-06 23:09:15,729 INFO L748 eck$LassoCheckResult]: Stem: 608#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2; 609#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~4#1;havoc main_~__retres1~4#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1; 617#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret12#1, start_simulation_#t~ret13#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 615#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 616#L221 assume 1 == ~m_i~0;~m_st~0 := 0; 530#L221-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 505#L226-1 assume !(1 == ~t2_i~0);~t2_st~0 := 2; 506#L231-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 489#L334 assume !(0 == ~M_E~0); 490#L334-2 assume !(0 == ~T1_E~0); 585#L339-1 assume !(0 == ~T2_E~0); 579#L344-1 assume 0 == ~E_1~0;~E_1~0 := 1; 580#L349-1 assume !(0 == ~E_2~0); 503#L354-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret8#1, activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 504#L156 assume !(1 == ~m_pc~0); 436#L156-2 is_master_triggered_~__retres1~0#1 := 0; 435#L167 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 597#is_master_triggered_returnLabel#1 activate_threads_#t~ret8#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 552#L405 assume !(0 != activate_threads_~tmp~1#1); 534#L405-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 535#L175 assume 1 == ~t1_pc~0; 594#L176 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 536#L186 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 500#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret9#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 501#L413 assume !(0 != activate_threads_~tmp___0~0#1); 587#L413-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 624#L194 assume !(1 == ~t2_pc~0); 578#L194-2 is_transmit2_triggered_~__retres1~2#1 := 0; 546#L205 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 547#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret10#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 478#L421 assume !(0 != activate_threads_~tmp___1~0#1); 479#L421-2 havoc activate_threads_#t~ret8#1, activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 448#L367 assume !(1 == ~M_E~0); 449#L367-2 assume !(1 == ~T1_E~0); 598#L372-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 599#L377-1 assume !(1 == ~E_1~0); 475#L382-1 assume !(1 == ~E_2~0); 476#L387-1 assume { :end_inline_reset_delta_events } true; 465#L528-2 [2023-11-06 23:09:15,730 INFO L750 eck$LassoCheckResult]: Loop: 465#L528-2 assume !false; 559#L529 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 458#L309-1 assume !false; 459#L272 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 439#L244 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 440#L261 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 447#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 425#L276 assume !(0 != eval_~tmp~0#1); 427#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 555#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 584#L334-3 assume 0 == ~M_E~0;~M_E~0 := 1; 618#L334-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 588#L339-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 589#L344-3 assume 0 == ~E_1~0;~E_1~0 := 1; 551#L349-3 assume !(0 == ~E_2~0); 487#L354-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret8#1, activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 488#L156-9 assume 1 == ~m_pc~0; 573#L157-3 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 431#L167-3 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 527#is_master_triggered_returnLabel#4 activate_threads_#t~ret8#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 590#L405-9 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 466#L405-11 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 467#L175-9 assume 1 == ~t1_pc~0; 512#L176-3 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 452#L186-3 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 453#is_transmit1_triggered_returnLabel#4 activate_threads_#t~ret9#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 614#L413-9 assume !(0 != activate_threads_~tmp___0~0#1); 606#L413-11 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 607#L194-9 assume !(1 == ~t2_pc~0); 480#L194-11 is_transmit2_triggered_~__retres1~2#1 := 0; 481#L205-3 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 432#is_transmit2_triggered_returnLabel#4 activate_threads_#t~ret10#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 433#L421-9 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 582#L421-11 havoc activate_threads_#t~ret8#1, activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 523#L367-3 assume 1 == ~M_E~0;~M_E~0 := 2; 437#L367-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 438#L372-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 460#L377-3 assume !(1 == ~E_1~0); 461#L382-3 assume 1 == ~E_2~0;~E_2~0 := 2; 484#L387-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 583#L244-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 492#L261-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 623#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret12#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret12#1;havoc start_simulation_#t~ret12#1; 613#L547 assume !(0 == start_simulation_~tmp~3#1); 600#L547-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret11#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 610#L244-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 521#L261-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 495#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret11#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret11#1;havoc stop_simulation_#t~ret11#1; 496#L502 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 502#L509 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 517#stop_simulation_returnLabel#1 start_simulation_#t~ret13#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret11#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret13#1;havoc start_simulation_#t~ret13#1; 464#L560 assume !(0 != start_simulation_~tmp___0~1#1); 465#L528-2 [2023-11-06 23:09:15,732 INFO L145 PredicateUnifier]: Initialized classic predicate unifier [2023-11-06 23:09:15,732 INFO L85 PathProgramCache]: Analyzing trace with hash 1357575776, now seen corresponding path program 1 times [2023-11-06 23:09:15,733 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-06 23:09:15,734 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1476495764] [2023-11-06 23:09:15,734 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-06 23:09:15,734 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-06 23:09:15,756 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-06 23:09:15,827 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-06 23:09:15,827 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-06 23:09:15,827 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1476495764] [2023-11-06 23:09:15,827 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1476495764] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-06 23:09:15,827 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-06 23:09:15,828 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-06 23:09:15,828 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1557117266] [2023-11-06 23:09:15,828 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-06 23:09:15,828 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-06 23:09:15,829 INFO L145 PredicateUnifier]: Initialized classic predicate unifier [2023-11-06 23:09:15,829 INFO L85 PathProgramCache]: Analyzing trace with hash -724130786, now seen corresponding path program 1 times [2023-11-06 23:09:15,829 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-06 23:09:15,830 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2065790556] [2023-11-06 23:09:15,830 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-06 23:09:15,831 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-06 23:09:15,867 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-06 23:09:15,920 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-06 23:09:15,921 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-06 23:09:15,921 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2065790556] [2023-11-06 23:09:15,921 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2065790556] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-06 23:09:15,922 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-06 23:09:15,922 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-06 23:09:15,922 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [908012731] [2023-11-06 23:09:15,922 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-06 23:09:15,923 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-06 23:09:15,923 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-06 23:09:15,923 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-06 23:09:15,924 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-06 23:09:15,924 INFO L87 Difference]: Start difference. First operand 201 states and 296 transitions. cyclomatic complexity: 96 Second operand has 3 states, 3 states have (on average 12.666666666666666) internal successors, (38), 3 states have internal predecessors, (38), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-06 23:09:15,943 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-06 23:09:15,943 INFO L93 Difference]: Finished difference Result 201 states and 295 transitions. [2023-11-06 23:09:15,943 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 201 states and 295 transitions. [2023-11-06 23:09:15,946 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 160 [2023-11-06 23:09:15,949 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 201 states to 201 states and 295 transitions. [2023-11-06 23:09:15,949 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 201 [2023-11-06 23:09:15,950 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 201 [2023-11-06 23:09:15,950 INFO L73 IsDeterministic]: Start isDeterministic. Operand 201 states and 295 transitions. [2023-11-06 23:09:15,951 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-06 23:09:15,952 INFO L218 hiAutomatonCegarLoop]: Abstraction has 201 states and 295 transitions. [2023-11-06 23:09:15,952 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 201 states and 295 transitions. [2023-11-06 23:09:15,962 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 201 to 201. [2023-11-06 23:09:15,962 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 201 states, 201 states have (on average 1.4676616915422886) internal successors, (295), 200 states have internal predecessors, (295), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-06 23:09:15,964 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 201 states to 201 states and 295 transitions. [2023-11-06 23:09:15,964 INFO L240 hiAutomatonCegarLoop]: Abstraction has 201 states and 295 transitions. [2023-11-06 23:09:15,965 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-06 23:09:15,966 INFO L428 stractBuchiCegarLoop]: Abstraction has 201 states and 295 transitions. [2023-11-06 23:09:15,966 INFO L335 stractBuchiCegarLoop]: ======== Iteration 3 ============ [2023-11-06 23:09:15,966 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 201 states and 295 transitions. [2023-11-06 23:09:15,968 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 160 [2023-11-06 23:09:15,968 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-06 23:09:15,968 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-06 23:09:15,970 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-06 23:09:15,970 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-06 23:09:15,971 INFO L748 eck$LassoCheckResult]: Stem: 1017#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2; 1018#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~4#1;havoc main_~__retres1~4#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1; 1026#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret12#1, start_simulation_#t~ret13#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 1024#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 1025#L221 assume 1 == ~m_i~0;~m_st~0 := 0; 939#L221-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 914#L226-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 915#L231-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 898#L334 assume !(0 == ~M_E~0); 899#L334-2 assume !(0 == ~T1_E~0); 994#L339-1 assume !(0 == ~T2_E~0); 988#L344-1 assume 0 == ~E_1~0;~E_1~0 := 1; 989#L349-1 assume !(0 == ~E_2~0); 912#L354-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret8#1, activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 913#L156 assume !(1 == ~m_pc~0); 845#L156-2 is_master_triggered_~__retres1~0#1 := 0; 844#L167 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1006#is_master_triggered_returnLabel#1 activate_threads_#t~ret8#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 961#L405 assume !(0 != activate_threads_~tmp~1#1); 943#L405-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 944#L175 assume 1 == ~t1_pc~0; 1003#L176 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 945#L186 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 909#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret9#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 910#L413 assume !(0 != activate_threads_~tmp___0~0#1); 996#L413-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1033#L194 assume !(1 == ~t2_pc~0); 987#L194-2 is_transmit2_triggered_~__retres1~2#1 := 0; 955#L205 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 956#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret10#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 887#L421 assume !(0 != activate_threads_~tmp___1~0#1); 888#L421-2 havoc activate_threads_#t~ret8#1, activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 857#L367 assume !(1 == ~M_E~0); 858#L367-2 assume !(1 == ~T1_E~0); 1007#L372-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 1008#L377-1 assume !(1 == ~E_1~0); 884#L382-1 assume !(1 == ~E_2~0); 885#L387-1 assume { :end_inline_reset_delta_events } true; 874#L528-2 [2023-11-06 23:09:15,971 INFO L750 eck$LassoCheckResult]: Loop: 874#L528-2 assume !false; 968#L529 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 867#L309-1 assume !false; 868#L272 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 848#L244 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 849#L261 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 856#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 834#L276 assume !(0 != eval_~tmp~0#1); 836#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 964#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 993#L334-3 assume 0 == ~M_E~0;~M_E~0 := 1; 1027#L334-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 997#L339-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 998#L344-3 assume 0 == ~E_1~0;~E_1~0 := 1; 960#L349-3 assume !(0 == ~E_2~0); 896#L354-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret8#1, activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 897#L156-9 assume 1 == ~m_pc~0; 982#L157-3 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 840#L167-3 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 936#is_master_triggered_returnLabel#4 activate_threads_#t~ret8#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 999#L405-9 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 875#L405-11 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 876#L175-9 assume 1 == ~t1_pc~0; 921#L176-3 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 861#L186-3 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 862#is_transmit1_triggered_returnLabel#4 activate_threads_#t~ret9#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 1023#L413-9 assume !(0 != activate_threads_~tmp___0~0#1); 1015#L413-11 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1016#L194-9 assume 1 == ~t2_pc~0; 963#L195-3 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 890#L205-3 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 841#is_transmit2_triggered_returnLabel#4 activate_threads_#t~ret10#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 842#L421-9 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 991#L421-11 havoc activate_threads_#t~ret8#1, activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 932#L367-3 assume 1 == ~M_E~0;~M_E~0 := 2; 846#L367-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 847#L372-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 869#L377-3 assume !(1 == ~E_1~0); 870#L382-3 assume 1 == ~E_2~0;~E_2~0 := 2; 893#L387-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 992#L244-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 901#L261-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 1032#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret12#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret12#1;havoc start_simulation_#t~ret12#1; 1022#L547 assume !(0 == start_simulation_~tmp~3#1); 1009#L547-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret11#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 1019#L244-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 930#L261-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 904#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret11#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret11#1;havoc stop_simulation_#t~ret11#1; 905#L502 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 911#L509 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 926#stop_simulation_returnLabel#1 start_simulation_#t~ret13#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret11#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret13#1;havoc start_simulation_#t~ret13#1; 873#L560 assume !(0 != start_simulation_~tmp___0~1#1); 874#L528-2 [2023-11-06 23:09:15,972 INFO L145 PredicateUnifier]: Initialized classic predicate unifier [2023-11-06 23:09:15,972 INFO L85 PathProgramCache]: Analyzing trace with hash 1082816162, now seen corresponding path program 1 times [2023-11-06 23:09:15,972 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-06 23:09:15,973 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1703806638] [2023-11-06 23:09:15,973 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-06 23:09:15,973 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-06 23:09:15,986 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-06 23:09:16,077 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-06 23:09:16,077 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-06 23:09:16,078 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1703806638] [2023-11-06 23:09:16,078 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1703806638] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-06 23:09:16,078 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-06 23:09:16,078 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-06 23:09:16,079 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1739742994] [2023-11-06 23:09:16,079 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-06 23:09:16,079 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-06 23:09:16,080 INFO L145 PredicateUnifier]: Initialized classic predicate unifier [2023-11-06 23:09:16,080 INFO L85 PathProgramCache]: Analyzing trace with hash 866264191, now seen corresponding path program 1 times [2023-11-06 23:09:16,080 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-06 23:09:16,080 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [930081294] [2023-11-06 23:09:16,081 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-06 23:09:16,081 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-06 23:09:16,093 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-06 23:09:16,126 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-06 23:09:16,126 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-06 23:09:16,126 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [930081294] [2023-11-06 23:09:16,127 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [930081294] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-06 23:09:16,127 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-06 23:09:16,127 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-06 23:09:16,127 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1945125408] [2023-11-06 23:09:16,128 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-06 23:09:16,128 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-06 23:09:16,128 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-06 23:09:16,129 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2023-11-06 23:09:16,129 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2023-11-06 23:09:16,129 INFO L87 Difference]: Start difference. First operand 201 states and 295 transitions. cyclomatic complexity: 95 Second operand has 4 states, 4 states have (on average 9.5) internal successors, (38), 3 states have internal predecessors, (38), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-06 23:09:16,239 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-06 23:09:16,239 INFO L93 Difference]: Finished difference Result 342 states and 498 transitions. [2023-11-06 23:09:16,239 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 342 states and 498 transitions. [2023-11-06 23:09:16,243 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 296 [2023-11-06 23:09:16,246 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 342 states to 342 states and 498 transitions. [2023-11-06 23:09:16,247 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 342 [2023-11-06 23:09:16,248 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 342 [2023-11-06 23:09:16,248 INFO L73 IsDeterministic]: Start isDeterministic. Operand 342 states and 498 transitions. [2023-11-06 23:09:16,250 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-06 23:09:16,250 INFO L218 hiAutomatonCegarLoop]: Abstraction has 342 states and 498 transitions. [2023-11-06 23:09:16,251 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 342 states and 498 transitions. [2023-11-06 23:09:16,268 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 342 to 340. [2023-11-06 23:09:16,269 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 340 states, 340 states have (on average 1.4588235294117646) internal successors, (496), 339 states have internal predecessors, (496), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-06 23:09:16,271 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 340 states to 340 states and 496 transitions. [2023-11-06 23:09:16,271 INFO L240 hiAutomatonCegarLoop]: Abstraction has 340 states and 496 transitions. [2023-11-06 23:09:16,272 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2023-11-06 23:09:16,272 INFO L428 stractBuchiCegarLoop]: Abstraction has 340 states and 496 transitions. [2023-11-06 23:09:16,273 INFO L335 stractBuchiCegarLoop]: ======== Iteration 4 ============ [2023-11-06 23:09:16,273 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 340 states and 496 transitions. [2023-11-06 23:09:16,276 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 296 [2023-11-06 23:09:16,276 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-06 23:09:16,276 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-06 23:09:16,277 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-06 23:09:16,278 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-06 23:09:16,278 INFO L748 eck$LassoCheckResult]: Stem: 1591#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2; 1592#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~4#1;havoc main_~__retres1~4#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1; 1602#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret12#1, start_simulation_#t~ret13#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 1599#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 1600#L221 assume 1 == ~m_i~0;~m_st~0 := 0; 1501#L221-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 1472#L226-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 1473#L231-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 1454#L334 assume !(0 == ~M_E~0); 1455#L334-2 assume !(0 == ~T1_E~0); 1561#L339-1 assume !(0 == ~T2_E~0); 1554#L344-1 assume !(0 == ~E_1~0); 1555#L349-1 assume !(0 == ~E_2~0); 1470#L354-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret8#1, activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1471#L156 assume !(1 == ~m_pc~0); 1398#L156-2 is_master_triggered_~__retres1~0#1 := 0; 1397#L167 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1578#is_master_triggered_returnLabel#1 activate_threads_#t~ret8#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 1525#L405 assume !(0 != activate_threads_~tmp~1#1); 1505#L405-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1506#L175 assume 1 == ~t1_pc~0; 1575#L176 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 1507#L186 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1466#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret9#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 1467#L413 assume !(0 != activate_threads_~tmp___0~0#1); 1563#L413-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1612#L194 assume !(1 == ~t2_pc~0); 1552#L194-2 is_transmit2_triggered_~__retres1~2#1 := 0; 1517#L205 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1518#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret10#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 1442#L421 assume !(0 != activate_threads_~tmp___1~0#1); 1443#L421-2 havoc activate_threads_#t~ret8#1, activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1411#L367 assume !(1 == ~M_E~0); 1412#L367-2 assume !(1 == ~T1_E~0); 1579#L372-1 assume !(1 == ~T2_E~0); 1580#L377-1 assume 1 == ~E_1~0;~E_1~0 := 2; 1439#L382-1 assume !(1 == ~E_2~0); 1440#L387-1 assume { :end_inline_reset_delta_events } true; 1429#L528-2 [2023-11-06 23:09:16,278 INFO L750 eck$LassoCheckResult]: Loop: 1429#L528-2 assume !false; 1553#L529 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 1421#L309-1 assume !false; 1422#L272 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 1401#L244 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 1402#L261 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 1409#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 1410#L276 assume !(0 != eval_~tmp~0#1); 1528#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 1529#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 1619#L334-3 assume 0 == ~M_E~0;~M_E~0 := 1; 1603#L334-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 1604#L339-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 1620#L344-3 assume !(0 == ~E_1~0); 1695#L349-3 assume !(0 == ~E_2~0); 1694#L354-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret8#1, activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1693#L156-9 assume !(1 == ~m_pc~0); 1691#L156-11 is_master_triggered_~__retres1~0#1 := 0; 1690#L167-3 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1689#is_master_triggered_returnLabel#4 activate_threads_#t~ret8#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 1688#L405-9 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 1687#L405-11 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1686#L175-9 assume 1 == ~t1_pc~0; 1481#L176-3 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 1415#L186-3 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1416#is_transmit1_triggered_returnLabel#4 activate_threads_#t~ret9#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 1598#L413-9 assume !(0 != activate_threads_~tmp___0~0#1); 1589#L413-11 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1590#L194-9 assume 1 == ~t2_pc~0; 1613#L195-3 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 1680#L205-3 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1679#is_transmit2_triggered_returnLabel#4 activate_threads_#t~ret10#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 1678#L421-9 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 1677#L421-11 havoc activate_threads_#t~ret8#1, activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1676#L367-3 assume 1 == ~M_E~0;~M_E~0 := 2; 1675#L367-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 1674#L372-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 1456#L377-3 assume !(1 == ~E_1~0); 1425#L382-3 assume 1 == ~E_2~0;~E_2~0 := 2; 1673#L387-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 1672#L244-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 1669#L261-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 1668#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret12#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret12#1;havoc start_simulation_#t~ret12#1; 1666#L547 assume !(0 == start_simulation_~tmp~3#1); 1664#L547-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret11#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 1593#L244-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 1595#L261-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 1461#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret11#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret11#1;havoc stop_simulation_#t~ret11#1; 1462#L502 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 1486#L509 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 1487#stop_simulation_returnLabel#1 start_simulation_#t~ret13#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret11#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret13#1;havoc start_simulation_#t~ret13#1; 1428#L560 assume !(0 != start_simulation_~tmp___0~1#1); 1429#L528-2 [2023-11-06 23:09:16,279 INFO L145 PredicateUnifier]: Initialized classic predicate unifier [2023-11-06 23:09:16,279 INFO L85 PathProgramCache]: Analyzing trace with hash -1288865440, now seen corresponding path program 1 times [2023-11-06 23:09:16,279 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-06 23:09:16,280 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1487941410] [2023-11-06 23:09:16,280 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-06 23:09:16,280 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-06 23:09:16,289 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-06 23:09:16,336 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-06 23:09:16,336 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-06 23:09:16,336 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1487941410] [2023-11-06 23:09:16,337 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1487941410] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-06 23:09:16,337 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-06 23:09:16,337 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-06 23:09:16,337 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [907456281] [2023-11-06 23:09:16,338 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-06 23:09:16,338 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-06 23:09:16,338 INFO L145 PredicateUnifier]: Initialized classic predicate unifier [2023-11-06 23:09:16,339 INFO L85 PathProgramCache]: Analyzing trace with hash 1551047712, now seen corresponding path program 1 times [2023-11-06 23:09:16,339 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-06 23:09:16,339 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [444192741] [2023-11-06 23:09:16,339 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-06 23:09:16,340 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-06 23:09:16,349 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-06 23:09:16,386 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-06 23:09:16,386 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-06 23:09:16,386 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [444192741] [2023-11-06 23:09:16,387 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [444192741] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-06 23:09:16,387 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-06 23:09:16,387 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-06 23:09:16,387 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1843739562] [2023-11-06 23:09:16,388 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-06 23:09:16,388 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-06 23:09:16,388 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-06 23:09:16,388 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2023-11-06 23:09:16,389 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2023-11-06 23:09:16,389 INFO L87 Difference]: Start difference. First operand 340 states and 496 transitions. cyclomatic complexity: 158 Second operand has 4 states, 4 states have (on average 9.5) internal successors, (38), 3 states have internal predecessors, (38), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-06 23:09:16,512 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-06 23:09:16,513 INFO L93 Difference]: Finished difference Result 841 states and 1201 transitions. [2023-11-06 23:09:16,513 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 841 states and 1201 transitions. [2023-11-06 23:09:16,522 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 763 [2023-11-06 23:09:16,530 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 841 states to 841 states and 1201 transitions. [2023-11-06 23:09:16,530 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 841 [2023-11-06 23:09:16,531 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 841 [2023-11-06 23:09:16,531 INFO L73 IsDeterministic]: Start isDeterministic. Operand 841 states and 1201 transitions. [2023-11-06 23:09:16,533 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-06 23:09:16,533 INFO L218 hiAutomatonCegarLoop]: Abstraction has 841 states and 1201 transitions. [2023-11-06 23:09:16,535 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 841 states and 1201 transitions. [2023-11-06 23:09:16,557 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 841 to 780. [2023-11-06 23:09:16,559 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 780 states, 780 states have (on average 1.441025641025641) internal successors, (1124), 779 states have internal predecessors, (1124), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-06 23:09:16,563 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 780 states to 780 states and 1124 transitions. [2023-11-06 23:09:16,563 INFO L240 hiAutomatonCegarLoop]: Abstraction has 780 states and 1124 transitions. [2023-11-06 23:09:16,563 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2023-11-06 23:09:16,564 INFO L428 stractBuchiCegarLoop]: Abstraction has 780 states and 1124 transitions. [2023-11-06 23:09:16,564 INFO L335 stractBuchiCegarLoop]: ======== Iteration 5 ============ [2023-11-06 23:09:16,564 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 780 states and 1124 transitions. [2023-11-06 23:09:16,570 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 733 [2023-11-06 23:09:16,570 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-06 23:09:16,570 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-06 23:09:16,571 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-06 23:09:16,572 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-06 23:09:16,573 INFO L748 eck$LassoCheckResult]: Stem: 2790#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2; 2791#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~4#1;havoc main_~__retres1~4#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1; 2803#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret12#1, start_simulation_#t~ret13#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 2800#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 2801#L221 assume 1 == ~m_i~0;~m_st~0 := 0; 2683#L221-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 2655#L226-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 2656#L231-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 2639#L334 assume !(0 == ~M_E~0); 2640#L334-2 assume !(0 == ~T1_E~0); 2749#L339-1 assume !(0 == ~T2_E~0); 2742#L344-1 assume !(0 == ~E_1~0); 2743#L349-1 assume !(0 == ~E_2~0); 2653#L354-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret8#1, activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 2654#L156 assume !(1 == ~m_pc~0); 2754#L156-2 is_master_triggered_~__retres1~0#1 := 0; 2778#L167 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 2768#is_master_triggered_returnLabel#1 activate_threads_#t~ret8#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 2709#L405 assume !(0 != activate_threads_~tmp~1#1); 2691#L405-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 2692#L175 assume !(1 == ~t1_pc~0); 2696#L175-2 is_transmit1_triggered_~__retres1~1#1 := 0; 2693#L186 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 2650#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret9#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 2651#L413 assume !(0 != activate_threads_~tmp___0~0#1); 2753#L413-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 2822#L194 assume !(1 == ~t2_pc~0); 2740#L194-2 is_transmit2_triggered_~__retres1~2#1 := 0; 2701#L205 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 2702#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret10#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 2628#L421 assume !(0 != activate_threads_~tmp___1~0#1); 2629#L421-2 havoc activate_threads_#t~ret8#1, activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 2600#L367 assume !(1 == ~M_E~0); 2601#L367-2 assume !(1 == ~T1_E~0); 2769#L372-1 assume !(1 == ~T2_E~0); 2770#L377-1 assume 1 == ~E_1~0;~E_1~0 := 2; 2625#L382-1 assume !(1 == ~E_2~0); 2626#L387-1 assume { :end_inline_reset_delta_events } true; 3143#L528-2 [2023-11-06 23:09:16,573 INFO L750 eck$LassoCheckResult]: Loop: 3143#L528-2 assume !false; 2720#L529 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 2706#L309-1 assume !false; 3134#L272 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 2589#L244 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 2590#L261 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 2596#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 2597#L276 assume !(0 != eval_~tmp~0#1); 3130#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 3128#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 3126#L334-3 assume 0 == ~M_E~0;~M_E~0 := 1; 3124#L334-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 3121#L339-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 3122#L344-3 assume !(0 == ~E_1~0); 3115#L349-3 assume !(0 == ~E_2~0); 3116#L354-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret8#1, activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 2734#L156-9 assume !(1 == ~m_pc~0); 2583#L156-11 is_master_triggered_~__retres1~0#1 := 0; 2584#L167-3 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 2679#is_master_triggered_returnLabel#4 activate_threads_#t~ret8#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 2756#L405-9 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 2616#L405-11 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 2617#L175-9 assume !(1 == ~t1_pc~0); 2782#L175-11 is_transmit1_triggered_~__retres1~1#1 := 0; 2602#L186-3 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 2603#is_transmit1_triggered_returnLabel#4 activate_threads_#t~ret9#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 2799#L413-9 assume !(0 != activate_threads_~tmp___0~0#1); 2785#L413-11 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 2786#L194-9 assume !(1 == ~t2_pc~0); 2630#L194-11 is_transmit2_triggered_~__retres1~2#1 := 0; 2631#L205-3 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 2585#is_transmit2_triggered_returnLabel#4 activate_threads_#t~ret10#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 2586#L421-9 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 2745#L421-11 havoc activate_threads_#t~ret8#1, activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 2675#L367-3 assume 1 == ~M_E~0;~M_E~0 := 2; 2587#L367-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 2588#L372-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 2610#L377-3 assume !(1 == ~E_1~0); 2611#L382-3 assume 1 == ~E_2~0;~E_2~0 := 2; 2634#L387-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 2746#L244-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 2642#L261-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 2818#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret12#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret12#1;havoc start_simulation_#t~ret12#1; 2797#L547 assume !(0 == start_simulation_~tmp~3#1); 2773#L547-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret11#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 2792#L244-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 2673#L261-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 2645#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret11#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret11#1;havoc stop_simulation_#t~ret11#1; 2646#L502 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 2652#L509 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 2669#stop_simulation_returnLabel#1 start_simulation_#t~ret13#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret11#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret13#1;havoc start_simulation_#t~ret13#1; 3144#L560 assume !(0 != start_simulation_~tmp___0~1#1); 3143#L528-2 [2023-11-06 23:09:16,574 INFO L145 PredicateUnifier]: Initialized classic predicate unifier [2023-11-06 23:09:16,574 INFO L85 PathProgramCache]: Analyzing trace with hash -148513729, now seen corresponding path program 1 times [2023-11-06 23:09:16,574 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-06 23:09:16,574 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [385439209] [2023-11-06 23:09:16,574 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-06 23:09:16,575 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-06 23:09:16,590 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-06 23:09:16,705 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-06 23:09:16,706 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-06 23:09:16,706 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [385439209] [2023-11-06 23:09:16,706 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [385439209] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-06 23:09:16,706 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-06 23:09:16,707 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-06 23:09:16,707 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1169493366] [2023-11-06 23:09:16,707 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-06 23:09:16,708 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-06 23:09:16,708 INFO L145 PredicateUnifier]: Initialized classic predicate unifier [2023-11-06 23:09:16,708 INFO L85 PathProgramCache]: Analyzing trace with hash -96491490, now seen corresponding path program 1 times [2023-11-06 23:09:16,709 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-06 23:09:16,709 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [634489902] [2023-11-06 23:09:16,709 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-06 23:09:16,709 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-06 23:09:16,732 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-06 23:09:16,838 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-06 23:09:16,839 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-06 23:09:16,839 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [634489902] [2023-11-06 23:09:16,839 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [634489902] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-06 23:09:16,839 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-06 23:09:16,840 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2023-11-06 23:09:16,840 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [368748931] [2023-11-06 23:09:16,840 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-06 23:09:16,841 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-06 23:09:16,841 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-06 23:09:16,841 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2023-11-06 23:09:16,842 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2023-11-06 23:09:16,842 INFO L87 Difference]: Start difference. First operand 780 states and 1124 transitions. cyclomatic complexity: 348 Second operand has 4 states, 4 states have (on average 9.5) internal successors, (38), 3 states have internal predecessors, (38), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-06 23:09:16,929 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-06 23:09:16,929 INFO L93 Difference]: Finished difference Result 694 states and 973 transitions. [2023-11-06 23:09:16,929 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 694 states and 973 transitions. [2023-11-06 23:09:16,938 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 646 [2023-11-06 23:09:16,944 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 694 states to 694 states and 973 transitions. [2023-11-06 23:09:16,945 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 694 [2023-11-06 23:09:16,946 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 694 [2023-11-06 23:09:16,946 INFO L73 IsDeterministic]: Start isDeterministic. Operand 694 states and 973 transitions. [2023-11-06 23:09:16,947 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-06 23:09:16,948 INFO L218 hiAutomatonCegarLoop]: Abstraction has 694 states and 973 transitions. [2023-11-06 23:09:16,949 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 694 states and 973 transitions. [2023-11-06 23:09:16,962 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 694 to 678. [2023-11-06 23:09:16,964 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 678 states, 678 states have (on average 1.4056047197640118) internal successors, (953), 677 states have internal predecessors, (953), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-06 23:09:16,967 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 678 states to 678 states and 953 transitions. [2023-11-06 23:09:16,968 INFO L240 hiAutomatonCegarLoop]: Abstraction has 678 states and 953 transitions. [2023-11-06 23:09:16,968 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2023-11-06 23:09:16,971 INFO L428 stractBuchiCegarLoop]: Abstraction has 678 states and 953 transitions. [2023-11-06 23:09:16,971 INFO L335 stractBuchiCegarLoop]: ======== Iteration 6 ============ [2023-11-06 23:09:16,971 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 678 states and 953 transitions. [2023-11-06 23:09:16,976 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 634 [2023-11-06 23:09:16,977 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-06 23:09:16,977 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-06 23:09:16,980 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-06 23:09:16,980 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-06 23:09:16,981 INFO L748 eck$LassoCheckResult]: Stem: 4254#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2; 4255#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~4#1;havoc main_~__retres1~4#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1; 4269#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret12#1, start_simulation_#t~ret13#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 4265#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 4266#L221 assume 1 == ~m_i~0;~m_st~0 := 0; 4165#L221-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 4140#L226-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 4141#L231-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 4124#L334 assume !(0 == ~M_E~0); 4125#L334-2 assume !(0 == ~T1_E~0); 4227#L339-1 assume !(0 == ~T2_E~0); 4220#L344-1 assume !(0 == ~E_1~0); 4221#L349-1 assume !(0 == ~E_2~0); 4138#L354-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret8#1, activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 4139#L156 assume !(1 == ~m_pc~0); 4232#L156-2 is_master_triggered_~__retres1~0#1 := 0; 4245#L167 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 4239#is_master_triggered_returnLabel#1 activate_threads_#t~ret8#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 4187#L405 assume !(0 != activate_threads_~tmp~1#1); 4169#L405-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 4170#L175 assume !(1 == ~t1_pc~0); 4177#L175-2 is_transmit1_triggered_~__retres1~1#1 := 0; 4171#L186 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 4135#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret9#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 4136#L413 assume !(0 != activate_threads_~tmp___0~0#1); 4229#L413-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 4281#L194 assume !(1 == ~t2_pc~0); 4219#L194-2 is_transmit2_triggered_~__retres1~2#1 := 0; 4181#L205 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 4182#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret10#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 4113#L421 assume !(0 != activate_threads_~tmp___1~0#1); 4114#L421-2 havoc activate_threads_#t~ret8#1, activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 4083#L367 assume !(1 == ~M_E~0); 4084#L367-2 assume !(1 == ~T1_E~0); 4240#L372-1 assume !(1 == ~T2_E~0); 4241#L377-1 assume !(1 == ~E_1~0); 4110#L382-1 assume !(1 == ~E_2~0); 4111#L387-1 assume { :end_inline_reset_delta_events } true; 4190#L528-2 [2023-11-06 23:09:16,981 INFO L750 eck$LassoCheckResult]: Loop: 4190#L528-2 assume !false; 4323#L529 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 4321#L309-1 assume !false; 4320#L272 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 4318#L244 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 4316#L261 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 4315#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 4313#L276 assume !(0 != eval_~tmp~0#1); 4314#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 4407#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 4406#L334-3 assume 0 == ~M_E~0;~M_E~0 := 1; 4405#L334-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 4404#L339-3 assume !(0 == ~T2_E~0); 4403#L344-3 assume !(0 == ~E_1~0); 4402#L349-3 assume !(0 == ~E_2~0); 4401#L354-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret8#1, activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 4400#L156-9 assume !(1 == ~m_pc~0); 4399#L156-11 is_master_triggered_~__retres1~0#1 := 0; 4398#L167-3 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 4397#is_master_triggered_returnLabel#4 activate_threads_#t~ret8#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 4396#L405-9 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 4394#L405-11 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 4392#L175-9 assume !(1 == ~t1_pc~0); 4390#L175-11 is_transmit1_triggered_~__retres1~1#1 := 0; 4388#L186-3 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 4386#is_transmit1_triggered_returnLabel#4 activate_threads_#t~ret9#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 4384#L413-9 assume !(0 != activate_threads_~tmp___0~0#1); 4382#L413-11 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 4380#L194-9 assume 1 == ~t2_pc~0; 4377#L195-3 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 4375#L205-3 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 4373#is_transmit2_triggered_returnLabel#4 activate_threads_#t~ret10#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 4371#L421-9 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 4369#L421-11 havoc activate_threads_#t~ret8#1, activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 4366#L367-3 assume 1 == ~M_E~0;~M_E~0 := 2; 4364#L367-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 4362#L372-3 assume !(1 == ~T2_E~0); 4360#L377-3 assume !(1 == ~E_1~0); 4358#L382-3 assume 1 == ~E_2~0;~E_2~0 := 2; 4356#L387-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 4354#L244-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 4350#L261-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 4348#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret12#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret12#1;havoc start_simulation_#t~ret12#1; 4345#L547 assume !(0 == start_simulation_~tmp~3#1); 4343#L547-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret11#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 4342#L244-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 4339#L261-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 4338#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret11#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret11#1;havoc stop_simulation_#t~ret11#1; 4337#L502 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 4336#L509 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 4334#stop_simulation_returnLabel#1 start_simulation_#t~ret13#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret11#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret13#1;havoc start_simulation_#t~ret13#1; 4331#L560 assume !(0 != start_simulation_~tmp___0~1#1); 4190#L528-2 [2023-11-06 23:09:16,982 INFO L145 PredicateUnifier]: Initialized classic predicate unifier [2023-11-06 23:09:16,982 INFO L85 PathProgramCache]: Analyzing trace with hash -148511807, now seen corresponding path program 1 times [2023-11-06 23:09:16,983 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-06 23:09:16,984 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [59715880] [2023-11-06 23:09:16,984 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-06 23:09:16,984 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-06 23:09:16,997 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-06 23:09:16,997 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-06 23:09:17,002 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-06 23:09:17,040 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-06 23:09:17,041 INFO L145 PredicateUnifier]: Initialized classic predicate unifier [2023-11-06 23:09:17,041 INFO L85 PathProgramCache]: Analyzing trace with hash -898972165, now seen corresponding path program 1 times [2023-11-06 23:09:17,041 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-06 23:09:17,042 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [968545489] [2023-11-06 23:09:17,042 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-06 23:09:17,042 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-06 23:09:17,055 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-06 23:09:17,102 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-06 23:09:17,102 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-06 23:09:17,103 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [968545489] [2023-11-06 23:09:17,103 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [968545489] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-06 23:09:17,103 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-06 23:09:17,103 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2023-11-06 23:09:17,104 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [488132642] [2023-11-06 23:09:17,104 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-06 23:09:17,104 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-06 23:09:17,105 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-06 23:09:17,105 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2023-11-06 23:09:17,105 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2023-11-06 23:09:17,106 INFO L87 Difference]: Start difference. First operand 678 states and 953 transitions. cyclomatic complexity: 278 Second operand has 5 states, 5 states have (on average 10.4) internal successors, (52), 5 states have internal predecessors, (52), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-06 23:09:17,205 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-06 23:09:17,205 INFO L93 Difference]: Finished difference Result 1146 states and 1580 transitions. [2023-11-06 23:09:17,205 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1146 states and 1580 transitions. [2023-11-06 23:09:17,215 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 1097 [2023-11-06 23:09:17,224 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1146 states to 1146 states and 1580 transitions. [2023-11-06 23:09:17,225 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1146 [2023-11-06 23:09:17,226 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1146 [2023-11-06 23:09:17,226 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1146 states and 1580 transitions. [2023-11-06 23:09:17,228 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-06 23:09:17,228 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1146 states and 1580 transitions. [2023-11-06 23:09:17,229 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1146 states and 1580 transitions. [2023-11-06 23:09:17,241 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1146 to 693. [2023-11-06 23:09:17,243 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 693 states, 693 states have (on average 1.3968253968253967) internal successors, (968), 692 states have internal predecessors, (968), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-06 23:09:17,246 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 693 states to 693 states and 968 transitions. [2023-11-06 23:09:17,246 INFO L240 hiAutomatonCegarLoop]: Abstraction has 693 states and 968 transitions. [2023-11-06 23:09:17,247 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 9 states. [2023-11-06 23:09:17,249 INFO L428 stractBuchiCegarLoop]: Abstraction has 693 states and 968 transitions. [2023-11-06 23:09:17,249 INFO L335 stractBuchiCegarLoop]: ======== Iteration 7 ============ [2023-11-06 23:09:17,249 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 693 states and 968 transitions. [2023-11-06 23:09:17,254 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 649 [2023-11-06 23:09:17,254 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-06 23:09:17,254 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-06 23:09:17,255 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-06 23:09:17,256 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-06 23:09:17,256 INFO L748 eck$LassoCheckResult]: Stem: 6113#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2; 6114#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~4#1;havoc main_~__retres1~4#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1; 6127#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret12#1, start_simulation_#t~ret13#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 6123#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 6124#L221 assume 1 == ~m_i~0;~m_st~0 := 0; 6012#L221-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 5984#L226-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 5985#L231-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 5966#L334 assume !(0 == ~M_E~0); 5967#L334-2 assume !(0 == ~T1_E~0); 6075#L339-1 assume !(0 == ~T2_E~0); 6066#L344-1 assume !(0 == ~E_1~0); 6067#L349-1 assume !(0 == ~E_2~0); 5982#L354-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret8#1, activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 5983#L156 assume !(1 == ~m_pc~0); 6080#L156-2 is_master_triggered_~__retres1~0#1 := 0; 6099#L167 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 6090#is_master_triggered_returnLabel#1 activate_threads_#t~ret8#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 6035#L405 assume !(0 != activate_threads_~tmp~1#1); 6017#L405-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 6018#L175 assume !(1 == ~t1_pc~0); 6025#L175-2 is_transmit1_triggered_~__retres1~1#1 := 0; 6019#L186 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 5979#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret9#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 5980#L413 assume !(0 != activate_threads_~tmp___0~0#1); 6077#L413-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 6141#L194 assume !(1 == ~t2_pc~0); 6064#L194-2 is_transmit2_triggered_~__retres1~2#1 := 0; 6029#L205 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 6030#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret10#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 5954#L421 assume !(0 != activate_threads_~tmp___1~0#1); 5955#L421-2 havoc activate_threads_#t~ret8#1, activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 5924#L367 assume !(1 == ~M_E~0); 5925#L367-2 assume !(1 == ~T1_E~0); 6091#L372-1 assume !(1 == ~T2_E~0); 6092#L377-1 assume !(1 == ~E_1~0); 5951#L382-1 assume !(1 == ~E_2~0); 5952#L387-1 assume { :end_inline_reset_delta_events } true; 6037#L528-2 [2023-11-06 23:09:17,256 INFO L750 eck$LassoCheckResult]: Loop: 6037#L528-2 assume !false; 6044#L529 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 5934#L309-1 assume !false; 5935#L272 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 6443#L244 assume !(0 == ~m_st~0); 6444#L248 assume !(0 == ~t1_st~0); 6441#L252 assume !(0 == ~t2_st~0);exists_runnable_thread_~__retres1~3#1 := 0; 6442#L261 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 6378#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 6379#L276 assume !(0 != eval_~tmp~0#1); 6438#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 6437#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 6436#L334-3 assume 0 == ~M_E~0;~M_E~0 := 1; 6435#L334-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 6434#L339-3 assume !(0 == ~T2_E~0); 6433#L344-3 assume !(0 == ~E_1~0); 6432#L349-3 assume !(0 == ~E_2~0); 5964#L354-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret8#1, activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 5965#L156-9 assume !(1 == ~m_pc~0); 6058#L156-11 is_master_triggered_~__retres1~0#1 := 0; 6008#L167-3 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 6009#is_master_triggered_returnLabel#4 activate_threads_#t~ret8#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 6081#L405-9 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 6082#L405-11 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 6146#L175-9 assume !(1 == ~t1_pc~0); 6147#L175-11 is_transmit1_triggered_~__retres1~1#1 := 0; 5928#L186-3 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 5929#is_transmit1_triggered_returnLabel#4 activate_threads_#t~ret9#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 6121#L413-9 assume !(0 != activate_threads_~tmp___0~0#1); 6122#L413-11 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 6142#L194-9 assume !(1 == ~t2_pc~0); 6144#L194-11 is_transmit2_triggered_~__retres1~2#1 := 0; 6151#L205-3 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 6152#is_transmit2_triggered_returnLabel#4 activate_threads_#t~ret10#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 6069#L421-9 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 6070#L421-11 havoc activate_threads_#t~ret8#1, activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 6003#L367-3 assume 1 == ~M_E~0;~M_E~0 := 2; 6004#L367-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 5968#L372-3 assume !(1 == ~T2_E~0); 5969#L377-3 assume !(1 == ~E_1~0); 5960#L382-3 assume 1 == ~E_2~0;~E_2~0 := 2; 5961#L387-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 6109#L244-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 5971#L261-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 6139#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret12#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret12#1;havoc start_simulation_#t~ret12#1; 6119#L547 assume !(0 == start_simulation_~tmp~3#1); 6120#L547-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret11#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 6131#L244-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 6571#L261-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 6569#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret11#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret11#1;havoc stop_simulation_#t~ret11#1; 6567#L502 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 6566#L509 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 6563#stop_simulation_returnLabel#1 start_simulation_#t~ret13#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret11#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret13#1;havoc start_simulation_#t~ret13#1; 6561#L560 assume !(0 != start_simulation_~tmp___0~1#1); 6037#L528-2 [2023-11-06 23:09:17,257 INFO L145 PredicateUnifier]: Initialized classic predicate unifier [2023-11-06 23:09:17,258 INFO L85 PathProgramCache]: Analyzing trace with hash -148511807, now seen corresponding path program 2 times [2023-11-06 23:09:17,260 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-06 23:09:17,261 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [489542201] [2023-11-06 23:09:17,261 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-06 23:09:17,262 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-06 23:09:17,272 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-06 23:09:17,272 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-06 23:09:17,285 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-06 23:09:17,293 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-06 23:09:17,294 INFO L145 PredicateUnifier]: Initialized classic predicate unifier [2023-11-06 23:09:17,295 INFO L85 PathProgramCache]: Analyzing trace with hash -975167437, now seen corresponding path program 1 times [2023-11-06 23:09:17,296 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-06 23:09:17,296 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1950542833] [2023-11-06 23:09:17,296 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-06 23:09:17,296 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-06 23:09:17,313 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-06 23:09:17,397 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-06 23:09:17,397 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-06 23:09:17,397 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1950542833] [2023-11-06 23:09:17,398 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1950542833] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-06 23:09:17,398 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-06 23:09:17,398 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2023-11-06 23:09:17,398 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1961383700] [2023-11-06 23:09:17,398 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-06 23:09:17,400 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-06 23:09:17,400 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-06 23:09:17,400 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2023-11-06 23:09:17,401 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2023-11-06 23:09:17,401 INFO L87 Difference]: Start difference. First operand 693 states and 968 transitions. cyclomatic complexity: 278 Second operand has 5 states, 5 states have (on average 10.8) internal successors, (54), 5 states have internal predecessors, (54), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-06 23:09:17,525 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-06 23:09:17,526 INFO L93 Difference]: Finished difference Result 1379 states and 1895 transitions. [2023-11-06 23:09:17,526 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1379 states and 1895 transitions. [2023-11-06 23:09:17,537 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 1335 [2023-11-06 23:09:17,548 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1379 states to 1379 states and 1895 transitions. [2023-11-06 23:09:17,549 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1379 [2023-11-06 23:09:17,550 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1379 [2023-11-06 23:09:17,550 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1379 states and 1895 transitions. [2023-11-06 23:09:17,552 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-06 23:09:17,552 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1379 states and 1895 transitions. [2023-11-06 23:09:17,554 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1379 states and 1895 transitions. [2023-11-06 23:09:17,567 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1379 to 729. [2023-11-06 23:09:17,569 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 729 states, 729 states have (on average 1.373113854595336) internal successors, (1001), 728 states have internal predecessors, (1001), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-06 23:09:17,572 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 729 states to 729 states and 1001 transitions. [2023-11-06 23:09:17,572 INFO L240 hiAutomatonCegarLoop]: Abstraction has 729 states and 1001 transitions. [2023-11-06 23:09:17,572 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2023-11-06 23:09:17,573 INFO L428 stractBuchiCegarLoop]: Abstraction has 729 states and 1001 transitions. [2023-11-06 23:09:17,573 INFO L335 stractBuchiCegarLoop]: ======== Iteration 8 ============ [2023-11-06 23:09:17,573 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 729 states and 1001 transitions. [2023-11-06 23:09:17,577 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 685 [2023-11-06 23:09:17,578 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-06 23:09:17,578 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-06 23:09:17,579 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-06 23:09:17,579 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-06 23:09:17,579 INFO L748 eck$LassoCheckResult]: Stem: 8199#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2; 8200#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~4#1;havoc main_~__retres1~4#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1; 8212#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret12#1, start_simulation_#t~ret13#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 8207#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 8208#L221 assume 1 == ~m_i~0;~m_st~0 := 0; 8097#L221-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 8066#L226-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 8067#L231-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 8049#L334 assume !(0 == ~M_E~0); 8050#L334-2 assume !(0 == ~T1_E~0); 8167#L339-1 assume !(0 == ~T2_E~0); 8161#L344-1 assume !(0 == ~E_1~0); 8162#L349-1 assume !(0 == ~E_2~0); 8064#L354-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret8#1, activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 8065#L156 assume !(1 == ~m_pc~0); 8172#L156-2 is_master_triggered_~__retres1~0#1 := 0; 8190#L167 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 8183#is_master_triggered_returnLabel#1 activate_threads_#t~ret8#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 8123#L405 assume !(0 != activate_threads_~tmp~1#1); 8101#L405-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 8102#L175 assume !(1 == ~t1_pc~0); 8109#L175-2 is_transmit1_triggered_~__retres1~1#1 := 0; 8103#L186 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 8061#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret9#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 8062#L413 assume !(0 != activate_threads_~tmp___0~0#1); 8169#L413-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 8234#L194 assume !(1 == ~t2_pc~0); 8160#L194-2 is_transmit2_triggered_~__retres1~2#1 := 0; 8113#L205 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 8114#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret10#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 8038#L421 assume !(0 != activate_threads_~tmp___1~0#1); 8039#L421-2 havoc activate_threads_#t~ret8#1, activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 8008#L367 assume !(1 == ~M_E~0); 8009#L367-2 assume !(1 == ~T1_E~0); 8184#L372-1 assume !(1 == ~T2_E~0); 8185#L377-1 assume !(1 == ~E_1~0); 8035#L382-1 assume !(1 == ~E_2~0); 8036#L387-1 assume { :end_inline_reset_delta_events } true; 8126#L528-2 [2023-11-06 23:09:17,579 INFO L750 eck$LassoCheckResult]: Loop: 8126#L528-2 assume !false; 8273#L529 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 8271#L309-1 assume !false; 8270#L272 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 8268#L244 assume !(0 == ~m_st~0); 8269#L248 assume !(0 == ~t1_st~0); 8266#L252 assume !(0 == ~t2_st~0);exists_runnable_thread_~__retres1~3#1 := 0; 8267#L261 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 8262#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 8263#L276 assume !(0 != eval_~tmp~0#1); 8358#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 8357#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 8356#L334-3 assume 0 == ~M_E~0;~M_E~0 := 1; 8355#L334-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 8354#L339-3 assume !(0 == ~T2_E~0); 8353#L344-3 assume !(0 == ~E_1~0); 8352#L349-3 assume !(0 == ~E_2~0); 8351#L354-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret8#1, activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 8350#L156-9 assume !(1 == ~m_pc~0); 8349#L156-11 is_master_triggered_~__retres1~0#1 := 0; 8348#L167-3 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 8347#is_master_triggered_returnLabel#4 activate_threads_#t~ret8#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 8346#L405-9 assume !(0 != activate_threads_~tmp~1#1); 8344#L405-11 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 8342#L175-9 assume !(1 == ~t1_pc~0); 8340#L175-11 is_transmit1_triggered_~__retres1~1#1 := 0; 8338#L186-3 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 8336#is_transmit1_triggered_returnLabel#4 activate_threads_#t~ret9#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 8334#L413-9 assume !(0 != activate_threads_~tmp___0~0#1); 8332#L413-11 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 8330#L194-9 assume 1 == ~t2_pc~0; 8327#L195-3 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 8325#L205-3 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 8323#is_transmit2_triggered_returnLabel#4 activate_threads_#t~ret10#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 8321#L421-9 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 8319#L421-11 havoc activate_threads_#t~ret8#1, activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 8316#L367-3 assume 1 == ~M_E~0;~M_E~0 := 2; 8314#L367-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 8312#L372-3 assume !(1 == ~T2_E~0); 8310#L377-3 assume !(1 == ~E_1~0); 8308#L382-3 assume 1 == ~E_2~0;~E_2~0 := 2; 8306#L387-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 8304#L244-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 8300#L261-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 8298#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret12#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret12#1;havoc start_simulation_#t~ret12#1; 8295#L547 assume !(0 == start_simulation_~tmp~3#1); 8293#L547-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret11#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 8292#L244-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 8289#L261-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 8288#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret11#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret11#1;havoc stop_simulation_#t~ret11#1; 8287#L502 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 8286#L509 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 8284#stop_simulation_returnLabel#1 start_simulation_#t~ret13#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret11#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret13#1;havoc start_simulation_#t~ret13#1; 8281#L560 assume !(0 != start_simulation_~tmp___0~1#1); 8126#L528-2 [2023-11-06 23:09:17,580 INFO L145 PredicateUnifier]: Initialized classic predicate unifier [2023-11-06 23:09:17,580 INFO L85 PathProgramCache]: Analyzing trace with hash -148511807, now seen corresponding path program 3 times [2023-11-06 23:09:17,580 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-06 23:09:17,581 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [584510841] [2023-11-06 23:09:17,581 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-06 23:09:17,581 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-06 23:09:17,589 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-06 23:09:17,589 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-06 23:09:17,594 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-06 23:09:17,600 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-06 23:09:17,600 INFO L145 PredicateUnifier]: Initialized classic predicate unifier [2023-11-06 23:09:17,601 INFO L85 PathProgramCache]: Analyzing trace with hash 889987154, now seen corresponding path program 1 times [2023-11-06 23:09:17,601 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-06 23:09:17,601 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1320498301] [2023-11-06 23:09:17,601 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-06 23:09:17,601 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-06 23:09:17,608 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-06 23:09:17,629 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-06 23:09:17,629 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-06 23:09:17,630 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1320498301] [2023-11-06 23:09:17,630 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1320498301] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-06 23:09:17,630 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-06 23:09:17,630 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-06 23:09:17,631 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [747783559] [2023-11-06 23:09:17,631 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-06 23:09:17,631 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-06 23:09:17,631 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-06 23:09:17,632 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-06 23:09:17,632 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-06 23:09:17,632 INFO L87 Difference]: Start difference. First operand 729 states and 1001 transitions. cyclomatic complexity: 275 Second operand has 3 states, 3 states have (on average 18.0) internal successors, (54), 3 states have internal predecessors, (54), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-06 23:09:17,682 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-06 23:09:17,682 INFO L93 Difference]: Finished difference Result 1186 states and 1597 transitions. [2023-11-06 23:09:17,683 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1186 states and 1597 transitions. [2023-11-06 23:09:17,693 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 1140 [2023-11-06 23:09:17,702 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1186 states to 1186 states and 1597 transitions. [2023-11-06 23:09:17,702 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1186 [2023-11-06 23:09:17,703 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1186 [2023-11-06 23:09:17,704 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1186 states and 1597 transitions. [2023-11-06 23:09:17,707 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-06 23:09:17,707 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1186 states and 1597 transitions. [2023-11-06 23:09:17,708 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1186 states and 1597 transitions. [2023-11-06 23:09:17,723 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1186 to 1151. [2023-11-06 23:09:17,726 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1151 states, 1151 states have (on average 1.3483927019982624) internal successors, (1552), 1150 states have internal predecessors, (1552), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-06 23:09:17,731 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1151 states to 1151 states and 1552 transitions. [2023-11-06 23:09:17,731 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1151 states and 1552 transitions. [2023-11-06 23:09:17,731 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-06 23:09:17,735 INFO L428 stractBuchiCegarLoop]: Abstraction has 1151 states and 1552 transitions. [2023-11-06 23:09:17,735 INFO L335 stractBuchiCegarLoop]: ======== Iteration 9 ============ [2023-11-06 23:09:17,735 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1151 states and 1552 transitions. [2023-11-06 23:09:17,742 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 1105 [2023-11-06 23:09:17,742 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-06 23:09:17,742 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-06 23:09:17,744 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-06 23:09:17,744 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-06 23:09:17,744 INFO L748 eck$LassoCheckResult]: Stem: 10109#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2; 10110#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~4#1;havoc main_~__retres1~4#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1; 10121#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret12#1, start_simulation_#t~ret13#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 10118#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 10119#L221 assume 1 == ~m_i~0;~m_st~0 := 0; 10013#L221-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 9985#L226-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 9986#L231-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 9969#L334 assume !(0 == ~M_E~0); 9970#L334-2 assume !(0 == ~T1_E~0); 10077#L339-1 assume !(0 == ~T2_E~0); 10071#L344-1 assume !(0 == ~E_1~0); 10072#L349-1 assume !(0 == ~E_2~0); 9983#L354-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret8#1, activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 9984#L156 assume !(1 == ~m_pc~0); 10082#L156-2 is_master_triggered_~__retres1~0#1 := 0; 10099#L167 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 10093#is_master_triggered_returnLabel#1 activate_threads_#t~ret8#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 10040#L405 assume !(0 != activate_threads_~tmp~1#1); 10019#L405-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 10020#L175 assume !(1 == ~t1_pc~0); 10027#L175-2 is_transmit1_triggered_~__retres1~1#1 := 0; 10021#L186 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 9980#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret9#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 9981#L413 assume !(0 != activate_threads_~tmp___0~0#1); 10079#L413-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 10142#L194 assume !(1 == ~t2_pc~0); 10070#L194-2 is_transmit2_triggered_~__retres1~2#1 := 0; 10031#L205 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 10032#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret10#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 9958#L421 assume !(0 != activate_threads_~tmp___1~0#1); 9959#L421-2 havoc activate_threads_#t~ret8#1, activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 9928#L367 assume !(1 == ~M_E~0); 9929#L367-2 assume !(1 == ~T1_E~0); 10094#L372-1 assume !(1 == ~T2_E~0); 10095#L377-1 assume !(1 == ~E_1~0); 9955#L382-1 assume !(1 == ~E_2~0); 9956#L387-1 assume { :end_inline_reset_delta_events } true; 10043#L528-2 assume !false; 10171#L529 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 10169#L309-1 [2023-11-06 23:09:17,744 INFO L750 eck$LassoCheckResult]: Loop: 10169#L309-1 assume !false; 10168#L272 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 10167#L244 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 10166#L261 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 10165#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 10164#L276 assume 0 != eval_~tmp~0#1; 10162#L276-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;havoc eval_#t~nondet5#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet5#1;havoc eval_#t~nondet5#1; 10160#L284 assume !(0 != eval_~tmp_ndt_1~0#1); 10161#L284-2 havoc eval_~tmp_ndt_1~0#1; 10177#L281-1 assume !(0 == ~t1_st~0); 10172#L295-1 assume !(0 == ~t2_st~0); 10169#L309-1 [2023-11-06 23:09:17,745 INFO L145 PredicateUnifier]: Initialized classic predicate unifier [2023-11-06 23:09:17,745 INFO L85 PathProgramCache]: Analyzing trace with hash -985920349, now seen corresponding path program 1 times [2023-11-06 23:09:17,745 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-06 23:09:17,747 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1522087238] [2023-11-06 23:09:17,747 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-06 23:09:17,748 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-06 23:09:17,761 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-06 23:09:17,761 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-06 23:09:17,766 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-06 23:09:17,782 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-06 23:09:17,783 INFO L145 PredicateUnifier]: Initialized classic predicate unifier [2023-11-06 23:09:17,783 INFO L85 PathProgramCache]: Analyzing trace with hash 993947407, now seen corresponding path program 1 times [2023-11-06 23:09:17,786 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-06 23:09:17,787 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [186212669] [2023-11-06 23:09:17,787 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-06 23:09:17,787 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-06 23:09:17,791 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-06 23:09:17,791 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-06 23:09:17,792 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-06 23:09:17,803 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-06 23:09:17,803 INFO L145 PredicateUnifier]: Initialized classic predicate unifier [2023-11-06 23:09:17,804 INFO L85 PathProgramCache]: Analyzing trace with hash 1252886829, now seen corresponding path program 1 times [2023-11-06 23:09:17,804 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-06 23:09:17,804 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2102512622] [2023-11-06 23:09:17,804 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-06 23:09:17,804 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-06 23:09:17,811 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-06 23:09:17,832 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-06 23:09:17,833 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-06 23:09:17,833 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2102512622] [2023-11-06 23:09:17,833 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2102512622] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-06 23:09:17,833 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-06 23:09:17,833 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-06 23:09:17,833 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1872608606] [2023-11-06 23:09:17,834 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-06 23:09:17,899 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-06 23:09:17,899 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-06 23:09:17,899 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-06 23:09:17,900 INFO L87 Difference]: Start difference. First operand 1151 states and 1552 transitions. cyclomatic complexity: 405 Second operand has 3 states, 3 states have (on average 17.0) internal successors, (51), 3 states have internal predecessors, (51), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-06 23:09:17,945 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-06 23:09:17,945 INFO L93 Difference]: Finished difference Result 2023 states and 2695 transitions. [2023-11-06 23:09:17,945 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2023 states and 2695 transitions. [2023-11-06 23:09:17,961 INFO L131 ngComponentsAnalysis]: Automaton has 6 accepting balls. 1881 [2023-11-06 23:09:17,977 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2023 states to 2023 states and 2695 transitions. [2023-11-06 23:09:17,977 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2023 [2023-11-06 23:09:17,979 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2023 [2023-11-06 23:09:17,979 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2023 states and 2695 transitions. [2023-11-06 23:09:17,982 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-06 23:09:17,982 INFO L218 hiAutomatonCegarLoop]: Abstraction has 2023 states and 2695 transitions. [2023-11-06 23:09:17,985 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2023 states and 2695 transitions. [2023-11-06 23:09:18,011 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2023 to 1925. [2023-11-06 23:09:18,015 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1925 states, 1925 states have (on average 1.3366233766233766) internal successors, (2573), 1924 states have internal predecessors, (2573), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-06 23:09:18,023 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1925 states to 1925 states and 2573 transitions. [2023-11-06 23:09:18,023 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1925 states and 2573 transitions. [2023-11-06 23:09:18,023 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-06 23:09:18,024 INFO L428 stractBuchiCegarLoop]: Abstraction has 1925 states and 2573 transitions. [2023-11-06 23:09:18,024 INFO L335 stractBuchiCegarLoop]: ======== Iteration 10 ============ [2023-11-06 23:09:18,024 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1925 states and 2573 transitions. [2023-11-06 23:09:18,036 INFO L131 ngComponentsAnalysis]: Automaton has 5 accepting balls. 1818 [2023-11-06 23:09:18,036 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-06 23:09:18,036 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-06 23:09:18,037 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-06 23:09:18,037 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-06 23:09:18,037 INFO L748 eck$LassoCheckResult]: Stem: 13306#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2; 13307#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~4#1;havoc main_~__retres1~4#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1; 13321#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret12#1, start_simulation_#t~ret13#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 13317#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 13318#L221 assume 1 == ~m_i~0;~m_st~0 := 0; 13195#L221-2 assume !(1 == ~t1_i~0);~t1_st~0 := 2; 13196#L226-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 13324#L231-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 13325#L334 assume !(0 == ~M_E~0); 13334#L334-2 assume !(0 == ~T1_E~0); 13335#L339-1 assume !(0 == ~T2_E~0); 13258#L344-1 assume !(0 == ~E_1~0); 13259#L349-1 assume !(0 == ~E_2~0); 13164#L354-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret8#1, activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 13165#L156 assume !(1 == ~m_pc~0); 13315#L156-2 is_master_triggered_~__retres1~0#1 := 0; 13316#L167 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 13283#is_master_triggered_returnLabel#1 activate_threads_#t~ret8#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 13284#L405 assume !(0 != activate_threads_~tmp~1#1); 13203#L405-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 13204#L175 assume !(1 == ~t1_pc~0); 13211#L175-2 is_transmit1_triggered_~__retres1~1#1 := 0; 13212#L186 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 13161#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret9#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 13162#L413 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 13270#L413-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 13345#L194 assume !(1 == ~t2_pc~0); 13257#L194-2 is_transmit2_triggered_~__retres1~2#1 := 0; 13216#L205 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 13217#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret10#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 13139#L421 assume !(0 != activate_threads_~tmp___1~0#1); 13140#L421-2 havoc activate_threads_#t~ret8#1, activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 13111#L367 assume !(1 == ~M_E~0); 13112#L367-2 assume !(1 == ~T1_E~0); 13344#L372-1 assume !(1 == ~T2_E~0); 13288#L377-1 assume !(1 == ~E_1~0); 13136#L382-1 assume !(1 == ~E_2~0); 13137#L387-1 assume { :end_inline_reset_delta_events } true; 13438#L528-2 assume !false; 13420#L529 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 13419#L309-1 [2023-11-06 23:09:18,037 INFO L750 eck$LassoCheckResult]: Loop: 13419#L309-1 assume !false; 13414#L272 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 13415#L244 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 13409#L261 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 13410#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 13405#L276 assume 0 != eval_~tmp~0#1; 13406#L276-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;havoc eval_#t~nondet5#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet5#1;havoc eval_#t~nondet5#1; 13399#L284 assume !(0 != eval_~tmp_ndt_1~0#1); 13401#L284-2 havoc eval_~tmp_ndt_1~0#1; 13434#L281-1 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0#1;havoc eval_#t~nondet6#1;eval_~tmp_ndt_2~0#1 := eval_#t~nondet6#1;havoc eval_#t~nondet6#1; 13430#L298 assume !(0 != eval_~tmp_ndt_2~0#1); 13428#L298-2 havoc eval_~tmp_ndt_2~0#1; 13421#L295-1 assume !(0 == ~t2_st~0); 13419#L309-1 [2023-11-06 23:09:18,037 INFO L145 PredicateUnifier]: Initialized classic predicate unifier [2023-11-06 23:09:18,038 INFO L85 PathProgramCache]: Analyzing trace with hash -808857497, now seen corresponding path program 1 times [2023-11-06 23:09:18,038 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-06 23:09:18,038 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [966874290] [2023-11-06 23:09:18,038 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-06 23:09:18,038 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-06 23:09:18,044 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-06 23:09:18,059 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-06 23:09:18,059 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-06 23:09:18,059 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [966874290] [2023-11-06 23:09:18,060 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [966874290] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-06 23:09:18,060 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-06 23:09:18,060 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-06 23:09:18,060 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [534470423] [2023-11-06 23:09:18,060 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-06 23:09:18,060 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-06 23:09:18,061 INFO L145 PredicateUnifier]: Initialized classic predicate unifier [2023-11-06 23:09:18,061 INFO L85 PathProgramCache]: Analyzing trace with hash 1697436410, now seen corresponding path program 1 times [2023-11-06 23:09:18,061 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-06 23:09:18,061 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1907583454] [2023-11-06 23:09:18,061 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-06 23:09:18,061 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-06 23:09:18,064 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-06 23:09:18,065 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-06 23:09:18,066 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-06 23:09:18,068 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-06 23:09:18,123 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-06 23:09:18,124 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-06 23:09:18,124 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-06 23:09:18,124 INFO L87 Difference]: Start difference. First operand 1925 states and 2573 transitions. cyclomatic complexity: 653 Second operand has 3 states, 3 states have (on average 13.333333333333334) internal successors, (40), 3 states have internal predecessors, (40), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-06 23:09:18,138 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-06 23:09:18,139 INFO L93 Difference]: Finished difference Result 1748 states and 2340 transitions. [2023-11-06 23:09:18,139 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1748 states and 2340 transitions. [2023-11-06 23:09:18,152 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 1702 [2023-11-06 23:09:18,165 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1748 states to 1748 states and 2340 transitions. [2023-11-06 23:09:18,165 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1748 [2023-11-06 23:09:18,167 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1748 [2023-11-06 23:09:18,167 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1748 states and 2340 transitions. [2023-11-06 23:09:18,170 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-06 23:09:18,170 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1748 states and 2340 transitions. [2023-11-06 23:09:18,172 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1748 states and 2340 transitions. [2023-11-06 23:09:18,194 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1748 to 1748. [2023-11-06 23:09:18,237 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1748 states, 1748 states have (on average 1.3386727688787186) internal successors, (2340), 1747 states have internal predecessors, (2340), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-06 23:09:18,243 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1748 states to 1748 states and 2340 transitions. [2023-11-06 23:09:18,244 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1748 states and 2340 transitions. [2023-11-06 23:09:18,244 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-06 23:09:18,244 INFO L428 stractBuchiCegarLoop]: Abstraction has 1748 states and 2340 transitions. [2023-11-06 23:09:18,245 INFO L335 stractBuchiCegarLoop]: ======== Iteration 11 ============ [2023-11-06 23:09:18,245 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1748 states and 2340 transitions. [2023-11-06 23:09:18,254 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 1702 [2023-11-06 23:09:18,254 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-06 23:09:18,254 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-06 23:09:18,255 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-06 23:09:18,255 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-06 23:09:18,255 INFO L748 eck$LassoCheckResult]: Stem: 16971#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2; 16972#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~4#1;havoc main_~__retres1~4#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1; 16982#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret12#1, start_simulation_#t~ret13#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 16979#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 16980#L221 assume 1 == ~m_i~0;~m_st~0 := 0; 16871#L221-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 16845#L226-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 16846#L231-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 16829#L334 assume !(0 == ~M_E~0); 16830#L334-2 assume !(0 == ~T1_E~0); 16936#L339-1 assume !(0 == ~T2_E~0); 16930#L344-1 assume !(0 == ~E_1~0); 16931#L349-1 assume !(0 == ~E_2~0); 16843#L354-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret8#1, activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 16844#L156 assume !(1 == ~m_pc~0); 16941#L156-2 is_master_triggered_~__retres1~0#1 := 0; 16959#L167 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 16950#is_master_triggered_returnLabel#1 activate_threads_#t~ret8#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 16896#L405 assume !(0 != activate_threads_~tmp~1#1); 16876#L405-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 16877#L175 assume !(1 == ~t1_pc~0); 16884#L175-2 is_transmit1_triggered_~__retres1~1#1 := 0; 16878#L186 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 16840#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret9#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 16841#L413 assume !(0 != activate_threads_~tmp___0~0#1); 16938#L413-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 17003#L194 assume !(1 == ~t2_pc~0); 16929#L194-2 is_transmit2_triggered_~__retres1~2#1 := 0; 16889#L205 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 16890#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret10#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 16818#L421 assume !(0 != activate_threads_~tmp___1~0#1); 16819#L421-2 havoc activate_threads_#t~ret8#1, activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 16790#L367 assume !(1 == ~M_E~0); 16791#L367-2 assume !(1 == ~T1_E~0); 16951#L372-1 assume !(1 == ~T2_E~0); 16952#L377-1 assume !(1 == ~E_1~0); 16815#L382-1 assume !(1 == ~E_2~0); 16816#L387-1 assume { :end_inline_reset_delta_events } true; 16899#L528-2 assume !false; 18500#L529 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 18498#L309-1 [2023-11-06 23:09:18,255 INFO L750 eck$LassoCheckResult]: Loop: 18498#L309-1 assume !false; 18497#L272 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 18496#L244 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 18495#L261 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 18494#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 18493#L276 assume 0 != eval_~tmp~0#1; 18492#L276-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;havoc eval_#t~nondet5#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet5#1;havoc eval_#t~nondet5#1; 16872#L284 assume !(0 != eval_~tmp_ndt_1~0#1); 16874#L284-2 havoc eval_~tmp_ndt_1~0#1; 16913#L281-1 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0#1;havoc eval_#t~nondet6#1;eval_~tmp_ndt_2~0#1 := eval_#t~nondet6#1;havoc eval_#t~nondet6#1; 16914#L298 assume !(0 != eval_~tmp_ndt_2~0#1); 16970#L298-2 havoc eval_~tmp_ndt_2~0#1; 18501#L295-1 assume !(0 == ~t2_st~0); 18498#L309-1 [2023-11-06 23:09:18,256 INFO L145 PredicateUnifier]: Initialized classic predicate unifier [2023-11-06 23:09:18,256 INFO L85 PathProgramCache]: Analyzing trace with hash -985920349, now seen corresponding path program 2 times [2023-11-06 23:09:18,256 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-06 23:09:18,256 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [122023287] [2023-11-06 23:09:18,256 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-06 23:09:18,256 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-06 23:09:18,263 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-06 23:09:18,264 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-06 23:09:18,268 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-06 23:09:18,273 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-06 23:09:18,273 INFO L145 PredicateUnifier]: Initialized classic predicate unifier [2023-11-06 23:09:18,273 INFO L85 PathProgramCache]: Analyzing trace with hash 1697436410, now seen corresponding path program 2 times [2023-11-06 23:09:18,273 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-06 23:09:18,273 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1441757141] [2023-11-06 23:09:18,274 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-06 23:09:18,274 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-06 23:09:18,277 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-06 23:09:18,277 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-06 23:09:18,279 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-06 23:09:18,280 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-06 23:09:18,281 INFO L145 PredicateUnifier]: Initialized classic predicate unifier [2023-11-06 23:09:18,281 INFO L85 PathProgramCache]: Analyzing trace with hash 1430117784, now seen corresponding path program 1 times [2023-11-06 23:09:18,281 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-06 23:09:18,281 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [817162254] [2023-11-06 23:09:18,282 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-06 23:09:18,282 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-06 23:09:18,289 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-06 23:09:18,312 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-06 23:09:18,312 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-06 23:09:18,313 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [817162254] [2023-11-06 23:09:18,313 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [817162254] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-06 23:09:18,313 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-06 23:09:18,313 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2023-11-06 23:09:18,313 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [543823985] [2023-11-06 23:09:18,313 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-06 23:09:18,373 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-06 23:09:18,374 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-06 23:09:18,374 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-06 23:09:18,374 INFO L87 Difference]: Start difference. First operand 1748 states and 2340 transitions. cyclomatic complexity: 595 Second operand has 3 states, 2 states have (on average 26.5) internal successors, (53), 3 states have internal predecessors, (53), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-06 23:09:18,435 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-06 23:09:18,435 INFO L93 Difference]: Finished difference Result 3097 states and 4118 transitions. [2023-11-06 23:09:18,436 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 3097 states and 4118 transitions. [2023-11-06 23:09:18,455 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 3046 [2023-11-06 23:09:18,478 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 3097 states to 3097 states and 4118 transitions. [2023-11-06 23:09:18,478 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 3097 [2023-11-06 23:09:18,481 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 3097 [2023-11-06 23:09:18,481 INFO L73 IsDeterministic]: Start isDeterministic. Operand 3097 states and 4118 transitions. [2023-11-06 23:09:18,485 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-06 23:09:18,486 INFO L218 hiAutomatonCegarLoop]: Abstraction has 3097 states and 4118 transitions. [2023-11-06 23:09:18,489 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3097 states and 4118 transitions. [2023-11-06 23:09:18,531 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3097 to 3097. [2023-11-06 23:09:18,538 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 3097 states, 3097 states have (on average 1.3296738779463997) internal successors, (4118), 3096 states have internal predecessors, (4118), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-06 23:09:18,549 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3097 states to 3097 states and 4118 transitions. [2023-11-06 23:09:18,550 INFO L240 hiAutomatonCegarLoop]: Abstraction has 3097 states and 4118 transitions. [2023-11-06 23:09:18,551 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-06 23:09:18,552 INFO L428 stractBuchiCegarLoop]: Abstraction has 3097 states and 4118 transitions. [2023-11-06 23:09:18,552 INFO L335 stractBuchiCegarLoop]: ======== Iteration 12 ============ [2023-11-06 23:09:18,552 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 3097 states and 4118 transitions. [2023-11-06 23:09:18,564 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 3046 [2023-11-06 23:09:18,564 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-06 23:09:18,564 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-06 23:09:18,565 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-06 23:09:18,565 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-06 23:09:18,565 INFO L748 eck$LassoCheckResult]: Stem: 21829#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2; 21830#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~4#1;havoc main_~__retres1~4#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1; 21845#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret12#1, start_simulation_#t~ret13#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 21842#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 21843#L221 assume 1 == ~m_i~0;~m_st~0 := 0; 21727#L221-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 21698#L226-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 21699#L231-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 21682#L334 assume !(0 == ~M_E~0); 21683#L334-2 assume !(0 == ~T1_E~0); 21798#L339-1 assume !(0 == ~T2_E~0); 21790#L344-1 assume !(0 == ~E_1~0); 21791#L349-1 assume !(0 == ~E_2~0); 21696#L354-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret8#1, activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 21697#L156 assume !(1 == ~m_pc~0); 21803#L156-2 is_master_triggered_~__retres1~0#1 := 0; 21819#L167 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 21813#is_master_triggered_returnLabel#1 activate_threads_#t~ret8#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 21754#L405 assume !(0 != activate_threads_~tmp~1#1); 21731#L405-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 21732#L175 assume !(1 == ~t1_pc~0); 21740#L175-2 is_transmit1_triggered_~__retres1~1#1 := 0; 21733#L186 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 21693#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret9#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 21694#L413 assume !(0 != activate_threads_~tmp___0~0#1); 21800#L413-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 21863#L194 assume !(1 == ~t2_pc~0); 21789#L194-2 is_transmit2_triggered_~__retres1~2#1 := 0; 21744#L205 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 21745#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret10#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 21671#L421 assume !(0 != activate_threads_~tmp___1~0#1); 21672#L421-2 havoc activate_threads_#t~ret8#1, activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 21641#L367 assume !(1 == ~M_E~0); 21642#L367-2 assume !(1 == ~T1_E~0); 21814#L372-1 assume !(1 == ~T2_E~0); 21815#L377-1 assume !(1 == ~E_1~0); 21668#L382-1 assume !(1 == ~E_2~0); 21669#L387-1 assume { :end_inline_reset_delta_events } true; 21757#L528-2 assume !false; 24527#L529 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 24525#L309-1 [2023-11-06 23:09:18,565 INFO L750 eck$LassoCheckResult]: Loop: 24525#L309-1 assume !false; 24523#L272 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 24520#L244 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 24519#L261 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 24518#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 24516#L276 assume 0 != eval_~tmp~0#1; 24514#L276-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;havoc eval_#t~nondet5#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet5#1;havoc eval_#t~nondet5#1; 21728#L284 assume !(0 != eval_~tmp_ndt_1~0#1); 21729#L284-2 havoc eval_~tmp_ndt_1~0#1; 24547#L281-1 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0#1;havoc eval_#t~nondet6#1;eval_~tmp_ndt_2~0#1 := eval_#t~nondet6#1;havoc eval_#t~nondet6#1; 24544#L298 assume !(0 != eval_~tmp_ndt_2~0#1); 24543#L298-2 havoc eval_~tmp_ndt_2~0#1; 21779#L295-1 assume 0 == ~t2_st~0;havoc eval_~tmp_ndt_3~0#1;havoc eval_#t~nondet7#1;eval_~tmp_ndt_3~0#1 := eval_#t~nondet7#1;havoc eval_#t~nondet7#1; 21780#L312 assume !(0 != eval_~tmp_ndt_3~0#1); 21807#L312-2 havoc eval_~tmp_ndt_3~0#1; 24525#L309-1 [2023-11-06 23:09:18,565 INFO L145 PredicateUnifier]: Initialized classic predicate unifier [2023-11-06 23:09:18,566 INFO L85 PathProgramCache]: Analyzing trace with hash -985920349, now seen corresponding path program 3 times [2023-11-06 23:09:18,566 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-06 23:09:18,566 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [179038694] [2023-11-06 23:09:18,566 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-06 23:09:18,567 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-06 23:09:18,581 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-06 23:09:18,581 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-06 23:09:18,585 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-06 23:09:18,595 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-06 23:09:18,597 INFO L145 PredicateUnifier]: Initialized classic predicate unifier [2023-11-06 23:09:18,597 INFO L85 PathProgramCache]: Analyzing trace with hash -851208175, now seen corresponding path program 1 times [2023-11-06 23:09:18,597 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-06 23:09:18,597 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [840520063] [2023-11-06 23:09:18,597 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-06 23:09:18,597 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-06 23:09:18,601 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-06 23:09:18,601 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-06 23:09:18,604 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-06 23:09:18,606 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-06 23:09:18,606 INFO L145 PredicateUnifier]: Initialized classic predicate unifier [2023-11-06 23:09:18,606 INFO L85 PathProgramCache]: Analyzing trace with hash -46370001, now seen corresponding path program 1 times [2023-11-06 23:09:18,606 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-06 23:09:18,607 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [444218466] [2023-11-06 23:09:18,607 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-06 23:09:18,607 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-06 23:09:18,619 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-06 23:09:18,619 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-06 23:09:18,624 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-06 23:09:18,629 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-06 23:09:19,473 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-06 23:09:19,474 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-06 23:09:19,489 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-06 23:09:19,625 INFO L201 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer CFG 06.11 11:09:19 BoogieIcfgContainer [2023-11-06 23:09:19,631 INFO L131 PluginConnector]: ------------------------ END BuchiAutomizer---------------------------- [2023-11-06 23:09:19,632 INFO L112 PluginConnector]: ------------------------Witness Printer---------------------------- [2023-11-06 23:09:19,633 INFO L270 PluginConnector]: Initializing Witness Printer... [2023-11-06 23:09:19,633 INFO L274 PluginConnector]: Witness Printer initialized [2023-11-06 23:09:19,633 INFO L184 PluginConnector]: Executing the observer RCFGCatcher from plugin Witness Printer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 06.11 11:09:15" (3/4) ... [2023-11-06 23:09:19,635 INFO L134 WitnessPrinter]: Generating witness for non-termination counterexample [2023-11-06 23:09:19,721 INFO L149 WitnessManager]: Wrote witness to /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_69caa52f-ede6-4d44-b7cb-879a059aaf8c/bin/uautomizer-verify-WvqO1wxjHP/witness.graphml.graphml [2023-11-06 23:09:19,722 INFO L131 PluginConnector]: ------------------------ END Witness Printer---------------------------- [2023-11-06 23:09:19,722 INFO L158 Benchmark]: Toolchain (without parser) took 6041.86ms. Allocated memory was 155.2MB in the beginning and 203.4MB in the end (delta: 48.2MB). Free memory was 118.5MB in the beginning and 109.8MB in the end (delta: 8.8MB). Peak memory consumption was 58.5MB. Max. memory is 16.1GB. [2023-11-06 23:09:19,723 INFO L158 Benchmark]: CDTParser took 0.57ms. Allocated memory is still 107.0MB. Free memory is still 55.5MB. There was no memory consumed. Max. memory is 16.1GB. [2023-11-06 23:09:19,723 INFO L158 Benchmark]: CACSL2BoogieTranslator took 330.25ms. Allocated memory is still 155.2MB. Free memory was 118.2MB in the beginning and 104.7MB in the end (delta: 13.5MB). Peak memory consumption was 14.7MB. Max. memory is 16.1GB. [2023-11-06 23:09:19,723 INFO L158 Benchmark]: Boogie Procedure Inliner took 54.34ms. Allocated memory is still 155.2MB. Free memory was 104.7MB in the beginning and 101.8MB in the end (delta: 2.9MB). Peak memory consumption was 2.1MB. Max. memory is 16.1GB. [2023-11-06 23:09:19,724 INFO L158 Benchmark]: Boogie Preprocessor took 45.75ms. Allocated memory is still 155.2MB. Free memory was 101.8MB in the beginning and 99.4MB in the end (delta: 2.4MB). Peak memory consumption was 2.1MB. Max. memory is 16.1GB. [2023-11-06 23:09:19,725 INFO L158 Benchmark]: RCFGBuilder took 899.21ms. Allocated memory is still 155.2MB. Free memory was 99.4MB in the beginning and 119.1MB in the end (delta: -19.6MB). Peak memory consumption was 26.9MB. Max. memory is 16.1GB. [2023-11-06 23:09:19,726 INFO L158 Benchmark]: BuchiAutomizer took 4617.26ms. Allocated memory was 155.2MB in the beginning and 203.4MB in the end (delta: 48.2MB). Free memory was 119.1MB in the beginning and 115.0MB in the end (delta: 4.1MB). Peak memory consumption was 52.6MB. Max. memory is 16.1GB. [2023-11-06 23:09:19,726 INFO L158 Benchmark]: Witness Printer took 89.25ms. Allocated memory is still 203.4MB. Free memory was 115.0MB in the beginning and 109.8MB in the end (delta: 5.2MB). Peak memory consumption was 4.2MB. Max. memory is 16.1GB. [2023-11-06 23:09:19,728 INFO L338 ainManager$Toolchain]: ####################### End [Toolchain 1] ####################### --- Results --- * Results from de.uni_freiburg.informatik.ultimate.core: - StatisticsResult: Toolchain Benchmarks Benchmark results are: * CDTParser took 0.57ms. Allocated memory is still 107.0MB. Free memory is still 55.5MB. There was no memory consumed. Max. memory is 16.1GB. * CACSL2BoogieTranslator took 330.25ms. Allocated memory is still 155.2MB. Free memory was 118.2MB in the beginning and 104.7MB in the end (delta: 13.5MB). Peak memory consumption was 14.7MB. Max. memory is 16.1GB. * Boogie Procedure Inliner took 54.34ms. Allocated memory is still 155.2MB. Free memory was 104.7MB in the beginning and 101.8MB in the end (delta: 2.9MB). Peak memory consumption was 2.1MB. Max. memory is 16.1GB. * Boogie Preprocessor took 45.75ms. Allocated memory is still 155.2MB. Free memory was 101.8MB in the beginning and 99.4MB in the end (delta: 2.4MB). Peak memory consumption was 2.1MB. Max. memory is 16.1GB. * RCFGBuilder took 899.21ms. Allocated memory is still 155.2MB. Free memory was 99.4MB in the beginning and 119.1MB in the end (delta: -19.6MB). Peak memory consumption was 26.9MB. Max. memory is 16.1GB. * BuchiAutomizer took 4617.26ms. Allocated memory was 155.2MB in the beginning and 203.4MB in the end (delta: 48.2MB). Free memory was 119.1MB in the beginning and 115.0MB in the end (delta: 4.1MB). Peak memory consumption was 52.6MB. Max. memory is 16.1GB. * Witness Printer took 89.25ms. Allocated memory is still 203.4MB. Free memory was 115.0MB in the beginning and 109.8MB in the end (delta: 5.2MB). Peak memory consumption was 4.2MB. Max. memory is 16.1GB. * Results from de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction: - StatisticsResult: Constructed decomposition of program Your program was decomposed into 11 terminating modules (11 trivial, 0 deterministic, 0 nondeterministic) and one nonterminating remainder module.11 modules have a trivial ranking function, the largest among these consists of 5 locations. The remainder module has 3097 locations. - StatisticsResult: Timing statistics BüchiAutomizer plugin needed 4.4s and 12 iterations. TraceHistogramMax:1. Analysis of lassos took 2.7s. Construction of modules took 0.3s. Büchi inclusion checks took 1.1s. Highest rank in rank-based complementation 0. Minimization of det autom 11. Minimization of nondet autom 0. Automata minimization 0.4s AutomataMinimizationTime, 11 MinimizatonAttempts, 1315 StatesRemovedByMinimization, 7 NontrivialMinimizations. Non-live state removal took 0.2s Buchi closure took 0.0s. Biggest automaton had -1 states and ocurred in iteration -1. Nontrivial modules had stage [0, 0, 0, 0, 0]. InterpolantCoveringCapabilityFinite: 0/0 InterpolantCoveringCapabilityBuchi: 0/0 HoareTripleCheckerStatistics: 0 mSolverCounterUnknown, 3876 SdHoareTripleChecker+Valid, 0.5s IncrementalHoareTripleChecker+Time, 0 mSdLazyCounter, 3876 mSDsluCounter, 6681 SdHoareTripleChecker+Invalid, 0.4s Time, 0 mProtectedAction, 0 SdHoareTripleChecker+Unchecked, 0 IncrementalHoareTripleChecker+Unchecked, 3296 mSDsCounter, 116 IncrementalHoareTripleChecker+Valid, 0 mProtectedPredicate, 326 IncrementalHoareTripleChecker+Invalid, 442 SdHoareTripleChecker+Unknown, 0 mSolverCounterNotChecked, 116 mSolverCounterUnsat, 3385 mSDtfsCounter, 326 mSolverCounterSat, 0.1s SdHoareTripleChecker+Time, 0 IncrementalHoareTripleChecker+Unknown LassoAnalysisResults: nont1 unkn0 SFLI3 SFLT0 conc2 concLT0 SILN1 SILU0 SILI5 SILT0 lasso0 LassoPreprocessingBenchmarks: LassoTerminationAnalysisBenchmarks: not availableLassoTerminationAnalysisBenchmarks: LassoNonterminationAnalysisSatFixpoint: 0 LassoNonterminationAnalysisSatUnbounded: 0 LassoNonterminationAnalysisUnsat: 0 LassoNonterminationAnalysisUnknown: 0 LassoNonterminationAnalysisTime: 0.0s InitialAbstractionConstructionTime: 0.0s - TerminationAnalysisResult: Nontermination possible Buchi Automizer proved that your program is nonterminating for some inputs - LassoShapedNonTerminationArgument [Line: 271]: Nontermination argument in form of an infinite program execution. Nontermination argument in form of an infinite program execution. Stem: [L25] int m_pc = 0; [L26] int t1_pc = 0; [L27] int t2_pc = 0; [L28] int m_st ; [L29] int t1_st ; [L30] int t2_st ; [L31] int m_i ; [L32] int t1_i ; [L33] int t2_i ; [L34] int M_E = 2; [L35] int T1_E = 2; [L36] int T2_E = 2; [L37] int E_1 = 2; [L38] int E_2 = 2; VAL [E_1=2, E_2=2, M_E=2, T1_E=2, T2_E=2, m_i=0, m_pc=0, m_st=0, t1_i=0, t1_pc=0, t1_st=0, t2_i=0, t2_pc=0, t2_st=0] [L573] int __retres1 ; [L577] CALL init_model() [L487] m_i = 1 [L488] t1_i = 1 [L489] t2_i = 1 VAL [E_1=2, E_2=2, M_E=2, T1_E=2, T2_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0] [L577] RET init_model() [L578] CALL start_simulation() [L514] int kernel_st ; [L515] int tmp ; [L516] int tmp___0 ; [L520] kernel_st = 0 [L521] FCALL update_channels() [L522] CALL init_threads() [L221] COND TRUE m_i == 1 [L222] m_st = 0 VAL [E_1=2, E_2=2, M_E=2, T1_E=2, T2_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0] [L226] COND TRUE t1_i == 1 [L227] t1_st = 0 VAL [E_1=2, E_2=2, M_E=2, T1_E=2, T2_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0] [L231] COND TRUE t2_i == 1 [L232] t2_st = 0 VAL [E_1=2, E_2=2, M_E=2, T1_E=2, T2_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0] [L522] RET init_threads() [L523] CALL fire_delta_events() [L334] COND FALSE !(M_E == 0) VAL [E_1=2, E_2=2, M_E=2, T1_E=2, T2_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0] [L339] COND FALSE !(T1_E == 0) VAL [E_1=2, E_2=2, M_E=2, T1_E=2, T2_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0] [L344] COND FALSE !(T2_E == 0) VAL [E_1=2, E_2=2, M_E=2, T1_E=2, T2_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0] [L349] COND FALSE !(E_1 == 0) VAL [E_1=2, E_2=2, M_E=2, T1_E=2, T2_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0] [L354] COND FALSE !(E_2 == 0) VAL [E_1=2, E_2=2, M_E=2, T1_E=2, T2_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0] [L523] RET fire_delta_events() [L524] CALL activate_threads() [L397] int tmp ; [L398] int tmp___0 ; [L399] int tmp___1 ; [L403] CALL, EXPR is_master_triggered() [L153] int __retres1 ; VAL [E_1=2, E_2=2, M_E=2, T1_E=2, T2_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0] [L156] COND FALSE !(m_pc == 1) VAL [E_1=2, E_2=2, M_E=2, T1_E=2, T2_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0] [L166] __retres1 = 0 VAL [E_1=2, E_2=2, M_E=2, T1_E=2, T2_E=2, __retres1=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0] [L168] return (__retres1); VAL [E_1=2, E_2=2, M_E=2, T1_E=2, T2_E=2, \result=0, __retres1=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0] [L403] RET, EXPR is_master_triggered() [L403] tmp = is_master_triggered() [L405] COND FALSE !(\read(tmp)) VAL [E_1=2, E_2=2, M_E=2, T1_E=2, T2_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, tmp=0] [L411] CALL, EXPR is_transmit1_triggered() [L172] int __retres1 ; VAL [E_1=2, E_2=2, M_E=2, T1_E=2, T2_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0] [L175] COND FALSE !(t1_pc == 1) VAL [E_1=2, E_2=2, M_E=2, T1_E=2, T2_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0] [L185] __retres1 = 0 VAL [E_1=2, E_2=2, M_E=2, T1_E=2, T2_E=2, __retres1=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0] [L187] return (__retres1); VAL [E_1=2, E_2=2, M_E=2, T1_E=2, T2_E=2, \result=0, __retres1=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0] [L411] RET, EXPR is_transmit1_triggered() [L411] tmp___0 = is_transmit1_triggered() [L413] COND FALSE !(\read(tmp___0)) VAL [E_1=2, E_2=2, M_E=2, T1_E=2, T2_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, tmp=0, tmp___0=0] [L419] CALL, EXPR is_transmit2_triggered() [L191] int __retres1 ; VAL [E_1=2, E_2=2, M_E=2, T1_E=2, T2_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0] [L194] COND FALSE !(t2_pc == 1) VAL [E_1=2, E_2=2, M_E=2, T1_E=2, T2_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0] [L204] __retres1 = 0 VAL [E_1=2, E_2=2, M_E=2, T1_E=2, T2_E=2, __retres1=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0] [L206] return (__retres1); VAL [E_1=2, E_2=2, M_E=2, T1_E=2, T2_E=2, \result=0, __retres1=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0] [L419] RET, EXPR is_transmit2_triggered() [L419] tmp___1 = is_transmit2_triggered() [L421] COND FALSE !(\read(tmp___1)) VAL [E_1=2, E_2=2, M_E=2, T1_E=2, T2_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, tmp=0, tmp___0=0, tmp___1=0] [L524] RET activate_threads() [L525] CALL reset_delta_events() [L367] COND FALSE !(M_E == 1) VAL [E_1=2, E_2=2, M_E=2, T1_E=2, T2_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0] [L372] COND FALSE !(T1_E == 1) VAL [E_1=2, E_2=2, M_E=2, T1_E=2, T2_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0] [L377] COND FALSE !(T2_E == 1) VAL [E_1=2, E_2=2, M_E=2, T1_E=2, T2_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0] [L382] COND FALSE !(E_1 == 1) VAL [E_1=2, E_2=2, M_E=2, T1_E=2, T2_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0] [L387] COND FALSE !(E_2 == 1) VAL [E_1=2, E_2=2, M_E=2, T1_E=2, T2_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0] [L525] RET reset_delta_events() [L528] COND TRUE 1 VAL [E_1=2, E_2=2, M_E=2, T1_E=2, T2_E=2, kernel_st=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0] [L531] kernel_st = 1 [L532] CALL eval() [L267] int tmp ; VAL [E_1=2, E_2=2, M_E=2, T1_E=2, T2_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0] Loop: [L271] COND TRUE 1 [L274] CALL, EXPR exists_runnable_thread() [L241] int __retres1 ; [L244] COND TRUE m_st == 0 [L245] __retres1 = 1 [L262] return (__retres1); [L274] RET, EXPR exists_runnable_thread() [L274] tmp = exists_runnable_thread() [L276] COND TRUE \read(tmp) [L281] COND TRUE m_st == 0 [L282] int tmp_ndt_1; [L283] EXPR tmp_ndt_1 = __VERIFIER_nondet_int() [L284] COND FALSE, EXPR !(\read(tmp_ndt_1)) [L281-L292] { int tmp_ndt_1; tmp_ndt_1 = __VERIFIER_nondet_int(); if (tmp_ndt_1) { { m_st = 1; master(); } } else { } } [L295] COND TRUE t1_st == 0 [L296] int tmp_ndt_2; [L297] EXPR tmp_ndt_2 = __VERIFIER_nondet_int() [L298] COND FALSE, EXPR !(\read(tmp_ndt_2)) [L295-L306] { int tmp_ndt_2; tmp_ndt_2 = __VERIFIER_nondet_int(); if (tmp_ndt_2) { { t1_st = 1; transmit1(); } } else { } } [L309] COND TRUE t2_st == 0 [L310] int tmp_ndt_3; [L311] EXPR tmp_ndt_3 = __VERIFIER_nondet_int() [L312] COND FALSE, EXPR !(\read(tmp_ndt_3)) [L309-L320] { int tmp_ndt_3; tmp_ndt_3 = __VERIFIER_nondet_int(); if (tmp_ndt_3) { { t2_st = 1; transmit2(); } } else { } } End of lasso representation. - StatisticsResult: NonterminationArgumentStatistics Fixpoint - NonterminatingLassoResult [Line: 271]: Nonterminating execution Found a nonterminating execution for the following lasso shaped sequence of statements. Stem: [L25] int m_pc = 0; [L26] int t1_pc = 0; [L27] int t2_pc = 0; [L28] int m_st ; [L29] int t1_st ; [L30] int t2_st ; [L31] int m_i ; [L32] int t1_i ; [L33] int t2_i ; [L34] int M_E = 2; [L35] int T1_E = 2; [L36] int T2_E = 2; [L37] int E_1 = 2; [L38] int E_2 = 2; VAL [E_1=2, E_2=2, M_E=2, T1_E=2, T2_E=2, m_i=0, m_pc=0, m_st=0, t1_i=0, t1_pc=0, t1_st=0, t2_i=0, t2_pc=0, t2_st=0] [L573] int __retres1 ; [L577] CALL init_model() [L487] m_i = 1 [L488] t1_i = 1 [L489] t2_i = 1 VAL [E_1=2, E_2=2, M_E=2, T1_E=2, T2_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0] [L577] RET init_model() [L578] CALL start_simulation() [L514] int kernel_st ; [L515] int tmp ; [L516] int tmp___0 ; [L520] kernel_st = 0 [L521] FCALL update_channels() [L522] CALL init_threads() [L221] COND TRUE m_i == 1 [L222] m_st = 0 VAL [E_1=2, E_2=2, M_E=2, T1_E=2, T2_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0] [L226] COND TRUE t1_i == 1 [L227] t1_st = 0 VAL [E_1=2, E_2=2, M_E=2, T1_E=2, T2_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0] [L231] COND TRUE t2_i == 1 [L232] t2_st = 0 VAL [E_1=2, E_2=2, M_E=2, T1_E=2, T2_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0] [L522] RET init_threads() [L523] CALL fire_delta_events() [L334] COND FALSE !(M_E == 0) VAL [E_1=2, E_2=2, M_E=2, T1_E=2, T2_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0] [L339] COND FALSE !(T1_E == 0) VAL [E_1=2, E_2=2, M_E=2, T1_E=2, T2_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0] [L344] COND FALSE !(T2_E == 0) VAL [E_1=2, E_2=2, M_E=2, T1_E=2, T2_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0] [L349] COND FALSE !(E_1 == 0) VAL [E_1=2, E_2=2, M_E=2, T1_E=2, T2_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0] [L354] COND FALSE !(E_2 == 0) VAL [E_1=2, E_2=2, M_E=2, T1_E=2, T2_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0] [L523] RET fire_delta_events() [L524] CALL activate_threads() [L397] int tmp ; [L398] int tmp___0 ; [L399] int tmp___1 ; [L403] CALL, EXPR is_master_triggered() [L153] int __retres1 ; VAL [E_1=2, E_2=2, M_E=2, T1_E=2, T2_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0] [L156] COND FALSE !(m_pc == 1) VAL [E_1=2, E_2=2, M_E=2, T1_E=2, T2_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0] [L166] __retres1 = 0 VAL [E_1=2, E_2=2, M_E=2, T1_E=2, T2_E=2, __retres1=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0] [L168] return (__retres1); VAL [E_1=2, E_2=2, M_E=2, T1_E=2, T2_E=2, \result=0, __retres1=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0] [L403] RET, EXPR is_master_triggered() [L403] tmp = is_master_triggered() [L405] COND FALSE !(\read(tmp)) VAL [E_1=2, E_2=2, M_E=2, T1_E=2, T2_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, tmp=0] [L411] CALL, EXPR is_transmit1_triggered() [L172] int __retres1 ; VAL [E_1=2, E_2=2, M_E=2, T1_E=2, T2_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0] [L175] COND FALSE !(t1_pc == 1) VAL [E_1=2, E_2=2, M_E=2, T1_E=2, T2_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0] [L185] __retres1 = 0 VAL [E_1=2, E_2=2, M_E=2, T1_E=2, T2_E=2, __retres1=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0] [L187] return (__retres1); VAL [E_1=2, E_2=2, M_E=2, T1_E=2, T2_E=2, \result=0, __retres1=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0] [L411] RET, EXPR is_transmit1_triggered() [L411] tmp___0 = is_transmit1_triggered() [L413] COND FALSE !(\read(tmp___0)) VAL [E_1=2, E_2=2, M_E=2, T1_E=2, T2_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, tmp=0, tmp___0=0] [L419] CALL, EXPR is_transmit2_triggered() [L191] int __retres1 ; VAL [E_1=2, E_2=2, M_E=2, T1_E=2, T2_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0] [L194] COND FALSE !(t2_pc == 1) VAL [E_1=2, E_2=2, M_E=2, T1_E=2, T2_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0] [L204] __retres1 = 0 VAL [E_1=2, E_2=2, M_E=2, T1_E=2, T2_E=2, __retres1=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0] [L206] return (__retres1); VAL [E_1=2, E_2=2, M_E=2, T1_E=2, T2_E=2, \result=0, __retres1=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0] [L419] RET, EXPR is_transmit2_triggered() [L419] tmp___1 = is_transmit2_triggered() [L421] COND FALSE !(\read(tmp___1)) VAL [E_1=2, E_2=2, M_E=2, T1_E=2, T2_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, tmp=0, tmp___0=0, tmp___1=0] [L524] RET activate_threads() [L525] CALL reset_delta_events() [L367] COND FALSE !(M_E == 1) VAL [E_1=2, E_2=2, M_E=2, T1_E=2, T2_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0] [L372] COND FALSE !(T1_E == 1) VAL [E_1=2, E_2=2, M_E=2, T1_E=2, T2_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0] [L377] COND FALSE !(T2_E == 1) VAL [E_1=2, E_2=2, M_E=2, T1_E=2, T2_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0] [L382] COND FALSE !(E_1 == 1) VAL [E_1=2, E_2=2, M_E=2, T1_E=2, T2_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0] [L387] COND FALSE !(E_2 == 1) VAL [E_1=2, E_2=2, M_E=2, T1_E=2, T2_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0] [L525] RET reset_delta_events() [L528] COND TRUE 1 VAL [E_1=2, E_2=2, M_E=2, T1_E=2, T2_E=2, kernel_st=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0] [L531] kernel_st = 1 [L532] CALL eval() [L267] int tmp ; VAL [E_1=2, E_2=2, M_E=2, T1_E=2, T2_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0] Loop: [L271] COND TRUE 1 [L274] CALL, EXPR exists_runnable_thread() [L241] int __retres1 ; [L244] COND TRUE m_st == 0 [L245] __retres1 = 1 [L262] return (__retres1); [L274] RET, EXPR exists_runnable_thread() [L274] tmp = exists_runnable_thread() [L276] COND TRUE \read(tmp) [L281] COND TRUE m_st == 0 [L282] int tmp_ndt_1; [L283] EXPR tmp_ndt_1 = __VERIFIER_nondet_int() [L284] COND FALSE, EXPR !(\read(tmp_ndt_1)) [L281-L292] { int tmp_ndt_1; tmp_ndt_1 = __VERIFIER_nondet_int(); if (tmp_ndt_1) { { m_st = 1; master(); } } else { } } [L295] COND TRUE t1_st == 0 [L296] int tmp_ndt_2; [L297] EXPR tmp_ndt_2 = __VERIFIER_nondet_int() [L298] COND FALSE, EXPR !(\read(tmp_ndt_2)) [L295-L306] { int tmp_ndt_2; tmp_ndt_2 = __VERIFIER_nondet_int(); if (tmp_ndt_2) { { t1_st = 1; transmit1(); } } else { } } [L309] COND TRUE t2_st == 0 [L310] int tmp_ndt_3; [L311] EXPR tmp_ndt_3 = __VERIFIER_nondet_int() [L312] COND FALSE, EXPR !(\read(tmp_ndt_3)) [L309-L320] { int tmp_ndt_3; tmp_ndt_3 = __VERIFIER_nondet_int(); if (tmp_ndt_3) { { t2_st = 1; transmit2(); } } else { } } End of lasso representation. RESULT: Ultimate proved your program to be incorrect! [2023-11-06 23:09:19,810 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_69caa52f-ede6-4d44-b7cb-879a059aaf8c/bin/uautomizer-verify-WvqO1wxjHP/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (1)] Forceful destruction successful, exit code 0 Received shutdown request... --- End real Ultimate output --- Execution finished normally Writing output log to file Ultimate.log Writing human readable error path to file UltimateCounterExample.errorpath Result: FALSE(TERM)