./Ultimate.py --spec ../../sv-benchmarks/c/properties/termination.prp --file ../../sv-benchmarks/c/systemc/transmitter.05.cil.c --full-output --architecture 32bit -------------------------------------------------------------------------------- Checking for termination Using default analysis Version e7bb482b Calling Ultimate with: /usr/lib/jvm/java-11-openjdk-amd64/bin/java -Dosgi.configuration.area=/tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_0e04129a-54f6-4cb3-8369-3da3b1f77b7c/bin/uautomizer-verify-WvqO1wxjHP/data/config -Xmx15G -Xms4m -jar /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_0e04129a-54f6-4cb3-8369-3da3b1f77b7c/bin/uautomizer-verify-WvqO1wxjHP/plugins/org.eclipse.equinox.launcher_1.5.800.v20200727-1323.jar -data @noDefault -ultimatedata /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_0e04129a-54f6-4cb3-8369-3da3b1f77b7c/bin/uautomizer-verify-WvqO1wxjHP/data -tc /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_0e04129a-54f6-4cb3-8369-3da3b1f77b7c/bin/uautomizer-verify-WvqO1wxjHP/config/AutomizerTermination.xml -i ../../sv-benchmarks/c/systemc/transmitter.05.cil.c -s /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_0e04129a-54f6-4cb3-8369-3da3b1f77b7c/bin/uautomizer-verify-WvqO1wxjHP/config/svcomp-Termination-32bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_0e04129a-54f6-4cb3-8369-3da3b1f77b7c/bin/uautomizer-verify-WvqO1wxjHP --witnessprinter.witness.filename witness.graphml --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(F end) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 32bit --witnessprinter.graph.data.programhash d8722862ca37b1ee13dec8b9e420cd40ba7901837b8f3b6258499da6e8a2ca6f --- Real Ultimate output --- This is Ultimate 0.2.3-dev-e7bb482 [2023-11-06 22:25:50,330 INFO L188 SettingsManager]: Resetting all preferences to default values... [2023-11-06 22:25:50,460 INFO L114 SettingsManager]: Loading settings from /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_0e04129a-54f6-4cb3-8369-3da3b1f77b7c/bin/uautomizer-verify-WvqO1wxjHP/config/svcomp-Termination-32bit-Automizer_Default.epf [2023-11-06 22:25:50,471 WARN L101 SettingsManager]: Preference file contains the following unknown settings: [2023-11-06 22:25:50,472 WARN L103 SettingsManager]: * de.uni_freiburg.informatik.ultimate.core.Log level for class [2023-11-06 22:25:50,517 INFO L130 SettingsManager]: Preferences different from defaults after loading the file: [2023-11-06 22:25:50,518 INFO L151 SettingsManager]: Preferences of UltimateCore differ from their defaults: [2023-11-06 22:25:50,519 INFO L153 SettingsManager]: * Log level for class=de.uni_freiburg.informatik.ultimate.lib.smtlibutils.quantifier.QuantifierPusher=ERROR; [2023-11-06 22:25:50,520 INFO L151 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2023-11-06 22:25:50,527 INFO L153 SettingsManager]: * Create parallel compositions if possible=false [2023-11-06 22:25:50,528 INFO L153 SettingsManager]: * Use SBE=true [2023-11-06 22:25:50,529 INFO L151 SettingsManager]: Preferences of BuchiAutomizer differ from their defaults: [2023-11-06 22:25:50,530 INFO L153 SettingsManager]: * NCSB implementation=INTSET_LAZY3 [2023-11-06 22:25:50,532 INFO L153 SettingsManager]: * Use old map elimination=false [2023-11-06 22:25:50,533 INFO L153 SettingsManager]: * Use external solver (rank synthesis)=false [2023-11-06 22:25:50,533 INFO L153 SettingsManager]: * Use only trivial implications for array writes=true [2023-11-06 22:25:50,534 INFO L153 SettingsManager]: * Rank analysis=LINEAR_WITH_GUESSES [2023-11-06 22:25:50,535 INFO L151 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2023-11-06 22:25:50,536 INFO L153 SettingsManager]: * Pointer base address is valid at dereference=ASSUME [2023-11-06 22:25:50,536 INFO L153 SettingsManager]: * sizeof long=4 [2023-11-06 22:25:50,537 INFO L153 SettingsManager]: * Overapproximate operations on floating types=true [2023-11-06 22:25:50,538 INFO L153 SettingsManager]: * sizeof POINTER=4 [2023-11-06 22:25:50,538 INFO L153 SettingsManager]: * Check division by zero=IGNORE [2023-11-06 22:25:50,539 INFO L153 SettingsManager]: * Pointer to allocated memory at dereference=ASSUME [2023-11-06 22:25:50,539 INFO L153 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=ASSUME [2023-11-06 22:25:50,540 INFO L153 SettingsManager]: * Check array bounds for arrays that are off heap=ASSUME [2023-11-06 22:25:50,540 INFO L153 SettingsManager]: * Check unreachability of reach_error function=false [2023-11-06 22:25:50,541 INFO L153 SettingsManager]: * sizeof long double=12 [2023-11-06 22:25:50,542 INFO L153 SettingsManager]: * Check if freed pointer was valid=false [2023-11-06 22:25:50,542 INFO L153 SettingsManager]: * Assume nondeterminstic values are in range=false [2023-11-06 22:25:50,544 INFO L153 SettingsManager]: * Use constant arrays=true [2023-11-06 22:25:50,544 INFO L151 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2023-11-06 22:25:50,545 INFO L153 SettingsManager]: * Size of a code block=SequenceOfStatements [2023-11-06 22:25:50,546 INFO L151 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2023-11-06 22:25:50,546 INFO L153 SettingsManager]: * Trace refinement strategy=CAMEL [2023-11-06 22:25:50,547 INFO L151 SettingsManager]: Preferences of IcfgTransformer differ from their defaults: [2023-11-06 22:25:50,547 INFO L153 SettingsManager]: * TransformationType=MODULO_NEIGHBOR WARNING: An illegal reflective access operation has occurred WARNING: Illegal reflective access by com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 (file:/tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_0e04129a-54f6-4cb3-8369-3da3b1f77b7c/bin/uautomizer-verify-WvqO1wxjHP/plugins/com.sun.xml.bind_2.2.0.v201505121915.jar) to method java.lang.ClassLoader.defineClass(java.lang.String,byte[],int,int) WARNING: Please consider reporting this to the maintainers of com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 WARNING: Use --illegal-access=warn to enable warnings of further illegal reflective access operations WARNING: All illegal access operations will be denied in a future release Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_0e04129a-54f6-4cb3-8369-3da3b1f77b7c/bin/uautomizer-verify-WvqO1wxjHP Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness.graphml Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(F end) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 32bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> d8722862ca37b1ee13dec8b9e420cd40ba7901837b8f3b6258499da6e8a2ca6f [2023-11-06 22:25:50,916 INFO L75 nceAwareModelManager]: Repository-Root is: /tmp [2023-11-06 22:25:50,949 INFO L261 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2023-11-06 22:25:50,952 INFO L217 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2023-11-06 22:25:50,955 INFO L270 PluginConnector]: Initializing CDTParser... [2023-11-06 22:25:50,956 INFO L274 PluginConnector]: CDTParser initialized [2023-11-06 22:25:50,958 INFO L431 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_0e04129a-54f6-4cb3-8369-3da3b1f77b7c/bin/uautomizer-verify-WvqO1wxjHP/../../sv-benchmarks/c/systemc/transmitter.05.cil.c [2023-11-06 22:25:54,478 INFO L533 CDTParser]: Created temporary CDT project at NULL [2023-11-06 22:25:54,787 INFO L384 CDTParser]: Found 1 translation units. [2023-11-06 22:25:54,797 INFO L180 CDTParser]: Scanning /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_0e04129a-54f6-4cb3-8369-3da3b1f77b7c/sv-benchmarks/c/systemc/transmitter.05.cil.c [2023-11-06 22:25:54,819 INFO L427 CDTParser]: About to delete temporary CDT project at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_0e04129a-54f6-4cb3-8369-3da3b1f77b7c/bin/uautomizer-verify-WvqO1wxjHP/data/d0a375b51/c045eb084da248d095708da6eb6c1015/FLAG6bc44bd88 [2023-11-06 22:25:54,838 INFO L435 CDTParser]: Successfully deleted /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_0e04129a-54f6-4cb3-8369-3da3b1f77b7c/bin/uautomizer-verify-WvqO1wxjHP/data/d0a375b51/c045eb084da248d095708da6eb6c1015 [2023-11-06 22:25:54,845 INFO L299 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2023-11-06 22:25:54,846 INFO L133 ToolchainWalker]: Walking toolchain with 6 elements. [2023-11-06 22:25:54,850 INFO L112 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2023-11-06 22:25:54,851 INFO L270 PluginConnector]: Initializing CACSL2BoogieTranslator... [2023-11-06 22:25:54,857 INFO L274 PluginConnector]: CACSL2BoogieTranslator initialized [2023-11-06 22:25:54,858 INFO L184 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 06.11 10:25:54" (1/1) ... [2023-11-06 22:25:54,859 INFO L204 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@25684442 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.11 10:25:54, skipping insertion in model container [2023-11-06 22:25:54,860 INFO L184 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 06.11 10:25:54" (1/1) ... [2023-11-06 22:25:54,929 INFO L177 MainTranslator]: Built tables and reachable declarations [2023-11-06 22:25:55,260 INFO L209 PostProcessor]: Analyzing one entry point: main [2023-11-06 22:25:55,280 INFO L202 MainTranslator]: Completed pre-run [2023-11-06 22:25:55,331 INFO L209 PostProcessor]: Analyzing one entry point: main [2023-11-06 22:25:55,351 INFO L206 MainTranslator]: Completed translation [2023-11-06 22:25:55,352 INFO L201 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.11 10:25:55 WrapperNode [2023-11-06 22:25:55,352 INFO L131 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2023-11-06 22:25:55,353 INFO L112 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2023-11-06 22:25:55,353 INFO L270 PluginConnector]: Initializing Boogie Procedure Inliner... [2023-11-06 22:25:55,353 INFO L274 PluginConnector]: Boogie Procedure Inliner initialized [2023-11-06 22:25:55,361 INFO L184 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.11 10:25:55" (1/1) ... [2023-11-06 22:25:55,372 INFO L184 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.11 10:25:55" (1/1) ... [2023-11-06 22:25:55,426 INFO L138 Inliner]: procedures = 38, calls = 46, calls flagged for inlining = 41, calls inlined = 87, statements flattened = 1241 [2023-11-06 22:25:55,427 INFO L131 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2023-11-06 22:25:55,427 INFO L112 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2023-11-06 22:25:55,428 INFO L270 PluginConnector]: Initializing Boogie Preprocessor... [2023-11-06 22:25:55,428 INFO L274 PluginConnector]: Boogie Preprocessor initialized [2023-11-06 22:25:55,438 INFO L184 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.11 10:25:55" (1/1) ... [2023-11-06 22:25:55,439 INFO L184 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.11 10:25:55" (1/1) ... [2023-11-06 22:25:55,446 INFO L184 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.11 10:25:55" (1/1) ... [2023-11-06 22:25:55,447 INFO L184 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.11 10:25:55" (1/1) ... [2023-11-06 22:25:55,479 INFO L184 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.11 10:25:55" (1/1) ... [2023-11-06 22:25:55,497 INFO L184 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.11 10:25:55" (1/1) ... [2023-11-06 22:25:55,517 INFO L184 PluginConnector]: Executing the observer LTLStepAnnotator from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.11 10:25:55" (1/1) ... [2023-11-06 22:25:55,523 INFO L184 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.11 10:25:55" (1/1) ... [2023-11-06 22:25:55,542 INFO L131 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2023-11-06 22:25:55,543 INFO L112 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2023-11-06 22:25:55,543 INFO L270 PluginConnector]: Initializing RCFGBuilder... [2023-11-06 22:25:55,544 INFO L274 PluginConnector]: RCFGBuilder initialized [2023-11-06 22:25:55,545 INFO L184 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.11 10:25:55" (1/1) ... [2023-11-06 22:25:55,557 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2023-11-06 22:25:55,575 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_0e04129a-54f6-4cb3-8369-3da3b1f77b7c/bin/uautomizer-verify-WvqO1wxjHP/z3 [2023-11-06 22:25:55,594 INFO L229 MonitoredProcess]: Starting monitored process 1 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_0e04129a-54f6-4cb3-8369-3da3b1f77b7c/bin/uautomizer-verify-WvqO1wxjHP/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2023-11-06 22:25:55,624 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_0e04129a-54f6-4cb3-8369-3da3b1f77b7c/bin/uautomizer-verify-WvqO1wxjHP/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (1)] Waiting until timeout for monitored process [2023-11-06 22:25:55,652 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocInit [2023-11-06 22:25:55,653 INFO L130 BoogieDeclarations]: Found specification of procedure write~init~int [2023-11-06 22:25:55,653 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2023-11-06 22:25:55,654 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2023-11-06 22:25:55,788 INFO L236 CfgBuilder]: Building ICFG [2023-11-06 22:25:55,791 INFO L262 CfgBuilder]: Building CFG for each procedure with an implementation [2023-11-06 22:25:56,979 INFO L277 CfgBuilder]: Performing block encoding [2023-11-06 22:25:57,008 INFO L297 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2023-11-06 22:25:57,009 INFO L302 CfgBuilder]: Removed 9 assume(true) statements. [2023-11-06 22:25:57,014 INFO L201 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 06.11 10:25:57 BoogieIcfgContainer [2023-11-06 22:25:57,014 INFO L131 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2023-11-06 22:25:57,016 INFO L112 PluginConnector]: ------------------------BuchiAutomizer---------------------------- [2023-11-06 22:25:57,016 INFO L270 PluginConnector]: Initializing BuchiAutomizer... [2023-11-06 22:25:57,020 INFO L274 PluginConnector]: BuchiAutomizer initialized [2023-11-06 22:25:57,021 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2023-11-06 22:25:57,022 INFO L184 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "CDTParser AST 06.11 10:25:54" (1/3) ... [2023-11-06 22:25:57,023 INFO L204 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@206600c and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 06.11 10:25:57, skipping insertion in model container [2023-11-06 22:25:57,023 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2023-11-06 22:25:57,024 INFO L184 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.11 10:25:55" (2/3) ... [2023-11-06 22:25:57,026 INFO L204 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@206600c and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 06.11 10:25:57, skipping insertion in model container [2023-11-06 22:25:57,027 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2023-11-06 22:25:57,027 INFO L184 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 06.11 10:25:57" (3/3) ... [2023-11-06 22:25:57,032 INFO L332 chiAutomizerObserver]: Analyzing ICFG transmitter.05.cil.c [2023-11-06 22:25:57,179 INFO L303 stractBuchiCegarLoop]: Interprodecural is true [2023-11-06 22:25:57,182 INFO L304 stractBuchiCegarLoop]: Hoare is false [2023-11-06 22:25:57,183 INFO L305 stractBuchiCegarLoop]: Compute interpolants for ForwardPredicates [2023-11-06 22:25:57,184 INFO L306 stractBuchiCegarLoop]: Backedges is STRAIGHT_LINE [2023-11-06 22:25:57,184 INFO L307 stractBuchiCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2023-11-06 22:25:57,184 INFO L308 stractBuchiCegarLoop]: Difference is false [2023-11-06 22:25:57,184 INFO L309 stractBuchiCegarLoop]: Minimize is MINIMIZE_SEVPA [2023-11-06 22:25:57,185 INFO L313 stractBuchiCegarLoop]: ======== Iteration 0 == of CEGAR loop == BuchiAutomatonCegarLoop ======== [2023-11-06 22:25:57,198 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 512 states, 511 states have (on average 1.5264187866927592) internal successors, (780), 511 states have internal predecessors, (780), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-06 22:25:57,261 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 431 [2023-11-06 22:25:57,262 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-06 22:25:57,262 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-06 22:25:57,275 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-06 22:25:57,276 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-06 22:25:57,276 INFO L335 stractBuchiCegarLoop]: ======== Iteration 1 ============ [2023-11-06 22:25:57,278 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 512 states, 511 states have (on average 1.5264187866927592) internal successors, (780), 511 states have internal predecessors, (780), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-06 22:25:57,298 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 431 [2023-11-06 22:25:57,299 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-06 22:25:57,299 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-06 22:25:57,303 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-06 22:25:57,303 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-06 22:25:57,314 INFO L748 eck$LassoCheckResult]: Stem: 151#$Ultimate##0true assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2; 412#L-1true assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~7#1;havoc main_~__retres1~7#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 243#init_model_returnLabel#1true assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret18#1, start_simulation_#t~ret19#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 409#update_channels_returnLabel#1true assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 257#L401true assume !(1 == ~m_i~0);~m_st~0 := 2; 348#L401-2true assume 1 == ~t1_i~0;~t1_st~0 := 0; 114#L406-1true assume !(1 == ~t2_i~0);~t2_st~0 := 2; 402#L411-1true assume !(1 == ~t3_i~0);~t3_st~0 := 2; 389#L416-1true assume !(1 == ~t4_i~0);~t4_st~0 := 2; 467#L421-1true assume !(1 == ~t5_i~0);~t5_st~0 := 2; 330#L426-1true assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 93#L586true assume 0 == ~M_E~0;~M_E~0 := 1; 125#L586-2true assume !(0 == ~T1_E~0); 232#L591-1true assume !(0 == ~T2_E~0); 207#L596-1true assume !(0 == ~T3_E~0); 273#L601-1true assume !(0 == ~T4_E~0); 249#L606-1true assume !(0 == ~T5_E~0); 471#L611-1true assume !(0 == ~E_1~0); 347#L616-1true assume !(0 == ~E_2~0); 353#L621-1true assume 0 == ~E_3~0;~E_3~0 := 1; 49#L626-1true assume !(0 == ~E_4~0); 304#L631-1true assume !(0 == ~E_5~0); 147#L636-1true assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 47#L279true assume 1 == ~m_pc~0; 215#L280true assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 371#L290true is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 131#is_master_triggered_returnLabel#1true activate_threads_#t~ret11#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 272#L720true assume !(0 != activate_threads_~tmp~1#1); 493#L720-2true assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 152#L298true assume !(1 == ~t1_pc~0); 21#L298-2true is_transmit1_triggered_~__retres1~1#1 := 0; 457#L309true is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 33#is_transmit1_triggered_returnLabel#1true activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 54#L728true assume !(0 != activate_threads_~tmp___0~0#1); 264#L728-2true assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 128#L317true assume 1 == ~t2_pc~0; 240#L318true assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 475#L328true is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 246#is_transmit2_triggered_returnLabel#1true activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 157#L736true assume !(0 != activate_threads_~tmp___1~0#1); 424#L736-2true assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 326#L336true assume 1 == ~t3_pc~0; 188#L337true assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 494#L347true is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 9#is_transmit3_triggered_returnLabel#1true activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 281#L744true assume !(0 != activate_threads_~tmp___2~0#1); 337#L744-2true assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 403#L355true assume !(1 == ~t4_pc~0); 335#L355-2true is_transmit4_triggered_~__retres1~4#1 := 0; 106#L366true is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 71#is_transmit4_triggered_returnLabel#1true activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 318#L752true assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 61#L752-2true assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 375#L374true assume 1 == ~t5_pc~0; 387#L375true assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 390#L385true is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 135#is_transmit5_triggered_returnLabel#1true activate_threads_#t~ret16#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 430#L760true assume !(0 != activate_threads_~tmp___4~0#1); 234#L760-2true havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 438#L649true assume 1 == ~M_E~0;~M_E~0 := 2; 499#L649-2true assume !(1 == ~T1_E~0); 39#L654-1true assume !(1 == ~T2_E~0); 269#L659-1true assume !(1 == ~T3_E~0); 156#L664-1true assume !(1 == ~T4_E~0); 35#L669-1true assume !(1 == ~T5_E~0); 320#L674-1true assume !(1 == ~E_1~0); 333#L679-1true assume !(1 == ~E_2~0); 96#L684-1true assume 1 == ~E_3~0;~E_3~0 := 2; 202#L689-1true assume !(1 == ~E_4~0); 490#L694-1true assume !(1 == ~E_5~0); 201#L699-1true assume { :end_inline_reset_delta_events } true; 480#L900-2true [2023-11-06 22:25:57,317 INFO L750 eck$LassoCheckResult]: Loop: 480#L900-2true assume !false; 508#L901true start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 212#L561-1true assume false; 75#eval_returnLabel#1true havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 363#update_channels_returnLabel#2true assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 425#L586-3true assume 0 == ~M_E~0;~M_E~0 := 1; 319#L586-5true assume 0 == ~T1_E~0;~T1_E~0 := 1; 218#L591-3true assume 0 == ~T2_E~0;~T2_E~0 := 1; 109#L596-3true assume 0 == ~T3_E~0;~T3_E~0 := 1; 229#L601-3true assume 0 == ~T4_E~0;~T4_E~0 := 1; 377#L606-3true assume !(0 == ~T5_E~0); 261#L611-3true assume 0 == ~E_1~0;~E_1~0 := 1; 265#L616-3true assume 0 == ~E_2~0;~E_2~0 := 1; 43#L621-3true assume 0 == ~E_3~0;~E_3~0 := 1; 20#L626-3true assume 0 == ~E_4~0;~E_4~0 := 1; 509#L631-3true assume 0 == ~E_5~0;~E_5~0 := 1; 23#L636-3true assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 435#L279-18true assume !(1 == ~m_pc~0); 164#L279-20true is_master_triggered_~__retres1~0#1 := 0; 222#L290-6true is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 161#is_master_triggered_returnLabel#7true activate_threads_#t~ret11#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 395#L720-18true assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 349#L720-20true assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 233#L298-18true assume !(1 == ~t1_pc~0); 8#L298-20true is_transmit1_triggered_~__retres1~1#1 := 0; 113#L309-6true is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 422#is_transmit1_triggered_returnLabel#7true activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 123#L728-18true assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 450#L728-20true assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 208#L317-18true assume !(1 == ~t2_pc~0); 228#L317-20true is_transmit2_triggered_~__retres1~2#1 := 0; 242#L328-6true is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 238#is_transmit2_triggered_returnLabel#7true activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 115#L736-18true assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 356#L736-20true assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 352#L336-18true assume 1 == ~t3_pc~0; 323#L337-6true assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 398#L347-6true is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 263#is_transmit3_triggered_returnLabel#7true activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 177#L744-18true assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 78#L744-20true assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 291#L355-18true assume 1 == ~t4_pc~0; 414#L356-6true assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 421#L366-6true is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 180#is_transmit4_triggered_returnLabel#7true activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 213#L752-18true assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 132#L752-20true assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 336#L374-18true assume !(1 == ~t5_pc~0); 294#L374-20true is_transmit5_triggered_~__retres1~5#1 := 0; 173#L385-6true is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 133#is_transmit5_triggered_returnLabel#7true activate_threads_#t~ret16#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 452#L760-18true assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 275#L760-20true havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 462#L649-3true assume 1 == ~M_E~0;~M_E~0 := 2; 187#L649-5true assume 1 == ~T1_E~0;~T1_E~0 := 2; 170#L654-3true assume 1 == ~T2_E~0;~T2_E~0 := 2; 83#L659-3true assume 1 == ~T3_E~0;~T3_E~0 := 2; 456#L664-3true assume 1 == ~T4_E~0;~T4_E~0 := 2; 24#L669-3true assume !(1 == ~T5_E~0); 484#L674-3true assume 1 == ~E_1~0;~E_1~0 := 2; 19#L679-3true assume 1 == ~E_2~0;~E_2~0 := 2; 183#L684-3true assume 1 == ~E_3~0;~E_3~0 := 2; 2#L689-3true assume 1 == ~E_4~0;~E_4~0 := 2; 137#L694-3true assume 1 == ~E_5~0;~E_5~0 := 2; 17#L699-3true assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 419#L439-1true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 483#L471-1true exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 217#exists_runnable_thread_returnLabel#2true start_simulation_#t~ret18#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret18#1;havoc start_simulation_#t~ret18#1; 200#L919true assume !(0 == start_simulation_~tmp~3#1); 492#L919-2true assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret17#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 301#L439-2true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 380#L471-2true exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 31#exists_runnable_thread_returnLabel#3true stop_simulation_#t~ret17#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret17#1;havoc stop_simulation_#t~ret17#1; 193#L874true assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 355#L881true stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 372#stop_simulation_returnLabel#1true start_simulation_#t~ret19#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret17#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret19#1;havoc start_simulation_#t~ret19#1; 332#L932true assume !(0 != start_simulation_~tmp___0~1#1); 480#L900-2true [2023-11-06 22:25:57,325 INFO L145 PredicateUnifier]: Initialized classic predicate unifier [2023-11-06 22:25:57,326 INFO L85 PathProgramCache]: Analyzing trace with hash -777385748, now seen corresponding path program 1 times [2023-11-06 22:25:57,337 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-06 22:25:57,338 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1749103640] [2023-11-06 22:25:57,338 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-06 22:25:57,339 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-06 22:25:57,454 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-06 22:25:57,618 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-06 22:25:57,619 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-06 22:25:57,619 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1749103640] [2023-11-06 22:25:57,620 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1749103640] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-06 22:25:57,620 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-06 22:25:57,621 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-06 22:25:57,623 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1270230251] [2023-11-06 22:25:57,624 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-06 22:25:57,630 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-06 22:25:57,633 INFO L145 PredicateUnifier]: Initialized classic predicate unifier [2023-11-06 22:25:57,633 INFO L85 PathProgramCache]: Analyzing trace with hash 1472852014, now seen corresponding path program 1 times [2023-11-06 22:25:57,633 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-06 22:25:57,634 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1111096805] [2023-11-06 22:25:57,634 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-06 22:25:57,634 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-06 22:25:57,678 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-06 22:25:57,743 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-06 22:25:57,744 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-06 22:25:57,744 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1111096805] [2023-11-06 22:25:57,744 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1111096805] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-06 22:25:57,745 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-06 22:25:57,745 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2023-11-06 22:25:57,745 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [491857262] [2023-11-06 22:25:57,745 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-06 22:25:57,747 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-06 22:25:57,748 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-06 22:25:57,794 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-06 22:25:57,795 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-06 22:25:57,799 INFO L87 Difference]: Start difference. First operand has 512 states, 511 states have (on average 1.5264187866927592) internal successors, (780), 511 states have internal predecessors, (780), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand has 3 states, 3 states have (on average 23.666666666666668) internal successors, (71), 3 states have internal predecessors, (71), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-06 22:25:57,907 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-06 22:25:57,908 INFO L93 Difference]: Finished difference Result 510 states and 758 transitions. [2023-11-06 22:25:57,910 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 510 states and 758 transitions. [2023-11-06 22:25:57,922 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 427 [2023-11-06 22:25:57,947 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 510 states to 504 states and 752 transitions. [2023-11-06 22:25:57,950 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 504 [2023-11-06 22:25:57,953 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 504 [2023-11-06 22:25:57,954 INFO L73 IsDeterministic]: Start isDeterministic. Operand 504 states and 752 transitions. [2023-11-06 22:25:57,965 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-06 22:25:57,965 INFO L218 hiAutomatonCegarLoop]: Abstraction has 504 states and 752 transitions. [2023-11-06 22:25:57,993 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 504 states and 752 transitions. [2023-11-06 22:25:58,059 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 504 to 504. [2023-11-06 22:25:58,063 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 504 states, 504 states have (on average 1.492063492063492) internal successors, (752), 503 states have internal predecessors, (752), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-06 22:25:58,066 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 504 states to 504 states and 752 transitions. [2023-11-06 22:25:58,069 INFO L240 hiAutomatonCegarLoop]: Abstraction has 504 states and 752 transitions. [2023-11-06 22:25:58,070 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-06 22:25:58,076 INFO L428 stractBuchiCegarLoop]: Abstraction has 504 states and 752 transitions. [2023-11-06 22:25:58,077 INFO L335 stractBuchiCegarLoop]: ======== Iteration 2 ============ [2023-11-06 22:25:58,077 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 504 states and 752 transitions. [2023-11-06 22:25:58,085 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 427 [2023-11-06 22:25:58,086 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-06 22:25:58,086 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-06 22:25:58,095 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-06 22:25:58,096 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-06 22:25:58,096 INFO L748 eck$LassoCheckResult]: Stem: 1302#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2; 1303#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~7#1;havoc main_~__retres1~7#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 1408#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret18#1, start_simulation_#t~ret19#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 1409#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 1426#L401 assume 1 == ~m_i~0;~m_st~0 := 0; 1427#L401-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 1237#L406-1 assume !(1 == ~t2_i~0);~t2_st~0 := 2; 1238#L411-1 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 1515#L416-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 1516#L421-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 1482#L426-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 1206#L586 assume 0 == ~M_E~0;~M_E~0 := 1; 1207#L586-2 assume !(0 == ~T1_E~0); 1258#L591-1 assume !(0 == ~T2_E~0); 1372#L596-1 assume !(0 == ~T3_E~0); 1373#L601-1 assume !(0 == ~T4_E~0); 1414#L606-1 assume !(0 == ~T5_E~0); 1415#L611-1 assume !(0 == ~E_1~0); 1490#L616-1 assume !(0 == ~E_2~0); 1491#L621-1 assume 0 == ~E_3~0;~E_3~0 := 1; 1133#L626-1 assume !(0 == ~E_4~0); 1134#L631-1 assume !(0 == ~E_5~0); 1297#L636-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1128#L279 assume 1 == ~m_pc~0; 1129#L280 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 1378#L290 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1272#is_master_triggered_returnLabel#1 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 1273#L720 assume !(0 != activate_threads_~tmp~1#1); 1437#L720-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1304#L298 assume !(1 == ~t1_pc~0); 1075#L298-2 is_transmit1_triggered_~__retres1~1#1 := 0; 1076#L309 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1101#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 1102#L728 assume !(0 != activate_threads_~tmp___0~0#1); 1142#L728-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1264#L317 assume 1 == ~t2_pc~0; 1265#L318 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 1406#L328 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1413#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 1313#L736 assume !(0 != activate_threads_~tmp___1~0#1); 1314#L736-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1479#L336 assume 1 == ~t3_pc~0; 1351#L337 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 1352#L347 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1048#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 1049#L744 assume !(0 != activate_threads_~tmp___2~0#1); 1445#L744-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1486#L355 assume !(1 == ~t4_pc~0); 1369#L355-2 is_transmit4_triggered_~__retres1~4#1 := 0; 1224#L366 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1172#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 1173#L752 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 1152#L752-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1153#L374 assume 1 == ~t5_pc~0; 1508#L375 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 1288#L385 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1278#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 1279#L760 assume !(0 != activate_threads_~tmp___4~0#1); 1397#L760-2 havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1398#L649 assume 1 == ~M_E~0;~M_E~0 := 2; 1527#L649-2 assume !(1 == ~T1_E~0); 1114#L654-1 assume !(1 == ~T2_E~0); 1115#L659-1 assume !(1 == ~T3_E~0); 1312#L664-1 assume !(1 == ~T4_E~0); 1106#L669-1 assume !(1 == ~T5_E~0); 1107#L674-1 assume !(1 == ~E_1~0); 1471#L679-1 assume !(1 == ~E_2~0); 1211#L684-1 assume 1 == ~E_3~0;~E_3~0 := 2; 1212#L689-1 assume !(1 == ~E_4~0); 1365#L694-1 assume !(1 == ~E_5~0); 1363#L699-1 assume { :end_inline_reset_delta_events } true; 1364#L900-2 [2023-11-06 22:25:58,097 INFO L750 eck$LassoCheckResult]: Loop: 1364#L900-2 assume !false; 1533#L901 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 1283#L561-1 assume !false; 1339#L482 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 1331#L439 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 1077#L471 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 1078#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 1200#L486 assume !(0 != eval_~tmp~0#1); 1179#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 1180#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 1502#L586-3 assume 0 == ~M_E~0;~M_E~0 := 1; 1470#L586-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 1380#L591-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 1228#L596-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 1229#L601-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 1393#L606-3 assume !(0 == ~T5_E~0); 1429#L611-3 assume 0 == ~E_1~0;~E_1~0 := 1; 1430#L616-3 assume 0 == ~E_2~0;~E_2~0 := 1; 1122#L621-3 assume 0 == ~E_3~0;~E_3~0 := 1; 1073#L626-3 assume 0 == ~E_4~0;~E_4~0 := 1; 1074#L631-3 assume 0 == ~E_5~0;~E_5~0 := 1; 1079#L636-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1080#L279-18 assume 1 == ~m_pc~0; 1187#L280-6 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 1188#L290-6 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1317#is_master_triggered_returnLabel#7 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 1318#L720-18 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 1492#L720-20 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1396#L298-18 assume !(1 == ~t1_pc~0); 1046#L298-20 is_transmit1_triggered_~__retres1~1#1 := 0; 1047#L309-6 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1236#is_transmit1_triggered_returnLabel#7 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 1254#L728-18 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 1255#L728-20 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1374#L317-18 assume 1 == ~t2_pc~0; 1289#L318-6 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 1290#L328-6 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1404#is_transmit2_triggered_returnLabel#7 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 1239#L736-18 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 1240#L736-20 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1495#L336-18 assume 1 == ~t3_pc~0; 1475#L337-6 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 1476#L347-6 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1431#is_transmit3_triggered_returnLabel#7 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 1340#L744-18 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 1181#L744-20 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1182#L355-18 assume !(1 == ~t4_pc~0); 1443#L355-20 is_transmit4_triggered_~__retres1~4#1 := 0; 1444#L366-6 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1345#is_transmit4_triggered_returnLabel#7 activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 1346#L752-18 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 1274#L752-20 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1275#L374-18 assume !(1 == ~t5_pc~0); 1457#L374-20 is_transmit5_triggered_~__retres1~5#1 := 0; 1336#L385-6 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1276#is_transmit5_triggered_returnLabel#7 activate_threads_#t~ret16#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 1277#L760-18 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 1438#L760-20 havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1439#L649-3 assume 1 == ~M_E~0;~M_E~0 := 2; 1350#L649-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 1330#L654-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 1191#L659-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 1192#L664-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 1083#L669-3 assume !(1 == ~T5_E~0); 1084#L674-3 assume 1 == ~E_1~0;~E_1~0 := 2; 1071#L679-3 assume 1 == ~E_2~0;~E_2~0 := 2; 1072#L684-3 assume 1 == ~E_3~0;~E_3~0 := 2; 1031#L689-3 assume 1 == ~E_4~0;~E_4~0 := 2; 1032#L694-3 assume 1 == ~E_5~0;~E_5~0 := 2; 1066#L699-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 1067#L439-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 1069#L471-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 1379#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret18#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret18#1;havoc start_simulation_#t~ret18#1; 1362#L919 assume !(0 == start_simulation_~tmp~3#1); 1082#L919-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret17#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 1461#L439-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 1060#L471-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 1098#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret17#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret17#1;havoc stop_simulation_#t~ret17#1; 1099#L874 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 1358#L881 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 1496#stop_simulation_returnLabel#1 start_simulation_#t~ret19#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret17#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret19#1;havoc start_simulation_#t~ret19#1; 1484#L932 assume !(0 != start_simulation_~tmp___0~1#1); 1364#L900-2 [2023-11-06 22:25:58,098 INFO L145 PredicateUnifier]: Initialized classic predicate unifier [2023-11-06 22:25:58,098 INFO L85 PathProgramCache]: Analyzing trace with hash 438767978, now seen corresponding path program 1 times [2023-11-06 22:25:58,098 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-06 22:25:58,099 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1446191519] [2023-11-06 22:25:58,099 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-06 22:25:58,099 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-06 22:25:58,118 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-06 22:25:58,185 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-06 22:25:58,186 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-06 22:25:58,186 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1446191519] [2023-11-06 22:25:58,186 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1446191519] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-06 22:25:58,187 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-06 22:25:58,187 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-06 22:25:58,187 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2140811555] [2023-11-06 22:25:58,187 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-06 22:25:58,188 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-06 22:25:58,188 INFO L145 PredicateUnifier]: Initialized classic predicate unifier [2023-11-06 22:25:58,188 INFO L85 PathProgramCache]: Analyzing trace with hash 1177747720, now seen corresponding path program 1 times [2023-11-06 22:25:58,189 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-06 22:25:58,189 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1343080174] [2023-11-06 22:25:58,189 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-06 22:25:58,190 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-06 22:25:58,256 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-06 22:25:58,412 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-06 22:25:58,413 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-06 22:25:58,414 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1343080174] [2023-11-06 22:25:58,414 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1343080174] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-06 22:25:58,414 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-06 22:25:58,414 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2023-11-06 22:25:58,415 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [25289216] [2023-11-06 22:25:58,416 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-06 22:25:58,418 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-06 22:25:58,419 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-06 22:25:58,419 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-06 22:25:58,420 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-06 22:25:58,421 INFO L87 Difference]: Start difference. First operand 504 states and 752 transitions. cyclomatic complexity: 249 Second operand has 3 states, 3 states have (on average 23.666666666666668) internal successors, (71), 3 states have internal predecessors, (71), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-06 22:25:58,459 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-06 22:25:58,459 INFO L93 Difference]: Finished difference Result 504 states and 751 transitions. [2023-11-06 22:25:58,459 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 504 states and 751 transitions. [2023-11-06 22:25:58,468 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 427 [2023-11-06 22:25:58,474 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 504 states to 504 states and 751 transitions. [2023-11-06 22:25:58,474 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 504 [2023-11-06 22:25:58,475 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 504 [2023-11-06 22:25:58,476 INFO L73 IsDeterministic]: Start isDeterministic. Operand 504 states and 751 transitions. [2023-11-06 22:25:58,478 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-06 22:25:58,478 INFO L218 hiAutomatonCegarLoop]: Abstraction has 504 states and 751 transitions. [2023-11-06 22:25:58,479 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 504 states and 751 transitions. [2023-11-06 22:25:58,498 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 504 to 504. [2023-11-06 22:25:58,499 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 504 states, 504 states have (on average 1.4900793650793651) internal successors, (751), 503 states have internal predecessors, (751), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-06 22:25:58,503 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 504 states to 504 states and 751 transitions. [2023-11-06 22:25:58,506 INFO L240 hiAutomatonCegarLoop]: Abstraction has 504 states and 751 transitions. [2023-11-06 22:25:58,507 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-06 22:25:58,509 INFO L428 stractBuchiCegarLoop]: Abstraction has 504 states and 751 transitions. [2023-11-06 22:25:58,509 INFO L335 stractBuchiCegarLoop]: ======== Iteration 3 ============ [2023-11-06 22:25:58,509 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 504 states and 751 transitions. [2023-11-06 22:25:58,514 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 427 [2023-11-06 22:25:58,515 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-06 22:25:58,516 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-06 22:25:58,518 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-06 22:25:58,518 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-06 22:25:58,519 INFO L748 eck$LassoCheckResult]: Stem: 2319#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2; 2320#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~7#1;havoc main_~__retres1~7#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 2425#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret18#1, start_simulation_#t~ret19#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 2426#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 2443#L401 assume 1 == ~m_i~0;~m_st~0 := 0; 2444#L401-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 2254#L406-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 2255#L411-1 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 2532#L416-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 2533#L421-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 2499#L426-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 2223#L586 assume 0 == ~M_E~0;~M_E~0 := 1; 2224#L586-2 assume !(0 == ~T1_E~0); 2275#L591-1 assume !(0 == ~T2_E~0); 2389#L596-1 assume !(0 == ~T3_E~0); 2390#L601-1 assume !(0 == ~T4_E~0); 2431#L606-1 assume !(0 == ~T5_E~0); 2432#L611-1 assume !(0 == ~E_1~0); 2507#L616-1 assume !(0 == ~E_2~0); 2508#L621-1 assume 0 == ~E_3~0;~E_3~0 := 1; 2150#L626-1 assume !(0 == ~E_4~0); 2151#L631-1 assume !(0 == ~E_5~0); 2314#L636-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 2145#L279 assume 1 == ~m_pc~0; 2146#L280 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 2395#L290 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 2289#is_master_triggered_returnLabel#1 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 2290#L720 assume !(0 != activate_threads_~tmp~1#1); 2454#L720-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 2321#L298 assume !(1 == ~t1_pc~0); 2092#L298-2 is_transmit1_triggered_~__retres1~1#1 := 0; 2093#L309 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 2118#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 2119#L728 assume !(0 != activate_threads_~tmp___0~0#1); 2159#L728-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 2281#L317 assume 1 == ~t2_pc~0; 2282#L318 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 2423#L328 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 2430#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 2330#L736 assume !(0 != activate_threads_~tmp___1~0#1); 2331#L736-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 2496#L336 assume 1 == ~t3_pc~0; 2368#L337 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 2369#L347 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 2065#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 2066#L744 assume !(0 != activate_threads_~tmp___2~0#1); 2462#L744-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 2503#L355 assume !(1 == ~t4_pc~0); 2386#L355-2 is_transmit4_triggered_~__retres1~4#1 := 0; 2241#L366 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 2189#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 2190#L752 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 2169#L752-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 2170#L374 assume 1 == ~t5_pc~0; 2525#L375 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 2305#L385 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 2295#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 2296#L760 assume !(0 != activate_threads_~tmp___4~0#1); 2414#L760-2 havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 2415#L649 assume 1 == ~M_E~0;~M_E~0 := 2; 2544#L649-2 assume !(1 == ~T1_E~0); 2131#L654-1 assume !(1 == ~T2_E~0); 2132#L659-1 assume !(1 == ~T3_E~0); 2329#L664-1 assume !(1 == ~T4_E~0); 2123#L669-1 assume !(1 == ~T5_E~0); 2124#L674-1 assume !(1 == ~E_1~0); 2488#L679-1 assume !(1 == ~E_2~0); 2228#L684-1 assume 1 == ~E_3~0;~E_3~0 := 2; 2229#L689-1 assume !(1 == ~E_4~0); 2382#L694-1 assume !(1 == ~E_5~0); 2380#L699-1 assume { :end_inline_reset_delta_events } true; 2381#L900-2 [2023-11-06 22:25:58,523 INFO L750 eck$LassoCheckResult]: Loop: 2381#L900-2 assume !false; 2550#L901 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 2300#L561-1 assume !false; 2356#L482 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 2348#L439 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 2094#L471 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 2095#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 2217#L486 assume !(0 != eval_~tmp~0#1); 2196#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 2197#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 2519#L586-3 assume 0 == ~M_E~0;~M_E~0 := 1; 2487#L586-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 2397#L591-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 2245#L596-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 2246#L601-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 2410#L606-3 assume !(0 == ~T5_E~0); 2446#L611-3 assume 0 == ~E_1~0;~E_1~0 := 1; 2447#L616-3 assume 0 == ~E_2~0;~E_2~0 := 1; 2139#L621-3 assume 0 == ~E_3~0;~E_3~0 := 1; 2090#L626-3 assume 0 == ~E_4~0;~E_4~0 := 1; 2091#L631-3 assume 0 == ~E_5~0;~E_5~0 := 1; 2096#L636-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 2097#L279-18 assume 1 == ~m_pc~0; 2204#L280-6 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 2205#L290-6 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 2334#is_master_triggered_returnLabel#7 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 2335#L720-18 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 2509#L720-20 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 2413#L298-18 assume 1 == ~t1_pc~0; 2070#L299-6 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 2064#L309-6 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 2253#is_transmit1_triggered_returnLabel#7 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 2271#L728-18 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 2272#L728-20 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 2391#L317-18 assume 1 == ~t2_pc~0; 2306#L318-6 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 2307#L328-6 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 2421#is_transmit2_triggered_returnLabel#7 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 2256#L736-18 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 2257#L736-20 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 2512#L336-18 assume 1 == ~t3_pc~0; 2492#L337-6 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 2493#L347-6 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 2448#is_transmit3_triggered_returnLabel#7 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 2357#L744-18 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 2198#L744-20 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 2199#L355-18 assume 1 == ~t4_pc~0; 2472#L356-6 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 2461#L366-6 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 2362#is_transmit4_triggered_returnLabel#7 activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 2363#L752-18 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 2291#L752-20 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 2292#L374-18 assume 1 == ~t5_pc~0; 2502#L375-6 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 2353#L385-6 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 2293#is_transmit5_triggered_returnLabel#7 activate_threads_#t~ret16#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 2294#L760-18 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 2455#L760-20 havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 2456#L649-3 assume 1 == ~M_E~0;~M_E~0 := 2; 2367#L649-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 2347#L654-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 2208#L659-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 2209#L664-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 2098#L669-3 assume !(1 == ~T5_E~0); 2099#L674-3 assume 1 == ~E_1~0;~E_1~0 := 2; 2088#L679-3 assume 1 == ~E_2~0;~E_2~0 := 2; 2089#L684-3 assume 1 == ~E_3~0;~E_3~0 := 2; 2048#L689-3 assume 1 == ~E_4~0;~E_4~0 := 2; 2049#L694-3 assume 1 == ~E_5~0;~E_5~0 := 2; 2083#L699-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 2084#L439-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 2086#L471-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 2396#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret18#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret18#1;havoc start_simulation_#t~ret18#1; 2379#L919 assume !(0 == start_simulation_~tmp~3#1); 2101#L919-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret17#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 2478#L439-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 2077#L471-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 2115#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret17#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret17#1;havoc stop_simulation_#t~ret17#1; 2116#L874 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 2375#L881 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 2513#stop_simulation_returnLabel#1 start_simulation_#t~ret19#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret17#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret19#1;havoc start_simulation_#t~ret19#1; 2501#L932 assume !(0 != start_simulation_~tmp___0~1#1); 2381#L900-2 [2023-11-06 22:25:58,523 INFO L145 PredicateUnifier]: Initialized classic predicate unifier [2023-11-06 22:25:58,524 INFO L85 PathProgramCache]: Analyzing trace with hash 2124947816, now seen corresponding path program 1 times [2023-11-06 22:25:58,524 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-06 22:25:58,525 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [423714777] [2023-11-06 22:25:58,525 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-06 22:25:58,525 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-06 22:25:58,556 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-06 22:25:58,630 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-06 22:25:58,630 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-06 22:25:58,631 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [423714777] [2023-11-06 22:25:58,631 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [423714777] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-06 22:25:58,631 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-06 22:25:58,631 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-06 22:25:58,632 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [123753980] [2023-11-06 22:25:58,632 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-06 22:25:58,632 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-06 22:25:58,633 INFO L145 PredicateUnifier]: Initialized classic predicate unifier [2023-11-06 22:25:58,633 INFO L85 PathProgramCache]: Analyzing trace with hash -1398059989, now seen corresponding path program 1 times [2023-11-06 22:25:58,633 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-06 22:25:58,634 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [417985895] [2023-11-06 22:25:58,634 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-06 22:25:58,634 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-06 22:25:58,661 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-06 22:25:58,783 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-06 22:25:58,783 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-06 22:25:58,784 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [417985895] [2023-11-06 22:25:58,785 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [417985895] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-06 22:25:58,785 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-06 22:25:58,785 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2023-11-06 22:25:58,786 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [626656138] [2023-11-06 22:25:58,786 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-06 22:25:58,787 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-06 22:25:58,788 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-06 22:25:58,788 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-06 22:25:58,788 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-06 22:25:58,789 INFO L87 Difference]: Start difference. First operand 504 states and 751 transitions. cyclomatic complexity: 248 Second operand has 3 states, 3 states have (on average 23.666666666666668) internal successors, (71), 3 states have internal predecessors, (71), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-06 22:25:58,816 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-06 22:25:58,816 INFO L93 Difference]: Finished difference Result 504 states and 750 transitions. [2023-11-06 22:25:58,817 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 504 states and 750 transitions. [2023-11-06 22:25:58,877 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 427 [2023-11-06 22:25:58,887 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 504 states to 504 states and 750 transitions. [2023-11-06 22:25:58,888 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 504 [2023-11-06 22:25:58,889 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 504 [2023-11-06 22:25:58,889 INFO L73 IsDeterministic]: Start isDeterministic. Operand 504 states and 750 transitions. [2023-11-06 22:25:58,890 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-06 22:25:58,890 INFO L218 hiAutomatonCegarLoop]: Abstraction has 504 states and 750 transitions. [2023-11-06 22:25:58,892 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 504 states and 750 transitions. [2023-11-06 22:25:58,900 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 504 to 504. [2023-11-06 22:25:58,902 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 504 states, 504 states have (on average 1.4880952380952381) internal successors, (750), 503 states have internal predecessors, (750), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-06 22:25:58,906 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 504 states to 504 states and 750 transitions. [2023-11-06 22:25:58,906 INFO L240 hiAutomatonCegarLoop]: Abstraction has 504 states and 750 transitions. [2023-11-06 22:25:58,906 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-06 22:25:58,909 INFO L428 stractBuchiCegarLoop]: Abstraction has 504 states and 750 transitions. [2023-11-06 22:25:58,909 INFO L335 stractBuchiCegarLoop]: ======== Iteration 4 ============ [2023-11-06 22:25:58,909 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 504 states and 750 transitions. [2023-11-06 22:25:58,913 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 427 [2023-11-06 22:25:58,914 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-06 22:25:58,914 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-06 22:25:58,916 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-06 22:25:58,917 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-06 22:25:58,917 INFO L748 eck$LassoCheckResult]: Stem: 3336#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2; 3337#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~7#1;havoc main_~__retres1~7#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 3442#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret18#1, start_simulation_#t~ret19#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 3443#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 3460#L401 assume 1 == ~m_i~0;~m_st~0 := 0; 3461#L401-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 3271#L406-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 3272#L411-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 3549#L416-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 3550#L421-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 3516#L426-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 3240#L586 assume 0 == ~M_E~0;~M_E~0 := 1; 3241#L586-2 assume !(0 == ~T1_E~0); 3292#L591-1 assume !(0 == ~T2_E~0); 3406#L596-1 assume !(0 == ~T3_E~0); 3407#L601-1 assume !(0 == ~T4_E~0); 3448#L606-1 assume !(0 == ~T5_E~0); 3449#L611-1 assume !(0 == ~E_1~0); 3524#L616-1 assume !(0 == ~E_2~0); 3525#L621-1 assume 0 == ~E_3~0;~E_3~0 := 1; 3167#L626-1 assume !(0 == ~E_4~0); 3168#L631-1 assume !(0 == ~E_5~0); 3331#L636-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 3162#L279 assume 1 == ~m_pc~0; 3163#L280 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 3412#L290 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 3306#is_master_triggered_returnLabel#1 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 3307#L720 assume !(0 != activate_threads_~tmp~1#1); 3471#L720-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 3338#L298 assume !(1 == ~t1_pc~0); 3109#L298-2 is_transmit1_triggered_~__retres1~1#1 := 0; 3110#L309 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 3135#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 3136#L728 assume !(0 != activate_threads_~tmp___0~0#1); 3176#L728-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 3298#L317 assume 1 == ~t2_pc~0; 3299#L318 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 3440#L328 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 3447#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 3347#L736 assume !(0 != activate_threads_~tmp___1~0#1); 3348#L736-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 3513#L336 assume 1 == ~t3_pc~0; 3385#L337 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 3386#L347 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 3082#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 3083#L744 assume !(0 != activate_threads_~tmp___2~0#1); 3479#L744-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 3520#L355 assume !(1 == ~t4_pc~0); 3403#L355-2 is_transmit4_triggered_~__retres1~4#1 := 0; 3258#L366 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 3206#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 3207#L752 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 3186#L752-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 3187#L374 assume 1 == ~t5_pc~0; 3542#L375 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 3322#L385 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 3312#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 3313#L760 assume !(0 != activate_threads_~tmp___4~0#1); 3431#L760-2 havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 3432#L649 assume 1 == ~M_E~0;~M_E~0 := 2; 3561#L649-2 assume !(1 == ~T1_E~0); 3148#L654-1 assume !(1 == ~T2_E~0); 3149#L659-1 assume !(1 == ~T3_E~0); 3346#L664-1 assume !(1 == ~T4_E~0); 3140#L669-1 assume !(1 == ~T5_E~0); 3141#L674-1 assume !(1 == ~E_1~0); 3505#L679-1 assume !(1 == ~E_2~0); 3245#L684-1 assume 1 == ~E_3~0;~E_3~0 := 2; 3246#L689-1 assume !(1 == ~E_4~0); 3399#L694-1 assume !(1 == ~E_5~0); 3397#L699-1 assume { :end_inline_reset_delta_events } true; 3398#L900-2 [2023-11-06 22:25:58,921 INFO L750 eck$LassoCheckResult]: Loop: 3398#L900-2 assume !false; 3567#L901 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 3317#L561-1 assume !false; 3373#L482 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 3365#L439 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 3111#L471 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 3112#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 3234#L486 assume !(0 != eval_~tmp~0#1); 3213#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 3214#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 3536#L586-3 assume 0 == ~M_E~0;~M_E~0 := 1; 3504#L586-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 3414#L591-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 3262#L596-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 3263#L601-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 3427#L606-3 assume !(0 == ~T5_E~0); 3463#L611-3 assume 0 == ~E_1~0;~E_1~0 := 1; 3464#L616-3 assume 0 == ~E_2~0;~E_2~0 := 1; 3156#L621-3 assume 0 == ~E_3~0;~E_3~0 := 1; 3107#L626-3 assume 0 == ~E_4~0;~E_4~0 := 1; 3108#L631-3 assume 0 == ~E_5~0;~E_5~0 := 1; 3113#L636-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 3114#L279-18 assume 1 == ~m_pc~0; 3221#L280-6 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 3222#L290-6 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 3351#is_master_triggered_returnLabel#7 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 3352#L720-18 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 3526#L720-20 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 3430#L298-18 assume !(1 == ~t1_pc~0); 3080#L298-20 is_transmit1_triggered_~__retres1~1#1 := 0; 3081#L309-6 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 3270#is_transmit1_triggered_returnLabel#7 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 3288#L728-18 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 3289#L728-20 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 3408#L317-18 assume 1 == ~t2_pc~0; 3323#L318-6 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 3324#L328-6 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 3438#is_transmit2_triggered_returnLabel#7 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 3273#L736-18 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 3274#L736-20 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 3529#L336-18 assume 1 == ~t3_pc~0; 3509#L337-6 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 3510#L347-6 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 3465#is_transmit3_triggered_returnLabel#7 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 3374#L744-18 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 3215#L744-20 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 3216#L355-18 assume 1 == ~t4_pc~0; 3489#L356-6 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 3478#L366-6 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 3379#is_transmit4_triggered_returnLabel#7 activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 3380#L752-18 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 3308#L752-20 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 3309#L374-18 assume !(1 == ~t5_pc~0); 3491#L374-20 is_transmit5_triggered_~__retres1~5#1 := 0; 3370#L385-6 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 3310#is_transmit5_triggered_returnLabel#7 activate_threads_#t~ret16#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 3311#L760-18 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 3472#L760-20 havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 3473#L649-3 assume 1 == ~M_E~0;~M_E~0 := 2; 3384#L649-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 3364#L654-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 3225#L659-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 3226#L664-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 3115#L669-3 assume !(1 == ~T5_E~0); 3116#L674-3 assume 1 == ~E_1~0;~E_1~0 := 2; 3105#L679-3 assume 1 == ~E_2~0;~E_2~0 := 2; 3106#L684-3 assume 1 == ~E_3~0;~E_3~0 := 2; 3065#L689-3 assume 1 == ~E_4~0;~E_4~0 := 2; 3066#L694-3 assume 1 == ~E_5~0;~E_5~0 := 2; 3100#L699-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 3101#L439-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 3103#L471-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 3413#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret18#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret18#1;havoc start_simulation_#t~ret18#1; 3396#L919 assume !(0 == start_simulation_~tmp~3#1); 3118#L919-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret17#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 3495#L439-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 3094#L471-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 3132#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret17#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret17#1;havoc stop_simulation_#t~ret17#1; 3133#L874 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 3392#L881 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 3530#stop_simulation_returnLabel#1 start_simulation_#t~ret19#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret17#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret19#1;havoc start_simulation_#t~ret19#1; 3518#L932 assume !(0 != start_simulation_~tmp___0~1#1); 3398#L900-2 [2023-11-06 22:25:58,922 INFO L145 PredicateUnifier]: Initialized classic predicate unifier [2023-11-06 22:25:58,922 INFO L85 PathProgramCache]: Analyzing trace with hash -2115626582, now seen corresponding path program 1 times [2023-11-06 22:25:58,922 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-06 22:25:58,923 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1916815246] [2023-11-06 22:25:58,923 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-06 22:25:58,923 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-06 22:25:58,955 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-06 22:25:59,006 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-06 22:25:59,007 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-06 22:25:59,007 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1916815246] [2023-11-06 22:25:59,007 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1916815246] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-06 22:25:59,008 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-06 22:25:59,008 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-06 22:25:59,008 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1407580142] [2023-11-06 22:25:59,008 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-06 22:25:59,009 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-06 22:25:59,009 INFO L145 PredicateUnifier]: Initialized classic predicate unifier [2023-11-06 22:25:59,009 INFO L85 PathProgramCache]: Analyzing trace with hash -1352402967, now seen corresponding path program 1 times [2023-11-06 22:25:59,010 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-06 22:25:59,010 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1993357268] [2023-11-06 22:25:59,010 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-06 22:25:59,010 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-06 22:25:59,028 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-06 22:25:59,126 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-06 22:25:59,126 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-06 22:25:59,127 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1993357268] [2023-11-06 22:25:59,127 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1993357268] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-06 22:25:59,127 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-06 22:25:59,127 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2023-11-06 22:25:59,127 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [344104670] [2023-11-06 22:25:59,128 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-06 22:25:59,129 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-06 22:25:59,129 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-06 22:25:59,129 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-06 22:25:59,130 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-06 22:25:59,130 INFO L87 Difference]: Start difference. First operand 504 states and 750 transitions. cyclomatic complexity: 247 Second operand has 3 states, 3 states have (on average 23.666666666666668) internal successors, (71), 3 states have internal predecessors, (71), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-06 22:25:59,152 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-06 22:25:59,152 INFO L93 Difference]: Finished difference Result 504 states and 749 transitions. [2023-11-06 22:25:59,153 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 504 states and 749 transitions. [2023-11-06 22:25:59,158 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 427 [2023-11-06 22:25:59,164 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 504 states to 504 states and 749 transitions. [2023-11-06 22:25:59,164 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 504 [2023-11-06 22:25:59,165 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 504 [2023-11-06 22:25:59,165 INFO L73 IsDeterministic]: Start isDeterministic. Operand 504 states and 749 transitions. [2023-11-06 22:25:59,166 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-06 22:25:59,167 INFO L218 hiAutomatonCegarLoop]: Abstraction has 504 states and 749 transitions. [2023-11-06 22:25:59,168 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 504 states and 749 transitions. [2023-11-06 22:25:59,176 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 504 to 504. [2023-11-06 22:25:59,178 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 504 states, 504 states have (on average 1.4861111111111112) internal successors, (749), 503 states have internal predecessors, (749), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-06 22:25:59,181 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 504 states to 504 states and 749 transitions. [2023-11-06 22:25:59,181 INFO L240 hiAutomatonCegarLoop]: Abstraction has 504 states and 749 transitions. [2023-11-06 22:25:59,181 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-06 22:25:59,186 INFO L428 stractBuchiCegarLoop]: Abstraction has 504 states and 749 transitions. [2023-11-06 22:25:59,190 INFO L335 stractBuchiCegarLoop]: ======== Iteration 5 ============ [2023-11-06 22:25:59,190 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 504 states and 749 transitions. [2023-11-06 22:25:59,194 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 427 [2023-11-06 22:25:59,194 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-06 22:25:59,194 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-06 22:25:59,201 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-06 22:25:59,201 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-06 22:25:59,201 INFO L748 eck$LassoCheckResult]: Stem: 4353#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2; 4354#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~7#1;havoc main_~__retres1~7#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 4459#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret18#1, start_simulation_#t~ret19#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 4460#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 4477#L401 assume 1 == ~m_i~0;~m_st~0 := 0; 4478#L401-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 4288#L406-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 4289#L411-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 4566#L416-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 4567#L421-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 4533#L426-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 4257#L586 assume 0 == ~M_E~0;~M_E~0 := 1; 4258#L586-2 assume !(0 == ~T1_E~0); 4309#L591-1 assume !(0 == ~T2_E~0); 4423#L596-1 assume !(0 == ~T3_E~0); 4424#L601-1 assume !(0 == ~T4_E~0); 4465#L606-1 assume !(0 == ~T5_E~0); 4466#L611-1 assume !(0 == ~E_1~0); 4541#L616-1 assume !(0 == ~E_2~0); 4542#L621-1 assume 0 == ~E_3~0;~E_3~0 := 1; 4184#L626-1 assume !(0 == ~E_4~0); 4185#L631-1 assume !(0 == ~E_5~0); 4348#L636-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 4179#L279 assume 1 == ~m_pc~0; 4180#L280 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 4429#L290 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 4323#is_master_triggered_returnLabel#1 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 4324#L720 assume !(0 != activate_threads_~tmp~1#1); 4488#L720-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 4355#L298 assume !(1 == ~t1_pc~0); 4126#L298-2 is_transmit1_triggered_~__retres1~1#1 := 0; 4127#L309 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 4152#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 4153#L728 assume !(0 != activate_threads_~tmp___0~0#1); 4193#L728-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 4315#L317 assume 1 == ~t2_pc~0; 4316#L318 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 4457#L328 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 4464#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 4364#L736 assume !(0 != activate_threads_~tmp___1~0#1); 4365#L736-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 4530#L336 assume 1 == ~t3_pc~0; 4402#L337 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 4403#L347 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 4099#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 4100#L744 assume !(0 != activate_threads_~tmp___2~0#1); 4496#L744-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 4537#L355 assume !(1 == ~t4_pc~0); 4420#L355-2 is_transmit4_triggered_~__retres1~4#1 := 0; 4275#L366 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 4223#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 4224#L752 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 4203#L752-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 4204#L374 assume 1 == ~t5_pc~0; 4559#L375 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 4339#L385 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 4329#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 4330#L760 assume !(0 != activate_threads_~tmp___4~0#1); 4448#L760-2 havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 4449#L649 assume 1 == ~M_E~0;~M_E~0 := 2; 4578#L649-2 assume !(1 == ~T1_E~0); 4165#L654-1 assume !(1 == ~T2_E~0); 4166#L659-1 assume !(1 == ~T3_E~0); 4363#L664-1 assume !(1 == ~T4_E~0); 4157#L669-1 assume !(1 == ~T5_E~0); 4158#L674-1 assume !(1 == ~E_1~0); 4522#L679-1 assume !(1 == ~E_2~0); 4262#L684-1 assume 1 == ~E_3~0;~E_3~0 := 2; 4263#L689-1 assume !(1 == ~E_4~0); 4416#L694-1 assume !(1 == ~E_5~0); 4414#L699-1 assume { :end_inline_reset_delta_events } true; 4415#L900-2 [2023-11-06 22:25:59,202 INFO L750 eck$LassoCheckResult]: Loop: 4415#L900-2 assume !false; 4584#L901 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 4334#L561-1 assume !false; 4390#L482 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 4382#L439 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 4128#L471 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 4129#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 4251#L486 assume !(0 != eval_~tmp~0#1); 4230#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 4231#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 4553#L586-3 assume 0 == ~M_E~0;~M_E~0 := 1; 4521#L586-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 4431#L591-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 4279#L596-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 4280#L601-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 4444#L606-3 assume !(0 == ~T5_E~0); 4480#L611-3 assume 0 == ~E_1~0;~E_1~0 := 1; 4481#L616-3 assume 0 == ~E_2~0;~E_2~0 := 1; 4173#L621-3 assume 0 == ~E_3~0;~E_3~0 := 1; 4124#L626-3 assume 0 == ~E_4~0;~E_4~0 := 1; 4125#L631-3 assume 0 == ~E_5~0;~E_5~0 := 1; 4130#L636-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 4131#L279-18 assume !(1 == ~m_pc~0); 4240#L279-20 is_master_triggered_~__retres1~0#1 := 0; 4239#L290-6 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 4368#is_master_triggered_returnLabel#7 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 4369#L720-18 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 4543#L720-20 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 4447#L298-18 assume !(1 == ~t1_pc~0); 4097#L298-20 is_transmit1_triggered_~__retres1~1#1 := 0; 4098#L309-6 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 4287#is_transmit1_triggered_returnLabel#7 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 4305#L728-18 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 4306#L728-20 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 4425#L317-18 assume 1 == ~t2_pc~0; 4340#L318-6 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 4341#L328-6 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 4455#is_transmit2_triggered_returnLabel#7 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 4290#L736-18 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 4291#L736-20 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 4546#L336-18 assume !(1 == ~t3_pc~0); 4528#L336-20 is_transmit3_triggered_~__retres1~3#1 := 0; 4527#L347-6 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 4482#is_transmit3_triggered_returnLabel#7 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 4391#L744-18 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 4232#L744-20 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 4233#L355-18 assume 1 == ~t4_pc~0; 4506#L356-6 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 4495#L366-6 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 4396#is_transmit4_triggered_returnLabel#7 activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 4397#L752-18 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 4325#L752-20 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 4326#L374-18 assume 1 == ~t5_pc~0; 4536#L375-6 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 4387#L385-6 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 4327#is_transmit5_triggered_returnLabel#7 activate_threads_#t~ret16#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 4328#L760-18 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 4489#L760-20 havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 4490#L649-3 assume 1 == ~M_E~0;~M_E~0 := 2; 4401#L649-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 4381#L654-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 4242#L659-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 4243#L664-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 4132#L669-3 assume !(1 == ~T5_E~0); 4133#L674-3 assume 1 == ~E_1~0;~E_1~0 := 2; 4122#L679-3 assume 1 == ~E_2~0;~E_2~0 := 2; 4123#L684-3 assume 1 == ~E_3~0;~E_3~0 := 2; 4082#L689-3 assume 1 == ~E_4~0;~E_4~0 := 2; 4083#L694-3 assume 1 == ~E_5~0;~E_5~0 := 2; 4117#L699-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 4118#L439-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 4120#L471-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 4430#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret18#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret18#1;havoc start_simulation_#t~ret18#1; 4413#L919 assume !(0 == start_simulation_~tmp~3#1); 4135#L919-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret17#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 4512#L439-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 4111#L471-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 4149#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret17#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret17#1;havoc stop_simulation_#t~ret17#1; 4150#L874 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 4409#L881 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 4547#stop_simulation_returnLabel#1 start_simulation_#t~ret19#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret17#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret19#1;havoc start_simulation_#t~ret19#1; 4535#L932 assume !(0 != start_simulation_~tmp___0~1#1); 4415#L900-2 [2023-11-06 22:25:59,202 INFO L145 PredicateUnifier]: Initialized classic predicate unifier [2023-11-06 22:25:59,208 INFO L85 PathProgramCache]: Analyzing trace with hash -1698229976, now seen corresponding path program 1 times [2023-11-06 22:25:59,208 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-06 22:25:59,208 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [416405921] [2023-11-06 22:25:59,209 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-06 22:25:59,209 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-06 22:25:59,227 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-06 22:25:59,268 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-06 22:25:59,268 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-06 22:25:59,269 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [416405921] [2023-11-06 22:25:59,269 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [416405921] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-06 22:25:59,270 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-06 22:25:59,270 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-06 22:25:59,270 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1807178311] [2023-11-06 22:25:59,270 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-06 22:25:59,271 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-06 22:25:59,271 INFO L145 PredicateUnifier]: Initialized classic predicate unifier [2023-11-06 22:25:59,271 INFO L85 PathProgramCache]: Analyzing trace with hash -1062290040, now seen corresponding path program 1 times [2023-11-06 22:25:59,271 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-06 22:25:59,272 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1510054474] [2023-11-06 22:25:59,272 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-06 22:25:59,272 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-06 22:25:59,293 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-06 22:25:59,358 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-06 22:25:59,359 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-06 22:25:59,359 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1510054474] [2023-11-06 22:25:59,359 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1510054474] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-06 22:25:59,359 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-06 22:25:59,360 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2023-11-06 22:25:59,360 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1952197732] [2023-11-06 22:25:59,360 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-06 22:25:59,360 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-06 22:25:59,361 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-06 22:25:59,361 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-06 22:25:59,361 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-06 22:25:59,362 INFO L87 Difference]: Start difference. First operand 504 states and 749 transitions. cyclomatic complexity: 246 Second operand has 3 states, 3 states have (on average 23.666666666666668) internal successors, (71), 3 states have internal predecessors, (71), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-06 22:25:59,383 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-06 22:25:59,384 INFO L93 Difference]: Finished difference Result 504 states and 748 transitions. [2023-11-06 22:25:59,384 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 504 states and 748 transitions. [2023-11-06 22:25:59,390 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 427 [2023-11-06 22:25:59,395 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 504 states to 504 states and 748 transitions. [2023-11-06 22:25:59,395 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 504 [2023-11-06 22:25:59,396 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 504 [2023-11-06 22:25:59,396 INFO L73 IsDeterministic]: Start isDeterministic. Operand 504 states and 748 transitions. [2023-11-06 22:25:59,397 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-06 22:25:59,398 INFO L218 hiAutomatonCegarLoop]: Abstraction has 504 states and 748 transitions. [2023-11-06 22:25:59,399 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 504 states and 748 transitions. [2023-11-06 22:25:59,407 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 504 to 504. [2023-11-06 22:25:59,409 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 504 states, 504 states have (on average 1.4841269841269842) internal successors, (748), 503 states have internal predecessors, (748), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-06 22:25:59,412 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 504 states to 504 states and 748 transitions. [2023-11-06 22:25:59,412 INFO L240 hiAutomatonCegarLoop]: Abstraction has 504 states and 748 transitions. [2023-11-06 22:25:59,412 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-06 22:25:59,415 INFO L428 stractBuchiCegarLoop]: Abstraction has 504 states and 748 transitions. [2023-11-06 22:25:59,416 INFO L335 stractBuchiCegarLoop]: ======== Iteration 6 ============ [2023-11-06 22:25:59,416 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 504 states and 748 transitions. [2023-11-06 22:25:59,420 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 427 [2023-11-06 22:25:59,420 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-06 22:25:59,420 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-06 22:25:59,422 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-06 22:25:59,422 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-06 22:25:59,422 INFO L748 eck$LassoCheckResult]: Stem: 5370#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2; 5371#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~7#1;havoc main_~__retres1~7#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 5476#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret18#1, start_simulation_#t~ret19#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 5477#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 5494#L401 assume 1 == ~m_i~0;~m_st~0 := 0; 5495#L401-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 5305#L406-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 5306#L411-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 5583#L416-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 5584#L421-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 5550#L426-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 5274#L586 assume 0 == ~M_E~0;~M_E~0 := 1; 5275#L586-2 assume !(0 == ~T1_E~0); 5326#L591-1 assume !(0 == ~T2_E~0); 5440#L596-1 assume !(0 == ~T3_E~0); 5441#L601-1 assume !(0 == ~T4_E~0); 5482#L606-1 assume !(0 == ~T5_E~0); 5483#L611-1 assume !(0 == ~E_1~0); 5558#L616-1 assume !(0 == ~E_2~0); 5559#L621-1 assume 0 == ~E_3~0;~E_3~0 := 1; 5201#L626-1 assume !(0 == ~E_4~0); 5202#L631-1 assume !(0 == ~E_5~0); 5365#L636-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 5196#L279 assume 1 == ~m_pc~0; 5197#L280 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 5446#L290 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 5340#is_master_triggered_returnLabel#1 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 5341#L720 assume !(0 != activate_threads_~tmp~1#1); 5505#L720-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 5372#L298 assume !(1 == ~t1_pc~0); 5143#L298-2 is_transmit1_triggered_~__retres1~1#1 := 0; 5144#L309 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 5169#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 5170#L728 assume !(0 != activate_threads_~tmp___0~0#1); 5210#L728-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 5332#L317 assume 1 == ~t2_pc~0; 5333#L318 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 5474#L328 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 5481#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 5381#L736 assume !(0 != activate_threads_~tmp___1~0#1); 5382#L736-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 5547#L336 assume 1 == ~t3_pc~0; 5419#L337 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 5420#L347 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 5116#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 5117#L744 assume !(0 != activate_threads_~tmp___2~0#1); 5513#L744-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 5554#L355 assume !(1 == ~t4_pc~0); 5437#L355-2 is_transmit4_triggered_~__retres1~4#1 := 0; 5292#L366 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 5240#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 5241#L752 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 5220#L752-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 5221#L374 assume 1 == ~t5_pc~0; 5576#L375 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 5356#L385 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 5346#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 5347#L760 assume !(0 != activate_threads_~tmp___4~0#1); 5465#L760-2 havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 5466#L649 assume 1 == ~M_E~0;~M_E~0 := 2; 5595#L649-2 assume !(1 == ~T1_E~0); 5182#L654-1 assume !(1 == ~T2_E~0); 5183#L659-1 assume !(1 == ~T3_E~0); 5380#L664-1 assume !(1 == ~T4_E~0); 5174#L669-1 assume !(1 == ~T5_E~0); 5175#L674-1 assume !(1 == ~E_1~0); 5539#L679-1 assume !(1 == ~E_2~0); 5279#L684-1 assume 1 == ~E_3~0;~E_3~0 := 2; 5280#L689-1 assume !(1 == ~E_4~0); 5433#L694-1 assume !(1 == ~E_5~0); 5431#L699-1 assume { :end_inline_reset_delta_events } true; 5432#L900-2 [2023-11-06 22:25:59,423 INFO L750 eck$LassoCheckResult]: Loop: 5432#L900-2 assume !false; 5601#L901 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 5351#L561-1 assume !false; 5407#L482 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 5399#L439 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 5145#L471 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 5146#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 5268#L486 assume !(0 != eval_~tmp~0#1); 5247#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 5248#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 5570#L586-3 assume 0 == ~M_E~0;~M_E~0 := 1; 5538#L586-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 5448#L591-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 5296#L596-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 5297#L601-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 5461#L606-3 assume !(0 == ~T5_E~0); 5497#L611-3 assume 0 == ~E_1~0;~E_1~0 := 1; 5498#L616-3 assume 0 == ~E_2~0;~E_2~0 := 1; 5190#L621-3 assume 0 == ~E_3~0;~E_3~0 := 1; 5141#L626-3 assume 0 == ~E_4~0;~E_4~0 := 1; 5142#L631-3 assume 0 == ~E_5~0;~E_5~0 := 1; 5147#L636-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 5148#L279-18 assume 1 == ~m_pc~0; 5255#L280-6 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 5256#L290-6 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 5385#is_master_triggered_returnLabel#7 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 5386#L720-18 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 5560#L720-20 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 5464#L298-18 assume 1 == ~t1_pc~0; 5121#L299-6 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 5115#L309-6 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 5304#is_transmit1_triggered_returnLabel#7 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 5322#L728-18 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 5323#L728-20 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 5442#L317-18 assume 1 == ~t2_pc~0; 5357#L318-6 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 5358#L328-6 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 5472#is_transmit2_triggered_returnLabel#7 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 5307#L736-18 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 5308#L736-20 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 5563#L336-18 assume 1 == ~t3_pc~0; 5543#L337-6 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 5544#L347-6 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 5499#is_transmit3_triggered_returnLabel#7 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 5408#L744-18 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 5249#L744-20 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 5250#L355-18 assume 1 == ~t4_pc~0; 5523#L356-6 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 5512#L366-6 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 5413#is_transmit4_triggered_returnLabel#7 activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 5414#L752-18 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 5342#L752-20 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 5343#L374-18 assume 1 == ~t5_pc~0; 5553#L375-6 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 5404#L385-6 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 5344#is_transmit5_triggered_returnLabel#7 activate_threads_#t~ret16#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 5345#L760-18 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 5506#L760-20 havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 5507#L649-3 assume 1 == ~M_E~0;~M_E~0 := 2; 5418#L649-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 5398#L654-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 5259#L659-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 5260#L664-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 5149#L669-3 assume !(1 == ~T5_E~0); 5150#L674-3 assume 1 == ~E_1~0;~E_1~0 := 2; 5139#L679-3 assume 1 == ~E_2~0;~E_2~0 := 2; 5140#L684-3 assume 1 == ~E_3~0;~E_3~0 := 2; 5099#L689-3 assume 1 == ~E_4~0;~E_4~0 := 2; 5100#L694-3 assume 1 == ~E_5~0;~E_5~0 := 2; 5134#L699-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 5135#L439-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 5137#L471-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 5447#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret18#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret18#1;havoc start_simulation_#t~ret18#1; 5430#L919 assume !(0 == start_simulation_~tmp~3#1); 5152#L919-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret17#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 5529#L439-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 5128#L471-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 5166#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret17#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret17#1;havoc stop_simulation_#t~ret17#1; 5167#L874 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 5426#L881 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 5564#stop_simulation_returnLabel#1 start_simulation_#t~ret19#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret17#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret19#1;havoc start_simulation_#t~ret19#1; 5552#L932 assume !(0 != start_simulation_~tmp___0~1#1); 5432#L900-2 [2023-11-06 22:25:59,424 INFO L145 PredicateUnifier]: Initialized classic predicate unifier [2023-11-06 22:25:59,424 INFO L85 PathProgramCache]: Analyzing trace with hash 1917465066, now seen corresponding path program 1 times [2023-11-06 22:25:59,425 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-06 22:25:59,425 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1042468329] [2023-11-06 22:25:59,425 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-06 22:25:59,425 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-06 22:25:59,451 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-06 22:25:59,494 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-06 22:25:59,495 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-06 22:25:59,495 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1042468329] [2023-11-06 22:25:59,495 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1042468329] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-06 22:25:59,496 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-06 22:25:59,496 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2023-11-06 22:25:59,496 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1985320542] [2023-11-06 22:25:59,496 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-06 22:25:59,496 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-06 22:25:59,497 INFO L145 PredicateUnifier]: Initialized classic predicate unifier [2023-11-06 22:25:59,497 INFO L85 PathProgramCache]: Analyzing trace with hash -1398059989, now seen corresponding path program 2 times [2023-11-06 22:25:59,498 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-06 22:25:59,502 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2027135070] [2023-11-06 22:25:59,503 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-06 22:25:59,503 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-06 22:25:59,519 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-06 22:25:59,575 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-06 22:25:59,575 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-06 22:25:59,575 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2027135070] [2023-11-06 22:25:59,576 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2027135070] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-06 22:25:59,577 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-06 22:25:59,577 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2023-11-06 22:25:59,577 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1087176508] [2023-11-06 22:25:59,577 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-06 22:25:59,578 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-06 22:25:59,578 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-06 22:25:59,579 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-06 22:25:59,579 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-06 22:25:59,579 INFO L87 Difference]: Start difference. First operand 504 states and 748 transitions. cyclomatic complexity: 245 Second operand has 3 states, 3 states have (on average 23.666666666666668) internal successors, (71), 2 states have internal predecessors, (71), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-06 22:25:59,690 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-06 22:25:59,690 INFO L93 Difference]: Finished difference Result 887 states and 1304 transitions. [2023-11-06 22:25:59,690 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 887 states and 1304 transitions. [2023-11-06 22:25:59,700 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 810 [2023-11-06 22:25:59,727 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 887 states to 887 states and 1304 transitions. [2023-11-06 22:25:59,727 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 887 [2023-11-06 22:25:59,729 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 887 [2023-11-06 22:25:59,729 INFO L73 IsDeterministic]: Start isDeterministic. Operand 887 states and 1304 transitions. [2023-11-06 22:25:59,731 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-06 22:25:59,731 INFO L218 hiAutomatonCegarLoop]: Abstraction has 887 states and 1304 transitions. [2023-11-06 22:25:59,734 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 887 states and 1304 transitions. [2023-11-06 22:25:59,756 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 887 to 887. [2023-11-06 22:25:59,759 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 887 states, 887 states have (on average 1.4701240135287486) internal successors, (1304), 886 states have internal predecessors, (1304), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-06 22:25:59,765 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 887 states to 887 states and 1304 transitions. [2023-11-06 22:25:59,765 INFO L240 hiAutomatonCegarLoop]: Abstraction has 887 states and 1304 transitions. [2023-11-06 22:25:59,766 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-06 22:25:59,768 INFO L428 stractBuchiCegarLoop]: Abstraction has 887 states and 1304 transitions. [2023-11-06 22:25:59,768 INFO L335 stractBuchiCegarLoop]: ======== Iteration 7 ============ [2023-11-06 22:25:59,769 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 887 states and 1304 transitions. [2023-11-06 22:25:59,777 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 810 [2023-11-06 22:25:59,777 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-06 22:25:59,777 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-06 22:25:59,779 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-06 22:25:59,779 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-06 22:25:59,780 INFO L748 eck$LassoCheckResult]: Stem: 6769#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2; 6770#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~7#1;havoc main_~__retres1~7#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 6878#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret18#1, start_simulation_#t~ret19#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 6879#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 6896#L401 assume 1 == ~m_i~0;~m_st~0 := 0; 6897#L401-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 6704#L406-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 6705#L411-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 6987#L416-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 6988#L421-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 6954#L426-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 6676#L586 assume !(0 == ~M_E~0); 6677#L586-2 assume !(0 == ~T1_E~0); 6725#L591-1 assume !(0 == ~T2_E~0); 6842#L596-1 assume !(0 == ~T3_E~0); 6843#L601-1 assume !(0 == ~T4_E~0); 6884#L606-1 assume !(0 == ~T5_E~0); 6885#L611-1 assume !(0 == ~E_1~0); 6961#L616-1 assume !(0 == ~E_2~0); 6962#L621-1 assume 0 == ~E_3~0;~E_3~0 := 1; 6601#L626-1 assume !(0 == ~E_4~0); 6602#L631-1 assume !(0 == ~E_5~0); 6764#L636-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 6596#L279 assume !(1 == ~m_pc~0); 6598#L279-2 is_master_triggered_~__retres1~0#1 := 0; 6908#L290 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 6739#is_master_triggered_returnLabel#1 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 6740#L720 assume !(0 != activate_threads_~tmp~1#1); 6907#L720-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 6771#L298 assume !(1 == ~t1_pc~0); 6545#L298-2 is_transmit1_triggered_~__retres1~1#1 := 0; 6546#L309 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 6572#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 6573#L728 assume !(0 != activate_threads_~tmp___0~0#1); 6610#L728-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 6731#L317 assume 1 == ~t2_pc~0; 6732#L318 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 6877#L328 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 6883#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 6781#L736 assume !(0 != activate_threads_~tmp___1~0#1); 6782#L736-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 6951#L336 assume 1 == ~t3_pc~0; 6820#L337 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 6821#L347 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 6516#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 6517#L744 assume !(0 != activate_threads_~tmp___2~0#1); 6916#L744-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 6958#L355 assume !(1 == ~t4_pc~0); 6841#L355-2 is_transmit4_triggered_~__retres1~4#1 := 0; 6693#L366 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 6640#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 6641#L752 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 6623#L752-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 6624#L374 assume 1 == ~t5_pc~0; 6980#L375 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 6758#L385 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 6745#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 6746#L760 assume !(0 != activate_threads_~tmp___4~0#1); 6866#L760-2 havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 6867#L649 assume !(1 == ~M_E~0); 7000#L649-2 assume !(1 == ~T1_E~0); 6582#L654-1 assume !(1 == ~T2_E~0); 6583#L659-1 assume !(1 == ~T3_E~0); 6779#L664-1 assume !(1 == ~T4_E~0); 6574#L669-1 assume !(1 == ~T5_E~0); 6575#L674-1 assume !(1 == ~E_1~0); 6942#L679-1 assume !(1 == ~E_2~0); 6678#L684-1 assume 1 == ~E_3~0;~E_3~0 := 2; 6679#L689-1 assume !(1 == ~E_4~0); 6836#L694-1 assume !(1 == ~E_5~0); 6833#L699-1 assume { :end_inline_reset_delta_events } true; 6834#L900-2 [2023-11-06 22:25:59,781 INFO L750 eck$LassoCheckResult]: Loop: 6834#L900-2 assume !false; 7007#L901 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 6750#L561-1 assume !false; 6808#L482 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 6799#L439 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 6543#L471 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 6544#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 6667#L486 assume !(0 != eval_~tmp~0#1); 6647#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 6648#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 6974#L586-3 assume !(0 == ~M_E~0); 6941#L586-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 6849#L591-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 6695#L596-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 6696#L601-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 6862#L606-3 assume !(0 == ~T5_E~0); 6899#L611-3 assume 0 == ~E_1~0;~E_1~0 := 1; 6900#L616-3 assume 0 == ~E_2~0;~E_2~0 := 1; 6590#L621-3 assume 0 == ~E_3~0;~E_3~0 := 1; 6541#L626-3 assume 0 == ~E_4~0;~E_4~0 := 1; 6542#L631-3 assume 0 == ~E_5~0;~E_5~0 := 1; 6547#L636-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 6548#L279-18 assume !(1 == ~m_pc~0); 6656#L279-20 is_master_triggered_~__retres1~0#1 := 0; 6791#L290-6 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 6784#is_master_triggered_returnLabel#7 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 6785#L720-18 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 6963#L720-20 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 6865#L298-18 assume !(1 == ~t1_pc~0); 6514#L298-20 is_transmit1_triggered_~__retres1~1#1 := 0; 6515#L309-6 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 6703#is_transmit1_triggered_returnLabel#7 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 6721#L728-18 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 6722#L728-20 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 6844#L317-18 assume 1 == ~t2_pc~0; 6754#L318-6 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 6755#L328-6 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 6873#is_transmit2_triggered_returnLabel#7 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 6706#L736-18 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 6707#L736-20 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 6966#L336-18 assume 1 == ~t3_pc~0; 6946#L337-6 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 6947#L347-6 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 6901#is_transmit3_triggered_returnLabel#7 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 6807#L744-18 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 6649#L744-20 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 6650#L355-18 assume !(1 == ~t4_pc~0); 6914#L355-20 is_transmit4_triggered_~__retres1~4#1 := 0; 6915#L366-6 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 6812#is_transmit4_triggered_returnLabel#7 activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 6813#L752-18 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 6741#L752-20 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 6742#L374-18 assume !(1 == ~t5_pc~0); 6928#L374-20 is_transmit5_triggered_~__retres1~5#1 := 0; 6804#L385-6 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 6743#is_transmit5_triggered_returnLabel#7 activate_threads_#t~ret16#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 6744#L760-18 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 6909#L760-20 havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 6910#L649-3 assume !(1 == ~M_E~0); 6818#L649-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 6798#L654-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 6658#L659-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 6659#L664-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 6549#L669-3 assume !(1 == ~T5_E~0); 6550#L674-3 assume 1 == ~E_1~0;~E_1~0 := 2; 6539#L679-3 assume 1 == ~E_2~0;~E_2~0 := 2; 6540#L684-3 assume 1 == ~E_3~0;~E_3~0 := 2; 6499#L689-3 assume 1 == ~E_4~0;~E_4~0 := 2; 6500#L694-3 assume 1 == ~E_5~0;~E_5~0 := 2; 6534#L699-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 6535#L439-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 6537#L471-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 6848#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret18#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret18#1;havoc start_simulation_#t~ret18#1; 6832#L919 assume !(0 == start_simulation_~tmp~3#1); 6552#L919-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret17#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 6932#L439-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 6528#L471-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 6566#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret17#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret17#1;havoc stop_simulation_#t~ret17#1; 6567#L874 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 6826#L881 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 6967#stop_simulation_returnLabel#1 start_simulation_#t~ret19#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret17#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret19#1;havoc start_simulation_#t~ret19#1; 6955#L932 assume !(0 != start_simulation_~tmp___0~1#1); 6834#L900-2 [2023-11-06 22:25:59,782 INFO L145 PredicateUnifier]: Initialized classic predicate unifier [2023-11-06 22:25:59,782 INFO L85 PathProgramCache]: Analyzing trace with hash -484678139, now seen corresponding path program 1 times [2023-11-06 22:25:59,782 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-06 22:25:59,782 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2084898421] [2023-11-06 22:25:59,784 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-06 22:25:59,785 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-06 22:25:59,804 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-06 22:25:59,876 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-06 22:25:59,877 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-06 22:25:59,877 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2084898421] [2023-11-06 22:25:59,877 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2084898421] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-06 22:25:59,877 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-06 22:25:59,878 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-06 22:25:59,878 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1007922052] [2023-11-06 22:25:59,878 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-06 22:25:59,879 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-06 22:25:59,879 INFO L145 PredicateUnifier]: Initialized classic predicate unifier [2023-11-06 22:25:59,880 INFO L85 PathProgramCache]: Analyzing trace with hash -785849181, now seen corresponding path program 1 times [2023-11-06 22:25:59,880 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-06 22:25:59,880 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [738165606] [2023-11-06 22:25:59,880 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-06 22:25:59,881 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-06 22:25:59,899 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-06 22:25:59,967 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-06 22:25:59,967 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-06 22:25:59,967 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [738165606] [2023-11-06 22:25:59,967 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [738165606] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-06 22:25:59,968 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-06 22:25:59,968 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2023-11-06 22:25:59,968 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1084260482] [2023-11-06 22:25:59,968 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-06 22:25:59,969 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-06 22:25:59,969 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-06 22:25:59,969 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2023-11-06 22:25:59,970 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2023-11-06 22:25:59,970 INFO L87 Difference]: Start difference. First operand 887 states and 1304 transitions. cyclomatic complexity: 418 Second operand has 4 states, 4 states have (on average 17.75) internal successors, (71), 3 states have internal predecessors, (71), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-06 22:26:00,150 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-06 22:26:00,151 INFO L93 Difference]: Finished difference Result 1620 states and 2381 transitions. [2023-11-06 22:26:00,151 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1620 states and 2381 transitions. [2023-11-06 22:26:00,171 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 1532 [2023-11-06 22:26:00,188 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1620 states to 1620 states and 2381 transitions. [2023-11-06 22:26:00,189 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1620 [2023-11-06 22:26:00,191 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1620 [2023-11-06 22:26:00,191 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1620 states and 2381 transitions. [2023-11-06 22:26:00,194 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-06 22:26:00,194 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1620 states and 2381 transitions. [2023-11-06 22:26:00,197 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1620 states and 2381 transitions. [2023-11-06 22:26:00,234 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1620 to 1618. [2023-11-06 22:26:00,239 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1618 states, 1618 states have (on average 1.4703337453646477) internal successors, (2379), 1617 states have internal predecessors, (2379), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-06 22:26:00,249 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1618 states to 1618 states and 2379 transitions. [2023-11-06 22:26:00,249 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1618 states and 2379 transitions. [2023-11-06 22:26:00,250 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2023-11-06 22:26:00,250 INFO L428 stractBuchiCegarLoop]: Abstraction has 1618 states and 2379 transitions. [2023-11-06 22:26:00,251 INFO L335 stractBuchiCegarLoop]: ======== Iteration 8 ============ [2023-11-06 22:26:00,251 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1618 states and 2379 transitions. [2023-11-06 22:26:00,264 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 1532 [2023-11-06 22:26:00,264 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-06 22:26:00,265 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-06 22:26:00,266 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-06 22:26:00,267 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-06 22:26:00,267 INFO L748 eck$LassoCheckResult]: Stem: 9293#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2; 9294#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~7#1;havoc main_~__retres1~7#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 9404#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret18#1, start_simulation_#t~ret19#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 9405#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 9422#L401 assume 1 == ~m_i~0;~m_st~0 := 0; 9423#L401-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 9227#L406-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 9228#L411-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 9529#L416-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 9530#L421-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 9491#L426-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 9197#L586 assume !(0 == ~M_E~0); 9198#L586-2 assume !(0 == ~T1_E~0); 9248#L591-1 assume !(0 == ~T2_E~0); 9367#L596-1 assume !(0 == ~T3_E~0); 9368#L601-1 assume !(0 == ~T4_E~0); 9409#L606-1 assume !(0 == ~T5_E~0); 9410#L611-1 assume !(0 == ~E_1~0); 9499#L616-1 assume !(0 == ~E_2~0); 9500#L621-1 assume !(0 == ~E_3~0); 9121#L626-1 assume !(0 == ~E_4~0); 9122#L631-1 assume !(0 == ~E_5~0); 9288#L636-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 9118#L279 assume !(1 == ~m_pc~0); 9120#L279-2 is_master_triggered_~__retres1~0#1 := 0; 9439#L290 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 9262#is_master_triggered_returnLabel#1 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 9263#L720 assume !(0 != activate_threads_~tmp~1#1); 9438#L720-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 9295#L298 assume !(1 == ~t1_pc~0); 9064#L298-2 is_transmit1_triggered_~__retres1~1#1 := 0; 9065#L309 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 9090#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 9091#L728 assume !(0 != activate_threads_~tmp___0~0#1); 9130#L728-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 9254#L317 assume 1 == ~t2_pc~0; 9255#L318 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 9402#L328 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 9408#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 9305#L736 assume !(0 != activate_threads_~tmp___1~0#1); 9306#L736-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 9484#L336 assume 1 == ~t3_pc~0; 9346#L337 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 9347#L347 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 9035#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 9036#L744 assume !(0 != activate_threads_~tmp___2~0#1); 9447#L744-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 9495#L355 assume !(1 == ~t4_pc~0); 9366#L355-2 is_transmit4_triggered_~__retres1~4#1 := 0; 9216#L366 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 9160#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 9161#L752 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 9143#L752-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 9144#L374 assume 1 == ~t5_pc~0; 9520#L375 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 9282#L385 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 9268#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 9269#L760 assume !(0 != activate_threads_~tmp___4~0#1); 9391#L760-2 havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 9392#L649 assume !(1 == ~M_E~0); 9551#L649-2 assume !(1 == ~T1_E~0); 9100#L654-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 9101#L659-1 assume !(1 == ~T3_E~0); 9646#L664-1 assume !(1 == ~T4_E~0); 9645#L669-1 assume !(1 == ~T5_E~0); 9644#L674-1 assume !(1 == ~E_1~0); 9643#L679-1 assume !(1 == ~E_2~0); 9642#L684-1 assume 1 == ~E_3~0;~E_3~0 := 2; 9201#L689-1 assume !(1 == ~E_4~0); 9361#L694-1 assume !(1 == ~E_5~0); 9629#L699-1 assume { :end_inline_reset_delta_events } true; 9621#L900-2 [2023-11-06 22:26:00,268 INFO L750 eck$LassoCheckResult]: Loop: 9621#L900-2 assume !false; 9615#L901 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 9611#L561-1 assume !false; 9610#L482 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 9608#L439 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 9603#L471 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 9602#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 9600#L486 assume !(0 != eval_~tmp~0#1); 9599#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 9598#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 9597#L586-3 assume !(0 == ~M_E~0); 9596#L586-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 9593#L591-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 9594#L596-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 10599#L601-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 10598#L606-3 assume !(0 == ~T5_E~0); 10597#L611-3 assume 0 == ~E_1~0;~E_1~0 := 1; 10596#L616-3 assume 0 == ~E_2~0;~E_2~0 := 1; 10595#L621-3 assume !(0 == ~E_3~0); 10594#L626-3 assume 0 == ~E_4~0;~E_4~0 := 1; 10593#L631-3 assume 0 == ~E_5~0;~E_5~0 := 1; 10592#L636-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 10591#L279-18 assume !(1 == ~m_pc~0); 10589#L279-20 is_master_triggered_~__retres1~0#1 := 0; 10588#L290-6 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 10587#is_master_triggered_returnLabel#7 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 10586#L720-18 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 10585#L720-20 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 10584#L298-18 assume !(1 == ~t1_pc~0); 10582#L298-20 is_transmit1_triggered_~__retres1~1#1 := 0; 10581#L309-6 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 10580#is_transmit1_triggered_returnLabel#7 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 10579#L728-18 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 10578#L728-20 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 10577#L317-18 assume !(1 == ~t2_pc~0); 10576#L317-20 is_transmit2_triggered_~__retres1~2#1 := 0; 10574#L328-6 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 10573#is_transmit2_triggered_returnLabel#7 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 10572#L736-18 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 10571#L736-20 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 10570#L336-18 assume !(1 == ~t3_pc~0); 10568#L336-20 is_transmit3_triggered_~__retres1~3#1 := 0; 10567#L347-6 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 10566#is_transmit3_triggered_returnLabel#7 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 10565#L744-18 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 10564#L744-20 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 10563#L355-18 assume 1 == ~t4_pc~0; 10561#L356-6 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 10560#L366-6 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 10354#is_transmit4_triggered_returnLabel#7 activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 9828#L752-18 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 9829#L752-20 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 9492#L374-18 assume 1 == ~t5_pc~0; 9493#L375-6 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 9329#L385-6 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 9266#is_transmit5_triggered_returnLabel#7 activate_threads_#t~ret16#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 9267#L760-18 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 9440#L760-20 havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 9441#L649-3 assume !(1 == ~M_E~0); 9343#L649-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 9323#L654-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 9178#L659-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 9179#L664-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 9070#L669-3 assume !(1 == ~T5_E~0); 9071#L674-3 assume 1 == ~E_1~0;~E_1~0 := 2; 9058#L679-3 assume 1 == ~E_2~0;~E_2~0 := 2; 9059#L684-3 assume 1 == ~E_3~0;~E_3~0 := 2; 9018#L689-3 assume 1 == ~E_4~0;~E_4~0 := 2; 9019#L694-3 assume 1 == ~E_5~0;~E_5~0 := 2; 9053#L699-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 9054#L439-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 9056#L471-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 9373#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret18#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret18#1;havoc start_simulation_#t~ret18#1; 9356#L919 assume !(0 == start_simulation_~tmp~3#1); 9069#L919-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret17#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 9571#L439-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 9677#L471-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 9675#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret17#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret17#1;havoc stop_simulation_#t~ret17#1; 9668#L874 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 9656#L881 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 9640#stop_simulation_returnLabel#1 start_simulation_#t~ret19#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret17#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret19#1;havoc start_simulation_#t~ret19#1; 9628#L932 assume !(0 != start_simulation_~tmp___0~1#1); 9621#L900-2 [2023-11-06 22:26:00,268 INFO L145 PredicateUnifier]: Initialized classic predicate unifier [2023-11-06 22:26:00,269 INFO L85 PathProgramCache]: Analyzing trace with hash 1446688901, now seen corresponding path program 1 times [2023-11-06 22:26:00,269 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-06 22:26:00,269 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [858793462] [2023-11-06 22:26:00,269 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-06 22:26:00,269 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-06 22:26:00,282 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-06 22:26:00,330 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-06 22:26:00,330 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-06 22:26:00,330 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [858793462] [2023-11-06 22:26:00,330 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [858793462] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-06 22:26:00,330 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-06 22:26:00,331 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-06 22:26:00,331 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1150005725] [2023-11-06 22:26:00,331 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-06 22:26:00,331 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-06 22:26:00,332 INFO L145 PredicateUnifier]: Initialized classic predicate unifier [2023-11-06 22:26:00,332 INFO L85 PathProgramCache]: Analyzing trace with hash 259039073, now seen corresponding path program 1 times [2023-11-06 22:26:00,332 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-06 22:26:00,332 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1200949322] [2023-11-06 22:26:00,332 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-06 22:26:00,333 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-06 22:26:00,345 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-06 22:26:00,390 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-06 22:26:00,390 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-06 22:26:00,391 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1200949322] [2023-11-06 22:26:00,391 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1200949322] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-06 22:26:00,391 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-06 22:26:00,391 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2023-11-06 22:26:00,391 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [107956037] [2023-11-06 22:26:00,392 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-06 22:26:00,392 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-06 22:26:00,392 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-06 22:26:00,392 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2023-11-06 22:26:00,392 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2023-11-06 22:26:00,393 INFO L87 Difference]: Start difference. First operand 1618 states and 2379 transitions. cyclomatic complexity: 763 Second operand has 4 states, 4 states have (on average 17.75) internal successors, (71), 3 states have internal predecessors, (71), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-06 22:26:00,627 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-06 22:26:00,627 INFO L93 Difference]: Finished difference Result 4476 states and 6484 transitions. [2023-11-06 22:26:00,628 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 4476 states and 6484 transitions. [2023-11-06 22:26:00,677 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 4188 [2023-11-06 22:26:00,721 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 4476 states to 4476 states and 6484 transitions. [2023-11-06 22:26:00,721 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 4476 [2023-11-06 22:26:00,731 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 4476 [2023-11-06 22:26:00,731 INFO L73 IsDeterministic]: Start isDeterministic. Operand 4476 states and 6484 transitions. [2023-11-06 22:26:00,738 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-06 22:26:00,738 INFO L218 hiAutomatonCegarLoop]: Abstraction has 4476 states and 6484 transitions. [2023-11-06 22:26:00,745 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 4476 states and 6484 transitions. [2023-11-06 22:26:00,871 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 4476 to 4234. [2023-11-06 22:26:00,881 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 4234 states, 4234 states have (on average 1.4553613604156825) internal successors, (6162), 4233 states have internal predecessors, (6162), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-06 22:26:00,903 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 4234 states to 4234 states and 6162 transitions. [2023-11-06 22:26:00,903 INFO L240 hiAutomatonCegarLoop]: Abstraction has 4234 states and 6162 transitions. [2023-11-06 22:26:00,903 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2023-11-06 22:26:00,904 INFO L428 stractBuchiCegarLoop]: Abstraction has 4234 states and 6162 transitions. [2023-11-06 22:26:00,904 INFO L335 stractBuchiCegarLoop]: ======== Iteration 9 ============ [2023-11-06 22:26:00,904 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 4234 states and 6162 transitions. [2023-11-06 22:26:00,934 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 4130 [2023-11-06 22:26:00,934 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-06 22:26:00,934 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-06 22:26:00,936 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-06 22:26:00,936 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-06 22:26:00,936 INFO L748 eck$LassoCheckResult]: Stem: 15403#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2; 15404#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~7#1;havoc main_~__retres1~7#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 15523#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret18#1, start_simulation_#t~ret19#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 15524#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 15541#L401 assume 1 == ~m_i~0;~m_st~0 := 0; 15542#L401-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 15337#L406-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 15338#L411-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 15655#L416-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 15656#L421-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 15614#L426-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 15300#L586 assume !(0 == ~M_E~0); 15301#L586-2 assume !(0 == ~T1_E~0); 15358#L591-1 assume !(0 == ~T2_E~0); 15481#L596-1 assume !(0 == ~T3_E~0); 15482#L601-1 assume !(0 == ~T4_E~0); 15529#L606-1 assume !(0 == ~T5_E~0); 15530#L611-1 assume !(0 == ~E_1~0); 15623#L616-1 assume !(0 == ~E_2~0); 15624#L621-1 assume !(0 == ~E_3~0); 15226#L626-1 assume !(0 == ~E_4~0); 15227#L631-1 assume !(0 == ~E_5~0); 15396#L636-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 15222#L279 assume !(1 == ~m_pc~0); 15223#L279-2 is_master_triggered_~__retres1~0#1 := 0; 15555#L290 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 15371#is_master_triggered_returnLabel#1 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 15372#L720 assume !(0 != activate_threads_~tmp~1#1); 15554#L720-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 15405#L298 assume !(1 == ~t1_pc~0); 15168#L298-2 is_transmit1_triggered_~__retres1~1#1 := 0; 15169#L309 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 15194#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 15195#L728 assume !(0 != activate_threads_~tmp___0~0#1); 15235#L728-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 15364#L317 assume !(1 == ~t2_pc~0); 15365#L317-2 is_transmit2_triggered_~__retres1~2#1 := 0; 15577#L328 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 15528#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 15414#L736 assume !(0 != activate_threads_~tmp___1~0#1); 15415#L736-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 15611#L336 assume 1 == ~t3_pc~0; 15456#L337 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 15457#L347 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 15141#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 15142#L744 assume !(0 != activate_threads_~tmp___2~0#1); 15564#L744-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 15619#L355 assume !(1 == ~t4_pc~0); 15478#L355-2 is_transmit4_triggered_~__retres1~4#1 := 0; 15323#L366 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 15265#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 15266#L752 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 15245#L752-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 15246#L374 assume 1 == ~t5_pc~0; 15648#L375 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 15387#L385 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 15377#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 15378#L760 assume !(0 != activate_threads_~tmp___4~0#1); 15511#L760-2 havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 15512#L649 assume !(1 == ~M_E~0); 15680#L649-2 assume !(1 == ~T1_E~0); 15206#L654-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 15207#L659-1 assume !(1 == ~T3_E~0); 15413#L664-1 assume !(1 == ~T4_E~0); 15198#L669-1 assume !(1 == ~T5_E~0); 15199#L674-1 assume !(1 == ~E_1~0); 17217#L679-1 assume !(1 == ~E_2~0); 17215#L684-1 assume 1 == ~E_3~0;~E_3~0 := 2; 15307#L689-1 assume !(1 == ~E_4~0); 15473#L694-1 assume !(1 == ~E_5~0); 15471#L699-1 assume { :end_inline_reset_delta_events } true; 15472#L900-2 [2023-11-06 22:26:00,937 INFO L750 eck$LassoCheckResult]: Loop: 15472#L900-2 assume !false; 15694#L901 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 15382#L561-1 assume !false; 15442#L482 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 15434#L439 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 15170#L471 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 15171#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 15293#L486 assume !(0 != eval_~tmp~0#1); 15295#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 19251#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 15673#L586-3 assume !(0 == ~M_E~0); 15674#L586-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 19067#L591-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 19066#L596-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 19065#L601-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 19064#L606-3 assume !(0 == ~T5_E~0); 19063#L611-3 assume 0 == ~E_1~0;~E_1~0 := 1; 19062#L616-3 assume 0 == ~E_2~0;~E_2~0 := 1; 19061#L621-3 assume !(0 == ~E_3~0); 19060#L626-3 assume 0 == ~E_4~0;~E_4~0 := 1; 19059#L631-3 assume 0 == ~E_5~0;~E_5~0 := 1; 19058#L636-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 19057#L279-18 assume !(1 == ~m_pc~0); 19056#L279-20 is_master_triggered_~__retres1~0#1 := 0; 19055#L290-6 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 19054#is_master_triggered_returnLabel#7 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 19053#L720-18 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 19052#L720-20 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 19051#L298-18 assume !(1 == ~t1_pc~0); 19049#L298-20 is_transmit1_triggered_~__retres1~1#1 := 0; 19048#L309-6 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 19047#is_transmit1_triggered_returnLabel#7 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 19046#L728-18 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 19045#L728-20 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 19044#L317-18 assume !(1 == ~t2_pc~0); 19043#L317-20 is_transmit2_triggered_~__retres1~2#1 := 0; 19042#L328-6 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 19041#is_transmit2_triggered_returnLabel#7 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 19040#L736-18 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 19039#L736-20 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 19038#L336-18 assume !(1 == ~t3_pc~0); 19036#L336-20 is_transmit3_triggered_~__retres1~3#1 := 0; 19035#L347-6 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 19034#is_transmit3_triggered_returnLabel#7 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 19033#L744-18 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 19032#L744-20 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 19031#L355-18 assume 1 == ~t4_pc~0; 19027#L356-6 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 19026#L366-6 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 19025#is_transmit4_triggered_returnLabel#7 activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 19024#L752-18 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 19023#L752-20 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 19022#L374-18 assume 1 == ~t5_pc~0; 15690#L375-6 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 15439#L385-6 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 15375#is_transmit5_triggered_returnLabel#7 activate_threads_#t~ret16#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 15376#L760-18 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 15556#L760-20 havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 15557#L649-3 assume !(1 == ~M_E~0); 15688#L649-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 19125#L654-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 17692#L659-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 19124#L664-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 19123#L669-3 assume !(1 == ~T5_E~0); 19122#L674-3 assume 1 == ~E_1~0;~E_1~0 := 2; 19121#L679-3 assume 1 == ~E_2~0;~E_2~0 := 2; 19120#L684-3 assume 1 == ~E_3~0;~E_3~0 := 2; 17659#L689-3 assume 1 == ~E_4~0;~E_4~0 := 2; 19119#L694-3 assume 1 == ~E_5~0;~E_5~0 := 2; 19118#L699-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 15671#L439-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 15162#L471-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 15491#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret18#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret18#1;havoc start_simulation_#t~ret18#1; 15469#L919 assume !(0 == start_simulation_~tmp~3#1); 15177#L919-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret17#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 15585#L439-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 15153#L471-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 15191#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret17#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret17#1;havoc stop_simulation_#t~ret17#1; 15192#L874 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 15464#L881 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 15629#stop_simulation_returnLabel#1 start_simulation_#t~ret19#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret17#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret19#1;havoc start_simulation_#t~ret19#1; 15616#L932 assume !(0 != start_simulation_~tmp___0~1#1); 15472#L900-2 [2023-11-06 22:26:00,937 INFO L145 PredicateUnifier]: Initialized classic predicate unifier [2023-11-06 22:26:00,938 INFO L85 PathProgramCache]: Analyzing trace with hash -318127708, now seen corresponding path program 1 times [2023-11-06 22:26:00,938 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-06 22:26:00,938 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1686613915] [2023-11-06 22:26:00,938 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-06 22:26:00,938 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-06 22:26:00,950 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-06 22:26:01,002 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-06 22:26:01,003 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-06 22:26:01,003 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1686613915] [2023-11-06 22:26:01,003 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1686613915] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-06 22:26:01,003 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-06 22:26:01,004 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-06 22:26:01,004 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1884750935] [2023-11-06 22:26:01,004 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-06 22:26:01,004 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-06 22:26:01,005 INFO L145 PredicateUnifier]: Initialized classic predicate unifier [2023-11-06 22:26:01,005 INFO L85 PathProgramCache]: Analyzing trace with hash 259039073, now seen corresponding path program 2 times [2023-11-06 22:26:01,005 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-06 22:26:01,005 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1438139768] [2023-11-06 22:26:01,006 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-06 22:26:01,006 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-06 22:26:01,019 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-06 22:26:01,071 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-06 22:26:01,071 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-06 22:26:01,071 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1438139768] [2023-11-06 22:26:01,071 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1438139768] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-06 22:26:01,071 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-06 22:26:01,072 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2023-11-06 22:26:01,072 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1547465677] [2023-11-06 22:26:01,072 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-06 22:26:01,072 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-06 22:26:01,073 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-06 22:26:01,073 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2023-11-06 22:26:01,073 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2023-11-06 22:26:01,073 INFO L87 Difference]: Start difference. First operand 4234 states and 6162 transitions. cyclomatic complexity: 1932 Second operand has 4 states, 4 states have (on average 17.75) internal successors, (71), 3 states have internal predecessors, (71), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-06 22:26:01,383 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-06 22:26:01,383 INFO L93 Difference]: Finished difference Result 11567 states and 16676 transitions. [2023-11-06 22:26:01,383 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 11567 states and 16676 transitions. [2023-11-06 22:26:01,493 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 11004 [2023-11-06 22:26:01,595 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 11567 states to 11567 states and 16676 transitions. [2023-11-06 22:26:01,595 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 11567 [2023-11-06 22:26:01,609 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 11567 [2023-11-06 22:26:01,610 INFO L73 IsDeterministic]: Start isDeterministic. Operand 11567 states and 16676 transitions. [2023-11-06 22:26:01,628 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-06 22:26:01,628 INFO L218 hiAutomatonCegarLoop]: Abstraction has 11567 states and 16676 transitions. [2023-11-06 22:26:01,645 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 11567 states and 16676 transitions. [2023-11-06 22:26:01,944 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 11567 to 10883. [2023-11-06 22:26:01,973 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 10883 states, 10883 states have (on average 1.450335385463567) internal successors, (15784), 10882 states have internal predecessors, (15784), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-06 22:26:02,012 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 10883 states to 10883 states and 15784 transitions. [2023-11-06 22:26:02,012 INFO L240 hiAutomatonCegarLoop]: Abstraction has 10883 states and 15784 transitions. [2023-11-06 22:26:02,013 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2023-11-06 22:26:02,015 INFO L428 stractBuchiCegarLoop]: Abstraction has 10883 states and 15784 transitions. [2023-11-06 22:26:02,015 INFO L335 stractBuchiCegarLoop]: ======== Iteration 10 ============ [2023-11-06 22:26:02,015 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 10883 states and 15784 transitions. [2023-11-06 22:26:02,148 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 10740 [2023-11-06 22:26:02,148 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-06 22:26:02,148 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-06 22:26:02,150 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-06 22:26:02,150 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-06 22:26:02,150 INFO L748 eck$LassoCheckResult]: Stem: 31218#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2; 31219#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~7#1;havoc main_~__retres1~7#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 31343#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret18#1, start_simulation_#t~ret19#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 31344#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 31363#L401 assume 1 == ~m_i~0;~m_st~0 := 0; 31364#L401-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 31150#L406-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 31151#L411-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 31500#L416-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 31501#L421-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 31448#L426-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 31116#L586 assume !(0 == ~M_E~0); 31117#L586-2 assume !(0 == ~T1_E~0); 31172#L591-1 assume !(0 == ~T2_E~0); 31297#L596-1 assume !(0 == ~T3_E~0); 31298#L601-1 assume !(0 == ~T4_E~0); 31349#L606-1 assume !(0 == ~T5_E~0); 31350#L611-1 assume !(0 == ~E_1~0); 31462#L616-1 assume !(0 == ~E_2~0); 31463#L621-1 assume !(0 == ~E_3~0); 31038#L626-1 assume !(0 == ~E_4~0); 31039#L631-1 assume !(0 == ~E_5~0); 31211#L636-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 31034#L279 assume !(1 == ~m_pc~0); 31035#L279-2 is_master_triggered_~__retres1~0#1 := 0; 31380#L290 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 31185#is_master_triggered_returnLabel#1 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 31186#L720 assume !(0 != activate_threads_~tmp~1#1); 31379#L720-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 31220#L298 assume !(1 == ~t1_pc~0); 30980#L298-2 is_transmit1_triggered_~__retres1~1#1 := 0; 30981#L309 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 31006#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 31007#L728 assume !(0 != activate_threads_~tmp___0~0#1); 31047#L728-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 31178#L317 assume !(1 == ~t2_pc~0); 31179#L317-2 is_transmit2_triggered_~__retres1~2#1 := 0; 31404#L328 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 31348#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 31229#L736 assume !(0 != activate_threads_~tmp___1~0#1); 31230#L736-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 31444#L336 assume !(1 == ~t3_pc~0); 31445#L336-2 is_transmit3_triggered_~__retres1~3#1 := 0; 31534#L347 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 30954#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 30955#L744 assume !(0 != activate_threads_~tmp___2~0#1); 31388#L744-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 31454#L355 assume !(1 == ~t4_pc~0); 31294#L355-2 is_transmit4_triggered_~__retres1~4#1 := 0; 31137#L366 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 31080#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 31081#L752 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 31060#L752-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 31061#L374 assume 1 == ~t5_pc~0; 31491#L375 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 31201#L385 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 31191#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 31192#L760 assume !(0 != activate_threads_~tmp___4~0#1); 31332#L760-2 havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 31333#L649 assume !(1 == ~M_E~0); 31524#L649-2 assume !(1 == ~T1_E~0); 31018#L654-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 31019#L659-1 assume !(1 == ~T3_E~0); 36459#L664-1 assume !(1 == ~T4_E~0); 36458#L669-1 assume !(1 == ~T5_E~0); 36457#L674-1 assume !(1 == ~E_1~0); 36456#L679-1 assume !(1 == ~E_2~0); 36455#L684-1 assume 1 == ~E_3~0;~E_3~0 := 2; 31123#L689-1 assume !(1 == ~E_4~0); 31558#L694-1 assume !(1 == ~E_5~0); 31559#L699-1 assume { :end_inline_reset_delta_events } true; 36426#L900-2 [2023-11-06 22:26:02,150 INFO L750 eck$LassoCheckResult]: Loop: 36426#L900-2 assume !false; 40342#L901 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 40338#L561-1 assume !false; 40337#L482 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 40335#L439 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 40330#L471 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 40329#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 40327#L486 assume !(0 != eval_~tmp~0#1); 40326#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 40325#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 40324#L586-3 assume !(0 == ~M_E~0); 40323#L586-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 40322#L591-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 40321#L596-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 40320#L601-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 40319#L606-3 assume !(0 == ~T5_E~0); 40318#L611-3 assume 0 == ~E_1~0;~E_1~0 := 1; 40317#L616-3 assume 0 == ~E_2~0;~E_2~0 := 1; 40316#L621-3 assume !(0 == ~E_3~0); 40315#L626-3 assume 0 == ~E_4~0;~E_4~0 := 1; 40314#L631-3 assume 0 == ~E_5~0;~E_5~0 := 1; 40313#L636-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 40312#L279-18 assume !(1 == ~m_pc~0); 40311#L279-20 is_master_triggered_~__retres1~0#1 := 0; 40310#L290-6 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 40309#is_master_triggered_returnLabel#7 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 40308#L720-18 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 40307#L720-20 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 40306#L298-18 assume !(1 == ~t1_pc~0); 40304#L298-20 is_transmit1_triggered_~__retres1~1#1 := 0; 40303#L309-6 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 40302#is_transmit1_triggered_returnLabel#7 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 40301#L728-18 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 40300#L728-20 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 40299#L317-18 assume !(1 == ~t2_pc~0); 40298#L317-20 is_transmit2_triggered_~__retres1~2#1 := 0; 40297#L328-6 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 40296#is_transmit2_triggered_returnLabel#7 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 40295#L736-18 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 40294#L736-20 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 40293#L336-18 assume !(1 == ~t3_pc~0); 40292#L336-20 is_transmit3_triggered_~__retres1~3#1 := 0; 40291#L347-6 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 40290#is_transmit3_triggered_returnLabel#7 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 40289#L744-18 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 40288#L744-20 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 40287#L355-18 assume 1 == ~t4_pc~0; 40285#L356-6 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 40284#L366-6 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 40283#is_transmit4_triggered_returnLabel#7 activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 40282#L752-18 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 40281#L752-20 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 40280#L374-18 assume !(1 == ~t5_pc~0); 40278#L374-20 is_transmit5_triggered_~__retres1~5#1 := 0; 40277#L385-6 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 40276#is_transmit5_triggered_returnLabel#7 activate_threads_#t~ret16#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 40275#L760-18 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 40274#L760-20 havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 40273#L649-3 assume !(1 == ~M_E~0); 40271#L649-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 40270#L654-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 37461#L659-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 40269#L664-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 40268#L669-3 assume !(1 == ~T5_E~0); 40267#L674-3 assume 1 == ~E_1~0;~E_1~0 := 2; 40266#L679-3 assume 1 == ~E_2~0;~E_2~0 := 2; 40265#L684-3 assume 1 == ~E_3~0;~E_3~0 := 2; 37448#L689-3 assume 1 == ~E_4~0;~E_4~0 := 2; 40264#L694-3 assume 1 == ~E_5~0;~E_5~0 := 2; 40263#L699-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 40259#L439-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 40256#L471-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 40255#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret18#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret18#1;havoc start_simulation_#t~ret18#1; 40254#L919 assume !(0 == start_simulation_~tmp~3#1); 38628#L919-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret17#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 38629#L439-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 40348#L471-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 40347#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret17#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret17#1;havoc stop_simulation_#t~ret17#1; 40346#L874 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 40345#L881 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 40344#stop_simulation_returnLabel#1 start_simulation_#t~ret19#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret17#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret19#1;havoc start_simulation_#t~ret19#1; 40343#L932 assume !(0 != start_simulation_~tmp___0~1#1); 36426#L900-2 [2023-11-06 22:26:02,151 INFO L145 PredicateUnifier]: Initialized classic predicate unifier [2023-11-06 22:26:02,151 INFO L85 PathProgramCache]: Analyzing trace with hash -375271933, now seen corresponding path program 1 times [2023-11-06 22:26:02,151 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-06 22:26:02,151 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [726682289] [2023-11-06 22:26:02,151 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-06 22:26:02,152 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-06 22:26:02,165 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-06 22:26:02,232 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-06 22:26:02,232 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-06 22:26:02,232 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [726682289] [2023-11-06 22:26:02,233 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [726682289] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-06 22:26:02,234 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-06 22:26:02,234 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2023-11-06 22:26:02,234 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1356081276] [2023-11-06 22:26:02,234 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-06 22:26:02,235 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-06 22:26:02,235 INFO L145 PredicateUnifier]: Initialized classic predicate unifier [2023-11-06 22:26:02,235 INFO L85 PathProgramCache]: Analyzing trace with hash 201894848, now seen corresponding path program 1 times [2023-11-06 22:26:02,236 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-06 22:26:02,236 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1437768457] [2023-11-06 22:26:02,236 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-06 22:26:02,237 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-06 22:26:02,251 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-06 22:26:02,309 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-06 22:26:02,309 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-06 22:26:02,310 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1437768457] [2023-11-06 22:26:02,310 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1437768457] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-06 22:26:02,310 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-06 22:26:02,310 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2023-11-06 22:26:02,310 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [878305467] [2023-11-06 22:26:02,311 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-06 22:26:02,311 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-06 22:26:02,311 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-06 22:26:02,312 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2023-11-06 22:26:02,312 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2023-11-06 22:26:02,312 INFO L87 Difference]: Start difference. First operand 10883 states and 15784 transitions. cyclomatic complexity: 4909 Second operand has 5 states, 5 states have (on average 14.2) internal successors, (71), 5 states have internal predecessors, (71), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-06 22:26:02,746 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-06 22:26:02,746 INFO L93 Difference]: Finished difference Result 22523 states and 32310 transitions. [2023-11-06 22:26:02,747 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 22523 states and 32310 transitions. [2023-11-06 22:26:02,907 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 22280 [2023-11-06 22:26:03,049 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 22523 states to 22523 states and 32310 transitions. [2023-11-06 22:26:03,049 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 22523 [2023-11-06 22:26:03,076 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 22523 [2023-11-06 22:26:03,077 INFO L73 IsDeterministic]: Start isDeterministic. Operand 22523 states and 32310 transitions. [2023-11-06 22:26:03,110 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-06 22:26:03,111 INFO L218 hiAutomatonCegarLoop]: Abstraction has 22523 states and 32310 transitions. [2023-11-06 22:26:03,143 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 22523 states and 32310 transitions. [2023-11-06 22:26:03,530 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 22523 to 11366. [2023-11-06 22:26:03,561 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 11366 states, 11366 states have (on average 1.4311983107513637) internal successors, (16267), 11365 states have internal predecessors, (16267), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-06 22:26:03,609 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 11366 states to 11366 states and 16267 transitions. [2023-11-06 22:26:03,609 INFO L240 hiAutomatonCegarLoop]: Abstraction has 11366 states and 16267 transitions. [2023-11-06 22:26:03,610 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2023-11-06 22:26:03,611 INFO L428 stractBuchiCegarLoop]: Abstraction has 11366 states and 16267 transitions. [2023-11-06 22:26:03,611 INFO L335 stractBuchiCegarLoop]: ======== Iteration 11 ============ [2023-11-06 22:26:03,611 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 11366 states and 16267 transitions. [2023-11-06 22:26:03,659 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 11220 [2023-11-06 22:26:03,660 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-06 22:26:03,660 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-06 22:26:03,661 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-06 22:26:03,662 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-06 22:26:03,662 INFO L748 eck$LassoCheckResult]: Stem: 64641#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2; 64642#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~7#1;havoc main_~__retres1~7#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 64764#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret18#1, start_simulation_#t~ret19#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 64765#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 64782#L401 assume 1 == ~m_i~0;~m_st~0 := 0; 64783#L401-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 64575#L406-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 64576#L411-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 64902#L416-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 64903#L421-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 64857#L426-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 64540#L586 assume !(0 == ~M_E~0); 64541#L586-2 assume !(0 == ~T1_E~0); 64599#L591-1 assume !(0 == ~T2_E~0); 64726#L596-1 assume !(0 == ~T3_E~0); 64727#L601-1 assume !(0 == ~T4_E~0); 64770#L606-1 assume !(0 == ~T5_E~0); 64771#L611-1 assume !(0 == ~E_1~0); 64869#L616-1 assume !(0 == ~E_2~0); 64870#L621-1 assume !(0 == ~E_3~0); 64459#L626-1 assume !(0 == ~E_4~0); 64460#L631-1 assume !(0 == ~E_5~0); 64636#L636-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 64455#L279 assume !(1 == ~m_pc~0); 64456#L279-2 is_master_triggered_~__retres1~0#1 := 0; 64798#L290 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 64612#is_master_triggered_returnLabel#1 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 64613#L720 assume !(0 != activate_threads_~tmp~1#1); 64797#L720-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 64643#L298 assume !(1 == ~t1_pc~0); 64401#L298-2 is_transmit1_triggered_~__retres1~1#1 := 0; 64402#L309 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 64427#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 64428#L728 assume !(0 != activate_threads_~tmp___0~0#1); 64469#L728-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 64605#L317 assume !(1 == ~t2_pc~0); 64606#L317-2 is_transmit2_triggered_~__retres1~2#1 := 0; 64818#L328 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 64769#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 64653#L736 assume !(0 != activate_threads_~tmp___1~0#1); 64654#L736-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 64853#L336 assume !(1 == ~t3_pc~0); 64854#L336-2 is_transmit3_triggered_~__retres1~3#1 := 0; 64938#L347 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 64375#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 64376#L744 assume !(0 != activate_threads_~tmp___2~0#1); 64806#L744-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 64864#L355 assume !(1 == ~t4_pc~0); 64723#L355-2 is_transmit4_triggered_~__retres1~4#1 := 0; 64561#L366 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 64562#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 64840#L752 assume !(0 != activate_threads_~tmp___3~0#1); 64481#L752-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 64482#L374 assume 1 == ~t5_pc~0; 64890#L375 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 64627#L385 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 64618#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 64619#L760 assume !(0 != activate_threads_~tmp___4~0#1); 64753#L760-2 havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 64754#L649 assume !(1 == ~M_E~0); 64923#L649-2 assume !(1 == ~T1_E~0); 64439#L654-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 64440#L659-1 assume !(1 == ~T3_E~0); 73010#L664-1 assume !(1 == ~T4_E~0); 64431#L669-1 assume !(1 == ~T5_E~0); 64432#L674-1 assume !(1 == ~E_1~0); 64861#L679-1 assume !(1 == ~E_2~0); 64862#L684-1 assume 1 == ~E_3~0;~E_3~0 := 2; 64547#L689-1 assume !(1 == ~E_4~0); 64717#L694-1 assume !(1 == ~E_5~0); 64715#L699-1 assume { :end_inline_reset_delta_events } true; 64716#L900-2 [2023-11-06 22:26:03,662 INFO L750 eck$LassoCheckResult]: Loop: 64716#L900-2 assume !false; 74125#L901 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 74118#L561-1 assume !false; 74116#L482 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 74112#L439 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 74104#L471 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 74102#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 74099#L486 assume !(0 != eval_~tmp~0#1); 74100#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 75184#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 75183#L586-3 assume !(0 == ~M_E~0); 75182#L586-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 75181#L591-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 75180#L596-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 75179#L601-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 75178#L606-3 assume !(0 == ~T5_E~0); 75177#L611-3 assume 0 == ~E_1~0;~E_1~0 := 1; 75176#L616-3 assume 0 == ~E_2~0;~E_2~0 := 1; 75175#L621-3 assume !(0 == ~E_3~0); 75174#L626-3 assume 0 == ~E_4~0;~E_4~0 := 1; 75173#L631-3 assume 0 == ~E_5~0;~E_5~0 := 1; 75172#L636-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 75171#L279-18 assume !(1 == ~m_pc~0); 75170#L279-20 is_master_triggered_~__retres1~0#1 := 0; 75169#L290-6 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 75168#is_master_triggered_returnLabel#7 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 75167#L720-18 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 75166#L720-20 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 75165#L298-18 assume !(1 == ~t1_pc~0); 75163#L298-20 is_transmit1_triggered_~__retres1~1#1 := 0; 75162#L309-6 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 75161#is_transmit1_triggered_returnLabel#7 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 75160#L728-18 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 75159#L728-20 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 75158#L317-18 assume !(1 == ~t2_pc~0); 75157#L317-20 is_transmit2_triggered_~__retres1~2#1 := 0; 75156#L328-6 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 75155#is_transmit2_triggered_returnLabel#7 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 75154#L736-18 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 75153#L736-20 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 75152#L336-18 assume !(1 == ~t3_pc~0); 75151#L336-20 is_transmit3_triggered_~__retres1~3#1 := 0; 75150#L347-6 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 75149#is_transmit3_triggered_returnLabel#7 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 75148#L744-18 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 75147#L744-20 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 75146#L355-18 assume !(1 == ~t4_pc~0); 75145#L355-20 is_transmit4_triggered_~__retres1~4#1 := 0; 75143#L366-6 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 75141#is_transmit4_triggered_returnLabel#7 activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 75139#L752-18 assume !(0 != activate_threads_~tmp___3~0#1); 75107#L752-20 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 75068#L374-18 assume 1 == ~t5_pc~0; 75065#L375-6 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 75062#L385-6 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 75060#is_transmit5_triggered_returnLabel#7 activate_threads_#t~ret16#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 75057#L760-18 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 74464#L760-20 havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 74463#L649-3 assume !(1 == ~M_E~0); 74458#L649-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 74456#L654-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 72203#L659-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 74443#L664-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 74439#L669-3 assume !(1 == ~T5_E~0); 74425#L674-3 assume 1 == ~E_1~0;~E_1~0 := 2; 74417#L679-3 assume 1 == ~E_2~0;~E_2~0 := 2; 74412#L684-3 assume 1 == ~E_3~0;~E_3~0 := 2; 72196#L689-3 assume 1 == ~E_4~0;~E_4~0 := 2; 74406#L694-3 assume 1 == ~E_5~0;~E_5~0 := 2; 74402#L699-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 74396#L439-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 74391#L471-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 74388#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret18#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret18#1;havoc start_simulation_#t~ret18#1; 74382#L919 assume !(0 == start_simulation_~tmp~3#1); 74378#L919-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret17#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 74358#L439-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 74349#L471-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 74343#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret17#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret17#1;havoc stop_simulation_#t~ret17#1; 74340#L874 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 74335#L881 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 74330#stop_simulation_returnLabel#1 start_simulation_#t~ret19#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret17#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret19#1;havoc start_simulation_#t~ret19#1; 74327#L932 assume !(0 != start_simulation_~tmp___0~1#1); 64716#L900-2 [2023-11-06 22:26:03,663 INFO L145 PredicateUnifier]: Initialized classic predicate unifier [2023-11-06 22:26:03,663 INFO L85 PathProgramCache]: Analyzing trace with hash -1192920383, now seen corresponding path program 1 times [2023-11-06 22:26:03,663 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-06 22:26:03,663 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1708380458] [2023-11-06 22:26:03,664 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-06 22:26:03,664 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-06 22:26:03,688 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-06 22:26:03,766 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-06 22:26:03,766 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-06 22:26:03,766 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1708380458] [2023-11-06 22:26:03,767 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1708380458] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-06 22:26:03,767 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-06 22:26:03,767 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2023-11-06 22:26:03,767 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [228270229] [2023-11-06 22:26:03,767 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-06 22:26:03,768 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-06 22:26:03,768 INFO L145 PredicateUnifier]: Initialized classic predicate unifier [2023-11-06 22:26:03,768 INFO L85 PathProgramCache]: Analyzing trace with hash -1231017922, now seen corresponding path program 1 times [2023-11-06 22:26:03,769 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-06 22:26:03,769 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1324846527] [2023-11-06 22:26:03,769 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-06 22:26:03,769 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-06 22:26:03,782 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-06 22:26:03,833 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-06 22:26:03,834 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-06 22:26:03,834 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1324846527] [2023-11-06 22:26:03,834 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1324846527] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-06 22:26:03,834 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-06 22:26:03,834 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2023-11-06 22:26:03,835 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1150495307] [2023-11-06 22:26:03,835 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-06 22:26:03,835 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-06 22:26:03,835 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-06 22:26:03,836 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-06 22:26:03,836 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-06 22:26:03,837 INFO L87 Difference]: Start difference. First operand 11366 states and 16267 transitions. cyclomatic complexity: 4909 Second operand has 3 states, 3 states have (on average 23.666666666666668) internal successors, (71), 2 states have internal predecessors, (71), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-06 22:26:04,023 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-06 22:26:04,024 INFO L93 Difference]: Finished difference Result 22449 states and 31890 transitions. [2023-11-06 22:26:04,024 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 22449 states and 31890 transitions. [2023-11-06 22:26:04,250 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 22172 [2023-11-06 22:26:04,333 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 22449 states to 22449 states and 31890 transitions. [2023-11-06 22:26:04,333 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 22449 [2023-11-06 22:26:04,359 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 22449 [2023-11-06 22:26:04,360 INFO L73 IsDeterministic]: Start isDeterministic. Operand 22449 states and 31890 transitions. [2023-11-06 22:26:04,383 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-06 22:26:04,383 INFO L218 hiAutomatonCegarLoop]: Abstraction has 22449 states and 31890 transitions. [2023-11-06 22:26:04,412 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 22449 states and 31890 transitions. [2023-11-06 22:26:04,828 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 22449 to 22305. [2023-11-06 22:26:04,866 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 22305 states, 22305 states have (on average 1.421654337592468) internal successors, (31710), 22304 states have internal predecessors, (31710), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-06 22:26:05,092 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 22305 states to 22305 states and 31710 transitions. [2023-11-06 22:26:05,093 INFO L240 hiAutomatonCegarLoop]: Abstraction has 22305 states and 31710 transitions. [2023-11-06 22:26:05,093 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-06 22:26:05,094 INFO L428 stractBuchiCegarLoop]: Abstraction has 22305 states and 31710 transitions. [2023-11-06 22:26:05,094 INFO L335 stractBuchiCegarLoop]: ======== Iteration 12 ============ [2023-11-06 22:26:05,094 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 22305 states and 31710 transitions. [2023-11-06 22:26:05,261 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 22100 [2023-11-06 22:26:05,261 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-06 22:26:05,261 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-06 22:26:05,263 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-06 22:26:05,263 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-06 22:26:05,263 INFO L748 eck$LassoCheckResult]: Stem: 98461#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2; 98462#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~7#1;havoc main_~__retres1~7#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 98591#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret18#1, start_simulation_#t~ret19#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 98592#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 98611#L401 assume 1 == ~m_i~0;~m_st~0 := 0; 98612#L401-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 98395#L406-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 98396#L411-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 98740#L416-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 98741#L421-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 98691#L426-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 98363#L586 assume !(0 == ~M_E~0); 98364#L586-2 assume !(0 == ~T1_E~0); 98417#L591-1 assume !(0 == ~T2_E~0); 98546#L596-1 assume !(0 == ~T3_E~0); 98547#L601-1 assume !(0 == ~T4_E~0); 98599#L606-1 assume !(0 == ~T5_E~0); 98600#L611-1 assume !(0 == ~E_1~0); 98703#L616-1 assume !(0 == ~E_2~0); 98704#L621-1 assume !(0 == ~E_3~0); 98284#L626-1 assume !(0 == ~E_4~0); 98285#L631-1 assume !(0 == ~E_5~0); 98456#L636-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 98280#L279 assume !(1 == ~m_pc~0); 98281#L279-2 is_master_triggered_~__retres1~0#1 := 0; 98628#L290 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 98430#is_master_triggered_returnLabel#1 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 98431#L720 assume !(0 != activate_threads_~tmp~1#1); 98627#L720-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 98463#L298 assume !(1 == ~t1_pc~0); 98225#L298-2 is_transmit1_triggered_~__retres1~1#1 := 0; 98226#L309 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 98251#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 98252#L728 assume !(0 != activate_threads_~tmp___0~0#1); 98294#L728-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 98423#L317 assume !(1 == ~t2_pc~0); 98424#L317-2 is_transmit2_triggered_~__retres1~2#1 := 0; 98651#L328 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 98596#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 98472#L736 assume !(0 != activate_threads_~tmp___1~0#1); 98473#L736-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 98687#L336 assume !(1 == ~t3_pc~0); 98688#L336-2 is_transmit3_triggered_~__retres1~3#1 := 0; 98777#L347 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 98199#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 98200#L744 assume !(0 != activate_threads_~tmp___2~0#1); 98636#L744-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 98697#L355 assume !(1 == ~t4_pc~0); 98543#L355-2 is_transmit4_triggered_~__retres1~4#1 := 0; 98382#L366 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 98326#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 98327#L752 assume !(0 != activate_threads_~tmp___3~0#1); 98306#L752-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 98307#L374 assume !(1 == ~t5_pc~0); 98446#L374-2 is_transmit5_triggered_~__retres1~5#1 := 0; 98447#L385 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 98436#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 98437#L760 assume !(0 != activate_threads_~tmp___4~0#1); 98578#L760-2 havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 98579#L649 assume !(1 == ~M_E~0); 98764#L649-2 assume !(1 == ~T1_E~0); 98264#L654-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 98265#L659-1 assume !(1 == ~T3_E~0); 98471#L664-1 assume !(1 == ~T4_E~0); 98256#L669-1 assume !(1 == ~T5_E~0); 98257#L674-1 assume !(1 == ~E_1~0); 98678#L679-1 assume !(1 == ~E_2~0); 98368#L684-1 assume 1 == ~E_3~0;~E_3~0 := 2; 98369#L689-1 assume !(1 == ~E_4~0); 98537#L694-1 assume !(1 == ~E_5~0); 109177#L699-1 assume { :end_inline_reset_delta_events } true; 109173#L900-2 [2023-11-06 22:26:05,264 INFO L750 eck$LassoCheckResult]: Loop: 109173#L900-2 assume !false; 109171#L901 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 109166#L561-1 assume !false; 109164#L482 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 109155#L439 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 109149#L471 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 109148#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 109051#L486 assume !(0 != eval_~tmp~0#1); 109052#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 110386#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 110384#L586-3 assume !(0 == ~M_E~0); 110382#L586-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 110381#L591-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 110380#L596-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 110379#L601-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 110378#L606-3 assume !(0 == ~T5_E~0); 110371#L611-3 assume 0 == ~E_1~0;~E_1~0 := 1; 110369#L616-3 assume 0 == ~E_2~0;~E_2~0 := 1; 110367#L621-3 assume !(0 == ~E_3~0); 110364#L626-3 assume 0 == ~E_4~0;~E_4~0 := 1; 110363#L631-3 assume 0 == ~E_5~0;~E_5~0 := 1; 110361#L636-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 110359#L279-18 assume !(1 == ~m_pc~0); 110357#L279-20 is_master_triggered_~__retres1~0#1 := 0; 110355#L290-6 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 110353#is_master_triggered_returnLabel#7 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 110351#L720-18 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 110349#L720-20 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 110346#L298-18 assume !(1 == ~t1_pc~0); 110343#L298-20 is_transmit1_triggered_~__retres1~1#1 := 0; 110341#L309-6 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 110339#is_transmit1_triggered_returnLabel#7 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 110337#L728-18 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 110335#L728-20 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 110333#L317-18 assume !(1 == ~t2_pc~0); 110331#L317-20 is_transmit2_triggered_~__retres1~2#1 := 0; 110329#L328-6 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 110327#is_transmit2_triggered_returnLabel#7 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 110325#L736-18 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 110323#L736-20 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 110321#L336-18 assume !(1 == ~t3_pc~0); 110319#L336-20 is_transmit3_triggered_~__retres1~3#1 := 0; 110317#L347-6 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 110315#is_transmit3_triggered_returnLabel#7 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 110313#L744-18 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 110309#L744-20 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 110307#L355-18 assume 1 == ~t4_pc~0; 110305#L356-6 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 110306#L366-6 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 110416#is_transmit4_triggered_returnLabel#7 activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 110295#L752-18 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 110293#L752-20 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 110291#L374-18 assume !(1 == ~t5_pc~0); 110289#L374-20 is_transmit5_triggered_~__retres1~5#1 := 0; 110287#L385-6 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 110285#is_transmit5_triggered_returnLabel#7 activate_threads_#t~ret16#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 110283#L760-18 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 110280#L760-20 havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 110278#L649-3 assume !(1 == ~M_E~0); 110272#L649-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 110270#L654-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 110266#L659-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 110264#L664-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 110262#L669-3 assume !(1 == ~T5_E~0); 110260#L674-3 assume 1 == ~E_1~0;~E_1~0 := 2; 110256#L679-3 assume 1 == ~E_2~0;~E_2~0 := 2; 110254#L684-3 assume 1 == ~E_3~0;~E_3~0 := 2; 110250#L689-3 assume 1 == ~E_4~0;~E_4~0 := 2; 110249#L694-3 assume 1 == ~E_5~0;~E_5~0 := 2; 110248#L699-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 110244#L439-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 110239#L471-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 110237#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret18#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret18#1;havoc start_simulation_#t~ret18#1; 110234#L919 assume !(0 == start_simulation_~tmp~3#1); 110231#L919-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret17#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 109200#L439-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 109192#L471-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 109190#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret17#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret17#1;havoc stop_simulation_#t~ret17#1; 109187#L874 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 109186#L881 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 109184#stop_simulation_returnLabel#1 start_simulation_#t~ret19#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret17#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret19#1;havoc start_simulation_#t~ret19#1; 109176#L932 assume !(0 != start_simulation_~tmp___0~1#1); 109173#L900-2 [2023-11-06 22:26:05,265 INFO L145 PredicateUnifier]: Initialized classic predicate unifier [2023-11-06 22:26:05,265 INFO L85 PathProgramCache]: Analyzing trace with hash -52568672, now seen corresponding path program 1 times [2023-11-06 22:26:05,265 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-06 22:26:05,265 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1698719340] [2023-11-06 22:26:05,266 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-06 22:26:05,266 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-06 22:26:05,279 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-06 22:26:05,335 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-06 22:26:05,335 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-06 22:26:05,338 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1698719340] [2023-11-06 22:26:05,338 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1698719340] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-06 22:26:05,342 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-06 22:26:05,342 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2023-11-06 22:26:05,343 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1722233580] [2023-11-06 22:26:05,343 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-06 22:26:05,343 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-06 22:26:05,344 INFO L145 PredicateUnifier]: Initialized classic predicate unifier [2023-11-06 22:26:05,344 INFO L85 PathProgramCache]: Analyzing trace with hash 201894848, now seen corresponding path program 2 times [2023-11-06 22:26:05,344 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-06 22:26:05,344 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [590783141] [2023-11-06 22:26:05,345 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-06 22:26:05,345 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-06 22:26:05,362 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-06 22:26:05,429 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-06 22:26:05,429 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-06 22:26:05,429 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [590783141] [2023-11-06 22:26:05,429 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [590783141] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-06 22:26:05,430 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-06 22:26:05,430 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2023-11-06 22:26:05,430 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1177198278] [2023-11-06 22:26:05,430 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-06 22:26:05,431 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-06 22:26:05,431 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-06 22:26:05,431 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-06 22:26:05,432 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-06 22:26:05,432 INFO L87 Difference]: Start difference. First operand 22305 states and 31710 transitions. cyclomatic complexity: 9421 Second operand has 3 states, 3 states have (on average 23.666666666666668) internal successors, (71), 2 states have internal predecessors, (71), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-06 22:26:05,582 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-06 22:26:05,583 INFO L93 Difference]: Finished difference Result 22299 states and 31517 transitions. [2023-11-06 22:26:05,583 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 22299 states and 31517 transitions. [2023-11-06 22:26:05,870 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 22100 [2023-11-06 22:26:05,982 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 22299 states to 22299 states and 31517 transitions. [2023-11-06 22:26:05,983 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 22299 [2023-11-06 22:26:06,009 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 22299 [2023-11-06 22:26:06,009 INFO L73 IsDeterministic]: Start isDeterministic. Operand 22299 states and 31517 transitions. [2023-11-06 22:26:06,032 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-06 22:26:06,032 INFO L218 hiAutomatonCegarLoop]: Abstraction has 22299 states and 31517 transitions. [2023-11-06 22:26:06,058 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 22299 states and 31517 transitions. [2023-11-06 22:26:06,340 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 22299 to 11459. [2023-11-06 22:26:06,361 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 11459 states, 11459 states have (on average 1.4110306309451086) internal successors, (16169), 11458 states have internal predecessors, (16169), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-06 22:26:06,402 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 11459 states to 11459 states and 16169 transitions. [2023-11-06 22:26:06,403 INFO L240 hiAutomatonCegarLoop]: Abstraction has 11459 states and 16169 transitions. [2023-11-06 22:26:06,403 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-06 22:26:06,405 INFO L428 stractBuchiCegarLoop]: Abstraction has 11459 states and 16169 transitions. [2023-11-06 22:26:06,405 INFO L335 stractBuchiCegarLoop]: ======== Iteration 13 ============ [2023-11-06 22:26:06,406 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 11459 states and 16169 transitions. [2023-11-06 22:26:06,448 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 11323 [2023-11-06 22:26:06,449 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-06 22:26:06,449 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-06 22:26:06,451 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-06 22:26:06,451 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-06 22:26:06,451 INFO L748 eck$LassoCheckResult]: Stem: 143071#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2; 143072#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~7#1;havoc main_~__retres1~7#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 143195#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret18#1, start_simulation_#t~ret19#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 143196#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 143214#L401 assume 1 == ~m_i~0;~m_st~0 := 0; 143215#L401-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 143006#L406-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 143007#L411-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 143337#L416-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 143338#L421-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 143294#L426-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 142975#L586 assume !(0 == ~M_E~0); 142976#L586-2 assume !(0 == ~T1_E~0); 143029#L591-1 assume !(0 == ~T2_E~0); 143151#L596-1 assume !(0 == ~T3_E~0); 143152#L601-1 assume !(0 == ~T4_E~0); 143202#L606-1 assume !(0 == ~T5_E~0); 143203#L611-1 assume !(0 == ~E_1~0); 143303#L616-1 assume !(0 == ~E_2~0); 143304#L621-1 assume !(0 == ~E_3~0); 142895#L626-1 assume !(0 == ~E_4~0); 142896#L631-1 assume !(0 == ~E_5~0); 143066#L636-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 142893#L279 assume !(1 == ~m_pc~0); 142894#L279-2 is_master_triggered_~__retres1~0#1 := 0; 143231#L290 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 143042#is_master_triggered_returnLabel#1 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 143043#L720 assume !(0 != activate_threads_~tmp~1#1); 143230#L720-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 143073#L298 assume !(1 == ~t1_pc~0); 142840#L298-2 is_transmit1_triggered_~__retres1~1#1 := 0; 142841#L309 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 142867#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 142868#L728 assume !(0 != activate_threads_~tmp___0~0#1); 142904#L728-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 143035#L317 assume !(1 == ~t2_pc~0); 143036#L317-2 is_transmit2_triggered_~__retres1~2#1 := 0; 143252#L328 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 143201#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 143083#L736 assume !(0 != activate_threads_~tmp___1~0#1); 143084#L736-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 143288#L336 assume !(1 == ~t3_pc~0); 143289#L336-2 is_transmit3_triggered_~__retres1~3#1 := 0; 143370#L347 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 142812#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 142813#L744 assume !(0 != activate_threads_~tmp___2~0#1); 143239#L744-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 143298#L355 assume !(1 == ~t4_pc~0); 143150#L355-2 is_transmit4_triggered_~__retres1~4#1 := 0; 143296#L366 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 142936#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 142937#L752 assume !(0 != activate_threads_~tmp___3~0#1); 142919#L752-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 142920#L374 assume !(1 == ~t5_pc~0); 143059#L374-2 is_transmit5_triggered_~__retres1~5#1 := 0; 143060#L385 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 143048#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 143049#L760 assume !(0 != activate_threads_~tmp___4~0#1); 143181#L760-2 havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 143182#L649 assume !(1 == ~M_E~0); 143362#L649-2 assume !(1 == ~T1_E~0); 142877#L654-1 assume !(1 == ~T2_E~0); 142878#L659-1 assume !(1 == ~T3_E~0); 143081#L664-1 assume !(1 == ~T4_E~0); 142869#L669-1 assume !(1 == ~T5_E~0); 142870#L674-1 assume !(1 == ~E_1~0); 143278#L679-1 assume !(1 == ~E_2~0); 142977#L684-1 assume 1 == ~E_3~0;~E_3~0 := 2; 142978#L689-1 assume !(1 == ~E_4~0); 143145#L694-1 assume !(1 == ~E_5~0); 143142#L699-1 assume { :end_inline_reset_delta_events } true; 143143#L900-2 [2023-11-06 22:26:06,452 INFO L750 eck$LassoCheckResult]: Loop: 143143#L900-2 assume !false; 147867#L901 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 147854#L561-1 assume !false; 147847#L482 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 147841#L439 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 147826#L471 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 147818#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 147811#L486 assume !(0 != eval_~tmp~0#1); 147812#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 151150#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 151149#L586-3 assume !(0 == ~M_E~0); 151148#L586-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 151147#L591-3 assume !(0 == ~T2_E~0); 151146#L596-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 151145#L601-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 151144#L606-3 assume !(0 == ~T5_E~0); 151143#L611-3 assume 0 == ~E_1~0;~E_1~0 := 1; 151142#L616-3 assume 0 == ~E_2~0;~E_2~0 := 1; 151141#L621-3 assume !(0 == ~E_3~0); 151140#L626-3 assume 0 == ~E_4~0;~E_4~0 := 1; 151139#L631-3 assume 0 == ~E_5~0;~E_5~0 := 1; 151138#L636-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 151137#L279-18 assume !(1 == ~m_pc~0); 151136#L279-20 is_master_triggered_~__retres1~0#1 := 0; 151135#L290-6 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 151134#is_master_triggered_returnLabel#7 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 151133#L720-18 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 151132#L720-20 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 151131#L298-18 assume 1 == ~t1_pc~0; 151130#L299-6 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 151128#L309-6 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 151127#is_transmit1_triggered_returnLabel#7 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 151126#L728-18 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 151125#L728-20 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 151124#L317-18 assume !(1 == ~t2_pc~0); 151123#L317-20 is_transmit2_triggered_~__retres1~2#1 := 0; 151122#L328-6 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 151121#is_transmit2_triggered_returnLabel#7 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 151120#L736-18 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 151119#L736-20 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 151118#L336-18 assume !(1 == ~t3_pc~0); 151117#L336-20 is_transmit3_triggered_~__retres1~3#1 := 0; 151116#L347-6 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 151115#is_transmit3_triggered_returnLabel#7 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 151114#L744-18 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 151113#L744-20 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 151112#L355-18 assume 1 == ~t4_pc~0; 151110#L356-6 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 151111#L366-6 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 151151#is_transmit4_triggered_returnLabel#7 activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 151105#L752-18 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 151104#L752-20 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 151103#L374-18 assume !(1 == ~t5_pc~0); 151102#L374-20 is_transmit5_triggered_~__retres1~5#1 := 0; 151101#L385-6 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 151100#is_transmit5_triggered_returnLabel#7 activate_threads_#t~ret16#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 151099#L760-18 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 151098#L760-20 havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 151097#L649-3 assume !(1 == ~M_E~0); 151032#L649-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 151096#L654-3 assume !(1 == ~T2_E~0); 151095#L659-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 151094#L664-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 151093#L669-3 assume !(1 == ~T5_E~0); 151092#L674-3 assume 1 == ~E_1~0;~E_1~0 := 2; 151091#L679-3 assume 1 == ~E_2~0;~E_2~0 := 2; 151090#L684-3 assume 1 == ~E_3~0;~E_3~0 := 2; 151089#L689-3 assume 1 == ~E_4~0;~E_4~0 := 2; 151088#L694-3 assume 1 == ~E_5~0;~E_5~0 := 2; 151087#L699-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 150995#L439-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 150991#L471-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 150989#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret18#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret18#1;havoc start_simulation_#t~ret18#1; 150986#L919 assume !(0 == start_simulation_~tmp~3#1); 150987#L919-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret17#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 151203#L439-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 151197#L471-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 151196#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret17#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret17#1;havoc stop_simulation_#t~ret17#1; 151195#L874 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 151194#L881 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 151193#stop_simulation_returnLabel#1 start_simulation_#t~ret19#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret17#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret19#1;havoc start_simulation_#t~ret19#1; 151192#L932 assume !(0 != start_simulation_~tmp___0~1#1); 143143#L900-2 [2023-11-06 22:26:06,453 INFO L145 PredicateUnifier]: Initialized classic predicate unifier [2023-11-06 22:26:06,453 INFO L85 PathProgramCache]: Analyzing trace with hash -445595682, now seen corresponding path program 1 times [2023-11-06 22:26:06,453 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-06 22:26:06,453 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1763638073] [2023-11-06 22:26:06,453 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-06 22:26:06,454 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-06 22:26:06,471 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-06 22:26:06,529 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-06 22:26:06,529 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-06 22:26:06,530 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1763638073] [2023-11-06 22:26:06,530 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1763638073] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-06 22:26:06,530 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-06 22:26:06,530 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-06 22:26:06,531 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1551571332] [2023-11-06 22:26:06,531 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-06 22:26:06,532 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-06 22:26:06,533 INFO L145 PredicateUnifier]: Initialized classic predicate unifier [2023-11-06 22:26:06,533 INFO L85 PathProgramCache]: Analyzing trace with hash -2068561187, now seen corresponding path program 1 times [2023-11-06 22:26:06,533 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-06 22:26:06,533 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1000035174] [2023-11-06 22:26:06,533 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-06 22:26:06,534 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-06 22:26:06,549 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-06 22:26:06,709 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-06 22:26:06,709 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-06 22:26:06,710 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1000035174] [2023-11-06 22:26:06,710 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1000035174] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-06 22:26:06,710 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-06 22:26:06,710 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2023-11-06 22:26:06,711 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1776878768] [2023-11-06 22:26:06,711 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-06 22:26:06,712 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-06 22:26:06,712 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-06 22:26:06,713 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2023-11-06 22:26:06,713 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2023-11-06 22:26:06,714 INFO L87 Difference]: Start difference. First operand 11459 states and 16169 transitions. cyclomatic complexity: 4718 Second operand has 4 states, 4 states have (on average 17.75) internal successors, (71), 3 states have internal predecessors, (71), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-06 22:26:06,916 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-06 22:26:06,916 INFO L93 Difference]: Finished difference Result 19121 states and 26796 transitions. [2023-11-06 22:26:06,917 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 19121 states and 26796 transitions. [2023-11-06 22:26:07,032 INFO L131 ngComponentsAnalysis]: Automaton has 12 accepting balls. 18933 [2023-11-06 22:26:07,125 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 19121 states to 19121 states and 26796 transitions. [2023-11-06 22:26:07,126 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 19121 [2023-11-06 22:26:07,149 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 19121 [2023-11-06 22:26:07,149 INFO L73 IsDeterministic]: Start isDeterministic. Operand 19121 states and 26796 transitions. [2023-11-06 22:26:07,172 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-06 22:26:07,172 INFO L218 hiAutomatonCegarLoop]: Abstraction has 19121 states and 26796 transitions. [2023-11-06 22:26:07,198 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 19121 states and 26796 transitions. [2023-11-06 22:26:07,516 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 19121 to 11459. [2023-11-06 22:26:07,534 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 11459 states, 11459 states have (on average 1.399249498211013) internal successors, (16034), 11458 states have internal predecessors, (16034), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-06 22:26:07,572 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 11459 states to 11459 states and 16034 transitions. [2023-11-06 22:26:07,572 INFO L240 hiAutomatonCegarLoop]: Abstraction has 11459 states and 16034 transitions. [2023-11-06 22:26:07,573 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2023-11-06 22:26:07,574 INFO L428 stractBuchiCegarLoop]: Abstraction has 11459 states and 16034 transitions. [2023-11-06 22:26:07,575 INFO L335 stractBuchiCegarLoop]: ======== Iteration 14 ============ [2023-11-06 22:26:07,575 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 11459 states and 16034 transitions. [2023-11-06 22:26:07,618 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 11323 [2023-11-06 22:26:07,618 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-06 22:26:07,618 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-06 22:26:07,620 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-06 22:26:07,620 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-06 22:26:07,621 INFO L748 eck$LassoCheckResult]: Stem: 173661#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2; 173662#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~7#1;havoc main_~__retres1~7#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 173779#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret18#1, start_simulation_#t~ret19#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 173780#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 173796#L401 assume 1 == ~m_i~0;~m_st~0 := 0; 173797#L401-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 173595#L406-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 173596#L411-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 173915#L416-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 173916#L421-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 173870#L426-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 173566#L586 assume !(0 == ~M_E~0); 173567#L586-2 assume !(0 == ~T1_E~0); 173617#L591-1 assume !(0 == ~T2_E~0); 173737#L596-1 assume !(0 == ~T3_E~0); 173738#L601-1 assume !(0 == ~T4_E~0); 173784#L606-1 assume !(0 == ~T5_E~0); 173785#L611-1 assume !(0 == ~E_1~0); 173883#L616-1 assume !(0 == ~E_2~0); 173884#L621-1 assume !(0 == ~E_3~0); 173487#L626-1 assume !(0 == ~E_4~0); 173488#L631-1 assume !(0 == ~E_5~0); 173654#L636-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 173485#L279 assume !(1 == ~m_pc~0); 173486#L279-2 is_master_triggered_~__retres1~0#1 := 0; 173812#L290 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 173628#is_master_triggered_returnLabel#1 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 173629#L720 assume !(0 != activate_threads_~tmp~1#1); 173811#L720-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 173663#L298 assume !(1 == ~t1_pc~0); 173432#L298-2 is_transmit1_triggered_~__retres1~1#1 := 0; 173433#L309 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 173459#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 173460#L728 assume !(0 != activate_threads_~tmp___0~0#1); 173496#L728-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 173622#L317 assume !(1 == ~t2_pc~0); 173623#L317-2 is_transmit2_triggered_~__retres1~2#1 := 0; 173832#L328 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 173783#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 173674#L736 assume !(0 != activate_threads_~tmp___1~0#1); 173675#L736-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 173863#L336 assume !(1 == ~t3_pc~0); 173864#L336-2 is_transmit3_triggered_~__retres1~3#1 := 0; 173946#L347 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 173404#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 173405#L744 assume !(0 != activate_threads_~tmp___2~0#1); 173820#L744-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 173875#L355 assume !(1 == ~t4_pc~0); 173736#L355-2 is_transmit4_triggered_~__retres1~4#1 := 0; 173872#L366 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 173527#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 173528#L752 assume !(0 != activate_threads_~tmp___3~0#1); 173509#L752-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 173510#L374 assume !(1 == ~t5_pc~0); 173646#L374-2 is_transmit5_triggered_~__retres1~5#1 := 0; 173647#L385 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 173635#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 173636#L760 assume !(0 != activate_threads_~tmp___4~0#1); 173764#L760-2 havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 173765#L649 assume !(1 == ~M_E~0); 173936#L649-2 assume !(1 == ~T1_E~0); 173469#L654-1 assume !(1 == ~T2_E~0); 173470#L659-1 assume !(1 == ~T3_E~0); 173671#L664-1 assume !(1 == ~T4_E~0); 173461#L669-1 assume !(1 == ~T5_E~0); 173462#L674-1 assume !(1 == ~E_1~0); 173854#L679-1 assume !(1 == ~E_2~0); 173568#L684-1 assume !(1 == ~E_3~0); 173569#L689-1 assume !(1 == ~E_4~0); 173731#L694-1 assume !(1 == ~E_5~0); 173728#L699-1 assume { :end_inline_reset_delta_events } true; 173729#L900-2 [2023-11-06 22:26:07,621 INFO L750 eck$LassoCheckResult]: Loop: 173729#L900-2 assume !false; 176993#L901 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 176961#L561-1 assume !false; 176962#L482 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 176673#L439 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 176667#L471 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 176663#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 176660#L486 assume !(0 != eval_~tmp~0#1); 176661#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 177322#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 177318#L586-3 assume !(0 == ~M_E~0); 177312#L586-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 177294#L591-3 assume !(0 == ~T2_E~0); 177293#L596-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 177292#L601-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 177290#L606-3 assume !(0 == ~T5_E~0); 177289#L611-3 assume 0 == ~E_1~0;~E_1~0 := 1; 177288#L616-3 assume 0 == ~E_2~0;~E_2~0 := 1; 177287#L621-3 assume !(0 == ~E_3~0); 177285#L626-3 assume 0 == ~E_4~0;~E_4~0 := 1; 177283#L631-3 assume 0 == ~E_5~0;~E_5~0 := 1; 177284#L636-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 177279#L279-18 assume !(1 == ~m_pc~0); 177280#L279-20 is_master_triggered_~__retres1~0#1 := 0; 177275#L290-6 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 177276#is_master_triggered_returnLabel#7 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 177269#L720-18 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 177270#L720-20 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 177262#L298-18 assume 1 == ~t1_pc~0; 177264#L299-6 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 177255#L309-6 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 177256#is_transmit1_triggered_returnLabel#7 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 177249#L728-18 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 177250#L728-20 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 177243#L317-18 assume !(1 == ~t2_pc~0); 177244#L317-20 is_transmit2_triggered_~__retres1~2#1 := 0; 177237#L328-6 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 177238#is_transmit2_triggered_returnLabel#7 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 177231#L736-18 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 177232#L736-20 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 177224#L336-18 assume !(1 == ~t3_pc~0); 177225#L336-20 is_transmit3_triggered_~__retres1~3#1 := 0; 177219#L347-6 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 177220#is_transmit3_triggered_returnLabel#7 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 177213#L744-18 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 177214#L744-20 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 177208#L355-18 assume 1 == ~t4_pc~0; 177206#L356-6 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 177207#L366-6 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 177286#is_transmit4_triggered_returnLabel#7 activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 177197#L752-18 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 177195#L752-20 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 177194#L374-18 assume !(1 == ~t5_pc~0); 177192#L374-20 is_transmit5_triggered_~__retres1~5#1 := 0; 177190#L385-6 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 177188#is_transmit5_triggered_returnLabel#7 activate_threads_#t~ret16#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 177186#L760-18 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 177183#L760-20 havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 177181#L649-3 assume !(1 == ~M_E~0); 177049#L649-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 177178#L654-3 assume !(1 == ~T2_E~0); 177176#L659-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 177174#L664-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 177172#L669-3 assume !(1 == ~T5_E~0); 177168#L674-3 assume 1 == ~E_1~0;~E_1~0 := 2; 177166#L679-3 assume 1 == ~E_2~0;~E_2~0 := 2; 177164#L684-3 assume !(1 == ~E_3~0); 177162#L689-3 assume 1 == ~E_4~0;~E_4~0 := 2; 177158#L694-3 assume 1 == ~E_5~0;~E_5~0 := 2; 177159#L699-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 177101#L439-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 177099#L471-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 177090#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret18#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret18#1;havoc start_simulation_#t~ret18#1; 177091#L919 assume !(0 == start_simulation_~tmp~3#1); 177055#L919-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret17#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 177056#L439-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 177028#L471-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 177029#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret17#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret17#1;havoc stop_simulation_#t~ret17#1; 177012#L874 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 177013#L881 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 176996#stop_simulation_returnLabel#1 start_simulation_#t~ret19#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret17#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret19#1;havoc start_simulation_#t~ret19#1; 176997#L932 assume !(0 != start_simulation_~tmp___0~1#1); 173729#L900-2 [2023-11-06 22:26:07,622 INFO L145 PredicateUnifier]: Initialized classic predicate unifier [2023-11-06 22:26:07,622 INFO L85 PathProgramCache]: Analyzing trace with hash -445536100, now seen corresponding path program 1 times [2023-11-06 22:26:07,622 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-06 22:26:07,623 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1785322601] [2023-11-06 22:26:07,623 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-06 22:26:07,623 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-06 22:26:07,737 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-06 22:26:07,737 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-06 22:26:07,749 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-06 22:26:07,807 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-06 22:26:07,809 INFO L145 PredicateUnifier]: Initialized classic predicate unifier [2023-11-06 22:26:07,810 INFO L85 PathProgramCache]: Analyzing trace with hash 1205337755, now seen corresponding path program 1 times [2023-11-06 22:26:07,810 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-06 22:26:07,810 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1096957137] [2023-11-06 22:26:07,810 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-06 22:26:07,811 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-06 22:26:07,829 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-06 22:26:07,893 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-06 22:26:07,894 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-06 22:26:07,894 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1096957137] [2023-11-06 22:26:07,894 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1096957137] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-06 22:26:07,894 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-06 22:26:07,894 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2023-11-06 22:26:07,895 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [783807651] [2023-11-06 22:26:07,895 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-06 22:26:07,896 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-06 22:26:07,897 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-06 22:26:07,898 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2023-11-06 22:26:07,898 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2023-11-06 22:26:07,899 INFO L87 Difference]: Start difference. First operand 11459 states and 16034 transitions. cyclomatic complexity: 4583 Second operand has 5 states, 5 states have (on average 16.4) internal successors, (82), 5 states have internal predecessors, (82), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-06 22:26:08,129 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-06 22:26:08,130 INFO L93 Difference]: Finished difference Result 20156 states and 27743 transitions. [2023-11-06 22:26:08,130 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 20156 states and 27743 transitions. [2023-11-06 22:26:08,233 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 19960 [2023-11-06 22:26:08,319 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 20156 states to 20156 states and 27743 transitions. [2023-11-06 22:26:08,319 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 20156 [2023-11-06 22:26:08,472 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 20156 [2023-11-06 22:26:08,485 INFO L73 IsDeterministic]: Start isDeterministic. Operand 20156 states and 27743 transitions. [2023-11-06 22:26:08,493 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-06 22:26:08,493 INFO L218 hiAutomatonCegarLoop]: Abstraction has 20156 states and 27743 transitions. [2023-11-06 22:26:08,511 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 20156 states and 27743 transitions. [2023-11-06 22:26:08,670 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 20156 to 11567. [2023-11-06 22:26:08,688 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 11567 states, 11567 states have (on average 1.395521742889254) internal successors, (16142), 11566 states have internal predecessors, (16142), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-06 22:26:08,720 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 11567 states to 11567 states and 16142 transitions. [2023-11-06 22:26:08,720 INFO L240 hiAutomatonCegarLoop]: Abstraction has 11567 states and 16142 transitions. [2023-11-06 22:26:08,721 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 9 states. [2023-11-06 22:26:08,722 INFO L428 stractBuchiCegarLoop]: Abstraction has 11567 states and 16142 transitions. [2023-11-06 22:26:08,722 INFO L335 stractBuchiCegarLoop]: ======== Iteration 15 ============ [2023-11-06 22:26:08,722 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 11567 states and 16142 transitions. [2023-11-06 22:26:08,764 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 11431 [2023-11-06 22:26:08,764 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-06 22:26:08,764 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-06 22:26:08,766 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-06 22:26:08,766 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-06 22:26:08,766 INFO L748 eck$LassoCheckResult]: Stem: 205295#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2; 205296#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~7#1;havoc main_~__retres1~7#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 205424#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret18#1, start_simulation_#t~ret19#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 205425#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 205442#L401 assume 1 == ~m_i~0;~m_st~0 := 0; 205443#L401-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 205229#L406-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 205230#L411-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 205567#L416-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 205568#L421-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 205520#L426-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 205196#L586 assume !(0 == ~M_E~0); 205197#L586-2 assume !(0 == ~T1_E~0); 205252#L591-1 assume !(0 == ~T2_E~0); 205375#L596-1 assume !(0 == ~T3_E~0); 205376#L601-1 assume !(0 == ~T4_E~0); 205430#L606-1 assume !(0 == ~T5_E~0); 205431#L611-1 assume !(0 == ~E_1~0); 205530#L616-1 assume !(0 == ~E_2~0); 205531#L621-1 assume !(0 == ~E_3~0); 205118#L626-1 assume !(0 == ~E_4~0); 205119#L631-1 assume !(0 == ~E_5~0); 205288#L636-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 205114#L279 assume !(1 == ~m_pc~0); 205115#L279-2 is_master_triggered_~__retres1~0#1 := 0; 205461#L290 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 205264#is_master_triggered_returnLabel#1 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 205265#L720 assume !(0 != activate_threads_~tmp~1#1); 205460#L720-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 205297#L298 assume !(1 == ~t1_pc~0); 205064#L298-2 is_transmit1_triggered_~__retres1~1#1 := 0; 205065#L309 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 205090#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 205091#L728 assume !(0 != activate_threads_~tmp___0~0#1); 205127#L728-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 205258#L317 assume !(1 == ~t2_pc~0); 205259#L317-2 is_transmit2_triggered_~__retres1~2#1 := 0; 205479#L328 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 205429#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 205308#L736 assume !(0 != activate_threads_~tmp___1~0#1); 205309#L736-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 205513#L336 assume !(1 == ~t3_pc~0); 205514#L336-2 is_transmit3_triggered_~__retres1~3#1 := 0; 205608#L347 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 205036#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 205037#L744 assume !(0 != activate_threads_~tmp___2~0#1); 205469#L744-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 205524#L355 assume !(1 == ~t4_pc~0); 205374#L355-2 is_transmit4_triggered_~__retres1~4#1 := 0; 205522#L366 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 205157#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 205158#L752 assume !(0 != activate_threads_~tmp___3~0#1); 205140#L752-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 205141#L374 assume !(1 == ~t5_pc~0); 205281#L374-2 is_transmit5_triggered_~__retres1~5#1 := 0; 205282#L385 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 205270#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 205271#L760 assume !(0 != activate_threads_~tmp___4~0#1); 205411#L760-2 havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 205412#L649 assume !(1 == ~M_E~0); 205596#L649-2 assume !(1 == ~T1_E~0); 205100#L654-1 assume !(1 == ~T2_E~0); 205101#L659-1 assume !(1 == ~T3_E~0); 205305#L664-1 assume !(1 == ~T4_E~0); 205092#L669-1 assume !(1 == ~T5_E~0); 205093#L674-1 assume !(1 == ~E_1~0); 205503#L679-1 assume !(1 == ~E_2~0); 205198#L684-1 assume !(1 == ~E_3~0); 205199#L689-1 assume !(1 == ~E_4~0); 205369#L694-1 assume !(1 == ~E_5~0); 205365#L699-1 assume { :end_inline_reset_delta_events } true; 205366#L900-2 [2023-11-06 22:26:08,767 INFO L750 eck$LassoCheckResult]: Loop: 205366#L900-2 assume !false; 213948#L901 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 213943#L561-1 assume !false; 213887#L482 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 213883#L439 assume !(0 == ~m_st~0); 213876#L443 assume !(0 == ~t1_st~0); 213855#L447 assume !(0 == ~t2_st~0); 213787#L451 assume !(0 == ~t3_st~0); 213780#L455 assume !(0 == ~t4_st~0); 213776#L459 assume !(0 == ~t5_st~0);exists_runnable_thread_~__retres1~6#1 := 0; 213772#L471 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 213764#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 213762#L486 assume !(0 != eval_~tmp~0#1); 213761#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 213760#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 213759#L586-3 assume !(0 == ~M_E~0); 213758#L586-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 213757#L591-3 assume !(0 == ~T2_E~0); 213756#L596-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 213755#L601-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 213754#L606-3 assume !(0 == ~T5_E~0); 213753#L611-3 assume 0 == ~E_1~0;~E_1~0 := 1; 213752#L616-3 assume 0 == ~E_2~0;~E_2~0 := 1; 213751#L621-3 assume !(0 == ~E_3~0); 213750#L626-3 assume 0 == ~E_4~0;~E_4~0 := 1; 213749#L631-3 assume 0 == ~E_5~0;~E_5~0 := 1; 213748#L636-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 213747#L279-18 assume !(1 == ~m_pc~0); 213746#L279-20 is_master_triggered_~__retres1~0#1 := 0; 213745#L290-6 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 213744#is_master_triggered_returnLabel#7 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 213743#L720-18 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 213742#L720-20 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 213741#L298-18 assume !(1 == ~t1_pc~0); 213739#L298-20 is_transmit1_triggered_~__retres1~1#1 := 0; 213738#L309-6 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 213737#is_transmit1_triggered_returnLabel#7 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 213736#L728-18 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 213735#L728-20 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 213734#L317-18 assume !(1 == ~t2_pc~0); 213733#L317-20 is_transmit2_triggered_~__retres1~2#1 := 0; 213732#L328-6 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 213731#is_transmit2_triggered_returnLabel#7 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 213730#L736-18 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 213729#L736-20 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 213728#L336-18 assume !(1 == ~t3_pc~0); 213727#L336-20 is_transmit3_triggered_~__retres1~3#1 := 0; 213726#L347-6 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 213725#is_transmit3_triggered_returnLabel#7 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 213724#L744-18 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 213723#L744-20 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 213722#L355-18 assume !(1 == ~t4_pc~0); 213721#L355-20 is_transmit4_triggered_~__retres1~4#1 := 0; 213719#L366-6 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 213717#is_transmit4_triggered_returnLabel#7 activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 213715#L752-18 assume !(0 != activate_threads_~tmp___3~0#1); 213713#L752-20 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 213712#L374-18 assume !(1 == ~t5_pc~0); 213711#L374-20 is_transmit5_triggered_~__retres1~5#1 := 0; 213710#L385-6 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 213709#is_transmit5_triggered_returnLabel#7 activate_threads_#t~ret16#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 213708#L760-18 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 213707#L760-20 havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 213706#L649-3 assume !(1 == ~M_E~0); 213168#L649-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 213705#L654-3 assume !(1 == ~T2_E~0); 213704#L659-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 213703#L664-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 213702#L669-3 assume !(1 == ~T5_E~0); 213701#L674-3 assume 1 == ~E_1~0;~E_1~0 := 2; 213700#L679-3 assume 1 == ~E_2~0;~E_2~0 := 2; 213699#L684-3 assume !(1 == ~E_3~0); 213698#L689-3 assume 1 == ~E_4~0;~E_4~0 := 2; 213697#L694-3 assume 1 == ~E_5~0;~E_5~0 := 2; 213696#L699-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 213692#L439-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 213688#L471-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 213686#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret18#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret18#1;havoc start_simulation_#t~ret18#1; 213619#L919 assume !(0 == start_simulation_~tmp~3#1); 213620#L919-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret17#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 214239#L439-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 214232#L471-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 214230#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret17#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret17#1;havoc stop_simulation_#t~ret17#1; 214227#L874 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 214224#L881 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 214221#stop_simulation_returnLabel#1 start_simulation_#t~ret19#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret17#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret19#1;havoc start_simulation_#t~ret19#1; 214217#L932 assume !(0 != start_simulation_~tmp___0~1#1); 205366#L900-2 [2023-11-06 22:26:08,768 INFO L145 PredicateUnifier]: Initialized classic predicate unifier [2023-11-06 22:26:08,768 INFO L85 PathProgramCache]: Analyzing trace with hash -445536100, now seen corresponding path program 2 times [2023-11-06 22:26:08,768 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-06 22:26:08,769 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2107808399] [2023-11-06 22:26:08,769 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-06 22:26:08,769 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-06 22:26:08,784 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-06 22:26:08,784 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-06 22:26:08,794 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-06 22:26:08,819 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-06 22:26:08,819 INFO L145 PredicateUnifier]: Initialized classic predicate unifier [2023-11-06 22:26:08,820 INFO L85 PathProgramCache]: Analyzing trace with hash 1223106454, now seen corresponding path program 1 times [2023-11-06 22:26:08,820 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-06 22:26:08,820 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [339476571] [2023-11-06 22:26:08,820 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-06 22:26:08,821 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-06 22:26:08,839 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-06 22:26:08,942 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-06 22:26:08,942 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-06 22:26:08,943 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [339476571] [2023-11-06 22:26:08,943 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [339476571] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-06 22:26:08,943 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-06 22:26:08,943 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2023-11-06 22:26:08,944 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1948130010] [2023-11-06 22:26:08,944 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-06 22:26:08,944 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-06 22:26:08,944 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-06 22:26:08,945 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2023-11-06 22:26:08,945 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2023-11-06 22:26:08,946 INFO L87 Difference]: Start difference. First operand 11567 states and 16142 transitions. cyclomatic complexity: 4583 Second operand has 5 states, 5 states have (on average 17.4) internal successors, (87), 5 states have internal predecessors, (87), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-06 22:26:09,362 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-06 22:26:09,362 INFO L93 Difference]: Finished difference Result 17319 states and 23983 transitions. [2023-11-06 22:26:09,363 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 17319 states and 23983 transitions. [2023-11-06 22:26:09,478 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 17183 [2023-11-06 22:26:09,563 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 17319 states to 17319 states and 23983 transitions. [2023-11-06 22:26:09,563 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 17319 [2023-11-06 22:26:09,598 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 17319 [2023-11-06 22:26:09,598 INFO L73 IsDeterministic]: Start isDeterministic. Operand 17319 states and 23983 transitions. [2023-11-06 22:26:09,617 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-06 22:26:09,617 INFO L218 hiAutomatonCegarLoop]: Abstraction has 17319 states and 23983 transitions. [2023-11-06 22:26:09,636 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 17319 states and 23983 transitions. [2023-11-06 22:26:09,822 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 17319 to 11711. [2023-11-06 22:26:09,840 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 11711 states, 11711 states have (on average 1.3804969686619417) internal successors, (16167), 11710 states have internal predecessors, (16167), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-06 22:26:09,881 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 11711 states to 11711 states and 16167 transitions. [2023-11-06 22:26:09,881 INFO L240 hiAutomatonCegarLoop]: Abstraction has 11711 states and 16167 transitions. [2023-11-06 22:26:09,882 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2023-11-06 22:26:09,882 INFO L428 stractBuchiCegarLoop]: Abstraction has 11711 states and 16167 transitions. [2023-11-06 22:26:09,882 INFO L335 stractBuchiCegarLoop]: ======== Iteration 16 ============ [2023-11-06 22:26:09,883 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 11711 states and 16167 transitions. [2023-11-06 22:26:09,929 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 11575 [2023-11-06 22:26:09,929 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-06 22:26:09,930 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-06 22:26:09,931 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-06 22:26:09,931 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-06 22:26:09,932 INFO L748 eck$LassoCheckResult]: Stem: 234191#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2; 234192#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~7#1;havoc main_~__retres1~7#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 234313#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret18#1, start_simulation_#t~ret19#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 234314#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 234336#L401 assume 1 == ~m_i~0;~m_st~0 := 0; 234337#L401-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 234126#L406-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 234127#L411-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 234456#L416-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 234457#L421-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 234407#L426-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 234096#L586 assume !(0 == ~M_E~0); 234097#L586-2 assume !(0 == ~T1_E~0); 234146#L591-1 assume !(0 == ~T2_E~0); 234272#L596-1 assume !(0 == ~T3_E~0); 234273#L601-1 assume !(0 == ~T4_E~0); 234322#L606-1 assume !(0 == ~T5_E~0); 234323#L611-1 assume !(0 == ~E_1~0); 234421#L616-1 assume !(0 == ~E_2~0); 234422#L621-1 assume !(0 == ~E_3~0); 234016#L626-1 assume !(0 == ~E_4~0); 234017#L631-1 assume !(0 == ~E_5~0); 234184#L636-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 234012#L279 assume !(1 == ~m_pc~0); 234013#L279-2 is_master_triggered_~__retres1~0#1 := 0; 234354#L290 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 234157#is_master_triggered_returnLabel#1 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 234158#L720 assume !(0 != activate_threads_~tmp~1#1); 234353#L720-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 234193#L298 assume !(1 == ~t1_pc~0); 233959#L298-2 is_transmit1_triggered_~__retres1~1#1 := 0; 233960#L309 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 233985#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 233986#L728 assume !(0 != activate_threads_~tmp___0~0#1); 234025#L728-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 234151#L317 assume !(1 == ~t2_pc~0); 234152#L317-2 is_transmit2_triggered_~__retres1~2#1 := 0; 234374#L328 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 234321#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 234204#L736 assume !(0 != activate_threads_~tmp___1~0#1); 234205#L736-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 234404#L336 assume !(1 == ~t3_pc~0); 234405#L336-2 is_transmit3_triggered_~__retres1~3#1 := 0; 234497#L347 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 233933#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 233934#L744 assume !(0 != activate_threads_~tmp___2~0#1); 234362#L744-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 234414#L355 assume !(1 == ~t4_pc~0); 234271#L355-2 is_transmit4_triggered_~__retres1~4#1 := 0; 234412#L366 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 234056#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 234057#L752 assume !(0 != activate_threads_~tmp___3~0#1); 234039#L752-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 234040#L374 assume !(1 == ~t5_pc~0); 234176#L374-2 is_transmit5_triggered_~__retres1~5#1 := 0; 234177#L385 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 234163#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 234164#L760 assume !(0 != activate_threads_~tmp___4~0#1); 234301#L760-2 havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 234302#L649 assume !(1 == ~M_E~0); 234487#L649-2 assume !(1 == ~T1_E~0); 233998#L654-1 assume !(1 == ~T2_E~0); 233999#L659-1 assume !(1 == ~T3_E~0); 234201#L664-1 assume !(1 == ~T4_E~0); 233990#L669-1 assume !(1 == ~T5_E~0); 233991#L674-1 assume !(1 == ~E_1~0); 234395#L679-1 assume !(1 == ~E_2~0); 234098#L684-1 assume !(1 == ~E_3~0); 234099#L689-1 assume !(1 == ~E_4~0); 234266#L694-1 assume !(1 == ~E_5~0); 234263#L699-1 assume { :end_inline_reset_delta_events } true; 234264#L900-2 [2023-11-06 22:26:09,932 INFO L750 eck$LassoCheckResult]: Loop: 234264#L900-2 assume !false; 239311#L901 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 239306#L561-1 assume !false; 239304#L482 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 239301#L439 assume !(0 == ~m_st~0); 239302#L443 assume !(0 == ~t1_st~0); 239298#L447 assume !(0 == ~t2_st~0); 239299#L451 assume !(0 == ~t3_st~0); 239300#L455 assume !(0 == ~t4_st~0); 239297#L459 assume !(0 == ~t5_st~0);exists_runnable_thread_~__retres1~6#1 := 0; 239294#L471 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 238830#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 238831#L486 assume !(0 != eval_~tmp~0#1); 239285#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 239283#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 239281#L586-3 assume !(0 == ~M_E~0); 239279#L586-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 239277#L591-3 assume !(0 == ~T2_E~0); 239276#L596-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 239274#L601-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 239272#L606-3 assume !(0 == ~T5_E~0); 239270#L611-3 assume 0 == ~E_1~0;~E_1~0 := 1; 239268#L616-3 assume 0 == ~E_2~0;~E_2~0 := 1; 239266#L621-3 assume !(0 == ~E_3~0); 239263#L626-3 assume 0 == ~E_4~0;~E_4~0 := 1; 239260#L631-3 assume 0 == ~E_5~0;~E_5~0 := 1; 239257#L636-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 239254#L279-18 assume !(1 == ~m_pc~0); 239252#L279-20 is_master_triggered_~__retres1~0#1 := 0; 239250#L290-6 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 239248#is_master_triggered_returnLabel#7 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 239246#L720-18 assume !(0 != activate_threads_~tmp~1#1); 239244#L720-20 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 239242#L298-18 assume !(1 == ~t1_pc~0); 239239#L298-20 is_transmit1_triggered_~__retres1~1#1 := 0; 239237#L309-6 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 239236#is_transmit1_triggered_returnLabel#7 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 239234#L728-18 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 239232#L728-20 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 239230#L317-18 assume !(1 == ~t2_pc~0); 239228#L317-20 is_transmit2_triggered_~__retres1~2#1 := 0; 239226#L328-6 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 239224#is_transmit2_triggered_returnLabel#7 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 239222#L736-18 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 239220#L736-20 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 239218#L336-18 assume !(1 == ~t3_pc~0); 239216#L336-20 is_transmit3_triggered_~__retres1~3#1 := 0; 239215#L347-6 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 239214#is_transmit3_triggered_returnLabel#7 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 239213#L744-18 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 239211#L744-20 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 239209#L355-18 assume !(1 == ~t4_pc~0); 239207#L355-20 is_transmit4_triggered_~__retres1~4#1 := 0; 239198#L366-6 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 239194#is_transmit4_triggered_returnLabel#7 activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 239190#L752-18 assume !(0 != activate_threads_~tmp___3~0#1); 239185#L752-20 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 239183#L374-18 assume !(1 == ~t5_pc~0); 239180#L374-20 is_transmit5_triggered_~__retres1~5#1 := 0; 239177#L385-6 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 239174#is_transmit5_triggered_returnLabel#7 activate_threads_#t~ret16#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 239171#L760-18 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 239168#L760-20 havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 239165#L649-3 assume !(1 == ~M_E~0); 238897#L649-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 239159#L654-3 assume !(1 == ~T2_E~0); 239156#L659-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 239153#L664-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 239150#L669-3 assume !(1 == ~T5_E~0); 239147#L674-3 assume 1 == ~E_1~0;~E_1~0 := 2; 239144#L679-3 assume 1 == ~E_2~0;~E_2~0 := 2; 239140#L684-3 assume !(1 == ~E_3~0); 239137#L689-3 assume 1 == ~E_4~0;~E_4~0 := 2; 239134#L694-3 assume 1 == ~E_5~0;~E_5~0 := 2; 239131#L699-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 239125#L439-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 239120#L471-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 239118#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret18#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret18#1;havoc start_simulation_#t~ret18#1; 239114#L919 assume !(0 == start_simulation_~tmp~3#1); 239115#L919-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret17#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 239348#L439-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 239340#L471-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 239337#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret17#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret17#1;havoc stop_simulation_#t~ret17#1; 239334#L874 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 239329#L881 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 239326#stop_simulation_returnLabel#1 start_simulation_#t~ret19#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret17#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret19#1;havoc start_simulation_#t~ret19#1; 239323#L932 assume !(0 != start_simulation_~tmp___0~1#1); 234264#L900-2 [2023-11-06 22:26:09,933 INFO L145 PredicateUnifier]: Initialized classic predicate unifier [2023-11-06 22:26:09,933 INFO L85 PathProgramCache]: Analyzing trace with hash -445536100, now seen corresponding path program 3 times [2023-11-06 22:26:09,934 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-06 22:26:09,934 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1022918940] [2023-11-06 22:26:09,936 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-06 22:26:09,936 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-06 22:26:09,953 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-06 22:26:09,953 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-06 22:26:09,961 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-06 22:26:09,984 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-06 22:26:09,985 INFO L145 PredicateUnifier]: Initialized classic predicate unifier [2023-11-06 22:26:09,985 INFO L85 PathProgramCache]: Analyzing trace with hash 1263781204, now seen corresponding path program 1 times [2023-11-06 22:26:09,985 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-06 22:26:09,986 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1867395678] [2023-11-06 22:26:09,986 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-06 22:26:09,986 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-06 22:26:10,001 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-06 22:26:10,148 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-06 22:26:10,148 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-06 22:26:10,148 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1867395678] [2023-11-06 22:26:10,148 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1867395678] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-06 22:26:10,148 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-06 22:26:10,149 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-06 22:26:10,149 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1540300069] [2023-11-06 22:26:10,149 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-06 22:26:10,150 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-06 22:26:10,150 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-06 22:26:10,150 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-06 22:26:10,150 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-06 22:26:10,151 INFO L87 Difference]: Start difference. First operand 11711 states and 16167 transitions. cyclomatic complexity: 4464 Second operand has 3 states, 3 states have (on average 29.0) internal successors, (87), 3 states have internal predecessors, (87), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-06 22:26:10,262 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-06 22:26:10,263 INFO L93 Difference]: Finished difference Result 17632 states and 23975 transitions. [2023-11-06 22:26:10,263 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 17632 states and 23975 transitions. [2023-11-06 22:26:10,354 INFO L131 ngComponentsAnalysis]: Automaton has 14 accepting balls. 17524 [2023-11-06 22:26:10,430 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 17632 states to 17632 states and 23975 transitions. [2023-11-06 22:26:10,430 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 17632 [2023-11-06 22:26:10,443 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 17632 [2023-11-06 22:26:10,444 INFO L73 IsDeterministic]: Start isDeterministic. Operand 17632 states and 23975 transitions. [2023-11-06 22:26:10,461 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-06 22:26:10,461 INFO L218 hiAutomatonCegarLoop]: Abstraction has 17632 states and 23975 transitions. [2023-11-06 22:26:10,477 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 17632 states and 23975 transitions. [2023-11-06 22:26:10,658 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 17632 to 17308. [2023-11-06 22:26:10,678 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 17308 states, 17308 states have (on average 1.3611624682227872) internal successors, (23559), 17307 states have internal predecessors, (23559), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-06 22:26:10,721 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 17308 states to 17308 states and 23559 transitions. [2023-11-06 22:26:10,721 INFO L240 hiAutomatonCegarLoop]: Abstraction has 17308 states and 23559 transitions. [2023-11-06 22:26:10,722 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-06 22:26:10,723 INFO L428 stractBuchiCegarLoop]: Abstraction has 17308 states and 23559 transitions. [2023-11-06 22:26:10,723 INFO L335 stractBuchiCegarLoop]: ======== Iteration 17 ============ [2023-11-06 22:26:10,724 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 17308 states and 23559 transitions. [2023-11-06 22:26:10,936 INFO L131 ngComponentsAnalysis]: Automaton has 14 accepting balls. 17200 [2023-11-06 22:26:10,937 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-06 22:26:10,937 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-06 22:26:10,938 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-06 22:26:10,938 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-06 22:26:10,938 INFO L748 eck$LassoCheckResult]: Stem: 263541#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2; 263542#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~7#1;havoc main_~__retres1~7#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 263673#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret18#1, start_simulation_#t~ret19#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 263674#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 263694#L401 assume 1 == ~m_i~0;~m_st~0 := 0; 263695#L401-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 263475#L406-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 263476#L411-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 263825#L416-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 263826#L421-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 263776#L426-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 263443#L586 assume !(0 == ~M_E~0); 263444#L586-2 assume !(0 == ~T1_E~0); 263495#L591-1 assume !(0 == ~T2_E~0); 263628#L596-1 assume !(0 == ~T3_E~0); 263629#L601-1 assume !(0 == ~T4_E~0); 263681#L606-1 assume !(0 == ~T5_E~0); 263682#L611-1 assume !(0 == ~E_1~0); 263791#L616-1 assume !(0 == ~E_2~0); 263792#L621-1 assume !(0 == ~E_3~0); 263368#L626-1 assume !(0 == ~E_4~0); 263369#L631-1 assume !(0 == ~E_5~0); 263534#L636-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 263364#L279 assume !(1 == ~m_pc~0); 263365#L279-2 is_master_triggered_~__retres1~0#1 := 0; 263712#L290 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 263507#is_master_triggered_returnLabel#1 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 263508#L720 assume !(0 != activate_threads_~tmp~1#1); 263711#L720-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 263543#L298 assume !(1 == ~t1_pc~0); 263310#L298-2 is_transmit1_triggered_~__retres1~1#1 := 0; 263311#L309 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 263336#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 263337#L728 assume !(0 != activate_threads_~tmp___0~0#1); 263377#L728-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 263501#L317 assume !(1 == ~t2_pc~0); 263502#L317-2 is_transmit2_triggered_~__retres1~2#1 := 0; 263733#L328 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 263678#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 263552#L736 assume !(0 != activate_threads_~tmp___1~0#1); 263553#L736-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 263771#L336 assume !(1 == ~t3_pc~0); 263772#L336-2 is_transmit3_triggered_~__retres1~3#1 := 0; 263869#L347 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 263283#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 263284#L744 assume !(0 != activate_threads_~tmp___2~0#1); 263720#L744-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 263784#L355 assume !(1 == ~t4_pc~0); 263625#L355-2 is_transmit4_triggered_~__retres1~4#1 := 0; 263783#L366 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 263407#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 263408#L752 assume !(0 != activate_threads_~tmp___3~0#1); 263388#L752-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 263389#L374 assume !(1 == ~t5_pc~0); 263522#L374-2 is_transmit5_triggered_~__retres1~5#1 := 0; 263523#L385 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 263513#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 263514#L760 assume !(0 != activate_threads_~tmp___4~0#1); 263661#L760-2 havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 263662#L649 assume !(1 == ~M_E~0); 263858#L649-2 assume !(1 == ~T1_E~0); 263349#L654-1 assume !(1 == ~T2_E~0); 263350#L659-1 assume !(1 == ~T3_E~0); 263551#L664-1 assume !(1 == ~T4_E~0); 263341#L669-1 assume !(1 == ~T5_E~0); 263342#L674-1 assume !(1 == ~E_1~0); 263762#L679-1 assume !(1 == ~E_2~0); 263447#L684-1 assume !(1 == ~E_3~0); 263448#L689-1 assume !(1 == ~E_4~0); 263621#L694-1 assume !(1 == ~E_5~0); 263619#L699-1 assume { :end_inline_reset_delta_events } true; 263620#L900-2 assume !false; 273175#L901 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 273150#L561-1 [2023-11-06 22:26:10,939 INFO L750 eck$LassoCheckResult]: Loop: 273150#L561-1 assume !false; 273142#L482 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 273133#L439 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 273124#L471 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 273116#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 273109#L486 assume 0 != eval_~tmp~0#1; 273100#L486-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;havoc eval_#t~nondet5#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet5#1;havoc eval_#t~nondet5#1; 273093#L494 assume !(0 != eval_~tmp_ndt_1~0#1); 273083#L494-2 havoc eval_~tmp_ndt_1~0#1; 273075#L491-1 assume !(0 == ~t1_st~0); 273067#L505-1 assume !(0 == ~t2_st~0); 273068#L519-1 assume !(0 == ~t3_st~0); 273180#L533-1 assume !(0 == ~t4_st~0); 273173#L547-1 assume !(0 == ~t5_st~0); 273150#L561-1 [2023-11-06 22:26:10,940 INFO L145 PredicateUnifier]: Initialized classic predicate unifier [2023-11-06 22:26:10,940 INFO L85 PathProgramCache]: Analyzing trace with hash 1336547998, now seen corresponding path program 1 times [2023-11-06 22:26:10,940 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-06 22:26:10,940 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [517358985] [2023-11-06 22:26:10,940 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-06 22:26:10,941 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-06 22:26:10,954 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-06 22:26:10,955 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-06 22:26:10,968 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-06 22:26:10,990 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-06 22:26:10,991 INFO L145 PredicateUnifier]: Initialized classic predicate unifier [2023-11-06 22:26:10,991 INFO L85 PathProgramCache]: Analyzing trace with hash 1972443, now seen corresponding path program 1 times [2023-11-06 22:26:10,991 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-06 22:26:10,991 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [86397405] [2023-11-06 22:26:10,991 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-06 22:26:10,992 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-06 22:26:10,996 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-06 22:26:10,996 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-06 22:26:10,999 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-06 22:26:11,000 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-06 22:26:11,001 INFO L145 PredicateUnifier]: Initialized classic predicate unifier [2023-11-06 22:26:11,001 INFO L85 PathProgramCache]: Analyzing trace with hash 44227768, now seen corresponding path program 1 times [2023-11-06 22:26:11,002 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-06 22:26:11,002 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [684356798] [2023-11-06 22:26:11,002 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-06 22:26:11,002 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-06 22:26:11,015 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-06 22:26:11,062 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-06 22:26:11,062 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-06 22:26:11,062 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [684356798] [2023-11-06 22:26:11,062 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [684356798] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-06 22:26:11,062 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-06 22:26:11,063 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-06 22:26:11,063 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [576993989] [2023-11-06 22:26:11,063 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-06 22:26:11,194 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-06 22:26:11,195 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-06 22:26:11,195 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-06 22:26:11,195 INFO L87 Difference]: Start difference. First operand 17308 states and 23559 transitions. cyclomatic complexity: 6265 Second operand has 3 states, 3 states have (on average 29.0) internal successors, (87), 3 states have internal predecessors, (87), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-06 22:26:11,370 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-06 22:26:11,370 INFO L93 Difference]: Finished difference Result 31904 states and 42861 transitions. [2023-11-06 22:26:11,371 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 31904 states and 42861 transitions. [2023-11-06 22:26:11,536 INFO L131 ngComponentsAnalysis]: Automaton has 14 accepting balls. 31694 [2023-11-06 22:26:11,664 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 31904 states to 31904 states and 42861 transitions. [2023-11-06 22:26:11,664 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 31904 [2023-11-06 22:26:11,688 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 31904 [2023-11-06 22:26:11,688 INFO L73 IsDeterministic]: Start isDeterministic. Operand 31904 states and 42861 transitions. [2023-11-06 22:26:11,904 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-06 22:26:11,913 INFO L218 hiAutomatonCegarLoop]: Abstraction has 31904 states and 42861 transitions. [2023-11-06 22:26:11,935 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 31904 states and 42861 transitions. [2023-11-06 22:26:12,236 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 31904 to 29845. [2023-11-06 22:26:12,268 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 29845 states, 29845 states have (on average 1.3503769475624057) internal successors, (40302), 29844 states have internal predecessors, (40302), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-06 22:26:12,342 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 29845 states to 29845 states and 40302 transitions. [2023-11-06 22:26:12,344 INFO L240 hiAutomatonCegarLoop]: Abstraction has 29845 states and 40302 transitions. [2023-11-06 22:26:12,345 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-06 22:26:12,345 INFO L428 stractBuchiCegarLoop]: Abstraction has 29845 states and 40302 transitions. [2023-11-06 22:26:12,345 INFO L335 stractBuchiCegarLoop]: ======== Iteration 18 ============ [2023-11-06 22:26:12,346 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 29845 states and 40302 transitions. [2023-11-06 22:26:12,755 INFO L131 ngComponentsAnalysis]: Automaton has 14 accepting balls. 29635 [2023-11-06 22:26:12,755 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-06 22:26:12,755 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-06 22:26:12,757 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-06 22:26:12,758 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-06 22:26:12,759 INFO L748 eck$LassoCheckResult]: Stem: 312764#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2; 312765#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~7#1;havoc main_~__retres1~7#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 312894#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret18#1, start_simulation_#t~ret19#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 312895#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 312916#L401 assume 1 == ~m_i~0;~m_st~0 := 0; 312917#L401-2 assume !(1 == ~t1_i~0);~t1_st~0 := 2; 313027#L406-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 313081#L411-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 313082#L416-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 313138#L421-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 313139#L426-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 312660#L586 assume !(0 == ~M_E~0); 312661#L586-2 assume !(0 == ~T1_E~0); 312879#L591-1 assume !(0 == ~T2_E~0); 312880#L596-1 assume !(0 == ~T3_E~0); 312937#L601-1 assume !(0 == ~T4_E~0); 312938#L606-1 assume !(0 == ~T5_E~0); 313141#L611-1 assume !(0 == ~E_1~0); 313142#L616-1 assume !(0 == ~E_2~0); 313033#L621-1 assume !(0 == ~E_3~0); 313034#L626-1 assume !(0 == ~E_4~0); 312979#L631-1 assume !(0 == ~E_5~0); 312980#L636-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 312579#L279 assume !(1 == ~m_pc~0); 312580#L279-2 is_master_triggered_~__retres1~0#1 := 0; 313049#L290 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 313050#is_master_triggered_returnLabel#1 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 312935#L720 assume !(0 != activate_threads_~tmp~1#1); 312936#L720-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 312766#L298 assume !(1 == ~t1_pc~0); 312767#L298-2 is_transmit1_triggered_~__retres1~1#1 := 0; 313128#L309 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 313129#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 312593#L728 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 312594#L728-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 312925#L317 assume !(1 == ~t2_pc~0); 312961#L317-2 is_transmit2_triggered_~__retres1~2#1 := 0; 312962#L328 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 312899#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 312900#L736 assume !(0 != activate_threads_~tmp___1~0#1); 313099#L736-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 313100#L336 assume !(1 == ~t3_pc~0); 313125#L336-2 is_transmit3_triggered_~__retres1~3#1 := 0; 313126#L347 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 312502#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 312503#L744 assume !(0 != activate_threads_~tmp___2~0#1); 313019#L744-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 313020#L355 assume !(1 == ~t4_pc~0); 312846#L355-2 is_transmit4_triggered_~__retres1~4#1 := 0; 313017#L366 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 312625#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 312626#L752 assume !(0 != activate_threads_~tmp___3~0#1); 312606#L752-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 312607#L374 assume !(1 == ~t5_pc~0); 312746#L374-2 is_transmit5_triggered_~__retres1~5#1 := 0; 312747#L385 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 312737#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 312738#L760 assume !(0 != activate_threads_~tmp___4~0#1); 312882#L760-2 havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 312883#L649 assume !(1 == ~M_E~0); 313162#L649-2 assume !(1 == ~T1_E~0); 313163#L654-1 assume !(1 == ~T2_E~0); 312931#L659-1 assume !(1 == ~T3_E~0); 312932#L664-1 assume !(1 == ~T4_E~0); 312557#L669-1 assume !(1 == ~T5_E~0); 312558#L674-1 assume !(1 == ~E_1~0); 313014#L679-1 assume !(1 == ~E_2~0); 313015#L684-1 assume !(1 == ~E_3~0); 312840#L689-1 assume !(1 == ~E_4~0); 312841#L694-1 assume !(1 == ~E_5~0); 312838#L699-1 assume { :end_inline_reset_delta_events } true; 312839#L900-2 assume !false; 331882#L901 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 331883#L561-1 [2023-11-06 22:26:12,759 INFO L750 eck$LassoCheckResult]: Loop: 331883#L561-1 assume !false; 332480#L482 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 332477#L439 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 332475#L471 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 332473#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 332471#L486 assume 0 != eval_~tmp~0#1; 332467#L486-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;havoc eval_#t~nondet5#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet5#1;havoc eval_#t~nondet5#1; 331855#L494 assume !(0 != eval_~tmp_ndt_1~0#1); 331852#L494-2 havoc eval_~tmp_ndt_1~0#1; 331849#L491-1 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0#1;havoc eval_#t~nondet6#1;eval_~tmp_ndt_2~0#1 := eval_#t~nondet6#1;havoc eval_#t~nondet6#1; 328393#L508 assume !(0 != eval_~tmp_ndt_2~0#1); 331845#L508-2 havoc eval_~tmp_ndt_2~0#1; 331842#L505-1 assume !(0 == ~t2_st~0); 331841#L519-1 assume !(0 == ~t3_st~0); 332488#L533-1 assume !(0 == ~t4_st~0); 332484#L547-1 assume !(0 == ~t5_st~0); 331883#L561-1 [2023-11-06 22:26:12,760 INFO L145 PredicateUnifier]: Initialized classic predicate unifier [2023-11-06 22:26:12,761 INFO L85 PathProgramCache]: Analyzing trace with hash -632671842, now seen corresponding path program 1 times [2023-11-06 22:26:12,761 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-06 22:26:12,761 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [924672076] [2023-11-06 22:26:12,761 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-06 22:26:12,762 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-06 22:26:12,778 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-06 22:26:12,807 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-06 22:26:12,807 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-06 22:26:12,807 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [924672076] [2023-11-06 22:26:12,808 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [924672076] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-06 22:26:12,808 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-06 22:26:12,808 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-06 22:26:12,808 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [271212819] [2023-11-06 22:26:12,809 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-06 22:26:12,809 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-06 22:26:12,810 INFO L145 PredicateUnifier]: Initialized classic predicate unifier [2023-11-06 22:26:12,810 INFO L85 PathProgramCache]: Analyzing trace with hash 1454566731, now seen corresponding path program 1 times [2023-11-06 22:26:12,810 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-06 22:26:12,811 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1831789499] [2023-11-06 22:26:12,811 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-06 22:26:12,811 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-06 22:26:12,816 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-06 22:26:12,816 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-06 22:26:12,819 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-06 22:26:12,822 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-06 22:26:12,940 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-06 22:26:12,941 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-06 22:26:12,941 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-06 22:26:12,942 INFO L87 Difference]: Start difference. First operand 29845 states and 40302 transitions. cyclomatic complexity: 10471 Second operand has 3 states, 3 states have (on average 24.333333333333332) internal successors, (73), 3 states have internal predecessors, (73), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-06 22:26:13,095 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-06 22:26:13,096 INFO L93 Difference]: Finished difference Result 29773 states and 40204 transitions. [2023-11-06 22:26:13,096 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 29773 states and 40204 transitions. [2023-11-06 22:26:13,287 INFO L131 ngComponentsAnalysis]: Automaton has 14 accepting balls. 29635 [2023-11-06 22:26:13,438 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 29773 states to 29773 states and 40204 transitions. [2023-11-06 22:26:13,438 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 29773 [2023-11-06 22:26:13,462 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 29773 [2023-11-06 22:26:13,462 INFO L73 IsDeterministic]: Start isDeterministic. Operand 29773 states and 40204 transitions. [2023-11-06 22:26:13,498 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-06 22:26:13,499 INFO L218 hiAutomatonCegarLoop]: Abstraction has 29773 states and 40204 transitions. [2023-11-06 22:26:13,528 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 29773 states and 40204 transitions. [2023-11-06 22:26:13,930 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 29773 to 29773. [2023-11-06 22:26:13,962 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 29773 states, 29773 states have (on average 1.3503509891512444) internal successors, (40204), 29772 states have internal predecessors, (40204), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-06 22:26:14,058 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 29773 states to 29773 states and 40204 transitions. [2023-11-06 22:26:14,058 INFO L240 hiAutomatonCegarLoop]: Abstraction has 29773 states and 40204 transitions. [2023-11-06 22:26:14,059 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-06 22:26:14,060 INFO L428 stractBuchiCegarLoop]: Abstraction has 29773 states and 40204 transitions. [2023-11-06 22:26:14,060 INFO L335 stractBuchiCegarLoop]: ======== Iteration 19 ============ [2023-11-06 22:26:14,060 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 29773 states and 40204 transitions. [2023-11-06 22:26:14,197 INFO L131 ngComponentsAnalysis]: Automaton has 14 accepting balls. 29635 [2023-11-06 22:26:14,198 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-06 22:26:14,198 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-06 22:26:14,199 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-06 22:26:14,200 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-06 22:26:14,200 INFO L748 eck$LassoCheckResult]: Stem: 372388#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2; 372389#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~7#1;havoc main_~__retres1~7#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 372519#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret18#1, start_simulation_#t~ret19#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 372520#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 372540#L401 assume 1 == ~m_i~0;~m_st~0 := 0; 372541#L401-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 372318#L406-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 372319#L411-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 372666#L416-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 372667#L421-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 372617#L426-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 372283#L586 assume !(0 == ~M_E~0); 372284#L586-2 assume !(0 == ~T1_E~0); 372341#L591-1 assume !(0 == ~T2_E~0); 372472#L596-1 assume !(0 == ~T3_E~0); 372473#L601-1 assume !(0 == ~T4_E~0); 372527#L606-1 assume !(0 == ~T5_E~0); 372528#L611-1 assume !(0 == ~E_1~0); 372629#L616-1 assume !(0 == ~E_2~0); 372630#L621-1 assume !(0 == ~E_3~0); 372207#L626-1 assume !(0 == ~E_4~0); 372208#L631-1 assume !(0 == ~E_5~0); 372381#L636-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 372203#L279 assume !(1 == ~m_pc~0); 372204#L279-2 is_master_triggered_~__retres1~0#1 := 0; 372556#L290 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 372353#is_master_triggered_returnLabel#1 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 372354#L720 assume !(0 != activate_threads_~tmp~1#1); 372555#L720-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 372390#L298 assume !(1 == ~t1_pc~0); 372152#L298-2 is_transmit1_triggered_~__retres1~1#1 := 0; 372153#L309 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 372178#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 372179#L728 assume !(0 != activate_threads_~tmp___0~0#1); 372218#L728-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 372347#L317 assume !(1 == ~t2_pc~0); 372348#L317-2 is_transmit2_triggered_~__retres1~2#1 := 0; 372577#L328 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 372524#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 372399#L736 assume !(0 != activate_threads_~tmp___1~0#1); 372400#L736-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 372613#L336 assume !(1 == ~t3_pc~0); 372614#L336-2 is_transmit3_triggered_~__retres1~3#1 := 0; 372705#L347 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 372127#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 372128#L744 assume !(0 != activate_threads_~tmp___2~0#1); 372564#L744-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 372625#L355 assume !(1 == ~t4_pc~0); 372469#L355-2 is_transmit4_triggered_~__retres1~4#1 := 0; 372622#L366 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 372248#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 372249#L752 assume !(0 != activate_threads_~tmp___3~0#1); 372229#L752-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 372230#L374 assume !(1 == ~t5_pc~0); 372370#L374-2 is_transmit5_triggered_~__retres1~5#1 := 0; 372371#L385 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 372360#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 372361#L760 assume !(0 != activate_threads_~tmp___4~0#1); 372507#L760-2 havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 372508#L649 assume !(1 == ~M_E~0); 372691#L649-2 assume !(1 == ~T1_E~0); 372190#L654-1 assume !(1 == ~T2_E~0); 372191#L659-1 assume !(1 == ~T3_E~0); 372398#L664-1 assume !(1 == ~T4_E~0); 372182#L669-1 assume !(1 == ~T5_E~0); 372183#L674-1 assume !(1 == ~E_1~0); 372604#L679-1 assume !(1 == ~E_2~0); 372287#L684-1 assume !(1 == ~E_3~0); 372288#L689-1 assume !(1 == ~E_4~0); 372465#L694-1 assume !(1 == ~E_5~0); 372463#L699-1 assume { :end_inline_reset_delta_events } true; 372464#L900-2 assume !false; 383606#L901 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 383599#L561-1 [2023-11-06 22:26:14,201 INFO L750 eck$LassoCheckResult]: Loop: 383599#L561-1 assume !false; 383597#L482 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 383594#L439 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 383592#L471 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 383589#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 383587#L486 assume 0 != eval_~tmp~0#1; 383584#L486-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;havoc eval_#t~nondet5#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet5#1;havoc eval_#t~nondet5#1; 383581#L494 assume !(0 != eval_~tmp_ndt_1~0#1); 383579#L494-2 havoc eval_~tmp_ndt_1~0#1; 383577#L491-1 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0#1;havoc eval_#t~nondet6#1;eval_~tmp_ndt_2~0#1 := eval_#t~nondet6#1;havoc eval_#t~nondet6#1; 383565#L508 assume !(0 != eval_~tmp_ndt_2~0#1); 383575#L508-2 havoc eval_~tmp_ndt_2~0#1; 384592#L505-1 assume !(0 == ~t2_st~0); 383614#L519-1 assume !(0 == ~t3_st~0); 383611#L533-1 assume !(0 == ~t4_st~0); 383604#L547-1 assume !(0 == ~t5_st~0); 383599#L561-1 [2023-11-06 22:26:14,201 INFO L145 PredicateUnifier]: Initialized classic predicate unifier [2023-11-06 22:26:14,202 INFO L85 PathProgramCache]: Analyzing trace with hash 1336547998, now seen corresponding path program 2 times [2023-11-06 22:26:14,203 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-06 22:26:14,203 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [626727691] [2023-11-06 22:26:14,203 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-06 22:26:14,204 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-06 22:26:14,222 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-06 22:26:14,223 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-06 22:26:14,235 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-06 22:26:14,257 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-06 22:26:14,258 INFO L145 PredicateUnifier]: Initialized classic predicate unifier [2023-11-06 22:26:14,258 INFO L85 PathProgramCache]: Analyzing trace with hash 1454566731, now seen corresponding path program 2 times [2023-11-06 22:26:14,259 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-06 22:26:14,259 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [103564626] [2023-11-06 22:26:14,259 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-06 22:26:14,259 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-06 22:26:14,265 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-06 22:26:14,265 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-06 22:26:14,268 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-06 22:26:14,271 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-06 22:26:14,271 INFO L145 PredicateUnifier]: Initialized classic predicate unifier [2023-11-06 22:26:14,272 INFO L85 PathProgramCache]: Analyzing trace with hash -887738904, now seen corresponding path program 1 times [2023-11-06 22:26:14,272 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-06 22:26:14,272 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [146268323] [2023-11-06 22:26:14,272 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-06 22:26:14,272 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-06 22:26:14,514 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-06 22:26:14,553 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-06 22:26:14,553 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-06 22:26:14,553 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [146268323] [2023-11-06 22:26:14,553 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [146268323] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-06 22:26:14,554 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-06 22:26:14,554 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-06 22:26:14,554 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [981390344] [2023-11-06 22:26:14,554 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-06 22:26:14,681 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-06 22:26:14,681 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-06 22:26:14,682 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-06 22:26:14,682 INFO L87 Difference]: Start difference. First operand 29773 states and 40204 transitions. cyclomatic complexity: 10445 Second operand has 3 states, 3 states have (on average 29.666666666666668) internal successors, (89), 3 states have internal predecessors, (89), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-06 22:26:14,903 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-06 22:26:14,903 INFO L93 Difference]: Finished difference Result 45826 states and 61457 transitions. [2023-11-06 22:26:14,903 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 45826 states and 61457 transitions. [2023-11-06 22:26:15,136 INFO L131 ngComponentsAnalysis]: Automaton has 14 accepting balls. 45648 [2023-11-06 22:26:15,339 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 45826 states to 45826 states and 61457 transitions. [2023-11-06 22:26:15,340 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 45826 [2023-11-06 22:26:15,372 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 45826 [2023-11-06 22:26:15,372 INFO L73 IsDeterministic]: Start isDeterministic. Operand 45826 states and 61457 transitions. [2023-11-06 22:26:15,415 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-06 22:26:15,416 INFO L218 hiAutomatonCegarLoop]: Abstraction has 45826 states and 61457 transitions. [2023-11-06 22:26:15,457 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 45826 states and 61457 transitions. [2023-11-06 22:26:16,187 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 45826 to 44644. [2023-11-06 22:26:16,222 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 44644 states, 44644 states have (on average 1.343495206522713) internal successors, (59979), 44643 states have internal predecessors, (59979), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-06 22:26:16,316 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 44644 states to 44644 states and 59979 transitions. [2023-11-06 22:26:16,317 INFO L240 hiAutomatonCegarLoop]: Abstraction has 44644 states and 59979 transitions. [2023-11-06 22:26:16,317 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-06 22:26:16,318 INFO L428 stractBuchiCegarLoop]: Abstraction has 44644 states and 59979 transitions. [2023-11-06 22:26:16,318 INFO L335 stractBuchiCegarLoop]: ======== Iteration 20 ============ [2023-11-06 22:26:16,318 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 44644 states and 59979 transitions. [2023-11-06 22:26:16,446 INFO L131 ngComponentsAnalysis]: Automaton has 14 accepting balls. 44466 [2023-11-06 22:26:16,446 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-06 22:26:16,447 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-06 22:26:16,448 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-06 22:26:16,448 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-06 22:26:16,448 INFO L748 eck$LassoCheckResult]: Stem: 447990#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2; 447991#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~7#1;havoc main_~__retres1~7#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 448127#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret18#1, start_simulation_#t~ret19#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 448128#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 448149#L401 assume 1 == ~m_i~0;~m_st~0 := 0; 448150#L401-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 447923#L406-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 447924#L411-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 448288#L416-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 448289#L421-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 448234#L426-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 447889#L586 assume !(0 == ~M_E~0); 447890#L586-2 assume !(0 == ~T1_E~0); 447947#L591-1 assume !(0 == ~T2_E~0); 448074#L596-1 assume !(0 == ~T3_E~0); 448075#L601-1 assume !(0 == ~T4_E~0); 448134#L606-1 assume !(0 == ~T5_E~0); 448135#L611-1 assume !(0 == ~E_1~0); 448247#L616-1 assume !(0 == ~E_2~0); 448248#L621-1 assume !(0 == ~E_3~0); 447814#L626-1 assume !(0 == ~E_4~0); 447815#L631-1 assume !(0 == ~E_5~0); 447985#L636-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 447810#L279 assume !(1 == ~m_pc~0); 447811#L279-2 is_master_triggered_~__retres1~0#1 := 0; 448168#L290 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 447959#is_master_triggered_returnLabel#1 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 447960#L720 assume !(0 != activate_threads_~tmp~1#1); 448167#L720-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 447992#L298 assume !(1 == ~t1_pc~0); 447759#L298-2 is_transmit1_triggered_~__retres1~1#1 := 0; 447760#L309 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 447785#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 447786#L728 assume !(0 != activate_threads_~tmp___0~0#1); 447824#L728-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 447953#L317 assume !(1 == ~t2_pc~0); 447954#L317-2 is_transmit2_triggered_~__retres1~2#1 := 0; 448188#L328 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 448133#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 448001#L736 assume !(0 != activate_threads_~tmp___1~0#1); 448002#L736-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 448230#L336 assume !(1 == ~t3_pc~0); 448231#L336-2 is_transmit3_triggered_~__retres1~3#1 := 0; 448337#L347 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 447733#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 447734#L744 assume !(0 != activate_threads_~tmp___2~0#1); 448176#L744-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 448240#L355 assume !(1 == ~t4_pc~0); 448071#L355-2 is_transmit4_triggered_~__retres1~4#1 := 0; 448238#L366 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 447854#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 447855#L752 assume !(0 != activate_threads_~tmp___3~0#1); 447834#L752-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 447835#L374 assume !(1 == ~t5_pc~0); 447975#L374-2 is_transmit5_triggered_~__retres1~5#1 := 0; 447976#L385 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 447965#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 447966#L760 assume !(0 != activate_threads_~tmp___4~0#1); 448115#L760-2 havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 448116#L649 assume !(1 == ~M_E~0); 448324#L649-2 assume !(1 == ~T1_E~0); 447797#L654-1 assume !(1 == ~T2_E~0); 447798#L659-1 assume !(1 == ~T3_E~0); 448000#L664-1 assume !(1 == ~T4_E~0); 447789#L669-1 assume !(1 == ~T5_E~0); 447790#L674-1 assume !(1 == ~E_1~0); 448221#L679-1 assume !(1 == ~E_2~0); 447893#L684-1 assume !(1 == ~E_3~0); 447894#L689-1 assume !(1 == ~E_4~0); 448067#L694-1 assume !(1 == ~E_5~0); 448065#L699-1 assume { :end_inline_reset_delta_events } true; 448066#L900-2 assume !false; 456433#L901 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 456434#L561-1 [2023-11-06 22:26:16,449 INFO L750 eck$LassoCheckResult]: Loop: 456434#L561-1 assume !false; 485848#L482 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 485846#L439 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 485845#L471 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 485844#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 485843#L486 assume 0 != eval_~tmp~0#1; 485841#L486-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;havoc eval_#t~nondet5#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet5#1;havoc eval_#t~nondet5#1; 485840#L494 assume !(0 != eval_~tmp_ndt_1~0#1); 485839#L494-2 havoc eval_~tmp_ndt_1~0#1; 485838#L491-1 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0#1;havoc eval_#t~nondet6#1;eval_~tmp_ndt_2~0#1 := eval_#t~nondet6#1;havoc eval_#t~nondet6#1; 484265#L508 assume !(0 != eval_~tmp_ndt_2~0#1); 485837#L508-2 havoc eval_~tmp_ndt_2~0#1; 485861#L505-1 assume 0 == ~t2_st~0;havoc eval_~tmp_ndt_3~0#1;havoc eval_#t~nondet7#1;eval_~tmp_ndt_3~0#1 := eval_#t~nondet7#1;havoc eval_#t~nondet7#1; 485860#L522 assume !(0 != eval_~tmp_ndt_3~0#1); 485859#L522-2 havoc eval_~tmp_ndt_3~0#1; 485855#L519-1 assume !(0 == ~t3_st~0); 485853#L533-1 assume !(0 == ~t4_st~0); 485850#L547-1 assume !(0 == ~t5_st~0); 456434#L561-1 [2023-11-06 22:26:16,449 INFO L145 PredicateUnifier]: Initialized classic predicate unifier [2023-11-06 22:26:16,449 INFO L85 PathProgramCache]: Analyzing trace with hash 1336547998, now seen corresponding path program 3 times [2023-11-06 22:26:16,450 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-06 22:26:16,450 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [32340113] [2023-11-06 22:26:16,450 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-06 22:26:16,450 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-06 22:26:16,465 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-06 22:26:16,465 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-06 22:26:16,473 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-06 22:26:16,487 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-06 22:26:16,488 INFO L145 PredicateUnifier]: Initialized classic predicate unifier [2023-11-06 22:26:16,488 INFO L85 PathProgramCache]: Analyzing trace with hash 990378971, now seen corresponding path program 1 times [2023-11-06 22:26:16,488 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-06 22:26:16,489 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [9984642] [2023-11-06 22:26:16,489 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-06 22:26:16,489 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-06 22:26:16,493 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-06 22:26:16,493 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-06 22:26:16,496 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-06 22:26:16,498 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-06 22:26:16,498 INFO L145 PredicateUnifier]: Initialized classic predicate unifier [2023-11-06 22:26:16,498 INFO L85 PathProgramCache]: Analyzing trace with hash 597526840, now seen corresponding path program 1 times [2023-11-06 22:26:16,499 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-06 22:26:16,499 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1091921683] [2023-11-06 22:26:16,499 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-06 22:26:16,499 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-06 22:26:16,512 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-06 22:26:16,547 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-06 22:26:16,547 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-06 22:26:16,548 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1091921683] [2023-11-06 22:26:16,548 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1091921683] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-06 22:26:16,550 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-06 22:26:16,550 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-06 22:26:16,551 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [113323785] [2023-11-06 22:26:16,551 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-06 22:26:16,650 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-06 22:26:16,651 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-06 22:26:16,651 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-06 22:26:16,651 INFO L87 Difference]: Start difference. First operand 44644 states and 59979 transitions. cyclomatic complexity: 15349 Second operand has 3 states, 3 states have (on average 30.333333333333332) internal successors, (91), 3 states have internal predecessors, (91), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-06 22:26:16,919 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-06 22:26:16,920 INFO L93 Difference]: Finished difference Result 70726 states and 94753 transitions. [2023-11-06 22:26:16,920 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 70726 states and 94753 transitions. [2023-11-06 22:26:17,809 INFO L131 ngComponentsAnalysis]: Automaton has 14 accepting balls. 70508 [2023-11-06 22:26:17,998 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 70726 states to 70726 states and 94753 transitions. [2023-11-06 22:26:17,999 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 70726 [2023-11-06 22:26:18,042 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 70726 [2023-11-06 22:26:18,042 INFO L73 IsDeterministic]: Start isDeterministic. Operand 70726 states and 94753 transitions. [2023-11-06 22:26:18,088 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-06 22:26:18,088 INFO L218 hiAutomatonCegarLoop]: Abstraction has 70726 states and 94753 transitions. [2023-11-06 22:26:18,138 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 70726 states and 94753 transitions. [2023-11-06 22:26:19,098 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 70726 to 69250. [2023-11-06 22:26:19,157 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 69250 states, 69250 states have (on average 1.3417617328519855) internal successors, (92917), 69249 states have internal predecessors, (92917), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-06 22:26:19,374 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 69250 states to 69250 states and 92917 transitions. [2023-11-06 22:26:19,374 INFO L240 hiAutomatonCegarLoop]: Abstraction has 69250 states and 92917 transitions. [2023-11-06 22:26:19,375 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-06 22:26:19,377 INFO L428 stractBuchiCegarLoop]: Abstraction has 69250 states and 92917 transitions. [2023-11-06 22:26:19,377 INFO L335 stractBuchiCegarLoop]: ======== Iteration 21 ============ [2023-11-06 22:26:19,378 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 69250 states and 92917 transitions. [2023-11-06 22:26:19,666 INFO L131 ngComponentsAnalysis]: Automaton has 14 accepting balls. 69032 [2023-11-06 22:26:19,667 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-06 22:26:19,667 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-06 22:26:19,668 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-06 22:26:19,668 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-06 22:26:19,669 INFO L748 eck$LassoCheckResult]: Stem: 563372#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2; 563373#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~7#1;havoc main_~__retres1~7#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 563512#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret18#1, start_simulation_#t~ret19#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 563513#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 563534#L401 assume 1 == ~m_i~0;~m_st~0 := 0; 563535#L401-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 563305#L406-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 563306#L411-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 563669#L416-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 563670#L421-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 563621#L426-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 563272#L586 assume !(0 == ~M_E~0); 563273#L586-2 assume !(0 == ~T1_E~0); 563329#L591-1 assume !(0 == ~T2_E~0); 563459#L596-1 assume !(0 == ~T3_E~0); 563460#L601-1 assume !(0 == ~T4_E~0); 563519#L606-1 assume !(0 == ~T5_E~0); 563520#L611-1 assume !(0 == ~E_1~0); 563634#L616-1 assume !(0 == ~E_2~0); 563635#L621-1 assume !(0 == ~E_3~0); 563195#L626-1 assume !(0 == ~E_4~0); 563196#L631-1 assume !(0 == ~E_5~0); 563365#L636-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 563193#L279 assume !(1 == ~m_pc~0); 563194#L279-2 is_master_triggered_~__retres1~0#1 := 0; 563553#L290 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 563340#is_master_triggered_returnLabel#1 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 563341#L720 assume !(0 != activate_threads_~tmp~1#1); 563552#L720-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 563374#L298 assume !(1 == ~t1_pc~0); 563139#L298-2 is_transmit1_triggered_~__retres1~1#1 := 0; 563140#L309 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 563165#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 563166#L728 assume !(0 != activate_threads_~tmp___0~0#1); 563204#L728-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 563334#L317 assume !(1 == ~t2_pc~0); 563335#L317-2 is_transmit2_triggered_~__retres1~2#1 := 0; 563575#L328 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 563518#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 563385#L736 assume !(0 != activate_threads_~tmp___1~0#1); 563386#L736-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 563614#L336 assume !(1 == ~t3_pc~0); 563615#L336-2 is_transmit3_triggered_~__retres1~3#1 := 0; 563724#L347 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 563111#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 563112#L744 assume !(0 != activate_threads_~tmp___2~0#1); 563562#L744-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 563628#L355 assume !(1 == ~t4_pc~0); 563458#L355-2 is_transmit4_triggered_~__retres1~4#1 := 0; 563625#L366 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 563235#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 563236#L752 assume !(0 != activate_threads_~tmp___3~0#1); 563218#L752-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 563219#L374 assume !(1 == ~t5_pc~0); 563358#L374-2 is_transmit5_triggered_~__retres1~5#1 := 0; 563359#L385 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 563346#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 563347#L760 assume !(0 != activate_threads_~tmp___4~0#1); 563500#L760-2 havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 563501#L649 assume !(1 == ~M_E~0); 563712#L649-2 assume !(1 == ~T1_E~0); 563175#L654-1 assume !(1 == ~T2_E~0); 563176#L659-1 assume !(1 == ~T3_E~0); 563382#L664-1 assume !(1 == ~T4_E~0); 563167#L669-1 assume !(1 == ~T5_E~0); 563168#L674-1 assume !(1 == ~E_1~0); 563603#L679-1 assume !(1 == ~E_2~0); 563274#L684-1 assume !(1 == ~E_3~0); 563275#L689-1 assume !(1 == ~E_4~0); 563453#L694-1 assume !(1 == ~E_5~0); 563449#L699-1 assume { :end_inline_reset_delta_events } true; 563450#L900-2 assume !false; 613629#L901 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 613623#L561-1 [2023-11-06 22:26:19,669 INFO L750 eck$LassoCheckResult]: Loop: 613623#L561-1 assume !false; 613618#L482 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 613613#L439 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 613607#L471 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 613603#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 613600#L486 assume 0 != eval_~tmp~0#1; 613596#L486-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;havoc eval_#t~nondet5#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet5#1;havoc eval_#t~nondet5#1; 613594#L494 assume !(0 != eval_~tmp_ndt_1~0#1); 613593#L494-2 havoc eval_~tmp_ndt_1~0#1; 612335#L491-1 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0#1;havoc eval_#t~nondet6#1;eval_~tmp_ndt_2~0#1 := eval_#t~nondet6#1;havoc eval_#t~nondet6#1; 611764#L508 assume !(0 != eval_~tmp_ndt_2~0#1); 611765#L508-2 havoc eval_~tmp_ndt_2~0#1; 611758#L505-1 assume 0 == ~t2_st~0;havoc eval_~tmp_ndt_3~0#1;havoc eval_#t~nondet7#1;eval_~tmp_ndt_3~0#1 := eval_#t~nondet7#1;havoc eval_#t~nondet7#1; 611759#L522 assume !(0 != eval_~tmp_ndt_3~0#1); 611508#L522-2 havoc eval_~tmp_ndt_3~0#1; 611509#L519-1 assume 0 == ~t3_st~0;havoc eval_~tmp_ndt_4~0#1;havoc eval_#t~nondet8#1;eval_~tmp_ndt_4~0#1 := eval_#t~nondet8#1;havoc eval_#t~nondet8#1; 609638#L536 assume !(0 != eval_~tmp_ndt_4~0#1); 609639#L536-2 havoc eval_~tmp_ndt_4~0#1; 613634#L533-1 assume !(0 == ~t4_st~0); 613627#L547-1 assume !(0 == ~t5_st~0); 613623#L561-1 [2023-11-06 22:26:19,670 INFO L145 PredicateUnifier]: Initialized classic predicate unifier [2023-11-06 22:26:19,670 INFO L85 PathProgramCache]: Analyzing trace with hash 1336547998, now seen corresponding path program 4 times [2023-11-06 22:26:19,670 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-06 22:26:19,671 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [652666999] [2023-11-06 22:26:19,671 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-06 22:26:19,671 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-06 22:26:19,688 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-06 22:26:19,689 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-06 22:26:19,698 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-06 22:26:19,715 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-06 22:26:19,716 INFO L145 PredicateUnifier]: Initialized classic predicate unifier [2023-11-06 22:26:19,717 INFO L85 PathProgramCache]: Analyzing trace with hash -1898656693, now seen corresponding path program 1 times [2023-11-06 22:26:19,718 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-06 22:26:19,719 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1793418234] [2023-11-06 22:26:19,719 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-06 22:26:19,719 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-06 22:26:19,725 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-06 22:26:19,725 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-06 22:26:19,728 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-06 22:26:19,732 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-06 22:26:19,733 INFO L145 PredicateUnifier]: Initialized classic predicate unifier [2023-11-06 22:26:19,733 INFO L85 PathProgramCache]: Analyzing trace with hash -1472432536, now seen corresponding path program 1 times [2023-11-06 22:26:19,733 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-06 22:26:19,734 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1772394736] [2023-11-06 22:26:19,734 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-06 22:26:19,734 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-06 22:26:19,751 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-06 22:26:19,807 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-06 22:26:19,808 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-06 22:26:19,808 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1772394736] [2023-11-06 22:26:19,808 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1772394736] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-06 22:26:19,808 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-06 22:26:19,809 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-06 22:26:19,809 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [47478239] [2023-11-06 22:26:19,809 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-06 22:26:19,935 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-06 22:26:19,935 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-06 22:26:19,935 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-06 22:26:19,936 INFO L87 Difference]: Start difference. First operand 69250 states and 92917 transitions. cyclomatic complexity: 23681 Second operand has 3 states, 3 states have (on average 31.0) internal successors, (93), 3 states have internal predecessors, (93), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-06 22:26:20,515 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-06 22:26:20,515 INFO L93 Difference]: Finished difference Result 121238 states and 162499 transitions. [2023-11-06 22:26:20,516 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 121238 states and 162499 transitions. [2023-11-06 22:26:21,693 INFO L131 ngComponentsAnalysis]: Automaton has 14 accepting balls. 120880 [2023-11-06 22:26:21,994 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 121238 states to 121238 states and 162499 transitions. [2023-11-06 22:26:21,994 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 121238 [2023-11-06 22:26:22,067 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 121238 [2023-11-06 22:26:22,067 INFO L73 IsDeterministic]: Start isDeterministic. Operand 121238 states and 162499 transitions. [2023-11-06 22:26:22,169 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-06 22:26:22,170 INFO L218 hiAutomatonCegarLoop]: Abstraction has 121238 states and 162499 transitions. [2023-11-06 22:26:22,272 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 121238 states and 162499 transitions. [2023-11-06 22:26:23,872 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 121238 to 117794. [2023-11-06 22:26:23,946 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 117794 states, 117794 states have (on average 1.3447119547684943) internal successors, (158399), 117793 states have internal predecessors, (158399), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-06 22:26:24,178 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 117794 states to 117794 states and 158399 transitions. [2023-11-06 22:26:24,178 INFO L240 hiAutomatonCegarLoop]: Abstraction has 117794 states and 158399 transitions. [2023-11-06 22:26:24,179 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-06 22:26:24,179 INFO L428 stractBuchiCegarLoop]: Abstraction has 117794 states and 158399 transitions. [2023-11-06 22:26:24,179 INFO L335 stractBuchiCegarLoop]: ======== Iteration 22 ============ [2023-11-06 22:26:24,181 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 117794 states and 158399 transitions. [2023-11-06 22:26:25,112 INFO L131 ngComponentsAnalysis]: Automaton has 14 accepting balls. 117436 [2023-11-06 22:26:25,127 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-06 22:26:25,127 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-06 22:26:25,129 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-06 22:26:25,141 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-06 22:26:25,144 INFO L748 eck$LassoCheckResult]: Stem: 753869#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2; 753870#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~7#1;havoc main_~__retres1~7#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 754007#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret18#1, start_simulation_#t~ret19#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 754008#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 754029#L401 assume 1 == ~m_i~0;~m_st~0 := 0; 754030#L401-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 753802#L406-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 753803#L411-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 754182#L416-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 754183#L421-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 754120#L426-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 753768#L586 assume !(0 == ~M_E~0); 753769#L586-2 assume !(0 == ~T1_E~0); 753827#L591-1 assume !(0 == ~T2_E~0); 753957#L596-1 assume !(0 == ~T3_E~0); 753958#L601-1 assume !(0 == ~T4_E~0); 754015#L606-1 assume !(0 == ~T5_E~0); 754016#L611-1 assume !(0 == ~E_1~0); 754136#L616-1 assume !(0 == ~E_2~0); 754137#L621-1 assume !(0 == ~E_3~0); 753689#L626-1 assume !(0 == ~E_4~0); 753690#L631-1 assume !(0 == ~E_5~0); 753864#L636-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 753685#L279 assume !(1 == ~m_pc~0); 753686#L279-2 is_master_triggered_~__retres1~0#1 := 0; 754049#L290 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 753837#is_master_triggered_returnLabel#1 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 753838#L720 assume !(0 != activate_threads_~tmp~1#1); 754048#L720-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 753871#L298 assume !(1 == ~t1_pc~0); 753632#L298-2 is_transmit1_triggered_~__retres1~1#1 := 0; 753633#L309 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 753659#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 753660#L728 assume !(0 != activate_threads_~tmp___0~0#1); 753699#L728-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 753831#L317 assume !(1 == ~t2_pc~0); 753832#L317-2 is_transmit2_triggered_~__retres1~2#1 := 0; 754070#L328 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 754012#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 753880#L736 assume !(0 != activate_threads_~tmp___1~0#1); 753881#L736-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 754116#L336 assume !(1 == ~t3_pc~0); 754117#L336-2 is_transmit3_triggered_~__retres1~3#1 := 0; 754238#L347 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 753607#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 753608#L744 assume !(0 != activate_threads_~tmp___2~0#1); 754057#L744-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 754126#L355 assume !(1 == ~t4_pc~0); 753954#L355-2 is_transmit4_triggered_~__retres1~4#1 := 0; 754124#L366 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 753732#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 753733#L752 assume !(0 != activate_threads_~tmp___3~0#1); 753712#L752-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 753713#L374 assume !(1 == ~t5_pc~0); 753853#L374-2 is_transmit5_triggered_~__retres1~5#1 := 0; 753854#L385 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 753843#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 753844#L760 assume !(0 != activate_threads_~tmp___4~0#1); 753995#L760-2 havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 753996#L649 assume !(1 == ~M_E~0); 754227#L649-2 assume !(1 == ~T1_E~0); 753671#L654-1 assume !(1 == ~T2_E~0); 753672#L659-1 assume !(1 == ~T3_E~0); 753879#L664-1 assume !(1 == ~T4_E~0); 753663#L669-1 assume !(1 == ~T5_E~0); 753664#L674-1 assume !(1 == ~E_1~0); 754106#L679-1 assume !(1 == ~E_2~0); 753772#L684-1 assume !(1 == ~E_3~0); 753773#L689-1 assume !(1 == ~E_4~0); 753950#L694-1 assume !(1 == ~E_5~0); 753948#L699-1 assume { :end_inline_reset_delta_events } true; 753949#L900-2 assume !false; 811660#L901 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 811655#L561-1 [2023-11-06 22:26:25,145 INFO L750 eck$LassoCheckResult]: Loop: 811655#L561-1 assume !false; 811653#L482 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 811650#L439 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 811647#L471 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 811645#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 811643#L486 assume 0 != eval_~tmp~0#1; 811640#L486-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;havoc eval_#t~nondet5#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet5#1;havoc eval_#t~nondet5#1; 811638#L494 assume !(0 != eval_~tmp_ndt_1~0#1); 811637#L494-2 havoc eval_~tmp_ndt_1~0#1; 811636#L491-1 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0#1;havoc eval_#t~nondet6#1;eval_~tmp_ndt_2~0#1 := eval_#t~nondet6#1;havoc eval_#t~nondet6#1; 811604#L508 assume !(0 != eval_~tmp_ndt_2~0#1); 811635#L508-2 havoc eval_~tmp_ndt_2~0#1; 811661#L505-1 assume 0 == ~t2_st~0;havoc eval_~tmp_ndt_3~0#1;havoc eval_#t~nondet7#1;eval_~tmp_ndt_3~0#1 := eval_#t~nondet7#1;havoc eval_#t~nondet7#1; 811656#L522 assume !(0 != eval_~tmp_ndt_3~0#1); 811654#L522-2 havoc eval_~tmp_ndt_3~0#1; 811652#L519-1 assume 0 == ~t3_st~0;havoc eval_~tmp_ndt_4~0#1;havoc eval_#t~nondet8#1;eval_~tmp_ndt_4~0#1 := eval_#t~nondet8#1;havoc eval_#t~nondet8#1; 811648#L536 assume !(0 != eval_~tmp_ndt_4~0#1); 811646#L536-2 havoc eval_~tmp_ndt_4~0#1; 811644#L533-1 assume 0 == ~t4_st~0;havoc eval_~tmp_ndt_5~0#1;havoc eval_#t~nondet9#1;eval_~tmp_ndt_5~0#1 := eval_#t~nondet9#1;havoc eval_#t~nondet9#1; 811304#L550 assume !(0 != eval_~tmp_ndt_5~0#1); 811642#L550-2 havoc eval_~tmp_ndt_5~0#1; 811658#L547-1 assume !(0 == ~t5_st~0); 811655#L561-1 [2023-11-06 22:26:25,145 INFO L145 PredicateUnifier]: Initialized classic predicate unifier [2023-11-06 22:26:25,146 INFO L85 PathProgramCache]: Analyzing trace with hash 1336547998, now seen corresponding path program 5 times [2023-11-06 22:26:25,146 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-06 22:26:25,146 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1799537355] [2023-11-06 22:26:25,146 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-06 22:26:25,152 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-06 22:26:25,179 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-06 22:26:25,179 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-06 22:26:25,187 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-06 22:26:25,227 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-06 22:26:25,228 INFO L145 PredicateUnifier]: Initialized classic predicate unifier [2023-11-06 22:26:25,228 INFO L85 PathProgramCache]: Analyzing trace with hash 746708699, now seen corresponding path program 1 times [2023-11-06 22:26:25,228 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-06 22:26:25,229 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [93295073] [2023-11-06 22:26:25,229 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-06 22:26:25,229 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-06 22:26:25,234 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-06 22:26:25,234 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-06 22:26:25,236 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-06 22:26:25,252 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-06 22:26:25,252 INFO L145 PredicateUnifier]: Initialized classic predicate unifier [2023-11-06 22:26:25,253 INFO L85 PathProgramCache]: Analyzing trace with hash -1968736840, now seen corresponding path program 1 times [2023-11-06 22:26:25,253 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-06 22:26:25,253 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [415563211] [2023-11-06 22:26:25,253 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-06 22:26:25,253 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-06 22:26:25,279 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-06 22:26:25,357 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-06 22:26:25,357 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-06 22:26:25,357 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [415563211] [2023-11-06 22:26:25,358 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [415563211] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-06 22:26:25,358 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-06 22:26:25,358 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2023-11-06 22:26:25,358 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [90749417] [2023-11-06 22:26:25,358 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-06 22:26:25,514 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-06 22:26:25,515 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-06 22:26:25,515 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-06 22:26:25,515 INFO L87 Difference]: Start difference. First operand 117794 states and 158399 transitions. cyclomatic complexity: 40619 Second operand has 3 states, 2 states have (on average 47.5) internal successors, (95), 3 states have internal predecessors, (95), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-06 22:26:26,061 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-06 22:26:26,062 INFO L93 Difference]: Finished difference Result 137184 states and 183887 transitions. [2023-11-06 22:26:26,062 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 137184 states and 183887 transitions. [2023-11-06 22:26:26,628 INFO L131 ngComponentsAnalysis]: Automaton has 15 accepting balls. 133358 [2023-11-06 22:26:27,743 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 137184 states to 137184 states and 183887 transitions. [2023-11-06 22:26:27,743 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 137184 [2023-11-06 22:26:27,819 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 137184 [2023-11-06 22:26:27,820 INFO L73 IsDeterministic]: Start isDeterministic. Operand 137184 states and 183887 transitions. [2023-11-06 22:26:27,894 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-06 22:26:27,895 INFO L218 hiAutomatonCegarLoop]: Abstraction has 137184 states and 183887 transitions. [2023-11-06 22:26:27,988 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 137184 states and 183887 transitions. [2023-11-06 22:26:29,874 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 137184 to 137184. [2023-11-06 22:26:29,989 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 137184 states, 137184 states have (on average 1.3404405761604852) internal successors, (183887), 137183 states have internal predecessors, (183887), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-06 22:26:30,364 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 137184 states to 137184 states and 183887 transitions. [2023-11-06 22:26:30,365 INFO L240 hiAutomatonCegarLoop]: Abstraction has 137184 states and 183887 transitions. [2023-11-06 22:26:30,365 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-06 22:26:30,366 INFO L428 stractBuchiCegarLoop]: Abstraction has 137184 states and 183887 transitions. [2023-11-06 22:26:30,366 INFO L335 stractBuchiCegarLoop]: ======== Iteration 23 ============ [2023-11-06 22:26:30,366 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 137184 states and 183887 transitions. [2023-11-06 22:26:30,787 INFO L131 ngComponentsAnalysis]: Automaton has 15 accepting balls. 133358 [2023-11-06 22:26:30,787 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-06 22:26:30,787 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-06 22:26:30,789 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-06 22:26:30,789 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-06 22:26:30,789 INFO L748 eck$LassoCheckResult]: Stem: 1008849#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2; 1008850#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~7#1;havoc main_~__retres1~7#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 1008985#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret18#1, start_simulation_#t~ret19#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 1008986#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 1009006#L401 assume 1 == ~m_i~0;~m_st~0 := 0; 1009007#L401-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 1008785#L406-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 1008786#L411-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 1009141#L416-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 1009142#L421-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 1009092#L426-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 1008751#L586 assume !(0 == ~M_E~0); 1008752#L586-2 assume !(0 == ~T1_E~0); 1008808#L591-1 assume !(0 == ~T2_E~0); 1008939#L596-1 assume !(0 == ~T3_E~0); 1008940#L601-1 assume !(0 == ~T4_E~0); 1008992#L606-1 assume !(0 == ~T5_E~0); 1008993#L611-1 assume !(0 == ~E_1~0); 1009105#L616-1 assume !(0 == ~E_2~0); 1009106#L621-1 assume !(0 == ~E_3~0); 1008673#L626-1 assume !(0 == ~E_4~0); 1008674#L631-1 assume !(0 == ~E_5~0); 1008844#L636-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1008669#L279 assume !(1 == ~m_pc~0); 1008670#L279-2 is_master_triggered_~__retres1~0#1 := 0; 1009025#L290 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1008819#is_master_triggered_returnLabel#1 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 1008820#L720 assume !(0 != activate_threads_~tmp~1#1); 1009024#L720-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1008851#L298 assume !(1 == ~t1_pc~0); 1008618#L298-2 is_transmit1_triggered_~__retres1~1#1 := 0; 1008619#L309 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1008644#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 1008645#L728 assume !(0 != activate_threads_~tmp___0~0#1); 1008683#L728-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1008813#L317 assume !(1 == ~t2_pc~0); 1008814#L317-2 is_transmit2_triggered_~__retres1~2#1 := 0; 1009049#L328 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1008991#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 1008860#L736 assume !(0 != activate_threads_~tmp___1~0#1); 1008861#L736-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1009087#L336 assume !(1 == ~t3_pc~0); 1009088#L336-2 is_transmit3_triggered_~__retres1~3#1 := 0; 1009189#L347 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1008593#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 1008594#L744 assume !(0 != activate_threads_~tmp___2~0#1); 1009033#L744-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1009098#L355 assume !(1 == ~t4_pc~0); 1008936#L355-2 is_transmit4_triggered_~__retres1~4#1 := 0; 1009096#L366 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1008714#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 1008715#L752 assume !(0 != activate_threads_~tmp___3~0#1); 1008694#L752-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1008695#L374 assume !(1 == ~t5_pc~0); 1008834#L374-2 is_transmit5_triggered_~__retres1~5#1 := 0; 1008835#L385 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1008825#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 1008826#L760 assume !(0 != activate_threads_~tmp___4~0#1); 1008974#L760-2 havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1008975#L649 assume !(1 == ~M_E~0); 1009179#L649-2 assume !(1 == ~T1_E~0); 1008656#L654-1 assume !(1 == ~T2_E~0); 1008657#L659-1 assume !(1 == ~T3_E~0); 1008859#L664-1 assume !(1 == ~T4_E~0); 1008648#L669-1 assume !(1 == ~T5_E~0); 1008649#L674-1 assume !(1 == ~E_1~0); 1009077#L679-1 assume !(1 == ~E_2~0); 1008755#L684-1 assume !(1 == ~E_3~0); 1008756#L689-1 assume !(1 == ~E_4~0); 1008931#L694-1 assume !(1 == ~E_5~0); 1008929#L699-1 assume { :end_inline_reset_delta_events } true; 1008930#L900-2 assume !false; 1139597#L901 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 1139595#L561-1 [2023-11-06 22:26:30,790 INFO L750 eck$LassoCheckResult]: Loop: 1139595#L561-1 assume !false; 1139593#L482 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 1139578#L439 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 1139579#L471 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 1141755#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 1141753#L486 assume 0 != eval_~tmp~0#1; 1141751#L486-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;havoc eval_#t~nondet5#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet5#1;havoc eval_#t~nondet5#1; 1141748#L494 assume !(0 != eval_~tmp_ndt_1~0#1); 1141749#L494-2 havoc eval_~tmp_ndt_1~0#1; 1086608#L491-1 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0#1;havoc eval_#t~nondet6#1;eval_~tmp_ndt_2~0#1 := eval_#t~nondet6#1;havoc eval_#t~nondet6#1; 1086606#L508 assume !(0 != eval_~tmp_ndt_2~0#1); 1086603#L508-2 havoc eval_~tmp_ndt_2~0#1; 1086599#L505-1 assume 0 == ~t2_st~0;havoc eval_~tmp_ndt_3~0#1;havoc eval_#t~nondet7#1;eval_~tmp_ndt_3~0#1 := eval_#t~nondet7#1;havoc eval_#t~nondet7#1; 1083837#L522 assume !(0 != eval_~tmp_ndt_3~0#1); 1083838#L522-2 havoc eval_~tmp_ndt_3~0#1; 1120070#L519-1 assume 0 == ~t3_st~0;havoc eval_~tmp_ndt_4~0#1;havoc eval_#t~nondet8#1;eval_~tmp_ndt_4~0#1 := eval_#t~nondet8#1;havoc eval_#t~nondet8#1; 1120068#L536 assume !(0 != eval_~tmp_ndt_4~0#1); 1120066#L536-2 havoc eval_~tmp_ndt_4~0#1; 1120063#L533-1 assume 0 == ~t4_st~0;havoc eval_~tmp_ndt_5~0#1;havoc eval_#t~nondet9#1;eval_~tmp_ndt_5~0#1 := eval_#t~nondet9#1;havoc eval_#t~nondet9#1; 1120060#L550 assume !(0 != eval_~tmp_ndt_5~0#1); 1120058#L550-2 havoc eval_~tmp_ndt_5~0#1; 1120056#L547-1 assume 0 == ~t5_st~0;havoc eval_~tmp_ndt_6~0#1;havoc eval_#t~nondet10#1;eval_~tmp_ndt_6~0#1 := eval_#t~nondet10#1;havoc eval_#t~nondet10#1; 1120054#L564 assume !(0 != eval_~tmp_ndt_6~0#1); 1120055#L564-2 havoc eval_~tmp_ndt_6~0#1; 1139595#L561-1 [2023-11-06 22:26:30,790 INFO L145 PredicateUnifier]: Initialized classic predicate unifier [2023-11-06 22:26:30,791 INFO L85 PathProgramCache]: Analyzing trace with hash 1336547998, now seen corresponding path program 6 times [2023-11-06 22:26:30,791 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-06 22:26:30,791 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [523224675] [2023-11-06 22:26:30,791 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-06 22:26:30,791 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-06 22:26:30,806 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-06 22:26:30,806 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-06 22:26:30,814 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-06 22:26:30,829 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-06 22:26:30,830 INFO L145 PredicateUnifier]: Initialized classic predicate unifier [2023-11-06 22:26:30,830 INFO L85 PathProgramCache]: Analyzing trace with hash 327523058, now seen corresponding path program 1 times [2023-11-06 22:26:30,830 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-06 22:26:30,831 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1907973091] [2023-11-06 22:26:30,831 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-06 22:26:30,831 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-06 22:26:30,836 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-06 22:26:30,836 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-06 22:26:30,839 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-06 22:26:30,842 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-06 22:26:30,842 INFO L145 PredicateUnifier]: Initialized classic predicate unifier [2023-11-06 22:26:30,842 INFO L85 PathProgramCache]: Analyzing trace with hash 2124476047, now seen corresponding path program 1 times [2023-11-06 22:26:30,843 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-06 22:26:30,843 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [751728965] [2023-11-06 22:26:30,843 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-06 22:26:30,843 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-06 22:26:30,857 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-06 22:26:30,857 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-06 22:26:30,866 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-06 22:26:30,888 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-06 22:26:33,638 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-06 22:26:33,638 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-06 22:26:33,676 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-06 22:26:33,923 INFO L201 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer CFG 06.11 10:26:33 BoogieIcfgContainer [2023-11-06 22:26:33,923 INFO L131 PluginConnector]: ------------------------ END BuchiAutomizer---------------------------- [2023-11-06 22:26:33,924 INFO L112 PluginConnector]: ------------------------Witness Printer---------------------------- [2023-11-06 22:26:33,924 INFO L270 PluginConnector]: Initializing Witness Printer... [2023-11-06 22:26:33,924 INFO L274 PluginConnector]: Witness Printer initialized [2023-11-06 22:26:33,925 INFO L184 PluginConnector]: Executing the observer RCFGCatcher from plugin Witness Printer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 06.11 10:25:57" (3/4) ... [2023-11-06 22:26:33,927 INFO L134 WitnessPrinter]: Generating witness for non-termination counterexample [2023-11-06 22:26:34,054 INFO L149 WitnessManager]: Wrote witness to /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_0e04129a-54f6-4cb3-8369-3da3b1f77b7c/bin/uautomizer-verify-WvqO1wxjHP/witness.graphml.graphml [2023-11-06 22:26:34,054 INFO L131 PluginConnector]: ------------------------ END Witness Printer---------------------------- [2023-11-06 22:26:34,055 INFO L158 Benchmark]: Toolchain (without parser) took 39208.86ms. Allocated memory was 203.4MB in the beginning and 13.0GB in the end (delta: 12.8GB). Free memory was 157.5MB in the beginning and 10.9GB in the end (delta: -10.7GB). Peak memory consumption was 2.1GB. Max. memory is 16.1GB. [2023-11-06 22:26:34,055 INFO L158 Benchmark]: CDTParser took 0.36ms. Allocated memory is still 130.0MB. Free memory is still 82.0MB. There was no memory consumed. Max. memory is 16.1GB. [2023-11-06 22:26:34,056 INFO L158 Benchmark]: CACSL2BoogieTranslator took 502.40ms. Allocated memory is still 203.4MB. Free memory was 157.5MB in the beginning and 141.6MB in the end (delta: 15.9MB). Peak memory consumption was 14.7MB. Max. memory is 16.1GB. [2023-11-06 22:26:34,056 INFO L158 Benchmark]: Boogie Procedure Inliner took 73.81ms. Allocated memory is still 203.4MB. Free memory was 141.6MB in the beginning and 136.5MB in the end (delta: 5.1MB). Peak memory consumption was 6.3MB. Max. memory is 16.1GB. [2023-11-06 22:26:34,057 INFO L158 Benchmark]: Boogie Preprocessor took 114.95ms. Allocated memory is still 203.4MB. Free memory was 136.5MB in the beginning and 132.3MB in the end (delta: 4.2MB). Peak memory consumption was 4.2MB. Max. memory is 16.1GB. [2023-11-06 22:26:34,057 INFO L158 Benchmark]: RCFGBuilder took 1471.21ms. Allocated memory is still 203.4MB. Free memory was 132.3MB in the beginning and 77.2MB in the end (delta: 55.1MB). Peak memory consumption was 54.5MB. Max. memory is 16.1GB. [2023-11-06 22:26:34,058 INFO L158 Benchmark]: BuchiAutomizer took 36907.88ms. Allocated memory was 203.4MB in the beginning and 13.0GB in the end (delta: 12.8GB). Free memory was 76.6MB in the beginning and 10.9GB in the end (delta: -10.8GB). Peak memory consumption was 2.0GB. Max. memory is 16.1GB. [2023-11-06 22:26:34,058 INFO L158 Benchmark]: Witness Printer took 130.70ms. Allocated memory is still 13.0GB. Free memory was 10.9GB in the beginning and 10.9GB in the end (delta: 9.5MB). Peak memory consumption was 10.5MB. Max. memory is 16.1GB. [2023-11-06 22:26:34,061 INFO L338 ainManager$Toolchain]: ####################### End [Toolchain 1] ####################### --- Results --- * Results from de.uni_freiburg.informatik.ultimate.core: - StatisticsResult: Toolchain Benchmarks Benchmark results are: * CDTParser took 0.36ms. Allocated memory is still 130.0MB. Free memory is still 82.0MB. There was no memory consumed. Max. memory is 16.1GB. * CACSL2BoogieTranslator took 502.40ms. Allocated memory is still 203.4MB. Free memory was 157.5MB in the beginning and 141.6MB in the end (delta: 15.9MB). Peak memory consumption was 14.7MB. Max. memory is 16.1GB. * Boogie Procedure Inliner took 73.81ms. Allocated memory is still 203.4MB. Free memory was 141.6MB in the beginning and 136.5MB in the end (delta: 5.1MB). Peak memory consumption was 6.3MB. Max. memory is 16.1GB. * Boogie Preprocessor took 114.95ms. Allocated memory is still 203.4MB. Free memory was 136.5MB in the beginning and 132.3MB in the end (delta: 4.2MB). Peak memory consumption was 4.2MB. Max. memory is 16.1GB. * RCFGBuilder took 1471.21ms. Allocated memory is still 203.4MB. Free memory was 132.3MB in the beginning and 77.2MB in the end (delta: 55.1MB). Peak memory consumption was 54.5MB. Max. memory is 16.1GB. * BuchiAutomizer took 36907.88ms. Allocated memory was 203.4MB in the beginning and 13.0GB in the end (delta: 12.8GB). Free memory was 76.6MB in the beginning and 10.9GB in the end (delta: -10.8GB). Peak memory consumption was 2.0GB. Max. memory is 16.1GB. * Witness Printer took 130.70ms. Allocated memory is still 13.0GB. Free memory was 10.9GB in the beginning and 10.9GB in the end (delta: 9.5MB). Peak memory consumption was 10.5MB. Max. memory is 16.1GB. * Results from de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction: - StatisticsResult: Constructed decomposition of program Your program was decomposed into 22 terminating modules (22 trivial, 0 deterministic, 0 nondeterministic) and one nonterminating remainder module.22 modules have a trivial ranking function, the largest among these consists of 5 locations. The remainder module has 137184 locations. - StatisticsResult: Timing statistics BüchiAutomizer plugin needed 36.6s and 23 iterations. TraceHistogramMax:1. Analysis of lassos took 8.1s. Construction of modules took 1.1s. Büchi inclusion checks took 23.9s. Highest rank in rank-based complementation 0. Minimization of det autom 22. Minimization of nondet autom 0. Automata minimization 11.2s AutomataMinimizationTime, 22 MinimizatonAttempts, 53413 StatesRemovedByMinimization, 14 NontrivialMinimizations. Non-live state removal took 7.6s Buchi closure took 0.6s. Biggest automaton had -1 states and ocurred in iteration -1. Nontrivial modules had stage [0, 0, 0, 0, 0]. InterpolantCoveringCapabilityFinite: 0/0 InterpolantCoveringCapabilityBuchi: 0/0 HoareTripleCheckerStatistics: 0 mSolverCounterUnknown, 19301 SdHoareTripleChecker+Valid, 1.4s IncrementalHoareTripleChecker+Time, 0 mSdLazyCounter, 19301 mSDsluCounter, 33381 SdHoareTripleChecker+Invalid, 1.1s Time, 0 mProtectedAction, 0 SdHoareTripleChecker+Unchecked, 0 IncrementalHoareTripleChecker+Unchecked, 16299 mSDsCounter, 316 IncrementalHoareTripleChecker+Valid, 0 mProtectedPredicate, 772 IncrementalHoareTripleChecker+Invalid, 1088 SdHoareTripleChecker+Unknown, 0 mSolverCounterNotChecked, 316 mSolverCounterUnsat, 17082 mSDtfsCounter, 772 mSolverCounterSat, 0.3s SdHoareTripleChecker+Time, 0 IncrementalHoareTripleChecker+Unknown LassoAnalysisResults: nont1 unkn0 SFLI3 SFLT0 conc5 concLT0 SILN1 SILU0 SILI13 SILT0 lasso0 LassoPreprocessingBenchmarks: LassoTerminationAnalysisBenchmarks: not availableLassoTerminationAnalysisBenchmarks: LassoNonterminationAnalysisSatFixpoint: 0 LassoNonterminationAnalysisSatUnbounded: 0 LassoNonterminationAnalysisUnsat: 0 LassoNonterminationAnalysisUnknown: 0 LassoNonterminationAnalysisTime: 0.0s InitialAbstractionConstructionTime: 0.0s - TerminationAnalysisResult: Nontermination possible Buchi Automizer proved that your program is nonterminating for some inputs - LassoShapedNonTerminationArgument [Line: 481]: Nontermination argument in form of an infinite program execution. Nontermination argument in form of an infinite program execution. Stem: [L25] int m_pc = 0; [L26] int t1_pc = 0; [L27] int t2_pc = 0; [L28] int t3_pc = 0; [L29] int t4_pc = 0; [L30] int t5_pc = 0; [L31] int m_st ; [L32] int t1_st ; [L33] int t2_st ; [L34] int t3_st ; [L35] int t4_st ; [L36] int t5_st ; [L37] int m_i ; [L38] int t1_i ; [L39] int t2_i ; [L40] int t3_i ; [L41] int t4_i ; [L42] int t5_i ; [L43] int M_E = 2; [L44] int T1_E = 2; [L45] int T2_E = 2; [L46] int T3_E = 2; [L47] int T4_E = 2; [L48] int T5_E = 2; [L49] int E_1 = 2; [L50] int E_2 = 2; [L51] int E_3 = 2; [L52] int E_4 = 2; [L53] int E_5 = 2; VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, m_i=0, m_pc=0, m_st=0, t1_i=0, t1_pc=0, t1_st=0, t2_i=0, t2_pc=0, t2_st=0, t3_i=0, t3_pc=0, t3_st=0, t4_i=0, t4_pc=0, t4_st=0, t5_i=0, t5_pc=0, t5_st=0] [L945] int __retres1 ; [L949] CALL init_model() [L856] m_i = 1 [L857] t1_i = 1 [L858] t2_i = 1 [L859] t3_i = 1 [L860] t4_i = 1 [L861] t5_i = 1 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0] [L949] RET init_model() [L950] CALL start_simulation() [L886] int kernel_st ; [L887] int tmp ; [L888] int tmp___0 ; [L892] kernel_st = 0 [L893] FCALL update_channels() [L894] CALL init_threads() [L401] COND TRUE m_i == 1 [L402] m_st = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0] [L406] COND TRUE t1_i == 1 [L407] t1_st = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0] [L411] COND TRUE t2_i == 1 [L412] t2_st = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0] [L416] COND TRUE t3_i == 1 [L417] t3_st = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0] [L421] COND TRUE t4_i == 1 [L422] t4_st = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0] [L426] COND TRUE t5_i == 1 [L427] t5_st = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0] [L894] RET init_threads() [L895] CALL fire_delta_events() [L586] COND FALSE !(M_E == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0] [L591] COND FALSE !(T1_E == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0] [L596] COND FALSE !(T2_E == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0] [L601] COND FALSE !(T3_E == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0] [L606] COND FALSE !(T4_E == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0] [L611] COND FALSE !(T5_E == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0] [L616] COND FALSE !(E_1 == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0] [L621] COND FALSE !(E_2 == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0] [L626] COND FALSE !(E_3 == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0] [L631] COND FALSE !(E_4 == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0] [L636] COND FALSE !(E_5 == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0] [L895] RET fire_delta_events() [L896] CALL activate_threads() [L709] int tmp ; [L710] int tmp___0 ; [L711] int tmp___1 ; [L712] int tmp___2 ; [L713] int tmp___3 ; [L714] int tmp___4 ; [L718] CALL, EXPR is_master_triggered() [L276] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0] [L279] COND FALSE !(m_pc == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0] [L289] __retres1 = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, __retres1=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0] [L291] return (__retres1); VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, \result=0, __retres1=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0] [L718] RET, EXPR is_master_triggered() [L718] tmp = is_master_triggered() [L720] COND FALSE !(\read(tmp)) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, tmp=0] [L726] CALL, EXPR is_transmit1_triggered() [L295] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0] [L298] COND FALSE !(t1_pc == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0] [L308] __retres1 = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, __retres1=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0] [L310] return (__retres1); VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, \result=0, __retres1=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0] [L726] RET, EXPR is_transmit1_triggered() [L726] tmp___0 = is_transmit1_triggered() [L728] COND FALSE !(\read(tmp___0)) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, tmp=0, tmp___0=0] [L734] CALL, EXPR is_transmit2_triggered() [L314] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0] [L317] COND FALSE !(t2_pc == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0] [L327] __retres1 = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, __retres1=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0] [L329] return (__retres1); VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, \result=0, __retres1=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0] [L734] RET, EXPR is_transmit2_triggered() [L734] tmp___1 = is_transmit2_triggered() [L736] COND FALSE !(\read(tmp___1)) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, tmp=0, tmp___0=0, tmp___1=0] [L742] CALL, EXPR is_transmit3_triggered() [L333] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0] [L336] COND FALSE !(t3_pc == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0] [L346] __retres1 = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, __retres1=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0] [L348] return (__retres1); VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, \result=0, __retres1=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0] [L742] RET, EXPR is_transmit3_triggered() [L742] tmp___2 = is_transmit3_triggered() [L744] COND FALSE !(\read(tmp___2)) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, tmp=0, tmp___0=0, tmp___1=0, tmp___2=0] [L750] CALL, EXPR is_transmit4_triggered() [L352] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0] [L355] COND FALSE !(t4_pc == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0] [L365] __retres1 = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, __retres1=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0] [L367] return (__retres1); VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, \result=0, __retres1=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0] [L750] RET, EXPR is_transmit4_triggered() [L750] tmp___3 = is_transmit4_triggered() [L752] COND FALSE !(\read(tmp___3)) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, tmp=0, tmp___0=0, tmp___1=0, tmp___2=0, tmp___3=0] [L758] CALL, EXPR is_transmit5_triggered() [L371] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0] [L374] COND FALSE !(t5_pc == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0] [L384] __retres1 = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, __retres1=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0] [L386] return (__retres1); VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, \result=0, __retres1=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0] [L758] RET, EXPR is_transmit5_triggered() [L758] tmp___4 = is_transmit5_triggered() [L760] COND FALSE !(\read(tmp___4)) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, tmp=0, tmp___0=0, tmp___1=0, tmp___2=0, tmp___3=0, tmp___4=0] [L896] RET activate_threads() [L897] CALL reset_delta_events() [L649] COND FALSE !(M_E == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0] [L654] COND FALSE !(T1_E == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0] [L659] COND FALSE !(T2_E == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0] [L664] COND FALSE !(T3_E == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0] [L669] COND FALSE !(T4_E == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0] [L674] COND FALSE !(T5_E == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0] [L679] COND FALSE !(E_1 == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0] [L684] COND FALSE !(E_2 == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0] [L689] COND FALSE !(E_3 == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0] [L694] COND FALSE !(E_4 == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0] [L699] COND FALSE !(E_5 == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0] [L897] RET reset_delta_events() [L900] COND TRUE 1 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, kernel_st=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0] [L903] kernel_st = 1 [L904] CALL eval() [L477] int tmp ; VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0] Loop: [L481] COND TRUE 1 [L484] CALL, EXPR exists_runnable_thread() [L436] int __retres1 ; [L439] COND TRUE m_st == 0 [L440] __retres1 = 1 [L472] return (__retres1); [L484] RET, EXPR exists_runnable_thread() [L484] tmp = exists_runnable_thread() [L486] COND TRUE \read(tmp) [L491] COND TRUE m_st == 0 [L492] int tmp_ndt_1; [L493] EXPR tmp_ndt_1 = __VERIFIER_nondet_int() [L494] COND FALSE, EXPR !(\read(tmp_ndt_1)) [L491-L502] { int tmp_ndt_1; tmp_ndt_1 = __VERIFIER_nondet_int(); if (tmp_ndt_1) { { m_st = 1; master(); } } else { } } [L505] COND TRUE t1_st == 0 [L506] int tmp_ndt_2; [L507] EXPR tmp_ndt_2 = __VERIFIER_nondet_int() [L508] COND FALSE, EXPR !(\read(tmp_ndt_2)) [L505-L516] { int tmp_ndt_2; tmp_ndt_2 = __VERIFIER_nondet_int(); if (tmp_ndt_2) { { t1_st = 1; transmit1(); } } else { } } [L519] COND TRUE t2_st == 0 [L520] int tmp_ndt_3; [L521] EXPR tmp_ndt_3 = __VERIFIER_nondet_int() [L522] COND FALSE, EXPR !(\read(tmp_ndt_3)) [L519-L530] { int tmp_ndt_3; tmp_ndt_3 = __VERIFIER_nondet_int(); if (tmp_ndt_3) { { t2_st = 1; transmit2(); } } else { } } [L533] COND TRUE t3_st == 0 [L534] int tmp_ndt_4; [L535] EXPR tmp_ndt_4 = __VERIFIER_nondet_int() [L536] COND FALSE, EXPR !(\read(tmp_ndt_4)) [L533-L544] { int tmp_ndt_4; tmp_ndt_4 = __VERIFIER_nondet_int(); if (tmp_ndt_4) { { t3_st = 1; transmit3(); } } else { } } [L547] COND TRUE t4_st == 0 [L548] int tmp_ndt_5; [L549] EXPR tmp_ndt_5 = __VERIFIER_nondet_int() [L550] COND FALSE, EXPR !(\read(tmp_ndt_5)) [L547-L558] { int tmp_ndt_5; tmp_ndt_5 = __VERIFIER_nondet_int(); if (tmp_ndt_5) { { t4_st = 1; transmit4(); } } else { } } [L561] COND TRUE t5_st == 0 [L562] int tmp_ndt_6; [L563] EXPR tmp_ndt_6 = __VERIFIER_nondet_int() [L564] COND FALSE, EXPR !(\read(tmp_ndt_6)) [L561-L572] { int tmp_ndt_6; tmp_ndt_6 = __VERIFIER_nondet_int(); if (tmp_ndt_6) { { t5_st = 1; transmit5(); } } else { } } End of lasso representation. - StatisticsResult: NonterminationArgumentStatistics Fixpoint - NonterminatingLassoResult [Line: 481]: Nonterminating execution Found a nonterminating execution for the following lasso shaped sequence of statements. Stem: [L25] int m_pc = 0; [L26] int t1_pc = 0; [L27] int t2_pc = 0; [L28] int t3_pc = 0; [L29] int t4_pc = 0; [L30] int t5_pc = 0; [L31] int m_st ; [L32] int t1_st ; [L33] int t2_st ; [L34] int t3_st ; [L35] int t4_st ; [L36] int t5_st ; [L37] int m_i ; [L38] int t1_i ; [L39] int t2_i ; [L40] int t3_i ; [L41] int t4_i ; [L42] int t5_i ; [L43] int M_E = 2; [L44] int T1_E = 2; [L45] int T2_E = 2; [L46] int T3_E = 2; [L47] int T4_E = 2; [L48] int T5_E = 2; [L49] int E_1 = 2; [L50] int E_2 = 2; [L51] int E_3 = 2; [L52] int E_4 = 2; [L53] int E_5 = 2; VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, m_i=0, m_pc=0, m_st=0, t1_i=0, t1_pc=0, t1_st=0, t2_i=0, t2_pc=0, t2_st=0, t3_i=0, t3_pc=0, t3_st=0, t4_i=0, t4_pc=0, t4_st=0, t5_i=0, t5_pc=0, t5_st=0] [L945] int __retres1 ; [L949] CALL init_model() [L856] m_i = 1 [L857] t1_i = 1 [L858] t2_i = 1 [L859] t3_i = 1 [L860] t4_i = 1 [L861] t5_i = 1 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0] [L949] RET init_model() [L950] CALL start_simulation() [L886] int kernel_st ; [L887] int tmp ; [L888] int tmp___0 ; [L892] kernel_st = 0 [L893] FCALL update_channels() [L894] CALL init_threads() [L401] COND TRUE m_i == 1 [L402] m_st = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0] [L406] COND TRUE t1_i == 1 [L407] t1_st = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0] [L411] COND TRUE t2_i == 1 [L412] t2_st = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0] [L416] COND TRUE t3_i == 1 [L417] t3_st = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0] [L421] COND TRUE t4_i == 1 [L422] t4_st = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0] [L426] COND TRUE t5_i == 1 [L427] t5_st = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0] [L894] RET init_threads() [L895] CALL fire_delta_events() [L586] COND FALSE !(M_E == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0] [L591] COND FALSE !(T1_E == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0] [L596] COND FALSE !(T2_E == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0] [L601] COND FALSE !(T3_E == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0] [L606] COND FALSE !(T4_E == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0] [L611] COND FALSE !(T5_E == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0] [L616] COND FALSE !(E_1 == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0] [L621] COND FALSE !(E_2 == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0] [L626] COND FALSE !(E_3 == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0] [L631] COND FALSE !(E_4 == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0] [L636] COND FALSE !(E_5 == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0] [L895] RET fire_delta_events() [L896] CALL activate_threads() [L709] int tmp ; [L710] int tmp___0 ; [L711] int tmp___1 ; [L712] int tmp___2 ; [L713] int tmp___3 ; [L714] int tmp___4 ; [L718] CALL, EXPR is_master_triggered() [L276] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0] [L279] COND FALSE !(m_pc == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0] [L289] __retres1 = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, __retres1=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0] [L291] return (__retres1); VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, \result=0, __retres1=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0] [L718] RET, EXPR is_master_triggered() [L718] tmp = is_master_triggered() [L720] COND FALSE !(\read(tmp)) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, tmp=0] [L726] CALL, EXPR is_transmit1_triggered() [L295] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0] [L298] COND FALSE !(t1_pc == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0] [L308] __retres1 = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, __retres1=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0] [L310] return (__retres1); VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, \result=0, __retres1=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0] [L726] RET, EXPR is_transmit1_triggered() [L726] tmp___0 = is_transmit1_triggered() [L728] COND FALSE !(\read(tmp___0)) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, tmp=0, tmp___0=0] [L734] CALL, EXPR is_transmit2_triggered() [L314] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0] [L317] COND FALSE !(t2_pc == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0] [L327] __retres1 = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, __retres1=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0] [L329] return (__retres1); VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, \result=0, __retres1=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0] [L734] RET, EXPR is_transmit2_triggered() [L734] tmp___1 = is_transmit2_triggered() [L736] COND FALSE !(\read(tmp___1)) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, tmp=0, tmp___0=0, tmp___1=0] [L742] CALL, EXPR is_transmit3_triggered() [L333] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0] [L336] COND FALSE !(t3_pc == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0] [L346] __retres1 = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, __retres1=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0] [L348] return (__retres1); VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, \result=0, __retres1=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0] [L742] RET, EXPR is_transmit3_triggered() [L742] tmp___2 = is_transmit3_triggered() [L744] COND FALSE !(\read(tmp___2)) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, tmp=0, tmp___0=0, tmp___1=0, tmp___2=0] [L750] CALL, EXPR is_transmit4_triggered() [L352] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0] [L355] COND FALSE !(t4_pc == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0] [L365] __retres1 = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, __retres1=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0] [L367] return (__retres1); VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, \result=0, __retres1=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0] [L750] RET, EXPR is_transmit4_triggered() [L750] tmp___3 = is_transmit4_triggered() [L752] COND FALSE !(\read(tmp___3)) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, tmp=0, tmp___0=0, tmp___1=0, tmp___2=0, tmp___3=0] [L758] CALL, EXPR is_transmit5_triggered() [L371] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0] [L374] COND FALSE !(t5_pc == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0] [L384] __retres1 = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, __retres1=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0] [L386] return (__retres1); VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, \result=0, __retres1=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0] [L758] RET, EXPR is_transmit5_triggered() [L758] tmp___4 = is_transmit5_triggered() [L760] COND FALSE !(\read(tmp___4)) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, tmp=0, tmp___0=0, tmp___1=0, tmp___2=0, tmp___3=0, tmp___4=0] [L896] RET activate_threads() [L897] CALL reset_delta_events() [L649] COND FALSE !(M_E == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0] [L654] COND FALSE !(T1_E == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0] [L659] COND FALSE !(T2_E == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0] [L664] COND FALSE !(T3_E == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0] [L669] COND FALSE !(T4_E == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0] [L674] COND FALSE !(T5_E == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0] [L679] COND FALSE !(E_1 == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0] [L684] COND FALSE !(E_2 == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0] [L689] COND FALSE !(E_3 == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0] [L694] COND FALSE !(E_4 == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0] [L699] COND FALSE !(E_5 == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0] [L897] RET reset_delta_events() [L900] COND TRUE 1 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, kernel_st=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0] [L903] kernel_st = 1 [L904] CALL eval() [L477] int tmp ; VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0] Loop: [L481] COND TRUE 1 [L484] CALL, EXPR exists_runnable_thread() [L436] int __retres1 ; [L439] COND TRUE m_st == 0 [L440] __retres1 = 1 [L472] return (__retres1); [L484] RET, EXPR exists_runnable_thread() [L484] tmp = exists_runnable_thread() [L486] COND TRUE \read(tmp) [L491] COND TRUE m_st == 0 [L492] int tmp_ndt_1; [L493] EXPR tmp_ndt_1 = __VERIFIER_nondet_int() [L494] COND FALSE, EXPR !(\read(tmp_ndt_1)) [L491-L502] { int tmp_ndt_1; tmp_ndt_1 = __VERIFIER_nondet_int(); if (tmp_ndt_1) { { m_st = 1; master(); } } else { } } [L505] COND TRUE t1_st == 0 [L506] int tmp_ndt_2; [L507] EXPR tmp_ndt_2 = __VERIFIER_nondet_int() [L508] COND FALSE, EXPR !(\read(tmp_ndt_2)) [L505-L516] { int tmp_ndt_2; tmp_ndt_2 = __VERIFIER_nondet_int(); if (tmp_ndt_2) { { t1_st = 1; transmit1(); } } else { } } [L519] COND TRUE t2_st == 0 [L520] int tmp_ndt_3; [L521] EXPR tmp_ndt_3 = __VERIFIER_nondet_int() [L522] COND FALSE, EXPR !(\read(tmp_ndt_3)) [L519-L530] { int tmp_ndt_3; tmp_ndt_3 = __VERIFIER_nondet_int(); if (tmp_ndt_3) { { t2_st = 1; transmit2(); } } else { } } [L533] COND TRUE t3_st == 0 [L534] int tmp_ndt_4; [L535] EXPR tmp_ndt_4 = __VERIFIER_nondet_int() [L536] COND FALSE, EXPR !(\read(tmp_ndt_4)) [L533-L544] { int tmp_ndt_4; tmp_ndt_4 = __VERIFIER_nondet_int(); if (tmp_ndt_4) { { t3_st = 1; transmit3(); } } else { } } [L547] COND TRUE t4_st == 0 [L548] int tmp_ndt_5; [L549] EXPR tmp_ndt_5 = __VERIFIER_nondet_int() [L550] COND FALSE, EXPR !(\read(tmp_ndt_5)) [L547-L558] { int tmp_ndt_5; tmp_ndt_5 = __VERIFIER_nondet_int(); if (tmp_ndt_5) { { t4_st = 1; transmit4(); } } else { } } [L561] COND TRUE t5_st == 0 [L562] int tmp_ndt_6; [L563] EXPR tmp_ndt_6 = __VERIFIER_nondet_int() [L564] COND FALSE, EXPR !(\read(tmp_ndt_6)) [L561-L572] { int tmp_ndt_6; tmp_ndt_6 = __VERIFIER_nondet_int(); if (tmp_ndt_6) { { t5_st = 1; transmit5(); } } else { } } End of lasso representation. RESULT: Ultimate proved your program to be incorrect! [2023-11-06 22:26:34,241 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_0e04129a-54f6-4cb3-8369-3da3b1f77b7c/bin/uautomizer-verify-WvqO1wxjHP/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (1)] Forceful destruction successful, exit code 0 Received shutdown request... --- End real Ultimate output --- Execution finished normally Writing output log to file Ultimate.log Writing human readable error path to file UltimateCounterExample.errorpath Result: FALSE(TERM)