./Ultimate.py --spec ../../sv-benchmarks/c/properties/termination.prp --file ../../sv-benchmarks/c/systemc/transmitter.06.cil.c --full-output --architecture 32bit -------------------------------------------------------------------------------- Checking for termination Using default analysis Version e7bb482b Calling Ultimate with: /usr/lib/jvm/java-1.11.0-openjdk-amd64/bin/java -Dosgi.configuration.area=/tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_13dea121-f3fd-4f40-8510-ef12d3d88dee/bin/uautomizer-verify-WvqO1wxjHP/data/config -Xmx15G -Xms4m -jar /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_13dea121-f3fd-4f40-8510-ef12d3d88dee/bin/uautomizer-verify-WvqO1wxjHP/plugins/org.eclipse.equinox.launcher_1.5.800.v20200727-1323.jar -data @noDefault -ultimatedata /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_13dea121-f3fd-4f40-8510-ef12d3d88dee/bin/uautomizer-verify-WvqO1wxjHP/data -tc /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_13dea121-f3fd-4f40-8510-ef12d3d88dee/bin/uautomizer-verify-WvqO1wxjHP/config/AutomizerTermination.xml -i ../../sv-benchmarks/c/systemc/transmitter.06.cil.c -s /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_13dea121-f3fd-4f40-8510-ef12d3d88dee/bin/uautomizer-verify-WvqO1wxjHP/config/svcomp-Termination-32bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_13dea121-f3fd-4f40-8510-ef12d3d88dee/bin/uautomizer-verify-WvqO1wxjHP --witnessprinter.witness.filename witness.graphml --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(F end) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 32bit --witnessprinter.graph.data.programhash bbfdf3f22061e77485b28b33d06a9820d2c4b7aa22afc378a1743c2d746b69df --- Real Ultimate output --- This is Ultimate 0.2.3-dev-e7bb482 [2023-11-06 22:07:59,887 INFO L188 SettingsManager]: Resetting all preferences to default values... [2023-11-06 22:07:59,956 INFO L114 SettingsManager]: Loading settings from /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_13dea121-f3fd-4f40-8510-ef12d3d88dee/bin/uautomizer-verify-WvqO1wxjHP/config/svcomp-Termination-32bit-Automizer_Default.epf [2023-11-06 22:07:59,962 WARN L101 SettingsManager]: Preference file contains the following unknown settings: [2023-11-06 22:07:59,962 WARN L103 SettingsManager]: * de.uni_freiburg.informatik.ultimate.core.Log level for class [2023-11-06 22:07:59,999 INFO L130 SettingsManager]: Preferences different from defaults after loading the file: [2023-11-06 22:08:00,001 INFO L151 SettingsManager]: Preferences of UltimateCore differ from their defaults: [2023-11-06 22:08:00,002 INFO L153 SettingsManager]: * Log level for class=de.uni_freiburg.informatik.ultimate.lib.smtlibutils.quantifier.QuantifierPusher=ERROR; [2023-11-06 22:08:00,004 INFO L151 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2023-11-06 22:08:00,008 INFO L153 SettingsManager]: * Create parallel compositions if possible=false [2023-11-06 22:08:00,010 INFO L153 SettingsManager]: * Use SBE=true [2023-11-06 22:08:00,010 INFO L151 SettingsManager]: Preferences of BuchiAutomizer differ from their defaults: [2023-11-06 22:08:00,011 INFO L153 SettingsManager]: * NCSB implementation=INTSET_LAZY3 [2023-11-06 22:08:00,012 INFO L153 SettingsManager]: * Use old map elimination=false [2023-11-06 22:08:00,013 INFO L153 SettingsManager]: * Use external solver (rank synthesis)=false [2023-11-06 22:08:00,013 INFO L153 SettingsManager]: * Use only trivial implications for array writes=true [2023-11-06 22:08:00,013 INFO L153 SettingsManager]: * Rank analysis=LINEAR_WITH_GUESSES [2023-11-06 22:08:00,014 INFO L151 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2023-11-06 22:08:00,015 INFO L153 SettingsManager]: * Pointer base address is valid at dereference=ASSUME [2023-11-06 22:08:00,015 INFO L153 SettingsManager]: * sizeof long=4 [2023-11-06 22:08:00,017 INFO L153 SettingsManager]: * Overapproximate operations on floating types=true [2023-11-06 22:08:00,020 INFO L153 SettingsManager]: * sizeof POINTER=4 [2023-11-06 22:08:00,021 INFO L153 SettingsManager]: * Check division by zero=IGNORE [2023-11-06 22:08:00,021 INFO L153 SettingsManager]: * Pointer to allocated memory at dereference=ASSUME [2023-11-06 22:08:00,021 INFO L153 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=ASSUME [2023-11-06 22:08:00,022 INFO L153 SettingsManager]: * Check array bounds for arrays that are off heap=ASSUME [2023-11-06 22:08:00,022 INFO L153 SettingsManager]: * Check unreachability of reach_error function=false [2023-11-06 22:08:00,023 INFO L153 SettingsManager]: * sizeof long double=12 [2023-11-06 22:08:00,023 INFO L153 SettingsManager]: * Check if freed pointer was valid=false [2023-11-06 22:08:00,023 INFO L153 SettingsManager]: * Assume nondeterminstic values are in range=false [2023-11-06 22:08:00,025 INFO L153 SettingsManager]: * Use constant arrays=true [2023-11-06 22:08:00,025 INFO L151 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2023-11-06 22:08:00,025 INFO L153 SettingsManager]: * Size of a code block=SequenceOfStatements [2023-11-06 22:08:00,025 INFO L151 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2023-11-06 22:08:00,026 INFO L153 SettingsManager]: * Trace refinement strategy=CAMEL [2023-11-06 22:08:00,026 INFO L151 SettingsManager]: Preferences of IcfgTransformer differ from their defaults: [2023-11-06 22:08:00,026 INFO L153 SettingsManager]: * TransformationType=MODULO_NEIGHBOR WARNING: An illegal reflective access operation has occurred WARNING: Illegal reflective access by com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 (file:/tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_13dea121-f3fd-4f40-8510-ef12d3d88dee/bin/uautomizer-verify-WvqO1wxjHP/plugins/com.sun.xml.bind_2.2.0.v201505121915.jar) to method java.lang.ClassLoader.defineClass(java.lang.String,byte[],int,int) WARNING: Please consider reporting this to the maintainers of com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 WARNING: Use --illegal-access=warn to enable warnings of further illegal reflective access operations WARNING: All illegal access operations will be denied in a future release Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_13dea121-f3fd-4f40-8510-ef12d3d88dee/bin/uautomizer-verify-WvqO1wxjHP Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness.graphml Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(F end) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 32bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> bbfdf3f22061e77485b28b33d06a9820d2c4b7aa22afc378a1743c2d746b69df [2023-11-06 22:08:00,320 INFO L75 nceAwareModelManager]: Repository-Root is: /tmp [2023-11-06 22:08:00,340 INFO L261 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2023-11-06 22:08:00,345 INFO L217 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2023-11-06 22:08:00,347 INFO L270 PluginConnector]: Initializing CDTParser... [2023-11-06 22:08:00,348 INFO L274 PluginConnector]: CDTParser initialized [2023-11-06 22:08:00,349 INFO L431 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_13dea121-f3fd-4f40-8510-ef12d3d88dee/bin/uautomizer-verify-WvqO1wxjHP/../../sv-benchmarks/c/systemc/transmitter.06.cil.c [2023-11-06 22:08:03,510 INFO L533 CDTParser]: Created temporary CDT project at NULL [2023-11-06 22:08:03,734 INFO L384 CDTParser]: Found 1 translation units. [2023-11-06 22:08:03,734 INFO L180 CDTParser]: Scanning /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_13dea121-f3fd-4f40-8510-ef12d3d88dee/sv-benchmarks/c/systemc/transmitter.06.cil.c [2023-11-06 22:08:03,749 INFO L427 CDTParser]: About to delete temporary CDT project at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_13dea121-f3fd-4f40-8510-ef12d3d88dee/bin/uautomizer-verify-WvqO1wxjHP/data/39b30dcbb/7b665bc97ebf4ef4afa750fbaf19bb7f/FLAGcaba851a7 [2023-11-06 22:08:03,764 INFO L435 CDTParser]: Successfully deleted /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_13dea121-f3fd-4f40-8510-ef12d3d88dee/bin/uautomizer-verify-WvqO1wxjHP/data/39b30dcbb/7b665bc97ebf4ef4afa750fbaf19bb7f [2023-11-06 22:08:03,767 INFO L299 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2023-11-06 22:08:03,769 INFO L133 ToolchainWalker]: Walking toolchain with 6 elements. [2023-11-06 22:08:03,770 INFO L112 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2023-11-06 22:08:03,771 INFO L270 PluginConnector]: Initializing CACSL2BoogieTranslator... [2023-11-06 22:08:03,780 INFO L274 PluginConnector]: CACSL2BoogieTranslator initialized [2023-11-06 22:08:03,781 INFO L184 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 06.11 10:08:03" (1/1) ... [2023-11-06 22:08:03,782 INFO L204 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@45458abd and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.11 10:08:03, skipping insertion in model container [2023-11-06 22:08:03,782 INFO L184 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 06.11 10:08:03" (1/1) ... [2023-11-06 22:08:03,829 INFO L177 MainTranslator]: Built tables and reachable declarations [2023-11-06 22:08:04,071 INFO L209 PostProcessor]: Analyzing one entry point: main [2023-11-06 22:08:04,091 INFO L202 MainTranslator]: Completed pre-run [2023-11-06 22:08:04,149 INFO L209 PostProcessor]: Analyzing one entry point: main [2023-11-06 22:08:04,170 INFO L206 MainTranslator]: Completed translation [2023-11-06 22:08:04,170 INFO L201 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.11 10:08:04 WrapperNode [2023-11-06 22:08:04,170 INFO L131 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2023-11-06 22:08:04,172 INFO L112 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2023-11-06 22:08:04,172 INFO L270 PluginConnector]: Initializing Boogie Procedure Inliner... [2023-11-06 22:08:04,172 INFO L274 PluginConnector]: Boogie Procedure Inliner initialized [2023-11-06 22:08:04,180 INFO L184 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.11 10:08:04" (1/1) ... [2023-11-06 22:08:04,191 INFO L184 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.11 10:08:04" (1/1) ... [2023-11-06 22:08:04,284 INFO L138 Inliner]: procedures = 40, calls = 49, calls flagged for inlining = 44, calls inlined = 105, statements flattened = 1536 [2023-11-06 22:08:04,284 INFO L131 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2023-11-06 22:08:04,285 INFO L112 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2023-11-06 22:08:04,285 INFO L270 PluginConnector]: Initializing Boogie Preprocessor... [2023-11-06 22:08:04,285 INFO L274 PluginConnector]: Boogie Preprocessor initialized [2023-11-06 22:08:04,294 INFO L184 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.11 10:08:04" (1/1) ... [2023-11-06 22:08:04,294 INFO L184 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.11 10:08:04" (1/1) ... [2023-11-06 22:08:04,307 INFO L184 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.11 10:08:04" (1/1) ... [2023-11-06 22:08:04,307 INFO L184 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.11 10:08:04" (1/1) ... [2023-11-06 22:08:04,334 INFO L184 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.11 10:08:04" (1/1) ... [2023-11-06 22:08:04,353 INFO L184 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.11 10:08:04" (1/1) ... [2023-11-06 22:08:04,358 INFO L184 PluginConnector]: Executing the observer LTLStepAnnotator from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.11 10:08:04" (1/1) ... [2023-11-06 22:08:04,364 INFO L184 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.11 10:08:04" (1/1) ... [2023-11-06 22:08:04,373 INFO L131 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2023-11-06 22:08:04,374 INFO L112 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2023-11-06 22:08:04,374 INFO L270 PluginConnector]: Initializing RCFGBuilder... [2023-11-06 22:08:04,374 INFO L274 PluginConnector]: RCFGBuilder initialized [2023-11-06 22:08:04,375 INFO L184 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.11 10:08:04" (1/1) ... [2023-11-06 22:08:04,383 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2023-11-06 22:08:04,393 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_13dea121-f3fd-4f40-8510-ef12d3d88dee/bin/uautomizer-verify-WvqO1wxjHP/z3 [2023-11-06 22:08:04,410 INFO L229 MonitoredProcess]: Starting monitored process 1 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_13dea121-f3fd-4f40-8510-ef12d3d88dee/bin/uautomizer-verify-WvqO1wxjHP/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2023-11-06 22:08:04,425 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_13dea121-f3fd-4f40-8510-ef12d3d88dee/bin/uautomizer-verify-WvqO1wxjHP/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (1)] Waiting until timeout for monitored process [2023-11-06 22:08:04,452 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocInit [2023-11-06 22:08:04,453 INFO L130 BoogieDeclarations]: Found specification of procedure write~init~int [2023-11-06 22:08:04,453 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2023-11-06 22:08:04,453 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2023-11-06 22:08:04,602 INFO L236 CfgBuilder]: Building ICFG [2023-11-06 22:08:04,604 INFO L262 CfgBuilder]: Building CFG for each procedure with an implementation [2023-11-06 22:08:05,803 INFO L277 CfgBuilder]: Performing block encoding [2023-11-06 22:08:05,834 INFO L297 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2023-11-06 22:08:05,834 INFO L302 CfgBuilder]: Removed 10 assume(true) statements. [2023-11-06 22:08:05,840 INFO L201 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 06.11 10:08:05 BoogieIcfgContainer [2023-11-06 22:08:05,840 INFO L131 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2023-11-06 22:08:05,842 INFO L112 PluginConnector]: ------------------------BuchiAutomizer---------------------------- [2023-11-06 22:08:05,843 INFO L270 PluginConnector]: Initializing BuchiAutomizer... [2023-11-06 22:08:05,847 INFO L274 PluginConnector]: BuchiAutomizer initialized [2023-11-06 22:08:05,848 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2023-11-06 22:08:05,848 INFO L184 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "CDTParser AST 06.11 10:08:03" (1/3) ... [2023-11-06 22:08:05,850 INFO L204 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@f06f6f1 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 06.11 10:08:05, skipping insertion in model container [2023-11-06 22:08:05,850 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2023-11-06 22:08:05,850 INFO L184 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.11 10:08:04" (2/3) ... [2023-11-06 22:08:05,852 INFO L204 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@f06f6f1 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 06.11 10:08:05, skipping insertion in model container [2023-11-06 22:08:05,853 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2023-11-06 22:08:05,853 INFO L184 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 06.11 10:08:05" (3/3) ... [2023-11-06 22:08:05,884 INFO L332 chiAutomizerObserver]: Analyzing ICFG transmitter.06.cil.c [2023-11-06 22:08:05,956 INFO L303 stractBuchiCegarLoop]: Interprodecural is true [2023-11-06 22:08:05,957 INFO L304 stractBuchiCegarLoop]: Hoare is false [2023-11-06 22:08:05,957 INFO L305 stractBuchiCegarLoop]: Compute interpolants for ForwardPredicates [2023-11-06 22:08:05,957 INFO L306 stractBuchiCegarLoop]: Backedges is STRAIGHT_LINE [2023-11-06 22:08:05,957 INFO L307 stractBuchiCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2023-11-06 22:08:05,957 INFO L308 stractBuchiCegarLoop]: Difference is false [2023-11-06 22:08:05,958 INFO L309 stractBuchiCegarLoop]: Minimize is MINIMIZE_SEVPA [2023-11-06 22:08:05,958 INFO L313 stractBuchiCegarLoop]: ======== Iteration 0 == of CEGAR loop == BuchiAutomatonCegarLoop ======== [2023-11-06 22:08:05,967 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 641 states, 640 states have (on average 1.521875) internal successors, (974), 640 states have internal predecessors, (974), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-06 22:08:06,034 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 548 [2023-11-06 22:08:06,034 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-06 22:08:06,034 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-06 22:08:06,047 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-06 22:08:06,047 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-06 22:08:06,047 INFO L335 stractBuchiCegarLoop]: ======== Iteration 1 ============ [2023-11-06 22:08:06,049 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 641 states, 640 states have (on average 1.521875) internal successors, (974), 640 states have internal predecessors, (974), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-06 22:08:06,063 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 548 [2023-11-06 22:08:06,064 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-06 22:08:06,064 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-06 22:08:06,068 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-06 22:08:06,068 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-06 22:08:06,077 INFO L748 eck$LassoCheckResult]: Stem: 183#$Ultimate##0true assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2; 525#L-1true assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~8#1;havoc main_~__retres1~8#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 291#init_model_returnLabel#1true assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret20#1, start_simulation_#t~ret21#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 521#update_channels_returnLabel#1true assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 2#L461true assume !(1 == ~m_i~0);~m_st~0 := 2; 350#L461-2true assume 1 == ~t1_i~0;~t1_st~0 := 0; 565#L466-1true assume !(1 == ~t2_i~0);~t2_st~0 := 2; 617#L471-1true assume !(1 == ~t3_i~0);~t3_st~0 := 2; 43#L476-1true assume !(1 == ~t4_i~0);~t4_st~0 := 2; 277#L481-1true assume !(1 == ~t5_i~0);~t5_st~0 := 2; 136#L486-1true assume !(1 == ~t6_i~0);~t6_st~0 := 2; 51#L491-1true assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 536#L670true assume !(0 == ~M_E~0); 306#L670-2true assume !(0 == ~T1_E~0); 255#L675-1true assume !(0 == ~T2_E~0); 349#L680-1true assume !(0 == ~T3_E~0); 445#L685-1true assume !(0 == ~T4_E~0); 313#L690-1true assume !(0 == ~T5_E~0); 616#L695-1true assume !(0 == ~T6_E~0); 395#L700-1true assume 0 == ~E_1~0;~E_1~0 := 1; 382#L705-1true assume !(0 == ~E_2~0); 557#L710-1true assume !(0 == ~E_3~0); 253#L715-1true assume !(0 == ~E_4~0); 199#L720-1true assume !(0 == ~E_5~0); 240#L725-1true assume !(0 == ~E_6~0); 281#L730-1true assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 415#L320true assume 1 == ~m_pc~0; 229#L321true assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 162#L331true is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 158#is_master_triggered_returnLabel#1true activate_threads_#t~ret12#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 137#L825true assume !(0 != activate_threads_~tmp~1#1); 460#L825-2true assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 140#L339true assume !(1 == ~t1_pc~0); 432#L339-2true is_transmit1_triggered_~__retres1~1#1 := 0; 122#L350true is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 42#is_transmit1_triggered_returnLabel#1true activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 54#L833true assume !(0 != activate_threads_~tmp___0~0#1); 550#L833-2true assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 13#L358true assume 1 == ~t2_pc~0; 595#L359true assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 519#L369true is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 293#is_transmit2_triggered_returnLabel#1true activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 243#L841true assume !(0 != activate_threads_~tmp___1~0#1); 134#L841-2true assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 465#L377true assume !(1 == ~t3_pc~0); 330#L377-2true is_transmit3_triggered_~__retres1~3#1 := 0; 341#L388true is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 11#is_transmit3_triggered_returnLabel#1true activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 139#L849true assume !(0 != activate_threads_~tmp___2~0#1); 346#L849-2true assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 96#L396true assume 1 == ~t4_pc~0; 457#L397true assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 14#L407true is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 87#is_transmit4_triggered_returnLabel#1true activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 268#L857true assume !(0 != activate_threads_~tmp___3~0#1); 79#L857-2true assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 125#L415true assume 1 == ~t5_pc~0; 334#L416true assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 282#L426true is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 164#is_transmit5_triggered_returnLabel#1true activate_threads_#t~ret17#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 435#L865true assume !(0 != activate_threads_~tmp___4~0#1); 32#L865-2true assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 331#L434true assume !(1 == ~t6_pc~0); 220#L434-2true is_transmit6_triggered_~__retres1~6#1 := 0; 361#L445true is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 286#is_transmit6_triggered_returnLabel#1true activate_threads_#t~ret18#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 362#L873true assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 146#L873-2true havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 548#L743true assume !(1 == ~M_E~0); 73#L743-2true assume !(1 == ~T1_E~0); 496#L748-1true assume !(1 == ~T2_E~0); 274#L753-1true assume !(1 == ~T3_E~0); 399#L758-1true assume 1 == ~T4_E~0;~T4_E~0 := 2; 472#L763-1true assume !(1 == ~T5_E~0); 561#L768-1true assume !(1 == ~T6_E~0); 143#L773-1true assume !(1 == ~E_1~0); 629#L778-1true assume !(1 == ~E_2~0); 131#L783-1true assume !(1 == ~E_3~0); 605#L788-1true assume !(1 == ~E_4~0); 347#L793-1true assume !(1 == ~E_5~0); 300#L798-1true assume 1 == ~E_6~0;~E_6~0 := 2; 63#L803-1true assume { :end_inline_reset_delta_events } true; 246#L1024-2true [2023-11-06 22:08:06,080 INFO L750 eck$LassoCheckResult]: Loop: 246#L1024-2true assume !false; 483#L1025true start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 128#L645-1true assume !true; 91#eval_returnLabel#1true havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 447#update_channels_returnLabel#2true assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 58#L670-3true assume 0 == ~M_E~0;~M_E~0 := 1; 235#L670-5true assume 0 == ~T1_E~0;~T1_E~0 := 1; 159#L675-3true assume 0 == ~T2_E~0;~T2_E~0 := 1; 438#L680-3true assume 0 == ~T3_E~0;~T3_E~0 := 1; 344#L685-3true assume 0 == ~T4_E~0;~T4_E~0 := 1; 611#L690-3true assume 0 == ~T5_E~0;~T5_E~0 := 1; 567#L695-3true assume !(0 == ~T6_E~0); 355#L700-3true assume 0 == ~E_1~0;~E_1~0 := 1; 638#L705-3true assume 0 == ~E_2~0;~E_2~0 := 1; 86#L710-3true assume 0 == ~E_3~0;~E_3~0 := 1; 390#L715-3true assume 0 == ~E_4~0;~E_4~0 := 1; 244#L720-3true assume 0 == ~E_5~0;~E_5~0 := 1; 314#L725-3true assume 0 == ~E_6~0;~E_6~0 := 1; 506#L730-3true assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 144#L320-21true assume 1 == ~m_pc~0; 470#L321-7true assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 543#L331-7true is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 112#is_master_triggered_returnLabel#8true activate_threads_#t~ret12#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 486#L825-21true assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 454#L825-23true assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 94#L339-21true assume 1 == ~t1_pc~0; 169#L340-7true assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 626#L350-7true is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 77#is_transmit1_triggered_returnLabel#8true activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 24#L833-21true assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 70#L833-23true assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 587#L358-21true assume !(1 == ~t2_pc~0); 100#L358-23true is_transmit2_triggered_~__retres1~2#1 := 0; 64#L369-7true is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 198#is_transmit2_triggered_returnLabel#8true activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 405#L841-21true assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 80#L841-23true assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 477#L377-21true assume 1 == ~t3_pc~0; 570#L378-7true assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 267#L388-7true is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 542#is_transmit3_triggered_returnLabel#8true activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 288#L849-21true assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 178#L849-23true assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 301#L396-21true assume !(1 == ~t4_pc~0); 190#L396-23true is_transmit4_triggered_~__retres1~4#1 := 0; 230#L407-7true is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 499#is_transmit4_triggered_returnLabel#8true activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 16#L857-21true assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 303#L857-23true assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 160#L415-21true assume 1 == ~t5_pc~0; 516#L416-7true assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 437#L426-7true is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 272#is_transmit5_triggered_returnLabel#8true activate_threads_#t~ret17#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 225#L865-21true assume !(0 != activate_threads_~tmp___4~0#1); 202#L865-23true assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 383#L434-21true assume !(1 == ~t6_pc~0); 28#L434-23true is_transmit6_triggered_~__retres1~6#1 := 0; 431#L445-7true is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 252#is_transmit6_triggered_returnLabel#8true activate_threads_#t~ret18#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 155#L873-21true assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 260#L873-23true havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 151#L743-3true assume 1 == ~M_E~0;~M_E~0 := 2; 502#L743-5true assume 1 == ~T1_E~0;~T1_E~0 := 2; 564#L748-3true assume 1 == ~T2_E~0;~T2_E~0 := 2; 261#L753-3true assume !(1 == ~T3_E~0); 214#L758-3true assume 1 == ~T4_E~0;~T4_E~0 := 2; 172#L763-3true assume 1 == ~T5_E~0;~T5_E~0 := 2; 533#L768-3true assume 1 == ~T6_E~0;~T6_E~0 := 2; 478#L773-3true assume 1 == ~E_1~0;~E_1~0 := 2; 110#L778-3true assume 1 == ~E_2~0;~E_2~0 := 2; 265#L783-3true assume 1 == ~E_3~0;~E_3~0 := 2; 580#L788-3true assume 1 == ~E_4~0;~E_4~0 := 2; 528#L793-3true assume !(1 == ~E_5~0); 541#L798-3true assume 1 == ~E_6~0;~E_6~0 := 2; 304#L803-3true assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 104#L504-1true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 401#L541-1true exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 264#exists_runnable_thread_returnLabel#2true start_simulation_#t~ret20#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret20#1;havoc start_simulation_#t~ret20#1; 448#L1043true assume !(0 == start_simulation_~tmp~3#1); 443#L1043-2true assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret19#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 262#L504-2true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 333#L541-2true exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 41#exists_runnable_thread_returnLabel#3true stop_simulation_#t~ret19#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret19#1;havoc stop_simulation_#t~ret19#1; 234#L998true assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 57#L1005true stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 466#stop_simulation_returnLabel#1true start_simulation_#t~ret21#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret19#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret21#1;havoc start_simulation_#t~ret21#1; 224#L1056true assume !(0 != start_simulation_~tmp___0~1#1); 246#L1024-2true [2023-11-06 22:08:06,086 INFO L145 PredicateUnifier]: Initialized classic predicate unifier [2023-11-06 22:08:06,087 INFO L85 PathProgramCache]: Analyzing trace with hash -1010496615, now seen corresponding path program 1 times [2023-11-06 22:08:06,097 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-06 22:08:06,097 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [427633616] [2023-11-06 22:08:06,098 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-06 22:08:06,098 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-06 22:08:06,199 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-06 22:08:06,348 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-06 22:08:06,349 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-06 22:08:06,349 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [427633616] [2023-11-06 22:08:06,350 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [427633616] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-06 22:08:06,351 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-06 22:08:06,351 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-06 22:08:06,353 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [620301817] [2023-11-06 22:08:06,353 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-06 22:08:06,358 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-06 22:08:06,361 INFO L145 PredicateUnifier]: Initialized classic predicate unifier [2023-11-06 22:08:06,362 INFO L85 PathProgramCache]: Analyzing trace with hash -1655056166, now seen corresponding path program 1 times [2023-11-06 22:08:06,362 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-06 22:08:06,362 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [117269265] [2023-11-06 22:08:06,363 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-06 22:08:06,363 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-06 22:08:06,395 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-06 22:08:06,465 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-06 22:08:06,466 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-06 22:08:06,466 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [117269265] [2023-11-06 22:08:06,466 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [117269265] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-06 22:08:06,466 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-06 22:08:06,466 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2023-11-06 22:08:06,467 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1527104801] [2023-11-06 22:08:06,467 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-06 22:08:06,468 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-06 22:08:06,469 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-06 22:08:06,505 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-06 22:08:06,505 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-06 22:08:06,508 INFO L87 Difference]: Start difference. First operand has 641 states, 640 states have (on average 1.521875) internal successors, (974), 640 states have internal predecessors, (974), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand has 3 states, 3 states have (on average 27.333333333333332) internal successors, (82), 3 states have internal predecessors, (82), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-06 22:08:06,580 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-06 22:08:06,580 INFO L93 Difference]: Finished difference Result 639 states and 950 transitions. [2023-11-06 22:08:06,582 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 639 states and 950 transitions. [2023-11-06 22:08:06,590 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 544 [2023-11-06 22:08:06,603 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 639 states to 633 states and 944 transitions. [2023-11-06 22:08:06,604 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 633 [2023-11-06 22:08:06,606 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 633 [2023-11-06 22:08:06,607 INFO L73 IsDeterministic]: Start isDeterministic. Operand 633 states and 944 transitions. [2023-11-06 22:08:06,613 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-06 22:08:06,614 INFO L218 hiAutomatonCegarLoop]: Abstraction has 633 states and 944 transitions. [2023-11-06 22:08:06,634 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 633 states and 944 transitions. [2023-11-06 22:08:06,673 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 633 to 633. [2023-11-06 22:08:06,675 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 633 states, 633 states have (on average 1.4913112164296998) internal successors, (944), 632 states have internal predecessors, (944), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-06 22:08:06,679 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 633 states to 633 states and 944 transitions. [2023-11-06 22:08:06,680 INFO L240 hiAutomatonCegarLoop]: Abstraction has 633 states and 944 transitions. [2023-11-06 22:08:06,681 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-06 22:08:06,685 INFO L428 stractBuchiCegarLoop]: Abstraction has 633 states and 944 transitions. [2023-11-06 22:08:06,685 INFO L335 stractBuchiCegarLoop]: ======== Iteration 2 ============ [2023-11-06 22:08:06,685 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 633 states and 944 transitions. [2023-11-06 22:08:06,690 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 544 [2023-11-06 22:08:06,690 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-06 22:08:06,690 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-06 22:08:06,693 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-06 22:08:06,694 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-06 22:08:06,694 INFO L748 eck$LassoCheckResult]: Stem: 1630#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2; 1631#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~8#1;havoc main_~__retres1~8#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 1760#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret20#1, start_simulation_#t~ret21#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 1761#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 1289#L461 assume 1 == ~m_i~0;~m_st~0 := 0; 1290#L461-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 1816#L466-1 assume !(1 == ~t2_i~0);~t2_st~0 := 2; 1914#L471-1 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 1387#L476-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 1388#L481-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 1552#L486-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 1401#L491-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 1402#L670 assume !(0 == ~M_E~0); 1772#L670-2 assume !(0 == ~T1_E~0); 1725#L675-1 assume !(0 == ~T2_E~0); 1726#L680-1 assume !(0 == ~T3_E~0); 1814#L685-1 assume !(0 == ~T4_E~0); 1779#L690-1 assume !(0 == ~T5_E~0); 1780#L695-1 assume !(0 == ~T6_E~0); 1851#L700-1 assume 0 == ~E_1~0;~E_1~0 := 1; 1840#L705-1 assume !(0 == ~E_2~0); 1841#L710-1 assume !(0 == ~E_3~0); 1724#L715-1 assume !(0 == ~E_4~0); 1656#L720-1 assume !(0 == ~E_5~0); 1657#L725-1 assume !(0 == ~E_6~0); 1704#L730-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1749#L320 assume 1 == ~m_pc~0; 1697#L321 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 1599#L331 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1593#is_master_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 1553#L825 assume !(0 != activate_threads_~tmp~1#1); 1554#L825-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1558#L339 assume !(1 == ~t1_pc~0); 1559#L339-2 is_transmit1_triggered_~__retres1~1#1 := 0; 1528#L350 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1383#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 1384#L833 assume !(0 != activate_threads_~tmp___0~0#1); 1406#L833-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1315#L358 assume 1 == ~t2_pc~0; 1316#L359 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 1833#L369 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1763#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 1707#L841 assume !(0 != activate_threads_~tmp___1~0#1); 1548#L841-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1549#L377 assume !(1 == ~t3_pc~0); 1798#L377-2 is_transmit3_triggered_~__retres1~3#1 := 0; 1799#L388 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1311#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 1312#L849 assume !(0 != activate_threads_~tmp___2~0#1); 1557#L849-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1483#L396 assume 1 == ~t4_pc~0; 1484#L397 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 1318#L407 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1319#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 1465#L857 assume !(0 != activate_threads_~tmp___3~0#1); 1450#L857-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1451#L415 assume 1 == ~t5_pc~0; 1533#L416 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 1588#L426 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1603#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 1604#L865 assume !(0 != activate_threads_~tmp___4~0#1); 1359#L865-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1360#L434 assume !(1 == ~t6_pc~0); 1685#L434-2 is_transmit6_triggered_~__retres1~6#1 := 0; 1686#L445 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1754#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1755#L873 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 1572#L873-2 havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1573#L743 assume !(1 == ~M_E~0); 1442#L743-2 assume !(1 == ~T1_E~0); 1443#L748-1 assume !(1 == ~T2_E~0); 1745#L753-1 assume !(1 == ~T3_E~0); 1746#L758-1 assume 1 == ~T4_E~0;~T4_E~0 := 2; 1854#L763-1 assume !(1 == ~T5_E~0); 1886#L768-1 assume !(1 == ~T6_E~0); 1567#L773-1 assume !(1 == ~E_1~0); 1568#L778-1 assume !(1 == ~E_2~0); 1543#L783-1 assume !(1 == ~E_3~0); 1544#L788-1 assume !(1 == ~E_4~0); 1812#L793-1 assume !(1 == ~E_5~0); 1768#L798-1 assume 1 == ~E_6~0;~E_6~0 := 2; 1423#L803-1 assume { :end_inline_reset_delta_events } true; 1424#L1024-2 [2023-11-06 22:08:06,695 INFO L750 eck$LassoCheckResult]: Loop: 1424#L1024-2 assume !false; 1712#L1025 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 1297#L645-1 assume !false; 1538#L552 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 1653#L504 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 1367#L541 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 1786#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 1787#L556 assume !(0 != eval_~tmp~0#1); 1474#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 1475#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 1417#L670-3 assume 0 == ~M_E~0;~M_E~0 := 1; 1418#L670-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 1596#L675-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 1597#L680-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 1809#L685-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 1810#L690-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 1915#L695-3 assume !(0 == ~T6_E~0); 1818#L700-3 assume 0 == ~E_1~0;~E_1~0 := 1; 1819#L705-3 assume 0 == ~E_2~0;~E_2~0 := 1; 1463#L710-3 assume 0 == ~E_3~0;~E_3~0 := 1; 1464#L715-3 assume 0 == ~E_4~0;~E_4~0 := 1; 1708#L720-3 assume 0 == ~E_5~0;~E_5~0 := 1; 1709#L725-3 assume 0 == ~E_6~0;~E_6~0 := 1; 1781#L730-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1569#L320-21 assume !(1 == ~m_pc~0); 1570#L320-23 is_master_triggered_~__retres1~0#1 := 0; 1706#L331-7 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1513#is_master_triggered_returnLabel#8 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 1514#L825-21 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 1876#L825-23 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1478#L339-21 assume 1 == ~t1_pc~0; 1479#L340-7 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 1609#L350-7 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1447#is_transmit1_triggered_returnLabel#8 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 1343#L833-21 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 1344#L833-23 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1440#L358-21 assume !(1 == ~t2_pc~0); 1492#L358-23 is_transmit2_triggered_~__retres1~2#1 := 0; 1425#L369-7 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1426#is_transmit2_triggered_returnLabel#8 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 1654#L841-21 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 1452#L841-23 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1453#L377-21 assume 1 == ~t3_pc~0; 1888#L378-7 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 1737#L388-7 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1738#is_transmit3_triggered_returnLabel#8 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 1756#L849-21 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 1620#L849-23 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1621#L396-21 assume !(1 == ~t4_pc~0); 1640#L396-23 is_transmit4_triggered_~__retres1~4#1 := 0; 1641#L407-7 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1696#is_transmit4_triggered_returnLabel#8 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 1325#L857-21 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 1326#L857-23 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1594#L415-21 assume 1 == ~t5_pc~0; 1595#L416-7 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 1566#L426-7 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1744#is_transmit5_triggered_returnLabel#8 activate_threads_#t~ret17#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 1690#L865-21 assume !(0 != activate_threads_~tmp___4~0#1); 1659#L865-23 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1660#L434-21 assume !(1 == ~t6_pc~0); 1348#L434-23 is_transmit6_triggered_~__retres1~6#1 := 0; 1349#L445-7 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1723#is_transmit6_triggered_returnLabel#8 activate_threads_#t~ret18#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1589#L873-21 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 1590#L873-23 havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1582#L743-3 assume 1 == ~M_E~0;~M_E~0 := 2; 1583#L743-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 1898#L748-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 1731#L753-3 assume !(1 == ~T3_E~0); 1675#L758-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 1611#L763-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 1612#L768-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 1889#L773-3 assume 1 == ~E_1~0;~E_1~0 := 2; 1507#L778-3 assume 1 == ~E_2~0;~E_2~0 := 2; 1508#L783-3 assume 1 == ~E_3~0;~E_3~0 := 2; 1736#L788-3 assume 1 == ~E_4~0;~E_4~0 := 2; 1906#L793-3 assume !(1 == ~E_5~0); 1907#L798-3 assume 1 == ~E_6~0;~E_6~0 := 2; 1771#L803-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 1498#L504-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 1395#L541-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 1734#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret20#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret20#1;havoc start_simulation_#t~ret20#1; 1735#L1043 assume !(0 == start_simulation_~tmp~3#1); 1869#L1043-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret19#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 1732#L504-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 1516#L541-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 1381#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret19#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret19#1;havoc stop_simulation_#t~ret19#1; 1382#L998 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 1411#L1005 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 1412#stop_simulation_returnLabel#1 start_simulation_#t~ret21#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret19#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret21#1;havoc start_simulation_#t~ret21#1; 1689#L1056 assume !(0 != start_simulation_~tmp___0~1#1); 1424#L1024-2 [2023-11-06 22:08:06,697 INFO L145 PredicateUnifier]: Initialized classic predicate unifier [2023-11-06 22:08:06,697 INFO L85 PathProgramCache]: Analyzing trace with hash -1849530277, now seen corresponding path program 1 times [2023-11-06 22:08:06,698 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-06 22:08:06,698 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1943095632] [2023-11-06 22:08:06,698 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-06 22:08:06,698 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-06 22:08:06,731 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-06 22:08:06,836 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-06 22:08:06,837 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-06 22:08:06,837 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1943095632] [2023-11-06 22:08:06,837 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1943095632] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-06 22:08:06,837 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-06 22:08:06,838 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-06 22:08:06,838 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2070822282] [2023-11-06 22:08:06,838 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-06 22:08:06,838 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-06 22:08:06,839 INFO L145 PredicateUnifier]: Initialized classic predicate unifier [2023-11-06 22:08:06,839 INFO L85 PathProgramCache]: Analyzing trace with hash -721591099, now seen corresponding path program 1 times [2023-11-06 22:08:06,839 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-06 22:08:06,840 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1637101357] [2023-11-06 22:08:06,840 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-06 22:08:06,840 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-06 22:08:06,884 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-06 22:08:07,024 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-06 22:08:07,024 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-06 22:08:07,025 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1637101357] [2023-11-06 22:08:07,025 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1637101357] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-06 22:08:07,025 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-06 22:08:07,026 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-06 22:08:07,026 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1958936452] [2023-11-06 22:08:07,027 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-06 22:08:07,028 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-06 22:08:07,029 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-06 22:08:07,030 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-06 22:08:07,030 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-06 22:08:07,031 INFO L87 Difference]: Start difference. First operand 633 states and 944 transitions. cyclomatic complexity: 312 Second operand has 3 states, 3 states have (on average 27.333333333333332) internal successors, (82), 3 states have internal predecessors, (82), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-06 22:08:07,071 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-06 22:08:07,071 INFO L93 Difference]: Finished difference Result 633 states and 943 transitions. [2023-11-06 22:08:07,072 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 633 states and 943 transitions. [2023-11-06 22:08:07,079 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 544 [2023-11-06 22:08:07,087 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 633 states to 633 states and 943 transitions. [2023-11-06 22:08:07,087 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 633 [2023-11-06 22:08:07,088 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 633 [2023-11-06 22:08:07,089 INFO L73 IsDeterministic]: Start isDeterministic. Operand 633 states and 943 transitions. [2023-11-06 22:08:07,096 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-06 22:08:07,096 INFO L218 hiAutomatonCegarLoop]: Abstraction has 633 states and 943 transitions. [2023-11-06 22:08:07,098 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 633 states and 943 transitions. [2023-11-06 22:08:07,131 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 633 to 633. [2023-11-06 22:08:07,133 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 633 states, 633 states have (on average 1.4897314375987363) internal successors, (943), 632 states have internal predecessors, (943), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-06 22:08:07,137 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 633 states to 633 states and 943 transitions. [2023-11-06 22:08:07,142 INFO L240 hiAutomatonCegarLoop]: Abstraction has 633 states and 943 transitions. [2023-11-06 22:08:07,143 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-06 22:08:07,145 INFO L428 stractBuchiCegarLoop]: Abstraction has 633 states and 943 transitions. [2023-11-06 22:08:07,146 INFO L335 stractBuchiCegarLoop]: ======== Iteration 3 ============ [2023-11-06 22:08:07,146 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 633 states and 943 transitions. [2023-11-06 22:08:07,153 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 544 [2023-11-06 22:08:07,155 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-06 22:08:07,155 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-06 22:08:07,160 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-06 22:08:07,166 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-06 22:08:07,169 INFO L748 eck$LassoCheckResult]: Stem: 2905#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2; 2906#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~8#1;havoc main_~__retres1~8#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 3033#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret20#1, start_simulation_#t~ret21#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 3034#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 2562#L461 assume 1 == ~m_i~0;~m_st~0 := 0; 2563#L461-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 3089#L466-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 3187#L471-1 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 2660#L476-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 2661#L481-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 2825#L486-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 2675#L491-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 2676#L670 assume !(0 == ~M_E~0); 3047#L670-2 assume !(0 == ~T1_E~0); 2998#L675-1 assume !(0 == ~T2_E~0); 2999#L680-1 assume !(0 == ~T3_E~0); 3087#L685-1 assume !(0 == ~T4_E~0); 3053#L690-1 assume !(0 == ~T5_E~0); 3054#L695-1 assume !(0 == ~T6_E~0); 3124#L700-1 assume 0 == ~E_1~0;~E_1~0 := 1; 3113#L705-1 assume !(0 == ~E_2~0); 3114#L710-1 assume !(0 == ~E_3~0); 2997#L715-1 assume !(0 == ~E_4~0); 2929#L720-1 assume !(0 == ~E_5~0); 2930#L725-1 assume !(0 == ~E_6~0); 2977#L730-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 3022#L320 assume 1 == ~m_pc~0; 2970#L321 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 2872#L331 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 2866#is_master_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 2826#L825 assume !(0 != activate_threads_~tmp~1#1); 2827#L825-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 2835#L339 assume !(1 == ~t1_pc~0); 2836#L339-2 is_transmit1_triggered_~__retres1~1#1 := 0; 2801#L350 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 2656#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 2657#L833 assume !(0 != activate_threads_~tmp___0~0#1); 2679#L833-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 2588#L358 assume 1 == ~t2_pc~0; 2589#L359 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 3106#L369 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 3036#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 2980#L841 assume !(0 != activate_threads_~tmp___1~0#1); 2821#L841-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 2822#L377 assume !(1 == ~t3_pc~0); 3071#L377-2 is_transmit3_triggered_~__retres1~3#1 := 0; 3072#L388 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 2586#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 2587#L849 assume !(0 != activate_threads_~tmp___2~0#1); 2830#L849-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 2758#L396 assume 1 == ~t4_pc~0; 2759#L397 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 2591#L407 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 2592#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 2738#L857 assume !(0 != activate_threads_~tmp___3~0#1); 2723#L857-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 2724#L415 assume 1 == ~t5_pc~0; 2808#L416 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 2861#L426 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 2879#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 2880#L865 assume !(0 != activate_threads_~tmp___4~0#1); 2632#L865-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 2633#L434 assume !(1 == ~t6_pc~0); 2959#L434-2 is_transmit6_triggered_~__retres1~6#1 := 0; 2960#L445 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 3027#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 3028#L873 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 2845#L873-2 havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 2846#L743 assume !(1 == ~M_E~0); 2715#L743-2 assume !(1 == ~T1_E~0); 2716#L748-1 assume !(1 == ~T2_E~0); 3018#L753-1 assume !(1 == ~T3_E~0); 3019#L758-1 assume 1 == ~T4_E~0;~T4_E~0 := 2; 3127#L763-1 assume !(1 == ~T5_E~0); 3159#L768-1 assume !(1 == ~T6_E~0); 2843#L773-1 assume !(1 == ~E_1~0); 2844#L778-1 assume !(1 == ~E_2~0); 2816#L783-1 assume !(1 == ~E_3~0); 2817#L788-1 assume !(1 == ~E_4~0); 3085#L793-1 assume !(1 == ~E_5~0); 3041#L798-1 assume 1 == ~E_6~0;~E_6~0 := 2; 2698#L803-1 assume { :end_inline_reset_delta_events } true; 2699#L1024-2 [2023-11-06 22:08:07,170 INFO L750 eck$LassoCheckResult]: Loop: 2699#L1024-2 assume !false; 2985#L1025 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 2570#L645-1 assume !false; 2813#L552 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 2926#L504 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 2640#L541 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 3059#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 3060#L556 assume !(0 != eval_~tmp~0#1); 2747#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 2748#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 2692#L670-3 assume 0 == ~M_E~0;~M_E~0 := 1; 2693#L670-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 2867#L675-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 2868#L680-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 3082#L685-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 3083#L690-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 3188#L695-3 assume !(0 == ~T6_E~0); 3090#L700-3 assume 0 == ~E_1~0;~E_1~0 := 1; 3091#L705-3 assume 0 == ~E_2~0;~E_2~0 := 1; 2736#L710-3 assume 0 == ~E_3~0;~E_3~0 := 1; 2737#L715-3 assume 0 == ~E_4~0;~E_4~0 := 1; 2981#L720-3 assume 0 == ~E_5~0;~E_5~0 := 1; 2982#L725-3 assume 0 == ~E_6~0;~E_6~0 := 1; 3052#L730-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 2838#L320-21 assume !(1 == ~m_pc~0); 2839#L320-23 is_master_triggered_~__retres1~0#1 := 0; 2979#L331-7 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 2786#is_master_triggered_returnLabel#8 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 2787#L825-21 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 3148#L825-23 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 2751#L339-21 assume 1 == ~t1_pc~0; 2752#L340-7 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 2881#L350-7 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 2720#is_transmit1_triggered_returnLabel#8 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 2616#L833-21 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 2617#L833-23 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 2713#L358-21 assume 1 == ~t2_pc~0; 2834#L359-7 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 2696#L369-7 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 2697#is_transmit2_triggered_returnLabel#8 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 2927#L841-21 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 2725#L841-23 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 2726#L377-21 assume 1 == ~t3_pc~0; 3161#L378-7 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 3012#L388-7 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 3013#is_transmit3_triggered_returnLabel#8 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 3029#L849-21 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 2893#L849-23 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 2894#L396-21 assume !(1 == ~t4_pc~0); 2913#L396-23 is_transmit4_triggered_~__retres1~4#1 := 0; 2914#L407-7 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 2969#is_transmit4_triggered_returnLabel#8 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 2598#L857-21 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 2599#L857-23 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 2869#L415-21 assume 1 == ~t5_pc~0; 2870#L416-7 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 2842#L426-7 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 3017#is_transmit5_triggered_returnLabel#8 activate_threads_#t~ret17#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 2963#L865-21 assume !(0 != activate_threads_~tmp___4~0#1); 2932#L865-23 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 2933#L434-21 assume 1 == ~t6_pc~0; 2942#L435-7 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 2624#L445-7 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 2996#is_transmit6_triggered_returnLabel#8 activate_threads_#t~ret18#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 2862#L873-21 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 2863#L873-23 havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 2855#L743-3 assume 1 == ~M_E~0;~M_E~0 := 2; 2856#L743-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 3171#L748-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 3004#L753-3 assume !(1 == ~T3_E~0); 2948#L758-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 2884#L763-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 2885#L768-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 3162#L773-3 assume 1 == ~E_1~0;~E_1~0 := 2; 2780#L778-3 assume 1 == ~E_2~0;~E_2~0 := 2; 2781#L783-3 assume 1 == ~E_3~0;~E_3~0 := 2; 3009#L788-3 assume 1 == ~E_4~0;~E_4~0 := 2; 3179#L793-3 assume !(1 == ~E_5~0); 3180#L798-3 assume 1 == ~E_6~0;~E_6~0 := 2; 3044#L803-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 2771#L504-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 2668#L541-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 3007#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret20#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret20#1;havoc start_simulation_#t~ret20#1; 3008#L1043 assume !(0 == start_simulation_~tmp~3#1); 3142#L1043-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret19#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 3005#L504-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 2790#L541-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 2654#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret19#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret19#1;havoc stop_simulation_#t~ret19#1; 2655#L998 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 2684#L1005 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 2685#stop_simulation_returnLabel#1 start_simulation_#t~ret21#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret19#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret21#1;havoc start_simulation_#t~ret21#1; 2962#L1056 assume !(0 != start_simulation_~tmp___0~1#1); 2699#L1024-2 [2023-11-06 22:08:07,171 INFO L145 PredicateUnifier]: Initialized classic predicate unifier [2023-11-06 22:08:07,171 INFO L85 PathProgramCache]: Analyzing trace with hash 227806621, now seen corresponding path program 1 times [2023-11-06 22:08:07,171 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-06 22:08:07,171 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1255741828] [2023-11-06 22:08:07,172 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-06 22:08:07,172 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-06 22:08:07,211 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-06 22:08:07,288 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-06 22:08:07,290 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-06 22:08:07,291 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1255741828] [2023-11-06 22:08:07,291 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1255741828] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-06 22:08:07,291 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-06 22:08:07,291 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-06 22:08:07,292 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1906947961] [2023-11-06 22:08:07,292 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-06 22:08:07,292 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-06 22:08:07,293 INFO L145 PredicateUnifier]: Initialized classic predicate unifier [2023-11-06 22:08:07,295 INFO L85 PathProgramCache]: Analyzing trace with hash -1648316281, now seen corresponding path program 1 times [2023-11-06 22:08:07,295 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-06 22:08:07,295 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [619590978] [2023-11-06 22:08:07,297 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-06 22:08:07,297 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-06 22:08:07,327 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-06 22:08:07,414 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-06 22:08:07,414 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-06 22:08:07,414 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [619590978] [2023-11-06 22:08:07,414 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [619590978] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-06 22:08:07,415 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-06 22:08:07,415 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-06 22:08:07,415 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1357705812] [2023-11-06 22:08:07,415 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-06 22:08:07,415 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-06 22:08:07,416 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-06 22:08:07,416 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-06 22:08:07,416 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-06 22:08:07,417 INFO L87 Difference]: Start difference. First operand 633 states and 943 transitions. cyclomatic complexity: 311 Second operand has 3 states, 3 states have (on average 27.333333333333332) internal successors, (82), 3 states have internal predecessors, (82), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-06 22:08:07,440 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-06 22:08:07,440 INFO L93 Difference]: Finished difference Result 633 states and 942 transitions. [2023-11-06 22:08:07,440 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 633 states and 942 transitions. [2023-11-06 22:08:07,447 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 544 [2023-11-06 22:08:07,452 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 633 states to 633 states and 942 transitions. [2023-11-06 22:08:07,452 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 633 [2023-11-06 22:08:07,454 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 633 [2023-11-06 22:08:07,454 INFO L73 IsDeterministic]: Start isDeterministic. Operand 633 states and 942 transitions. [2023-11-06 22:08:07,455 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-06 22:08:07,455 INFO L218 hiAutomatonCegarLoop]: Abstraction has 633 states and 942 transitions. [2023-11-06 22:08:07,457 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 633 states and 942 transitions. [2023-11-06 22:08:07,468 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 633 to 633. [2023-11-06 22:08:07,469 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 633 states, 633 states have (on average 1.4881516587677726) internal successors, (942), 632 states have internal predecessors, (942), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-06 22:08:07,473 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 633 states to 633 states and 942 transitions. [2023-11-06 22:08:07,473 INFO L240 hiAutomatonCegarLoop]: Abstraction has 633 states and 942 transitions. [2023-11-06 22:08:07,473 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-06 22:08:07,475 INFO L428 stractBuchiCegarLoop]: Abstraction has 633 states and 942 transitions. [2023-11-06 22:08:07,475 INFO L335 stractBuchiCegarLoop]: ======== Iteration 4 ============ [2023-11-06 22:08:07,475 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 633 states and 942 transitions. [2023-11-06 22:08:07,480 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 544 [2023-11-06 22:08:07,480 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-06 22:08:07,480 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-06 22:08:07,488 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-06 22:08:07,488 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-06 22:08:07,489 INFO L748 eck$LassoCheckResult]: Stem: 4173#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2; 4174#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~8#1;havoc main_~__retres1~8#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 4306#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret20#1, start_simulation_#t~ret21#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 4307#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 3835#L461 assume 1 == ~m_i~0;~m_st~0 := 0; 3836#L461-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 4361#L466-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 4460#L471-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 3931#L476-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 3932#L481-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 4098#L486-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 3947#L491-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 3948#L670 assume !(0 == ~M_E~0); 4318#L670-2 assume !(0 == ~T1_E~0); 4271#L675-1 assume !(0 == ~T2_E~0); 4272#L680-1 assume !(0 == ~T3_E~0); 4360#L685-1 assume !(0 == ~T4_E~0); 4325#L690-1 assume !(0 == ~T5_E~0); 4326#L695-1 assume !(0 == ~T6_E~0); 4397#L700-1 assume 0 == ~E_1~0;~E_1~0 := 1; 4386#L705-1 assume !(0 == ~E_2~0); 4387#L710-1 assume !(0 == ~E_3~0); 4270#L715-1 assume !(0 == ~E_4~0); 4201#L720-1 assume !(0 == ~E_5~0); 4202#L725-1 assume !(0 == ~E_6~0); 4250#L730-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 4295#L320 assume 1 == ~m_pc~0; 4242#L321 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 4145#L331 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 4139#is_master_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 4099#L825 assume !(0 != activate_threads_~tmp~1#1); 4100#L825-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 4104#L339 assume !(1 == ~t1_pc~0); 4105#L339-2 is_transmit1_triggered_~__retres1~1#1 := 0; 4074#L350 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 3929#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 3930#L833 assume !(0 != activate_threads_~tmp___0~0#1); 3952#L833-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 3861#L358 assume 1 == ~t2_pc~0; 3862#L359 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 4379#L369 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 4309#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 4253#L841 assume !(0 != activate_threads_~tmp___1~0#1); 4094#L841-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 4095#L377 assume !(1 == ~t3_pc~0); 4344#L377-2 is_transmit3_triggered_~__retres1~3#1 := 0; 4345#L388 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 3857#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 3858#L849 assume !(0 != activate_threads_~tmp___2~0#1); 4103#L849-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 4029#L396 assume 1 == ~t4_pc~0; 4030#L397 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 3864#L407 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 3865#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 4011#L857 assume !(0 != activate_threads_~tmp___3~0#1); 3996#L857-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 3997#L415 assume 1 == ~t5_pc~0; 4079#L416 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 4130#L426 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 4148#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 4149#L865 assume !(0 != activate_threads_~tmp___4~0#1); 3905#L865-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 3906#L434 assume !(1 == ~t6_pc~0); 4231#L434-2 is_transmit6_triggered_~__retres1~6#1 := 0; 4232#L445 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 4300#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 4301#L873 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 4118#L873-2 havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 4119#L743 assume !(1 == ~M_E~0); 3988#L743-2 assume !(1 == ~T1_E~0); 3989#L748-1 assume !(1 == ~T2_E~0); 4291#L753-1 assume !(1 == ~T3_E~0); 4292#L758-1 assume 1 == ~T4_E~0;~T4_E~0 := 2; 4400#L763-1 assume !(1 == ~T5_E~0); 4432#L768-1 assume !(1 == ~T6_E~0); 4111#L773-1 assume !(1 == ~E_1~0); 4112#L778-1 assume !(1 == ~E_2~0); 4089#L783-1 assume !(1 == ~E_3~0); 4090#L788-1 assume !(1 == ~E_4~0); 4358#L793-1 assume !(1 == ~E_5~0); 4314#L798-1 assume 1 == ~E_6~0;~E_6~0 := 2; 3969#L803-1 assume { :end_inline_reset_delta_events } true; 3970#L1024-2 [2023-11-06 22:08:07,489 INFO L750 eck$LassoCheckResult]: Loop: 3970#L1024-2 assume !false; 4258#L1025 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 3843#L645-1 assume !false; 4084#L552 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 4199#L504 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 3913#L541 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 4332#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 4333#L556 assume !(0 != eval_~tmp~0#1); 4018#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 4019#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 3959#L670-3 assume 0 == ~M_E~0;~M_E~0 := 1; 3960#L670-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 4140#L675-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 4141#L680-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 4355#L685-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 4356#L690-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 4461#L695-3 assume !(0 == ~T6_E~0); 4363#L700-3 assume 0 == ~E_1~0;~E_1~0 := 1; 4364#L705-3 assume 0 == ~E_2~0;~E_2~0 := 1; 4009#L710-3 assume 0 == ~E_3~0;~E_3~0 := 1; 4010#L715-3 assume 0 == ~E_4~0;~E_4~0 := 1; 4254#L720-3 assume 0 == ~E_5~0;~E_5~0 := 1; 4255#L725-3 assume 0 == ~E_6~0;~E_6~0 := 1; 4327#L730-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 4113#L320-21 assume !(1 == ~m_pc~0); 4114#L320-23 is_master_triggered_~__retres1~0#1 := 0; 4252#L331-7 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 4059#is_master_triggered_returnLabel#8 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 4060#L825-21 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 4421#L825-23 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 4024#L339-21 assume 1 == ~t1_pc~0; 4025#L340-7 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 4155#L350-7 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 3993#is_transmit1_triggered_returnLabel#8 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 3889#L833-21 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 3890#L833-23 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 3986#L358-21 assume !(1 == ~t2_pc~0); 4038#L358-23 is_transmit2_triggered_~__retres1~2#1 := 0; 3971#L369-7 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 3972#is_transmit2_triggered_returnLabel#8 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 4200#L841-21 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 3998#L841-23 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 3999#L377-21 assume 1 == ~t3_pc~0; 4434#L378-7 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 4285#L388-7 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 4286#is_transmit3_triggered_returnLabel#8 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 4302#L849-21 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 4166#L849-23 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 4167#L396-21 assume !(1 == ~t4_pc~0); 4186#L396-23 is_transmit4_triggered_~__retres1~4#1 := 0; 4187#L407-7 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 4244#is_transmit4_triggered_returnLabel#8 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 3871#L857-21 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 3872#L857-23 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 4142#L415-21 assume !(1 == ~t5_pc~0); 4116#L415-23 is_transmit5_triggered_~__retres1~5#1 := 0; 4117#L426-7 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 4290#is_transmit5_triggered_returnLabel#8 activate_threads_#t~ret17#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 4236#L865-21 assume !(0 != activate_threads_~tmp___4~0#1); 4205#L865-23 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 4206#L434-21 assume 1 == ~t6_pc~0; 4215#L435-7 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 3897#L445-7 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 4269#is_transmit6_triggered_returnLabel#8 activate_threads_#t~ret18#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 4135#L873-21 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 4136#L873-23 havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 4128#L743-3 assume 1 == ~M_E~0;~M_E~0 := 2; 4129#L743-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 4444#L748-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 4277#L753-3 assume !(1 == ~T3_E~0); 4221#L758-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 4157#L763-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 4158#L768-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 4435#L773-3 assume 1 == ~E_1~0;~E_1~0 := 2; 4053#L778-3 assume 1 == ~E_2~0;~E_2~0 := 2; 4054#L783-3 assume 1 == ~E_3~0;~E_3~0 := 2; 4282#L788-3 assume 1 == ~E_4~0;~E_4~0 := 2; 4452#L793-3 assume !(1 == ~E_5~0); 4453#L798-3 assume 1 == ~E_6~0;~E_6~0 := 2; 4317#L803-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 4044#L504-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 3941#L541-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 4280#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret20#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret20#1;havoc start_simulation_#t~ret20#1; 4281#L1043 assume !(0 == start_simulation_~tmp~3#1); 4415#L1043-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret19#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 4278#L504-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 4063#L541-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 3927#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret19#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret19#1;havoc stop_simulation_#t~ret19#1; 3928#L998 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 3957#L1005 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 3958#stop_simulation_returnLabel#1 start_simulation_#t~ret21#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret19#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret21#1;havoc start_simulation_#t~ret21#1; 4235#L1056 assume !(0 != start_simulation_~tmp___0~1#1); 3970#L1024-2 [2023-11-06 22:08:07,490 INFO L145 PredicateUnifier]: Initialized classic predicate unifier [2023-11-06 22:08:07,490 INFO L85 PathProgramCache]: Analyzing trace with hash -1506297829, now seen corresponding path program 1 times [2023-11-06 22:08:07,491 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-06 22:08:07,491 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1255105112] [2023-11-06 22:08:07,493 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-06 22:08:07,493 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-06 22:08:07,520 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-06 22:08:07,558 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-06 22:08:07,558 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-06 22:08:07,559 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1255105112] [2023-11-06 22:08:07,560 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1255105112] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-06 22:08:07,560 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-06 22:08:07,560 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-06 22:08:07,560 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [742339027] [2023-11-06 22:08:07,561 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-06 22:08:07,561 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-06 22:08:07,561 INFO L145 PredicateUnifier]: Initialized classic predicate unifier [2023-11-06 22:08:07,562 INFO L85 PathProgramCache]: Analyzing trace with hash -1117245051, now seen corresponding path program 1 times [2023-11-06 22:08:07,562 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-06 22:08:07,567 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [404672368] [2023-11-06 22:08:07,567 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-06 22:08:07,567 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-06 22:08:07,585 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-06 22:08:07,634 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-06 22:08:07,634 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-06 22:08:07,634 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [404672368] [2023-11-06 22:08:07,634 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [404672368] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-06 22:08:07,634 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-06 22:08:07,635 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-06 22:08:07,635 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [910904622] [2023-11-06 22:08:07,635 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-06 22:08:07,635 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-06 22:08:07,635 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-06 22:08:07,636 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-06 22:08:07,636 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-06 22:08:07,636 INFO L87 Difference]: Start difference. First operand 633 states and 942 transitions. cyclomatic complexity: 310 Second operand has 3 states, 3 states have (on average 27.333333333333332) internal successors, (82), 3 states have internal predecessors, (82), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-06 22:08:07,655 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-06 22:08:07,655 INFO L93 Difference]: Finished difference Result 633 states and 941 transitions. [2023-11-06 22:08:07,655 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 633 states and 941 transitions. [2023-11-06 22:08:07,660 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 544 [2023-11-06 22:08:07,666 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 633 states to 633 states and 941 transitions. [2023-11-06 22:08:07,666 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 633 [2023-11-06 22:08:07,667 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 633 [2023-11-06 22:08:07,667 INFO L73 IsDeterministic]: Start isDeterministic. Operand 633 states and 941 transitions. [2023-11-06 22:08:07,668 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-06 22:08:07,668 INFO L218 hiAutomatonCegarLoop]: Abstraction has 633 states and 941 transitions. [2023-11-06 22:08:07,669 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 633 states and 941 transitions. [2023-11-06 22:08:07,678 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 633 to 633. [2023-11-06 22:08:07,680 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 633 states, 633 states have (on average 1.4865718799368088) internal successors, (941), 632 states have internal predecessors, (941), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-06 22:08:07,682 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 633 states to 633 states and 941 transitions. [2023-11-06 22:08:07,682 INFO L240 hiAutomatonCegarLoop]: Abstraction has 633 states and 941 transitions. [2023-11-06 22:08:07,683 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-06 22:08:07,685 INFO L428 stractBuchiCegarLoop]: Abstraction has 633 states and 941 transitions. [2023-11-06 22:08:07,689 INFO L335 stractBuchiCegarLoop]: ======== Iteration 5 ============ [2023-11-06 22:08:07,689 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 633 states and 941 transitions. [2023-11-06 22:08:07,693 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 544 [2023-11-06 22:08:07,693 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-06 22:08:07,694 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-06 22:08:07,695 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-06 22:08:07,695 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-06 22:08:07,695 INFO L748 eck$LassoCheckResult]: Stem: 5446#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2; 5447#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~8#1;havoc main_~__retres1~8#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 5579#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret20#1, start_simulation_#t~ret21#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 5580#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 5108#L461 assume 1 == ~m_i~0;~m_st~0 := 0; 5109#L461-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 5634#L466-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 5733#L471-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 5204#L476-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 5205#L481-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 5371#L486-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 5220#L491-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 5221#L670 assume !(0 == ~M_E~0); 5591#L670-2 assume !(0 == ~T1_E~0); 5544#L675-1 assume !(0 == ~T2_E~0); 5545#L680-1 assume !(0 == ~T3_E~0); 5633#L685-1 assume !(0 == ~T4_E~0); 5598#L690-1 assume !(0 == ~T5_E~0); 5599#L695-1 assume !(0 == ~T6_E~0); 5670#L700-1 assume 0 == ~E_1~0;~E_1~0 := 1; 5659#L705-1 assume !(0 == ~E_2~0); 5660#L710-1 assume !(0 == ~E_3~0); 5543#L715-1 assume !(0 == ~E_4~0); 5474#L720-1 assume !(0 == ~E_5~0); 5475#L725-1 assume !(0 == ~E_6~0); 5523#L730-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 5568#L320 assume 1 == ~m_pc~0; 5515#L321 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 5418#L331 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 5412#is_master_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 5372#L825 assume !(0 != activate_threads_~tmp~1#1); 5373#L825-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 5377#L339 assume !(1 == ~t1_pc~0); 5378#L339-2 is_transmit1_triggered_~__retres1~1#1 := 0; 5347#L350 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 5202#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 5203#L833 assume !(0 != activate_threads_~tmp___0~0#1); 5225#L833-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 5134#L358 assume 1 == ~t2_pc~0; 5135#L359 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 5652#L369 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 5582#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 5526#L841 assume !(0 != activate_threads_~tmp___1~0#1); 5367#L841-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 5368#L377 assume !(1 == ~t3_pc~0); 5617#L377-2 is_transmit3_triggered_~__retres1~3#1 := 0; 5618#L388 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 5130#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 5131#L849 assume !(0 != activate_threads_~tmp___2~0#1); 5376#L849-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 5302#L396 assume 1 == ~t4_pc~0; 5303#L397 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 5137#L407 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 5138#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 5284#L857 assume !(0 != activate_threads_~tmp___3~0#1); 5269#L857-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 5270#L415 assume 1 == ~t5_pc~0; 5352#L416 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 5403#L426 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 5421#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 5422#L865 assume !(0 != activate_threads_~tmp___4~0#1); 5178#L865-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 5179#L434 assume !(1 == ~t6_pc~0); 5504#L434-2 is_transmit6_triggered_~__retres1~6#1 := 0; 5505#L445 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 5573#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 5574#L873 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 5391#L873-2 havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 5392#L743 assume !(1 == ~M_E~0); 5261#L743-2 assume !(1 == ~T1_E~0); 5262#L748-1 assume !(1 == ~T2_E~0); 5564#L753-1 assume !(1 == ~T3_E~0); 5565#L758-1 assume 1 == ~T4_E~0;~T4_E~0 := 2; 5673#L763-1 assume !(1 == ~T5_E~0); 5705#L768-1 assume !(1 == ~T6_E~0); 5384#L773-1 assume !(1 == ~E_1~0); 5385#L778-1 assume !(1 == ~E_2~0); 5362#L783-1 assume !(1 == ~E_3~0); 5363#L788-1 assume !(1 == ~E_4~0); 5631#L793-1 assume !(1 == ~E_5~0); 5587#L798-1 assume 1 == ~E_6~0;~E_6~0 := 2; 5242#L803-1 assume { :end_inline_reset_delta_events } true; 5243#L1024-2 [2023-11-06 22:08:07,696 INFO L750 eck$LassoCheckResult]: Loop: 5243#L1024-2 assume !false; 5531#L1025 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 5116#L645-1 assume !false; 5357#L552 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 5472#L504 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 5186#L541 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 5605#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 5606#L556 assume !(0 != eval_~tmp~0#1); 5291#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 5292#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 5232#L670-3 assume 0 == ~M_E~0;~M_E~0 := 1; 5233#L670-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 5413#L675-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 5414#L680-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 5628#L685-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 5629#L690-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 5734#L695-3 assume !(0 == ~T6_E~0); 5636#L700-3 assume 0 == ~E_1~0;~E_1~0 := 1; 5637#L705-3 assume 0 == ~E_2~0;~E_2~0 := 1; 5282#L710-3 assume 0 == ~E_3~0;~E_3~0 := 1; 5283#L715-3 assume 0 == ~E_4~0;~E_4~0 := 1; 5527#L720-3 assume 0 == ~E_5~0;~E_5~0 := 1; 5528#L725-3 assume 0 == ~E_6~0;~E_6~0 := 1; 5600#L730-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 5386#L320-21 assume !(1 == ~m_pc~0); 5387#L320-23 is_master_triggered_~__retres1~0#1 := 0; 5525#L331-7 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 5332#is_master_triggered_returnLabel#8 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 5333#L825-21 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 5694#L825-23 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 5297#L339-21 assume 1 == ~t1_pc~0; 5298#L340-7 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 5428#L350-7 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 5266#is_transmit1_triggered_returnLabel#8 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 5162#L833-21 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 5163#L833-23 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 5259#L358-21 assume 1 == ~t2_pc~0; 5383#L359-7 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 5244#L369-7 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 5245#is_transmit2_triggered_returnLabel#8 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 5473#L841-21 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 5271#L841-23 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 5272#L377-21 assume 1 == ~t3_pc~0; 5707#L378-7 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 5558#L388-7 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 5559#is_transmit3_triggered_returnLabel#8 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 5575#L849-21 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 5439#L849-23 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 5440#L396-21 assume !(1 == ~t4_pc~0); 5459#L396-23 is_transmit4_triggered_~__retres1~4#1 := 0; 5460#L407-7 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 5517#is_transmit4_triggered_returnLabel#8 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 5144#L857-21 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 5145#L857-23 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 5415#L415-21 assume 1 == ~t5_pc~0; 5416#L416-7 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 5390#L426-7 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 5563#is_transmit5_triggered_returnLabel#8 activate_threads_#t~ret17#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 5509#L865-21 assume !(0 != activate_threads_~tmp___4~0#1); 5478#L865-23 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 5479#L434-21 assume 1 == ~t6_pc~0; 5488#L435-7 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 5170#L445-7 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 5542#is_transmit6_triggered_returnLabel#8 activate_threads_#t~ret18#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 5408#L873-21 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 5409#L873-23 havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 5401#L743-3 assume 1 == ~M_E~0;~M_E~0 := 2; 5402#L743-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 5717#L748-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 5550#L753-3 assume !(1 == ~T3_E~0); 5494#L758-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 5430#L763-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 5431#L768-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 5708#L773-3 assume 1 == ~E_1~0;~E_1~0 := 2; 5326#L778-3 assume 1 == ~E_2~0;~E_2~0 := 2; 5327#L783-3 assume 1 == ~E_3~0;~E_3~0 := 2; 5555#L788-3 assume 1 == ~E_4~0;~E_4~0 := 2; 5725#L793-3 assume !(1 == ~E_5~0); 5726#L798-3 assume 1 == ~E_6~0;~E_6~0 := 2; 5590#L803-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 5317#L504-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 5214#L541-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 5553#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret20#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret20#1;havoc start_simulation_#t~ret20#1; 5554#L1043 assume !(0 == start_simulation_~tmp~3#1); 5688#L1043-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret19#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 5551#L504-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 5336#L541-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 5200#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret19#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret19#1;havoc stop_simulation_#t~ret19#1; 5201#L998 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 5230#L1005 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 5231#stop_simulation_returnLabel#1 start_simulation_#t~ret21#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret19#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret21#1;havoc start_simulation_#t~ret21#1; 5508#L1056 assume !(0 != start_simulation_~tmp___0~1#1); 5243#L1024-2 [2023-11-06 22:08:07,698 INFO L145 PredicateUnifier]: Initialized classic predicate unifier [2023-11-06 22:08:07,698 INFO L85 PathProgramCache]: Analyzing trace with hash 1901446621, now seen corresponding path program 1 times [2023-11-06 22:08:07,698 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-06 22:08:07,698 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [498072011] [2023-11-06 22:08:07,699 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-06 22:08:07,699 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-06 22:08:07,713 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-06 22:08:07,776 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-06 22:08:07,777 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-06 22:08:07,777 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [498072011] [2023-11-06 22:08:07,777 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [498072011] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-06 22:08:07,777 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-06 22:08:07,777 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-06 22:08:07,777 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [953864455] [2023-11-06 22:08:07,777 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-06 22:08:07,778 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-06 22:08:07,778 INFO L145 PredicateUnifier]: Initialized classic predicate unifier [2023-11-06 22:08:07,778 INFO L85 PathProgramCache]: Analyzing trace with hash -1648316281, now seen corresponding path program 2 times [2023-11-06 22:08:07,778 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-06 22:08:07,779 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [845662515] [2023-11-06 22:08:07,779 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-06 22:08:07,779 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-06 22:08:07,798 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-06 22:08:07,845 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-06 22:08:07,845 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-06 22:08:07,846 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [845662515] [2023-11-06 22:08:07,846 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [845662515] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-06 22:08:07,846 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-06 22:08:07,846 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-06 22:08:07,846 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1601405567] [2023-11-06 22:08:07,847 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-06 22:08:07,847 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-06 22:08:07,847 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-06 22:08:07,848 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-06 22:08:07,848 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-06 22:08:07,848 INFO L87 Difference]: Start difference. First operand 633 states and 941 transitions. cyclomatic complexity: 309 Second operand has 3 states, 3 states have (on average 27.333333333333332) internal successors, (82), 3 states have internal predecessors, (82), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-06 22:08:07,867 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-06 22:08:07,867 INFO L93 Difference]: Finished difference Result 633 states and 940 transitions. [2023-11-06 22:08:07,867 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 633 states and 940 transitions. [2023-11-06 22:08:07,872 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 544 [2023-11-06 22:08:07,878 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 633 states to 633 states and 940 transitions. [2023-11-06 22:08:07,878 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 633 [2023-11-06 22:08:07,879 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 633 [2023-11-06 22:08:07,879 INFO L73 IsDeterministic]: Start isDeterministic. Operand 633 states and 940 transitions. [2023-11-06 22:08:07,880 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-06 22:08:07,880 INFO L218 hiAutomatonCegarLoop]: Abstraction has 633 states and 940 transitions. [2023-11-06 22:08:07,882 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 633 states and 940 transitions. [2023-11-06 22:08:07,891 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 633 to 633. [2023-11-06 22:08:07,892 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 633 states, 633 states have (on average 1.4849921011058451) internal successors, (940), 632 states have internal predecessors, (940), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-06 22:08:07,895 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 633 states to 633 states and 940 transitions. [2023-11-06 22:08:07,895 INFO L240 hiAutomatonCegarLoop]: Abstraction has 633 states and 940 transitions. [2023-11-06 22:08:07,895 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-06 22:08:07,898 INFO L428 stractBuchiCegarLoop]: Abstraction has 633 states and 940 transitions. [2023-11-06 22:08:07,898 INFO L335 stractBuchiCegarLoop]: ======== Iteration 6 ============ [2023-11-06 22:08:07,898 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 633 states and 940 transitions. [2023-11-06 22:08:07,902 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 544 [2023-11-06 22:08:07,903 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-06 22:08:07,903 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-06 22:08:07,904 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-06 22:08:07,904 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-06 22:08:07,905 INFO L748 eck$LassoCheckResult]: Stem: 6722#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2; 6723#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~8#1;havoc main_~__retres1~8#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 6852#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret20#1, start_simulation_#t~ret21#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 6853#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 6381#L461 assume 1 == ~m_i~0;~m_st~0 := 0; 6382#L461-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 6908#L466-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 7006#L471-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 6479#L476-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 6480#L481-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 6644#L486-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 6493#L491-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 6494#L670 assume !(0 == ~M_E~0); 6864#L670-2 assume !(0 == ~T1_E~0); 6817#L675-1 assume !(0 == ~T2_E~0); 6818#L680-1 assume !(0 == ~T3_E~0); 6906#L685-1 assume !(0 == ~T4_E~0); 6871#L690-1 assume !(0 == ~T5_E~0); 6872#L695-1 assume !(0 == ~T6_E~0); 6943#L700-1 assume 0 == ~E_1~0;~E_1~0 := 1; 6932#L705-1 assume !(0 == ~E_2~0); 6933#L710-1 assume !(0 == ~E_3~0); 6816#L715-1 assume !(0 == ~E_4~0); 6747#L720-1 assume !(0 == ~E_5~0); 6748#L725-1 assume !(0 == ~E_6~0); 6796#L730-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 6841#L320 assume 1 == ~m_pc~0; 6789#L321 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 6691#L331 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 6685#is_master_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 6645#L825 assume !(0 != activate_threads_~tmp~1#1); 6646#L825-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 6650#L339 assume !(1 == ~t1_pc~0); 6651#L339-2 is_transmit1_triggered_~__retres1~1#1 := 0; 6620#L350 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 6475#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 6476#L833 assume !(0 != activate_threads_~tmp___0~0#1); 6498#L833-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 6407#L358 assume 1 == ~t2_pc~0; 6408#L359 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 6925#L369 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 6855#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 6799#L841 assume !(0 != activate_threads_~tmp___1~0#1); 6640#L841-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 6641#L377 assume !(1 == ~t3_pc~0); 6890#L377-2 is_transmit3_triggered_~__retres1~3#1 := 0; 6891#L388 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 6403#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 6404#L849 assume !(0 != activate_threads_~tmp___2~0#1); 6649#L849-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 6575#L396 assume 1 == ~t4_pc~0; 6576#L397 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 6410#L407 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 6411#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 6557#L857 assume !(0 != activate_threads_~tmp___3~0#1); 6542#L857-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 6543#L415 assume 1 == ~t5_pc~0; 6625#L416 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 6680#L426 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 6695#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 6696#L865 assume !(0 != activate_threads_~tmp___4~0#1); 6451#L865-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 6452#L434 assume !(1 == ~t6_pc~0); 6777#L434-2 is_transmit6_triggered_~__retres1~6#1 := 0; 6778#L445 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 6846#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 6847#L873 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 6664#L873-2 havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 6665#L743 assume !(1 == ~M_E~0); 6534#L743-2 assume !(1 == ~T1_E~0); 6535#L748-1 assume !(1 == ~T2_E~0); 6837#L753-1 assume !(1 == ~T3_E~0); 6838#L758-1 assume 1 == ~T4_E~0;~T4_E~0 := 2; 6946#L763-1 assume !(1 == ~T5_E~0); 6978#L768-1 assume !(1 == ~T6_E~0); 6659#L773-1 assume !(1 == ~E_1~0); 6660#L778-1 assume !(1 == ~E_2~0); 6635#L783-1 assume !(1 == ~E_3~0); 6636#L788-1 assume !(1 == ~E_4~0); 6904#L793-1 assume !(1 == ~E_5~0); 6860#L798-1 assume 1 == ~E_6~0;~E_6~0 := 2; 6515#L803-1 assume { :end_inline_reset_delta_events } true; 6516#L1024-2 [2023-11-06 22:08:07,905 INFO L750 eck$LassoCheckResult]: Loop: 6516#L1024-2 assume !false; 6804#L1025 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 6389#L645-1 assume !false; 6630#L552 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 6745#L504 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 6459#L541 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 6878#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 6879#L556 assume !(0 != eval_~tmp~0#1); 6566#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 6567#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 6509#L670-3 assume 0 == ~M_E~0;~M_E~0 := 1; 6510#L670-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 6688#L675-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 6689#L680-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 6901#L685-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 6902#L690-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 7007#L695-3 assume !(0 == ~T6_E~0); 6910#L700-3 assume 0 == ~E_1~0;~E_1~0 := 1; 6911#L705-3 assume 0 == ~E_2~0;~E_2~0 := 1; 6555#L710-3 assume 0 == ~E_3~0;~E_3~0 := 1; 6556#L715-3 assume 0 == ~E_4~0;~E_4~0 := 1; 6800#L720-3 assume 0 == ~E_5~0;~E_5~0 := 1; 6801#L725-3 assume 0 == ~E_6~0;~E_6~0 := 1; 6873#L730-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 6661#L320-21 assume !(1 == ~m_pc~0); 6662#L320-23 is_master_triggered_~__retres1~0#1 := 0; 6798#L331-7 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 6605#is_master_triggered_returnLabel#8 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 6606#L825-21 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 6968#L825-23 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 6570#L339-21 assume 1 == ~t1_pc~0; 6571#L340-7 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 6701#L350-7 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 6539#is_transmit1_triggered_returnLabel#8 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 6435#L833-21 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 6436#L833-23 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 6532#L358-21 assume 1 == ~t2_pc~0; 6656#L359-7 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 6517#L369-7 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 6518#is_transmit2_triggered_returnLabel#8 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 6746#L841-21 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 6544#L841-23 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 6545#L377-21 assume 1 == ~t3_pc~0; 6980#L378-7 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 6829#L388-7 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 6830#is_transmit3_triggered_returnLabel#8 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 6848#L849-21 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 6712#L849-23 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 6713#L396-21 assume !(1 == ~t4_pc~0); 6732#L396-23 is_transmit4_triggered_~__retres1~4#1 := 0; 6733#L407-7 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 6788#is_transmit4_triggered_returnLabel#8 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 6417#L857-21 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 6418#L857-23 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 6686#L415-21 assume !(1 == ~t5_pc~0); 6657#L415-23 is_transmit5_triggered_~__retres1~5#1 := 0; 6658#L426-7 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 6836#is_transmit5_triggered_returnLabel#8 activate_threads_#t~ret17#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 6782#L865-21 assume !(0 != activate_threads_~tmp___4~0#1); 6751#L865-23 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 6752#L434-21 assume !(1 == ~t6_pc~0); 6440#L434-23 is_transmit6_triggered_~__retres1~6#1 := 0; 6441#L445-7 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 6815#is_transmit6_triggered_returnLabel#8 activate_threads_#t~ret18#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 6681#L873-21 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 6682#L873-23 havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 6674#L743-3 assume 1 == ~M_E~0;~M_E~0 := 2; 6675#L743-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 6990#L748-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 6823#L753-3 assume !(1 == ~T3_E~0); 6767#L758-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 6703#L763-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 6704#L768-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 6981#L773-3 assume 1 == ~E_1~0;~E_1~0 := 2; 6599#L778-3 assume 1 == ~E_2~0;~E_2~0 := 2; 6600#L783-3 assume 1 == ~E_3~0;~E_3~0 := 2; 6828#L788-3 assume 1 == ~E_4~0;~E_4~0 := 2; 6998#L793-3 assume !(1 == ~E_5~0); 6999#L798-3 assume 1 == ~E_6~0;~E_6~0 := 2; 6863#L803-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 6590#L504-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 6487#L541-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 6826#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret20#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret20#1;havoc start_simulation_#t~ret20#1; 6827#L1043 assume !(0 == start_simulation_~tmp~3#1); 6961#L1043-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret19#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 6824#L504-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 6608#L541-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 6473#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret19#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret19#1;havoc stop_simulation_#t~ret19#1; 6474#L998 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 6503#L1005 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 6504#stop_simulation_returnLabel#1 start_simulation_#t~ret21#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret19#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret21#1;havoc start_simulation_#t~ret21#1; 6781#L1056 assume !(0 != start_simulation_~tmp___0~1#1); 6516#L1024-2 [2023-11-06 22:08:07,906 INFO L145 PredicateUnifier]: Initialized classic predicate unifier [2023-11-06 22:08:07,906 INFO L85 PathProgramCache]: Analyzing trace with hash -482478117, now seen corresponding path program 1 times [2023-11-06 22:08:07,907 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-06 22:08:07,907 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1380346755] [2023-11-06 22:08:07,907 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-06 22:08:07,907 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-06 22:08:07,918 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-06 22:08:07,944 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-06 22:08:07,945 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-06 22:08:07,945 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1380346755] [2023-11-06 22:08:07,945 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1380346755] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-06 22:08:07,945 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-06 22:08:07,946 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-06 22:08:07,946 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [346847011] [2023-11-06 22:08:07,946 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-06 22:08:07,946 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-06 22:08:07,947 INFO L145 PredicateUnifier]: Initialized classic predicate unifier [2023-11-06 22:08:07,947 INFO L85 PathProgramCache]: Analyzing trace with hash -206020987, now seen corresponding path program 1 times [2023-11-06 22:08:07,952 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-06 22:08:07,952 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1112042631] [2023-11-06 22:08:07,952 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-06 22:08:07,953 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-06 22:08:07,966 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-06 22:08:08,010 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-06 22:08:08,011 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-06 22:08:08,011 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1112042631] [2023-11-06 22:08:08,011 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1112042631] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-06 22:08:08,011 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-06 22:08:08,012 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-06 22:08:08,012 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1397782779] [2023-11-06 22:08:08,012 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-06 22:08:08,013 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-06 22:08:08,013 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-06 22:08:08,013 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-06 22:08:08,013 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-06 22:08:08,014 INFO L87 Difference]: Start difference. First operand 633 states and 940 transitions. cyclomatic complexity: 308 Second operand has 3 states, 3 states have (on average 27.333333333333332) internal successors, (82), 3 states have internal predecessors, (82), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-06 22:08:08,032 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-06 22:08:08,032 INFO L93 Difference]: Finished difference Result 633 states and 939 transitions. [2023-11-06 22:08:08,032 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 633 states and 939 transitions. [2023-11-06 22:08:08,037 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 544 [2023-11-06 22:08:08,052 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 633 states to 633 states and 939 transitions. [2023-11-06 22:08:08,052 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 633 [2023-11-06 22:08:08,053 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 633 [2023-11-06 22:08:08,053 INFO L73 IsDeterministic]: Start isDeterministic. Operand 633 states and 939 transitions. [2023-11-06 22:08:08,054 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-06 22:08:08,054 INFO L218 hiAutomatonCegarLoop]: Abstraction has 633 states and 939 transitions. [2023-11-06 22:08:08,056 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 633 states and 939 transitions. [2023-11-06 22:08:08,065 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 633 to 633. [2023-11-06 22:08:08,066 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 633 states, 633 states have (on average 1.4834123222748816) internal successors, (939), 632 states have internal predecessors, (939), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-06 22:08:08,069 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 633 states to 633 states and 939 transitions. [2023-11-06 22:08:08,069 INFO L240 hiAutomatonCegarLoop]: Abstraction has 633 states and 939 transitions. [2023-11-06 22:08:08,070 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-06 22:08:08,072 INFO L428 stractBuchiCegarLoop]: Abstraction has 633 states and 939 transitions. [2023-11-06 22:08:08,072 INFO L335 stractBuchiCegarLoop]: ======== Iteration 7 ============ [2023-11-06 22:08:08,072 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 633 states and 939 transitions. [2023-11-06 22:08:08,076 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 544 [2023-11-06 22:08:08,077 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-06 22:08:08,077 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-06 22:08:08,078 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-06 22:08:08,078 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-06 22:08:08,079 INFO L748 eck$LassoCheckResult]: Stem: 7997#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2; 7998#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~8#1;havoc main_~__retres1~8#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 8125#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret20#1, start_simulation_#t~ret21#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 8126#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 7654#L461 assume 1 == ~m_i~0;~m_st~0 := 0; 7655#L461-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 8181#L466-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 8279#L471-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 7752#L476-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 7753#L481-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 7917#L486-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 7767#L491-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 7768#L670 assume !(0 == ~M_E~0); 8139#L670-2 assume !(0 == ~T1_E~0); 8090#L675-1 assume !(0 == ~T2_E~0); 8091#L680-1 assume !(0 == ~T3_E~0); 8179#L685-1 assume !(0 == ~T4_E~0); 8145#L690-1 assume !(0 == ~T5_E~0); 8146#L695-1 assume !(0 == ~T6_E~0); 8216#L700-1 assume 0 == ~E_1~0;~E_1~0 := 1; 8205#L705-1 assume !(0 == ~E_2~0); 8206#L710-1 assume !(0 == ~E_3~0); 8089#L715-1 assume !(0 == ~E_4~0); 8021#L720-1 assume !(0 == ~E_5~0); 8022#L725-1 assume !(0 == ~E_6~0); 8069#L730-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 8114#L320 assume 1 == ~m_pc~0; 8062#L321 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 7964#L331 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 7958#is_master_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 7918#L825 assume !(0 != activate_threads_~tmp~1#1); 7919#L825-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 7924#L339 assume !(1 == ~t1_pc~0); 7925#L339-2 is_transmit1_triggered_~__retres1~1#1 := 0; 7893#L350 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 7748#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 7749#L833 assume !(0 != activate_threads_~tmp___0~0#1); 7771#L833-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 7680#L358 assume 1 == ~t2_pc~0; 7681#L359 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 8198#L369 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 8128#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 8072#L841 assume !(0 != activate_threads_~tmp___1~0#1); 7913#L841-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 7914#L377 assume !(1 == ~t3_pc~0); 8163#L377-2 is_transmit3_triggered_~__retres1~3#1 := 0; 8164#L388 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 7678#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 7679#L849 assume !(0 != activate_threads_~tmp___2~0#1); 7922#L849-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 7850#L396 assume 1 == ~t4_pc~0; 7851#L397 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 7683#L407 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 7684#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 7830#L857 assume !(0 != activate_threads_~tmp___3~0#1); 7815#L857-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 7816#L415 assume 1 == ~t5_pc~0; 7900#L416 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 7953#L426 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 7971#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 7972#L865 assume !(0 != activate_threads_~tmp___4~0#1); 7724#L865-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 7725#L434 assume !(1 == ~t6_pc~0); 8051#L434-2 is_transmit6_triggered_~__retres1~6#1 := 0; 8052#L445 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 8119#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 8120#L873 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 7937#L873-2 havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 7938#L743 assume !(1 == ~M_E~0); 7807#L743-2 assume !(1 == ~T1_E~0); 7808#L748-1 assume !(1 == ~T2_E~0); 8110#L753-1 assume !(1 == ~T3_E~0); 8111#L758-1 assume 1 == ~T4_E~0;~T4_E~0 := 2; 8219#L763-1 assume !(1 == ~T5_E~0); 8251#L768-1 assume !(1 == ~T6_E~0); 7935#L773-1 assume !(1 == ~E_1~0); 7936#L778-1 assume !(1 == ~E_2~0); 7908#L783-1 assume !(1 == ~E_3~0); 7909#L788-1 assume !(1 == ~E_4~0); 8177#L793-1 assume !(1 == ~E_5~0); 8133#L798-1 assume 1 == ~E_6~0;~E_6~0 := 2; 7790#L803-1 assume { :end_inline_reset_delta_events } true; 7791#L1024-2 [2023-11-06 22:08:08,079 INFO L750 eck$LassoCheckResult]: Loop: 7791#L1024-2 assume !false; 8077#L1025 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 7662#L645-1 assume !false; 7905#L552 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 8018#L504 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 7732#L541 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 8151#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 8152#L556 assume !(0 != eval_~tmp~0#1); 7839#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 7840#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 7784#L670-3 assume 0 == ~M_E~0;~M_E~0 := 1; 7785#L670-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 7961#L675-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 7962#L680-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 8174#L685-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 8175#L690-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 8280#L695-3 assume !(0 == ~T6_E~0); 8182#L700-3 assume 0 == ~E_1~0;~E_1~0 := 1; 8183#L705-3 assume 0 == ~E_2~0;~E_2~0 := 1; 7828#L710-3 assume 0 == ~E_3~0;~E_3~0 := 1; 7829#L715-3 assume 0 == ~E_4~0;~E_4~0 := 1; 8073#L720-3 assume 0 == ~E_5~0;~E_5~0 := 1; 8074#L725-3 assume 0 == ~E_6~0;~E_6~0 := 1; 8144#L730-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 7930#L320-21 assume !(1 == ~m_pc~0); 7931#L320-23 is_master_triggered_~__retres1~0#1 := 0; 8071#L331-7 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 7878#is_master_triggered_returnLabel#8 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 7879#L825-21 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 8240#L825-23 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 7843#L339-21 assume 1 == ~t1_pc~0; 7844#L340-7 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 7973#L350-7 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 7812#is_transmit1_triggered_returnLabel#8 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 7708#L833-21 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 7709#L833-23 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 7805#L358-21 assume !(1 == ~t2_pc~0); 7857#L358-23 is_transmit2_triggered_~__retres1~2#1 := 0; 7788#L369-7 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 7789#is_transmit2_triggered_returnLabel#8 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 8019#L841-21 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 7817#L841-23 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 7818#L377-21 assume !(1 == ~t3_pc~0); 8192#L377-23 is_transmit3_triggered_~__retres1~3#1 := 0; 8102#L388-7 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 8103#is_transmit3_triggered_returnLabel#8 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 8121#L849-21 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 7985#L849-23 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 7986#L396-21 assume !(1 == ~t4_pc~0); 8005#L396-23 is_transmit4_triggered_~__retres1~4#1 := 0; 8006#L407-7 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 8061#is_transmit4_triggered_returnLabel#8 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 7690#L857-21 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 7691#L857-23 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 7959#L415-21 assume 1 == ~t5_pc~0; 7960#L416-7 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 7934#L426-7 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 8109#is_transmit5_triggered_returnLabel#8 activate_threads_#t~ret17#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 8055#L865-21 assume !(0 != activate_threads_~tmp___4~0#1); 8024#L865-23 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 8025#L434-21 assume 1 == ~t6_pc~0; 8034#L435-7 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 7716#L445-7 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 8088#is_transmit6_triggered_returnLabel#8 activate_threads_#t~ret18#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 7954#L873-21 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 7955#L873-23 havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 7947#L743-3 assume 1 == ~M_E~0;~M_E~0 := 2; 7948#L743-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 8263#L748-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 8096#L753-3 assume !(1 == ~T3_E~0); 8040#L758-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 7976#L763-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 7977#L768-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 8254#L773-3 assume 1 == ~E_1~0;~E_1~0 := 2; 7872#L778-3 assume 1 == ~E_2~0;~E_2~0 := 2; 7873#L783-3 assume 1 == ~E_3~0;~E_3~0 := 2; 8101#L788-3 assume 1 == ~E_4~0;~E_4~0 := 2; 8271#L793-3 assume !(1 == ~E_5~0); 8272#L798-3 assume 1 == ~E_6~0;~E_6~0 := 2; 8136#L803-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 7863#L504-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 7760#L541-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 8099#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret20#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret20#1;havoc start_simulation_#t~ret20#1; 8100#L1043 assume !(0 == start_simulation_~tmp~3#1); 8234#L1043-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret19#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 8097#L504-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 7881#L541-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 7746#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret19#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret19#1;havoc stop_simulation_#t~ret19#1; 7747#L998 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 7776#L1005 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 7777#stop_simulation_returnLabel#1 start_simulation_#t~ret21#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret19#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret21#1;havoc start_simulation_#t~ret21#1; 8054#L1056 assume !(0 != start_simulation_~tmp___0~1#1); 7791#L1024-2 [2023-11-06 22:08:08,080 INFO L145 PredicateUnifier]: Initialized classic predicate unifier [2023-11-06 22:08:08,080 INFO L85 PathProgramCache]: Analyzing trace with hash -559378915, now seen corresponding path program 1 times [2023-11-06 22:08:08,080 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-06 22:08:08,080 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [201724062] [2023-11-06 22:08:08,080 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-06 22:08:08,081 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-06 22:08:08,094 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-06 22:08:08,156 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-06 22:08:08,157 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-06 22:08:08,157 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [201724062] [2023-11-06 22:08:08,157 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [201724062] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-06 22:08:08,157 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-06 22:08:08,157 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-06 22:08:08,158 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2102064837] [2023-11-06 22:08:08,158 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-06 22:08:08,158 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-06 22:08:08,158 INFO L145 PredicateUnifier]: Initialized classic predicate unifier [2023-11-06 22:08:08,159 INFO L85 PathProgramCache]: Analyzing trace with hash 924064517, now seen corresponding path program 1 times [2023-11-06 22:08:08,159 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-06 22:08:08,159 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1754639770] [2023-11-06 22:08:08,159 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-06 22:08:08,159 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-06 22:08:08,175 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-06 22:08:08,208 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-06 22:08:08,208 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-06 22:08:08,208 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1754639770] [2023-11-06 22:08:08,208 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1754639770] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-06 22:08:08,208 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-06 22:08:08,209 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-06 22:08:08,209 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1201013959] [2023-11-06 22:08:08,209 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-06 22:08:08,209 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-06 22:08:08,210 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-06 22:08:08,210 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2023-11-06 22:08:08,210 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2023-11-06 22:08:08,210 INFO L87 Difference]: Start difference. First operand 633 states and 939 transitions. cyclomatic complexity: 307 Second operand has 4 states, 4 states have (on average 20.5) internal successors, (82), 3 states have internal predecessors, (82), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-06 22:08:08,393 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-06 22:08:08,393 INFO L93 Difference]: Finished difference Result 1138 states and 1686 transitions. [2023-11-06 22:08:08,393 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1138 states and 1686 transitions. [2023-11-06 22:08:08,402 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 1036 [2023-11-06 22:08:08,451 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1138 states to 1138 states and 1686 transitions. [2023-11-06 22:08:08,452 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1138 [2023-11-06 22:08:08,453 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1138 [2023-11-06 22:08:08,453 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1138 states and 1686 transitions. [2023-11-06 22:08:08,455 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-06 22:08:08,455 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1138 states and 1686 transitions. [2023-11-06 22:08:08,458 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1138 states and 1686 transitions. [2023-11-06 22:08:08,478 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1138 to 1136. [2023-11-06 22:08:08,483 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1136 states, 1136 states have (on average 1.482394366197183) internal successors, (1684), 1135 states have internal predecessors, (1684), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-06 22:08:08,487 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1136 states to 1136 states and 1684 transitions. [2023-11-06 22:08:08,487 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1136 states and 1684 transitions. [2023-11-06 22:08:08,488 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2023-11-06 22:08:08,490 INFO L428 stractBuchiCegarLoop]: Abstraction has 1136 states and 1684 transitions. [2023-11-06 22:08:08,490 INFO L335 stractBuchiCegarLoop]: ======== Iteration 8 ============ [2023-11-06 22:08:08,490 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1136 states and 1684 transitions. [2023-11-06 22:08:08,497 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 1036 [2023-11-06 22:08:08,498 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-06 22:08:08,498 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-06 22:08:08,499 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-06 22:08:08,499 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-06 22:08:08,500 INFO L748 eck$LassoCheckResult]: Stem: 9774#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2; 9775#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~8#1;havoc main_~__retres1~8#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 9907#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret20#1, start_simulation_#t~ret21#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 9908#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 9435#L461 assume 1 == ~m_i~0;~m_st~0 := 0; 9436#L461-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 9964#L466-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 10076#L471-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 9531#L476-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 9532#L481-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 9699#L486-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 9547#L491-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 9548#L670 assume !(0 == ~M_E~0); 9919#L670-2 assume !(0 == ~T1_E~0); 9872#L675-1 assume !(0 == ~T2_E~0); 9873#L680-1 assume !(0 == ~T3_E~0); 9963#L685-1 assume !(0 == ~T4_E~0); 9926#L690-1 assume !(0 == ~T5_E~0); 9927#L695-1 assume !(0 == ~T6_E~0); 10000#L700-1 assume !(0 == ~E_1~0); 9989#L705-1 assume !(0 == ~E_2~0); 9990#L710-1 assume !(0 == ~E_3~0); 9871#L715-1 assume !(0 == ~E_4~0); 9802#L720-1 assume !(0 == ~E_5~0); 9803#L725-1 assume !(0 == ~E_6~0); 9851#L730-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 9896#L320 assume 1 == ~m_pc~0; 9843#L321 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 9746#L331 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 9740#is_master_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 9700#L825 assume !(0 != activate_threads_~tmp~1#1); 9701#L825-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 9705#L339 assume !(1 == ~t1_pc~0); 9706#L339-2 is_transmit1_triggered_~__retres1~1#1 := 0; 9674#L350 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 9529#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 9530#L833 assume !(0 != activate_threads_~tmp___0~0#1); 9552#L833-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 9461#L358 assume 1 == ~t2_pc~0; 9462#L359 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 9982#L369 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 9910#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 9854#L841 assume !(0 != activate_threads_~tmp___1~0#1); 9695#L841-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 9696#L377 assume !(1 == ~t3_pc~0); 9946#L377-2 is_transmit3_triggered_~__retres1~3#1 := 0; 9947#L388 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 9457#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 9458#L849 assume !(0 != activate_threads_~tmp___2~0#1); 9704#L849-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 9629#L396 assume 1 == ~t4_pc~0; 9630#L397 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 9464#L407 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 9465#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 9611#L857 assume !(0 != activate_threads_~tmp___3~0#1); 9596#L857-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 9597#L415 assume 1 == ~t5_pc~0; 9679#L416 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 9731#L426 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 9749#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 9750#L865 assume !(0 != activate_threads_~tmp___4~0#1); 9505#L865-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 9506#L434 assume !(1 == ~t6_pc~0); 9832#L434-2 is_transmit6_triggered_~__retres1~6#1 := 0; 9833#L445 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 9901#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 9902#L873 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 9719#L873-2 havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 9720#L743 assume !(1 == ~M_E~0); 9588#L743-2 assume !(1 == ~T1_E~0); 9589#L748-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 9892#L753-1 assume !(1 == ~T3_E~0); 9893#L758-1 assume 1 == ~T4_E~0;~T4_E~0 := 2; 10003#L763-1 assume !(1 == ~T5_E~0); 10038#L768-1 assume !(1 == ~T6_E~0); 9712#L773-1 assume !(1 == ~E_1~0); 9713#L778-1 assume !(1 == ~E_2~0); 9690#L783-1 assume !(1 == ~E_3~0); 9691#L788-1 assume !(1 == ~E_4~0); 9961#L793-1 assume !(1 == ~E_5~0); 9915#L798-1 assume 1 == ~E_6~0;~E_6~0 := 2; 9569#L803-1 assume { :end_inline_reset_delta_events } true; 9570#L1024-2 [2023-11-06 22:08:08,500 INFO L750 eck$LassoCheckResult]: Loop: 9570#L1024-2 assume !false; 9859#L1025 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 9684#L645-1 assume !false; 9685#L552 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 9800#L504 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 9513#L541 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 9933#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 9934#L556 assume !(0 != eval_~tmp~0#1); 9618#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 9619#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 10092#L670-3 assume 0 == ~M_E~0;~M_E~0 := 1; 10091#L670-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 10089#L675-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 10090#L680-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 10570#L685-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 10569#L690-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 10568#L695-3 assume !(0 == ~T6_E~0); 10567#L700-3 assume !(0 == ~E_1~0); 10566#L705-3 assume 0 == ~E_2~0;~E_2~0 := 1; 10565#L710-3 assume 0 == ~E_3~0;~E_3~0 := 1; 10564#L715-3 assume 0 == ~E_4~0;~E_4~0 := 1; 10563#L720-3 assume 0 == ~E_5~0;~E_5~0 := 1; 10562#L725-3 assume 0 == ~E_6~0;~E_6~0 := 1; 10561#L730-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 10560#L320-21 assume !(1 == ~m_pc~0); 10558#L320-23 is_master_triggered_~__retres1~0#1 := 0; 10557#L331-7 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 10556#is_master_triggered_returnLabel#8 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 10555#L825-21 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 10554#L825-23 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 10553#L339-21 assume 1 == ~t1_pc~0; 10551#L340-7 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 10550#L350-7 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 9593#is_transmit1_triggered_returnLabel#8 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 9489#L833-21 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 9490#L833-23 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 9586#L358-21 assume !(1 == ~t2_pc~0); 10458#L358-23 is_transmit2_triggered_~__retres1~2#1 := 0; 10455#L369-7 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 10453#is_transmit2_triggered_returnLabel#8 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 10451#L841-21 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 10449#L841-23 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 10447#L377-21 assume 1 == ~t3_pc~0; 10444#L378-7 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 10441#L388-7 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 10439#is_transmit3_triggered_returnLabel#8 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 10437#L849-21 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 10435#L849-23 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 10433#L396-21 assume !(1 == ~t4_pc~0); 10430#L396-23 is_transmit4_triggered_~__retres1~4#1 := 0; 10427#L407-7 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 10425#is_transmit4_triggered_returnLabel#8 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 10423#L857-21 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 10421#L857-23 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 10419#L415-21 assume 1 == ~t5_pc~0; 10416#L416-7 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 10413#L426-7 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 10411#is_transmit5_triggered_returnLabel#8 activate_threads_#t~ret17#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 10385#L865-21 assume !(0 != activate_threads_~tmp___4~0#1); 10384#L865-23 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 10382#L434-21 assume 1 == ~t6_pc~0; 10379#L435-7 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 10377#L445-7 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 10375#is_transmit6_triggered_returnLabel#8 activate_threads_#t~ret18#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 10373#L873-21 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 10370#L873-23 havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 10368#L743-3 assume 1 == ~M_E~0;~M_E~0 := 2; 10053#L743-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 10054#L748-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 9878#L753-3 assume !(1 == ~T3_E~0); 9822#L758-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 9758#L763-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 9759#L768-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 10041#L773-3 assume 1 == ~E_1~0;~E_1~0 := 2; 9653#L778-3 assume 1 == ~E_2~0;~E_2~0 := 2; 9654#L783-3 assume 1 == ~E_3~0;~E_3~0 := 2; 9883#L788-3 assume 1 == ~E_4~0;~E_4~0 := 2; 10067#L793-3 assume !(1 == ~E_5~0); 10068#L798-3 assume 1 == ~E_6~0;~E_6~0 := 2; 9918#L803-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 9644#L504-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 9541#L541-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 9881#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret20#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret20#1;havoc start_simulation_#t~ret20#1; 9882#L1043 assume !(0 == start_simulation_~tmp~3#1); 10019#L1043-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret19#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 9879#L504-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 9663#L541-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 9527#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret19#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret19#1;havoc stop_simulation_#t~ret19#1; 9528#L998 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 9557#L1005 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 9558#stop_simulation_returnLabel#1 start_simulation_#t~ret21#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret19#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret21#1;havoc start_simulation_#t~ret21#1; 9836#L1056 assume !(0 != start_simulation_~tmp___0~1#1); 9570#L1024-2 [2023-11-06 22:08:08,501 INFO L145 PredicateUnifier]: Initialized classic predicate unifier [2023-11-06 22:08:08,501 INFO L85 PathProgramCache]: Analyzing trace with hash -1234940959, now seen corresponding path program 1 times [2023-11-06 22:08:08,502 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-06 22:08:08,502 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1289845163] [2023-11-06 22:08:08,502 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-06 22:08:08,502 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-06 22:08:08,516 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-06 22:08:08,562 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-06 22:08:08,562 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-06 22:08:08,564 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1289845163] [2023-11-06 22:08:08,564 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1289845163] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-06 22:08:08,564 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-06 22:08:08,564 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2023-11-06 22:08:08,564 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1248842698] [2023-11-06 22:08:08,565 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-06 22:08:08,565 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-06 22:08:08,565 INFO L145 PredicateUnifier]: Initialized classic predicate unifier [2023-11-06 22:08:08,565 INFO L85 PathProgramCache]: Analyzing trace with hash 93538728, now seen corresponding path program 1 times [2023-11-06 22:08:08,566 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-06 22:08:08,568 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [313085076] [2023-11-06 22:08:08,568 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-06 22:08:08,568 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-06 22:08:08,583 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-06 22:08:08,624 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-06 22:08:08,624 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-06 22:08:08,624 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [313085076] [2023-11-06 22:08:08,627 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [313085076] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-06 22:08:08,627 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-06 22:08:08,627 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-06 22:08:08,627 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [656770742] [2023-11-06 22:08:08,627 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-06 22:08:08,628 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-06 22:08:08,628 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-06 22:08:08,629 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-06 22:08:08,629 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-06 22:08:08,629 INFO L87 Difference]: Start difference. First operand 1136 states and 1684 transitions. cyclomatic complexity: 550 Second operand has 3 states, 3 states have (on average 27.333333333333332) internal successors, (82), 2 states have internal predecessors, (82), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-06 22:08:08,743 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-06 22:08:08,744 INFO L93 Difference]: Finished difference Result 1658 states and 2427 transitions. [2023-11-06 22:08:08,744 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1658 states and 2427 transitions. [2023-11-06 22:08:08,758 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 1557 [2023-11-06 22:08:08,771 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1658 states to 1658 states and 2427 transitions. [2023-11-06 22:08:08,771 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1658 [2023-11-06 22:08:08,773 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1658 [2023-11-06 22:08:08,773 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1658 states and 2427 transitions. [2023-11-06 22:08:08,777 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-06 22:08:08,777 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1658 states and 2427 transitions. [2023-11-06 22:08:08,780 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1658 states and 2427 transitions. [2023-11-06 22:08:08,807 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1658 to 1607. [2023-11-06 22:08:08,810 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1607 states, 1607 states have (on average 1.4667081518357188) internal successors, (2357), 1606 states have internal predecessors, (2357), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-06 22:08:08,817 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1607 states to 1607 states and 2357 transitions. [2023-11-06 22:08:08,817 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1607 states and 2357 transitions. [2023-11-06 22:08:08,817 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-06 22:08:08,820 INFO L428 stractBuchiCegarLoop]: Abstraction has 1607 states and 2357 transitions. [2023-11-06 22:08:08,820 INFO L335 stractBuchiCegarLoop]: ======== Iteration 9 ============ [2023-11-06 22:08:08,820 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1607 states and 2357 transitions. [2023-11-06 22:08:08,831 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 1507 [2023-11-06 22:08:08,831 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-06 22:08:08,831 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-06 22:08:08,833 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-06 22:08:08,833 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-06 22:08:08,833 INFO L748 eck$LassoCheckResult]: Stem: 12571#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2; 12572#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~8#1;havoc main_~__retres1~8#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 12704#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret20#1, start_simulation_#t~ret21#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 12705#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 12236#L461 assume 1 == ~m_i~0;~m_st~0 := 0; 12237#L461-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 12765#L466-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 12910#L471-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 12331#L476-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 12332#L481-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 12497#L486-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 12347#L491-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 12348#L670 assume !(0 == ~M_E~0); 12717#L670-2 assume !(0 == ~T1_E~0); 12669#L675-1 assume !(0 == ~T2_E~0); 12670#L680-1 assume !(0 == ~T3_E~0); 12764#L685-1 assume !(0 == ~T4_E~0); 12724#L690-1 assume !(0 == ~T5_E~0); 12725#L695-1 assume !(0 == ~T6_E~0); 12800#L700-1 assume !(0 == ~E_1~0); 12789#L705-1 assume !(0 == ~E_2~0); 12790#L710-1 assume !(0 == ~E_3~0); 12668#L715-1 assume !(0 == ~E_4~0); 12599#L720-1 assume !(0 == ~E_5~0); 12600#L725-1 assume !(0 == ~E_6~0); 12648#L730-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 12693#L320 assume !(1 == ~m_pc~0); 12818#L320-2 is_master_triggered_~__retres1~0#1 := 0; 12543#L331 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 12537#is_master_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 12498#L825 assume !(0 != activate_threads_~tmp~1#1); 12499#L825-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 12503#L339 assume !(1 == ~t1_pc~0); 12504#L339-2 is_transmit1_triggered_~__retres1~1#1 := 0; 12473#L350 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 12329#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 12330#L833 assume !(0 != activate_threads_~tmp___0~0#1); 12352#L833-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 12262#L358 assume 1 == ~t2_pc~0; 12263#L359 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 12782#L369 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 12708#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 12651#L841 assume !(0 != activate_threads_~tmp___1~0#1); 12493#L841-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 12494#L377 assume !(1 == ~t3_pc~0); 12746#L377-2 is_transmit3_triggered_~__retres1~3#1 := 0; 12747#L388 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 12258#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 12259#L849 assume !(0 != activate_threads_~tmp___2~0#1); 12502#L849-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 12428#L396 assume 1 == ~t4_pc~0; 12429#L397 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 12265#L407 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 12266#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 12410#L857 assume !(0 != activate_threads_~tmp___3~0#1); 12395#L857-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 12396#L415 assume 1 == ~t5_pc~0; 12478#L416 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 12528#L426 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 12546#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 12547#L865 assume !(0 != activate_threads_~tmp___4~0#1); 12306#L865-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 12307#L434 assume !(1 == ~t6_pc~0); 12630#L434-2 is_transmit6_triggered_~__retres1~6#1 := 0; 12631#L445 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 12698#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 12699#L873 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 12516#L873-2 havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 12517#L743 assume !(1 == ~M_E~0); 12388#L743-2 assume !(1 == ~T1_E~0); 12389#L748-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 12688#L753-1 assume !(1 == ~T3_E~0); 12689#L758-1 assume 1 == ~T4_E~0;~T4_E~0 := 2; 12803#L763-1 assume !(1 == ~T5_E~0); 12858#L768-1 assume !(1 == ~T6_E~0); 12510#L773-1 assume !(1 == ~E_1~0); 12511#L778-1 assume !(1 == ~E_2~0); 12488#L783-1 assume !(1 == ~E_3~0); 12489#L788-1 assume !(1 == ~E_4~0); 12762#L793-1 assume !(1 == ~E_5~0); 12713#L798-1 assume 1 == ~E_6~0;~E_6~0 := 2; 12369#L803-1 assume { :end_inline_reset_delta_events } true; 12370#L1024-2 [2023-11-06 22:08:08,834 INFO L750 eck$LassoCheckResult]: Loop: 12370#L1024-2 assume !false; 12656#L1025 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 12244#L645-1 assume !false; 12483#L552 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 12597#L504 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 12313#L541 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 12731#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 12732#L556 assume !(0 != eval_~tmp~0#1); 12417#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 12418#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 13403#L670-3 assume 0 == ~M_E~0;~M_E~0 := 1; 13402#L670-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 13401#L675-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 12826#L680-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 12827#L685-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 13815#L690-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 13812#L695-3 assume !(0 == ~T6_E~0); 13810#L700-3 assume !(0 == ~E_1~0); 13808#L705-3 assume 0 == ~E_2~0;~E_2~0 := 1; 13806#L710-3 assume 0 == ~E_3~0;~E_3~0 := 1; 13804#L715-3 assume 0 == ~E_4~0;~E_4~0 := 1; 13802#L720-3 assume 0 == ~E_5~0;~E_5~0 := 1; 13799#L725-3 assume 0 == ~E_6~0;~E_6~0 := 1; 13797#L730-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 13795#L320-21 assume !(1 == ~m_pc~0); 13793#L320-23 is_master_triggered_~__retres1~0#1 := 0; 13791#L331-7 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 13789#is_master_triggered_returnLabel#8 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 13786#L825-21 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 13784#L825-23 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 13782#L339-21 assume 1 == ~t1_pc~0; 13779#L340-7 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 13777#L350-7 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 13775#is_transmit1_triggered_returnLabel#8 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 13773#L833-21 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 13771#L833-23 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 13769#L358-21 assume !(1 == ~t2_pc~0); 13766#L358-23 is_transmit2_triggered_~__retres1~2#1 := 0; 13764#L369-7 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 13763#is_transmit2_triggered_returnLabel#8 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 13762#L841-21 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 13761#L841-23 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 13760#L377-21 assume 1 == ~t3_pc~0; 13758#L378-7 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 13757#L388-7 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 13756#is_transmit3_triggered_returnLabel#8 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 13755#L849-21 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 13754#L849-23 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 13753#L396-21 assume !(1 == ~t4_pc~0); 13751#L396-23 is_transmit4_triggered_~__retres1~4#1 := 0; 13750#L407-7 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 13749#is_transmit4_triggered_returnLabel#8 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 13748#L857-21 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 13747#L857-23 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 13746#L415-21 assume 1 == ~t5_pc~0; 13744#L416-7 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 13743#L426-7 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 13742#is_transmit5_triggered_returnLabel#8 activate_threads_#t~ret17#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 13741#L865-21 assume !(0 != activate_threads_~tmp___4~0#1); 13740#L865-23 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 13739#L434-21 assume 1 == ~t6_pc~0; 13737#L435-7 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 13736#L445-7 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 13735#is_transmit6_triggered_returnLabel#8 activate_threads_#t~ret18#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 13734#L873-21 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 13733#L873-23 havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 13732#L743-3 assume 1 == ~M_E~0;~M_E~0 := 2; 13731#L743-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 13730#L748-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 12909#L753-3 assume !(1 == ~T3_E~0); 13729#L758-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 13728#L763-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 13727#L768-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 13726#L773-3 assume 1 == ~E_1~0;~E_1~0 := 2; 12863#L778-3 assume 1 == ~E_2~0;~E_2~0 := 2; 13725#L783-3 assume 1 == ~E_3~0;~E_3~0 := 2; 13723#L788-3 assume 1 == ~E_4~0;~E_4~0 := 2; 13722#L793-3 assume !(1 == ~E_5~0); 13720#L798-3 assume 1 == ~E_6~0;~E_6~0 := 2; 13718#L803-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 13716#L504-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 13708#L541-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 13707#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret20#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret20#1;havoc start_simulation_#t~ret20#1; 13705#L1043 assume !(0 == start_simulation_~tmp~3#1); 13703#L1043-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret19#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 13702#L504-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 13695#L541-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 13694#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret19#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret19#1;havoc stop_simulation_#t~ret19#1; 13493#L998 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 13450#L1005 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 12851#stop_simulation_returnLabel#1 start_simulation_#t~ret21#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret19#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret21#1;havoc start_simulation_#t~ret21#1; 12634#L1056 assume !(0 != start_simulation_~tmp___0~1#1); 12370#L1024-2 [2023-11-06 22:08:08,834 INFO L145 PredicateUnifier]: Initialized classic predicate unifier [2023-11-06 22:08:08,835 INFO L85 PathProgramCache]: Analyzing trace with hash -1227190400, now seen corresponding path program 1 times [2023-11-06 22:08:08,835 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-06 22:08:08,835 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [792792077] [2023-11-06 22:08:08,835 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-06 22:08:08,835 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-06 22:08:08,852 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-06 22:08:08,915 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-06 22:08:08,915 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-06 22:08:08,915 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [792792077] [2023-11-06 22:08:08,915 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [792792077] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-06 22:08:08,915 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-06 22:08:08,916 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-06 22:08:08,916 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1086558480] [2023-11-06 22:08:08,916 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-06 22:08:08,916 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-06 22:08:08,917 INFO L145 PredicateUnifier]: Initialized classic predicate unifier [2023-11-06 22:08:08,917 INFO L85 PathProgramCache]: Analyzing trace with hash 93538728, now seen corresponding path program 2 times [2023-11-06 22:08:08,917 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-06 22:08:08,917 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1399557644] [2023-11-06 22:08:08,917 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-06 22:08:08,918 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-06 22:08:08,940 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-06 22:08:08,972 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-06 22:08:08,972 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-06 22:08:08,972 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1399557644] [2023-11-06 22:08:08,972 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1399557644] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-06 22:08:08,972 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-06 22:08:08,973 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-06 22:08:08,973 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [822339200] [2023-11-06 22:08:08,973 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-06 22:08:08,973 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-06 22:08:08,973 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-06 22:08:08,974 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2023-11-06 22:08:08,974 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2023-11-06 22:08:08,974 INFO L87 Difference]: Start difference. First operand 1607 states and 2357 transitions. cyclomatic complexity: 753 Second operand has 4 states, 4 states have (on average 20.5) internal successors, (82), 3 states have internal predecessors, (82), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-06 22:08:09,191 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-06 22:08:09,192 INFO L93 Difference]: Finished difference Result 3942 states and 5717 transitions. [2023-11-06 22:08:09,192 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 3942 states and 5717 transitions. [2023-11-06 22:08:09,270 INFO L131 ngComponentsAnalysis]: Automaton has 5 accepting balls. 3781 [2023-11-06 22:08:09,302 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 3942 states to 3942 states and 5717 transitions. [2023-11-06 22:08:09,302 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 3942 [2023-11-06 22:08:09,306 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 3942 [2023-11-06 22:08:09,307 INFO L73 IsDeterministic]: Start isDeterministic. Operand 3942 states and 5717 transitions. [2023-11-06 22:08:09,312 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-06 22:08:09,312 INFO L218 hiAutomatonCegarLoop]: Abstraction has 3942 states and 5717 transitions. [2023-11-06 22:08:09,317 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3942 states and 5717 transitions. [2023-11-06 22:08:09,368 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3942 to 2935. [2023-11-06 22:08:09,374 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2935 states, 2935 states have (on average 1.4579216354344122) internal successors, (4279), 2934 states have internal predecessors, (4279), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-06 22:08:09,386 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2935 states to 2935 states and 4279 transitions. [2023-11-06 22:08:09,386 INFO L240 hiAutomatonCegarLoop]: Abstraction has 2935 states and 4279 transitions. [2023-11-06 22:08:09,386 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2023-11-06 22:08:09,388 INFO L428 stractBuchiCegarLoop]: Abstraction has 2935 states and 4279 transitions. [2023-11-06 22:08:09,388 INFO L335 stractBuchiCegarLoop]: ======== Iteration 10 ============ [2023-11-06 22:08:09,388 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2935 states and 4279 transitions. [2023-11-06 22:08:09,402 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 2835 [2023-11-06 22:08:09,402 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-06 22:08:09,402 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-06 22:08:09,404 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-06 22:08:09,404 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-06 22:08:09,404 INFO L748 eck$LassoCheckResult]: Stem: 18141#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2; 18142#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~8#1;havoc main_~__retres1~8#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 18268#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret20#1, start_simulation_#t~ret21#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 18269#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 17795#L461 assume 1 == ~m_i~0;~m_st~0 := 0; 17796#L461-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 18336#L466-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 18472#L471-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 17890#L476-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 17891#L481-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 18055#L486-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 17905#L491-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 17906#L670 assume !(0 == ~M_E~0); 18285#L670-2 assume !(0 == ~T1_E~0); 18233#L675-1 assume !(0 == ~T2_E~0); 18234#L680-1 assume !(0 == ~T3_E~0); 18334#L685-1 assume !(0 == ~T4_E~0); 18291#L690-1 assume !(0 == ~T5_E~0); 18292#L695-1 assume !(0 == ~T6_E~0); 18375#L700-1 assume !(0 == ~E_1~0); 18363#L705-1 assume !(0 == ~E_2~0); 18364#L710-1 assume !(0 == ~E_3~0); 18232#L715-1 assume !(0 == ~E_4~0); 18165#L720-1 assume !(0 == ~E_5~0); 18166#L725-1 assume !(0 == ~E_6~0); 18211#L730-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 18257#L320 assume !(1 == ~m_pc~0); 18394#L320-2 is_master_triggered_~__retres1~0#1 := 0; 18104#L331 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 18098#is_master_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 18056#L825 assume !(0 != activate_threads_~tmp~1#1); 18057#L825-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 18064#L339 assume !(1 == ~t1_pc~0); 18065#L339-2 is_transmit1_triggered_~__retres1~1#1 := 0; 18031#L350 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 17886#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 17887#L833 assume !(0 != activate_threads_~tmp___0~0#1); 17909#L833-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 17821#L358 assume !(1 == ~t2_pc~0); 17822#L358-2 is_transmit2_triggered_~__retres1~2#1 := 0; 18354#L369 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 18271#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 18215#L841 assume !(0 != activate_threads_~tmp___1~0#1); 18051#L841-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 18052#L377 assume !(1 == ~t3_pc~0); 18314#L377-2 is_transmit3_triggered_~__retres1~3#1 := 0; 18315#L388 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 17817#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 17818#L849 assume !(0 != activate_threads_~tmp___2~0#1); 18060#L849-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 17989#L396 assume 1 == ~t4_pc~0; 17990#L397 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 17823#L407 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 17824#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 17970#L857 assume !(0 != activate_threads_~tmp___3~0#1); 17954#L857-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 17955#L415 assume 1 == ~t5_pc~0; 18038#L416 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 18093#L426 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 18108#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 18109#L865 assume !(0 != activate_threads_~tmp___4~0#1); 17863#L865-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 17864#L434 assume !(1 == ~t6_pc~0); 18194#L434-2 is_transmit6_triggered_~__retres1~6#1 := 0; 18195#L445 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 18262#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 18263#L873 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 18077#L873-2 havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 18078#L743 assume !(1 == ~M_E~0); 17947#L743-2 assume !(1 == ~T1_E~0); 17948#L748-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 18443#L753-1 assume !(1 == ~T3_E~0); 18378#L758-1 assume 1 == ~T4_E~0;~T4_E~0 := 2; 18379#L763-1 assume !(1 == ~T5_E~0); 18470#L768-1 assume !(1 == ~T6_E~0); 18471#L773-1 assume !(1 == ~E_1~0); 18075#L778-1 assume !(1 == ~E_2~0); 18498#L783-1 assume !(1 == ~E_3~0); 18489#L788-1 assume !(1 == ~E_4~0); 18490#L793-1 assume !(1 == ~E_5~0); 18276#L798-1 assume 1 == ~E_6~0;~E_6~0 := 2; 18277#L803-1 assume { :end_inline_reset_delta_events } true; 20348#L1024-2 [2023-11-06 22:08:09,404 INFO L750 eck$LassoCheckResult]: Loop: 20348#L1024-2 assume !false; 20345#L1025 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 20340#L645-1 assume !false; 20338#L552 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 20336#L504 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 20327#L541 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 20323#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 20318#L556 assume !(0 != eval_~tmp~0#1); 20319#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 20727#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 20725#L670-3 assume 0 == ~M_E~0;~M_E~0 := 1; 20723#L670-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 20721#L675-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 20719#L680-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 20717#L685-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 20714#L690-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 20712#L695-3 assume !(0 == ~T6_E~0); 20710#L700-3 assume !(0 == ~E_1~0); 20708#L705-3 assume 0 == ~E_2~0;~E_2~0 := 1; 20706#L710-3 assume 0 == ~E_3~0;~E_3~0 := 1; 20704#L715-3 assume 0 == ~E_4~0;~E_4~0 := 1; 20703#L720-3 assume 0 == ~E_5~0;~E_5~0 := 1; 20701#L725-3 assume 0 == ~E_6~0;~E_6~0 := 1; 20699#L730-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 20697#L320-21 assume !(1 == ~m_pc~0); 20695#L320-23 is_master_triggered_~__retres1~0#1 := 0; 20693#L331-7 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 20690#is_master_triggered_returnLabel#8 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 20688#L825-21 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 20687#L825-23 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 20686#L339-21 assume 1 == ~t1_pc~0; 20684#L340-7 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 20683#L350-7 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 20682#is_transmit1_triggered_returnLabel#8 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 20681#L833-21 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 20680#L833-23 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 20679#L358-21 assume !(1 == ~t2_pc~0); 19412#L358-23 is_transmit2_triggered_~__retres1~2#1 := 0; 20678#L369-7 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 20677#is_transmit2_triggered_returnLabel#8 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 20676#L841-21 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 20675#L841-23 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 20674#L377-21 assume 1 == ~t3_pc~0; 20672#L378-7 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 20671#L388-7 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 20670#is_transmit3_triggered_returnLabel#8 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 20669#L849-21 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 20668#L849-23 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 20667#L396-21 assume !(1 == ~t4_pc~0); 20665#L396-23 is_transmit4_triggered_~__retres1~4#1 := 0; 20664#L407-7 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 20663#is_transmit4_triggered_returnLabel#8 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 20662#L857-21 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 18280#L857-23 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 18099#L415-21 assume 1 == ~t5_pc~0; 18100#L416-7 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 18073#L426-7 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 18252#is_transmit5_triggered_returnLabel#8 activate_threads_#t~ret17#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 18199#L865-21 assume !(0 != activate_threads_~tmp___4~0#1); 18168#L865-23 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 18169#L434-21 assume 1 == ~t6_pc~0; 18361#L435-7 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 20653#L445-7 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 20652#is_transmit6_triggered_returnLabel#8 activate_threads_#t~ret18#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 20651#L873-21 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 20650#L873-23 havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 20649#L743-3 assume 1 == ~M_E~0;~M_E~0 := 2; 18444#L743-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 18445#L748-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 18239#L753-3 assume !(1 == ~T3_E~0); 18240#L758-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 20646#L763-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 20645#L768-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 20644#L773-3 assume 1 == ~E_1~0;~E_1~0 := 2; 18431#L778-3 assume 1 == ~E_2~0;~E_2~0 := 2; 20643#L783-3 assume 1 == ~E_3~0;~E_3~0 := 2; 20642#L788-3 assume 1 == ~E_4~0;~E_4~0 := 2; 18456#L793-3 assume !(1 == ~E_5~0); 18457#L798-3 assume 1 == ~E_6~0;~E_6~0 := 2; 18281#L803-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 18282#L504-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 20601#L541-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 20599#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret20#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret20#1;havoc start_simulation_#t~ret20#1; 20597#L1043 assume !(0 == start_simulation_~tmp~3#1); 20595#L1043-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret19#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 20452#L504-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 20442#L541-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 20437#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret19#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret19#1;havoc stop_simulation_#t~ret19#1; 20433#L998 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 20428#L1005 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 20423#stop_simulation_returnLabel#1 start_simulation_#t~ret21#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret19#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret21#1;havoc start_simulation_#t~ret21#1; 20422#L1056 assume !(0 != start_simulation_~tmp___0~1#1); 20348#L1024-2 [2023-11-06 22:08:09,405 INFO L145 PredicateUnifier]: Initialized classic predicate unifier [2023-11-06 22:08:09,405 INFO L85 PathProgramCache]: Analyzing trace with hash 1792674207, now seen corresponding path program 1 times [2023-11-06 22:08:09,405 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-06 22:08:09,405 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1718051496] [2023-11-06 22:08:09,405 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-06 22:08:09,406 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-06 22:08:09,420 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-06 22:08:09,461 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-06 22:08:09,461 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-06 22:08:09,461 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1718051496] [2023-11-06 22:08:09,461 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1718051496] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-06 22:08:09,461 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-06 22:08:09,462 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2023-11-06 22:08:09,462 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [828642959] [2023-11-06 22:08:09,462 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-06 22:08:09,463 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-06 22:08:09,464 INFO L145 PredicateUnifier]: Initialized classic predicate unifier [2023-11-06 22:08:09,464 INFO L85 PathProgramCache]: Analyzing trace with hash 93538728, now seen corresponding path program 3 times [2023-11-06 22:08:09,464 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-06 22:08:09,464 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1614724944] [2023-11-06 22:08:09,464 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-06 22:08:09,464 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-06 22:08:09,476 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-06 22:08:09,508 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-06 22:08:09,509 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-06 22:08:09,509 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1614724944] [2023-11-06 22:08:09,509 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1614724944] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-06 22:08:09,509 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-06 22:08:09,509 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-06 22:08:09,509 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1105932385] [2023-11-06 22:08:09,510 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-06 22:08:09,510 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-06 22:08:09,510 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-06 22:08:09,510 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-06 22:08:09,511 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-06 22:08:09,511 INFO L87 Difference]: Start difference. First operand 2935 states and 4279 transitions. cyclomatic complexity: 1347 Second operand has 3 states, 3 states have (on average 27.333333333333332) internal successors, (82), 2 states have internal predecessors, (82), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-06 22:08:09,605 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-06 22:08:09,605 INFO L93 Difference]: Finished difference Result 5431 states and 7877 transitions. [2023-11-06 22:08:09,605 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 5431 states and 7877 transitions. [2023-11-06 22:08:09,641 INFO L131 ngComponentsAnalysis]: Automaton has 6 accepting balls. 5318 [2023-11-06 22:08:09,683 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 5431 states to 5431 states and 7877 transitions. [2023-11-06 22:08:09,683 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 5431 [2023-11-06 22:08:09,689 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 5431 [2023-11-06 22:08:09,689 INFO L73 IsDeterministic]: Start isDeterministic. Operand 5431 states and 7877 transitions. [2023-11-06 22:08:09,697 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-06 22:08:09,697 INFO L218 hiAutomatonCegarLoop]: Abstraction has 5431 states and 7877 transitions. [2023-11-06 22:08:09,703 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 5431 states and 7877 transitions. [2023-11-06 22:08:09,794 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 5431 to 5419. [2023-11-06 22:08:09,805 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 5419 states, 5419 states have (on average 1.4513747923971212) internal successors, (7865), 5418 states have internal predecessors, (7865), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-06 22:08:09,921 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 5419 states to 5419 states and 7865 transitions. [2023-11-06 22:08:09,922 INFO L240 hiAutomatonCegarLoop]: Abstraction has 5419 states and 7865 transitions. [2023-11-06 22:08:09,923 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-06 22:08:09,923 INFO L428 stractBuchiCegarLoop]: Abstraction has 5419 states and 7865 transitions. [2023-11-06 22:08:09,923 INFO L335 stractBuchiCegarLoop]: ======== Iteration 11 ============ [2023-11-06 22:08:09,924 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 5419 states and 7865 transitions. [2023-11-06 22:08:09,956 INFO L131 ngComponentsAnalysis]: Automaton has 6 accepting balls. 5306 [2023-11-06 22:08:09,956 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-06 22:08:09,956 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-06 22:08:09,958 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-06 22:08:09,958 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-06 22:08:09,959 INFO L748 eck$LassoCheckResult]: Stem: 26508#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2; 26509#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~8#1;havoc main_~__retres1~8#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 26644#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret20#1, start_simulation_#t~ret21#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 26645#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 26168#L461 assume 1 == ~m_i~0;~m_st~0 := 0; 26169#L461-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 26713#L466-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 26880#L471-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 26264#L476-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 26265#L481-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 26427#L486-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 26279#L491-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 26280#L670 assume !(0 == ~M_E~0); 26657#L670-2 assume !(0 == ~T1_E~0); 26607#L675-1 assume !(0 == ~T2_E~0); 26608#L680-1 assume !(0 == ~T3_E~0); 26711#L685-1 assume !(0 == ~T4_E~0); 26665#L690-1 assume !(0 == ~T5_E~0); 26666#L695-1 assume !(0 == ~T6_E~0); 26757#L700-1 assume !(0 == ~E_1~0); 26744#L705-1 assume !(0 == ~E_2~0); 26745#L710-1 assume !(0 == ~E_3~0); 26606#L715-1 assume !(0 == ~E_4~0); 26536#L720-1 assume !(0 == ~E_5~0); 26537#L725-1 assume !(0 == ~E_6~0); 26585#L730-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 26632#L320 assume !(1 == ~m_pc~0); 26774#L320-2 is_master_triggered_~__retres1~0#1 := 0; 26475#L331 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 26469#is_master_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 26428#L825 assume !(0 != activate_threads_~tmp~1#1); 26429#L825-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 26434#L339 assume !(1 == ~t1_pc~0); 26435#L339-2 is_transmit1_triggered_~__retres1~1#1 := 0; 26402#L350 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 26260#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 26261#L833 assume !(0 != activate_threads_~tmp___0~0#1); 26283#L833-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 26194#L358 assume !(1 == ~t2_pc~0); 26195#L358-2 is_transmit2_triggered_~__retres1~2#1 := 0; 26736#L369 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 26647#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 26588#L841 assume !(0 != activate_threads_~tmp___1~0#1); 26423#L841-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 26424#L377 assume !(1 == ~t3_pc~0); 26690#L377-2 is_transmit3_triggered_~__retres1~3#1 := 0; 26691#L388 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 26190#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 26191#L849 assume !(0 != activate_threads_~tmp___2~0#1); 26432#L849-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 26361#L396 assume !(1 == ~t4_pc~0); 26362#L396-2 is_transmit4_triggered_~__retres1~4#1 := 0; 26196#L407 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 26197#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 26344#L857 assume !(0 != activate_threads_~tmp___3~0#1); 26328#L857-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 26329#L415 assume 1 == ~t5_pc~0; 26409#L416 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 26463#L426 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 26479#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 26480#L865 assume !(0 != activate_threads_~tmp___4~0#1); 26237#L865-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 26238#L434 assume !(1 == ~t6_pc~0); 26567#L434-2 is_transmit6_triggered_~__retres1~6#1 := 0; 26568#L445 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 26638#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 26639#L873 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 26447#L873-2 havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 26448#L743 assume !(1 == ~M_E~0); 26320#L743-2 assume !(1 == ~T1_E~0); 26321#L748-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 26842#L753-1 assume !(1 == ~T3_E~0); 30814#L758-1 assume 1 == ~T4_E~0;~T4_E~0 := 2; 30813#L763-1 assume !(1 == ~T5_E~0); 30812#L768-1 assume !(1 == ~T6_E~0); 30811#L773-1 assume !(1 == ~E_1~0); 26443#L778-1 assume !(1 == ~E_2~0); 30810#L783-1 assume !(1 == ~E_3~0); 30809#L788-1 assume !(1 == ~E_4~0); 30808#L793-1 assume !(1 == ~E_5~0); 30807#L798-1 assume 1 == ~E_6~0;~E_6~0 := 2; 30806#L803-1 assume { :end_inline_reset_delta_events } true; 26593#L1024-2 [2023-11-06 22:08:09,959 INFO L750 eck$LassoCheckResult]: Loop: 26593#L1024-2 assume !false; 26594#L1025 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 26176#L645-1 assume !false; 26532#L552 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 26533#L504 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 30716#L541 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 30715#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 30713#L556 assume !(0 != eval_~tmp~0#1); 30714#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 31445#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 31443#L670-3 assume 0 == ~M_E~0;~M_E~0 := 1; 31441#L670-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 31437#L675-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 31432#L680-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 31429#L685-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 31427#L690-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 31425#L695-3 assume !(0 == ~T6_E~0); 31423#L700-3 assume !(0 == ~E_1~0); 31419#L705-3 assume 0 == ~E_2~0;~E_2~0 := 1; 31417#L710-3 assume 0 == ~E_3~0;~E_3~0 := 1; 31413#L715-3 assume 0 == ~E_4~0;~E_4~0 := 1; 31410#L720-3 assume 0 == ~E_5~0;~E_5~0 := 1; 31405#L725-3 assume 0 == ~E_6~0;~E_6~0 := 1; 31402#L730-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 31395#L320-21 assume !(1 == ~m_pc~0); 31394#L320-23 is_master_triggered_~__retres1~0#1 := 0; 31248#L331-7 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 31247#is_master_triggered_returnLabel#8 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 31246#L825-21 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 31245#L825-23 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 31244#L339-21 assume 1 == ~t1_pc~0; 31242#L340-7 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 31241#L350-7 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 31240#is_transmit1_triggered_returnLabel#8 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 31239#L833-21 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 31238#L833-23 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 31237#L358-21 assume !(1 == ~t2_pc~0); 31132#L358-23 is_transmit2_triggered_~__retres1~2#1 := 0; 31236#L369-7 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 31235#is_transmit2_triggered_returnLabel#8 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 31234#L841-21 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 31233#L841-23 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 31232#L377-21 assume 1 == ~t3_pc~0; 31230#L378-7 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 31229#L388-7 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 31228#is_transmit3_triggered_returnLabel#8 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 31227#L849-21 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 31226#L849-23 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 31225#L396-21 assume !(1 == ~t4_pc~0); 31224#L396-23 is_transmit4_triggered_~__retres1~4#1 := 0; 31223#L407-7 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 31222#is_transmit4_triggered_returnLabel#8 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 31221#L857-21 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 31220#L857-23 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 31219#L415-21 assume 1 == ~t5_pc~0; 31217#L416-7 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 31216#L426-7 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 31215#is_transmit5_triggered_returnLabel#8 activate_threads_#t~ret17#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 31214#L865-21 assume !(0 != activate_threads_~tmp___4~0#1); 31213#L865-23 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 31212#L434-21 assume 1 == ~t6_pc~0; 31210#L435-7 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 31209#L445-7 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 31208#is_transmit6_triggered_returnLabel#8 activate_threads_#t~ret18#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 31207#L873-21 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 31206#L873-23 havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 31205#L743-3 assume 1 == ~M_E~0;~M_E~0 := 2; 31204#L743-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 31203#L748-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 29709#L753-3 assume !(1 == ~T3_E~0); 31202#L758-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 31201#L763-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 31200#L768-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 31199#L773-3 assume 1 == ~E_1~0;~E_1~0 := 2; 29686#L778-3 assume 1 == ~E_2~0;~E_2~0 := 2; 31198#L783-3 assume 1 == ~E_3~0;~E_3~0 := 2; 31197#L788-3 assume 1 == ~E_4~0;~E_4~0 := 2; 31196#L793-3 assume !(1 == ~E_5~0); 31195#L798-3 assume 1 == ~E_6~0;~E_6~0 := 2; 31194#L803-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 29677#L504-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 29671#L541-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 29666#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret20#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret20#1;havoc start_simulation_#t~ret20#1; 29667#L1043 assume !(0 == start_simulation_~tmp~3#1); 26791#L1043-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret19#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 26792#L504-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 30819#L541-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 30818#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret19#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret19#1;havoc stop_simulation_#t~ret19#1; 30817#L998 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 30816#L1005 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 30815#stop_simulation_returnLabel#1 start_simulation_#t~ret21#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret19#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret21#1;havoc start_simulation_#t~ret21#1; 30805#L1056 assume !(0 != start_simulation_~tmp___0~1#1); 26593#L1024-2 [2023-11-06 22:08:09,960 INFO L145 PredicateUnifier]: Initialized classic predicate unifier [2023-11-06 22:08:09,960 INFO L85 PathProgramCache]: Analyzing trace with hash -1583318466, now seen corresponding path program 1 times [2023-11-06 22:08:09,960 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-06 22:08:09,960 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [230809810] [2023-11-06 22:08:09,961 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-06 22:08:09,961 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-06 22:08:09,975 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-06 22:08:10,022 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-06 22:08:10,022 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-06 22:08:10,022 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [230809810] [2023-11-06 22:08:10,023 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [230809810] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-06 22:08:10,023 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-06 22:08:10,023 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2023-11-06 22:08:10,023 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2124315777] [2023-11-06 22:08:10,023 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-06 22:08:10,024 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-06 22:08:10,024 INFO L145 PredicateUnifier]: Initialized classic predicate unifier [2023-11-06 22:08:10,024 INFO L85 PathProgramCache]: Analyzing trace with hash 93538728, now seen corresponding path program 4 times [2023-11-06 22:08:10,024 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-06 22:08:10,025 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [34240451] [2023-11-06 22:08:10,025 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-06 22:08:10,025 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-06 22:08:10,040 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-06 22:08:10,077 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-06 22:08:10,078 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-06 22:08:10,078 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [34240451] [2023-11-06 22:08:10,078 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [34240451] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-06 22:08:10,078 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-06 22:08:10,078 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-06 22:08:10,078 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1421984670] [2023-11-06 22:08:10,079 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-06 22:08:10,079 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-06 22:08:10,079 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-06 22:08:10,080 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-06 22:08:10,080 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-06 22:08:10,080 INFO L87 Difference]: Start difference. First operand 5419 states and 7865 transitions. cyclomatic complexity: 2452 Second operand has 3 states, 3 states have (on average 27.333333333333332) internal successors, (82), 2 states have internal predecessors, (82), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-06 22:08:10,206 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-06 22:08:10,206 INFO L93 Difference]: Finished difference Result 10072 states and 14560 transitions. [2023-11-06 22:08:10,206 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 10072 states and 14560 transitions. [2023-11-06 22:08:10,279 INFO L131 ngComponentsAnalysis]: Automaton has 12 accepting balls. 9920 [2023-11-06 22:08:10,344 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 10072 states to 10072 states and 14560 transitions. [2023-11-06 22:08:10,344 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 10072 [2023-11-06 22:08:10,357 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 10072 [2023-11-06 22:08:10,357 INFO L73 IsDeterministic]: Start isDeterministic. Operand 10072 states and 14560 transitions. [2023-11-06 22:08:10,371 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-06 22:08:10,371 INFO L218 hiAutomatonCegarLoop]: Abstraction has 10072 states and 14560 transitions. [2023-11-06 22:08:10,384 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 10072 states and 14560 transitions. [2023-11-06 22:08:10,547 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 10072 to 10048. [2023-11-06 22:08:10,568 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 10048 states, 10048 states have (on average 1.446656050955414) internal successors, (14536), 10047 states have internal predecessors, (14536), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-06 22:08:10,597 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 10048 states to 10048 states and 14536 transitions. [2023-11-06 22:08:10,597 INFO L240 hiAutomatonCegarLoop]: Abstraction has 10048 states and 14536 transitions. [2023-11-06 22:08:10,598 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-06 22:08:10,598 INFO L428 stractBuchiCegarLoop]: Abstraction has 10048 states and 14536 transitions. [2023-11-06 22:08:10,598 INFO L335 stractBuchiCegarLoop]: ======== Iteration 12 ============ [2023-11-06 22:08:10,599 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 10048 states and 14536 transitions. [2023-11-06 22:08:10,642 INFO L131 ngComponentsAnalysis]: Automaton has 12 accepting balls. 9896 [2023-11-06 22:08:10,642 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-06 22:08:10,642 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-06 22:08:10,644 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-06 22:08:10,644 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-06 22:08:10,645 INFO L748 eck$LassoCheckResult]: Stem: 42006#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2; 42007#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~8#1;havoc main_~__retres1~8#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 42136#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret20#1, start_simulation_#t~ret21#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 42137#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 41666#L461 assume 1 == ~m_i~0;~m_st~0 := 0; 41667#L461-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 42204#L466-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 42365#L471-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 41760#L476-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 41761#L481-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 41923#L486-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 41775#L491-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 41776#L670 assume !(0 == ~M_E~0); 42151#L670-2 assume !(0 == ~T1_E~0); 42100#L675-1 assume !(0 == ~T2_E~0); 42101#L680-1 assume !(0 == ~T3_E~0); 42202#L685-1 assume !(0 == ~T4_E~0); 42158#L690-1 assume !(0 == ~T5_E~0); 42159#L695-1 assume !(0 == ~T6_E~0); 42247#L700-1 assume !(0 == ~E_1~0); 42232#L705-1 assume !(0 == ~E_2~0); 42233#L710-1 assume !(0 == ~E_3~0); 42099#L715-1 assume !(0 == ~E_4~0); 42030#L720-1 assume !(0 == ~E_5~0); 42031#L725-1 assume !(0 == ~E_6~0); 42079#L730-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 42125#L320 assume !(1 == ~m_pc~0); 42271#L320-2 is_master_triggered_~__retres1~0#1 := 0; 41971#L331 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 41964#is_master_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 41924#L825 assume !(0 != activate_threads_~tmp~1#1); 41925#L825-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 41934#L339 assume !(1 == ~t1_pc~0); 41935#L339-2 is_transmit1_triggered_~__retres1~1#1 := 0; 41900#L350 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 41756#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 41757#L833 assume !(0 != activate_threads_~tmp___0~0#1); 41779#L833-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 41692#L358 assume !(1 == ~t2_pc~0); 41693#L358-2 is_transmit2_triggered_~__retres1~2#1 := 0; 42223#L369 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 42140#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 42082#L841 assume !(0 != activate_threads_~tmp___1~0#1); 41919#L841-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 41920#L377 assume !(1 == ~t3_pc~0); 42183#L377-2 is_transmit3_triggered_~__retres1~3#1 := 0; 42184#L388 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 41690#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 41691#L849 assume !(0 != activate_threads_~tmp___2~0#1); 41927#L849-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 41859#L396 assume !(1 == ~t4_pc~0); 41860#L396-2 is_transmit4_triggered_~__retres1~4#1 := 0; 41694#L407 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 41695#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 41839#L857 assume !(0 != activate_threads_~tmp___3~0#1); 41823#L857-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 41824#L415 assume !(1 == ~t5_pc~0); 41907#L415-2 is_transmit5_triggered_~__retres1~5#1 := 0; 41959#L426 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 41978#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 41979#L865 assume !(0 != activate_threads_~tmp___4~0#1); 41733#L865-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 41734#L434 assume !(1 == ~t6_pc~0); 42061#L434-2 is_transmit6_triggered_~__retres1~6#1 := 0; 42062#L445 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 42130#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 42131#L873 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 41943#L873-2 havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 41944#L743 assume !(1 == ~M_E~0); 41815#L743-2 assume !(1 == ~T1_E~0); 41816#L748-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 42119#L753-1 assume !(1 == ~T3_E~0); 42120#L758-1 assume 1 == ~T4_E~0;~T4_E~0 := 2; 42250#L763-1 assume !(1 == ~T5_E~0); 42310#L768-1 assume !(1 == ~T6_E~0); 41941#L773-1 assume !(1 == ~E_1~0); 41942#L778-1 assume !(1 == ~E_2~0); 41914#L783-1 assume !(1 == ~E_3~0); 41915#L788-1 assume !(1 == ~E_4~0); 42200#L793-1 assume !(1 == ~E_5~0); 42145#L798-1 assume 1 == ~E_6~0;~E_6~0 := 2; 41798#L803-1 assume { :end_inline_reset_delta_events } true; 41799#L1024-2 [2023-11-06 22:08:10,645 INFO L750 eck$LassoCheckResult]: Loop: 41799#L1024-2 assume !false; 47464#L1025 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 47459#L645-1 assume !false; 47457#L552 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 47455#L504 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 47444#L541 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 47441#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 42388#L556 assume !(0 != eval_~tmp~0#1); 42389#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 50789#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 50787#L670-3 assume 0 == ~M_E~0;~M_E~0 := 1; 50785#L670-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 50783#L675-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 50781#L680-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 50779#L685-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 50777#L690-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 50774#L695-3 assume !(0 == ~T6_E~0); 50772#L700-3 assume !(0 == ~E_1~0); 50770#L705-3 assume 0 == ~E_2~0;~E_2~0 := 1; 50768#L710-3 assume 0 == ~E_3~0;~E_3~0 := 1; 50766#L715-3 assume 0 == ~E_4~0;~E_4~0 := 1; 50764#L720-3 assume 0 == ~E_5~0;~E_5~0 := 1; 50763#L725-3 assume 0 == ~E_6~0;~E_6~0 := 1; 50761#L730-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 50759#L320-21 assume !(1 == ~m_pc~0); 50757#L320-23 is_master_triggered_~__retres1~0#1 := 0; 50755#L331-7 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 50753#is_master_triggered_returnLabel#8 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 50750#L825-21 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 50748#L825-23 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 50746#L339-21 assume 1 == ~t1_pc~0; 50743#L340-7 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 50741#L350-7 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 50739#is_transmit1_triggered_returnLabel#8 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 50738#L833-21 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 50710#L833-23 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 49621#L358-21 assume !(1 == ~t2_pc~0); 49619#L358-23 is_transmit2_triggered_~__retres1~2#1 := 0; 49617#L369-7 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 49615#is_transmit2_triggered_returnLabel#8 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 49613#L841-21 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 49611#L841-23 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 49603#L377-21 assume 1 == ~t3_pc~0; 49600#L378-7 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 49598#L388-7 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 49594#is_transmit3_triggered_returnLabel#8 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 49592#L849-21 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 49584#L849-23 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 49582#L396-21 assume !(1 == ~t4_pc~0); 49580#L396-23 is_transmit4_triggered_~__retres1~4#1 := 0; 49578#L407-7 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 49576#is_transmit4_triggered_returnLabel#8 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 49574#L857-21 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 49572#L857-23 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 49570#L415-21 assume !(1 == ~t5_pc~0); 49565#L415-23 is_transmit5_triggered_~__retres1~5#1 := 0; 49563#L426-7 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 49561#is_transmit5_triggered_returnLabel#8 activate_threads_#t~ret17#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 49553#L865-21 assume !(0 != activate_threads_~tmp___4~0#1); 49551#L865-23 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 49549#L434-21 assume 1 == ~t6_pc~0; 49545#L435-7 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 49544#L445-7 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 49543#is_transmit6_triggered_returnLabel#8 activate_threads_#t~ret18#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 49542#L873-21 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 49541#L873-23 havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 49537#L743-3 assume 1 == ~M_E~0;~M_E~0 := 2; 49533#L743-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 49530#L748-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 49234#L753-3 assume !(1 == ~T3_E~0); 49527#L758-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 49526#L763-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 47575#L768-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 47573#L773-3 assume 1 == ~E_1~0;~E_1~0 := 2; 47571#L778-3 assume 1 == ~E_2~0;~E_2~0 := 2; 47569#L783-3 assume 1 == ~E_3~0;~E_3~0 := 2; 47567#L788-3 assume 1 == ~E_4~0;~E_4~0 := 2; 47565#L793-3 assume !(1 == ~E_5~0); 47563#L798-3 assume 1 == ~E_6~0;~E_6~0 := 2; 47561#L803-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 47559#L504-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 47551#L541-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 47549#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret20#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret20#1;havoc start_simulation_#t~ret20#1; 47546#L1043 assume !(0 == start_simulation_~tmp~3#1); 47516#L1043-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret19#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 47510#L504-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 47502#L541-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 47500#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret19#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret19#1;havoc stop_simulation_#t~ret19#1; 47496#L998 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 47492#L1005 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 47487#stop_simulation_returnLabel#1 start_simulation_#t~ret21#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret19#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret21#1;havoc start_simulation_#t~ret21#1; 47481#L1056 assume !(0 != start_simulation_~tmp___0~1#1); 41799#L1024-2 [2023-11-06 22:08:10,646 INFO L145 PredicateUnifier]: Initialized classic predicate unifier [2023-11-06 22:08:10,646 INFO L85 PathProgramCache]: Analyzing trace with hash -944533987, now seen corresponding path program 1 times [2023-11-06 22:08:10,646 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-06 22:08:10,648 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1659741464] [2023-11-06 22:08:10,648 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-06 22:08:10,649 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-06 22:08:10,732 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-06 22:08:10,794 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-06 22:08:10,794 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-06 22:08:10,794 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1659741464] [2023-11-06 22:08:10,795 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1659741464] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-06 22:08:10,795 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-06 22:08:10,795 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2023-11-06 22:08:10,796 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1788221123] [2023-11-06 22:08:10,796 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-06 22:08:10,797 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-06 22:08:10,797 INFO L145 PredicateUnifier]: Initialized classic predicate unifier [2023-11-06 22:08:10,797 INFO L85 PathProgramCache]: Analyzing trace with hash 616859399, now seen corresponding path program 1 times [2023-11-06 22:08:10,797 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-06 22:08:10,797 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [595117884] [2023-11-06 22:08:10,798 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-06 22:08:10,798 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-06 22:08:10,811 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-06 22:08:10,841 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-06 22:08:10,841 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-06 22:08:10,841 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [595117884] [2023-11-06 22:08:10,841 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [595117884] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-06 22:08:10,841 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-06 22:08:10,841 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-06 22:08:10,841 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [666987966] [2023-11-06 22:08:10,842 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-06 22:08:10,842 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-06 22:08:10,842 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-06 22:08:10,842 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2023-11-06 22:08:10,843 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2023-11-06 22:08:10,843 INFO L87 Difference]: Start difference. First operand 10048 states and 14536 transitions. cyclomatic complexity: 4500 Second operand has 5 states, 5 states have (on average 16.4) internal successors, (82), 5 states have internal predecessors, (82), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-06 22:08:11,136 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-06 22:08:11,136 INFO L93 Difference]: Finished difference Result 19750 states and 28281 transitions. [2023-11-06 22:08:11,137 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 19750 states and 28281 transitions. [2023-11-06 22:08:11,236 INFO L131 ngComponentsAnalysis]: Automaton has 12 accepting balls. 19512 [2023-11-06 22:08:11,307 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 19750 states to 19750 states and 28281 transitions. [2023-11-06 22:08:11,307 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 19750 [2023-11-06 22:08:11,329 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 19750 [2023-11-06 22:08:11,329 INFO L73 IsDeterministic]: Start isDeterministic. Operand 19750 states and 28281 transitions. [2023-11-06 22:08:11,503 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-06 22:08:11,504 INFO L218 hiAutomatonCegarLoop]: Abstraction has 19750 states and 28281 transitions. [2023-11-06 22:08:11,525 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 19750 states and 28281 transitions. [2023-11-06 22:08:11,696 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 19750 to 10471. [2023-11-06 22:08:11,713 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 10471 states, 10471 states have (on average 1.42861235794098) internal successors, (14959), 10470 states have internal predecessors, (14959), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-06 22:08:11,742 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 10471 states to 10471 states and 14959 transitions. [2023-11-06 22:08:11,742 INFO L240 hiAutomatonCegarLoop]: Abstraction has 10471 states and 14959 transitions. [2023-11-06 22:08:11,743 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2023-11-06 22:08:11,743 INFO L428 stractBuchiCegarLoop]: Abstraction has 10471 states and 14959 transitions. [2023-11-06 22:08:11,743 INFO L335 stractBuchiCegarLoop]: ======== Iteration 13 ============ [2023-11-06 22:08:11,743 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 10471 states and 14959 transitions. [2023-11-06 22:08:11,781 INFO L131 ngComponentsAnalysis]: Automaton has 12 accepting balls. 10316 [2023-11-06 22:08:11,781 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-06 22:08:11,781 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-06 22:08:11,783 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-06 22:08:11,783 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-06 22:08:11,783 INFO L748 eck$LassoCheckResult]: Stem: 71816#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2; 71817#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~8#1;havoc main_~__retres1~8#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 71958#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret20#1, start_simulation_#t~ret21#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 71959#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 71477#L461 assume 1 == ~m_i~0;~m_st~0 := 0; 71478#L461-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 72029#L466-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 72213#L471-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 71570#L476-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 71571#L481-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 71733#L486-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 71585#L491-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 71586#L670 assume !(0 == ~M_E~0); 71972#L670-2 assume !(0 == ~T1_E~0); 71918#L675-1 assume !(0 == ~T2_E~0); 71919#L680-1 assume !(0 == ~T3_E~0); 72026#L685-1 assume !(0 == ~T4_E~0); 71981#L690-1 assume !(0 == ~T5_E~0); 71982#L695-1 assume !(0 == ~T6_E~0); 72076#L700-1 assume !(0 == ~E_1~0); 72062#L705-1 assume !(0 == ~E_2~0); 72063#L710-1 assume !(0 == ~E_3~0); 71917#L715-1 assume !(0 == ~E_4~0); 71842#L720-1 assume !(0 == ~E_5~0); 71843#L725-1 assume !(0 == ~E_6~0); 71896#L730-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 71946#L320 assume !(1 == ~m_pc~0); 72100#L320-2 is_master_triggered_~__retres1~0#1 := 0; 71782#L331 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 71775#is_master_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 71734#L825 assume !(0 != activate_threads_~tmp~1#1); 71735#L825-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 71741#L339 assume !(1 == ~t1_pc~0); 71742#L339-2 is_transmit1_triggered_~__retres1~1#1 := 0; 71709#L350 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 71566#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 71567#L833 assume !(0 != activate_threads_~tmp___0~0#1); 71589#L833-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 71503#L358 assume !(1 == ~t2_pc~0); 71504#L358-2 is_transmit2_triggered_~__retres1~2#1 := 0; 72051#L369 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 71961#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 71899#L841 assume !(0 != activate_threads_~tmp___1~0#1); 71729#L841-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 71730#L377 assume !(1 == ~t3_pc~0); 72007#L377-2 is_transmit3_triggered_~__retres1~3#1 := 0; 72008#L388 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 71501#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 71502#L849 assume !(0 != activate_threads_~tmp___2~0#1); 71737#L849-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 71666#L396 assume !(1 == ~t4_pc~0); 71667#L396-2 is_transmit4_triggered_~__retres1~4#1 := 0; 71505#L407 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 71506#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 71649#L857 assume !(0 != activate_threads_~tmp___3~0#1); 71633#L857-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 71634#L415 assume !(1 == ~t5_pc~0); 71716#L415-2 is_transmit5_triggered_~__retres1~5#1 := 0; 71770#L426 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 71787#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 71788#L865 assume !(0 != activate_threads_~tmp___4~0#1); 71543#L865-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 71544#L434 assume !(1 == ~t6_pc~0); 71874#L434-2 is_transmit6_triggered_~__retres1~6#1 := 0; 71875#L445 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 72037#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 72038#L873 assume !(0 != activate_threads_~tmp___5~0#1); 71754#L873-2 havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 71755#L743 assume !(1 == ~M_E~0); 71625#L743-2 assume !(1 == ~T1_E~0); 71626#L748-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 72169#L753-1 assume !(1 == ~T3_E~0); 72079#L758-1 assume 1 == ~T4_E~0;~T4_E~0 := 2; 72080#L763-1 assume !(1 == ~T5_E~0); 72209#L768-1 assume !(1 == ~T6_E~0); 72210#L773-1 assume !(1 == ~E_1~0); 71750#L778-1 assume !(1 == ~E_2~0); 72253#L783-1 assume !(1 == ~E_3~0); 72241#L788-1 assume !(1 == ~E_4~0); 72242#L793-1 assume !(1 == ~E_5~0); 71967#L798-1 assume 1 == ~E_6~0;~E_6~0 := 2; 71968#L803-1 assume { :end_inline_reset_delta_events } true; 76081#L1024-2 [2023-11-06 22:08:11,784 INFO L750 eck$LassoCheckResult]: Loop: 76081#L1024-2 assume !false; 76082#L1025 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 77757#L645-1 assume !false; 76044#L552 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 76031#L504 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 76018#L541 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 76011#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 76003#L556 assume !(0 != eval_~tmp~0#1); 76005#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 78101#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 78100#L670-3 assume 0 == ~M_E~0;~M_E~0 := 1; 78099#L670-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 78098#L675-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 78096#L680-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 78094#L685-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 78092#L690-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 78090#L695-3 assume !(0 == ~T6_E~0); 78088#L700-3 assume !(0 == ~E_1~0); 78086#L705-3 assume 0 == ~E_2~0;~E_2~0 := 1; 78084#L710-3 assume 0 == ~E_3~0;~E_3~0 := 1; 78081#L715-3 assume 0 == ~E_4~0;~E_4~0 := 1; 78079#L720-3 assume 0 == ~E_5~0;~E_5~0 := 1; 78077#L725-3 assume 0 == ~E_6~0;~E_6~0 := 1; 78075#L730-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 78073#L320-21 assume !(1 == ~m_pc~0); 78071#L320-23 is_master_triggered_~__retres1~0#1 := 0; 78070#L331-7 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 78068#is_master_triggered_returnLabel#8 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 78066#L825-21 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 78064#L825-23 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 78062#L339-21 assume !(1 == ~t1_pc~0); 78059#L339-23 is_transmit1_triggered_~__retres1~1#1 := 0; 78055#L350-7 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 78053#is_transmit1_triggered_returnLabel#8 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 78051#L833-21 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 78049#L833-23 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 78047#L358-21 assume !(1 == ~t2_pc~0); 77159#L358-23 is_transmit2_triggered_~__retres1~2#1 := 0; 78045#L369-7 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 78043#is_transmit2_triggered_returnLabel#8 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 78041#L841-21 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 78039#L841-23 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 78037#L377-21 assume 1 == ~t3_pc~0; 78027#L378-7 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 78022#L388-7 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 78017#is_transmit3_triggered_returnLabel#8 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 78011#L849-21 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 78006#L849-23 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 78001#L396-21 assume !(1 == ~t4_pc~0); 77996#L396-23 is_transmit4_triggered_~__retres1~4#1 := 0; 77991#L407-7 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 77986#is_transmit4_triggered_returnLabel#8 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 77981#L857-21 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 77976#L857-23 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 77971#L415-21 assume !(1 == ~t5_pc~0); 77966#L415-23 is_transmit5_triggered_~__retres1~5#1 := 0; 77961#L426-7 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 77956#is_transmit5_triggered_returnLabel#8 activate_threads_#t~ret17#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 77951#L865-21 assume !(0 != activate_threads_~tmp___4~0#1); 77950#L865-23 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 77683#L434-21 assume !(1 == ~t6_pc~0); 77685#L434-23 is_transmit6_triggered_~__retres1~6#1 := 0; 77758#L445-7 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 77759#is_transmit6_triggered_returnLabel#8 activate_threads_#t~ret18#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 77650#L873-21 assume !(0 != activate_threads_~tmp___5~0#1); 77649#L873-23 havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 76506#L743-3 assume 1 == ~M_E~0;~M_E~0 := 2; 76507#L743-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 76500#L748-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 76501#L753-3 assume !(1 == ~T3_E~0); 76494#L758-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 76495#L763-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 76488#L768-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 76489#L773-3 assume 1 == ~E_1~0;~E_1~0 := 2; 76468#L778-3 assume 1 == ~E_2~0;~E_2~0 := 2; 76469#L783-3 assume 1 == ~E_3~0;~E_3~0 := 2; 76452#L788-3 assume 1 == ~E_4~0;~E_4~0 := 2; 76453#L793-3 assume !(1 == ~E_5~0); 76434#L798-3 assume 1 == ~E_6~0;~E_6~0 := 2; 76435#L803-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 76321#L504-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 76315#L541-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 76308#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret20#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret20#1;havoc start_simulation_#t~ret20#1; 76309#L1043 assume !(0 == start_simulation_~tmp~3#1); 76224#L1043-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret19#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 76225#L504-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 76125#L541-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 76126#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret19#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret19#1;havoc stop_simulation_#t~ret19#1; 76117#L998 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 76118#L1005 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 76109#stop_simulation_returnLabel#1 start_simulation_#t~ret21#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret19#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret21#1;havoc start_simulation_#t~ret21#1; 76110#L1056 assume !(0 != start_simulation_~tmp___0~1#1); 76081#L1024-2 [2023-11-06 22:08:11,784 INFO L145 PredicateUnifier]: Initialized classic predicate unifier [2023-11-06 22:08:11,785 INFO L85 PathProgramCache]: Analyzing trace with hash -1965602341, now seen corresponding path program 1 times [2023-11-06 22:08:11,785 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-06 22:08:11,785 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1184736089] [2023-11-06 22:08:11,785 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-06 22:08:11,785 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-06 22:08:11,873 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-06 22:08:11,923 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-06 22:08:11,923 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-06 22:08:11,923 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1184736089] [2023-11-06 22:08:11,923 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1184736089] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-06 22:08:11,924 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-06 22:08:11,924 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2023-11-06 22:08:11,924 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1889941821] [2023-11-06 22:08:11,924 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-06 22:08:11,925 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-06 22:08:11,926 INFO L145 PredicateUnifier]: Initialized classic predicate unifier [2023-11-06 22:08:11,926 INFO L85 PathProgramCache]: Analyzing trace with hash -1448880445, now seen corresponding path program 1 times [2023-11-06 22:08:11,926 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-06 22:08:11,926 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [573960227] [2023-11-06 22:08:11,926 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-06 22:08:11,927 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-06 22:08:11,941 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-06 22:08:11,969 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-06 22:08:11,970 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-06 22:08:11,970 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [573960227] [2023-11-06 22:08:11,970 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [573960227] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-06 22:08:11,970 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-06 22:08:11,970 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-06 22:08:11,970 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1448992865] [2023-11-06 22:08:11,971 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-06 22:08:11,971 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-06 22:08:11,971 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-06 22:08:11,972 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-06 22:08:11,972 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-06 22:08:11,973 INFO L87 Difference]: Start difference. First operand 10471 states and 14959 transitions. cyclomatic complexity: 4500 Second operand has 3 states, 3 states have (on average 27.333333333333332) internal successors, (82), 2 states have internal predecessors, (82), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-06 22:08:12,020 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-06 22:08:12,020 INFO L93 Difference]: Finished difference Result 10466 states and 14884 transitions. [2023-11-06 22:08:12,020 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 10466 states and 14884 transitions. [2023-11-06 22:08:12,066 INFO L131 ngComponentsAnalysis]: Automaton has 12 accepting balls. 10316 [2023-11-06 22:08:12,173 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 10466 states to 10466 states and 14884 transitions. [2023-11-06 22:08:12,174 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 10466 [2023-11-06 22:08:12,184 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 10466 [2023-11-06 22:08:12,184 INFO L73 IsDeterministic]: Start isDeterministic. Operand 10466 states and 14884 transitions. [2023-11-06 22:08:12,196 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-06 22:08:12,196 INFO L218 hiAutomatonCegarLoop]: Abstraction has 10466 states and 14884 transitions. [2023-11-06 22:08:12,208 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 10466 states and 14884 transitions. [2023-11-06 22:08:12,323 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 10466 to 7184. [2023-11-06 22:08:12,343 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 7184 states, 7184 states have (on average 1.4227449888641426) internal successors, (10221), 7183 states have internal predecessors, (10221), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-06 22:08:12,367 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 7184 states to 7184 states and 10221 transitions. [2023-11-06 22:08:12,368 INFO L240 hiAutomatonCegarLoop]: Abstraction has 7184 states and 10221 transitions. [2023-11-06 22:08:12,368 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-06 22:08:12,369 INFO L428 stractBuchiCegarLoop]: Abstraction has 7184 states and 10221 transitions. [2023-11-06 22:08:12,370 INFO L335 stractBuchiCegarLoop]: ======== Iteration 14 ============ [2023-11-06 22:08:12,370 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 7184 states and 10221 transitions. [2023-11-06 22:08:12,398 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 7056 [2023-11-06 22:08:12,398 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-06 22:08:12,399 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-06 22:08:12,400 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-06 22:08:12,401 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-06 22:08:12,401 INFO L748 eck$LassoCheckResult]: Stem: 92753#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2; 92754#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~8#1;havoc main_~__retres1~8#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 92889#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret20#1, start_simulation_#t~ret21#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 92890#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 92421#L461 assume 1 == ~m_i~0;~m_st~0 := 0; 92422#L461-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 92952#L466-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 93101#L471-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 92513#L476-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 92514#L481-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 92677#L486-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 92529#L491-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 92530#L670 assume !(0 == ~M_E~0); 92901#L670-2 assume !(0 == ~T1_E~0); 92851#L675-1 assume !(0 == ~T2_E~0); 92852#L680-1 assume !(0 == ~T3_E~0); 92951#L685-1 assume !(0 == ~T4_E~0); 92909#L690-1 assume !(0 == ~T5_E~0); 92910#L695-1 assume !(0 == ~T6_E~0); 92994#L700-1 assume !(0 == ~E_1~0); 92982#L705-1 assume !(0 == ~E_2~0); 92983#L710-1 assume !(0 == ~E_3~0); 92850#L715-1 assume !(0 == ~E_4~0); 92781#L720-1 assume !(0 == ~E_5~0); 92782#L725-1 assume !(0 == ~E_6~0); 92830#L730-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 92878#L320 assume !(1 == ~m_pc~0); 93011#L320-2 is_master_triggered_~__retres1~0#1 := 0; 92723#L331 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 92717#is_master_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 92678#L825 assume !(0 != activate_threads_~tmp~1#1); 92679#L825-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 92683#L339 assume !(1 == ~t1_pc~0); 92684#L339-2 is_transmit1_triggered_~__retres1~1#1 := 0; 92654#L350 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 92511#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 92512#L833 assume !(0 != activate_threads_~tmp___0~0#1); 92534#L833-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 92447#L358 assume !(1 == ~t2_pc~0); 92448#L358-2 is_transmit2_triggered_~__retres1~2#1 := 0; 92973#L369 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 92892#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 92833#L841 assume !(0 != activate_threads_~tmp___1~0#1); 92673#L841-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 92674#L377 assume !(1 == ~t3_pc~0); 92931#L377-2 is_transmit3_triggered_~__retres1~3#1 := 0; 92932#L388 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 92443#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 92444#L849 assume !(0 != activate_threads_~tmp___2~0#1); 92682#L849-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 92611#L396 assume !(1 == ~t4_pc~0); 92612#L396-2 is_transmit4_triggered_~__retres1~4#1 := 0; 92449#L407 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 92450#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 92593#L857 assume !(0 != activate_threads_~tmp___3~0#1); 92578#L857-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 92579#L415 assume !(1 == ~t5_pc~0); 92659#L415-2 is_transmit5_triggered_~__retres1~5#1 := 0; 92708#L426 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 92726#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 92727#L865 assume !(0 != activate_threads_~tmp___4~0#1); 92488#L865-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 92489#L434 assume !(1 == ~t6_pc~0); 92813#L434-2 is_transmit6_triggered_~__retres1~6#1 := 0; 92814#L445 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 92883#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 92884#L873 assume !(0 != activate_threads_~tmp___5~0#1); 92696#L873-2 havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 92697#L743 assume !(1 == ~M_E~0); 92570#L743-2 assume !(1 == ~T1_E~0); 92571#L748-1 assume !(1 == ~T2_E~0); 92871#L753-1 assume !(1 == ~T3_E~0); 92872#L758-1 assume 1 == ~T4_E~0;~T4_E~0 := 2; 92996#L763-1 assume !(1 == ~T5_E~0); 93053#L768-1 assume !(1 == ~T6_E~0); 92690#L773-1 assume !(1 == ~E_1~0); 92691#L778-1 assume !(1 == ~E_2~0); 92668#L783-1 assume !(1 == ~E_3~0); 92669#L788-1 assume !(1 == ~E_4~0); 92949#L793-1 assume !(1 == ~E_5~0); 92898#L798-1 assume 1 == ~E_6~0;~E_6~0 := 2; 92551#L803-1 assume { :end_inline_reset_delta_events } true; 92552#L1024-2 [2023-11-06 22:08:12,402 INFO L750 eck$LassoCheckResult]: Loop: 92552#L1024-2 assume !false; 97076#L1025 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 97071#L645-1 assume !false; 97070#L552 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 96954#L504 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 96943#L541 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 96933#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 96930#L556 assume !(0 != eval_~tmp~0#1); 96931#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 99489#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 99488#L670-3 assume 0 == ~M_E~0;~M_E~0 := 1; 99486#L670-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 99484#L675-3 assume !(0 == ~T2_E~0); 99482#L680-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 99480#L685-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 99478#L690-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 99476#L695-3 assume !(0 == ~T6_E~0); 99474#L700-3 assume !(0 == ~E_1~0); 99472#L705-3 assume 0 == ~E_2~0;~E_2~0 := 1; 99470#L710-3 assume 0 == ~E_3~0;~E_3~0 := 1; 99468#L715-3 assume 0 == ~E_4~0;~E_4~0 := 1; 99466#L720-3 assume 0 == ~E_5~0;~E_5~0 := 1; 99464#L725-3 assume 0 == ~E_6~0;~E_6~0 := 1; 99462#L730-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 99460#L320-21 assume !(1 == ~m_pc~0); 99458#L320-23 is_master_triggered_~__retres1~0#1 := 0; 99456#L331-7 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 99454#is_master_triggered_returnLabel#8 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 99452#L825-21 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 99450#L825-23 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 99448#L339-21 assume !(1 == ~t1_pc~0); 99445#L339-23 is_transmit1_triggered_~__retres1~1#1 := 0; 99441#L350-7 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 99439#is_transmit1_triggered_returnLabel#8 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 99437#L833-21 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 99435#L833-23 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 98019#L358-21 assume !(1 == ~t2_pc~0); 98018#L358-23 is_transmit2_triggered_~__retres1~2#1 := 0; 98017#L369-7 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 98016#is_transmit2_triggered_returnLabel#8 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 98015#L841-21 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 98014#L841-23 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 98013#L377-21 assume !(1 == ~t3_pc~0); 98011#L377-23 is_transmit3_triggered_~__retres1~3#1 := 0; 98009#L388-7 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 98008#is_transmit3_triggered_returnLabel#8 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 98007#L849-21 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 98006#L849-23 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 98005#L396-21 assume !(1 == ~t4_pc~0); 98003#L396-23 is_transmit4_triggered_~__retres1~4#1 := 0; 98001#L407-7 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 97999#is_transmit4_triggered_returnLabel#8 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 97997#L857-21 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 97995#L857-23 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 97993#L415-21 assume !(1 == ~t5_pc~0); 97991#L415-23 is_transmit5_triggered_~__retres1~5#1 := 0; 97988#L426-7 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 97986#is_transmit5_triggered_returnLabel#8 activate_threads_#t~ret17#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 97984#L865-21 assume !(0 != activate_threads_~tmp___4~0#1); 97982#L865-23 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 97980#L434-21 assume !(1 == ~t6_pc~0); 97976#L434-23 is_transmit6_triggered_~__retres1~6#1 := 0; 97973#L445-7 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 97971#is_transmit6_triggered_returnLabel#8 activate_threads_#t~ret18#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 97969#L873-21 assume !(0 != activate_threads_~tmp___5~0#1); 97966#L873-23 havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 97964#L743-3 assume 1 == ~M_E~0;~M_E~0 := 2; 97962#L743-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 97959#L748-3 assume !(1 == ~T2_E~0); 97957#L753-3 assume !(1 == ~T3_E~0); 97955#L758-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 97953#L763-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 97951#L768-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 97949#L773-3 assume 1 == ~E_1~0;~E_1~0 := 2; 97947#L778-3 assume 1 == ~E_2~0;~E_2~0 := 2; 97945#L783-3 assume 1 == ~E_3~0;~E_3~0 := 2; 97943#L788-3 assume 1 == ~E_4~0;~E_4~0 := 2; 97941#L793-3 assume !(1 == ~E_5~0); 97939#L798-3 assume 1 == ~E_6~0;~E_6~0 := 2; 97937#L803-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 97935#L504-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 97927#L541-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 97925#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret20#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret20#1;havoc start_simulation_#t~ret20#1; 97102#L1043 assume !(0 == start_simulation_~tmp~3#1); 97099#L1043-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret19#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 97097#L504-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 97089#L541-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 97087#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret19#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret19#1;havoc stop_simulation_#t~ret19#1; 97086#L998 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 97083#L1005 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 97081#stop_simulation_returnLabel#1 start_simulation_#t~ret21#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret19#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret21#1;havoc start_simulation_#t~ret21#1; 97079#L1056 assume !(0 != start_simulation_~tmp___0~1#1); 92552#L1024-2 [2023-11-06 22:08:12,402 INFO L145 PredicateUnifier]: Initialized classic predicate unifier [2023-11-06 22:08:12,403 INFO L85 PathProgramCache]: Analyzing trace with hash -1707436903, now seen corresponding path program 1 times [2023-11-06 22:08:12,403 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-06 22:08:12,403 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1299591504] [2023-11-06 22:08:12,403 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-06 22:08:12,403 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-06 22:08:12,419 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-06 22:08:12,483 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-06 22:08:12,483 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-06 22:08:12,483 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1299591504] [2023-11-06 22:08:12,484 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1299591504] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-06 22:08:12,484 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-06 22:08:12,485 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-06 22:08:12,485 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [484982185] [2023-11-06 22:08:12,485 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-06 22:08:12,487 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-06 22:08:12,488 INFO L145 PredicateUnifier]: Initialized classic predicate unifier [2023-11-06 22:08:12,488 INFO L85 PathProgramCache]: Analyzing trace with hash -160766178, now seen corresponding path program 1 times [2023-11-06 22:08:12,488 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-06 22:08:12,488 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [781233465] [2023-11-06 22:08:12,488 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-06 22:08:12,489 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-06 22:08:12,504 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-06 22:08:12,540 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-06 22:08:12,541 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-06 22:08:12,541 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [781233465] [2023-11-06 22:08:12,541 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [781233465] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-06 22:08:12,541 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-06 22:08:12,542 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-06 22:08:12,542 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1856850228] [2023-11-06 22:08:12,542 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-06 22:08:12,543 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-06 22:08:12,543 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-06 22:08:12,544 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2023-11-06 22:08:12,544 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2023-11-06 22:08:12,545 INFO L87 Difference]: Start difference. First operand 7184 states and 10221 transitions. cyclomatic complexity: 3045 Second operand has 4 states, 4 states have (on average 20.5) internal successors, (82), 3 states have internal predecessors, (82), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-06 22:08:12,680 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-06 22:08:12,681 INFO L93 Difference]: Finished difference Result 15375 states and 21827 transitions. [2023-11-06 22:08:12,681 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 15375 states and 21827 transitions. [2023-11-06 22:08:12,760 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 15136 [2023-11-06 22:08:12,956 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 15375 states to 15375 states and 21827 transitions. [2023-11-06 22:08:12,956 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 15375 [2023-11-06 22:08:12,973 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 15375 [2023-11-06 22:08:12,973 INFO L73 IsDeterministic]: Start isDeterministic. Operand 15375 states and 21827 transitions. [2023-11-06 22:08:12,989 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-06 22:08:12,990 INFO L218 hiAutomatonCegarLoop]: Abstraction has 15375 states and 21827 transitions. [2023-11-06 22:08:13,003 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 15375 states and 21827 transitions. [2023-11-06 22:08:13,102 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 15375 to 8270. [2023-11-06 22:08:13,114 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 8270 states, 8270 states have (on average 1.4203143893591295) internal successors, (11746), 8269 states have internal predecessors, (11746), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-06 22:08:13,137 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 8270 states to 8270 states and 11746 transitions. [2023-11-06 22:08:13,138 INFO L240 hiAutomatonCegarLoop]: Abstraction has 8270 states and 11746 transitions. [2023-11-06 22:08:13,138 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2023-11-06 22:08:13,139 INFO L428 stractBuchiCegarLoop]: Abstraction has 8270 states and 11746 transitions. [2023-11-06 22:08:13,139 INFO L335 stractBuchiCegarLoop]: ======== Iteration 15 ============ [2023-11-06 22:08:13,139 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 8270 states and 11746 transitions. [2023-11-06 22:08:13,235 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 8080 [2023-11-06 22:08:13,235 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-06 22:08:13,236 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-06 22:08:13,237 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-06 22:08:13,237 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-06 22:08:13,238 INFO L748 eck$LassoCheckResult]: Stem: 115335#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2; 115336#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~8#1;havoc main_~__retres1~8#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 115478#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret20#1, start_simulation_#t~ret21#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 115479#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 114990#L461 assume 1 == ~m_i~0;~m_st~0 := 0; 114991#L461-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 115556#L466-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 115736#L471-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 115082#L476-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 115083#L481-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 115253#L486-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 115098#L491-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 115099#L670 assume !(0 == ~M_E~0); 115493#L670-2 assume !(0 == ~T1_E~0); 115437#L675-1 assume !(0 == ~T2_E~0); 115438#L680-1 assume !(0 == ~T3_E~0); 115555#L685-1 assume 0 == ~T4_E~0;~T4_E~0 := 1; 115645#L690-1 assume !(0 == ~T5_E~0); 115767#L695-1 assume !(0 == ~T6_E~0); 115768#L700-1 assume !(0 == ~E_1~0); 115590#L705-1 assume !(0 == ~E_2~0); 115591#L710-1 assume !(0 == ~E_3~0); 115786#L715-1 assume !(0 == ~E_4~0); 115364#L720-1 assume !(0 == ~E_5~0); 115365#L725-1 assume !(0 == ~E_6~0); 115464#L730-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 115465#L320 assume !(1 == ~m_pc~0); 115746#L320-2 is_master_triggered_~__retres1~0#1 := 0; 115747#L331 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 115296#is_master_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 115297#L825 assume !(0 != activate_threads_~tmp~1#1); 115657#L825-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 115658#L339 assume !(1 == ~t1_pc~0); 115459#L339-2 is_transmit1_triggered_~__retres1~1#1 := 0; 115228#L350 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 115229#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 115103#L833 assume !(0 != activate_threads_~tmp___0~0#1); 115104#L833-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 115016#L358 assume !(1 == ~t2_pc~0); 115017#L358-2 is_transmit2_triggered_~__retres1~2#1 := 0; 115784#L369 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 115481#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 115482#L841 assume !(0 != activate_threads_~tmp___1~0#1); 115249#L841-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 115250#L377 assume !(1 == ~t3_pc~0); 115526#L377-2 is_transmit3_triggered_~__retres1~3#1 := 0; 115527#L388 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 115012#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 115013#L849 assume !(0 != activate_threads_~tmp___2~0#1); 115551#L849-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 115552#L396 assume !(1 == ~t4_pc~0); 115783#L396-2 is_transmit4_triggered_~__retres1~4#1 := 0; 115018#L407 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 115019#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 115452#L857 assume !(0 != activate_threads_~tmp___3~0#1); 115453#L857-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 115782#L415 assume !(1 == ~t5_pc~0); 115286#L415-2 is_transmit5_triggered_~__retres1~5#1 := 0; 115287#L426 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 115307#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 115308#L865 assume !(0 != activate_threads_~tmp___4~0#1); 115781#L865-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 115528#L434 assume !(1 == ~t6_pc~0); 115529#L434-2 is_transmit6_triggered_~__retres1~6#1 := 0; 115778#L445 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 115779#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 115569#L873 assume !(0 != activate_threads_~tmp___5~0#1); 115570#L873-2 havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 115721#L743 assume !(1 == ~M_E~0); 115722#L743-2 assume !(1 == ~T1_E~0); 115780#L748-1 assume !(1 == ~T2_E~0); 115460#L753-1 assume !(1 == ~T3_E~0); 115461#L758-1 assume 1 == ~T4_E~0;~T4_E~0 := 2; 115607#L763-1 assume !(1 == ~T5_E~0); 115672#L768-1 assume !(1 == ~T6_E~0); 115268#L773-1 assume !(1 == ~E_1~0); 115269#L778-1 assume !(1 == ~E_2~0); 115244#L783-1 assume !(1 == ~E_3~0); 115245#L788-1 assume !(1 == ~E_4~0); 115553#L793-1 assume !(1 == ~E_5~0); 115489#L798-1 assume 1 == ~E_6~0;~E_6~0 := 2; 115121#L803-1 assume { :end_inline_reset_delta_events } true; 115122#L1024-2 [2023-11-06 22:08:13,238 INFO L750 eck$LassoCheckResult]: Loop: 115122#L1024-2 assume !false; 118095#L1025 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 118090#L645-1 assume !false; 118087#L552 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 118085#L504 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 118078#L541 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 118074#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 118071#L556 assume !(0 != eval_~tmp~0#1); 118072#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 122424#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 122419#L670-3 assume 0 == ~M_E~0;~M_E~0 := 1; 122414#L670-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 122411#L675-3 assume !(0 == ~T2_E~0); 122410#L680-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 118253#L685-3 assume !(0 == ~T4_E~0); 118255#L690-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 123149#L695-3 assume !(0 == ~T6_E~0); 123147#L700-3 assume !(0 == ~E_1~0); 123145#L705-3 assume 0 == ~E_2~0;~E_2~0 := 1; 123143#L710-3 assume 0 == ~E_3~0;~E_3~0 := 1; 123141#L715-3 assume 0 == ~E_4~0;~E_4~0 := 1; 123139#L720-3 assume 0 == ~E_5~0;~E_5~0 := 1; 123137#L725-3 assume 0 == ~E_6~0;~E_6~0 := 1; 123135#L730-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 123133#L320-21 assume !(1 == ~m_pc~0); 123131#L320-23 is_master_triggered_~__retres1~0#1 := 0; 123129#L331-7 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 123127#is_master_triggered_returnLabel#8 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 123124#L825-21 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 123122#L825-23 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 123120#L339-21 assume 1 == ~t1_pc~0; 123117#L340-7 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 123115#L350-7 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 123113#is_transmit1_triggered_returnLabel#8 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 123112#L833-21 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 123110#L833-23 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 118422#L358-21 assume !(1 == ~t2_pc~0); 118420#L358-23 is_transmit2_triggered_~__retres1~2#1 := 0; 118418#L369-7 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 118416#is_transmit2_triggered_returnLabel#8 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 118413#L841-21 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 118411#L841-23 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 118407#L377-21 assume !(1 == ~t3_pc~0); 118405#L377-23 is_transmit3_triggered_~__retres1~3#1 := 0; 118402#L388-7 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 118401#is_transmit3_triggered_returnLabel#8 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 118398#L849-21 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 118397#L849-23 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 118396#L396-21 assume !(1 == ~t4_pc~0); 118395#L396-23 is_transmit4_triggered_~__retres1~4#1 := 0; 118394#L407-7 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 118393#is_transmit4_triggered_returnLabel#8 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 118392#L857-21 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 118391#L857-23 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 118390#L415-21 assume !(1 == ~t5_pc~0); 118389#L415-23 is_transmit5_triggered_~__retres1~5#1 := 0; 118388#L426-7 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 118387#is_transmit5_triggered_returnLabel#8 activate_threads_#t~ret17#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 118386#L865-21 assume !(0 != activate_threads_~tmp___4~0#1); 118385#L865-23 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 118383#L434-21 assume 1 == ~t6_pc~0; 118381#L435-7 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 118382#L445-7 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 118384#is_transmit6_triggered_returnLabel#8 activate_threads_#t~ret18#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 118374#L873-21 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 118372#L873-23 havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 118370#L743-3 assume 1 == ~M_E~0;~M_E~0 := 2; 118368#L743-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 118366#L748-3 assume !(1 == ~T2_E~0); 118364#L753-3 assume !(1 == ~T3_E~0); 118157#L758-3 assume !(1 == ~T4_E~0); 118154#L763-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 118152#L768-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 118150#L773-3 assume 1 == ~E_1~0;~E_1~0 := 2; 118147#L778-3 assume 1 == ~E_2~0;~E_2~0 := 2; 118145#L783-3 assume 1 == ~E_3~0;~E_3~0 := 2; 118143#L788-3 assume 1 == ~E_4~0;~E_4~0 := 2; 118141#L793-3 assume !(1 == ~E_5~0); 118139#L798-3 assume 1 == ~E_6~0;~E_6~0 := 2; 118137#L803-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 118135#L504-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 118127#L541-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 118125#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret20#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret20#1;havoc start_simulation_#t~ret20#1; 118123#L1043 assume !(0 == start_simulation_~tmp~3#1); 118120#L1043-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret19#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 118118#L504-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 118110#L541-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 118108#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret19#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret19#1;havoc stop_simulation_#t~ret19#1; 118106#L998 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 118104#L1005 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 118102#stop_simulation_returnLabel#1 start_simulation_#t~ret21#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret19#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret21#1;havoc start_simulation_#t~ret21#1; 118098#L1056 assume !(0 != start_simulation_~tmp___0~1#1); 115122#L1024-2 [2023-11-06 22:08:13,239 INFO L145 PredicateUnifier]: Initialized classic predicate unifier [2023-11-06 22:08:13,239 INFO L85 PathProgramCache]: Analyzing trace with hash -975469477, now seen corresponding path program 1 times [2023-11-06 22:08:13,239 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-06 22:08:13,239 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [23316665] [2023-11-06 22:08:13,240 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-06 22:08:13,240 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-06 22:08:13,250 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-06 22:08:13,301 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-06 22:08:13,301 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-06 22:08:13,301 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [23316665] [2023-11-06 22:08:13,301 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [23316665] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-06 22:08:13,301 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-06 22:08:13,302 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-06 22:08:13,302 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1336572450] [2023-11-06 22:08:13,302 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-06 22:08:13,302 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-06 22:08:13,303 INFO L145 PredicateUnifier]: Initialized classic predicate unifier [2023-11-06 22:08:13,303 INFO L85 PathProgramCache]: Analyzing trace with hash -1332105250, now seen corresponding path program 1 times [2023-11-06 22:08:13,303 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-06 22:08:13,303 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [553997316] [2023-11-06 22:08:13,303 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-06 22:08:13,304 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-06 22:08:13,315 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-06 22:08:13,345 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-06 22:08:13,345 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-06 22:08:13,345 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [553997316] [2023-11-06 22:08:13,345 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [553997316] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-06 22:08:13,345 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-06 22:08:13,346 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-06 22:08:13,346 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1505279409] [2023-11-06 22:08:13,346 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-06 22:08:13,346 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-06 22:08:13,347 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-06 22:08:13,347 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2023-11-06 22:08:13,347 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2023-11-06 22:08:13,347 INFO L87 Difference]: Start difference. First operand 8270 states and 11746 transitions. cyclomatic complexity: 3484 Second operand has 4 states, 4 states have (on average 20.5) internal successors, (82), 3 states have internal predecessors, (82), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-06 22:08:13,403 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-06 22:08:13,403 INFO L93 Difference]: Finished difference Result 7184 states and 10171 transitions. [2023-11-06 22:08:13,403 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 7184 states and 10171 transitions. [2023-11-06 22:08:13,434 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 7056 [2023-11-06 22:08:13,459 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 7184 states to 7184 states and 10171 transitions. [2023-11-06 22:08:13,460 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 7184 [2023-11-06 22:08:13,467 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 7184 [2023-11-06 22:08:13,467 INFO L73 IsDeterministic]: Start isDeterministic. Operand 7184 states and 10171 transitions. [2023-11-06 22:08:13,474 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-06 22:08:13,474 INFO L218 hiAutomatonCegarLoop]: Abstraction has 7184 states and 10171 transitions. [2023-11-06 22:08:13,481 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 7184 states and 10171 transitions. [2023-11-06 22:08:13,549 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 7184 to 7184. [2023-11-06 22:08:13,560 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 7184 states, 7184 states have (on average 1.4157850779510022) internal successors, (10171), 7183 states have internal predecessors, (10171), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-06 22:08:13,580 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 7184 states to 7184 states and 10171 transitions. [2023-11-06 22:08:13,580 INFO L240 hiAutomatonCegarLoop]: Abstraction has 7184 states and 10171 transitions. [2023-11-06 22:08:13,581 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-06 22:08:13,581 INFO L428 stractBuchiCegarLoop]: Abstraction has 7184 states and 10171 transitions. [2023-11-06 22:08:13,581 INFO L335 stractBuchiCegarLoop]: ======== Iteration 16 ============ [2023-11-06 22:08:13,581 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 7184 states and 10171 transitions. [2023-11-06 22:08:13,603 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 7056 [2023-11-06 22:08:13,604 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-06 22:08:13,604 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-06 22:08:13,605 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-06 22:08:13,606 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-06 22:08:13,606 INFO L748 eck$LassoCheckResult]: Stem: 130788#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2; 130789#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~8#1;havoc main_~__retres1~8#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 130925#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret20#1, start_simulation_#t~ret21#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 130926#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 130454#L461 assume 1 == ~m_i~0;~m_st~0 := 0; 130455#L461-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 130990#L466-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 131141#L471-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 130546#L476-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 130547#L481-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 130713#L486-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 130562#L491-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 130563#L670 assume !(0 == ~M_E~0); 130939#L670-2 assume !(0 == ~T1_E~0); 130891#L675-1 assume !(0 == ~T2_E~0); 130892#L680-1 assume !(0 == ~T3_E~0); 130989#L685-1 assume !(0 == ~T4_E~0); 130946#L690-1 assume !(0 == ~T5_E~0); 130947#L695-1 assume !(0 == ~T6_E~0); 131035#L700-1 assume !(0 == ~E_1~0); 131020#L705-1 assume !(0 == ~E_2~0); 131021#L710-1 assume !(0 == ~E_3~0); 130890#L715-1 assume !(0 == ~E_4~0); 130817#L720-1 assume !(0 == ~E_5~0); 130818#L725-1 assume !(0 == ~E_6~0); 130870#L730-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 130914#L320 assume !(1 == ~m_pc~0); 131054#L320-2 is_master_triggered_~__retres1~0#1 := 0; 130759#L331 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 130753#is_master_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 130714#L825 assume !(0 != activate_threads_~tmp~1#1); 130715#L825-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 130718#L339 assume !(1 == ~t1_pc~0); 130719#L339-2 is_transmit1_triggered_~__retres1~1#1 := 0; 130690#L350 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 130544#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 130545#L833 assume !(0 != activate_threads_~tmp___0~0#1); 130567#L833-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 130480#L358 assume !(1 == ~t2_pc~0); 130481#L358-2 is_transmit2_triggered_~__retres1~2#1 := 0; 131011#L369 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 130929#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 130873#L841 assume !(0 != activate_threads_~tmp___1~0#1); 130709#L841-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 130710#L377 assume !(1 == ~t3_pc~0); 130969#L377-2 is_transmit3_triggered_~__retres1~3#1 := 0; 130970#L388 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 130476#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 130477#L849 assume !(0 != activate_threads_~tmp___2~0#1); 130717#L849-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 130645#L396 assume !(1 == ~t4_pc~0); 130646#L396-2 is_transmit4_triggered_~__retres1~4#1 := 0; 130482#L407 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 130483#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 130628#L857 assume !(0 != activate_threads_~tmp___3~0#1); 130612#L857-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 130613#L415 assume !(1 == ~t5_pc~0); 130695#L415-2 is_transmit5_triggered_~__retres1~5#1 := 0; 130744#L426 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 130762#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 130763#L865 assume !(0 != activate_threads_~tmp___4~0#1); 130521#L865-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 130522#L434 assume !(1 == ~t6_pc~0); 130848#L434-2 is_transmit6_triggered_~__retres1~6#1 := 0; 130849#L445 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 130919#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 130920#L873 assume !(0 != activate_threads_~tmp___5~0#1); 130732#L873-2 havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 130733#L743 assume !(1 == ~M_E~0); 130604#L743-2 assume !(1 == ~T1_E~0); 130605#L748-1 assume !(1 == ~T2_E~0); 130910#L753-1 assume !(1 == ~T3_E~0); 130911#L758-1 assume !(1 == ~T4_E~0); 131037#L763-1 assume !(1 == ~T5_E~0); 131095#L768-1 assume !(1 == ~T6_E~0); 130726#L773-1 assume !(1 == ~E_1~0); 130727#L778-1 assume !(1 == ~E_2~0); 130704#L783-1 assume !(1 == ~E_3~0); 130705#L788-1 assume !(1 == ~E_4~0); 130987#L793-1 assume !(1 == ~E_5~0); 130935#L798-1 assume 1 == ~E_6~0;~E_6~0 := 2; 130584#L803-1 assume { :end_inline_reset_delta_events } true; 130585#L1024-2 [2023-11-06 22:08:13,606 INFO L750 eck$LassoCheckResult]: Loop: 130585#L1024-2 assume !false; 136614#L1025 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 136611#L645-1 assume !false; 136610#L552 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 131149#L504 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 130528#L541 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 130953#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 130954#L556 assume !(0 != eval_~tmp~0#1); 131169#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 136779#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 136778#L670-3 assume 0 == ~M_E~0;~M_E~0 := 1; 136777#L670-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 136776#L675-3 assume !(0 == ~T2_E~0); 136775#L680-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 136774#L685-3 assume !(0 == ~T4_E~0); 136773#L690-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 136772#L695-3 assume !(0 == ~T6_E~0); 136771#L700-3 assume !(0 == ~E_1~0); 136770#L705-3 assume 0 == ~E_2~0;~E_2~0 := 1; 136768#L710-3 assume 0 == ~E_3~0;~E_3~0 := 1; 136767#L715-3 assume 0 == ~E_4~0;~E_4~0 := 1; 136766#L720-3 assume 0 == ~E_5~0;~E_5~0 := 1; 136765#L725-3 assume 0 == ~E_6~0;~E_6~0 := 1; 136764#L730-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 136763#L320-21 assume !(1 == ~m_pc~0); 136762#L320-23 is_master_triggered_~__retres1~0#1 := 0; 136761#L331-7 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 136759#is_master_triggered_returnLabel#8 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 136757#L825-21 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 136755#L825-23 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 136753#L339-21 assume 1 == ~t1_pc~0; 136750#L340-7 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 136748#L350-7 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 136746#is_transmit1_triggered_returnLabel#8 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 136743#L833-21 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 136741#L833-23 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 136739#L358-21 assume !(1 == ~t2_pc~0); 135699#L358-23 is_transmit2_triggered_~__retres1~2#1 := 0; 136736#L369-7 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 136734#is_transmit2_triggered_returnLabel#8 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 136733#L841-21 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 136731#L841-23 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 136729#L377-21 assume 1 == ~t3_pc~0; 136726#L378-7 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 136724#L388-7 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 136722#is_transmit3_triggered_returnLabel#8 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 136719#L849-21 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 136717#L849-23 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 136715#L396-21 assume !(1 == ~t4_pc~0); 136713#L396-23 is_transmit4_triggered_~__retres1~4#1 := 0; 136711#L407-7 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 136709#is_transmit4_triggered_returnLabel#8 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 136707#L857-21 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 136705#L857-23 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 136703#L415-21 assume !(1 == ~t5_pc~0); 136701#L415-23 is_transmit5_triggered_~__retres1~5#1 := 0; 136699#L426-7 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 136697#is_transmit5_triggered_returnLabel#8 activate_threads_#t~ret17#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 136695#L865-21 assume !(0 != activate_threads_~tmp___4~0#1); 136693#L865-23 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 136691#L434-21 assume 1 == ~t6_pc~0; 136689#L435-7 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 136690#L445-7 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 136769#is_transmit6_triggered_returnLabel#8 activate_threads_#t~ret18#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 136679#L873-21 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 136677#L873-23 havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 136675#L743-3 assume 1 == ~M_E~0;~M_E~0 := 2; 136674#L743-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 136671#L748-3 assume !(1 == ~T2_E~0); 136669#L753-3 assume !(1 == ~T3_E~0); 136667#L758-3 assume !(1 == ~T4_E~0); 136665#L763-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 136663#L768-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 136661#L773-3 assume 1 == ~E_1~0;~E_1~0 := 2; 136659#L778-3 assume 1 == ~E_2~0;~E_2~0 := 2; 136657#L783-3 assume 1 == ~E_3~0;~E_3~0 := 2; 136655#L788-3 assume 1 == ~E_4~0;~E_4~0 := 2; 136653#L793-3 assume !(1 == ~E_5~0); 136651#L798-3 assume 1 == ~E_6~0;~E_6~0 := 2; 136649#L803-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 136647#L504-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 136639#L541-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 136637#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret20#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret20#1;havoc start_simulation_#t~ret20#1; 136635#L1043 assume !(0 == start_simulation_~tmp~3#1); 136633#L1043-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret19#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 136632#L504-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 136625#L541-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 136624#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret19#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret19#1;havoc stop_simulation_#t~ret19#1; 136622#L998 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 136620#L1005 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 136618#stop_simulation_returnLabel#1 start_simulation_#t~ret21#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret19#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret21#1;havoc start_simulation_#t~ret21#1; 136617#L1056 assume !(0 != start_simulation_~tmp___0~1#1); 130585#L1024-2 [2023-11-06 22:08:13,607 INFO L145 PredicateUnifier]: Initialized classic predicate unifier [2023-11-06 22:08:13,607 INFO L85 PathProgramCache]: Analyzing trace with hash -2100463913, now seen corresponding path program 1 times [2023-11-06 22:08:13,607 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-06 22:08:13,608 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1647404297] [2023-11-06 22:08:13,608 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-06 22:08:13,608 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-06 22:08:13,623 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-06 22:08:13,679 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-06 22:08:13,679 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-06 22:08:13,679 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1647404297] [2023-11-06 22:08:13,679 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1647404297] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-06 22:08:13,679 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-06 22:08:13,680 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-06 22:08:13,680 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1438675251] [2023-11-06 22:08:13,680 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-06 22:08:13,680 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-06 22:08:13,681 INFO L145 PredicateUnifier]: Initialized classic predicate unifier [2023-11-06 22:08:13,681 INFO L85 PathProgramCache]: Analyzing trace with hash 398231807, now seen corresponding path program 1 times [2023-11-06 22:08:13,681 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-06 22:08:13,681 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1112354768] [2023-11-06 22:08:13,681 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-06 22:08:13,682 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-06 22:08:13,693 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-06 22:08:13,722 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-06 22:08:13,723 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-06 22:08:13,723 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1112354768] [2023-11-06 22:08:13,723 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1112354768] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-06 22:08:13,723 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-06 22:08:13,723 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-06 22:08:13,723 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [381534253] [2023-11-06 22:08:13,724 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-06 22:08:13,724 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-06 22:08:13,724 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-06 22:08:13,725 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2023-11-06 22:08:13,725 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2023-11-06 22:08:13,725 INFO L87 Difference]: Start difference. First operand 7184 states and 10171 transitions. cyclomatic complexity: 2995 Second operand has 4 states, 4 states have (on average 20.5) internal successors, (82), 3 states have internal predecessors, (82), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-06 22:08:13,959 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-06 22:08:13,959 INFO L93 Difference]: Finished difference Result 14490 states and 20348 transitions. [2023-11-06 22:08:13,959 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 14490 states and 20348 transitions. [2023-11-06 22:08:14,023 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 14236 [2023-11-06 22:08:14,075 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 14490 states to 14490 states and 20348 transitions. [2023-11-06 22:08:14,075 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 14490 [2023-11-06 22:08:14,089 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 14490 [2023-11-06 22:08:14,089 INFO L73 IsDeterministic]: Start isDeterministic. Operand 14490 states and 20348 transitions. [2023-11-06 22:08:14,103 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-06 22:08:14,103 INFO L218 hiAutomatonCegarLoop]: Abstraction has 14490 states and 20348 transitions. [2023-11-06 22:08:14,118 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 14490 states and 20348 transitions. [2023-11-06 22:08:14,220 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 14490 to 8003. [2023-11-06 22:08:14,232 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 8003 states, 8003 states have (on average 1.405847807072348) internal successors, (11251), 8002 states have internal predecessors, (11251), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-06 22:08:14,254 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 8003 states to 8003 states and 11251 transitions. [2023-11-06 22:08:14,254 INFO L240 hiAutomatonCegarLoop]: Abstraction has 8003 states and 11251 transitions. [2023-11-06 22:08:14,254 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2023-11-06 22:08:14,256 INFO L428 stractBuchiCegarLoop]: Abstraction has 8003 states and 11251 transitions. [2023-11-06 22:08:14,256 INFO L335 stractBuchiCegarLoop]: ======== Iteration 17 ============ [2023-11-06 22:08:14,256 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 8003 states and 11251 transitions. [2023-11-06 22:08:14,281 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 7816 [2023-11-06 22:08:14,281 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-06 22:08:14,281 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-06 22:08:14,283 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-06 22:08:14,283 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-06 22:08:14,284 INFO L748 eck$LassoCheckResult]: Stem: 152482#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2; 152483#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~8#1;havoc main_~__retres1~8#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 152626#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret20#1, start_simulation_#t~ret21#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 152627#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 152138#L461 assume 1 == ~m_i~0;~m_st~0 := 0; 152139#L461-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 152698#L466-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 152844#L471-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 152232#L476-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 152233#L481-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 152401#L486-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 152248#L491-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 152249#L670 assume !(0 == ~M_E~0); 152639#L670-2 assume !(0 == ~T1_E~0); 152583#L675-1 assume !(0 == ~T2_E~0); 152584#L680-1 assume !(0 == ~T3_E~0); 152697#L685-1 assume !(0 == ~T4_E~0); 152646#L690-1 assume !(0 == ~T5_E~0); 152647#L695-1 assume !(0 == ~T6_E~0); 152743#L700-1 assume !(0 == ~E_1~0); 152728#L705-1 assume !(0 == ~E_2~0); 152729#L710-1 assume !(0 == ~E_3~0); 152582#L715-1 assume !(0 == ~E_4~0); 152512#L720-1 assume !(0 == ~E_5~0); 152513#L725-1 assume 0 == ~E_6~0;~E_6~0 := 1; 152559#L730-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 152614#L320 assume !(1 == ~m_pc~0); 152853#L320-2 is_master_triggered_~__retres1~0#1 := 0; 152854#L331 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 152444#is_master_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 152445#L825 assume !(0 != activate_threads_~tmp~1#1); 152781#L825-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 152782#L339 assume !(1 == ~t1_pc~0); 152608#L339-2 is_transmit1_triggered_~__retres1~1#1 := 0; 152609#L350 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 152230#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 152231#L833 assume !(0 != activate_threads_~tmp___0~0#1); 152835#L833-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 152836#L358 assume !(1 == ~t2_pc~0); 152718#L358-2 is_transmit2_triggered_~__retres1~2#1 := 0; 152719#L369 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 152819#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 152563#L841 assume !(0 != activate_threads_~tmp___1~0#1); 152564#L841-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 152786#L377 assume !(1 == ~t3_pc~0); 152787#L377-2 is_transmit3_triggered_~__retres1~3#1 := 0; 152686#L388 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 152687#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 152406#L849 assume !(0 != activate_threads_~tmp___2~0#1); 152407#L849-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 152333#L396 assume !(1 == ~t4_pc~0); 152334#L396-2 is_transmit4_triggered_~__retres1~4#1 := 0; 152166#L407 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 152167#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 152600#L857 assume !(0 != activate_threads_~tmp___3~0#1); 152601#L857-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 152382#L415 assume !(1 == ~t5_pc~0); 152383#L415-2 is_transmit5_triggered_~__retres1~5#1 := 0; 152615#L426 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 152616#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 152893#L865 assume !(0 != activate_threads_~tmp___4~0#1); 152892#L865-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 152675#L434 assume !(1 == ~t6_pc~0); 152676#L434-2 is_transmit6_triggered_~__retres1~6#1 := 0; 152895#L445 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 152894#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 152888#L873 assume !(0 != activate_threads_~tmp___5~0#1); 152887#L873-2 havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 152886#L743 assume !(1 == ~M_E~0); 152885#L743-2 assume !(1 == ~T1_E~0); 152884#L748-1 assume !(1 == ~T2_E~0); 152883#L753-1 assume !(1 == ~T3_E~0); 152882#L758-1 assume !(1 == ~T4_E~0); 152881#L763-1 assume !(1 == ~T5_E~0); 152880#L768-1 assume !(1 == ~T6_E~0); 152879#L773-1 assume !(1 == ~E_1~0); 152878#L778-1 assume !(1 == ~E_2~0); 152877#L783-1 assume !(1 == ~E_3~0); 152876#L788-1 assume !(1 == ~E_4~0); 152875#L793-1 assume !(1 == ~E_5~0); 152874#L798-1 assume 1 == ~E_6~0;~E_6~0 := 2; 152272#L803-1 assume { :end_inline_reset_delta_events } true; 152273#L1024-2 [2023-11-06 22:08:14,284 INFO L750 eck$LassoCheckResult]: Loop: 152273#L1024-2 assume !false; 154426#L1025 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 154421#L645-1 assume !false; 154419#L552 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 154417#L504 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 154410#L541 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 154406#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 154403#L556 assume !(0 != eval_~tmp~0#1); 154404#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 159217#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 159216#L670-3 assume 0 == ~M_E~0;~M_E~0 := 1; 159214#L670-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 159213#L675-3 assume !(0 == ~T2_E~0); 159212#L680-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 159211#L685-3 assume !(0 == ~T4_E~0); 159210#L690-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 159209#L695-3 assume !(0 == ~T6_E~0); 159208#L700-3 assume !(0 == ~E_1~0); 159207#L705-3 assume 0 == ~E_2~0;~E_2~0 := 1; 159206#L710-3 assume 0 == ~E_3~0;~E_3~0 := 1; 159205#L715-3 assume 0 == ~E_4~0;~E_4~0 := 1; 159203#L720-3 assume 0 == ~E_5~0;~E_5~0 := 1; 159200#L725-3 assume 0 == ~E_6~0;~E_6~0 := 1; 159201#L730-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 159906#L320-21 assume !(1 == ~m_pc~0); 159905#L320-23 is_master_triggered_~__retres1~0#1 := 0; 159904#L331-7 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 159903#is_master_triggered_returnLabel#8 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 159902#L825-21 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 159901#L825-23 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 159900#L339-21 assume 1 == ~t1_pc~0; 159898#L340-7 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 159897#L350-7 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 159896#is_transmit1_triggered_returnLabel#8 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 159895#L833-21 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 159894#L833-23 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 159402#L358-21 assume !(1 == ~t2_pc~0); 159400#L358-23 is_transmit2_triggered_~__retres1~2#1 := 0; 159398#L369-7 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 159395#is_transmit2_triggered_returnLabel#8 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 159393#L841-21 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 159391#L841-23 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 159388#L377-21 assume !(1 == ~t3_pc~0); 159386#L377-23 is_transmit3_triggered_~__retres1~3#1 := 0; 159383#L388-7 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 159381#is_transmit3_triggered_returnLabel#8 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 159379#L849-21 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 159377#L849-23 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 159375#L396-21 assume !(1 == ~t4_pc~0); 159373#L396-23 is_transmit4_triggered_~__retres1~4#1 := 0; 159371#L407-7 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 159368#is_transmit4_triggered_returnLabel#8 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 159365#L857-21 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 159363#L857-23 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 159361#L415-21 assume !(1 == ~t5_pc~0); 159359#L415-23 is_transmit5_triggered_~__retres1~5#1 := 0; 159356#L426-7 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 159352#is_transmit5_triggered_returnLabel#8 activate_threads_#t~ret17#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 159349#L865-21 assume !(0 != activate_threads_~tmp___4~0#1); 159347#L865-23 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 159344#L434-21 assume !(1 == ~t6_pc~0); 159342#L434-23 is_transmit6_triggered_~__retres1~6#1 := 0; 159338#L445-7 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 159334#is_transmit6_triggered_returnLabel#8 activate_threads_#t~ret18#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 159330#L873-21 assume !(0 != activate_threads_~tmp___5~0#1); 159327#L873-23 havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 159325#L743-3 assume 1 == ~M_E~0;~M_E~0 := 2; 159323#L743-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 159321#L748-3 assume !(1 == ~T2_E~0); 159319#L753-3 assume !(1 == ~T3_E~0); 159317#L758-3 assume !(1 == ~T4_E~0); 159315#L763-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 159313#L768-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 159310#L773-3 assume 1 == ~E_1~0;~E_1~0 := 2; 159305#L778-3 assume 1 == ~E_2~0;~E_2~0 := 2; 159300#L783-3 assume 1 == ~E_3~0;~E_3~0 := 2; 159294#L788-3 assume 1 == ~E_4~0;~E_4~0 := 2; 159289#L793-3 assume !(1 == ~E_5~0); 159084#L798-3 assume 1 == ~E_6~0;~E_6~0 := 2; 159082#L803-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 158245#L504-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 158237#L541-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 158235#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret20#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret20#1;havoc start_simulation_#t~ret20#1; 154453#L1043 assume !(0 == start_simulation_~tmp~3#1); 154450#L1043-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret19#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 154448#L504-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 154440#L541-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 154438#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret19#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret19#1;havoc stop_simulation_#t~ret19#1; 154436#L998 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 154434#L1005 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 154432#stop_simulation_returnLabel#1 start_simulation_#t~ret21#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret19#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret21#1;havoc start_simulation_#t~ret21#1; 154429#L1056 assume !(0 != start_simulation_~tmp___0~1#1); 152273#L1024-2 [2023-11-06 22:08:14,285 INFO L145 PredicateUnifier]: Initialized classic predicate unifier [2023-11-06 22:08:14,285 INFO L85 PathProgramCache]: Analyzing trace with hash 1760774297, now seen corresponding path program 1 times [2023-11-06 22:08:14,285 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-06 22:08:14,285 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [55371495] [2023-11-06 22:08:14,285 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-06 22:08:14,286 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-06 22:08:14,296 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-06 22:08:14,370 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-06 22:08:14,371 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-06 22:08:14,371 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [55371495] [2023-11-06 22:08:14,371 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [55371495] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-06 22:08:14,371 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-06 22:08:14,371 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-06 22:08:14,372 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1832523167] [2023-11-06 22:08:14,372 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-06 22:08:14,372 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-06 22:08:14,372 INFO L145 PredicateUnifier]: Initialized classic predicate unifier [2023-11-06 22:08:14,373 INFO L85 PathProgramCache]: Analyzing trace with hash -922603717, now seen corresponding path program 1 times [2023-11-06 22:08:14,373 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-06 22:08:14,373 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [832675345] [2023-11-06 22:08:14,373 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-06 22:08:14,373 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-06 22:08:14,384 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-06 22:08:14,458 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-06 22:08:14,459 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-06 22:08:14,459 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [832675345] [2023-11-06 22:08:14,459 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [832675345] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-06 22:08:14,459 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-06 22:08:14,460 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-06 22:08:14,460 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [99751079] [2023-11-06 22:08:14,460 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-06 22:08:14,460 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-06 22:08:14,461 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-06 22:08:14,461 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2023-11-06 22:08:14,461 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2023-11-06 22:08:14,462 INFO L87 Difference]: Start difference. First operand 8003 states and 11251 transitions. cyclomatic complexity: 3256 Second operand has 4 states, 4 states have (on average 20.5) internal successors, (82), 3 states have internal predecessors, (82), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-06 22:08:14,590 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-06 22:08:14,591 INFO L93 Difference]: Finished difference Result 10165 states and 14264 transitions. [2023-11-06 22:08:14,591 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 10165 states and 14264 transitions. [2023-11-06 22:08:14,646 INFO L131 ngComponentsAnalysis]: Automaton has 12 accepting balls. 10020 [2023-11-06 22:08:14,688 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 10165 states to 10165 states and 14264 transitions. [2023-11-06 22:08:14,689 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 10165 [2023-11-06 22:08:14,699 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 10165 [2023-11-06 22:08:14,699 INFO L73 IsDeterministic]: Start isDeterministic. Operand 10165 states and 14264 transitions. [2023-11-06 22:08:14,709 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-06 22:08:14,709 INFO L218 hiAutomatonCegarLoop]: Abstraction has 10165 states and 14264 transitions. [2023-11-06 22:08:14,720 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 10165 states and 14264 transitions. [2023-11-06 22:08:14,811 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 10165 to 6917. [2023-11-06 22:08:14,822 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 6917 states, 6917 states have (on average 1.398872343501518) internal successors, (9676), 6916 states have internal predecessors, (9676), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-06 22:08:14,845 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 6917 states to 6917 states and 9676 transitions. [2023-11-06 22:08:14,845 INFO L240 hiAutomatonCegarLoop]: Abstraction has 6917 states and 9676 transitions. [2023-11-06 22:08:14,846 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2023-11-06 22:08:14,846 INFO L428 stractBuchiCegarLoop]: Abstraction has 6917 states and 9676 transitions. [2023-11-06 22:08:14,846 INFO L335 stractBuchiCegarLoop]: ======== Iteration 18 ============ [2023-11-06 22:08:14,847 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 6917 states and 9676 transitions. [2023-11-06 22:08:14,873 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 6792 [2023-11-06 22:08:14,874 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-06 22:08:14,874 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-06 22:08:14,876 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-06 22:08:14,876 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-06 22:08:14,876 INFO L748 eck$LassoCheckResult]: Stem: 170658#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2; 170659#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~8#1;havoc main_~__retres1~8#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 170790#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret20#1, start_simulation_#t~ret21#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 170791#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 170316#L461 assume 1 == ~m_i~0;~m_st~0 := 0; 170317#L461-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 170861#L466-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 171003#L471-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 170411#L476-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 170412#L481-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 170576#L486-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 170427#L491-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 170428#L670 assume !(0 == ~M_E~0); 170806#L670-2 assume !(0 == ~T1_E~0); 170755#L675-1 assume !(0 == ~T2_E~0); 170756#L680-1 assume !(0 == ~T3_E~0); 170859#L685-1 assume !(0 == ~T4_E~0); 170815#L690-1 assume !(0 == ~T5_E~0); 170816#L695-1 assume !(0 == ~T6_E~0); 170902#L700-1 assume !(0 == ~E_1~0); 170888#L705-1 assume !(0 == ~E_2~0); 170889#L710-1 assume !(0 == ~E_3~0); 170754#L715-1 assume !(0 == ~E_4~0); 170684#L720-1 assume !(0 == ~E_5~0); 170685#L725-1 assume !(0 == ~E_6~0); 170734#L730-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 170777#L320 assume !(1 == ~m_pc~0); 170917#L320-2 is_master_triggered_~__retres1~0#1 := 0; 170622#L331 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 170616#is_master_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 170577#L825 assume !(0 != activate_threads_~tmp~1#1); 170578#L825-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 170586#L339 assume !(1 == ~t1_pc~0); 170587#L339-2 is_transmit1_triggered_~__retres1~1#1 := 0; 170553#L350 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 170407#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 170408#L833 assume !(0 != activate_threads_~tmp___0~0#1); 170431#L833-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 170342#L358 assume !(1 == ~t2_pc~0); 170343#L358-2 is_transmit2_triggered_~__retres1~2#1 := 0; 170879#L369 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 170793#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 170737#L841 assume !(0 != activate_threads_~tmp___1~0#1); 170572#L841-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 170573#L377 assume !(1 == ~t3_pc~0); 170840#L377-2 is_transmit3_triggered_~__retres1~3#1 := 0; 170841#L388 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 170340#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 170341#L849 assume !(0 != activate_threads_~tmp___2~0#1); 170581#L849-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 170512#L396 assume !(1 == ~t4_pc~0); 170513#L396-2 is_transmit4_triggered_~__retres1~4#1 := 0; 170344#L407 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 170345#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 170493#L857 assume !(0 != activate_threads_~tmp___3~0#1); 170477#L857-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 170478#L415 assume !(1 == ~t5_pc~0); 170560#L415-2 is_transmit5_triggered_~__retres1~5#1 := 0; 170611#L426 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 170630#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 170631#L865 assume !(0 != activate_threads_~tmp___4~0#1); 170384#L865-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 170385#L434 assume !(1 == ~t6_pc~0); 170715#L434-2 is_transmit6_triggered_~__retres1~6#1 := 0; 170716#L445 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 170782#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 170783#L873 assume !(0 != activate_threads_~tmp___5~0#1); 170595#L873-2 havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 170596#L743 assume !(1 == ~M_E~0); 170468#L743-2 assume !(1 == ~T1_E~0); 170469#L748-1 assume !(1 == ~T2_E~0); 170773#L753-1 assume !(1 == ~T3_E~0); 170774#L758-1 assume !(1 == ~T4_E~0); 170904#L763-1 assume !(1 == ~T5_E~0); 170950#L768-1 assume !(1 == ~T6_E~0); 170593#L773-1 assume !(1 == ~E_1~0); 170594#L778-1 assume !(1 == ~E_2~0); 170567#L783-1 assume !(1 == ~E_3~0); 170568#L788-1 assume !(1 == ~E_4~0); 170857#L793-1 assume !(1 == ~E_5~0); 170799#L798-1 assume !(1 == ~E_6~0); 170450#L803-1 assume { :end_inline_reset_delta_events } true; 170451#L1024-2 [2023-11-06 22:08:14,877 INFO L750 eck$LassoCheckResult]: Loop: 170451#L1024-2 assume !false; 175241#L1025 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 175236#L645-1 assume !false; 175234#L552 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 175232#L504 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 175223#L541 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 175217#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 175211#L556 assume !(0 != eval_~tmp~0#1); 175212#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 176550#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 176545#L670-3 assume 0 == ~M_E~0;~M_E~0 := 1; 176540#L670-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 176535#L675-3 assume !(0 == ~T2_E~0); 176530#L680-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 176525#L685-3 assume !(0 == ~T4_E~0); 176520#L690-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 176515#L695-3 assume !(0 == ~T6_E~0); 176509#L700-3 assume !(0 == ~E_1~0); 176504#L705-3 assume 0 == ~E_2~0;~E_2~0 := 1; 176499#L710-3 assume 0 == ~E_3~0;~E_3~0 := 1; 176494#L715-3 assume 0 == ~E_4~0;~E_4~0 := 1; 176489#L720-3 assume 0 == ~E_5~0;~E_5~0 := 1; 176483#L725-3 assume !(0 == ~E_6~0); 176476#L730-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 176470#L320-21 assume !(1 == ~m_pc~0); 176464#L320-23 is_master_triggered_~__retres1~0#1 := 0; 176457#L331-7 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 176450#is_master_triggered_returnLabel#8 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 176444#L825-21 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 176437#L825-23 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 176431#L339-21 assume 1 == ~t1_pc~0; 176423#L340-7 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 176416#L350-7 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 176410#is_transmit1_triggered_returnLabel#8 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 176406#L833-21 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 176401#L833-23 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 176328#L358-21 assume !(1 == ~t2_pc~0); 176324#L358-23 is_transmit2_triggered_~__retres1~2#1 := 0; 176318#L369-7 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 176314#is_transmit2_triggered_returnLabel#8 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 176310#L841-21 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 176305#L841-23 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 176299#L377-21 assume 1 == ~t3_pc~0; 176292#L378-7 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 176287#L388-7 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 176282#is_transmit3_triggered_returnLabel#8 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 176277#L849-21 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 176272#L849-23 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 176266#L396-21 assume !(1 == ~t4_pc~0); 176261#L396-23 is_transmit4_triggered_~__retres1~4#1 := 0; 176255#L407-7 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 176249#is_transmit4_triggered_returnLabel#8 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 176243#L857-21 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 176232#L857-23 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 176229#L415-21 assume !(1 == ~t5_pc~0); 176227#L415-23 is_transmit5_triggered_~__retres1~5#1 := 0; 176225#L426-7 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 176223#is_transmit5_triggered_returnLabel#8 activate_threads_#t~ret17#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 176221#L865-21 assume !(0 != activate_threads_~tmp___4~0#1); 176219#L865-23 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 176217#L434-21 assume !(1 == ~t6_pc~0); 176214#L434-23 is_transmit6_triggered_~__retres1~6#1 := 0; 176212#L445-7 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 176210#is_transmit6_triggered_returnLabel#8 activate_threads_#t~ret18#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 176208#L873-21 assume !(0 != activate_threads_~tmp___5~0#1); 176205#L873-23 havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 176203#L743-3 assume 1 == ~M_E~0;~M_E~0 := 2; 176201#L743-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 176199#L748-3 assume !(1 == ~T2_E~0); 176197#L753-3 assume !(1 == ~T3_E~0); 176195#L758-3 assume !(1 == ~T4_E~0); 176192#L763-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 176190#L768-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 176188#L773-3 assume 1 == ~E_1~0;~E_1~0 := 2; 176186#L778-3 assume 1 == ~E_2~0;~E_2~0 := 2; 176184#L783-3 assume 1 == ~E_3~0;~E_3~0 := 2; 176182#L788-3 assume 1 == ~E_4~0;~E_4~0 := 2; 176180#L793-3 assume !(1 == ~E_5~0); 176178#L798-3 assume !(1 == ~E_6~0); 176150#L803-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 176132#L504-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 176118#L541-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 175401#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret20#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret20#1;havoc start_simulation_#t~ret20#1; 175392#L1043 assume !(0 == start_simulation_~tmp~3#1); 175389#L1043-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret19#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 175387#L504-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 175379#L541-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 175377#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret19#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret19#1;havoc stop_simulation_#t~ret19#1; 175375#L998 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 175372#L1005 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 175370#stop_simulation_returnLabel#1 start_simulation_#t~ret21#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret19#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret21#1;havoc start_simulation_#t~ret21#1; 175369#L1056 assume !(0 != start_simulation_~tmp___0~1#1); 170451#L1024-2 [2023-11-06 22:08:14,878 INFO L145 PredicateUnifier]: Initialized classic predicate unifier [2023-11-06 22:08:14,878 INFO L85 PathProgramCache]: Analyzing trace with hash -2100463851, now seen corresponding path program 1 times [2023-11-06 22:08:14,878 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-06 22:08:14,878 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1614870180] [2023-11-06 22:08:14,879 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-06 22:08:14,879 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-06 22:08:14,894 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-06 22:08:14,895 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-06 22:08:14,907 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-06 22:08:14,958 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-06 22:08:14,959 INFO L145 PredicateUnifier]: Initialized classic predicate unifier [2023-11-06 22:08:14,960 INFO L85 PathProgramCache]: Analyzing trace with hash 1705073880, now seen corresponding path program 1 times [2023-11-06 22:08:14,960 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-06 22:08:14,960 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [297563964] [2023-11-06 22:08:14,960 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-06 22:08:14,961 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-06 22:08:14,978 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-06 22:08:15,017 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-06 22:08:15,018 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-06 22:08:15,018 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [297563964] [2023-11-06 22:08:15,018 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [297563964] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-06 22:08:15,018 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-06 22:08:15,019 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-06 22:08:15,019 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [98083736] [2023-11-06 22:08:15,019 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-06 22:08:15,020 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-06 22:08:15,020 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-06 22:08:15,020 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-06 22:08:15,021 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-06 22:08:15,021 INFO L87 Difference]: Start difference. First operand 6917 states and 9676 transitions. cyclomatic complexity: 2767 Second operand has 3 states, 3 states have (on average 30.666666666666668) internal successors, (92), 3 states have internal predecessors, (92), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-06 22:08:15,080 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-06 22:08:15,080 INFO L93 Difference]: Finished difference Result 7952 states and 11098 transitions. [2023-11-06 22:08:15,081 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 7952 states and 11098 transitions. [2023-11-06 22:08:15,122 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 7768 [2023-11-06 22:08:15,155 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 7952 states to 7952 states and 11098 transitions. [2023-11-06 22:08:15,155 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 7952 [2023-11-06 22:08:15,163 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 7952 [2023-11-06 22:08:15,163 INFO L73 IsDeterministic]: Start isDeterministic. Operand 7952 states and 11098 transitions. [2023-11-06 22:08:15,171 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-06 22:08:15,171 INFO L218 hiAutomatonCegarLoop]: Abstraction has 7952 states and 11098 transitions. [2023-11-06 22:08:15,180 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 7952 states and 11098 transitions. [2023-11-06 22:08:15,349 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 7952 to 7952. [2023-11-06 22:08:15,360 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 7952 states, 7952 states have (on average 1.3956237424547284) internal successors, (11098), 7951 states have internal predecessors, (11098), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-06 22:08:15,381 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 7952 states to 7952 states and 11098 transitions. [2023-11-06 22:08:15,381 INFO L240 hiAutomatonCegarLoop]: Abstraction has 7952 states and 11098 transitions. [2023-11-06 22:08:15,381 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-06 22:08:15,382 INFO L428 stractBuchiCegarLoop]: Abstraction has 7952 states and 11098 transitions. [2023-11-06 22:08:15,382 INFO L335 stractBuchiCegarLoop]: ======== Iteration 19 ============ [2023-11-06 22:08:15,382 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 7952 states and 11098 transitions. [2023-11-06 22:08:15,406 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 7768 [2023-11-06 22:08:15,407 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-06 22:08:15,407 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-06 22:08:15,408 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-06 22:08:15,409 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-06 22:08:15,409 INFO L748 eck$LassoCheckResult]: Stem: 185539#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2; 185540#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~8#1;havoc main_~__retres1~8#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 185679#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret20#1, start_simulation_#t~ret21#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 185680#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 185191#L461 assume 1 == ~m_i~0;~m_st~0 := 0; 185192#L461-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 185754#L466-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 185933#L471-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 185284#L476-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 185285#L481-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 185448#L486-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 185300#L491-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 185301#L670 assume !(0 == ~M_E~0); 185699#L670-2 assume !(0 == ~T1_E~0); 185638#L675-1 assume !(0 == ~T2_E~0); 185639#L680-1 assume 0 == ~T3_E~0;~T3_E~0 := 1; 185751#L685-1 assume !(0 == ~T4_E~0); 185843#L690-1 assume !(0 == ~T5_E~0); 185960#L695-1 assume !(0 == ~T6_E~0); 185799#L700-1 assume !(0 == ~E_1~0); 185800#L705-1 assume !(0 == ~E_2~0); 185927#L710-1 assume !(0 == ~E_3~0); 185637#L715-1 assume !(0 == ~E_4~0); 185564#L720-1 assume !(0 == ~E_5~0); 185565#L725-1 assume !(0 == ~E_6~0); 185614#L730-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 186002#L320 assume !(1 == ~m_pc~0); 185941#L320-2 is_master_triggered_~__retres1~0#1 := 0; 185942#L331 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 185491#is_master_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 185492#L825 assume !(0 != activate_threads_~tmp~1#1); 186001#L825-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 185459#L339 assume !(1 == ~t1_pc~0); 185460#L339-2 is_transmit1_triggered_~__retres1~1#1 := 0; 185425#L350 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 185280#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 185281#L833 assume !(0 != activate_threads_~tmp___0~0#1); 185304#L833-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 185995#L358 assume !(1 == ~t2_pc~0); 185994#L358-2 is_transmit2_triggered_~__retres1~2#1 := 0; 185993#L369 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 185682#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 185618#L841 assume !(0 != activate_threads_~tmp___1~0#1); 185619#L841-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 185991#L377 assume !(1 == ~t3_pc~0); 185989#L377-2 is_transmit3_triggered_~__retres1~3#1 := 0; 185988#L388 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 185987#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 185453#L849 assume !(0 != activate_threads_~tmp___2~0#1); 185454#L849-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 185385#L396 assume !(1 == ~t4_pc~0); 185386#L396-2 is_transmit4_triggered_~__retres1~4#1 := 0; 185219#L407 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 185220#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 185365#L857 assume !(0 != activate_threads_~tmp___3~0#1); 185349#L857-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 185350#L415 assume !(1 == ~t5_pc~0); 185432#L415-2 is_transmit5_triggered_~__retres1~5#1 := 0; 185668#L426 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 185505#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 185506#L865 assume !(0 != activate_threads_~tmp___4~0#1); 185257#L865-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 185258#L434 assume !(1 == ~t6_pc~0); 185596#L434-2 is_transmit6_triggered_~__retres1~6#1 := 0; 185597#L445 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 185764#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 185973#L873 assume !(0 != activate_threads_~tmp___5~0#1); 185468#L873-2 havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 185469#L743 assume !(1 == ~M_E~0); 185340#L743-2 assume !(1 == ~T1_E~0); 185341#L748-1 assume !(1 == ~T2_E~0); 185662#L753-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 185663#L758-1 assume !(1 == ~T4_E~0); 185802#L763-1 assume !(1 == ~T5_E~0); 185863#L768-1 assume !(1 == ~T6_E~0); 185466#L773-1 assume !(1 == ~E_1~0); 185467#L778-1 assume !(1 == ~E_2~0); 185439#L783-1 assume !(1 == ~E_3~0); 185440#L788-1 assume !(1 == ~E_4~0); 185749#L793-1 assume !(1 == ~E_5~0); 185689#L798-1 assume !(1 == ~E_6~0); 185323#L803-1 assume { :end_inline_reset_delta_events } true; 185324#L1024-2 [2023-11-06 22:08:15,410 INFO L750 eck$LassoCheckResult]: Loop: 185324#L1024-2 assume !false; 191130#L1025 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 191123#L645-1 assume !false; 191121#L552 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 191119#L504 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 191112#L541 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 191109#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 191107#L556 assume !(0 != eval_~tmp~0#1); 191108#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 192229#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 192227#L670-3 assume 0 == ~M_E~0;~M_E~0 := 1; 192225#L670-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 192223#L675-3 assume !(0 == ~T2_E~0); 192221#L680-3 assume !(0 == ~T3_E~0); 185744#L685-3 assume !(0 == ~T4_E~0); 185745#L690-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 185934#L695-3 assume !(0 == ~T6_E~0); 185756#L700-3 assume !(0 == ~E_1~0); 185757#L705-3 assume 0 == ~E_2~0;~E_2~0 := 1; 185363#L710-3 assume 0 == ~E_3~0;~E_3~0 := 1; 185364#L715-3 assume 0 == ~E_4~0;~E_4~0 := 1; 185620#L720-3 assume 0 == ~E_5~0;~E_5~0 := 1; 185621#L725-3 assume !(0 == ~E_6~0); 185704#L730-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 185464#L320-21 assume !(1 == ~m_pc~0); 185465#L320-23 is_master_triggered_~__retres1~0#1 := 0; 185910#L331-7 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 185911#is_master_triggered_returnLabel#8 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 192986#L825-21 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 192985#L825-23 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 192984#L339-21 assume !(1 == ~t1_pc~0); 192982#L339-23 is_transmit1_triggered_~__retres1~1#1 := 0; 192979#L350-7 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 192977#is_transmit1_triggered_returnLabel#8 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 192975#L833-21 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 192973#L833-23 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 192971#L358-21 assume !(1 == ~t2_pc~0); 189428#L358-23 is_transmit2_triggered_~__retres1~2#1 := 0; 192968#L369-7 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 192966#is_transmit2_triggered_returnLabel#8 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 192964#L841-21 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 192962#L841-23 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 192961#L377-21 assume !(1 == ~t3_pc~0); 192960#L377-23 is_transmit3_triggered_~__retres1~3#1 := 0; 192958#L388-7 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 192957#is_transmit3_triggered_returnLabel#8 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 192233#L849-21 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 192232#L849-23 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 192231#L396-21 assume !(1 == ~t4_pc~0); 192230#L396-23 is_transmit4_triggered_~__retres1~4#1 := 0; 192228#L407-7 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 192226#is_transmit4_triggered_returnLabel#8 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 192224#L857-21 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 192222#L857-23 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 192220#L415-21 assume !(1 == ~t5_pc~0); 192218#L415-23 is_transmit5_triggered_~__retres1~5#1 := 0; 192216#L426-7 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 192214#is_transmit5_triggered_returnLabel#8 activate_threads_#t~ret17#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 192212#L865-21 assume !(0 != activate_threads_~tmp___4~0#1); 192210#L865-23 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 192208#L434-21 assume !(1 == ~t6_pc~0); 192205#L434-23 is_transmit6_triggered_~__retres1~6#1 := 0; 192203#L445-7 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 192201#is_transmit6_triggered_returnLabel#8 activate_threads_#t~ret18#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 192199#L873-21 assume !(0 != activate_threads_~tmp___5~0#1); 192197#L873-23 havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 192195#L743-3 assume 1 == ~M_E~0;~M_E~0 := 2; 191501#L743-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 191500#L748-3 assume !(1 == ~T2_E~0); 191460#L753-3 assume !(1 == ~T3_E~0); 191458#L758-3 assume !(1 == ~T4_E~0); 191456#L763-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 191454#L768-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 191452#L773-3 assume 1 == ~E_1~0;~E_1~0 := 2; 191450#L778-3 assume 1 == ~E_2~0;~E_2~0 := 2; 191447#L783-3 assume 1 == ~E_3~0;~E_3~0 := 2; 191445#L788-3 assume 1 == ~E_4~0;~E_4~0 := 2; 191443#L793-3 assume !(1 == ~E_5~0); 191430#L798-3 assume !(1 == ~E_6~0); 191396#L803-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 191358#L504-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 191345#L541-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 191340#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret20#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret20#1;havoc start_simulation_#t~ret20#1; 191334#L1043 assume !(0 == start_simulation_~tmp~3#1); 191331#L1043-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret19#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 191151#L504-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 191143#L541-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 191141#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret19#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret19#1;havoc stop_simulation_#t~ret19#1; 191139#L998 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 191137#L1005 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 191135#stop_simulation_returnLabel#1 start_simulation_#t~ret21#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret19#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret21#1;havoc start_simulation_#t~ret21#1; 191133#L1056 assume !(0 != start_simulation_~tmp___0~1#1); 185324#L1024-2 [2023-11-06 22:08:15,410 INFO L145 PredicateUnifier]: Initialized classic predicate unifier [2023-11-06 22:08:15,410 INFO L85 PathProgramCache]: Analyzing trace with hash -1585374703, now seen corresponding path program 1 times [2023-11-06 22:08:15,410 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-06 22:08:15,411 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1917038466] [2023-11-06 22:08:15,411 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-06 22:08:15,411 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-06 22:08:15,422 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-06 22:08:15,475 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-06 22:08:15,476 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-06 22:08:15,476 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1917038466] [2023-11-06 22:08:15,476 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1917038466] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-06 22:08:15,476 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-06 22:08:15,477 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-06 22:08:15,477 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [350017381] [2023-11-06 22:08:15,477 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-06 22:08:15,478 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-06 22:08:15,479 INFO L145 PredicateUnifier]: Initialized classic predicate unifier [2023-11-06 22:08:15,479 INFO L85 PathProgramCache]: Analyzing trace with hash 2034702488, now seen corresponding path program 1 times [2023-11-06 22:08:15,479 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-06 22:08:15,479 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1234861508] [2023-11-06 22:08:15,479 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-06 22:08:15,480 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-06 22:08:15,492 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-06 22:08:15,526 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-06 22:08:15,527 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-06 22:08:15,527 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1234861508] [2023-11-06 22:08:15,527 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1234861508] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-06 22:08:15,527 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-06 22:08:15,527 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-06 22:08:15,528 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [53562556] [2023-11-06 22:08:15,528 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-06 22:08:15,529 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-06 22:08:15,529 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-06 22:08:15,530 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2023-11-06 22:08:15,530 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2023-11-06 22:08:15,530 INFO L87 Difference]: Start difference. First operand 7952 states and 11098 transitions. cyclomatic complexity: 3154 Second operand has 4 states, 4 states have (on average 20.5) internal successors, (82), 3 states have internal predecessors, (82), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-06 22:08:15,631 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-06 22:08:15,632 INFO L93 Difference]: Finished difference Result 13759 states and 19220 transitions. [2023-11-06 22:08:15,632 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 13759 states and 19220 transitions. [2023-11-06 22:08:15,695 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 13584 [2023-11-06 22:08:15,746 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 13759 states to 13759 states and 19220 transitions. [2023-11-06 22:08:15,746 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 13759 [2023-11-06 22:08:15,755 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 13759 [2023-11-06 22:08:15,756 INFO L73 IsDeterministic]: Start isDeterministic. Operand 13759 states and 19220 transitions. [2023-11-06 22:08:15,767 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-06 22:08:15,767 INFO L218 hiAutomatonCegarLoop]: Abstraction has 13759 states and 19220 transitions. [2023-11-06 22:08:15,780 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 13759 states and 19220 transitions. [2023-11-06 22:08:15,862 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 13759 to 6917. [2023-11-06 22:08:15,871 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 6917 states, 6917 states have (on average 1.396414630620211) internal successors, (9659), 6916 states have internal predecessors, (9659), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-06 22:08:15,889 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 6917 states to 6917 states and 9659 transitions. [2023-11-06 22:08:15,890 INFO L240 hiAutomatonCegarLoop]: Abstraction has 6917 states and 9659 transitions. [2023-11-06 22:08:15,890 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2023-11-06 22:08:15,891 INFO L428 stractBuchiCegarLoop]: Abstraction has 6917 states and 9659 transitions. [2023-11-06 22:08:15,893 INFO L335 stractBuchiCegarLoop]: ======== Iteration 20 ============ [2023-11-06 22:08:15,893 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 6917 states and 9659 transitions. [2023-11-06 22:08:15,920 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 6792 [2023-11-06 22:08:15,921 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-06 22:08:15,921 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-06 22:08:15,923 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-06 22:08:15,923 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-06 22:08:15,924 INFO L748 eck$LassoCheckResult]: Stem: 207252#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2; 207253#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~8#1;havoc main_~__retres1~8#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 207380#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret20#1, start_simulation_#t~ret21#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 207381#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 206912#L461 assume 1 == ~m_i~0;~m_st~0 := 0; 206913#L461-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 207443#L466-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 207594#L471-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 207005#L476-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 207006#L481-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 207169#L486-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 207020#L491-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 207021#L670 assume !(0 == ~M_E~0); 207395#L670-2 assume !(0 == ~T1_E~0); 207347#L675-1 assume !(0 == ~T2_E~0); 207348#L680-1 assume !(0 == ~T3_E~0); 207441#L685-1 assume !(0 == ~T4_E~0); 207401#L690-1 assume !(0 == ~T5_E~0); 207402#L695-1 assume !(0 == ~T6_E~0); 207485#L700-1 assume !(0 == ~E_1~0); 207470#L705-1 assume !(0 == ~E_2~0); 207471#L710-1 assume !(0 == ~E_3~0); 207346#L715-1 assume !(0 == ~E_4~0); 207277#L720-1 assume !(0 == ~E_5~0); 207278#L725-1 assume !(0 == ~E_6~0); 207326#L730-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 207370#L320 assume !(1 == ~m_pc~0); 207507#L320-2 is_master_triggered_~__retres1~0#1 := 0; 207215#L331 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 207209#is_master_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 207170#L825 assume !(0 != activate_threads_~tmp~1#1); 207171#L825-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 207178#L339 assume !(1 == ~t1_pc~0); 207179#L339-2 is_transmit1_triggered_~__retres1~1#1 := 0; 207146#L350 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 207001#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 207002#L833 assume !(0 != activate_threads_~tmp___0~0#1); 207024#L833-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 206938#L358 assume !(1 == ~t2_pc~0); 206939#L358-2 is_transmit2_triggered_~__retres1~2#1 := 0; 207461#L369 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 207383#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 207329#L841 assume !(0 != activate_threads_~tmp___1~0#1); 207165#L841-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 207166#L377 assume !(1 == ~t3_pc~0); 207423#L377-2 is_transmit3_triggered_~__retres1~3#1 := 0; 207424#L388 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 206936#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 206937#L849 assume !(0 != activate_threads_~tmp___2~0#1); 207173#L849-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 207104#L396 assume !(1 == ~t4_pc~0); 207105#L396-2 is_transmit4_triggered_~__retres1~4#1 := 0; 206940#L407 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 206941#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 207085#L857 assume !(0 != activate_threads_~tmp___3~0#1); 207070#L857-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 207071#L415 assume !(1 == ~t5_pc~0); 207153#L415-2 is_transmit5_triggered_~__retres1~5#1 := 0; 207204#L426 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 207222#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 207223#L865 assume !(0 != activate_threads_~tmp___4~0#1); 206978#L865-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 206979#L434 assume !(1 == ~t6_pc~0); 207308#L434-2 is_transmit6_triggered_~__retres1~6#1 := 0; 207309#L445 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 207374#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 207375#L873 assume !(0 != activate_threads_~tmp___5~0#1); 207188#L873-2 havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 207189#L743 assume !(1 == ~M_E~0); 207060#L743-2 assume !(1 == ~T1_E~0); 207061#L748-1 assume !(1 == ~T2_E~0); 207365#L753-1 assume !(1 == ~T3_E~0); 207366#L758-1 assume !(1 == ~T4_E~0); 207487#L763-1 assume !(1 == ~T5_E~0); 207543#L768-1 assume !(1 == ~T6_E~0); 207186#L773-1 assume !(1 == ~E_1~0); 207187#L778-1 assume !(1 == ~E_2~0); 207160#L783-1 assume !(1 == ~E_3~0); 207161#L788-1 assume !(1 == ~E_4~0); 207439#L793-1 assume !(1 == ~E_5~0); 207389#L798-1 assume !(1 == ~E_6~0); 207043#L803-1 assume { :end_inline_reset_delta_events } true; 207044#L1024-2 [2023-11-06 22:08:15,924 INFO L750 eck$LassoCheckResult]: Loop: 207044#L1024-2 assume !false; 210441#L1025 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 210437#L645-1 assume !false; 210435#L552 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 210431#L504 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 210423#L541 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 210415#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 210412#L556 assume !(0 != eval_~tmp~0#1); 210413#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 212845#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 212843#L670-3 assume 0 == ~M_E~0;~M_E~0 := 1; 212841#L670-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 212839#L675-3 assume !(0 == ~T2_E~0); 212837#L680-3 assume !(0 == ~T3_E~0); 212835#L685-3 assume !(0 == ~T4_E~0); 212833#L690-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 212831#L695-3 assume !(0 == ~T6_E~0); 212828#L700-3 assume !(0 == ~E_1~0); 212826#L705-3 assume 0 == ~E_2~0;~E_2~0 := 1; 212824#L710-3 assume 0 == ~E_3~0;~E_3~0 := 1; 212822#L715-3 assume 0 == ~E_4~0;~E_4~0 := 1; 212820#L720-3 assume 0 == ~E_5~0;~E_5~0 := 1; 212818#L725-3 assume !(0 == ~E_6~0); 212815#L730-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 212813#L320-21 assume !(1 == ~m_pc~0); 212811#L320-23 is_master_triggered_~__retres1~0#1 := 0; 212809#L331-7 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 212807#is_master_triggered_returnLabel#8 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 212805#L825-21 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 212802#L825-23 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 212800#L339-21 assume !(1 == ~t1_pc~0); 212798#L339-23 is_transmit1_triggered_~__retres1~1#1 := 0; 212795#L350-7 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 212793#is_transmit1_triggered_returnLabel#8 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 212791#L833-21 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 212788#L833-23 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 212786#L358-21 assume !(1 == ~t2_pc~0); 212358#L358-23 is_transmit2_triggered_~__retres1~2#1 := 0; 212783#L369-7 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 212781#is_transmit2_triggered_returnLabel#8 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 212779#L841-21 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 212778#L841-23 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 212777#L377-21 assume 1 == ~t3_pc~0; 212775#L378-7 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 212774#L388-7 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 212773#is_transmit3_triggered_returnLabel#8 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 212772#L849-21 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 212770#L849-23 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 212768#L396-21 assume !(1 == ~t4_pc~0); 212766#L396-23 is_transmit4_triggered_~__retres1~4#1 := 0; 212764#L407-7 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 212762#is_transmit4_triggered_returnLabel#8 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 212760#L857-21 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 212758#L857-23 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 212756#L415-21 assume !(1 == ~t5_pc~0); 212754#L415-23 is_transmit5_triggered_~__retres1~5#1 := 0; 212752#L426-7 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 212750#is_transmit5_triggered_returnLabel#8 activate_threads_#t~ret17#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 212748#L865-21 assume !(0 != activate_threads_~tmp___4~0#1); 212746#L865-23 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 212744#L434-21 assume !(1 == ~t6_pc~0); 212741#L434-23 is_transmit6_triggered_~__retres1~6#1 := 0; 212739#L445-7 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 212736#is_transmit6_triggered_returnLabel#8 activate_threads_#t~ret18#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 212734#L873-21 assume !(0 != activate_threads_~tmp___5~0#1); 212732#L873-23 havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 212730#L743-3 assume 1 == ~M_E~0;~M_E~0 := 2; 212728#L743-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 212726#L748-3 assume !(1 == ~T2_E~0); 212723#L753-3 assume !(1 == ~T3_E~0); 212721#L758-3 assume !(1 == ~T4_E~0); 212719#L763-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 210503#L768-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 210500#L773-3 assume 1 == ~E_1~0;~E_1~0 := 2; 210498#L778-3 assume 1 == ~E_2~0;~E_2~0 := 2; 210496#L783-3 assume 1 == ~E_3~0;~E_3~0 := 2; 210494#L788-3 assume 1 == ~E_4~0;~E_4~0 := 2; 210492#L793-3 assume !(1 == ~E_5~0); 210490#L798-3 assume !(1 == ~E_6~0); 210488#L803-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 210486#L504-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 210478#L541-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 210476#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret20#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret20#1;havoc start_simulation_#t~ret20#1; 210473#L1043 assume !(0 == start_simulation_~tmp~3#1); 210470#L1043-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret19#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 210468#L504-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 210460#L541-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 210458#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret19#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret19#1;havoc stop_simulation_#t~ret19#1; 210456#L998 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 210454#L1005 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 210452#stop_simulation_returnLabel#1 start_simulation_#t~ret21#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret19#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret21#1;havoc start_simulation_#t~ret21#1; 210450#L1056 assume !(0 != start_simulation_~tmp___0~1#1); 207044#L1024-2 [2023-11-06 22:08:15,928 INFO L145 PredicateUnifier]: Initialized classic predicate unifier [2023-11-06 22:08:15,928 INFO L85 PathProgramCache]: Analyzing trace with hash -2100463851, now seen corresponding path program 2 times [2023-11-06 22:08:15,928 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-06 22:08:15,928 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1805448833] [2023-11-06 22:08:15,929 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-06 22:08:15,929 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-06 22:08:15,944 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-06 22:08:15,945 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-06 22:08:15,956 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-06 22:08:15,999 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-06 22:08:15,999 INFO L145 PredicateUnifier]: Initialized classic predicate unifier [2023-11-06 22:08:16,000 INFO L85 PathProgramCache]: Analyzing trace with hash -529927751, now seen corresponding path program 1 times [2023-11-06 22:08:16,000 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-06 22:08:16,001 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1700199311] [2023-11-06 22:08:16,001 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-06 22:08:16,001 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-06 22:08:16,016 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-06 22:08:16,064 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-06 22:08:16,065 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-06 22:08:16,065 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1700199311] [2023-11-06 22:08:16,065 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1700199311] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-06 22:08:16,065 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-06 22:08:16,065 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-06 22:08:16,066 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1025342056] [2023-11-06 22:08:16,066 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-06 22:08:16,066 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-06 22:08:16,066 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-06 22:08:16,067 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-06 22:08:16,067 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-06 22:08:16,067 INFO L87 Difference]: Start difference. First operand 6917 states and 9659 transitions. cyclomatic complexity: 2750 Second operand has 3 states, 3 states have (on average 30.666666666666668) internal successors, (92), 3 states have internal predecessors, (92), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-06 22:08:16,180 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-06 22:08:16,181 INFO L93 Difference]: Finished difference Result 10384 states and 14430 transitions. [2023-11-06 22:08:16,181 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 10384 states and 14430 transitions. [2023-11-06 22:08:16,235 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 10188 [2023-11-06 22:08:16,277 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 10384 states to 10384 states and 14430 transitions. [2023-11-06 22:08:16,277 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 10384 [2023-11-06 22:08:16,285 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 10384 [2023-11-06 22:08:16,285 INFO L73 IsDeterministic]: Start isDeterministic. Operand 10384 states and 14430 transitions. [2023-11-06 22:08:16,295 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-06 22:08:16,295 INFO L218 hiAutomatonCegarLoop]: Abstraction has 10384 states and 14430 transitions. [2023-11-06 22:08:16,303 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 10384 states and 14430 transitions. [2023-11-06 22:08:16,420 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 10384 to 10380. [2023-11-06 22:08:16,432 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 10380 states, 10380 states have (on average 1.3897880539499037) internal successors, (14426), 10379 states have internal predecessors, (14426), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-06 22:08:16,464 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 10380 states to 10380 states and 14426 transitions. [2023-11-06 22:08:16,464 INFO L240 hiAutomatonCegarLoop]: Abstraction has 10380 states and 14426 transitions. [2023-11-06 22:08:16,464 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-06 22:08:16,465 INFO L428 stractBuchiCegarLoop]: Abstraction has 10380 states and 14426 transitions. [2023-11-06 22:08:16,465 INFO L335 stractBuchiCegarLoop]: ======== Iteration 21 ============ [2023-11-06 22:08:16,465 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 10380 states and 14426 transitions. [2023-11-06 22:08:16,503 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 10184 [2023-11-06 22:08:16,503 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-06 22:08:16,503 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-06 22:08:16,505 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-06 22:08:16,505 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-06 22:08:16,506 INFO L748 eck$LassoCheckResult]: Stem: 224563#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2; 224564#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~8#1;havoc main_~__retres1~8#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 224704#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret20#1, start_simulation_#t~ret21#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 224705#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 224219#L461 assume 1 == ~m_i~0;~m_st~0 := 0; 224220#L461-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 224768#L466-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 224911#L471-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 224311#L476-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 224312#L481-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 224481#L486-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 224328#L491-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 224329#L670 assume !(0 == ~M_E~0); 224717#L670-2 assume !(0 == ~T1_E~0); 224665#L675-1 assume !(0 == ~T2_E~0); 224666#L680-1 assume !(0 == ~T3_E~0); 224767#L685-1 assume !(0 == ~T4_E~0); 224725#L690-1 assume !(0 == ~T5_E~0); 224726#L695-1 assume !(0 == ~T6_E~0); 224814#L700-1 assume !(0 == ~E_1~0); 224800#L705-1 assume !(0 == ~E_2~0); 224801#L710-1 assume !(0 == ~E_3~0); 224664#L715-1 assume !(0 == ~E_4~0); 224592#L720-1 assume 0 == ~E_5~0;~E_5~0 := 1; 224593#L725-1 assume !(0 == ~E_6~0); 224691#L730-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 224692#L320 assume !(1 == ~m_pc~0); 224828#L320-2 is_master_triggered_~__retres1~0#1 := 0; 224533#L331 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 224534#is_master_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 224482#L825 assume !(0 != activate_threads_~tmp~1#1); 224483#L825-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 224850#L339 assume !(1 == ~t1_pc~0); 224985#L339-2 is_transmit1_triggered_~__retres1~1#1 := 0; 224984#L350 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 224983#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 224982#L833 assume !(0 != activate_threads_~tmp___0~0#1); 224903#L833-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 224244#L358 assume !(1 == ~t2_pc~0); 224245#L358-2 is_transmit2_triggered_~__retres1~2#1 := 0; 224791#L369 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 224891#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 224978#L841 assume !(0 != activate_threads_~tmp___1~0#1); 224477#L841-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 224478#L377 assume !(1 == ~t3_pc~0); 224749#L377-2 is_transmit3_triggered_~__retres1~3#1 := 0; 224750#L388 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 224240#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 224241#L849 assume !(0 != activate_threads_~tmp___2~0#1); 224972#L849-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 224971#L396 assume !(1 == ~t4_pc~0); 224970#L396-2 is_transmit4_triggered_~__retres1~4#1 := 0; 224969#L407 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 224968#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 224681#L857 assume !(0 != activate_threads_~tmp___3~0#1); 224682#L857-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 224967#L415 assume !(1 == ~t5_pc~0); 224514#L415-2 is_transmit5_triggered_~__retres1~5#1 := 0; 224515#L426 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 224966#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 224965#L865 assume !(0 != activate_threads_~tmp___4~0#1); 224964#L865-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 224963#L434 assume !(1 == ~t6_pc~0); 224961#L434-2 is_transmit6_triggered_~__retres1~6#1 := 0; 224960#L445 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 224697#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 224698#L873 assume !(0 != activate_threads_~tmp___5~0#1); 224778#L873-2 havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 224902#L743 assume !(1 == ~M_E~0); 224369#L743-2 assume !(1 == ~T1_E~0); 224370#L748-1 assume !(1 == ~T2_E~0); 224882#L753-1 assume !(1 == ~T3_E~0); 224956#L758-1 assume !(1 == ~T4_E~0); 224955#L763-1 assume !(1 == ~T5_E~0); 224954#L768-1 assume !(1 == ~T6_E~0); 224953#L773-1 assume !(1 == ~E_1~0); 224952#L778-1 assume !(1 == ~E_2~0); 224472#L783-1 assume !(1 == ~E_3~0); 224473#L788-1 assume !(1 == ~E_4~0); 224765#L793-1 assume 1 == ~E_5~0;~E_5~0 := 2; 224712#L798-1 assume !(1 == ~E_6~0); 224350#L803-1 assume { :end_inline_reset_delta_events } true; 224351#L1024-2 [2023-11-06 22:08:16,506 INFO L750 eck$LassoCheckResult]: Loop: 224351#L1024-2 assume !false; 227439#L1025 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 227431#L645-1 assume !false; 227429#L552 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 227427#L504 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 227418#L541 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 227415#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 227409#L556 assume !(0 != eval_~tmp~0#1); 227410#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 227811#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 227809#L670-3 assume 0 == ~M_E~0;~M_E~0 := 1; 227807#L670-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 227805#L675-3 assume !(0 == ~T2_E~0); 227803#L680-3 assume !(0 == ~T3_E~0); 227801#L685-3 assume !(0 == ~T4_E~0); 227799#L690-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 227797#L695-3 assume !(0 == ~T6_E~0); 227795#L700-3 assume !(0 == ~E_1~0); 227793#L705-3 assume 0 == ~E_2~0;~E_2~0 := 1; 227791#L710-3 assume 0 == ~E_3~0;~E_3~0 := 1; 227789#L715-3 assume 0 == ~E_4~0;~E_4~0 := 1; 227779#L720-3 assume 0 == ~E_5~0;~E_5~0 := 1; 227775#L725-3 assume !(0 == ~E_6~0); 227771#L730-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 227766#L320-21 assume !(1 == ~m_pc~0); 227763#L320-23 is_master_triggered_~__retres1~0#1 := 0; 227754#L331-7 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 227752#is_master_triggered_returnLabel#8 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 227750#L825-21 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 227747#L825-23 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 227744#L339-21 assume !(1 == ~t1_pc~0); 227741#L339-23 is_transmit1_triggered_~__retres1~1#1 := 0; 227736#L350-7 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 227733#is_transmit1_triggered_returnLabel#8 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 227730#L833-21 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 227727#L833-23 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 227723#L358-21 assume !(1 == ~t2_pc~0); 227335#L358-23 is_transmit2_triggered_~__retres1~2#1 := 0; 227719#L369-7 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 227716#is_transmit2_triggered_returnLabel#8 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 227713#L841-21 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 227710#L841-23 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 227708#L377-21 assume !(1 == ~t3_pc~0); 227705#L377-23 is_transmit3_triggered_~__retres1~3#1 := 0; 227700#L388-7 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 227697#is_transmit3_triggered_returnLabel#8 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 227694#L849-21 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 227691#L849-23 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 227687#L396-21 assume !(1 == ~t4_pc~0); 227684#L396-23 is_transmit4_triggered_~__retres1~4#1 := 0; 227681#L407-7 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 227678#is_transmit4_triggered_returnLabel#8 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 227675#L857-21 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 227671#L857-23 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 227667#L415-21 assume !(1 == ~t5_pc~0); 227663#L415-23 is_transmit5_triggered_~__retres1~5#1 := 0; 227659#L426-7 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 227655#is_transmit5_triggered_returnLabel#8 activate_threads_#t~ret17#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 227650#L865-21 assume !(0 != activate_threads_~tmp___4~0#1); 227646#L865-23 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 227642#L434-21 assume !(1 == ~t6_pc~0); 227636#L434-23 is_transmit6_triggered_~__retres1~6#1 := 0; 227632#L445-7 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 227628#is_transmit6_triggered_returnLabel#8 activate_threads_#t~ret18#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 227625#L873-21 assume !(0 != activate_threads_~tmp___5~0#1); 227620#L873-23 havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 227616#L743-3 assume 1 == ~M_E~0;~M_E~0 := 2; 227612#L743-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 227608#L748-3 assume !(1 == ~T2_E~0); 227604#L753-3 assume !(1 == ~T3_E~0); 227599#L758-3 assume !(1 == ~T4_E~0); 227595#L763-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 227591#L768-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 227587#L773-3 assume 1 == ~E_1~0;~E_1~0 := 2; 227583#L778-3 assume 1 == ~E_2~0;~E_2~0 := 2; 227579#L783-3 assume 1 == ~E_3~0;~E_3~0 := 2; 227574#L788-3 assume 1 == ~E_4~0;~E_4~0 := 2; 227570#L793-3 assume 1 == ~E_5~0;~E_5~0 := 2; 227566#L798-3 assume !(1 == ~E_6~0); 227563#L803-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 227554#L504-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 227544#L541-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 227540#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret20#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret20#1;havoc start_simulation_#t~ret20#1; 227534#L1043 assume !(0 == start_simulation_~tmp~3#1); 227530#L1043-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret19#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 227487#L504-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 227477#L541-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 227473#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret19#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret19#1;havoc stop_simulation_#t~ret19#1; 227467#L998 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 227461#L1005 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 227456#stop_simulation_returnLabel#1 start_simulation_#t~ret21#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret19#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret21#1;havoc start_simulation_#t~ret21#1; 227449#L1056 assume !(0 != start_simulation_~tmp___0~1#1); 224351#L1024-2 [2023-11-06 22:08:16,508 INFO L145 PredicateUnifier]: Initialized classic predicate unifier [2023-11-06 22:08:16,508 INFO L85 PathProgramCache]: Analyzing trace with hash 1633801745, now seen corresponding path program 1 times [2023-11-06 22:08:16,508 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-06 22:08:16,508 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [774373960] [2023-11-06 22:08:16,509 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-06 22:08:16,509 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-06 22:08:16,525 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-06 22:08:16,584 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-06 22:08:16,585 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-06 22:08:16,585 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [774373960] [2023-11-06 22:08:16,585 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [774373960] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-06 22:08:16,585 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-06 22:08:16,585 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-06 22:08:16,586 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1502112666] [2023-11-06 22:08:16,586 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-06 22:08:16,586 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-06 22:08:16,587 INFO L145 PredicateUnifier]: Initialized classic predicate unifier [2023-11-06 22:08:16,587 INFO L85 PathProgramCache]: Analyzing trace with hash -980401130, now seen corresponding path program 1 times [2023-11-06 22:08:16,587 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-06 22:08:16,587 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1730682944] [2023-11-06 22:08:16,587 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-06 22:08:16,588 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-06 22:08:16,602 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-06 22:08:16,658 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-06 22:08:16,659 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-06 22:08:16,659 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1730682944] [2023-11-06 22:08:16,659 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1730682944] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-06 22:08:16,659 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-06 22:08:16,659 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2023-11-06 22:08:16,660 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [503263841] [2023-11-06 22:08:16,660 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-06 22:08:16,660 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-06 22:08:16,660 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-06 22:08:16,661 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2023-11-06 22:08:16,661 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2023-11-06 22:08:16,661 INFO L87 Difference]: Start difference. First operand 10380 states and 14426 transitions. cyclomatic complexity: 4054 Second operand has 4 states, 4 states have (on average 20.5) internal successors, (82), 3 states have internal predecessors, (82), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-06 22:08:16,842 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-06 22:08:16,842 INFO L93 Difference]: Finished difference Result 19203 states and 26700 transitions. [2023-11-06 22:08:16,842 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 19203 states and 26700 transitions. [2023-11-06 22:08:16,942 INFO L131 ngComponentsAnalysis]: Automaton has 20 accepting balls. 18216 [2023-11-06 22:08:17,024 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 19203 states to 19203 states and 26700 transitions. [2023-11-06 22:08:17,024 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 19203 [2023-11-06 22:08:17,037 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 19203 [2023-11-06 22:08:17,038 INFO L73 IsDeterministic]: Start isDeterministic. Operand 19203 states and 26700 transitions. [2023-11-06 22:08:17,056 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-06 22:08:17,056 INFO L218 hiAutomatonCegarLoop]: Abstraction has 19203 states and 26700 transitions. [2023-11-06 22:08:17,070 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 19203 states and 26700 transitions. [2023-11-06 22:08:17,213 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 19203 to 9837. [2023-11-06 22:08:17,224 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 9837 states, 9837 states have (on average 1.3888380603842634) internal successors, (13662), 9836 states have internal predecessors, (13662), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-06 22:08:17,249 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 9837 states to 9837 states and 13662 transitions. [2023-11-06 22:08:17,250 INFO L240 hiAutomatonCegarLoop]: Abstraction has 9837 states and 13662 transitions. [2023-11-06 22:08:17,250 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2023-11-06 22:08:17,251 INFO L428 stractBuchiCegarLoop]: Abstraction has 9837 states and 13662 transitions. [2023-11-06 22:08:17,252 INFO L335 stractBuchiCegarLoop]: ======== Iteration 22 ============ [2023-11-06 22:08:17,252 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 9837 states and 13662 transitions. [2023-11-06 22:08:17,287 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 9700 [2023-11-06 22:08:17,288 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-06 22:08:17,288 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-06 22:08:17,290 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-06 22:08:17,291 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-06 22:08:17,291 INFO L748 eck$LassoCheckResult]: Stem: 254153#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2; 254154#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~8#1;havoc main_~__retres1~8#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 254289#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret20#1, start_simulation_#t~ret21#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 254290#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 253814#L461 assume 1 == ~m_i~0;~m_st~0 := 0; 253815#L461-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 254358#L466-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 254508#L471-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 253907#L476-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 253908#L481-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 254073#L486-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 253923#L491-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 253924#L670 assume !(0 == ~M_E~0); 254301#L670-2 assume !(0 == ~T1_E~0); 254255#L675-1 assume !(0 == ~T2_E~0); 254256#L680-1 assume !(0 == ~T3_E~0); 254357#L685-1 assume !(0 == ~T4_E~0); 254310#L690-1 assume !(0 == ~T5_E~0); 254311#L695-1 assume !(0 == ~T6_E~0); 254403#L700-1 assume !(0 == ~E_1~0); 254389#L705-1 assume !(0 == ~E_2~0); 254390#L710-1 assume !(0 == ~E_3~0); 254254#L715-1 assume !(0 == ~E_4~0); 254183#L720-1 assume !(0 == ~E_5~0); 254184#L725-1 assume !(0 == ~E_6~0); 254233#L730-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 254279#L320 assume !(1 == ~m_pc~0); 254425#L320-2 is_master_triggered_~__retres1~0#1 := 0; 254124#L331 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 254116#is_master_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 254074#L825 assume !(0 != activate_threads_~tmp~1#1); 254075#L825-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 254080#L339 assume !(1 == ~t1_pc~0); 254081#L339-2 is_transmit1_triggered_~__retres1~1#1 := 0; 254050#L350 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 253905#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 253906#L833 assume !(0 != activate_threads_~tmp___0~0#1); 253929#L833-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 253839#L358 assume !(1 == ~t2_pc~0); 253840#L358-2 is_transmit2_triggered_~__retres1~2#1 := 0; 254381#L369 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 254292#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 254237#L841 assume !(0 != activate_threads_~tmp___1~0#1); 254069#L841-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 254070#L377 assume !(1 == ~t3_pc~0); 254335#L377-2 is_transmit3_triggered_~__retres1~3#1 := 0; 254336#L388 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 253835#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 253836#L849 assume !(0 != activate_threads_~tmp___2~0#1); 254079#L849-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 254005#L396 assume !(1 == ~t4_pc~0); 254006#L396-2 is_transmit4_triggered_~__retres1~4#1 := 0; 253841#L407 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 253842#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 253988#L857 assume !(0 != activate_threads_~tmp___3~0#1); 253973#L857-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 253974#L415 assume !(1 == ~t5_pc~0); 254055#L415-2 is_transmit5_triggered_~__retres1~5#1 := 0; 254107#L426 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 254127#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 254128#L865 assume !(0 != activate_threads_~tmp___4~0#1); 253882#L865-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 253883#L434 assume !(1 == ~t6_pc~0); 254214#L434-2 is_transmit6_triggered_~__retres1~6#1 := 0; 254215#L445 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 254283#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 254284#L873 assume !(0 != activate_threads_~tmp___5~0#1); 254095#L873-2 havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 254096#L743 assume !(1 == ~M_E~0); 253965#L743-2 assume !(1 == ~T1_E~0); 253966#L748-1 assume !(1 == ~T2_E~0); 254274#L753-1 assume !(1 == ~T3_E~0); 254275#L758-1 assume !(1 == ~T4_E~0); 254407#L763-1 assume !(1 == ~T5_E~0); 254458#L768-1 assume !(1 == ~T6_E~0); 254089#L773-1 assume !(1 == ~E_1~0); 254090#L778-1 assume !(1 == ~E_2~0); 254064#L783-1 assume !(1 == ~E_3~0); 254065#L788-1 assume !(1 == ~E_4~0); 254354#L793-1 assume !(1 == ~E_5~0); 254298#L798-1 assume !(1 == ~E_6~0); 253946#L803-1 assume { :end_inline_reset_delta_events } true; 253947#L1024-2 [2023-11-06 22:08:17,292 INFO L750 eck$LassoCheckResult]: Loop: 253947#L1024-2 assume !false; 257286#L1025 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 257278#L645-1 assume !false; 257256#L552 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 257197#L504 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 257189#L541 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 257187#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 257184#L556 assume !(0 != eval_~tmp~0#1); 257185#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 257713#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 257711#L670-3 assume 0 == ~M_E~0;~M_E~0 := 1; 257709#L670-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 257706#L675-3 assume !(0 == ~T2_E~0); 257704#L680-3 assume !(0 == ~T3_E~0); 257702#L685-3 assume !(0 == ~T4_E~0); 257700#L690-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 257698#L695-3 assume !(0 == ~T6_E~0); 257696#L700-3 assume !(0 == ~E_1~0); 257695#L705-3 assume 0 == ~E_2~0;~E_2~0 := 1; 257693#L710-3 assume 0 == ~E_3~0;~E_3~0 := 1; 257691#L715-3 assume 0 == ~E_4~0;~E_4~0 := 1; 257689#L720-3 assume !(0 == ~E_5~0); 257687#L725-3 assume !(0 == ~E_6~0); 257685#L730-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 257682#L320-21 assume !(1 == ~m_pc~0); 257680#L320-23 is_master_triggered_~__retres1~0#1 := 0; 257678#L331-7 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 257676#is_master_triggered_returnLabel#8 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 257674#L825-21 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 257672#L825-23 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 257669#L339-21 assume !(1 == ~t1_pc~0); 257667#L339-23 is_transmit1_triggered_~__retres1~1#1 := 0; 257664#L350-7 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 257662#is_transmit1_triggered_returnLabel#8 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 257660#L833-21 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 257657#L833-23 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 257654#L358-21 assume !(1 == ~t2_pc~0); 256469#L358-23 is_transmit2_triggered_~__retres1~2#1 := 0; 257648#L369-7 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 257644#is_transmit2_triggered_returnLabel#8 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 257640#L841-21 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 257635#L841-23 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 257630#L377-21 assume !(1 == ~t3_pc~0); 257626#L377-23 is_transmit3_triggered_~__retres1~3#1 := 0; 257621#L388-7 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 257616#is_transmit3_triggered_returnLabel#8 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 257612#L849-21 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 257608#L849-23 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 257605#L396-21 assume !(1 == ~t4_pc~0); 257601#L396-23 is_transmit4_triggered_~__retres1~4#1 := 0; 257597#L407-7 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 257594#is_transmit4_triggered_returnLabel#8 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 257590#L857-21 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 257586#L857-23 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 257581#L415-21 assume !(1 == ~t5_pc~0); 257577#L415-23 is_transmit5_triggered_~__retres1~5#1 := 0; 257573#L426-7 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 257568#is_transmit5_triggered_returnLabel#8 activate_threads_#t~ret17#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 257564#L865-21 assume !(0 != activate_threads_~tmp___4~0#1); 257560#L865-23 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 257551#L434-21 assume !(1 == ~t6_pc~0); 257548#L434-23 is_transmit6_triggered_~__retres1~6#1 := 0; 257546#L445-7 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 257544#is_transmit6_triggered_returnLabel#8 activate_threads_#t~ret18#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 257542#L873-21 assume !(0 != activate_threads_~tmp___5~0#1); 257540#L873-23 havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 257537#L743-3 assume 1 == ~M_E~0;~M_E~0 := 2; 257535#L743-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 257533#L748-3 assume !(1 == ~T2_E~0); 257531#L753-3 assume !(1 == ~T3_E~0); 257529#L758-3 assume !(1 == ~T4_E~0); 257527#L763-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 257525#L768-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 257523#L773-3 assume 1 == ~E_1~0;~E_1~0 := 2; 257521#L778-3 assume 1 == ~E_2~0;~E_2~0 := 2; 257519#L783-3 assume 1 == ~E_3~0;~E_3~0 := 2; 257507#L788-3 assume 1 == ~E_4~0;~E_4~0 := 2; 257501#L793-3 assume !(1 == ~E_5~0); 257494#L798-3 assume !(1 == ~E_6~0); 257491#L803-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 257413#L504-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 257400#L541-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 257393#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret20#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret20#1;havoc start_simulation_#t~ret20#1; 257386#L1043 assume !(0 == start_simulation_~tmp~3#1); 257378#L1043-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret19#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 257369#L504-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 257356#L541-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 257350#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret19#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret19#1;havoc stop_simulation_#t~ret19#1; 257343#L998 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 257338#L1005 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 257333#stop_simulation_returnLabel#1 start_simulation_#t~ret21#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret19#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret21#1;havoc start_simulation_#t~ret21#1; 257328#L1056 assume !(0 != start_simulation_~tmp___0~1#1); 253947#L1024-2 [2023-11-06 22:08:17,292 INFO L145 PredicateUnifier]: Initialized classic predicate unifier [2023-11-06 22:08:17,292 INFO L85 PathProgramCache]: Analyzing trace with hash -2100463851, now seen corresponding path program 3 times [2023-11-06 22:08:17,293 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-06 22:08:17,293 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1050481322] [2023-11-06 22:08:17,293 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-06 22:08:17,294 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-06 22:08:17,309 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-06 22:08:17,309 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-06 22:08:17,326 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-06 22:08:17,347 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-06 22:08:17,348 INFO L145 PredicateUnifier]: Initialized classic predicate unifier [2023-11-06 22:08:17,349 INFO L85 PathProgramCache]: Analyzing trace with hash 1067351834, now seen corresponding path program 1 times [2023-11-06 22:08:17,349 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-06 22:08:17,349 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1204664608] [2023-11-06 22:08:17,349 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-06 22:08:17,349 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-06 22:08:17,365 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-06 22:08:17,424 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-06 22:08:17,424 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-06 22:08:17,424 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1204664608] [2023-11-06 22:08:17,425 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1204664608] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-06 22:08:17,425 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-06 22:08:17,425 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2023-11-06 22:08:17,425 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [649111695] [2023-11-06 22:08:17,425 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-06 22:08:17,426 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-06 22:08:17,426 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-06 22:08:17,426 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2023-11-06 22:08:17,427 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2023-11-06 22:08:17,427 INFO L87 Difference]: Start difference. First operand 9837 states and 13662 transitions. cyclomatic complexity: 3833 Second operand has 5 states, 5 states have (on average 18.4) internal successors, (92), 5 states have internal predecessors, (92), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-06 22:08:17,632 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-06 22:08:17,632 INFO L93 Difference]: Finished difference Result 17657 states and 24270 transitions. [2023-11-06 22:08:17,632 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 17657 states and 24270 transitions. [2023-11-06 22:08:17,711 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 17468 [2023-11-06 22:08:17,772 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 17657 states to 17657 states and 24270 transitions. [2023-11-06 22:08:17,772 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 17657 [2023-11-06 22:08:17,783 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 17657 [2023-11-06 22:08:17,783 INFO L73 IsDeterministic]: Start isDeterministic. Operand 17657 states and 24270 transitions. [2023-11-06 22:08:17,796 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-06 22:08:17,797 INFO L218 hiAutomatonCegarLoop]: Abstraction has 17657 states and 24270 transitions. [2023-11-06 22:08:17,808 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 17657 states and 24270 transitions. [2023-11-06 22:08:17,917 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 17657 to 9909. [2023-11-06 22:08:17,927 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 9909 states, 9909 states have (on average 1.3860127157129882) internal successors, (13734), 9908 states have internal predecessors, (13734), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-06 22:08:17,947 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 9909 states to 9909 states and 13734 transitions. [2023-11-06 22:08:17,947 INFO L240 hiAutomatonCegarLoop]: Abstraction has 9909 states and 13734 transitions. [2023-11-06 22:08:17,948 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 9 states. [2023-11-06 22:08:17,948 INFO L428 stractBuchiCegarLoop]: Abstraction has 9909 states and 13734 transitions. [2023-11-06 22:08:17,948 INFO L335 stractBuchiCegarLoop]: ======== Iteration 23 ============ [2023-11-06 22:08:17,948 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 9909 states and 13734 transitions. [2023-11-06 22:08:18,050 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 9772 [2023-11-06 22:08:18,050 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-06 22:08:18,050 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-06 22:08:18,052 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-06 22:08:18,052 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-06 22:08:18,052 INFO L748 eck$LassoCheckResult]: Stem: 281668#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2; 281669#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~8#1;havoc main_~__retres1~8#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 281809#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret20#1, start_simulation_#t~ret21#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 281810#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 281325#L461 assume 1 == ~m_i~0;~m_st~0 := 0; 281326#L461-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 281873#L466-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 282032#L471-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 281418#L476-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 281419#L481-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 281588#L486-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 281435#L491-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 281436#L670 assume !(0 == ~M_E~0); 281823#L670-2 assume !(0 == ~T1_E~0); 281772#L675-1 assume !(0 == ~T2_E~0); 281773#L680-1 assume !(0 == ~T3_E~0); 281872#L685-1 assume !(0 == ~T4_E~0); 281831#L690-1 assume !(0 == ~T5_E~0); 281832#L695-1 assume !(0 == ~T6_E~0); 281919#L700-1 assume !(0 == ~E_1~0); 281903#L705-1 assume !(0 == ~E_2~0); 281904#L710-1 assume !(0 == ~E_3~0); 281770#L715-1 assume !(0 == ~E_4~0); 281697#L720-1 assume !(0 == ~E_5~0); 281698#L725-1 assume !(0 == ~E_6~0); 281748#L730-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 281799#L320 assume !(1 == ~m_pc~0); 281933#L320-2 is_master_triggered_~__retres1~0#1 := 0; 281639#L331 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 281631#is_master_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 281589#L825 assume !(0 != activate_threads_~tmp~1#1); 281590#L825-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 281594#L339 assume !(1 == ~t1_pc~0); 281595#L339-2 is_transmit1_triggered_~__retres1~1#1 := 0; 281565#L350 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 281416#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 281417#L833 assume !(0 != activate_threads_~tmp___0~0#1); 281441#L833-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 281350#L358 assume !(1 == ~t2_pc~0); 281351#L358-2 is_transmit2_triggered_~__retres1~2#1 := 0; 281895#L369 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 281812#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 281752#L841 assume !(0 != activate_threads_~tmp___1~0#1); 281584#L841-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 281585#L377 assume !(1 == ~t3_pc~0); 281853#L377-2 is_transmit3_triggered_~__retres1~3#1 := 0; 281854#L388 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 281346#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 281347#L849 assume !(0 != activate_threads_~tmp___2~0#1); 281593#L849-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 281521#L396 assume !(1 == ~t4_pc~0); 281522#L396-2 is_transmit4_triggered_~__retres1~4#1 := 0; 281352#L407 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 281353#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 281505#L857 assume !(0 != activate_threads_~tmp___3~0#1); 281489#L857-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 281490#L415 assume !(1 == ~t5_pc~0); 281570#L415-2 is_transmit5_triggered_~__retres1~5#1 := 0; 281622#L426 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 281642#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 281643#L865 assume !(0 != activate_threads_~tmp___4~0#1); 281392#L865-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 281393#L434 assume !(1 == ~t6_pc~0); 281729#L434-2 is_transmit6_triggered_~__retres1~6#1 := 0; 281730#L445 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 281803#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 281804#L873 assume !(0 != activate_threads_~tmp___5~0#1); 281610#L873-2 havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 281611#L743 assume !(1 == ~M_E~0); 281479#L743-2 assume !(1 == ~T1_E~0); 281480#L748-1 assume !(1 == ~T2_E~0); 281793#L753-1 assume !(1 == ~T3_E~0); 281794#L758-1 assume !(1 == ~T4_E~0); 281921#L763-1 assume !(1 == ~T5_E~0); 281971#L768-1 assume !(1 == ~T6_E~0); 281603#L773-1 assume !(1 == ~E_1~0); 281604#L778-1 assume !(1 == ~E_2~0); 281579#L783-1 assume !(1 == ~E_3~0); 281580#L788-1 assume !(1 == ~E_4~0); 281870#L793-1 assume !(1 == ~E_5~0); 281819#L798-1 assume !(1 == ~E_6~0); 281458#L803-1 assume { :end_inline_reset_delta_events } true; 281459#L1024-2 [2023-11-06 22:08:18,053 INFO L750 eck$LassoCheckResult]: Loop: 281459#L1024-2 assume !false; 283364#L1025 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 283360#L645-1 assume !false; 283359#L552 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 283358#L504 assume !(0 == ~m_st~0); 283353#L508 assume !(0 == ~t1_st~0); 283354#L512 assume !(0 == ~t2_st~0); 283356#L516 assume !(0 == ~t3_st~0); 283351#L520 assume !(0 == ~t4_st~0); 283352#L524 assume !(0 == ~t5_st~0); 283355#L528 assume !(0 == ~t6_st~0);exists_runnable_thread_~__retres1~7#1 := 0; 283357#L541 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 282992#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 282993#L556 assume !(0 != eval_~tmp~0#1); 283475#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 283474#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 283473#L670-3 assume 0 == ~M_E~0;~M_E~0 := 1; 283472#L670-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 283471#L675-3 assume !(0 == ~T2_E~0); 283470#L680-3 assume !(0 == ~T3_E~0); 283469#L685-3 assume !(0 == ~T4_E~0); 283468#L690-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 283467#L695-3 assume !(0 == ~T6_E~0); 283466#L700-3 assume !(0 == ~E_1~0); 283465#L705-3 assume 0 == ~E_2~0;~E_2~0 := 1; 283464#L710-3 assume 0 == ~E_3~0;~E_3~0 := 1; 283463#L715-3 assume 0 == ~E_4~0;~E_4~0 := 1; 283462#L720-3 assume !(0 == ~E_5~0); 283461#L725-3 assume !(0 == ~E_6~0); 283460#L730-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 283459#L320-21 assume !(1 == ~m_pc~0); 283458#L320-23 is_master_triggered_~__retres1~0#1 := 0; 283457#L331-7 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 283456#is_master_triggered_returnLabel#8 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 283455#L825-21 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 283454#L825-23 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 283453#L339-21 assume !(1 == ~t1_pc~0); 283452#L339-23 is_transmit1_triggered_~__retres1~1#1 := 0; 283450#L350-7 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 283449#is_transmit1_triggered_returnLabel#8 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 283448#L833-21 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 283447#L833-23 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 283446#L358-21 assume !(1 == ~t2_pc~0); 283262#L358-23 is_transmit2_triggered_~__retres1~2#1 := 0; 283445#L369-7 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 283444#is_transmit2_triggered_returnLabel#8 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 283443#L841-21 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 283442#L841-23 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 283441#L377-21 assume !(1 == ~t3_pc~0); 283440#L377-23 is_transmit3_triggered_~__retres1~3#1 := 0; 283438#L388-7 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 283437#is_transmit3_triggered_returnLabel#8 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 283436#L849-21 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 283435#L849-23 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 283434#L396-21 assume !(1 == ~t4_pc~0); 283433#L396-23 is_transmit4_triggered_~__retres1~4#1 := 0; 283432#L407-7 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 283431#is_transmit4_triggered_returnLabel#8 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 283430#L857-21 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 283429#L857-23 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 283428#L415-21 assume !(1 == ~t5_pc~0); 283427#L415-23 is_transmit5_triggered_~__retres1~5#1 := 0; 283426#L426-7 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 283425#is_transmit5_triggered_returnLabel#8 activate_threads_#t~ret17#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 283424#L865-21 assume !(0 != activate_threads_~tmp___4~0#1); 283423#L865-23 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 283422#L434-21 assume !(1 == ~t6_pc~0); 283420#L434-23 is_transmit6_triggered_~__retres1~6#1 := 0; 283419#L445-7 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 283418#is_transmit6_triggered_returnLabel#8 activate_threads_#t~ret18#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 283417#L873-21 assume !(0 != activate_threads_~tmp___5~0#1); 283416#L873-23 havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 283415#L743-3 assume 1 == ~M_E~0;~M_E~0 := 2; 283414#L743-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 283413#L748-3 assume !(1 == ~T2_E~0); 283412#L753-3 assume !(1 == ~T3_E~0); 283411#L758-3 assume !(1 == ~T4_E~0); 283410#L763-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 283409#L768-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 283408#L773-3 assume 1 == ~E_1~0;~E_1~0 := 2; 283407#L778-3 assume 1 == ~E_2~0;~E_2~0 := 2; 283406#L783-3 assume 1 == ~E_3~0;~E_3~0 := 2; 283405#L788-3 assume 1 == ~E_4~0;~E_4~0 := 2; 283404#L793-3 assume !(1 == ~E_5~0); 283403#L798-3 assume !(1 == ~E_6~0); 283402#L803-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 283401#L504-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 283393#L541-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 283391#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret20#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret20#1;havoc start_simulation_#t~ret20#1; 283388#L1043 assume !(0 == start_simulation_~tmp~3#1); 283386#L1043-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret19#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 283385#L504-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 283378#L541-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 283377#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret19#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret19#1;havoc stop_simulation_#t~ret19#1; 283376#L998 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 283375#L1005 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 283373#stop_simulation_returnLabel#1 start_simulation_#t~ret21#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret19#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret21#1;havoc start_simulation_#t~ret21#1; 283371#L1056 assume !(0 != start_simulation_~tmp___0~1#1); 281459#L1024-2 [2023-11-06 22:08:18,053 INFO L145 PredicateUnifier]: Initialized classic predicate unifier [2023-11-06 22:08:18,053 INFO L85 PathProgramCache]: Analyzing trace with hash -2100463851, now seen corresponding path program 4 times [2023-11-06 22:08:18,053 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-06 22:08:18,055 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [773035486] [2023-11-06 22:08:18,056 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-06 22:08:18,056 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-06 22:08:18,072 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-06 22:08:18,073 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-06 22:08:18,081 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-06 22:08:18,104 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-06 22:08:18,104 INFO L145 PredicateUnifier]: Initialized classic predicate unifier [2023-11-06 22:08:18,105 INFO L85 PathProgramCache]: Analyzing trace with hash -1223614487, now seen corresponding path program 1 times [2023-11-06 22:08:18,105 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-06 22:08:18,105 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1427346645] [2023-11-06 22:08:18,105 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-06 22:08:18,105 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-06 22:08:18,120 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-06 22:08:18,208 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-06 22:08:18,209 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-06 22:08:18,209 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1427346645] [2023-11-06 22:08:18,209 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1427346645] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-06 22:08:18,209 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-06 22:08:18,209 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2023-11-06 22:08:18,209 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1941860490] [2023-11-06 22:08:18,210 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-06 22:08:18,210 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-06 22:08:18,210 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-06 22:08:18,211 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2023-11-06 22:08:18,211 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2023-11-06 22:08:18,211 INFO L87 Difference]: Start difference. First operand 9909 states and 13734 transitions. cyclomatic complexity: 3833 Second operand has 5 states, 5 states have (on average 19.6) internal successors, (98), 5 states have internal predecessors, (98), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-06 22:08:18,453 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-06 22:08:18,453 INFO L93 Difference]: Finished difference Result 18121 states and 24727 transitions. [2023-11-06 22:08:18,453 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 18121 states and 24727 transitions. [2023-11-06 22:08:18,532 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 17964 [2023-11-06 22:08:18,596 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 18121 states to 18121 states and 24727 transitions. [2023-11-06 22:08:18,597 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 18121 [2023-11-06 22:08:18,608 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 18121 [2023-11-06 22:08:18,608 INFO L73 IsDeterministic]: Start isDeterministic. Operand 18121 states and 24727 transitions. [2023-11-06 22:08:18,622 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-06 22:08:18,623 INFO L218 hiAutomatonCegarLoop]: Abstraction has 18121 states and 24727 transitions. [2023-11-06 22:08:18,635 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 18121 states and 24727 transitions. [2023-11-06 22:08:18,747 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 18121 to 10131. [2023-11-06 22:08:18,757 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 10131 states, 10131 states have (on average 1.3713355048859934) internal successors, (13893), 10130 states have internal predecessors, (13893), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-06 22:08:18,778 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 10131 states to 10131 states and 13893 transitions. [2023-11-06 22:08:18,779 INFO L240 hiAutomatonCegarLoop]: Abstraction has 10131 states and 13893 transitions. [2023-11-06 22:08:18,779 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2023-11-06 22:08:18,780 INFO L428 stractBuchiCegarLoop]: Abstraction has 10131 states and 13893 transitions. [2023-11-06 22:08:18,780 INFO L335 stractBuchiCegarLoop]: ======== Iteration 24 ============ [2023-11-06 22:08:18,780 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 10131 states and 13893 transitions. [2023-11-06 22:08:18,810 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 9994 [2023-11-06 22:08:18,810 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-06 22:08:18,810 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-06 22:08:18,812 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-06 22:08:18,812 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-06 22:08:18,813 INFO L748 eck$LassoCheckResult]: Stem: 309713#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2; 309714#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~8#1;havoc main_~__retres1~8#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 309848#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret20#1, start_simulation_#t~ret21#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 309849#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 309367#L461 assume 1 == ~m_i~0;~m_st~0 := 0; 309368#L461-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 309923#L466-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 310092#L471-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 309461#L476-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 309462#L481-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 309627#L486-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 309476#L491-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 309477#L670 assume !(0 == ~M_E~0); 309867#L670-2 assume !(0 == ~T1_E~0); 309811#L675-1 assume !(0 == ~T2_E~0); 309812#L680-1 assume !(0 == ~T3_E~0); 309921#L685-1 assume !(0 == ~T4_E~0); 309876#L690-1 assume !(0 == ~T5_E~0); 309877#L695-1 assume !(0 == ~T6_E~0); 309967#L700-1 assume !(0 == ~E_1~0); 309951#L705-1 assume !(0 == ~E_2~0); 309952#L710-1 assume !(0 == ~E_3~0); 309810#L715-1 assume !(0 == ~E_4~0); 309740#L720-1 assume !(0 == ~E_5~0); 309741#L725-1 assume !(0 == ~E_6~0); 309789#L730-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 309838#L320 assume !(1 == ~m_pc~0); 309987#L320-2 is_master_triggered_~__retres1~0#1 := 0; 309678#L331 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 309671#is_master_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 309628#L825 assume !(0 != activate_threads_~tmp~1#1); 309629#L825-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 309638#L339 assume !(1 == ~t1_pc~0); 309639#L339-2 is_transmit1_triggered_~__retres1~1#1 := 0; 309603#L350 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 309457#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 309458#L833 assume !(0 != activate_threads_~tmp___0~0#1); 309480#L833-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 309392#L358 assume !(1 == ~t2_pc~0); 309393#L358-2 is_transmit2_triggered_~__retres1~2#1 := 0; 309942#L369 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 309852#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 309793#L841 assume !(0 != activate_threads_~tmp___1~0#1); 309623#L841-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 309624#L377 assume !(1 == ~t3_pc~0); 309898#L377-2 is_transmit3_triggered_~__retres1~3#1 := 0; 309899#L388 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 309390#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 309391#L849 assume !(0 != activate_threads_~tmp___2~0#1); 309633#L849-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 309560#L396 assume !(1 == ~t4_pc~0); 309561#L396-2 is_transmit4_triggered_~__retres1~4#1 := 0; 309394#L407 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 309395#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 309541#L857 assume !(0 != activate_threads_~tmp___3~0#1); 309526#L857-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 309527#L415 assume !(1 == ~t5_pc~0); 309610#L415-2 is_transmit5_triggered_~__retres1~5#1 := 0; 309665#L426 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 309685#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 309686#L865 assume !(0 != activate_threads_~tmp___4~0#1); 309434#L865-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 309435#L434 assume !(1 == ~t6_pc~0); 309773#L434-2 is_transmit6_triggered_~__retres1~6#1 := 0; 309774#L445 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 309842#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 309843#L873 assume !(0 != activate_threads_~tmp___5~0#1); 309648#L873-2 havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 309649#L743 assume !(1 == ~M_E~0); 309517#L743-2 assume !(1 == ~T1_E~0); 309518#L748-1 assume !(1 == ~T2_E~0); 309832#L753-1 assume !(1 == ~T3_E~0); 309833#L758-1 assume !(1 == ~T4_E~0); 309969#L763-1 assume !(1 == ~T5_E~0); 310029#L768-1 assume !(1 == ~T6_E~0); 309646#L773-1 assume !(1 == ~E_1~0); 309647#L778-1 assume !(1 == ~E_2~0); 309618#L783-1 assume !(1 == ~E_3~0); 309619#L788-1 assume !(1 == ~E_4~0); 309919#L793-1 assume !(1 == ~E_5~0); 309861#L798-1 assume !(1 == ~E_6~0); 309500#L803-1 assume { :end_inline_reset_delta_events } true; 309501#L1024-2 [2023-11-06 22:08:18,814 INFO L750 eck$LassoCheckResult]: Loop: 309501#L1024-2 assume !false; 313927#L1025 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 313919#L645-1 assume !false; 313918#L552 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 313900#L504 assume !(0 == ~m_st~0); 313896#L508 assume !(0 == ~t1_st~0); 313897#L512 assume !(0 == ~t2_st~0); 313899#L516 assume !(0 == ~t3_st~0); 313893#L520 assume !(0 == ~t4_st~0); 313895#L524 assume !(0 == ~t5_st~0); 313898#L528 assume !(0 == ~t6_st~0);exists_runnable_thread_~__retres1~7#1 := 0; 313817#L541 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 313769#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 313770#L556 assume !(0 != eval_~tmp~0#1); 314397#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 314391#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 314385#L670-3 assume 0 == ~M_E~0;~M_E~0 := 1; 314380#L670-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 314375#L675-3 assume !(0 == ~T2_E~0); 314369#L680-3 assume !(0 == ~T3_E~0); 314363#L685-3 assume !(0 == ~T4_E~0); 314362#L690-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 314361#L695-3 assume !(0 == ~T6_E~0); 314360#L700-3 assume !(0 == ~E_1~0); 314359#L705-3 assume 0 == ~E_2~0;~E_2~0 := 1; 314358#L710-3 assume 0 == ~E_3~0;~E_3~0 := 1; 314357#L715-3 assume 0 == ~E_4~0;~E_4~0 := 1; 314349#L720-3 assume !(0 == ~E_5~0); 314347#L725-3 assume !(0 == ~E_6~0); 314345#L730-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 314344#L320-21 assume !(1 == ~m_pc~0); 314343#L320-23 is_master_triggered_~__retres1~0#1 := 0; 314342#L331-7 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 314340#is_master_triggered_returnLabel#8 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 314338#L825-21 assume !(0 != activate_threads_~tmp~1#1); 314337#L825-23 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 314336#L339-21 assume 1 == ~t1_pc~0; 314334#L340-7 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 314309#L350-7 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 314305#is_transmit1_triggered_returnLabel#8 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 314301#L833-21 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 314296#L833-23 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 314291#L358-21 assume !(1 == ~t2_pc~0); 314160#L358-23 is_transmit2_triggered_~__retres1~2#1 := 0; 314281#L369-7 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 314275#is_transmit2_triggered_returnLabel#8 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 314270#L841-21 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 314265#L841-23 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 314230#L377-21 assume !(1 == ~t3_pc~0); 314220#L377-23 is_transmit3_triggered_~__retres1~3#1 := 0; 314212#L388-7 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 314208#is_transmit3_triggered_returnLabel#8 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 314205#L849-21 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 314200#L849-23 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 314196#L396-21 assume !(1 == ~t4_pc~0); 314192#L396-23 is_transmit4_triggered_~__retres1~4#1 := 0; 314188#L407-7 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 314184#is_transmit4_triggered_returnLabel#8 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 314179#L857-21 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 314175#L857-23 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 314171#L415-21 assume !(1 == ~t5_pc~0); 314167#L415-23 is_transmit5_triggered_~__retres1~5#1 := 0; 314163#L426-7 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 314158#is_transmit5_triggered_returnLabel#8 activate_threads_#t~ret17#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 314153#L865-21 assume !(0 != activate_threads_~tmp___4~0#1); 314149#L865-23 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 314145#L434-21 assume !(1 == ~t6_pc~0); 314140#L434-23 is_transmit6_triggered_~__retres1~6#1 := 0; 314136#L445-7 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 314132#is_transmit6_triggered_returnLabel#8 activate_threads_#t~ret18#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 314126#L873-21 assume !(0 != activate_threads_~tmp___5~0#1); 314122#L873-23 havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 314118#L743-3 assume 1 == ~M_E~0;~M_E~0 := 2; 314113#L743-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 314109#L748-3 assume !(1 == ~T2_E~0); 314105#L753-3 assume !(1 == ~T3_E~0); 314101#L758-3 assume !(1 == ~T4_E~0); 314097#L763-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 314093#L768-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 314089#L773-3 assume 1 == ~E_1~0;~E_1~0 := 2; 314085#L778-3 assume 1 == ~E_2~0;~E_2~0 := 2; 314081#L783-3 assume 1 == ~E_3~0;~E_3~0 := 2; 314077#L788-3 assume 1 == ~E_4~0;~E_4~0 := 2; 314073#L793-3 assume !(1 == ~E_5~0); 314069#L798-3 assume !(1 == ~E_6~0); 314066#L803-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 314054#L504-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 314047#L541-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 314000#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret20#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret20#1;havoc start_simulation_#t~ret20#1; 313993#L1043 assume !(0 == start_simulation_~tmp~3#1); 313987#L1043-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret19#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 313978#L504-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 313969#L541-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 313958#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret19#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret19#1;havoc stop_simulation_#t~ret19#1; 313953#L998 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 313950#L1005 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 313945#stop_simulation_returnLabel#1 start_simulation_#t~ret21#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret19#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret21#1;havoc start_simulation_#t~ret21#1; 313940#L1056 assume !(0 != start_simulation_~tmp___0~1#1); 309501#L1024-2 [2023-11-06 22:08:18,814 INFO L145 PredicateUnifier]: Initialized classic predicate unifier [2023-11-06 22:08:18,814 INFO L85 PathProgramCache]: Analyzing trace with hash -2100463851, now seen corresponding path program 5 times [2023-11-06 22:08:18,815 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-06 22:08:18,815 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [485446712] [2023-11-06 22:08:18,815 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-06 22:08:18,815 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-06 22:08:18,830 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-06 22:08:18,830 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-06 22:08:18,839 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-06 22:08:18,866 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-06 22:08:18,867 INFO L145 PredicateUnifier]: Initialized classic predicate unifier [2023-11-06 22:08:18,867 INFO L85 PathProgramCache]: Analyzing trace with hash 1197233992, now seen corresponding path program 1 times [2023-11-06 22:08:18,867 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-06 22:08:18,867 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [680482498] [2023-11-06 22:08:18,867 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-06 22:08:18,868 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-06 22:08:18,880 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-06 22:08:18,911 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-06 22:08:18,911 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-06 22:08:18,911 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [680482498] [2023-11-06 22:08:18,911 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [680482498] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-06 22:08:18,912 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-06 22:08:18,912 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-06 22:08:18,912 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [524839897] [2023-11-06 22:08:18,912 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-06 22:08:18,913 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-06 22:08:18,913 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-06 22:08:18,914 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-06 22:08:18,914 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-06 22:08:18,914 INFO L87 Difference]: Start difference. First operand 10131 states and 13893 transitions. cyclomatic complexity: 3770 Second operand has 3 states, 3 states have (on average 32.666666666666664) internal successors, (98), 3 states have internal predecessors, (98), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-06 22:08:19,007 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-06 22:08:19,007 INFO L93 Difference]: Finished difference Result 17611 states and 23847 transitions. [2023-11-06 22:08:19,007 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 17611 states and 23847 transitions. [2023-11-06 22:08:19,083 INFO L131 ngComponentsAnalysis]: Automaton has 13 accepting balls. 17432 [2023-11-06 22:08:19,145 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 17611 states to 17611 states and 23847 transitions. [2023-11-06 22:08:19,146 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 17611 [2023-11-06 22:08:19,156 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 17611 [2023-11-06 22:08:19,157 INFO L73 IsDeterministic]: Start isDeterministic. Operand 17611 states and 23847 transitions. [2023-11-06 22:08:19,171 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-06 22:08:19,171 INFO L218 hiAutomatonCegarLoop]: Abstraction has 17611 states and 23847 transitions. [2023-11-06 22:08:19,182 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 17611 states and 23847 transitions. [2023-11-06 22:08:19,320 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 17611 to 17075. [2023-11-06 22:08:19,336 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 17075 states, 17075 states have (on average 1.3560761346998536) internal successors, (23155), 17074 states have internal predecessors, (23155), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-06 22:08:19,371 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 17075 states to 17075 states and 23155 transitions. [2023-11-06 22:08:19,371 INFO L240 hiAutomatonCegarLoop]: Abstraction has 17075 states and 23155 transitions. [2023-11-06 22:08:19,372 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-06 22:08:19,372 INFO L428 stractBuchiCegarLoop]: Abstraction has 17075 states and 23155 transitions. [2023-11-06 22:08:19,372 INFO L335 stractBuchiCegarLoop]: ======== Iteration 25 ============ [2023-11-06 22:08:19,372 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 17075 states and 23155 transitions. [2023-11-06 22:08:19,422 INFO L131 ngComponentsAnalysis]: Automaton has 13 accepting balls. 16896 [2023-11-06 22:08:19,423 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-06 22:08:19,423 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-06 22:08:19,424 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-06 22:08:19,424 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-06 22:08:19,424 INFO L748 eck$LassoCheckResult]: Stem: 337463#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2; 337464#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~8#1;havoc main_~__retres1~8#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 337597#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret20#1, start_simulation_#t~ret21#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 337598#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 337115#L461 assume 1 == ~m_i~0;~m_st~0 := 0; 337116#L461-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 337667#L466-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 337835#L471-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 337210#L476-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 337211#L481-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 337375#L486-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 337225#L491-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 337226#L670 assume !(0 == ~M_E~0); 337613#L670-2 assume !(0 == ~T1_E~0); 337559#L675-1 assume !(0 == ~T2_E~0); 337560#L680-1 assume !(0 == ~T3_E~0); 337665#L685-1 assume !(0 == ~T4_E~0); 337619#L690-1 assume !(0 == ~T5_E~0); 337620#L695-1 assume !(0 == ~T6_E~0); 337716#L700-1 assume !(0 == ~E_1~0); 337700#L705-1 assume !(0 == ~E_2~0); 337701#L710-1 assume !(0 == ~E_3~0); 337558#L715-1 assume !(0 == ~E_4~0); 337488#L720-1 assume !(0 == ~E_5~0); 337489#L725-1 assume !(0 == ~E_6~0); 337538#L730-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 337587#L320 assume !(1 == ~m_pc~0); 337739#L320-2 is_master_triggered_~__retres1~0#1 := 0; 337424#L331 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 337417#is_master_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 337376#L825 assume !(0 != activate_threads_~tmp~1#1); 337377#L825-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 337387#L339 assume !(1 == ~t1_pc~0); 337388#L339-2 is_transmit1_triggered_~__retres1~1#1 := 0; 337352#L350 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 337206#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 337207#L833 assume !(0 != activate_threads_~tmp___0~0#1); 337229#L833-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 337140#L358 assume !(1 == ~t2_pc~0); 337141#L358-2 is_transmit2_triggered_~__retres1~2#1 := 0; 337691#L369 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 337600#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 337541#L841 assume !(0 != activate_threads_~tmp___1~0#1); 337371#L841-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 337372#L377 assume !(1 == ~t3_pc~0); 337644#L377-2 is_transmit3_triggered_~__retres1~3#1 := 0; 337645#L388 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 337138#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 337139#L849 assume !(0 != activate_threads_~tmp___2~0#1); 337380#L849-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 337311#L396 assume !(1 == ~t4_pc~0); 337312#L396-2 is_transmit4_triggered_~__retres1~4#1 := 0; 337142#L407 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 337143#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 337291#L857 assume !(0 != activate_threads_~tmp___3~0#1); 337275#L857-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 337276#L415 assume !(1 == ~t5_pc~0); 337359#L415-2 is_transmit5_triggered_~__retres1~5#1 := 0; 337412#L426 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 337431#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 337432#L865 assume !(0 != activate_threads_~tmp___4~0#1); 337183#L865-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 337184#L434 assume !(1 == ~t6_pc~0); 337520#L434-2 is_transmit6_triggered_~__retres1~6#1 := 0; 337521#L445 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 337591#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 337592#L873 assume !(0 != activate_threads_~tmp___5~0#1); 337396#L873-2 havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 337397#L743 assume !(1 == ~M_E~0); 337266#L743-2 assume !(1 == ~T1_E~0); 337267#L748-1 assume !(1 == ~T2_E~0); 337580#L753-1 assume !(1 == ~T3_E~0); 337581#L758-1 assume !(1 == ~T4_E~0); 337719#L763-1 assume !(1 == ~T5_E~0); 337780#L768-1 assume !(1 == ~T6_E~0); 337394#L773-1 assume !(1 == ~E_1~0); 337395#L778-1 assume !(1 == ~E_2~0); 337366#L783-1 assume !(1 == ~E_3~0); 337367#L788-1 assume !(1 == ~E_4~0); 337663#L793-1 assume !(1 == ~E_5~0); 337605#L798-1 assume !(1 == ~E_6~0); 337248#L803-1 assume { :end_inline_reset_delta_events } true; 337249#L1024-2 assume !false; 346092#L1025 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 346087#L645-1 [2023-11-06 22:08:19,425 INFO L750 eck$LassoCheckResult]: Loop: 346087#L645-1 assume !false; 346084#L552 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 346081#L504 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 346079#L541 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 346077#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 346075#L556 assume 0 != eval_~tmp~0#1; 346073#L556-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;havoc eval_#t~nondet5#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet5#1;havoc eval_#t~nondet5#1; 346071#L564 assume !(0 != eval_~tmp_ndt_1~0#1); 346072#L564-2 havoc eval_~tmp_ndt_1~0#1; 346165#L561-1 assume !(0 == ~t1_st~0); 346159#L575-1 assume !(0 == ~t2_st~0); 346153#L589-1 assume !(0 == ~t3_st~0); 346147#L603-1 assume !(0 == ~t4_st~0); 346127#L617-1 assume !(0 == ~t5_st~0); 346089#L631-1 assume !(0 == ~t6_st~0); 346087#L645-1 [2023-11-06 22:08:19,425 INFO L145 PredicateUnifier]: Initialized classic predicate unifier [2023-11-06 22:08:19,425 INFO L85 PathProgramCache]: Analyzing trace with hash 88880503, now seen corresponding path program 1 times [2023-11-06 22:08:19,426 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-06 22:08:19,426 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [309699994] [2023-11-06 22:08:19,426 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-06 22:08:19,426 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-06 22:08:19,438 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-06 22:08:19,439 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-06 22:08:19,446 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-06 22:08:19,463 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-06 22:08:19,464 INFO L145 PredicateUnifier]: Initialized classic predicate unifier [2023-11-06 22:08:19,464 INFO L85 PathProgramCache]: Analyzing trace with hash -2144970051, now seen corresponding path program 1 times [2023-11-06 22:08:19,464 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-06 22:08:19,464 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [520934092] [2023-11-06 22:08:19,465 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-06 22:08:19,465 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-06 22:08:19,469 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-06 22:08:19,469 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-06 22:08:19,472 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-06 22:08:19,474 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-06 22:08:19,474 INFO L145 PredicateUnifier]: Initialized classic predicate unifier [2023-11-06 22:08:19,474 INFO L85 PathProgramCache]: Analyzing trace with hash -444216697, now seen corresponding path program 1 times [2023-11-06 22:08:19,475 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-06 22:08:19,475 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [429338734] [2023-11-06 22:08:19,475 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-06 22:08:19,475 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-06 22:08:19,492 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-06 22:08:19,529 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-06 22:08:19,529 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-06 22:08:19,530 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [429338734] [2023-11-06 22:08:19,530 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [429338734] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-06 22:08:19,530 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-06 22:08:19,530 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-06 22:08:19,530 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1910362522] [2023-11-06 22:08:19,530 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-06 22:08:19,670 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-06 22:08:19,670 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-06 22:08:19,670 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-06 22:08:19,671 INFO L87 Difference]: Start difference. First operand 17075 states and 23155 transitions. cyclomatic complexity: 6093 Second operand has 3 states, 3 states have (on average 33.0) internal successors, (99), 3 states have internal predecessors, (99), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-06 22:08:19,804 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-06 22:08:19,805 INFO L93 Difference]: Finished difference Result 32076 states and 43155 transitions. [2023-11-06 22:08:19,805 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 32076 states and 43155 transitions. [2023-11-06 22:08:19,941 INFO L131 ngComponentsAnalysis]: Automaton has 13 accepting balls. 31724 [2023-11-06 22:08:20,040 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 32076 states to 32076 states and 43155 transitions. [2023-11-06 22:08:20,040 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 32076 [2023-11-06 22:08:20,059 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 32076 [2023-11-06 22:08:20,060 INFO L73 IsDeterministic]: Start isDeterministic. Operand 32076 states and 43155 transitions. [2023-11-06 22:08:20,083 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-06 22:08:20,084 INFO L218 hiAutomatonCegarLoop]: Abstraction has 32076 states and 43155 transitions. [2023-11-06 22:08:20,109 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 32076 states and 43155 transitions. [2023-11-06 22:08:20,591 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 32076 to 30268. [2023-11-06 22:08:20,627 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 30268 states, 30268 states have (on average 1.3501717985991806) internal successors, (40867), 30267 states have internal predecessors, (40867), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-06 22:08:20,688 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 30268 states to 30268 states and 40867 transitions. [2023-11-06 22:08:20,688 INFO L240 hiAutomatonCegarLoop]: Abstraction has 30268 states and 40867 transitions. [2023-11-06 22:08:20,688 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-06 22:08:20,689 INFO L428 stractBuchiCegarLoop]: Abstraction has 30268 states and 40867 transitions. [2023-11-06 22:08:20,689 INFO L335 stractBuchiCegarLoop]: ======== Iteration 26 ============ [2023-11-06 22:08:20,689 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 30268 states and 40867 transitions. [2023-11-06 22:08:20,777 INFO L131 ngComponentsAnalysis]: Automaton has 13 accepting balls. 29916 [2023-11-06 22:08:20,777 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-06 22:08:20,777 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-06 22:08:20,778 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-06 22:08:20,778 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-06 22:08:20,779 INFO L748 eck$LassoCheckResult]: Stem: 386624#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2; 386625#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~8#1;havoc main_~__retres1~8#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 386765#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret20#1, start_simulation_#t~ret21#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 386766#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 386274#L461 assume 1 == ~m_i~0;~m_st~0 := 0; 386275#L461-2 assume !(1 == ~t1_i~0);~t1_st~0 := 2; 386835#L466-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 387011#L471-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 386367#L476-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 386368#L481-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 386541#L486-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 386383#L491-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 386384#L670 assume !(0 == ~M_E~0); 386779#L670-2 assume !(0 == ~T1_E~0); 386723#L675-1 assume !(0 == ~T2_E~0); 386724#L680-1 assume !(0 == ~T3_E~0); 386834#L685-1 assume !(0 == ~T4_E~0); 386787#L690-1 assume !(0 == ~T5_E~0); 386788#L695-1 assume !(0 == ~T6_E~0); 386887#L700-1 assume !(0 == ~E_1~0); 386870#L705-1 assume !(0 == ~E_2~0); 386871#L710-1 assume !(0 == ~E_3~0); 386722#L715-1 assume !(0 == ~E_4~0); 386652#L720-1 assume !(0 == ~E_5~0); 386653#L725-1 assume !(0 == ~E_6~0); 386700#L730-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 386753#L320 assume !(1 == ~m_pc~0); 386913#L320-2 is_master_triggered_~__retres1~0#1 := 0; 386590#L331 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 386583#is_master_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 386542#L825 assume !(0 != activate_threads_~tmp~1#1); 386543#L825-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 386547#L339 assume !(1 == ~t1_pc~0); 386548#L339-2 is_transmit1_triggered_~__retres1~1#1 := 0; 386517#L350 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 386365#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 386366#L833 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 386389#L833-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 404898#L358 assume !(1 == ~t2_pc~0); 404897#L358-2 is_transmit2_triggered_~__retres1~2#1 := 0; 404896#L369 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 404895#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 404894#L841 assume !(0 != activate_threads_~tmp___1~0#1); 386537#L841-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 386538#L377 assume !(1 == ~t3_pc~0); 404854#L377-2 is_transmit3_triggered_~__retres1~3#1 := 0; 404852#L388 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 404850#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 404842#L849 assume !(0 != activate_threads_~tmp___2~0#1); 404841#L849-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 404839#L396 assume !(1 == ~t4_pc~0); 404836#L396-2 is_transmit4_triggered_~__retres1~4#1 := 0; 404834#L407 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 404832#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 386741#L857 assume !(0 != activate_threads_~tmp___3~0#1); 386437#L857-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 386438#L415 assume !(1 == ~t5_pc~0); 386522#L415-2 is_transmit5_triggered_~__retres1~5#1 := 0; 404798#L426 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 404796#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 386923#L865 assume !(0 != activate_threads_~tmp___4~0#1); 386343#L865-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 386344#L434 assume !(1 == ~t6_pc~0); 400180#L434-2 is_transmit6_triggered_~__retres1~6#1 := 0; 400179#L445 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 400178#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 400177#L873 assume !(0 != activate_threads_~tmp___5~0#1); 400176#L873-2 havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 400175#L743 assume !(1 == ~M_E~0); 400174#L743-2 assume !(1 == ~T1_E~0); 400173#L748-1 assume !(1 == ~T2_E~0); 400172#L753-1 assume !(1 == ~T3_E~0); 400171#L758-1 assume !(1 == ~T4_E~0); 400167#L763-1 assume !(1 == ~T5_E~0); 387007#L768-1 assume !(1 == ~T6_E~0); 386554#L773-1 assume !(1 == ~E_1~0); 386555#L778-1 assume !(1 == ~E_2~0); 387051#L783-1 assume !(1 == ~E_3~0); 400142#L788-1 assume !(1 == ~E_4~0); 386832#L793-1 assume !(1 == ~E_5~0); 386774#L798-1 assume !(1 == ~E_6~0); 386408#L803-1 assume { :end_inline_reset_delta_events } true; 386409#L1024-2 assume !false; 402353#L1025 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 402347#L645-1 [2023-11-06 22:08:20,779 INFO L750 eck$LassoCheckResult]: Loop: 402347#L645-1 assume !false; 402345#L552 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 402342#L504 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 402339#L541 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 402337#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 402335#L556 assume 0 != eval_~tmp~0#1; 402332#L556-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;havoc eval_#t~nondet5#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet5#1;havoc eval_#t~nondet5#1; 402329#L564 assume !(0 != eval_~tmp_ndt_1~0#1); 402330#L564-2 havoc eval_~tmp_ndt_1~0#1; 402380#L561-1 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0#1;havoc eval_#t~nondet6#1;eval_~tmp_ndt_2~0#1 := eval_#t~nondet6#1;havoc eval_#t~nondet6#1; 400553#L578 assume !(0 != eval_~tmp_ndt_2~0#1); 402377#L578-2 havoc eval_~tmp_ndt_2~0#1; 402375#L575-1 assume !(0 == ~t2_st~0); 402371#L589-1 assume !(0 == ~t3_st~0); 402368#L603-1 assume !(0 == ~t4_st~0); 402363#L617-1 assume !(0 == ~t5_st~0); 402350#L631-1 assume !(0 == ~t6_st~0); 402347#L645-1 [2023-11-06 22:08:20,779 INFO L145 PredicateUnifier]: Initialized classic predicate unifier [2023-11-06 22:08:20,780 INFO L85 PathProgramCache]: Analyzing trace with hash -1610041797, now seen corresponding path program 1 times [2023-11-06 22:08:20,780 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-06 22:08:20,780 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1690591659] [2023-11-06 22:08:20,780 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-06 22:08:20,780 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-06 22:08:20,790 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-06 22:08:20,810 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-06 22:08:20,810 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-06 22:08:20,810 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1690591659] [2023-11-06 22:08:20,811 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1690591659] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-06 22:08:20,811 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-06 22:08:20,811 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-06 22:08:20,811 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1816303389] [2023-11-06 22:08:20,811 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-06 22:08:20,811 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-06 22:08:20,812 INFO L145 PredicateUnifier]: Initialized classic predicate unifier [2023-11-06 22:08:20,812 INFO L85 PathProgramCache]: Analyzing trace with hash 2044493828, now seen corresponding path program 1 times [2023-11-06 22:08:20,812 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-06 22:08:20,812 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [858730316] [2023-11-06 22:08:20,812 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-06 22:08:20,813 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-06 22:08:20,818 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-06 22:08:20,818 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-06 22:08:20,821 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-06 22:08:20,823 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-06 22:08:21,201 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-06 22:08:21,201 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-06 22:08:21,202 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-06 22:08:21,202 INFO L87 Difference]: Start difference. First operand 30268 states and 40867 transitions. cyclomatic complexity: 10612 Second operand has 3 states, 3 states have (on average 28.0) internal successors, (84), 3 states have internal predecessors, (84), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-06 22:08:21,334 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-06 22:08:21,334 INFO L93 Difference]: Finished difference Result 30187 states and 40758 transitions. [2023-11-06 22:08:21,334 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 30187 states and 40758 transitions. [2023-11-06 22:08:21,493 INFO L131 ngComponentsAnalysis]: Automaton has 13 accepting balls. 29916 [2023-11-06 22:08:21,765 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 30187 states to 30187 states and 40758 transitions. [2023-11-06 22:08:21,765 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 30187 [2023-11-06 22:08:21,797 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 30187 [2023-11-06 22:08:21,798 INFO L73 IsDeterministic]: Start isDeterministic. Operand 30187 states and 40758 transitions. [2023-11-06 22:08:21,832 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-06 22:08:21,832 INFO L218 hiAutomatonCegarLoop]: Abstraction has 30187 states and 40758 transitions. [2023-11-06 22:08:21,849 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 30187 states and 40758 transitions. [2023-11-06 22:08:22,230 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 30187 to 30187. [2023-11-06 22:08:22,257 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 30187 states, 30187 states have (on average 1.3501838539768776) internal successors, (40758), 30186 states have internal predecessors, (40758), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-06 22:08:22,322 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 30187 states to 30187 states and 40758 transitions. [2023-11-06 22:08:22,323 INFO L240 hiAutomatonCegarLoop]: Abstraction has 30187 states and 40758 transitions. [2023-11-06 22:08:22,324 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-06 22:08:22,324 INFO L428 stractBuchiCegarLoop]: Abstraction has 30187 states and 40758 transitions. [2023-11-06 22:08:22,324 INFO L335 stractBuchiCegarLoop]: ======== Iteration 27 ============ [2023-11-06 22:08:22,325 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 30187 states and 40758 transitions. [2023-11-06 22:08:22,417 INFO L131 ngComponentsAnalysis]: Automaton has 13 accepting balls. 29916 [2023-11-06 22:08:22,417 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-06 22:08:22,417 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-06 22:08:22,418 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-06 22:08:22,419 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-06 22:08:22,419 INFO L748 eck$LassoCheckResult]: Stem: 447079#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2; 447080#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~8#1;havoc main_~__retres1~8#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 447219#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret20#1, start_simulation_#t~ret21#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 447220#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 446735#L461 assume 1 == ~m_i~0;~m_st~0 := 0; 446736#L461-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 447284#L466-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 447448#L471-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 446827#L476-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 446828#L481-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 447000#L486-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 446843#L491-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 446844#L670 assume !(0 == ~M_E~0); 447233#L670-2 assume !(0 == ~T1_E~0); 447181#L675-1 assume !(0 == ~T2_E~0); 447182#L680-1 assume !(0 == ~T3_E~0); 447283#L685-1 assume !(0 == ~T4_E~0); 447241#L690-1 assume !(0 == ~T5_E~0); 447242#L695-1 assume !(0 == ~T6_E~0); 447333#L700-1 assume !(0 == ~E_1~0); 447316#L705-1 assume !(0 == ~E_2~0); 447317#L710-1 assume !(0 == ~E_3~0); 447180#L715-1 assume !(0 == ~E_4~0); 447109#L720-1 assume !(0 == ~E_5~0); 447110#L725-1 assume !(0 == ~E_6~0); 447160#L730-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 447209#L320 assume !(1 == ~m_pc~0); 447354#L320-2 is_master_triggered_~__retres1~0#1 := 0; 447048#L331 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 447040#is_master_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 447001#L825 assume !(0 != activate_threads_~tmp~1#1); 447002#L825-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 447006#L339 assume !(1 == ~t1_pc~0); 447007#L339-2 is_transmit1_triggered_~__retres1~1#1 := 0; 446976#L350 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 446825#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 446826#L833 assume !(0 != activate_threads_~tmp___0~0#1); 446848#L833-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 446760#L358 assume !(1 == ~t2_pc~0); 446761#L358-2 is_transmit2_triggered_~__retres1~2#1 := 0; 447308#L369 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 447222#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 447163#L841 assume !(0 != activate_threads_~tmp___1~0#1); 446996#L841-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 446997#L377 assume !(1 == ~t3_pc~0); 447265#L377-2 is_transmit3_triggered_~__retres1~3#1 := 0; 447266#L388 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 446756#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 446757#L849 assume !(0 != activate_threads_~tmp___2~0#1); 447005#L849-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 446927#L396 assume !(1 == ~t4_pc~0); 446928#L396-2 is_transmit4_triggered_~__retres1~4#1 := 0; 446762#L407 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 446763#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 446909#L857 assume !(0 != activate_threads_~tmp___3~0#1); 446894#L857-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 446895#L415 assume !(1 == ~t5_pc~0); 446981#L415-2 is_transmit5_triggered_~__retres1~5#1 := 0; 447031#L426 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 447051#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 447052#L865 assume !(0 != activate_threads_~tmp___4~0#1); 446803#L865-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 446804#L434 assume !(1 == ~t6_pc~0); 447142#L434-2 is_transmit6_triggered_~__retres1~6#1 := 0; 447143#L445 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 447213#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 447214#L873 assume !(0 != activate_threads_~tmp___5~0#1); 447019#L873-2 havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 447020#L743 assume !(1 == ~M_E~0); 446885#L743-2 assume !(1 == ~T1_E~0); 446886#L748-1 assume !(1 == ~T2_E~0); 447202#L753-1 assume !(1 == ~T3_E~0); 447203#L758-1 assume !(1 == ~T4_E~0); 447336#L763-1 assume !(1 == ~T5_E~0); 447396#L768-1 assume !(1 == ~T6_E~0); 447013#L773-1 assume !(1 == ~E_1~0); 447014#L778-1 assume !(1 == ~E_2~0); 446991#L783-1 assume !(1 == ~E_3~0); 446992#L788-1 assume !(1 == ~E_4~0); 447281#L793-1 assume !(1 == ~E_5~0); 447229#L798-1 assume !(1 == ~E_6~0); 446865#L803-1 assume { :end_inline_reset_delta_events } true; 446866#L1024-2 assume !false; 461118#L1025 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 461113#L645-1 [2023-11-06 22:08:22,419 INFO L750 eck$LassoCheckResult]: Loop: 461113#L645-1 assume !false; 461111#L552 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 461108#L504 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 461106#L541 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 461104#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 461102#L556 assume 0 != eval_~tmp~0#1; 461098#L556-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;havoc eval_#t~nondet5#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet5#1;havoc eval_#t~nondet5#1; 461096#L564 assume !(0 != eval_~tmp_ndt_1~0#1); 461094#L564-2 havoc eval_~tmp_ndt_1~0#1; 461092#L561-1 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0#1;havoc eval_#t~nondet6#1;eval_~tmp_ndt_2~0#1 := eval_#t~nondet6#1;havoc eval_#t~nondet6#1; 461075#L578 assume !(0 != eval_~tmp_ndt_2~0#1); 461090#L578-2 havoc eval_~tmp_ndt_2~0#1; 461153#L575-1 assume !(0 == ~t2_st~0); 461149#L589-1 assume !(0 == ~t3_st~0); 461145#L603-1 assume !(0 == ~t4_st~0); 461136#L617-1 assume !(0 == ~t5_st~0); 461115#L631-1 assume !(0 == ~t6_st~0); 461113#L645-1 [2023-11-06 22:08:22,420 INFO L145 PredicateUnifier]: Initialized classic predicate unifier [2023-11-06 22:08:22,420 INFO L85 PathProgramCache]: Analyzing trace with hash 88880503, now seen corresponding path program 2 times [2023-11-06 22:08:22,420 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-06 22:08:22,420 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1333098068] [2023-11-06 22:08:22,420 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-06 22:08:22,421 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-06 22:08:22,432 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-06 22:08:22,433 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-06 22:08:22,440 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-06 22:08:22,458 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-06 22:08:22,461 INFO L145 PredicateUnifier]: Initialized classic predicate unifier [2023-11-06 22:08:22,461 INFO L85 PathProgramCache]: Analyzing trace with hash 2044493828, now seen corresponding path program 2 times [2023-11-06 22:08:22,462 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-06 22:08:22,462 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1494136511] [2023-11-06 22:08:22,462 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-06 22:08:22,462 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-06 22:08:22,466 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-06 22:08:22,467 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-06 22:08:22,469 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-06 22:08:22,471 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-06 22:08:22,472 INFO L145 PredicateUnifier]: Initialized classic predicate unifier [2023-11-06 22:08:22,472 INFO L85 PathProgramCache]: Analyzing trace with hash 85927246, now seen corresponding path program 1 times [2023-11-06 22:08:22,472 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-06 22:08:22,473 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1036511481] [2023-11-06 22:08:22,473 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-06 22:08:22,473 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-06 22:08:22,486 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-06 22:08:22,522 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-06 22:08:22,523 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-06 22:08:22,523 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1036511481] [2023-11-06 22:08:22,523 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1036511481] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-06 22:08:22,523 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-06 22:08:22,523 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-06 22:08:22,523 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1366346291] [2023-11-06 22:08:22,524 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-06 22:08:22,769 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-06 22:08:22,770 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-06 22:08:22,770 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-06 22:08:22,770 INFO L87 Difference]: Start difference. First operand 30187 states and 40758 transitions. cyclomatic complexity: 10584 Second operand has 3 states, 3 states have (on average 33.666666666666664) internal successors, (101), 3 states have internal predecessors, (101), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-06 22:08:22,993 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-06 22:08:22,993 INFO L93 Difference]: Finished difference Result 57279 states and 76938 transitions. [2023-11-06 22:08:22,994 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 57279 states and 76938 transitions. [2023-11-06 22:08:23,398 INFO L131 ngComponentsAnalysis]: Automaton has 13 accepting balls. 56824 [2023-11-06 22:08:23,541 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 57279 states to 57279 states and 76938 transitions. [2023-11-06 22:08:23,542 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 57279 [2023-11-06 22:08:23,580 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 57279 [2023-11-06 22:08:23,580 INFO L73 IsDeterministic]: Start isDeterministic. Operand 57279 states and 76938 transitions. [2023-11-06 22:08:23,633 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-06 22:08:23,633 INFO L218 hiAutomatonCegarLoop]: Abstraction has 57279 states and 76938 transitions. [2023-11-06 22:08:23,673 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 57279 states and 76938 transitions. [2023-11-06 22:08:24,386 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 57279 to 55783. [2023-11-06 22:08:24,433 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 55783 states, 55783 states have (on average 1.3455353781618056) internal successors, (75058), 55782 states have internal predecessors, (75058), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-06 22:08:24,556 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 55783 states to 55783 states and 75058 transitions. [2023-11-06 22:08:24,556 INFO L240 hiAutomatonCegarLoop]: Abstraction has 55783 states and 75058 transitions. [2023-11-06 22:08:24,556 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-06 22:08:24,557 INFO L428 stractBuchiCegarLoop]: Abstraction has 55783 states and 75058 transitions. [2023-11-06 22:08:24,557 INFO L335 stractBuchiCegarLoop]: ======== Iteration 28 ============ [2023-11-06 22:08:24,557 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 55783 states and 75058 transitions. [2023-11-06 22:08:24,704 INFO L131 ngComponentsAnalysis]: Automaton has 13 accepting balls. 55328 [2023-11-06 22:08:24,704 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-06 22:08:24,704 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-06 22:08:24,705 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-06 22:08:24,705 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-06 22:08:24,705 INFO L748 eck$LassoCheckResult]: Stem: 534554#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2; 534555#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~8#1;havoc main_~__retres1~8#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 534693#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret20#1, start_simulation_#t~ret21#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 534694#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 534209#L461 assume 1 == ~m_i~0;~m_st~0 := 0; 534210#L461-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 534771#L466-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 534952#L471-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 534302#L476-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 534303#L481-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 534470#L486-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 534318#L491-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 534319#L670 assume !(0 == ~M_E~0); 534713#L670-2 assume !(0 == ~T1_E~0); 534657#L675-1 assume !(0 == ~T2_E~0); 534658#L680-1 assume !(0 == ~T3_E~0); 534770#L685-1 assume !(0 == ~T4_E~0); 534718#L690-1 assume !(0 == ~T5_E~0); 534719#L695-1 assume !(0 == ~T6_E~0); 534821#L700-1 assume !(0 == ~E_1~0); 534805#L705-1 assume !(0 == ~E_2~0); 534806#L710-1 assume !(0 == ~E_3~0); 534656#L715-1 assume !(0 == ~E_4~0); 534583#L720-1 assume !(0 == ~E_5~0); 534584#L725-1 assume !(0 == ~E_6~0); 534634#L730-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 534682#L320 assume !(1 == ~m_pc~0); 534847#L320-2 is_master_triggered_~__retres1~0#1 := 0; 534517#L331 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 534511#is_master_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 534471#L825 assume !(0 != activate_threads_~tmp~1#1); 534472#L825-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 534475#L339 assume !(1 == ~t1_pc~0); 534476#L339-2 is_transmit1_triggered_~__retres1~1#1 := 0; 534446#L350 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 534300#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 534301#L833 assume !(0 != activate_threads_~tmp___0~0#1); 534323#L833-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 534234#L358 assume !(1 == ~t2_pc~0); 534235#L358-2 is_transmit2_triggered_~__retres1~2#1 := 0; 534796#L369 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 534696#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 534639#L841 assume !(0 != activate_threads_~tmp___1~0#1); 534466#L841-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 534467#L377 assume !(1 == ~t3_pc~0); 534746#L377-2 is_transmit3_triggered_~__retres1~3#1 := 0; 534747#L388 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 534230#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 534231#L849 assume !(0 != activate_threads_~tmp___2~0#1); 534474#L849-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 534403#L396 assume !(1 == ~t4_pc~0); 534404#L396-2 is_transmit4_triggered_~__retres1~4#1 := 0; 534236#L407 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 534237#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 534386#L857 assume !(0 != activate_threads_~tmp___3~0#1); 534370#L857-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 534371#L415 assume !(1 == ~t5_pc~0); 534451#L415-2 is_transmit5_triggered_~__retres1~5#1 := 0; 534506#L426 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 534521#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 534522#L865 assume !(0 != activate_threads_~tmp___4~0#1); 534277#L865-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 534278#L434 assume !(1 == ~t6_pc~0); 534617#L434-2 is_transmit6_triggered_~__retres1~6#1 := 0; 534618#L445 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 534686#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 534687#L873 assume !(0 != activate_threads_~tmp___5~0#1); 534490#L873-2 havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 534491#L743 assume !(1 == ~M_E~0); 534359#L743-2 assume !(1 == ~T1_E~0); 534360#L748-1 assume !(1 == ~T2_E~0); 534677#L753-1 assume !(1 == ~T3_E~0); 534678#L758-1 assume !(1 == ~T4_E~0); 534824#L763-1 assume !(1 == ~T5_E~0); 534884#L768-1 assume !(1 == ~T6_E~0); 534486#L773-1 assume !(1 == ~E_1~0); 534487#L778-1 assume !(1 == ~E_2~0); 534460#L783-1 assume !(1 == ~E_3~0); 534461#L788-1 assume !(1 == ~E_4~0); 534767#L793-1 assume !(1 == ~E_5~0); 534703#L798-1 assume !(1 == ~E_6~0); 534340#L803-1 assume { :end_inline_reset_delta_events } true; 534341#L1024-2 assume !false; 588081#L1025 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 588080#L645-1 [2023-11-06 22:08:24,706 INFO L750 eck$LassoCheckResult]: Loop: 588080#L645-1 assume !false; 588079#L552 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 588078#L504 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 578809#L541 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 578808#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 578807#L556 assume 0 != eval_~tmp~0#1; 578804#L556-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;havoc eval_#t~nondet5#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet5#1;havoc eval_#t~nondet5#1; 578801#L564 assume !(0 != eval_~tmp_ndt_1~0#1); 578800#L564-2 havoc eval_~tmp_ndt_1~0#1; 574223#L561-1 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0#1;havoc eval_#t~nondet6#1;eval_~tmp_ndt_2~0#1 := eval_#t~nondet6#1;havoc eval_#t~nondet6#1; 574220#L578 assume !(0 != eval_~tmp_ndt_2~0#1); 574218#L578-2 havoc eval_~tmp_ndt_2~0#1; 574216#L575-1 assume 0 == ~t2_st~0;havoc eval_~tmp_ndt_3~0#1;havoc eval_#t~nondet7#1;eval_~tmp_ndt_3~0#1 := eval_#t~nondet7#1;havoc eval_#t~nondet7#1; 557125#L592 assume !(0 != eval_~tmp_ndt_3~0#1); 574213#L592-2 havoc eval_~tmp_ndt_3~0#1; 574210#L589-1 assume !(0 == ~t3_st~0); 574204#L603-1 assume !(0 == ~t4_st~0); 574083#L617-1 assume !(0 == ~t5_st~0); 574084#L631-1 assume !(0 == ~t6_st~0); 588080#L645-1 [2023-11-06 22:08:24,706 INFO L145 PredicateUnifier]: Initialized classic predicate unifier [2023-11-06 22:08:24,706 INFO L85 PathProgramCache]: Analyzing trace with hash 88880503, now seen corresponding path program 3 times [2023-11-06 22:08:24,707 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-06 22:08:24,707 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1560856624] [2023-11-06 22:08:24,707 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-06 22:08:24,707 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-06 22:08:24,719 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-06 22:08:24,719 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-06 22:08:24,727 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-06 22:08:24,745 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-06 22:08:24,745 INFO L145 PredicateUnifier]: Initialized classic predicate unifier [2023-11-06 22:08:24,745 INFO L85 PathProgramCache]: Analyzing trace with hash 1877482429, now seen corresponding path program 1 times [2023-11-06 22:08:24,745 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-06 22:08:24,746 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [477914285] [2023-11-06 22:08:24,746 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-06 22:08:24,746 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-06 22:08:24,750 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-06 22:08:24,750 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-06 22:08:24,752 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-06 22:08:24,754 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-06 22:08:24,755 INFO L145 PredicateUnifier]: Initialized classic predicate unifier [2023-11-06 22:08:24,755 INFO L85 PathProgramCache]: Analyzing trace with hash 890672775, now seen corresponding path program 1 times [2023-11-06 22:08:24,755 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-06 22:08:24,755 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [413343616] [2023-11-06 22:08:24,755 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-06 22:08:24,756 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-06 22:08:24,768 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-06 22:08:25,024 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-06 22:08:25,024 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-06 22:08:25,024 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [413343616] [2023-11-06 22:08:25,025 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [413343616] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-06 22:08:25,025 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-06 22:08:25,025 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-06 22:08:25,025 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1059926393] [2023-11-06 22:08:25,025 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-06 22:08:25,149 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-06 22:08:25,150 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-06 22:08:25,150 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-06 22:08:25,151 INFO L87 Difference]: Start difference. First operand 55783 states and 75058 transitions. cyclomatic complexity: 19288 Second operand has 3 states, 3 states have (on average 34.333333333333336) internal successors, (103), 3 states have internal predecessors, (103), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-06 22:08:25,529 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-06 22:08:25,529 INFO L93 Difference]: Finished difference Result 102719 states and 137514 transitions. [2023-11-06 22:08:25,530 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 102719 states and 137514 transitions. [2023-11-06 22:08:26,211 INFO L131 ngComponentsAnalysis]: Automaton has 13 accepting balls. 101896 [2023-11-06 22:08:26,430 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 102719 states to 102719 states and 137514 transitions. [2023-11-06 22:08:26,430 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 102719 [2023-11-06 22:08:26,484 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 102719 [2023-11-06 22:08:26,484 INFO L73 IsDeterministic]: Start isDeterministic. Operand 102719 states and 137514 transitions. [2023-11-06 22:08:26,538 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-06 22:08:26,538 INFO L218 hiAutomatonCegarLoop]: Abstraction has 102719 states and 137514 transitions. [2023-11-06 22:08:26,594 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 102719 states and 137514 transitions. [2023-11-06 22:08:27,738 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 102719 to 98079. [2023-11-06 22:08:28,050 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 98079 states, 98079 states have (on average 1.3449770083300197) internal successors, (131914), 98078 states have internal predecessors, (131914), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-06 22:08:28,307 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 98079 states to 98079 states and 131914 transitions. [2023-11-06 22:08:28,307 INFO L240 hiAutomatonCegarLoop]: Abstraction has 98079 states and 131914 transitions. [2023-11-06 22:08:28,308 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-06 22:08:28,314 INFO L428 stractBuchiCegarLoop]: Abstraction has 98079 states and 131914 transitions. [2023-11-06 22:08:28,314 INFO L335 stractBuchiCegarLoop]: ======== Iteration 29 ============ [2023-11-06 22:08:28,314 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 98079 states and 131914 transitions. [2023-11-06 22:08:28,563 INFO L131 ngComponentsAnalysis]: Automaton has 13 accepting balls. 97256 [2023-11-06 22:08:28,564 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-06 22:08:28,564 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-06 22:08:28,565 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-06 22:08:28,565 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-06 22:08:28,565 INFO L748 eck$LassoCheckResult]: Stem: 693063#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2; 693064#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~8#1;havoc main_~__retres1~8#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 693207#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret20#1, start_simulation_#t~ret21#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 693208#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 692719#L461 assume 1 == ~m_i~0;~m_st~0 := 0; 692720#L461-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 693278#L466-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 693480#L471-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 692812#L476-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 692813#L481-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 692980#L486-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 692828#L491-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 692829#L670 assume !(0 == ~M_E~0); 693220#L670-2 assume !(0 == ~T1_E~0); 693167#L675-1 assume !(0 == ~T2_E~0); 693168#L680-1 assume !(0 == ~T3_E~0); 693277#L685-1 assume !(0 == ~T4_E~0); 693228#L690-1 assume !(0 == ~T5_E~0); 693229#L695-1 assume !(0 == ~T6_E~0); 693332#L700-1 assume !(0 == ~E_1~0); 693315#L705-1 assume !(0 == ~E_2~0); 693316#L710-1 assume !(0 == ~E_3~0); 693166#L715-1 assume !(0 == ~E_4~0); 693093#L720-1 assume !(0 == ~E_5~0); 693094#L725-1 assume !(0 == ~E_6~0); 693145#L730-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 693195#L320 assume !(1 == ~m_pc~0); 693354#L320-2 is_master_triggered_~__retres1~0#1 := 0; 693028#L331 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 693022#is_master_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 692981#L825 assume !(0 != activate_threads_~tmp~1#1); 692982#L825-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 692985#L339 assume !(1 == ~t1_pc~0); 692986#L339-2 is_transmit1_triggered_~__retres1~1#1 := 0; 692956#L350 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 692810#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 692811#L833 assume !(0 != activate_threads_~tmp___0~0#1); 692833#L833-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 692744#L358 assume !(1 == ~t2_pc~0); 692745#L358-2 is_transmit2_triggered_~__retres1~2#1 := 0; 693306#L369 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 693210#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 693149#L841 assume !(0 != activate_threads_~tmp___1~0#1); 692976#L841-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 692977#L377 assume !(1 == ~t3_pc~0); 693255#L377-2 is_transmit3_triggered_~__retres1~3#1 := 0; 693256#L388 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 692740#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 692741#L849 assume !(0 != activate_threads_~tmp___2~0#1); 692984#L849-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 692913#L396 assume !(1 == ~t4_pc~0); 692914#L396-2 is_transmit4_triggered_~__retres1~4#1 := 0; 692746#L407 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 692747#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 692895#L857 assume !(0 != activate_threads_~tmp___3~0#1); 692879#L857-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 692880#L415 assume !(1 == ~t5_pc~0); 692961#L415-2 is_transmit5_triggered_~__retres1~5#1 := 0; 693013#L426 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 693031#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 693032#L865 assume !(0 != activate_threads_~tmp___4~0#1); 692788#L865-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 692789#L434 assume !(1 == ~t6_pc~0); 693126#L434-2 is_transmit6_triggered_~__retres1~6#1 := 0; 693127#L445 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 693199#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 693200#L873 assume !(0 != activate_threads_~tmp___5~0#1); 693000#L873-2 havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 693001#L743 assume !(1 == ~M_E~0); 692870#L743-2 assume !(1 == ~T1_E~0); 692871#L748-1 assume !(1 == ~T2_E~0); 693189#L753-1 assume !(1 == ~T3_E~0); 693190#L758-1 assume !(1 == ~T4_E~0); 693334#L763-1 assume !(1 == ~T5_E~0); 693404#L768-1 assume !(1 == ~T6_E~0); 692994#L773-1 assume !(1 == ~E_1~0); 692995#L778-1 assume !(1 == ~E_2~0); 692970#L783-1 assume !(1 == ~E_3~0); 692971#L788-1 assume !(1 == ~E_4~0); 693275#L793-1 assume !(1 == ~E_5~0); 693216#L798-1 assume !(1 == ~E_6~0); 692851#L803-1 assume { :end_inline_reset_delta_events } true; 692852#L1024-2 assume !false; 735292#L1025 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 735293#L645-1 [2023-11-06 22:08:28,566 INFO L750 eck$LassoCheckResult]: Loop: 735293#L645-1 assume !false; 736593#L552 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 736591#L504 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 736590#L541 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 736589#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 736588#L556 assume 0 != eval_~tmp~0#1; 736586#L556-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;havoc eval_#t~nondet5#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet5#1;havoc eval_#t~nondet5#1; 736585#L564 assume !(0 != eval_~tmp_ndt_1~0#1); 736584#L564-2 havoc eval_~tmp_ndt_1~0#1; 736583#L561-1 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0#1;havoc eval_#t~nondet6#1;eval_~tmp_ndt_2~0#1 := eval_#t~nondet6#1;havoc eval_#t~nondet6#1; 735219#L578 assume !(0 != eval_~tmp_ndt_2~0#1); 736582#L578-2 havoc eval_~tmp_ndt_2~0#1; 736613#L575-1 assume 0 == ~t2_st~0;havoc eval_~tmp_ndt_3~0#1;havoc eval_#t~nondet7#1;eval_~tmp_ndt_3~0#1 := eval_#t~nondet7#1;havoc eval_#t~nondet7#1; 736612#L592 assume !(0 != eval_~tmp_ndt_3~0#1); 736611#L592-2 havoc eval_~tmp_ndt_3~0#1; 736610#L589-1 assume 0 == ~t3_st~0;havoc eval_~tmp_ndt_4~0#1;havoc eval_#t~nondet8#1;eval_~tmp_ndt_4~0#1 := eval_#t~nondet8#1;havoc eval_#t~nondet8#1; 726953#L606 assume !(0 != eval_~tmp_ndt_4~0#1); 736606#L606-2 havoc eval_~tmp_ndt_4~0#1; 736603#L603-1 assume !(0 == ~t4_st~0); 736599#L617-1 assume !(0 == ~t5_st~0); 736594#L631-1 assume !(0 == ~t6_st~0); 735293#L645-1 [2023-11-06 22:08:28,566 INFO L145 PredicateUnifier]: Initialized classic predicate unifier [2023-11-06 22:08:28,566 INFO L85 PathProgramCache]: Analyzing trace with hash 88880503, now seen corresponding path program 4 times [2023-11-06 22:08:28,567 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-06 22:08:28,567 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [838386791] [2023-11-06 22:08:28,567 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-06 22:08:28,567 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-06 22:08:28,580 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-06 22:08:28,580 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-06 22:08:28,587 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-06 22:08:28,605 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-06 22:08:28,606 INFO L145 PredicateUnifier]: Initialized classic predicate unifier [2023-11-06 22:08:28,606 INFO L85 PathProgramCache]: Analyzing trace with hash -1290620220, now seen corresponding path program 1 times [2023-11-06 22:08:28,606 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-06 22:08:28,606 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1433098425] [2023-11-06 22:08:28,607 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-06 22:08:28,607 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-06 22:08:28,611 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-06 22:08:28,611 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-06 22:08:28,613 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-06 22:08:28,615 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-06 22:08:28,615 INFO L145 PredicateUnifier]: Initialized classic predicate unifier [2023-11-06 22:08:28,616 INFO L85 PathProgramCache]: Analyzing trace with hash -426925298, now seen corresponding path program 1 times [2023-11-06 22:08:28,616 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-06 22:08:28,616 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [437985679] [2023-11-06 22:08:28,616 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-06 22:08:28,616 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-06 22:08:28,629 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-06 22:08:28,669 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-06 22:08:28,669 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-06 22:08:28,670 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [437985679] [2023-11-06 22:08:28,670 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [437985679] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-06 22:08:28,670 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-06 22:08:28,670 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-06 22:08:28,670 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1856845802] [2023-11-06 22:08:28,670 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-06 22:08:28,796 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-06 22:08:28,796 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-06 22:08:28,796 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-06 22:08:28,797 INFO L87 Difference]: Start difference. First operand 98079 states and 131914 transitions. cyclomatic complexity: 33848 Second operand has 3 states, 3 states have (on average 35.0) internal successors, (105), 3 states have internal predecessors, (105), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-06 22:08:29,676 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-06 22:08:29,676 INFO L93 Difference]: Finished difference Result 128347 states and 171558 transitions. [2023-11-06 22:08:29,676 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 128347 states and 171558 transitions. [2023-11-06 22:08:30,151 INFO L131 ngComponentsAnalysis]: Automaton has 15 accepting balls. 127348 [2023-11-06 22:08:30,861 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 128347 states to 128347 states and 171558 transitions. [2023-11-06 22:08:30,862 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 128347 [2023-11-06 22:08:30,915 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 128347 [2023-11-06 22:08:30,915 INFO L73 IsDeterministic]: Start isDeterministic. Operand 128347 states and 171558 transitions. [2023-11-06 22:08:30,981 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-06 22:08:30,982 INFO L218 hiAutomatonCegarLoop]: Abstraction has 128347 states and 171558 transitions. [2023-11-06 22:08:31,032 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 128347 states and 171558 transitions. [2023-11-06 22:08:32,122 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 128347 to 126107. [2023-11-06 22:08:32,204 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 126107 states, 126107 states have (on average 1.3401159332947417) internal successors, (168998), 126106 states have internal predecessors, (168998), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-06 22:08:32,554 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 126107 states to 126107 states and 168998 transitions. [2023-11-06 22:08:32,555 INFO L240 hiAutomatonCegarLoop]: Abstraction has 126107 states and 168998 transitions. [2023-11-06 22:08:32,555 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-06 22:08:32,556 INFO L428 stractBuchiCegarLoop]: Abstraction has 126107 states and 168998 transitions. [2023-11-06 22:08:32,556 INFO L335 stractBuchiCegarLoop]: ======== Iteration 30 ============ [2023-11-06 22:08:32,556 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 126107 states and 168998 transitions. [2023-11-06 22:08:32,995 INFO L131 ngComponentsAnalysis]: Automaton has 15 accepting balls. 125108 [2023-11-06 22:08:32,996 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-06 22:08:32,996 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-06 22:08:32,997 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-06 22:08:32,997 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-06 22:08:32,998 INFO L748 eck$LassoCheckResult]: Stem: 919500#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2; 919501#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~8#1;havoc main_~__retres1~8#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 919649#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret20#1, start_simulation_#t~ret21#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 919650#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 919153#L461 assume 1 == ~m_i~0;~m_st~0 := 0; 919154#L461-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 919719#L466-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 919893#L471-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 919247#L476-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 919248#L481-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 919417#L486-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 919263#L491-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 919264#L670 assume !(0 == ~M_E~0); 919666#L670-2 assume !(0 == ~T1_E~0); 919606#L675-1 assume !(0 == ~T2_E~0); 919607#L680-1 assume !(0 == ~T3_E~0); 919718#L685-1 assume !(0 == ~T4_E~0); 919674#L690-1 assume !(0 == ~T5_E~0); 919675#L695-1 assume !(0 == ~T6_E~0); 919770#L700-1 assume !(0 == ~E_1~0); 919755#L705-1 assume !(0 == ~E_2~0); 919756#L710-1 assume !(0 == ~E_3~0); 919605#L715-1 assume !(0 == ~E_4~0); 919529#L720-1 assume !(0 == ~E_5~0); 919530#L725-1 assume !(0 == ~E_6~0); 919583#L730-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 919635#L320 assume !(1 == ~m_pc~0); 919791#L320-2 is_master_triggered_~__retres1~0#1 := 0; 919466#L331 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 919459#is_master_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 919418#L825 assume !(0 != activate_threads_~tmp~1#1); 919419#L825-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 919422#L339 assume !(1 == ~t1_pc~0); 919423#L339-2 is_transmit1_triggered_~__retres1~1#1 := 0; 919393#L350 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 919245#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 919246#L833 assume !(0 != activate_threads_~tmp___0~0#1); 919269#L833-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 919178#L358 assume !(1 == ~t2_pc~0); 919179#L358-2 is_transmit2_triggered_~__retres1~2#1 := 0; 919746#L369 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 919652#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 919588#L841 assume !(0 != activate_threads_~tmp___1~0#1); 919413#L841-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 919414#L377 assume !(1 == ~t3_pc~0); 919697#L377-2 is_transmit3_triggered_~__retres1~3#1 := 0; 919698#L388 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 919174#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 919175#L849 assume !(0 != activate_threads_~tmp___2~0#1); 919421#L849-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 919350#L396 assume !(1 == ~t4_pc~0); 919351#L396-2 is_transmit4_triggered_~__retres1~4#1 := 0; 919180#L407 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 919181#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 919331#L857 assume !(0 != activate_threads_~tmp___3~0#1); 919315#L857-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 919316#L415 assume !(1 == ~t5_pc~0); 919398#L415-2 is_transmit5_triggered_~__retres1~5#1 := 0; 919450#L426 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 919469#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 919470#L865 assume !(0 != activate_threads_~tmp___4~0#1); 919222#L865-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 919223#L434 assume !(1 == ~t6_pc~0); 919560#L434-2 is_transmit6_triggered_~__retres1~6#1 := 0; 919561#L445 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 919639#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 919640#L873 assume !(0 != activate_threads_~tmp___5~0#1); 919437#L873-2 havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 919438#L743 assume !(1 == ~M_E~0); 919306#L743-2 assume !(1 == ~T1_E~0); 919307#L748-1 assume !(1 == ~T2_E~0); 919628#L753-1 assume !(1 == ~T3_E~0); 919629#L758-1 assume !(1 == ~T4_E~0); 919772#L763-1 assume !(1 == ~T5_E~0); 919829#L768-1 assume !(1 == ~T6_E~0); 919431#L773-1 assume !(1 == ~E_1~0); 919432#L778-1 assume !(1 == ~E_2~0); 919407#L783-1 assume !(1 == ~E_3~0); 919408#L788-1 assume !(1 == ~E_4~0); 919716#L793-1 assume !(1 == ~E_5~0); 919659#L798-1 assume !(1 == ~E_6~0); 919286#L803-1 assume { :end_inline_reset_delta_events } true; 919287#L1024-2 assume !false; 949612#L1025 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 949608#L645-1 [2023-11-06 22:08:32,998 INFO L750 eck$LassoCheckResult]: Loop: 949608#L645-1 assume !false; 949605#L552 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 949601#L504 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 949599#L541 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 949597#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 949594#L556 assume 0 != eval_~tmp~0#1; 949590#L556-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;havoc eval_#t~nondet5#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet5#1;havoc eval_#t~nondet5#1; 949586#L564 assume !(0 != eval_~tmp_ndt_1~0#1); 949583#L564-2 havoc eval_~tmp_ndt_1~0#1; 943453#L561-1 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0#1;havoc eval_#t~nondet6#1;eval_~tmp_ndt_2~0#1 := eval_#t~nondet6#1;havoc eval_#t~nondet6#1; 943450#L578 assume !(0 != eval_~tmp_ndt_2~0#1); 943448#L578-2 havoc eval_~tmp_ndt_2~0#1; 943446#L575-1 assume 0 == ~t2_st~0;havoc eval_~tmp_ndt_3~0#1;havoc eval_#t~nondet7#1;eval_~tmp_ndt_3~0#1 := eval_#t~nondet7#1;havoc eval_#t~nondet7#1; 943443#L592 assume !(0 != eval_~tmp_ndt_3~0#1); 943441#L592-2 havoc eval_~tmp_ndt_3~0#1; 943439#L589-1 assume 0 == ~t3_st~0;havoc eval_~tmp_ndt_4~0#1;havoc eval_#t~nondet8#1;eval_~tmp_ndt_4~0#1 := eval_#t~nondet8#1;havoc eval_#t~nondet8#1; 943401#L606 assume !(0 != eval_~tmp_ndt_4~0#1); 943437#L606-2 havoc eval_~tmp_ndt_4~0#1; 949627#L603-1 assume 0 == ~t4_st~0;havoc eval_~tmp_ndt_5~0#1;havoc eval_#t~nondet9#1;eval_~tmp_ndt_5~0#1 := eval_#t~nondet9#1;havoc eval_#t~nondet9#1; 949625#L620 assume !(0 != eval_~tmp_ndt_5~0#1); 949624#L620-2 havoc eval_~tmp_ndt_5~0#1; 949621#L617-1 assume !(0 == ~t5_st~0); 949609#L631-1 assume !(0 == ~t6_st~0); 949608#L645-1 [2023-11-06 22:08:32,998 INFO L145 PredicateUnifier]: Initialized classic predicate unifier [2023-11-06 22:08:32,999 INFO L85 PathProgramCache]: Analyzing trace with hash 88880503, now seen corresponding path program 5 times [2023-11-06 22:08:32,999 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-06 22:08:32,999 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1811743557] [2023-11-06 22:08:32,999 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-06 22:08:32,999 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-06 22:08:33,014 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-06 22:08:33,014 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-06 22:08:33,024 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-06 22:08:33,044 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-06 22:08:33,044 INFO L145 PredicateUnifier]: Initialized classic predicate unifier [2023-11-06 22:08:33,044 INFO L85 PathProgramCache]: Analyzing trace with hash 767472829, now seen corresponding path program 1 times [2023-11-06 22:08:33,045 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-06 22:08:33,045 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [14078279] [2023-11-06 22:08:33,045 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-06 22:08:33,045 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-06 22:08:33,050 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-06 22:08:33,050 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-06 22:08:33,053 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-06 22:08:33,055 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-06 22:08:33,056 INFO L145 PredicateUnifier]: Initialized classic predicate unifier [2023-11-06 22:08:33,056 INFO L85 PathProgramCache]: Analyzing trace with hash 1849604743, now seen corresponding path program 1 times [2023-11-06 22:08:33,056 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-06 22:08:33,056 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [462010893] [2023-11-06 22:08:33,057 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-06 22:08:33,057 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-06 22:08:33,072 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-06 22:08:33,114 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-06 22:08:33,114 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-06 22:08:33,114 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [462010893] [2023-11-06 22:08:33,114 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [462010893] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-06 22:08:33,115 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-06 22:08:33,115 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-06 22:08:33,115 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [579487444] [2023-11-06 22:08:33,115 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-06 22:08:33,235 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-06 22:08:33,235 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-06 22:08:33,235 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-06 22:08:33,236 INFO L87 Difference]: Start difference. First operand 126107 states and 168998 transitions. cyclomatic complexity: 42906 Second operand has 3 states, 3 states have (on average 35.666666666666664) internal successors, (107), 3 states have internal predecessors, (107), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-06 22:08:34,566 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-06 22:08:34,566 INFO L93 Difference]: Finished difference Result 183031 states and 243810 transitions. [2023-11-06 22:08:34,566 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 183031 states and 243810 transitions. [2023-11-06 22:08:35,206 INFO L131 ngComponentsAnalysis]: Automaton has 15 accepting balls. 181680 [2023-11-06 22:08:36,288 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 183031 states to 183031 states and 243810 transitions. [2023-11-06 22:08:36,288 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 183031 [2023-11-06 22:08:36,346 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 183031 [2023-11-06 22:08:36,346 INFO L73 IsDeterministic]: Start isDeterministic. Operand 183031 states and 243810 transitions. [2023-11-06 22:08:36,395 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-06 22:08:36,395 INFO L218 hiAutomatonCegarLoop]: Abstraction has 183031 states and 243810 transitions. [2023-11-06 22:08:36,456 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 183031 states and 243810 transitions. [2023-11-06 22:08:37,890 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 183031 to 177655. [2023-11-06 22:08:37,990 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 177655 states, 177655 states have (on average 1.3356336720047282) internal successors, (237282), 177654 states have internal predecessors, (237282), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-06 22:08:39,168 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 177655 states to 177655 states and 237282 transitions. [2023-11-06 22:08:39,168 INFO L240 hiAutomatonCegarLoop]: Abstraction has 177655 states and 237282 transitions. [2023-11-06 22:08:39,168 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-06 22:08:39,169 INFO L428 stractBuchiCegarLoop]: Abstraction has 177655 states and 237282 transitions. [2023-11-06 22:08:39,169 INFO L335 stractBuchiCegarLoop]: ======== Iteration 31 ============ [2023-11-06 22:08:39,169 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 177655 states and 237282 transitions. [2023-11-06 22:08:39,694 INFO L131 ngComponentsAnalysis]: Automaton has 15 accepting balls. 176304 [2023-11-06 22:08:39,694 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-06 22:08:39,694 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-06 22:08:39,695 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-06 22:08:39,695 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-06 22:08:39,696 INFO L748 eck$LassoCheckResult]: Stem: 1228650#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2; 1228651#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~8#1;havoc main_~__retres1~8#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 1228798#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret20#1, start_simulation_#t~ret21#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 1228799#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 1228299#L461 assume 1 == ~m_i~0;~m_st~0 := 0; 1228300#L461-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 1228873#L466-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 1229087#L471-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 1228392#L476-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 1228393#L481-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 1228559#L486-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 1228407#L491-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 1228408#L670 assume !(0 == ~M_E~0); 1228814#L670-2 assume !(0 == ~T1_E~0); 1228753#L675-1 assume !(0 == ~T2_E~0); 1228754#L680-1 assume !(0 == ~T3_E~0); 1228871#L685-1 assume !(0 == ~T4_E~0); 1228821#L690-1 assume !(0 == ~T5_E~0); 1228822#L695-1 assume !(0 == ~T6_E~0); 1228929#L700-1 assume !(0 == ~E_1~0); 1228913#L705-1 assume !(0 == ~E_2~0); 1228914#L710-1 assume !(0 == ~E_3~0); 1228752#L715-1 assume !(0 == ~E_4~0); 1228677#L720-1 assume !(0 == ~E_5~0); 1228678#L725-1 assume !(0 == ~E_6~0); 1228730#L730-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1228786#L320 assume !(1 == ~m_pc~0); 1228955#L320-2 is_master_triggered_~__retres1~0#1 := 0; 1228608#L331 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1228601#is_master_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 1228560#L825 assume !(0 != activate_threads_~tmp~1#1); 1228561#L825-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1228569#L339 assume !(1 == ~t1_pc~0); 1228570#L339-2 is_transmit1_triggered_~__retres1~1#1 := 0; 1228536#L350 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1228388#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 1228389#L833 assume !(0 != activate_threads_~tmp___0~0#1); 1228411#L833-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1228324#L358 assume !(1 == ~t2_pc~0); 1228325#L358-2 is_transmit2_triggered_~__retres1~2#1 := 0; 1228903#L369 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1228801#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 1228734#L841 assume !(0 != activate_threads_~tmp___1~0#1); 1228555#L841-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1228556#L377 assume !(1 == ~t3_pc~0); 1228848#L377-2 is_transmit3_triggered_~__retres1~3#1 := 0; 1228849#L388 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1228322#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 1228323#L849 assume !(0 != activate_threads_~tmp___2~0#1); 1228565#L849-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1228493#L396 assume !(1 == ~t4_pc~0); 1228494#L396-2 is_transmit4_triggered_~__retres1~4#1 := 0; 1228326#L407 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1228327#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 1228473#L857 assume !(0 != activate_threads_~tmp___3~0#1); 1228457#L857-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1228458#L415 assume !(1 == ~t5_pc~0); 1228543#L415-2 is_transmit5_triggered_~__retres1~5#1 := 0; 1228595#L426 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1228615#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 1228616#L865 assume !(0 != activate_threads_~tmp___4~0#1); 1228366#L865-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1228367#L434 assume !(1 == ~t6_pc~0); 1228710#L434-2 is_transmit6_triggered_~__retres1~6#1 := 0; 1228711#L445 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1228791#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1228792#L873 assume !(0 != activate_threads_~tmp___5~0#1); 1228578#L873-2 havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1228579#L743 assume !(1 == ~M_E~0); 1228448#L743-2 assume !(1 == ~T1_E~0); 1228449#L748-1 assume !(1 == ~T2_E~0); 1228777#L753-1 assume !(1 == ~T3_E~0); 1228778#L758-1 assume !(1 == ~T4_E~0); 1228932#L763-1 assume !(1 == ~T5_E~0); 1229006#L768-1 assume !(1 == ~T6_E~0); 1228576#L773-1 assume !(1 == ~E_1~0); 1228577#L778-1 assume !(1 == ~E_2~0); 1228550#L783-1 assume !(1 == ~E_3~0); 1228551#L788-1 assume !(1 == ~E_4~0); 1228869#L793-1 assume !(1 == ~E_5~0); 1228807#L798-1 assume !(1 == ~E_6~0); 1228430#L803-1 assume { :end_inline_reset_delta_events } true; 1228431#L1024-2 assume !false; 1296290#L1025 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 1296283#L645-1 [2023-11-06 22:08:39,696 INFO L750 eck$LassoCheckResult]: Loop: 1296283#L645-1 assume !false; 1296281#L552 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 1296278#L504 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 1296275#L541 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 1296273#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 1296271#L556 assume 0 != eval_~tmp~0#1; 1296260#L556-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;havoc eval_#t~nondet5#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet5#1;havoc eval_#t~nondet5#1; 1296252#L564 assume !(0 != eval_~tmp_ndt_1~0#1); 1296244#L564-2 havoc eval_~tmp_ndt_1~0#1; 1296238#L561-1 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0#1;havoc eval_#t~nondet6#1;eval_~tmp_ndt_2~0#1 := eval_#t~nondet6#1;havoc eval_#t~nondet6#1; 1296232#L578 assume !(0 != eval_~tmp_ndt_2~0#1); 1296227#L578-2 havoc eval_~tmp_ndt_2~0#1; 1295584#L575-1 assume 0 == ~t2_st~0;havoc eval_~tmp_ndt_3~0#1;havoc eval_#t~nondet7#1;eval_~tmp_ndt_3~0#1 := eval_#t~nondet7#1;havoc eval_#t~nondet7#1; 1295581#L592 assume !(0 != eval_~tmp_ndt_3~0#1); 1295579#L592-2 havoc eval_~tmp_ndt_3~0#1; 1295577#L589-1 assume 0 == ~t3_st~0;havoc eval_~tmp_ndt_4~0#1;havoc eval_#t~nondet8#1;eval_~tmp_ndt_4~0#1 := eval_#t~nondet8#1;havoc eval_#t~nondet8#1; 1295405#L606 assume !(0 != eval_~tmp_ndt_4~0#1); 1295474#L606-2 havoc eval_~tmp_ndt_4~0#1; 1296432#L603-1 assume 0 == ~t4_st~0;havoc eval_~tmp_ndt_5~0#1;havoc eval_#t~nondet9#1;eval_~tmp_ndt_5~0#1 := eval_#t~nondet9#1;havoc eval_#t~nondet9#1; 1296425#L620 assume !(0 != eval_~tmp_ndt_5~0#1); 1296415#L620-2 havoc eval_~tmp_ndt_5~0#1; 1296380#L617-1 assume 0 == ~t5_st~0;havoc eval_~tmp_ndt_6~0#1;havoc eval_#t~nondet10#1;eval_~tmp_ndt_6~0#1 := eval_#t~nondet10#1;havoc eval_#t~nondet10#1; 1296366#L634 assume !(0 != eval_~tmp_ndt_6~0#1); 1296359#L634-2 havoc eval_~tmp_ndt_6~0#1; 1296287#L631-1 assume !(0 == ~t6_st~0); 1296283#L645-1 [2023-11-06 22:08:39,697 INFO L145 PredicateUnifier]: Initialized classic predicate unifier [2023-11-06 22:08:39,697 INFO L85 PathProgramCache]: Analyzing trace with hash 88880503, now seen corresponding path program 6 times [2023-11-06 22:08:39,697 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-06 22:08:39,697 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1829636203] [2023-11-06 22:08:39,698 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-06 22:08:39,698 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-06 22:08:39,712 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-06 22:08:39,712 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-06 22:08:39,721 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-06 22:08:39,741 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-06 22:08:39,741 INFO L145 PredicateUnifier]: Initialized classic predicate unifier [2023-11-06 22:08:39,742 INFO L85 PathProgramCache]: Analyzing trace with hash -1198969468, now seen corresponding path program 1 times [2023-11-06 22:08:39,742 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-06 22:08:39,742 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1952296039] [2023-11-06 22:08:39,742 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-06 22:08:39,742 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-06 22:08:39,747 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-06 22:08:39,748 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-06 22:08:39,750 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-06 22:08:39,753 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-06 22:08:39,754 INFO L145 PredicateUnifier]: Initialized classic predicate unifier [2023-11-06 22:08:39,754 INFO L85 PathProgramCache]: Analyzing trace with hash -652285746, now seen corresponding path program 1 times [2023-11-06 22:08:39,754 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-06 22:08:39,754 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1021199990] [2023-11-06 22:08:39,754 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-06 22:08:39,755 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-06 22:08:39,769 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-06 22:08:39,812 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-06 22:08:39,812 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-06 22:08:39,812 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1021199990] [2023-11-06 22:08:39,813 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1021199990] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-06 22:08:39,813 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-06 22:08:39,813 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2023-11-06 22:08:39,813 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1700492853] [2023-11-06 22:08:39,813 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-06 22:08:39,935 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-06 22:08:39,936 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-06 22:08:39,936 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-06 22:08:39,936 INFO L87 Difference]: Start difference. First operand 177655 states and 237282 transitions. cyclomatic complexity: 59642 Second operand has 3 states, 2 states have (on average 54.5) internal successors, (109), 3 states have internal predecessors, (109), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-06 22:08:41,882 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-06 22:08:41,882 INFO L93 Difference]: Finished difference Result 330319 states and 438554 transitions. [2023-11-06 22:08:41,883 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 330319 states and 438554 transitions. [2023-11-06 22:08:43,833 INFO L131 ngComponentsAnalysis]: Automaton has 15 accepting balls. 327704 [2023-11-06 22:08:44,429 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 330319 states to 330319 states and 438554 transitions. [2023-11-06 22:08:44,430 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 330319 [2023-11-06 22:08:44,544 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 330319 [2023-11-06 22:08:44,544 INFO L73 IsDeterministic]: Start isDeterministic. Operand 330319 states and 438554 transitions. [2023-11-06 22:08:44,636 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-06 22:08:44,636 INFO L218 hiAutomatonCegarLoop]: Abstraction has 330319 states and 438554 transitions. [2023-11-06 22:08:44,748 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 330319 states and 438554 transitions. [2023-11-06 22:08:47,903 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 330319 to 330319. [2023-11-06 22:08:48,114 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 330319 states, 330319 states have (on average 1.3276681026522845) internal successors, (438554), 330318 states have internal predecessors, (438554), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-06 22:08:50,059 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 330319 states to 330319 states and 438554 transitions. [2023-11-06 22:08:50,059 INFO L240 hiAutomatonCegarLoop]: Abstraction has 330319 states and 438554 transitions. [2023-11-06 22:08:50,059 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-06 22:08:50,060 INFO L428 stractBuchiCegarLoop]: Abstraction has 330319 states and 438554 transitions. [2023-11-06 22:08:50,060 INFO L335 stractBuchiCegarLoop]: ======== Iteration 32 ============ [2023-11-06 22:08:50,060 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 330319 states and 438554 transitions. [2023-11-06 22:08:50,840 INFO L131 ngComponentsAnalysis]: Automaton has 15 accepting balls. 327704 [2023-11-06 22:08:50,840 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-06 22:08:50,840 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-06 22:08:50,841 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-06 22:08:50,841 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-06 22:08:50,842 INFO L748 eck$LassoCheckResult]: Stem: 1736631#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2; 1736632#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~8#1;havoc main_~__retres1~8#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 1736769#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret20#1, start_simulation_#t~ret21#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 1736770#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 1736281#L461 assume 1 == ~m_i~0;~m_st~0 := 0; 1736282#L461-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 1736840#L466-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 1737026#L471-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 1736374#L476-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 1736375#L481-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 1736542#L486-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 1736389#L491-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 1736390#L670 assume !(0 == ~M_E~0); 1736784#L670-2 assume !(0 == ~T1_E~0); 1736728#L675-1 assume !(0 == ~T2_E~0); 1736729#L680-1 assume !(0 == ~T3_E~0); 1736838#L685-1 assume !(0 == ~T4_E~0); 1736793#L690-1 assume !(0 == ~T5_E~0); 1736794#L695-1 assume !(0 == ~T6_E~0); 1736891#L700-1 assume !(0 == ~E_1~0); 1736875#L705-1 assume !(0 == ~E_2~0); 1736876#L710-1 assume !(0 == ~E_3~0); 1736727#L715-1 assume !(0 == ~E_4~0); 1736656#L720-1 assume !(0 == ~E_5~0); 1736657#L725-1 assume !(0 == ~E_6~0); 1736707#L730-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1736757#L320 assume !(1 == ~m_pc~0); 1736912#L320-2 is_master_triggered_~__retres1~0#1 := 0; 1736591#L331 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1736584#is_master_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 1736543#L825 assume !(0 != activate_threads_~tmp~1#1); 1736544#L825-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1736553#L339 assume !(1 == ~t1_pc~0); 1736554#L339-2 is_transmit1_triggered_~__retres1~1#1 := 0; 1736517#L350 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1736370#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 1736371#L833 assume !(0 != activate_threads_~tmp___0~0#1); 1736393#L833-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1736306#L358 assume !(1 == ~t2_pc~0); 1736307#L358-2 is_transmit2_triggered_~__retres1~2#1 := 0; 1736866#L369 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1736772#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 1736710#L841 assume !(0 != activate_threads_~tmp___1~0#1); 1736538#L841-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1736539#L377 assume !(1 == ~t3_pc~0); 1736818#L377-2 is_transmit3_triggered_~__retres1~3#1 := 0; 1736819#L388 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1736304#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 1736305#L849 assume !(0 != activate_threads_~tmp___2~0#1); 1736547#L849-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1736473#L396 assume !(1 == ~t4_pc~0); 1736474#L396-2 is_transmit4_triggered_~__retres1~4#1 := 0; 1736308#L407 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1736309#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 1736454#L857 assume !(0 != activate_threads_~tmp___3~0#1); 1736439#L857-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1736440#L415 assume !(1 == ~t5_pc~0); 1736524#L415-2 is_transmit5_triggered_~__retres1~5#1 := 0; 1736579#L426 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1736599#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 1736600#L865 assume !(0 != activate_threads_~tmp___4~0#1); 1736348#L865-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1736349#L434 assume !(1 == ~t6_pc~0); 1736689#L434-2 is_transmit6_triggered_~__retres1~6#1 := 0; 1736690#L445 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1736761#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1736762#L873 assume !(0 != activate_threads_~tmp___5~0#1); 1736562#L873-2 havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1736563#L743 assume !(1 == ~M_E~0); 1736431#L743-2 assume !(1 == ~T1_E~0); 1736432#L748-1 assume !(1 == ~T2_E~0); 1736750#L753-1 assume !(1 == ~T3_E~0); 1736751#L758-1 assume !(1 == ~T4_E~0); 1736895#L763-1 assume !(1 == ~T5_E~0); 1736960#L768-1 assume !(1 == ~T6_E~0); 1736560#L773-1 assume !(1 == ~E_1~0); 1736561#L778-1 assume !(1 == ~E_2~0); 1736532#L783-1 assume !(1 == ~E_3~0); 1736533#L788-1 assume !(1 == ~E_4~0); 1736836#L793-1 assume !(1 == ~E_5~0); 1736777#L798-1 assume !(1 == ~E_6~0); 1736413#L803-1 assume { :end_inline_reset_delta_events } true; 1736414#L1024-2 assume !false; 1882491#L1025 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 1882488#L645-1 [2023-11-06 22:08:50,842 INFO L750 eck$LassoCheckResult]: Loop: 1882488#L645-1 assume !false; 1882486#L552 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 1882483#L504 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 1882481#L541 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 1882479#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 1882477#L556 assume 0 != eval_~tmp~0#1; 1882474#L556-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;havoc eval_#t~nondet5#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet5#1;havoc eval_#t~nondet5#1; 1882471#L564 assume !(0 != eval_~tmp_ndt_1~0#1); 1882469#L564-2 havoc eval_~tmp_ndt_1~0#1; 1882467#L561-1 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0#1;havoc eval_#t~nondet6#1;eval_~tmp_ndt_2~0#1 := eval_#t~nondet6#1;havoc eval_#t~nondet6#1; 1858446#L578 assume !(0 != eval_~tmp_ndt_2~0#1); 1858392#L578-2 havoc eval_~tmp_ndt_2~0#1; 1820827#L575-1 assume 0 == ~t2_st~0;havoc eval_~tmp_ndt_3~0#1;havoc eval_#t~nondet7#1;eval_~tmp_ndt_3~0#1 := eval_#t~nondet7#1;havoc eval_#t~nondet7#1; 1820825#L592 assume !(0 != eval_~tmp_ndt_3~0#1); 1820826#L592-2 havoc eval_~tmp_ndt_3~0#1; 1846951#L589-1 assume 0 == ~t3_st~0;havoc eval_~tmp_ndt_4~0#1;havoc eval_#t~nondet8#1;eval_~tmp_ndt_4~0#1 := eval_#t~nondet8#1;havoc eval_#t~nondet8#1; 1806367#L606 assume !(0 != eval_~tmp_ndt_4~0#1); 1846949#L606-2 havoc eval_~tmp_ndt_4~0#1; 1865672#L603-1 assume 0 == ~t4_st~0;havoc eval_~tmp_ndt_5~0#1;havoc eval_#t~nondet9#1;eval_~tmp_ndt_5~0#1 := eval_#t~nondet9#1;havoc eval_#t~nondet9#1; 1865669#L620 assume !(0 != eval_~tmp_ndt_5~0#1); 1865670#L620-2 havoc eval_~tmp_ndt_5~0#1; 1882502#L617-1 assume 0 == ~t5_st~0;havoc eval_~tmp_ndt_6~0#1;havoc eval_#t~nondet10#1;eval_~tmp_ndt_6~0#1 := eval_#t~nondet10#1;havoc eval_#t~nondet10#1; 1882499#L634 assume !(0 != eval_~tmp_ndt_6~0#1); 1882497#L634-2 havoc eval_~tmp_ndt_6~0#1; 1882495#L631-1 assume 0 == ~t6_st~0;havoc eval_~tmp_ndt_7~0#1;havoc eval_#t~nondet11#1;eval_~tmp_ndt_7~0#1 := eval_#t~nondet11#1;havoc eval_#t~nondet11#1; 1825392#L648 assume !(0 != eval_~tmp_ndt_7~0#1); 1882490#L648-2 havoc eval_~tmp_ndt_7~0#1; 1882488#L645-1 [2023-11-06 22:08:50,842 INFO L145 PredicateUnifier]: Initialized classic predicate unifier [2023-11-06 22:08:50,843 INFO L85 PathProgramCache]: Analyzing trace with hash 88880503, now seen corresponding path program 7 times [2023-11-06 22:08:50,843 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-06 22:08:50,843 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [394323277] [2023-11-06 22:08:50,843 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-06 22:08:50,843 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-06 22:08:50,865 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-06 22:08:50,865 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-06 22:08:50,871 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-06 22:08:50,892 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-06 22:08:50,893 INFO L145 PredicateUnifier]: Initialized classic predicate unifier [2023-11-06 22:08:50,893 INFO L85 PathProgramCache]: Analyzing trace with hash -1158409573, now seen corresponding path program 1 times [2023-11-06 22:08:50,893 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-06 22:08:50,893 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [659139817] [2023-11-06 22:08:50,893 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-06 22:08:50,894 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-06 22:08:50,898 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-06 22:08:50,898 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-06 22:08:50,900 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-06 22:08:50,902 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-06 22:08:50,903 INFO L145 PredicateUnifier]: Initialized classic predicate unifier [2023-11-06 22:08:50,903 INFO L85 PathProgramCache]: Analyzing trace with hash 218637157, now seen corresponding path program 1 times [2023-11-06 22:08:50,903 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-06 22:08:50,903 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1369824493] [2023-11-06 22:08:50,904 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-06 22:08:50,904 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-06 22:08:50,916 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-06 22:08:50,916 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-06 22:08:50,923 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-06 22:08:50,952 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-06 22:08:53,957 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-06 22:08:53,957 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-06 22:08:53,986 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-06 22:08:54,244 INFO L201 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer CFG 06.11 10:08:54 BoogieIcfgContainer [2023-11-06 22:08:54,244 INFO L131 PluginConnector]: ------------------------ END BuchiAutomizer---------------------------- [2023-11-06 22:08:54,244 INFO L112 PluginConnector]: ------------------------Witness Printer---------------------------- [2023-11-06 22:08:54,245 INFO L270 PluginConnector]: Initializing Witness Printer... [2023-11-06 22:08:54,245 INFO L274 PluginConnector]: Witness Printer initialized [2023-11-06 22:08:54,245 INFO L184 PluginConnector]: Executing the observer RCFGCatcher from plugin Witness Printer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 06.11 10:08:05" (3/4) ... [2023-11-06 22:08:54,247 INFO L134 WitnessPrinter]: Generating witness for non-termination counterexample [2023-11-06 22:08:54,372 INFO L149 WitnessManager]: Wrote witness to /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_13dea121-f3fd-4f40-8510-ef12d3d88dee/bin/uautomizer-verify-WvqO1wxjHP/witness.graphml.graphml [2023-11-06 22:08:54,372 INFO L131 PluginConnector]: ------------------------ END Witness Printer---------------------------- [2023-11-06 22:08:54,373 INFO L158 Benchmark]: Toolchain (without parser) took 50604.20ms. Allocated memory was 167.8MB in the beginning and 14.3GB in the end (delta: 14.1GB). Free memory was 122.2MB in the beginning and 10.2GB in the end (delta: -10.1GB). Peak memory consumption was 4.0GB. Max. memory is 16.1GB. [2023-11-06 22:08:54,374 INFO L158 Benchmark]: CDTParser took 0.56ms. Allocated memory is still 130.0MB. Free memory is still 82.6MB. There was no memory consumed. Max. memory is 16.1GB. [2023-11-06 22:08:54,374 INFO L158 Benchmark]: CACSL2BoogieTranslator took 400.42ms. Allocated memory is still 167.8MB. Free memory was 121.9MB in the beginning and 104.7MB in the end (delta: 17.1MB). Peak memory consumption was 16.8MB. Max. memory is 16.1GB. [2023-11-06 22:08:54,374 INFO L158 Benchmark]: Boogie Procedure Inliner took 112.86ms. Allocated memory is still 167.8MB. Free memory was 104.7MB in the beginning and 99.1MB in the end (delta: 5.6MB). Peak memory consumption was 6.3MB. Max. memory is 16.1GB. [2023-11-06 22:08:54,375 INFO L158 Benchmark]: Boogie Preprocessor took 88.32ms. Allocated memory is still 167.8MB. Free memory was 99.1MB in the beginning and 93.9MB in the end (delta: 5.2MB). Peak memory consumption was 4.2MB. Max. memory is 16.1GB. [2023-11-06 22:08:54,375 INFO L158 Benchmark]: RCFGBuilder took 1466.14ms. Allocated memory is still 167.8MB. Free memory was 93.9MB in the beginning and 75.1MB in the end (delta: 18.8MB). Peak memory consumption was 18.9MB. Max. memory is 16.1GB. [2023-11-06 22:08:54,376 INFO L158 Benchmark]: BuchiAutomizer took 48401.94ms. Allocated memory was 167.8MB in the beginning and 14.3GB in the end (delta: 14.1GB). Free memory was 75.1MB in the beginning and 10.3GB in the end (delta: -10.2GB). Peak memory consumption was 4.0GB. Max. memory is 16.1GB. [2023-11-06 22:08:54,376 INFO L158 Benchmark]: Witness Printer took 127.93ms. Allocated memory is still 14.3GB. Free memory was 10.3GB in the beginning and 10.2GB in the end (delta: 11.5MB). Peak memory consumption was 12.6MB. Max. memory is 16.1GB. [2023-11-06 22:08:54,379 INFO L338 ainManager$Toolchain]: ####################### End [Toolchain 1] ####################### --- Results --- * Results from de.uni_freiburg.informatik.ultimate.core: - StatisticsResult: Toolchain Benchmarks Benchmark results are: * CDTParser took 0.56ms. Allocated memory is still 130.0MB. Free memory is still 82.6MB. There was no memory consumed. Max. memory is 16.1GB. * CACSL2BoogieTranslator took 400.42ms. Allocated memory is still 167.8MB. Free memory was 121.9MB in the beginning and 104.7MB in the end (delta: 17.1MB). Peak memory consumption was 16.8MB. Max. memory is 16.1GB. * Boogie Procedure Inliner took 112.86ms. Allocated memory is still 167.8MB. Free memory was 104.7MB in the beginning and 99.1MB in the end (delta: 5.6MB). Peak memory consumption was 6.3MB. Max. memory is 16.1GB. * Boogie Preprocessor took 88.32ms. Allocated memory is still 167.8MB. Free memory was 99.1MB in the beginning and 93.9MB in the end (delta: 5.2MB). Peak memory consumption was 4.2MB. Max. memory is 16.1GB. * RCFGBuilder took 1466.14ms. Allocated memory is still 167.8MB. Free memory was 93.9MB in the beginning and 75.1MB in the end (delta: 18.8MB). Peak memory consumption was 18.9MB. Max. memory is 16.1GB. * BuchiAutomizer took 48401.94ms. Allocated memory was 167.8MB in the beginning and 14.3GB in the end (delta: 14.1GB). Free memory was 75.1MB in the beginning and 10.3GB in the end (delta: -10.2GB). Peak memory consumption was 4.0GB. Max. memory is 16.1GB. * Witness Printer took 127.93ms. Allocated memory is still 14.3GB. Free memory was 10.3GB in the beginning and 10.2GB in the end (delta: 11.5MB). Peak memory consumption was 12.6MB. Max. memory is 16.1GB. * Results from de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction: - StatisticsResult: Constructed decomposition of program Your program was decomposed into 31 terminating modules (31 trivial, 0 deterministic, 0 nondeterministic) and one nonterminating remainder module.31 modules have a trivial ranking function, the largest among these consists of 5 locations. The remainder module has 330319 locations. - StatisticsResult: Timing statistics BüchiAutomizer plugin needed 48.1s and 32 iterations. TraceHistogramMax:1. Analysis of lassos took 9.2s. Construction of modules took 1.1s. Büchi inclusion checks took 34.4s. Highest rank in rank-based complementation 0. Minimization of det autom 31. Minimization of nondet autom 0. Automata minimization 16.5s AutomataMinimizationTime, 31 MinimizatonAttempts, 78543 StatesRemovedByMinimization, 21 NontrivialMinimizations. Non-live state removal took 9.8s Buchi closure took 0.5s. Biggest automaton had -1 states and ocurred in iteration -1. Nontrivial modules had stage [0, 0, 0, 0, 0]. InterpolantCoveringCapabilityFinite: 0/0 InterpolantCoveringCapabilityBuchi: 0/0 HoareTripleCheckerStatistics: 0 mSolverCounterUnknown, 33940 SdHoareTripleChecker+Valid, 1.5s IncrementalHoareTripleChecker+Time, 0 mSdLazyCounter, 33940 mSDsluCounter, 58451 SdHoareTripleChecker+Invalid, 1.1s Time, 0 mProtectedAction, 0 SdHoareTripleChecker+Unchecked, 0 IncrementalHoareTripleChecker+Unchecked, 25229 mSDsCounter, 365 IncrementalHoareTripleChecker+Valid, 0 mProtectedPredicate, 1026 IncrementalHoareTripleChecker+Invalid, 1391 SdHoareTripleChecker+Unknown, 0 mSolverCounterNotChecked, 365 mSolverCounterUnsat, 33222 mSDtfsCounter, 1026 mSolverCounterSat, 0.3s SdHoareTripleChecker+Time, 0 IncrementalHoareTripleChecker+Unknown LassoAnalysisResults: nont1 unkn0 SFLI5 SFLT0 conc6 concLT0 SILN1 SILU0 SILI19 SILT0 lasso0 LassoPreprocessingBenchmarks: LassoTerminationAnalysisBenchmarks: not availableLassoTerminationAnalysisBenchmarks: LassoNonterminationAnalysisSatFixpoint: 0 LassoNonterminationAnalysisSatUnbounded: 0 LassoNonterminationAnalysisUnsat: 0 LassoNonterminationAnalysisUnknown: 0 LassoNonterminationAnalysisTime: 0.0s InitialAbstractionConstructionTime: 0.0s - TerminationAnalysisResult: Nontermination possible Buchi Automizer proved that your program is nonterminating for some inputs - LassoShapedNonTerminationArgument [Line: 551]: Nontermination argument in form of an infinite program execution. Nontermination argument in form of an infinite program execution. Stem: [L25] int m_pc = 0; [L26] int t1_pc = 0; [L27] int t2_pc = 0; [L28] int t3_pc = 0; [L29] int t4_pc = 0; [L30] int t5_pc = 0; [L31] int t6_pc = 0; [L32] int m_st ; [L33] int t1_st ; [L34] int t2_st ; [L35] int t3_st ; [L36] int t4_st ; [L37] int t5_st ; [L38] int t6_st ; [L39] int m_i ; [L40] int t1_i ; [L41] int t2_i ; [L42] int t3_i ; [L43] int t4_i ; [L44] int t5_i ; [L45] int t6_i ; [L46] int M_E = 2; [L47] int T1_E = 2; [L48] int T2_E = 2; [L49] int T3_E = 2; [L50] int T4_E = 2; [L51] int T5_E = 2; [L52] int T6_E = 2; [L53] int E_1 = 2; [L54] int E_2 = 2; [L55] int E_3 = 2; [L56] int E_4 = 2; [L57] int E_5 = 2; [L58] int E_6 = 2; VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, m_i=0, m_pc=0, m_st=0, t1_i=0, t1_pc=0, t1_st=0, t2_i=0, t2_pc=0, t2_st=0, t3_i=0, t3_pc=0, t3_st=0, t4_i=0, t4_pc=0, t4_st=0, t5_i=0, t5_pc=0, t5_st=0, t6_i=0, t6_pc=0, t6_st=0] [L1069] int __retres1 ; [L1073] CALL init_model() [L979] m_i = 1 [L980] t1_i = 1 [L981] t2_i = 1 [L982] t3_i = 1 [L983] t4_i = 1 [L984] t5_i = 1 [L985] t6_i = 1 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0] [L1073] RET init_model() [L1074] CALL start_simulation() [L1010] int kernel_st ; [L1011] int tmp ; [L1012] int tmp___0 ; [L1016] kernel_st = 0 [L1017] FCALL update_channels() [L1018] CALL init_threads() [L461] COND TRUE m_i == 1 [L462] m_st = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0] [L466] COND TRUE t1_i == 1 [L467] t1_st = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0] [L471] COND TRUE t2_i == 1 [L472] t2_st = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0] [L476] COND TRUE t3_i == 1 [L477] t3_st = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0] [L481] COND TRUE t4_i == 1 [L482] t4_st = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0] [L486] COND TRUE t5_i == 1 [L487] t5_st = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0] [L491] COND TRUE t6_i == 1 [L492] t6_st = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0] [L1018] RET init_threads() [L1019] CALL fire_delta_events() [L670] COND FALSE !(M_E == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0] [L675] COND FALSE !(T1_E == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0] [L680] COND FALSE !(T2_E == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0] [L685] COND FALSE !(T3_E == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0] [L690] COND FALSE !(T4_E == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0] [L695] COND FALSE !(T5_E == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0] [L700] COND FALSE !(T6_E == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0] [L705] COND FALSE !(E_1 == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0] [L710] COND FALSE !(E_2 == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0] [L715] COND FALSE !(E_3 == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0] [L720] COND FALSE !(E_4 == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0] [L725] COND FALSE !(E_5 == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0] [L730] COND FALSE !(E_6 == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0] [L1019] RET fire_delta_events() [L1020] CALL activate_threads() [L813] int tmp ; [L814] int tmp___0 ; [L815] int tmp___1 ; [L816] int tmp___2 ; [L817] int tmp___3 ; [L818] int tmp___4 ; [L819] int tmp___5 ; [L823] CALL, EXPR is_master_triggered() [L317] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0] [L320] COND FALSE !(m_pc == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0] [L330] __retres1 = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, __retres1=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0] [L332] return (__retres1); VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, \result=0, __retres1=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0] [L823] RET, EXPR is_master_triggered() [L823] tmp = is_master_triggered() [L825] COND FALSE !(\read(tmp)) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, tmp=0] [L831] CALL, EXPR is_transmit1_triggered() [L336] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0] [L339] COND FALSE !(t1_pc == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0] [L349] __retres1 = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, __retres1=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0] [L351] return (__retres1); VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, \result=0, __retres1=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0] [L831] RET, EXPR is_transmit1_triggered() [L831] tmp___0 = is_transmit1_triggered() [L833] COND FALSE !(\read(tmp___0)) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, tmp=0, tmp___0=0] [L839] CALL, EXPR is_transmit2_triggered() [L355] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0] [L358] COND FALSE !(t2_pc == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0] [L368] __retres1 = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, __retres1=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0] [L370] return (__retres1); VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, \result=0, __retres1=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0] [L839] RET, EXPR is_transmit2_triggered() [L839] tmp___1 = is_transmit2_triggered() [L841] COND FALSE !(\read(tmp___1)) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, tmp=0, tmp___0=0, tmp___1=0] [L847] CALL, EXPR is_transmit3_triggered() [L374] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0] [L377] COND FALSE !(t3_pc == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0] [L387] __retres1 = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, __retres1=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0] [L389] return (__retres1); VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, \result=0, __retres1=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0] [L847] RET, EXPR is_transmit3_triggered() [L847] tmp___2 = is_transmit3_triggered() [L849] COND FALSE !(\read(tmp___2)) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, tmp=0, tmp___0=0, tmp___1=0, tmp___2=0] [L855] CALL, EXPR is_transmit4_triggered() [L393] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0] [L396] COND FALSE !(t4_pc == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0] [L406] __retres1 = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, __retres1=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0] [L408] return (__retres1); VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, \result=0, __retres1=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0] [L855] RET, EXPR is_transmit4_triggered() [L855] tmp___3 = is_transmit4_triggered() [L857] COND FALSE !(\read(tmp___3)) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, tmp=0, tmp___0=0, tmp___1=0, tmp___2=0, tmp___3=0] [L863] CALL, EXPR is_transmit5_triggered() [L412] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0] [L415] COND FALSE !(t5_pc == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0] [L425] __retres1 = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, __retres1=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0] [L427] return (__retres1); VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, \result=0, __retres1=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0] [L863] RET, EXPR is_transmit5_triggered() [L863] tmp___4 = is_transmit5_triggered() [L865] COND FALSE !(\read(tmp___4)) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, tmp=0, tmp___0=0, tmp___1=0, tmp___2=0, tmp___3=0, tmp___4=0] [L871] CALL, EXPR is_transmit6_triggered() [L431] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0] [L434] COND FALSE !(t6_pc == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0] [L444] __retres1 = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, __retres1=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0] [L446] return (__retres1); VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, \result=0, __retres1=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0] [L871] RET, EXPR is_transmit6_triggered() [L871] tmp___5 = is_transmit6_triggered() [L873] COND FALSE !(\read(tmp___5)) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, tmp=0, tmp___0=0, tmp___1=0, tmp___2=0, tmp___3=0, tmp___4=0, tmp___5=0] [L1020] RET activate_threads() [L1021] CALL reset_delta_events() [L743] COND FALSE !(M_E == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0] [L748] COND FALSE !(T1_E == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0] [L753] COND FALSE !(T2_E == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0] [L758] COND FALSE !(T3_E == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0] [L763] COND FALSE !(T4_E == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0] [L768] COND FALSE !(T5_E == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0] [L773] COND FALSE !(T6_E == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0] [L778] COND FALSE !(E_1 == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0] [L783] COND FALSE !(E_2 == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0] [L788] COND FALSE !(E_3 == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0] [L793] COND FALSE !(E_4 == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0] [L798] COND FALSE !(E_5 == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0] [L803] COND FALSE !(E_6 == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0] [L1021] RET reset_delta_events() [L1024] COND TRUE 1 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, kernel_st=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0] [L1027] kernel_st = 1 [L1028] CALL eval() [L547] int tmp ; VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0] Loop: [L551] COND TRUE 1 [L554] CALL, EXPR exists_runnable_thread() [L501] int __retres1 ; [L504] COND TRUE m_st == 0 [L505] __retres1 = 1 [L542] return (__retres1); [L554] RET, EXPR exists_runnable_thread() [L554] tmp = exists_runnable_thread() [L556] COND TRUE \read(tmp) [L561] COND TRUE m_st == 0 [L562] int tmp_ndt_1; [L563] EXPR tmp_ndt_1 = __VERIFIER_nondet_int() [L564] COND FALSE, EXPR !(\read(tmp_ndt_1)) [L561-L572] { int tmp_ndt_1; tmp_ndt_1 = __VERIFIER_nondet_int(); if (tmp_ndt_1) { { m_st = 1; master(); } } else { } } [L575] COND TRUE t1_st == 0 [L576] int tmp_ndt_2; [L577] EXPR tmp_ndt_2 = __VERIFIER_nondet_int() [L578] COND FALSE, EXPR !(\read(tmp_ndt_2)) [L575-L586] { int tmp_ndt_2; tmp_ndt_2 = __VERIFIER_nondet_int(); if (tmp_ndt_2) { { t1_st = 1; transmit1(); } } else { } } [L589] COND TRUE t2_st == 0 [L590] int tmp_ndt_3; [L591] EXPR tmp_ndt_3 = __VERIFIER_nondet_int() [L592] COND FALSE, EXPR !(\read(tmp_ndt_3)) [L589-L600] { int tmp_ndt_3; tmp_ndt_3 = __VERIFIER_nondet_int(); if (tmp_ndt_3) { { t2_st = 1; transmit2(); } } else { } } [L603] COND TRUE t3_st == 0 [L604] int tmp_ndt_4; [L605] EXPR tmp_ndt_4 = __VERIFIER_nondet_int() [L606] COND FALSE, EXPR !(\read(tmp_ndt_4)) [L603-L614] { int tmp_ndt_4; tmp_ndt_4 = __VERIFIER_nondet_int(); if (tmp_ndt_4) { { t3_st = 1; transmit3(); } } else { } } [L617] COND TRUE t4_st == 0 [L618] int tmp_ndt_5; [L619] EXPR tmp_ndt_5 = __VERIFIER_nondet_int() [L620] COND FALSE, EXPR !(\read(tmp_ndt_5)) [L617-L628] { int tmp_ndt_5; tmp_ndt_5 = __VERIFIER_nondet_int(); if (tmp_ndt_5) { { t4_st = 1; transmit4(); } } else { } } [L631] COND TRUE t5_st == 0 [L632] int tmp_ndt_6; [L633] EXPR tmp_ndt_6 = __VERIFIER_nondet_int() [L634] COND FALSE, EXPR !(\read(tmp_ndt_6)) [L631-L642] { int tmp_ndt_6; tmp_ndt_6 = __VERIFIER_nondet_int(); if (tmp_ndt_6) { { t5_st = 1; transmit5(); } } else { } } [L645] COND TRUE t6_st == 0 [L646] int tmp_ndt_7; [L647] EXPR tmp_ndt_7 = __VERIFIER_nondet_int() [L648] COND FALSE, EXPR !(\read(tmp_ndt_7)) [L645-L656] { int tmp_ndt_7; tmp_ndt_7 = __VERIFIER_nondet_int(); if (tmp_ndt_7) { { t6_st = 1; transmit6(); } } else { } } End of lasso representation. - StatisticsResult: NonterminationArgumentStatistics Fixpoint - NonterminatingLassoResult [Line: 551]: Nonterminating execution Found a nonterminating execution for the following lasso shaped sequence of statements. Stem: [L25] int m_pc = 0; [L26] int t1_pc = 0; [L27] int t2_pc = 0; [L28] int t3_pc = 0; [L29] int t4_pc = 0; [L30] int t5_pc = 0; [L31] int t6_pc = 0; [L32] int m_st ; [L33] int t1_st ; [L34] int t2_st ; [L35] int t3_st ; [L36] int t4_st ; [L37] int t5_st ; [L38] int t6_st ; [L39] int m_i ; [L40] int t1_i ; [L41] int t2_i ; [L42] int t3_i ; [L43] int t4_i ; [L44] int t5_i ; [L45] int t6_i ; [L46] int M_E = 2; [L47] int T1_E = 2; [L48] int T2_E = 2; [L49] int T3_E = 2; [L50] int T4_E = 2; [L51] int T5_E = 2; [L52] int T6_E = 2; [L53] int E_1 = 2; [L54] int E_2 = 2; [L55] int E_3 = 2; [L56] int E_4 = 2; [L57] int E_5 = 2; [L58] int E_6 = 2; VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, m_i=0, m_pc=0, m_st=0, t1_i=0, t1_pc=0, t1_st=0, t2_i=0, t2_pc=0, t2_st=0, t3_i=0, t3_pc=0, t3_st=0, t4_i=0, t4_pc=0, t4_st=0, t5_i=0, t5_pc=0, t5_st=0, t6_i=0, t6_pc=0, t6_st=0] [L1069] int __retres1 ; [L1073] CALL init_model() [L979] m_i = 1 [L980] t1_i = 1 [L981] t2_i = 1 [L982] t3_i = 1 [L983] t4_i = 1 [L984] t5_i = 1 [L985] t6_i = 1 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0] [L1073] RET init_model() [L1074] CALL start_simulation() [L1010] int kernel_st ; [L1011] int tmp ; [L1012] int tmp___0 ; [L1016] kernel_st = 0 [L1017] FCALL update_channels() [L1018] CALL init_threads() [L461] COND TRUE m_i == 1 [L462] m_st = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0] [L466] COND TRUE t1_i == 1 [L467] t1_st = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0] [L471] COND TRUE t2_i == 1 [L472] t2_st = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0] [L476] COND TRUE t3_i == 1 [L477] t3_st = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0] [L481] COND TRUE t4_i == 1 [L482] t4_st = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0] [L486] COND TRUE t5_i == 1 [L487] t5_st = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0] [L491] COND TRUE t6_i == 1 [L492] t6_st = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0] [L1018] RET init_threads() [L1019] CALL fire_delta_events() [L670] COND FALSE !(M_E == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0] [L675] COND FALSE !(T1_E == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0] [L680] COND FALSE !(T2_E == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0] [L685] COND FALSE !(T3_E == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0] [L690] COND FALSE !(T4_E == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0] [L695] COND FALSE !(T5_E == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0] [L700] COND FALSE !(T6_E == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0] [L705] COND FALSE !(E_1 == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0] [L710] COND FALSE !(E_2 == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0] [L715] COND FALSE !(E_3 == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0] [L720] COND FALSE !(E_4 == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0] [L725] COND FALSE !(E_5 == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0] [L730] COND FALSE !(E_6 == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0] [L1019] RET fire_delta_events() [L1020] CALL activate_threads() [L813] int tmp ; [L814] int tmp___0 ; [L815] int tmp___1 ; [L816] int tmp___2 ; [L817] int tmp___3 ; [L818] int tmp___4 ; [L819] int tmp___5 ; [L823] CALL, EXPR is_master_triggered() [L317] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0] [L320] COND FALSE !(m_pc == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0] [L330] __retres1 = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, __retres1=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0] [L332] return (__retres1); VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, \result=0, __retres1=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0] [L823] RET, EXPR is_master_triggered() [L823] tmp = is_master_triggered() [L825] COND FALSE !(\read(tmp)) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, tmp=0] [L831] CALL, EXPR is_transmit1_triggered() [L336] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0] [L339] COND FALSE !(t1_pc == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0] [L349] __retres1 = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, __retres1=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0] [L351] return (__retres1); VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, \result=0, __retres1=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0] [L831] RET, EXPR is_transmit1_triggered() [L831] tmp___0 = is_transmit1_triggered() [L833] COND FALSE !(\read(tmp___0)) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, tmp=0, tmp___0=0] [L839] CALL, EXPR is_transmit2_triggered() [L355] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0] [L358] COND FALSE !(t2_pc == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0] [L368] __retres1 = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, __retres1=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0] [L370] return (__retres1); VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, \result=0, __retres1=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0] [L839] RET, EXPR is_transmit2_triggered() [L839] tmp___1 = is_transmit2_triggered() [L841] COND FALSE !(\read(tmp___1)) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, tmp=0, tmp___0=0, tmp___1=0] [L847] CALL, EXPR is_transmit3_triggered() [L374] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0] [L377] COND FALSE !(t3_pc == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0] [L387] __retres1 = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, __retres1=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0] [L389] return (__retres1); VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, \result=0, __retres1=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0] [L847] RET, EXPR is_transmit3_triggered() [L847] tmp___2 = is_transmit3_triggered() [L849] COND FALSE !(\read(tmp___2)) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, tmp=0, tmp___0=0, tmp___1=0, tmp___2=0] [L855] CALL, EXPR is_transmit4_triggered() [L393] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0] [L396] COND FALSE !(t4_pc == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0] [L406] __retres1 = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, __retres1=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0] [L408] return (__retres1); VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, \result=0, __retres1=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0] [L855] RET, EXPR is_transmit4_triggered() [L855] tmp___3 = is_transmit4_triggered() [L857] COND FALSE !(\read(tmp___3)) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, tmp=0, tmp___0=0, tmp___1=0, tmp___2=0, tmp___3=0] [L863] CALL, EXPR is_transmit5_triggered() [L412] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0] [L415] COND FALSE !(t5_pc == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0] [L425] __retres1 = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, __retres1=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0] [L427] return (__retres1); VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, \result=0, __retres1=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0] [L863] RET, EXPR is_transmit5_triggered() [L863] tmp___4 = is_transmit5_triggered() [L865] COND FALSE !(\read(tmp___4)) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, tmp=0, tmp___0=0, tmp___1=0, tmp___2=0, tmp___3=0, tmp___4=0] [L871] CALL, EXPR is_transmit6_triggered() [L431] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0] [L434] COND FALSE !(t6_pc == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0] [L444] __retres1 = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, __retres1=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0] [L446] return (__retres1); VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, \result=0, __retres1=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0] [L871] RET, EXPR is_transmit6_triggered() [L871] tmp___5 = is_transmit6_triggered() [L873] COND FALSE !(\read(tmp___5)) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, tmp=0, tmp___0=0, tmp___1=0, tmp___2=0, tmp___3=0, tmp___4=0, tmp___5=0] [L1020] RET activate_threads() [L1021] CALL reset_delta_events() [L743] COND FALSE !(M_E == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0] [L748] COND FALSE !(T1_E == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0] [L753] COND FALSE !(T2_E == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0] [L758] COND FALSE !(T3_E == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0] [L763] COND FALSE !(T4_E == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0] [L768] COND FALSE !(T5_E == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0] [L773] COND FALSE !(T6_E == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0] [L778] COND FALSE !(E_1 == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0] [L783] COND FALSE !(E_2 == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0] [L788] COND FALSE !(E_3 == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0] [L793] COND FALSE !(E_4 == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0] [L798] COND FALSE !(E_5 == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0] [L803] COND FALSE !(E_6 == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0] [L1021] RET reset_delta_events() [L1024] COND TRUE 1 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, kernel_st=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0] [L1027] kernel_st = 1 [L1028] CALL eval() [L547] int tmp ; VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0] Loop: [L551] COND TRUE 1 [L554] CALL, EXPR exists_runnable_thread() [L501] int __retres1 ; [L504] COND TRUE m_st == 0 [L505] __retres1 = 1 [L542] return (__retres1); [L554] RET, EXPR exists_runnable_thread() [L554] tmp = exists_runnable_thread() [L556] COND TRUE \read(tmp) [L561] COND TRUE m_st == 0 [L562] int tmp_ndt_1; [L563] EXPR tmp_ndt_1 = __VERIFIER_nondet_int() [L564] COND FALSE, EXPR !(\read(tmp_ndt_1)) [L561-L572] { int tmp_ndt_1; tmp_ndt_1 = __VERIFIER_nondet_int(); if (tmp_ndt_1) { { m_st = 1; master(); } } else { } } [L575] COND TRUE t1_st == 0 [L576] int tmp_ndt_2; [L577] EXPR tmp_ndt_2 = __VERIFIER_nondet_int() [L578] COND FALSE, EXPR !(\read(tmp_ndt_2)) [L575-L586] { int tmp_ndt_2; tmp_ndt_2 = __VERIFIER_nondet_int(); if (tmp_ndt_2) { { t1_st = 1; transmit1(); } } else { } } [L589] COND TRUE t2_st == 0 [L590] int tmp_ndt_3; [L591] EXPR tmp_ndt_3 = __VERIFIER_nondet_int() [L592] COND FALSE, EXPR !(\read(tmp_ndt_3)) [L589-L600] { int tmp_ndt_3; tmp_ndt_3 = __VERIFIER_nondet_int(); if (tmp_ndt_3) { { t2_st = 1; transmit2(); } } else { } } [L603] COND TRUE t3_st == 0 [L604] int tmp_ndt_4; [L605] EXPR tmp_ndt_4 = __VERIFIER_nondet_int() [L606] COND FALSE, EXPR !(\read(tmp_ndt_4)) [L603-L614] { int tmp_ndt_4; tmp_ndt_4 = __VERIFIER_nondet_int(); if (tmp_ndt_4) { { t3_st = 1; transmit3(); } } else { } } [L617] COND TRUE t4_st == 0 [L618] int tmp_ndt_5; [L619] EXPR tmp_ndt_5 = __VERIFIER_nondet_int() [L620] COND FALSE, EXPR !(\read(tmp_ndt_5)) [L617-L628] { int tmp_ndt_5; tmp_ndt_5 = __VERIFIER_nondet_int(); if (tmp_ndt_5) { { t4_st = 1; transmit4(); } } else { } } [L631] COND TRUE t5_st == 0 [L632] int tmp_ndt_6; [L633] EXPR tmp_ndt_6 = __VERIFIER_nondet_int() [L634] COND FALSE, EXPR !(\read(tmp_ndt_6)) [L631-L642] { int tmp_ndt_6; tmp_ndt_6 = __VERIFIER_nondet_int(); if (tmp_ndt_6) { { t5_st = 1; transmit5(); } } else { } } [L645] COND TRUE t6_st == 0 [L646] int tmp_ndt_7; [L647] EXPR tmp_ndt_7 = __VERIFIER_nondet_int() [L648] COND FALSE, EXPR !(\read(tmp_ndt_7)) [L645-L656] { int tmp_ndt_7; tmp_ndt_7 = __VERIFIER_nondet_int(); if (tmp_ndt_7) { { t6_st = 1; transmit6(); } } else { } } End of lasso representation. RESULT: Ultimate proved your program to be incorrect! [2023-11-06 22:08:54,547 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_13dea121-f3fd-4f40-8510-ef12d3d88dee/bin/uautomizer-verify-WvqO1wxjHP/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (1)] Forceful destruction successful, exit code 0 Received shutdown request... --- End real Ultimate output --- Execution finished normally Writing output log to file Ultimate.log Writing human readable error path to file UltimateCounterExample.errorpath Result: FALSE(TERM)