./Ultimate.py --spec ../../sv-benchmarks/c/properties/termination.prp --file ../../sv-benchmarks/c/systemc/transmitter.08.cil.c --full-output --architecture 32bit -------------------------------------------------------------------------------- Checking for termination Using default analysis Version e7bb482b Calling Ultimate with: /usr/lib/jvm/java-1.11.0-openjdk-amd64/bin/java -Dosgi.configuration.area=/tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_93969d14-f320-4438-a835-14eef8cfe3b0/bin/uautomizer-verify-WvqO1wxjHP/data/config -Xmx15G -Xms4m -jar /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_93969d14-f320-4438-a835-14eef8cfe3b0/bin/uautomizer-verify-WvqO1wxjHP/plugins/org.eclipse.equinox.launcher_1.5.800.v20200727-1323.jar -data @noDefault -ultimatedata /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_93969d14-f320-4438-a835-14eef8cfe3b0/bin/uautomizer-verify-WvqO1wxjHP/data -tc /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_93969d14-f320-4438-a835-14eef8cfe3b0/bin/uautomizer-verify-WvqO1wxjHP/config/AutomizerTermination.xml -i ../../sv-benchmarks/c/systemc/transmitter.08.cil.c -s /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_93969d14-f320-4438-a835-14eef8cfe3b0/bin/uautomizer-verify-WvqO1wxjHP/config/svcomp-Termination-32bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_93969d14-f320-4438-a835-14eef8cfe3b0/bin/uautomizer-verify-WvqO1wxjHP --witnessprinter.witness.filename witness.graphml --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(F end) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 32bit --witnessprinter.graph.data.programhash d0fbb3eaba725aed5c3b8bf09c66f0f1daed4feeee0b9a3792dc033de334e501 --- Real Ultimate output --- This is Ultimate 0.2.3-dev-e7bb482 [2023-11-06 21:58:32,959 INFO L188 SettingsManager]: Resetting all preferences to default values... [2023-11-06 21:58:33,064 INFO L114 SettingsManager]: Loading settings from /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_93969d14-f320-4438-a835-14eef8cfe3b0/bin/uautomizer-verify-WvqO1wxjHP/config/svcomp-Termination-32bit-Automizer_Default.epf [2023-11-06 21:58:33,073 WARN L101 SettingsManager]: Preference file contains the following unknown settings: [2023-11-06 21:58:33,074 WARN L103 SettingsManager]: * de.uni_freiburg.informatik.ultimate.core.Log level for class [2023-11-06 21:58:33,115 INFO L130 SettingsManager]: Preferences different from defaults after loading the file: [2023-11-06 21:58:33,116 INFO L151 SettingsManager]: Preferences of UltimateCore differ from their defaults: [2023-11-06 21:58:33,117 INFO L153 SettingsManager]: * Log level for class=de.uni_freiburg.informatik.ultimate.lib.smtlibutils.quantifier.QuantifierPusher=ERROR; [2023-11-06 21:58:33,118 INFO L151 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2023-11-06 21:58:33,125 INFO L153 SettingsManager]: * Create parallel compositions if possible=false [2023-11-06 21:58:33,127 INFO L153 SettingsManager]: * Use SBE=true [2023-11-06 21:58:33,127 INFO L151 SettingsManager]: Preferences of BuchiAutomizer differ from their defaults: [2023-11-06 21:58:33,128 INFO L153 SettingsManager]: * NCSB implementation=INTSET_LAZY3 [2023-11-06 21:58:33,130 INFO L153 SettingsManager]: * Use old map elimination=false [2023-11-06 21:58:33,130 INFO L153 SettingsManager]: * Use external solver (rank synthesis)=false [2023-11-06 21:58:33,130 INFO L153 SettingsManager]: * Use only trivial implications for array writes=true [2023-11-06 21:58:33,131 INFO L153 SettingsManager]: * Rank analysis=LINEAR_WITH_GUESSES [2023-11-06 21:58:33,132 INFO L151 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2023-11-06 21:58:33,132 INFO L153 SettingsManager]: * Pointer base address is valid at dereference=ASSUME [2023-11-06 21:58:33,133 INFO L153 SettingsManager]: * sizeof long=4 [2023-11-06 21:58:33,133 INFO L153 SettingsManager]: * Overapproximate operations on floating types=true [2023-11-06 21:58:33,134 INFO L153 SettingsManager]: * sizeof POINTER=4 [2023-11-06 21:58:33,134 INFO L153 SettingsManager]: * Check division by zero=IGNORE [2023-11-06 21:58:33,134 INFO L153 SettingsManager]: * Pointer to allocated memory at dereference=ASSUME [2023-11-06 21:58:33,135 INFO L153 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=ASSUME [2023-11-06 21:58:33,135 INFO L153 SettingsManager]: * Check array bounds for arrays that are off heap=ASSUME [2023-11-06 21:58:33,136 INFO L153 SettingsManager]: * Check unreachability of reach_error function=false [2023-11-06 21:58:33,136 INFO L153 SettingsManager]: * sizeof long double=12 [2023-11-06 21:58:33,136 INFO L153 SettingsManager]: * Check if freed pointer was valid=false [2023-11-06 21:58:33,137 INFO L153 SettingsManager]: * Assume nondeterminstic values are in range=false [2023-11-06 21:58:33,138 INFO L153 SettingsManager]: * Use constant arrays=true [2023-11-06 21:58:33,139 INFO L151 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2023-11-06 21:58:33,139 INFO L153 SettingsManager]: * Size of a code block=SequenceOfStatements [2023-11-06 21:58:33,139 INFO L151 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2023-11-06 21:58:33,139 INFO L153 SettingsManager]: * Trace refinement strategy=CAMEL [2023-11-06 21:58:33,140 INFO L151 SettingsManager]: Preferences of IcfgTransformer differ from their defaults: [2023-11-06 21:58:33,140 INFO L153 SettingsManager]: * TransformationType=MODULO_NEIGHBOR WARNING: An illegal reflective access operation has occurred WARNING: Illegal reflective access by com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 (file:/tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_93969d14-f320-4438-a835-14eef8cfe3b0/bin/uautomizer-verify-WvqO1wxjHP/plugins/com.sun.xml.bind_2.2.0.v201505121915.jar) to method java.lang.ClassLoader.defineClass(java.lang.String,byte[],int,int) WARNING: Please consider reporting this to the maintainers of com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 WARNING: Use --illegal-access=warn to enable warnings of further illegal reflective access operations WARNING: All illegal access operations will be denied in a future release Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_93969d14-f320-4438-a835-14eef8cfe3b0/bin/uautomizer-verify-WvqO1wxjHP Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness.graphml Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(F end) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 32bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> d0fbb3eaba725aed5c3b8bf09c66f0f1daed4feeee0b9a3792dc033de334e501 [2023-11-06 21:58:33,414 INFO L75 nceAwareModelManager]: Repository-Root is: /tmp [2023-11-06 21:58:33,439 INFO L261 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2023-11-06 21:58:33,441 INFO L217 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2023-11-06 21:58:33,443 INFO L270 PluginConnector]: Initializing CDTParser... [2023-11-06 21:58:33,444 INFO L274 PluginConnector]: CDTParser initialized [2023-11-06 21:58:33,445 INFO L431 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_93969d14-f320-4438-a835-14eef8cfe3b0/bin/uautomizer-verify-WvqO1wxjHP/../../sv-benchmarks/c/systemc/transmitter.08.cil.c [2023-11-06 21:58:36,535 INFO L533 CDTParser]: Created temporary CDT project at NULL [2023-11-06 21:58:36,780 INFO L384 CDTParser]: Found 1 translation units. [2023-11-06 21:58:36,780 INFO L180 CDTParser]: Scanning /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_93969d14-f320-4438-a835-14eef8cfe3b0/sv-benchmarks/c/systemc/transmitter.08.cil.c [2023-11-06 21:58:36,796 INFO L427 CDTParser]: About to delete temporary CDT project at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_93969d14-f320-4438-a835-14eef8cfe3b0/bin/uautomizer-verify-WvqO1wxjHP/data/04b710ac4/a597a2ff646c4c76afade0f7cddf23dd/FLAG99c0e3d96 [2023-11-06 21:58:36,811 INFO L435 CDTParser]: Successfully deleted /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_93969d14-f320-4438-a835-14eef8cfe3b0/bin/uautomizer-verify-WvqO1wxjHP/data/04b710ac4/a597a2ff646c4c76afade0f7cddf23dd [2023-11-06 21:58:36,814 INFO L299 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2023-11-06 21:58:36,815 INFO L133 ToolchainWalker]: Walking toolchain with 6 elements. [2023-11-06 21:58:36,817 INFO L112 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2023-11-06 21:58:36,817 INFO L270 PluginConnector]: Initializing CACSL2BoogieTranslator... [2023-11-06 21:58:36,829 INFO L274 PluginConnector]: CACSL2BoogieTranslator initialized [2023-11-06 21:58:36,830 INFO L184 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 06.11 09:58:36" (1/1) ... [2023-11-06 21:58:36,831 INFO L204 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@5b7b67d7 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.11 09:58:36, skipping insertion in model container [2023-11-06 21:58:36,831 INFO L184 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 06.11 09:58:36" (1/1) ... [2023-11-06 21:58:36,902 INFO L177 MainTranslator]: Built tables and reachable declarations [2023-11-06 21:58:37,275 INFO L209 PostProcessor]: Analyzing one entry point: main [2023-11-06 21:58:37,296 INFO L202 MainTranslator]: Completed pre-run [2023-11-06 21:58:37,397 INFO L209 PostProcessor]: Analyzing one entry point: main [2023-11-06 21:58:37,424 INFO L206 MainTranslator]: Completed translation [2023-11-06 21:58:37,425 INFO L201 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.11 09:58:37 WrapperNode [2023-11-06 21:58:37,425 INFO L131 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2023-11-06 21:58:37,427 INFO L112 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2023-11-06 21:58:37,427 INFO L270 PluginConnector]: Initializing Boogie Procedure Inliner... [2023-11-06 21:58:37,427 INFO L274 PluginConnector]: Boogie Procedure Inliner initialized [2023-11-06 21:58:37,434 INFO L184 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.11 09:58:37" (1/1) ... [2023-11-06 21:58:37,462 INFO L184 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.11 09:58:37" (1/1) ... [2023-11-06 21:58:37,547 INFO L138 Inliner]: procedures = 44, calls = 55, calls flagged for inlining = 50, calls inlined = 147, statements flattened = 2216 [2023-11-06 21:58:37,548 INFO L131 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2023-11-06 21:58:37,548 INFO L112 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2023-11-06 21:58:37,549 INFO L270 PluginConnector]: Initializing Boogie Preprocessor... [2023-11-06 21:58:37,549 INFO L274 PluginConnector]: Boogie Preprocessor initialized [2023-11-06 21:58:37,559 INFO L184 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.11 09:58:37" (1/1) ... [2023-11-06 21:58:37,560 INFO L184 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.11 09:58:37" (1/1) ... [2023-11-06 21:58:37,571 INFO L184 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.11 09:58:37" (1/1) ... [2023-11-06 21:58:37,584 INFO L184 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.11 09:58:37" (1/1) ... [2023-11-06 21:58:37,651 INFO L184 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.11 09:58:37" (1/1) ... [2023-11-06 21:58:37,734 INFO L184 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.11 09:58:37" (1/1) ... [2023-11-06 21:58:37,738 INFO L184 PluginConnector]: Executing the observer LTLStepAnnotator from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.11 09:58:37" (1/1) ... [2023-11-06 21:58:37,759 INFO L184 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.11 09:58:37" (1/1) ... [2023-11-06 21:58:37,807 INFO L131 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2023-11-06 21:58:37,809 INFO L112 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2023-11-06 21:58:37,809 INFO L270 PluginConnector]: Initializing RCFGBuilder... [2023-11-06 21:58:37,809 INFO L274 PluginConnector]: RCFGBuilder initialized [2023-11-06 21:58:37,810 INFO L184 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.11 09:58:37" (1/1) ... [2023-11-06 21:58:37,816 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2023-11-06 21:58:37,828 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_93969d14-f320-4438-a835-14eef8cfe3b0/bin/uautomizer-verify-WvqO1wxjHP/z3 [2023-11-06 21:58:37,844 INFO L229 MonitoredProcess]: Starting monitored process 1 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_93969d14-f320-4438-a835-14eef8cfe3b0/bin/uautomizer-verify-WvqO1wxjHP/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2023-11-06 21:58:37,871 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_93969d14-f320-4438-a835-14eef8cfe3b0/bin/uautomizer-verify-WvqO1wxjHP/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (1)] Waiting until timeout for monitored process [2023-11-06 21:58:37,892 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocInit [2023-11-06 21:58:37,892 INFO L130 BoogieDeclarations]: Found specification of procedure write~init~int [2023-11-06 21:58:37,893 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2023-11-06 21:58:37,893 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2023-11-06 21:58:38,033 INFO L236 CfgBuilder]: Building ICFG [2023-11-06 21:58:38,035 INFO L262 CfgBuilder]: Building CFG for each procedure with an implementation [2023-11-06 21:58:39,578 INFO L277 CfgBuilder]: Performing block encoding [2023-11-06 21:58:39,601 INFO L297 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2023-11-06 21:58:39,602 INFO L302 CfgBuilder]: Removed 12 assume(true) statements. [2023-11-06 21:58:39,608 INFO L201 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 06.11 09:58:39 BoogieIcfgContainer [2023-11-06 21:58:39,609 INFO L131 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2023-11-06 21:58:39,610 INFO L112 PluginConnector]: ------------------------BuchiAutomizer---------------------------- [2023-11-06 21:58:39,611 INFO L270 PluginConnector]: Initializing BuchiAutomizer... [2023-11-06 21:58:39,615 INFO L274 PluginConnector]: BuchiAutomizer initialized [2023-11-06 21:58:39,616 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2023-11-06 21:58:39,616 INFO L184 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "CDTParser AST 06.11 09:58:36" (1/3) ... [2023-11-06 21:58:39,617 INFO L204 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@18b7081 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 06.11 09:58:39, skipping insertion in model container [2023-11-06 21:58:39,618 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2023-11-06 21:58:39,618 INFO L184 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.11 09:58:37" (2/3) ... [2023-11-06 21:58:39,620 INFO L204 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@18b7081 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 06.11 09:58:39, skipping insertion in model container [2023-11-06 21:58:39,620 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2023-11-06 21:58:39,620 INFO L184 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 06.11 09:58:39" (3/3) ... [2023-11-06 21:58:39,625 INFO L332 chiAutomizerObserver]: Analyzing ICFG transmitter.08.cil.c [2023-11-06 21:58:39,710 INFO L303 stractBuchiCegarLoop]: Interprodecural is true [2023-11-06 21:58:39,711 INFO L304 stractBuchiCegarLoop]: Hoare is false [2023-11-06 21:58:39,711 INFO L305 stractBuchiCegarLoop]: Compute interpolants for ForwardPredicates [2023-11-06 21:58:39,711 INFO L306 stractBuchiCegarLoop]: Backedges is STRAIGHT_LINE [2023-11-06 21:58:39,711 INFO L307 stractBuchiCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2023-11-06 21:58:39,712 INFO L308 stractBuchiCegarLoop]: Difference is false [2023-11-06 21:58:39,712 INFO L309 stractBuchiCegarLoop]: Minimize is MINIMIZE_SEVPA [2023-11-06 21:58:39,712 INFO L313 stractBuchiCegarLoop]: ======== Iteration 0 == of CEGAR loop == BuchiAutomatonCegarLoop ======== [2023-11-06 21:58:39,721 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 941 states, 940 states have (on average 1.5127659574468084) internal successors, (1422), 940 states have internal predecessors, (1422), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-06 21:58:39,791 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 824 [2023-11-06 21:58:39,792 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-06 21:58:39,793 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-06 21:58:39,811 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-06 21:58:39,813 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-06 21:58:39,813 INFO L335 stractBuchiCegarLoop]: ======== Iteration 1 ============ [2023-11-06 21:58:39,816 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 941 states, 940 states have (on average 1.5127659574468084) internal successors, (1422), 940 states have internal predecessors, (1422), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-06 21:58:39,833 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 824 [2023-11-06 21:58:39,833 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-06 21:58:39,833 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-06 21:58:39,844 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-06 21:58:39,844 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-06 21:58:39,862 INFO L748 eck$LassoCheckResult]: Stem: 126#$Ultimate##0true assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2; 859#L-1true assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~10#1;havoc main_~__retres1~10#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; 683#init_model_returnLabel#1true assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret24#1, start_simulation_#t~ret25#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 855#update_channels_returnLabel#1true assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 685#L581true assume !(1 == ~m_i~0);~m_st~0 := 2; 193#L581-2true assume 1 == ~t1_i~0;~t1_st~0 := 0; 827#L586-1true assume !(1 == ~t2_i~0);~t2_st~0 := 2; 676#L591-1true assume !(1 == ~t3_i~0);~t3_st~0 := 2; 652#L596-1true assume !(1 == ~t4_i~0);~t4_st~0 := 2; 239#L601-1true assume !(1 == ~t5_i~0);~t5_st~0 := 2; 686#L606-1true assume !(1 == ~t6_i~0);~t6_st~0 := 2; 413#L611-1true assume !(1 == ~t7_i~0);~t7_st~0 := 2; 771#L616-1true assume !(1 == ~t8_i~0);~t8_st~0 := 2; 295#L621-1true assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 713#L838true assume !(0 == ~M_E~0); 422#L838-2true assume !(0 == ~T1_E~0); 25#L843-1true assume !(0 == ~T2_E~0); 83#L848-1true assume !(0 == ~T3_E~0); 435#L853-1true assume !(0 == ~T4_E~0); 287#L858-1true assume 0 == ~T5_E~0;~T5_E~0 := 1; 2#L863-1true assume !(0 == ~T6_E~0); 764#L868-1true assume !(0 == ~T7_E~0); 884#L873-1true assume !(0 == ~T8_E~0); 758#L878-1true assume !(0 == ~E_1~0); 722#L883-1true assume !(0 == ~E_2~0); 797#L888-1true assume !(0 == ~E_3~0); 390#L893-1true assume !(0 == ~E_4~0); 798#L898-1true assume 0 == ~E_5~0;~E_5~0 := 1; 928#L903-1true assume !(0 == ~E_6~0); 719#L908-1true assume !(0 == ~E_7~0); 506#L913-1true assume !(0 == ~E_8~0); 30#L918-1true assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 525#L402true assume !(1 == ~m_pc~0); 271#L402-2true is_master_triggered_~__retres1~0#1 := 0; 96#L413true is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 575#is_master_triggered_returnLabel#1true activate_threads_#t~ret14#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 243#L1035true assume !(0 != activate_threads_~tmp~1#1); 279#L1035-2true assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 710#L421true assume 1 == ~t1_pc~0; 826#L422true assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 900#L432true is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 32#is_transmit1_triggered_returnLabel#1true activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 315#L1043true assume !(0 != activate_threads_~tmp___0~0#1); 787#L1043-2true assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 912#L440true assume 1 == ~t2_pc~0; 18#L441true assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 101#L451true is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 209#is_transmit2_triggered_returnLabel#1true activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 833#L1051true assume !(0 != activate_threads_~tmp___1~0#1); 527#L1051-2true assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 213#L459true assume !(1 == ~t3_pc~0); 702#L459-2true is_transmit3_triggered_~__retres1~3#1 := 0; 782#L470true is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 12#is_transmit3_triggered_returnLabel#1true activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 93#L1059true assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 934#L1059-2true assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 98#L478true assume 1 == ~t4_pc~0; 394#L479true assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 674#L489true is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 67#is_transmit4_triggered_returnLabel#1true activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 198#L1067true assume !(0 != activate_threads_~tmp___3~0#1); 50#L1067-2true assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 432#L497true assume !(1 == ~t5_pc~0); 361#L497-2true is_transmit5_triggered_~__retres1~5#1 := 0; 458#L508true is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 577#is_transmit5_triggered_returnLabel#1true activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 788#L1075true assume !(0 != activate_threads_~tmp___4~0#1); 696#L1075-2true assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 891#L516true assume 1 == ~t6_pc~0; 892#L517true assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 412#L527true is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 199#is_transmit6_triggered_returnLabel#1true activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 123#L1083true assume !(0 != activate_threads_~tmp___5~0#1); 472#L1083-2true assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 406#L535true assume !(1 == ~t7_pc~0); 802#L535-2true is_transmit7_triggered_~__retres1~7#1 := 0; 470#L546true is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 870#is_transmit7_triggered_returnLabel#1true activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 500#L1091true assume !(0 != activate_threads_~tmp___6~0#1); 493#L1091-2true assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 687#L554true assume 1 == ~t8_pc~0; 438#L555true assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 828#L565true is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 518#is_transmit8_triggered_returnLabel#1true activate_threads_#t~ret22#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 171#L1099true assume !(0 != activate_threads_~tmp___7~0#1); 501#L1099-2true havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 7#L931true assume !(1 == ~M_E~0); 743#L931-2true assume 1 == ~T1_E~0;~T1_E~0 := 2; 824#L936-1true assume !(1 == ~T2_E~0); 909#L941-1true assume !(1 == ~T3_E~0); 280#L946-1true assume !(1 == ~T4_E~0); 707#L951-1true assume !(1 == ~T5_E~0); 131#L956-1true assume !(1 == ~T6_E~0); 893#L961-1true assume !(1 == ~T7_E~0); 391#L966-1true assume !(1 == ~T8_E~0); 495#L971-1true assume 1 == ~E_1~0;~E_1~0 := 2; 845#L976-1true assume !(1 == ~E_2~0); 463#L981-1true assume !(1 == ~E_3~0); 283#L986-1true assume !(1 == ~E_4~0); 146#L991-1true assume !(1 == ~E_5~0); 874#L996-1true assume !(1 == ~E_6~0); 776#L1001-1true assume !(1 == ~E_7~0); 431#L1006-1true assume !(1 == ~E_8~0); 708#L1011-1true assume { :end_inline_reset_delta_events } true; 36#L1272-2true [2023-11-06 21:58:39,875 INFO L750 eck$LassoCheckResult]: Loop: 36#L1272-2true assume !false; 427#L1273true start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 837#L813-1true assume false; 524#eval_returnLabel#1true havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 316#update_channels_returnLabel#2true assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 657#L838-3true assume 0 == ~M_E~0;~M_E~0 := 1; 478#L838-5true assume !(0 == ~T1_E~0); 808#L843-3true assume 0 == ~T2_E~0;~T2_E~0 := 1; 350#L848-3true assume 0 == ~T3_E~0;~T3_E~0 := 1; 392#L853-3true assume 0 == ~T4_E~0;~T4_E~0 := 1; 585#L858-3true assume 0 == ~T5_E~0;~T5_E~0 := 1; 452#L863-3true assume 0 == ~T6_E~0;~T6_E~0 := 1; 442#L868-3true assume 0 == ~T7_E~0;~T7_E~0 := 1; 461#L873-3true assume 0 == ~T8_E~0;~T8_E~0 := 1; 160#L878-3true assume !(0 == ~E_1~0); 19#L883-3true assume 0 == ~E_2~0;~E_2~0 := 1; 671#L888-3true assume 0 == ~E_3~0;~E_3~0 := 1; 20#L893-3true assume 0 == ~E_4~0;~E_4~0 := 1; 298#L898-3true assume 0 == ~E_5~0;~E_5~0 := 1; 606#L903-3true assume 0 == ~E_6~0;~E_6~0 := 1; 796#L908-3true assume 0 == ~E_7~0;~E_7~0 := 1; 303#L913-3true assume 0 == ~E_8~0;~E_8~0 := 1; 38#L918-3true assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 902#L402-27true assume 1 == ~m_pc~0; 14#L403-9true assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 850#L413-9true is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 471#is_master_triggered_returnLabel#10true activate_threads_#t~ret14#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 748#L1035-27true assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 640#L1035-29true assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 673#L421-27true assume 1 == ~t1_pc~0; 504#L422-9true assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 832#L432-9true is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 374#is_transmit1_triggered_returnLabel#10true activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 777#L1043-27true assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 898#L1043-29true assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 407#L440-27true assume 1 == ~t2_pc~0; 880#L441-9true assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 940#L451-9true is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 446#is_transmit2_triggered_returnLabel#10true activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 330#L1051-27true assume !(0 != activate_threads_~tmp___1~0#1); 420#L1051-29true assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 148#L459-27true assume !(1 == ~t3_pc~0); 662#L459-29true is_transmit3_triggered_~__retres1~3#1 := 0; 847#L470-9true is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 312#is_transmit3_triggered_returnLabel#10true activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 405#L1059-27true assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 762#L1059-29true assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 895#L478-27true assume !(1 == ~t4_pc~0); 141#L478-29true is_transmit4_triggered_~__retres1~4#1 := 0; 414#L489-9true is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 252#is_transmit4_triggered_returnLabel#10true activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 555#L1067-27true assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 763#L1067-29true assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 607#L497-27true assume 1 == ~t5_pc~0; 840#L498-9true assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 166#L508-9true is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 602#is_transmit5_triggered_returnLabel#10true activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 134#L1075-27true assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 678#L1075-29true assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 300#L516-27true assume !(1 == ~t6_pc~0); 418#L516-29true is_transmit6_triggered_~__retres1~6#1 := 0; 203#L527-9true is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 752#is_transmit6_triggered_returnLabel#10true activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 424#L1083-27true assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 774#L1083-29true assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 254#L535-27true assume !(1 == ~t7_pc~0); 534#L535-29true is_transmit7_triggered_~__retres1~7#1 := 0; 937#L546-9true is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 180#is_transmit7_triggered_returnLabel#10true activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 842#L1091-27true assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 225#L1091-29true assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 786#L554-27true assume !(1 == ~t8_pc~0); 26#L554-29true is_transmit8_triggered_~__retres1~8#1 := 0; 100#L565-9true is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 550#is_transmit8_triggered_returnLabel#10true activate_threads_#t~ret22#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 335#L1099-27true assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 158#L1099-29true havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 529#L931-3true assume 1 == ~M_E~0;~M_E~0 := 2; 91#L931-5true assume 1 == ~T1_E~0;~T1_E~0 := 2; 223#L936-3true assume 1 == ~T2_E~0;~T2_E~0 := 2; 311#L941-3true assume 1 == ~T3_E~0;~T3_E~0 := 2; 531#L946-3true assume 1 == ~T4_E~0;~T4_E~0 := 2; 168#L951-3true assume !(1 == ~T5_E~0); 513#L956-3true assume 1 == ~T6_E~0;~T6_E~0 := 2; 371#L961-3true assume 1 == ~T7_E~0;~T7_E~0 := 2; 232#L966-3true assume 1 == ~T8_E~0;~T8_E~0 := 2; 726#L971-3true assume 1 == ~E_1~0;~E_1~0 := 2; 411#L976-3true assume 1 == ~E_2~0;~E_2~0 := 2; 35#L981-3true assume 1 == ~E_3~0;~E_3~0 := 2; 159#L986-3true assume 1 == ~E_4~0;~E_4~0 := 2; 29#L991-3true assume !(1 == ~E_5~0); 482#L996-3true assume 1 == ~E_6~0;~E_6~0 := 2; 611#L1001-3true assume 1 == ~E_7~0;~E_7~0 := 2; 215#L1006-3true assume 1 == ~E_8~0;~E_8~0 := 2; 516#L1011-3true assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 48#L634-1true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 314#L681-1true exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 183#exists_runnable_thread_returnLabel#2true start_simulation_#t~ret24#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret24#1;havoc start_simulation_#t~ret24#1; 792#L1291true assume !(0 == start_simulation_~tmp~3#1); 759#L1291-2true assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 293#L634-2true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 4#L681-2true exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 31#exists_runnable_thread_returnLabel#3true stop_simulation_#t~ret23#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret23#1;havoc stop_simulation_#t~ret23#1; 730#L1246true assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 267#L1253true stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 329#stop_simulation_returnLabel#1true start_simulation_#t~ret25#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret25#1;havoc start_simulation_#t~ret25#1; 556#L1304true assume !(0 != start_simulation_~tmp___0~1#1); 36#L1272-2true [2023-11-06 21:58:39,881 INFO L145 PredicateUnifier]: Initialized classic predicate unifier [2023-11-06 21:58:39,883 INFO L85 PathProgramCache]: Analyzing trace with hash -1897256038, now seen corresponding path program 1 times [2023-11-06 21:58:39,894 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-06 21:58:39,894 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [3914790] [2023-11-06 21:58:39,894 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-06 21:58:39,895 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-06 21:58:40,013 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-06 21:58:40,272 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-06 21:58:40,277 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-06 21:58:40,277 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [3914790] [2023-11-06 21:58:40,278 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [3914790] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-06 21:58:40,278 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-06 21:58:40,278 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-06 21:58:40,280 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [138121641] [2023-11-06 21:58:40,281 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-06 21:58:40,292 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-06 21:58:40,296 INFO L145 PredicateUnifier]: Initialized classic predicate unifier [2023-11-06 21:58:40,297 INFO L85 PathProgramCache]: Analyzing trace with hash -651940443, now seen corresponding path program 1 times [2023-11-06 21:58:40,297 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-06 21:58:40,297 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [233767841] [2023-11-06 21:58:40,297 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-06 21:58:40,298 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-06 21:58:40,323 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-06 21:58:40,419 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-06 21:58:40,419 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-06 21:58:40,420 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [233767841] [2023-11-06 21:58:40,420 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [233767841] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-06 21:58:40,420 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-06 21:58:40,420 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2023-11-06 21:58:40,420 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [232945041] [2023-11-06 21:58:40,421 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-06 21:58:40,422 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-06 21:58:40,423 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-06 21:58:40,459 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-06 21:58:40,460 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-06 21:58:40,464 INFO L87 Difference]: Start difference. First operand has 941 states, 940 states have (on average 1.5127659574468084) internal successors, (1422), 940 states have internal predecessors, (1422), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand has 3 states, 3 states have (on average 34.666666666666664) internal successors, (104), 3 states have internal predecessors, (104), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-06 21:58:40,567 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-06 21:58:40,567 INFO L93 Difference]: Finished difference Result 939 states and 1394 transitions. [2023-11-06 21:58:40,569 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 939 states and 1394 transitions. [2023-11-06 21:58:40,582 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 820 [2023-11-06 21:58:40,598 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 939 states to 933 states and 1388 transitions. [2023-11-06 21:58:40,599 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 933 [2023-11-06 21:58:40,601 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 933 [2023-11-06 21:58:40,602 INFO L73 IsDeterministic]: Start isDeterministic. Operand 933 states and 1388 transitions. [2023-11-06 21:58:40,613 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-06 21:58:40,614 INFO L218 hiAutomatonCegarLoop]: Abstraction has 933 states and 1388 transitions. [2023-11-06 21:58:40,639 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 933 states and 1388 transitions. [2023-11-06 21:58:40,714 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 933 to 933. [2023-11-06 21:58:40,723 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 933 states, 933 states have (on average 1.487674169346195) internal successors, (1388), 932 states have internal predecessors, (1388), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-06 21:58:40,727 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 933 states to 933 states and 1388 transitions. [2023-11-06 21:58:40,729 INFO L240 hiAutomatonCegarLoop]: Abstraction has 933 states and 1388 transitions. [2023-11-06 21:58:40,730 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-06 21:58:40,736 INFO L428 stractBuchiCegarLoop]: Abstraction has 933 states and 1388 transitions. [2023-11-06 21:58:40,737 INFO L335 stractBuchiCegarLoop]: ======== Iteration 2 ============ [2023-11-06 21:58:40,737 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 933 states and 1388 transitions. [2023-11-06 21:58:40,748 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 820 [2023-11-06 21:58:40,749 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-06 21:58:40,749 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-06 21:58:40,751 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-06 21:58:40,752 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-06 21:58:40,752 INFO L748 eck$LassoCheckResult]: Stem: 2139#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2; 2140#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~10#1;havoc main_~__retres1~10#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; 2766#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret24#1, start_simulation_#t~ret25#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 2767#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 2768#L581 assume 1 == ~m_i~0;~m_st~0 := 0; 2258#L581-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 2259#L586-1 assume !(1 == ~t2_i~0);~t2_st~0 := 2; 2764#L591-1 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 2760#L596-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 2330#L601-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 2331#L606-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 2565#L611-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 2566#L616-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 2414#L621-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 2415#L838 assume !(0 == ~M_E~0); 2573#L838-2 assume !(0 == ~T1_E~0); 1938#L843-1 assume !(0 == ~T2_E~0); 1939#L848-1 assume !(0 == ~T3_E~0); 2059#L853-1 assume !(0 == ~T4_E~0); 2401#L858-1 assume 0 == ~T5_E~0;~T5_E~0 := 1; 1889#L863-1 assume !(0 == ~T6_E~0); 1890#L868-1 assume !(0 == ~T7_E~0); 2796#L873-1 assume !(0 == ~T8_E~0); 2794#L878-1 assume !(0 == ~E_1~0); 2785#L883-1 assume !(0 == ~E_2~0); 2786#L888-1 assume !(0 == ~E_3~0); 2534#L893-1 assume !(0 == ~E_4~0); 2535#L898-1 assume 0 == ~E_5~0;~E_5~0 := 1; 2806#L903-1 assume !(0 == ~E_6~0); 2783#L908-1 assume !(0 == ~E_7~0); 2664#L913-1 assume !(0 == ~E_8~0); 1950#L918-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1951#L402 assume !(1 == ~m_pc~0); 2162#L402-2 is_master_triggered_~__retres1~0#1 := 0; 2083#L413 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 2084#is_master_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 2336#L1035 assume !(0 != activate_threads_~tmp~1#1); 2337#L1035-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 2389#L421 assume 1 == ~t1_pc~0; 2779#L422 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 2797#L432 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1953#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 1954#L1043 assume !(0 != activate_threads_~tmp___0~0#1); 2443#L1043-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 2804#L440 assume 1 == ~t2_pc~0; 1922#L441 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 1923#L451 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 2093#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 2284#L1051 assume !(0 != activate_threads_~tmp___1~0#1); 2679#L1051-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 2287#L459 assume !(1 == ~t3_pc~0); 2288#L459-2 is_transmit3_triggered_~__retres1~3#1 := 0; 2777#L470 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1911#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 1912#L1059 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 2078#L1059-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 2087#L478 assume 1 == ~t4_pc~0; 2088#L479 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 2539#L489 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 2031#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 2032#L1067 assume !(0 != activate_threads_~tmp___3~0#1); 1992#L1067-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1993#L497 assume !(1 == ~t5_pc~0); 2042#L497-2 is_transmit5_triggered_~__retres1~5#1 := 0; 2043#L508 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 2610#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 2716#L1075 assume !(0 != activate_threads_~tmp___4~0#1); 2773#L1075-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 2774#L516 assume 1 == ~t6_pc~0; 2820#L517 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 2564#L527 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 2267#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 2133#L1083 assume !(0 != activate_threads_~tmp___5~0#1); 2134#L1083-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 2553#L535 assume !(1 == ~t7_pc~0); 2554#L535-2 is_transmit7_triggered_~__retres1~7#1 := 0; 2624#L546 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 2625#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 2656#L1091 assume !(0 != activate_threads_~tmp___6~0#1); 2646#L1091-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 2647#L554 assume 1 == ~t8_pc~0; 2589#L555 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 1914#L565 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 2672#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 2221#L1099 assume !(0 != activate_threads_~tmp___7~0#1); 2222#L1099-2 havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1900#L931 assume !(1 == ~M_E~0); 1901#L931-2 assume 1 == ~T1_E~0;~T1_E~0 := 2; 2792#L936-1 assume !(1 == ~T2_E~0); 2811#L941-1 assume !(1 == ~T3_E~0); 2390#L946-1 assume !(1 == ~T4_E~0); 2391#L951-1 assume !(1 == ~T5_E~0); 2148#L956-1 assume !(1 == ~T6_E~0); 2149#L961-1 assume !(1 == ~T7_E~0); 2536#L966-1 assume !(1 == ~T8_E~0); 2537#L971-1 assume 1 == ~E_1~0;~E_1~0 := 2; 2649#L976-1 assume !(1 == ~E_2~0); 2614#L981-1 assume !(1 == ~E_3~0); 2394#L986-1 assume !(1 == ~E_4~0); 2175#L991-1 assume !(1 == ~E_5~0); 2176#L996-1 assume !(1 == ~E_6~0); 2801#L1001-1 assume !(1 == ~E_7~0); 2584#L1006-1 assume !(1 == ~E_8~0); 2585#L1011-1 assume { :end_inline_reset_delta_events } true; 1961#L1272-2 [2023-11-06 21:58:40,753 INFO L750 eck$LassoCheckResult]: Loop: 1961#L1272-2 assume !false; 1962#L1273 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 2198#L813-1 assume !false; 2734#L692 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 2735#L634 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 1964#L681 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 2303#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 2304#L696 assume !(0 != eval_~tmp~0#1); 2677#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 2444#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 2445#L838-3 assume 0 == ~M_E~0;~M_E~0 := 1; 2633#L838-5 assume !(0 == ~T1_E~0); 2634#L843-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 2487#L848-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 2488#L853-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 2538#L858-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 2603#L863-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 2593#L868-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 2594#L873-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 2202#L878-3 assume !(0 == ~E_1~0); 1925#L883-3 assume 0 == ~E_2~0;~E_2~0 := 1; 1926#L888-3 assume 0 == ~E_3~0;~E_3~0 := 1; 1927#L893-3 assume 0 == ~E_4~0;~E_4~0 := 1; 1928#L898-3 assume 0 == ~E_5~0;~E_5~0 := 1; 2420#L903-3 assume 0 == ~E_6~0;~E_6~0 := 1; 2736#L908-3 assume 0 == ~E_7~0;~E_7~0 := 1; 2428#L913-3 assume 0 == ~E_8~0;~E_8~0 := 1; 1966#L918-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1967#L402-27 assume 1 == ~m_pc~0; 1915#L403-9 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 1916#L413-9 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 2626#is_master_triggered_returnLabel#10 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 2627#L1035-27 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 2753#L1035-29 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 2754#L421-27 assume !(1 == ~t1_pc~0); 2192#L421-29 is_transmit1_triggered_~__retres1~1#1 := 0; 2193#L432-9 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 2512#is_transmit1_triggered_returnLabel#10 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 2513#L1043-27 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 2802#L1043-29 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 2556#L440-27 assume !(1 == ~t2_pc~0); 2557#L440-29 is_transmit2_triggered_~__retres1~2#1 := 0; 2731#L451-9 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 2598#is_transmit2_triggered_returnLabel#10 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 2463#L1051-27 assume !(0 != activate_threads_~tmp___1~0#1); 2464#L1051-29 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 2178#L459-27 assume 1 == ~t3_pc~0; 2179#L460-9 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 2619#L470-9 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 2440#is_transmit3_triggered_returnLabel#10 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 2441#L1059-27 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 2552#L1059-29 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 2795#L478-27 assume !(1 == ~t4_pc~0); 2167#L478-29 is_transmit4_triggered_~__retres1~4#1 := 0; 2168#L489-9 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 2351#is_transmit4_triggered_returnLabel#10 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 2352#L1067-27 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 2701#L1067-29 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 2737#L497-27 assume 1 == ~t5_pc~0; 2738#L498-9 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 2211#L508-9 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 2212#is_transmit5_triggered_returnLabel#10 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 2154#L1075-27 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 2155#L1075-29 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 2422#L516-27 assume !(1 == ~t6_pc~0); 2423#L516-29 is_transmit6_triggered_~__retres1~6#1 := 0; 2275#L527-9 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 2276#is_transmit6_triggered_returnLabel#10 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 2575#L1083-27 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 2576#L1083-29 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 2355#L535-27 assume 1 == ~t7_pc~0; 2356#L536-9 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 2685#L546-9 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 2235#is_transmit7_triggered_returnLabel#10 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 2236#L1091-27 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 2306#L1091-29 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 2307#L554-27 assume !(1 == ~t8_pc~0); 1940#L554-29 is_transmit8_triggered_~__retres1~8#1 := 0; 1941#L565-9 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 2092#is_transmit8_triggered_returnLabel#10 activate_threads_#t~ret22#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 2472#L1099-27 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 2199#L1099-29 havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 2200#L931-3 assume 1 == ~M_E~0;~M_E~0 := 2; 2074#L931-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 2075#L936-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 2305#L941-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 2439#L946-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 2215#L951-3 assume !(1 == ~T5_E~0); 2216#L956-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 2510#L961-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 2315#L966-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 2316#L971-3 assume 1 == ~E_1~0;~E_1~0 := 2; 2563#L976-3 assume 1 == ~E_2~0;~E_2~0 := 2; 1959#L981-3 assume 1 == ~E_3~0;~E_3~0 := 2; 1960#L986-3 assume 1 == ~E_4~0;~E_4~0 := 2; 1948#L991-3 assume !(1 == ~E_5~0); 1949#L996-3 assume 1 == ~E_6~0;~E_6~0 := 2; 2639#L1001-3 assume 1 == ~E_7~0;~E_7~0 := 2; 2292#L1006-3 assume 1 == ~E_8~0;~E_8~0 := 2; 2293#L1011-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 1987#L634-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 1988#L681-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 2241#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret24#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret24#1;havoc start_simulation_#t~ret24#1; 2242#L1291 assume !(0 == start_simulation_~tmp~3#1); 2507#L1291-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 2410#L634-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 1893#L681-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 1894#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret23#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret23#1;havoc stop_simulation_#t~ret23#1; 1952#L1246 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 2376#L1253 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 2377#stop_simulation_returnLabel#1 start_simulation_#t~ret25#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret25#1;havoc start_simulation_#t~ret25#1; 2462#L1304 assume !(0 != start_simulation_~tmp___0~1#1); 1961#L1272-2 [2023-11-06 21:58:40,753 INFO L145 PredicateUnifier]: Initialized classic predicate unifier [2023-11-06 21:58:40,754 INFO L85 PathProgramCache]: Analyzing trace with hash 500214492, now seen corresponding path program 1 times [2023-11-06 21:58:40,754 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-06 21:58:40,754 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [825302488] [2023-11-06 21:58:40,754 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-06 21:58:40,755 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-06 21:58:40,774 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-06 21:58:40,835 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-06 21:58:40,835 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-06 21:58:40,836 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [825302488] [2023-11-06 21:58:40,836 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [825302488] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-06 21:58:40,836 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-06 21:58:40,836 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-06 21:58:40,837 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1941732967] [2023-11-06 21:58:40,837 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-06 21:58:40,837 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-06 21:58:40,838 INFO L145 PredicateUnifier]: Initialized classic predicate unifier [2023-11-06 21:58:40,838 INFO L85 PathProgramCache]: Analyzing trace with hash 56067214, now seen corresponding path program 1 times [2023-11-06 21:58:40,838 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-06 21:58:40,839 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [36925064] [2023-11-06 21:58:40,839 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-06 21:58:40,839 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-06 21:58:40,868 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-06 21:58:40,947 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-06 21:58:40,947 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-06 21:58:40,947 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [36925064] [2023-11-06 21:58:40,948 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [36925064] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-06 21:58:40,948 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-06 21:58:40,948 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-06 21:58:40,948 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1717625826] [2023-11-06 21:58:40,949 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-06 21:58:40,949 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-06 21:58:40,949 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-06 21:58:40,950 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-06 21:58:40,950 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-06 21:58:40,950 INFO L87 Difference]: Start difference. First operand 933 states and 1388 transitions. cyclomatic complexity: 456 Second operand has 3 states, 3 states have (on average 34.666666666666664) internal successors, (104), 3 states have internal predecessors, (104), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-06 21:58:40,996 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-06 21:58:40,996 INFO L93 Difference]: Finished difference Result 933 states and 1387 transitions. [2023-11-06 21:58:40,996 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 933 states and 1387 transitions. [2023-11-06 21:58:41,006 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 820 [2023-11-06 21:58:41,015 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 933 states to 933 states and 1387 transitions. [2023-11-06 21:58:41,015 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 933 [2023-11-06 21:58:41,017 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 933 [2023-11-06 21:58:41,018 INFO L73 IsDeterministic]: Start isDeterministic. Operand 933 states and 1387 transitions. [2023-11-06 21:58:41,020 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-06 21:58:41,020 INFO L218 hiAutomatonCegarLoop]: Abstraction has 933 states and 1387 transitions. [2023-11-06 21:58:41,056 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 933 states and 1387 transitions. [2023-11-06 21:58:41,077 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 933 to 933. [2023-11-06 21:58:41,079 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 933 states, 933 states have (on average 1.4866023579849947) internal successors, (1387), 932 states have internal predecessors, (1387), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-06 21:58:41,084 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 933 states to 933 states and 1387 transitions. [2023-11-06 21:58:41,087 INFO L240 hiAutomatonCegarLoop]: Abstraction has 933 states and 1387 transitions. [2023-11-06 21:58:41,088 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-06 21:58:41,089 INFO L428 stractBuchiCegarLoop]: Abstraction has 933 states and 1387 transitions. [2023-11-06 21:58:41,089 INFO L335 stractBuchiCegarLoop]: ======== Iteration 3 ============ [2023-11-06 21:58:41,089 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 933 states and 1387 transitions. [2023-11-06 21:58:41,096 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 820 [2023-11-06 21:58:41,096 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-06 21:58:41,096 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-06 21:58:41,098 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-06 21:58:41,099 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-06 21:58:41,099 INFO L748 eck$LassoCheckResult]: Stem: 4012#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2; 4013#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~10#1;havoc main_~__retres1~10#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; 4639#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret24#1, start_simulation_#t~ret25#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 4640#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 4641#L581 assume 1 == ~m_i~0;~m_st~0 := 0; 4131#L581-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 4132#L586-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 4637#L591-1 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 4633#L596-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 4203#L601-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 4204#L606-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 4438#L611-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 4439#L616-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 4287#L621-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 4288#L838 assume !(0 == ~M_E~0); 4446#L838-2 assume !(0 == ~T1_E~0); 3811#L843-1 assume !(0 == ~T2_E~0); 3812#L848-1 assume !(0 == ~T3_E~0); 3932#L853-1 assume !(0 == ~T4_E~0); 4274#L858-1 assume 0 == ~T5_E~0;~T5_E~0 := 1; 3762#L863-1 assume !(0 == ~T6_E~0); 3763#L868-1 assume !(0 == ~T7_E~0); 4669#L873-1 assume !(0 == ~T8_E~0); 4667#L878-1 assume !(0 == ~E_1~0); 4658#L883-1 assume !(0 == ~E_2~0); 4659#L888-1 assume !(0 == ~E_3~0); 4407#L893-1 assume !(0 == ~E_4~0); 4408#L898-1 assume 0 == ~E_5~0;~E_5~0 := 1; 4679#L903-1 assume !(0 == ~E_6~0); 4656#L908-1 assume !(0 == ~E_7~0); 4537#L913-1 assume !(0 == ~E_8~0); 3823#L918-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 3824#L402 assume !(1 == ~m_pc~0); 4035#L402-2 is_master_triggered_~__retres1~0#1 := 0; 3956#L413 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 3957#is_master_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 4209#L1035 assume !(0 != activate_threads_~tmp~1#1); 4210#L1035-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 4262#L421 assume 1 == ~t1_pc~0; 4652#L422 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 4670#L432 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 3826#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 3827#L1043 assume !(0 != activate_threads_~tmp___0~0#1); 4316#L1043-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 4677#L440 assume 1 == ~t2_pc~0; 3795#L441 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 3796#L451 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 3966#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 4157#L1051 assume !(0 != activate_threads_~tmp___1~0#1); 4552#L1051-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 4160#L459 assume !(1 == ~t3_pc~0); 4161#L459-2 is_transmit3_triggered_~__retres1~3#1 := 0; 4650#L470 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 3784#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 3785#L1059 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 3951#L1059-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 3960#L478 assume 1 == ~t4_pc~0; 3961#L479 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 4412#L489 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 3904#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 3905#L1067 assume !(0 != activate_threads_~tmp___3~0#1); 3865#L1067-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 3866#L497 assume !(1 == ~t5_pc~0); 3915#L497-2 is_transmit5_triggered_~__retres1~5#1 := 0; 3916#L508 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 4483#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 4589#L1075 assume !(0 != activate_threads_~tmp___4~0#1); 4646#L1075-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 4647#L516 assume 1 == ~t6_pc~0; 4693#L517 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 4437#L527 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 4140#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 4006#L1083 assume !(0 != activate_threads_~tmp___5~0#1); 4007#L1083-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 4426#L535 assume !(1 == ~t7_pc~0); 4427#L535-2 is_transmit7_triggered_~__retres1~7#1 := 0; 4497#L546 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 4498#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 4529#L1091 assume !(0 != activate_threads_~tmp___6~0#1); 4519#L1091-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 4520#L554 assume 1 == ~t8_pc~0; 4462#L555 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 3787#L565 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 4545#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 4094#L1099 assume !(0 != activate_threads_~tmp___7~0#1); 4095#L1099-2 havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 3773#L931 assume !(1 == ~M_E~0); 3774#L931-2 assume 1 == ~T1_E~0;~T1_E~0 := 2; 4665#L936-1 assume !(1 == ~T2_E~0); 4684#L941-1 assume !(1 == ~T3_E~0); 4263#L946-1 assume !(1 == ~T4_E~0); 4264#L951-1 assume !(1 == ~T5_E~0); 4021#L956-1 assume !(1 == ~T6_E~0); 4022#L961-1 assume !(1 == ~T7_E~0); 4409#L966-1 assume !(1 == ~T8_E~0); 4410#L971-1 assume 1 == ~E_1~0;~E_1~0 := 2; 4522#L976-1 assume !(1 == ~E_2~0); 4487#L981-1 assume !(1 == ~E_3~0); 4267#L986-1 assume !(1 == ~E_4~0); 4048#L991-1 assume !(1 == ~E_5~0); 4049#L996-1 assume !(1 == ~E_6~0); 4674#L1001-1 assume !(1 == ~E_7~0); 4457#L1006-1 assume !(1 == ~E_8~0); 4458#L1011-1 assume { :end_inline_reset_delta_events } true; 3834#L1272-2 [2023-11-06 21:58:41,100 INFO L750 eck$LassoCheckResult]: Loop: 3834#L1272-2 assume !false; 3835#L1273 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 4071#L813-1 assume !false; 4607#L692 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 4608#L634 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 3837#L681 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 4176#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 4177#L696 assume !(0 != eval_~tmp~0#1); 4550#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 4317#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 4318#L838-3 assume 0 == ~M_E~0;~M_E~0 := 1; 4506#L838-5 assume !(0 == ~T1_E~0); 4507#L843-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 4360#L848-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 4361#L853-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 4411#L858-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 4476#L863-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 4466#L868-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 4467#L873-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 4075#L878-3 assume !(0 == ~E_1~0); 3798#L883-3 assume 0 == ~E_2~0;~E_2~0 := 1; 3799#L888-3 assume 0 == ~E_3~0;~E_3~0 := 1; 3800#L893-3 assume 0 == ~E_4~0;~E_4~0 := 1; 3801#L898-3 assume 0 == ~E_5~0;~E_5~0 := 1; 4293#L903-3 assume 0 == ~E_6~0;~E_6~0 := 1; 4609#L908-3 assume 0 == ~E_7~0;~E_7~0 := 1; 4301#L913-3 assume 0 == ~E_8~0;~E_8~0 := 1; 3839#L918-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 3840#L402-27 assume 1 == ~m_pc~0; 3788#L403-9 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 3789#L413-9 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 4499#is_master_triggered_returnLabel#10 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 4500#L1035-27 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 4626#L1035-29 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 4627#L421-27 assume !(1 == ~t1_pc~0); 4065#L421-29 is_transmit1_triggered_~__retres1~1#1 := 0; 4066#L432-9 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 4385#is_transmit1_triggered_returnLabel#10 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 4386#L1043-27 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 4675#L1043-29 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 4429#L440-27 assume !(1 == ~t2_pc~0); 4430#L440-29 is_transmit2_triggered_~__retres1~2#1 := 0; 4604#L451-9 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 4471#is_transmit2_triggered_returnLabel#10 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 4336#L1051-27 assume !(0 != activate_threads_~tmp___1~0#1); 4337#L1051-29 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 4051#L459-27 assume 1 == ~t3_pc~0; 4052#L460-9 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 4492#L470-9 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 4313#is_transmit3_triggered_returnLabel#10 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 4314#L1059-27 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 4425#L1059-29 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 4668#L478-27 assume !(1 == ~t4_pc~0); 4040#L478-29 is_transmit4_triggered_~__retres1~4#1 := 0; 4041#L489-9 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 4224#is_transmit4_triggered_returnLabel#10 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 4225#L1067-27 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 4574#L1067-29 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 4610#L497-27 assume 1 == ~t5_pc~0; 4611#L498-9 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 4084#L508-9 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 4085#is_transmit5_triggered_returnLabel#10 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 4027#L1075-27 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 4028#L1075-29 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 4295#L516-27 assume !(1 == ~t6_pc~0); 4296#L516-29 is_transmit6_triggered_~__retres1~6#1 := 0; 4148#L527-9 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 4149#is_transmit6_triggered_returnLabel#10 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 4448#L1083-27 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 4449#L1083-29 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 4228#L535-27 assume 1 == ~t7_pc~0; 4229#L536-9 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 4558#L546-9 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 4108#is_transmit7_triggered_returnLabel#10 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 4109#L1091-27 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 4179#L1091-29 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 4180#L554-27 assume !(1 == ~t8_pc~0); 3813#L554-29 is_transmit8_triggered_~__retres1~8#1 := 0; 3814#L565-9 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 3965#is_transmit8_triggered_returnLabel#10 activate_threads_#t~ret22#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 4345#L1099-27 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 4072#L1099-29 havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 4073#L931-3 assume 1 == ~M_E~0;~M_E~0 := 2; 3947#L931-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 3948#L936-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 4178#L941-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 4312#L946-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 4088#L951-3 assume !(1 == ~T5_E~0); 4089#L956-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 4383#L961-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 4188#L966-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 4189#L971-3 assume 1 == ~E_1~0;~E_1~0 := 2; 4436#L976-3 assume 1 == ~E_2~0;~E_2~0 := 2; 3832#L981-3 assume 1 == ~E_3~0;~E_3~0 := 2; 3833#L986-3 assume 1 == ~E_4~0;~E_4~0 := 2; 3821#L991-3 assume !(1 == ~E_5~0); 3822#L996-3 assume 1 == ~E_6~0;~E_6~0 := 2; 4512#L1001-3 assume 1 == ~E_7~0;~E_7~0 := 2; 4165#L1006-3 assume 1 == ~E_8~0;~E_8~0 := 2; 4166#L1011-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 3860#L634-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 3861#L681-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 4114#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret24#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret24#1;havoc start_simulation_#t~ret24#1; 4115#L1291 assume !(0 == start_simulation_~tmp~3#1); 4380#L1291-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 4283#L634-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 3766#L681-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 3767#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret23#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret23#1;havoc stop_simulation_#t~ret23#1; 3825#L1246 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 4249#L1253 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 4250#stop_simulation_returnLabel#1 start_simulation_#t~ret25#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret25#1;havoc start_simulation_#t~ret25#1; 4335#L1304 assume !(0 != start_simulation_~tmp___0~1#1); 3834#L1272-2 [2023-11-06 21:58:41,100 INFO L145 PredicateUnifier]: Initialized classic predicate unifier [2023-11-06 21:58:41,100 INFO L85 PathProgramCache]: Analyzing trace with hash -1888349538, now seen corresponding path program 1 times [2023-11-06 21:58:41,101 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-06 21:58:41,101 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [332995023] [2023-11-06 21:58:41,101 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-06 21:58:41,101 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-06 21:58:41,119 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-06 21:58:41,161 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-06 21:58:41,161 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-06 21:58:41,161 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [332995023] [2023-11-06 21:58:41,161 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [332995023] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-06 21:58:41,161 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-06 21:58:41,162 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-06 21:58:41,162 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1454264556] [2023-11-06 21:58:41,162 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-06 21:58:41,163 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-06 21:58:41,163 INFO L145 PredicateUnifier]: Initialized classic predicate unifier [2023-11-06 21:58:41,163 INFO L85 PathProgramCache]: Analyzing trace with hash 56067214, now seen corresponding path program 2 times [2023-11-06 21:58:41,163 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-06 21:58:41,164 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1055405538] [2023-11-06 21:58:41,164 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-06 21:58:41,164 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-06 21:58:41,196 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-06 21:58:41,273 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-06 21:58:41,274 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-06 21:58:41,274 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1055405538] [2023-11-06 21:58:41,274 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1055405538] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-06 21:58:41,274 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-06 21:58:41,274 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-06 21:58:41,275 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [825987030] [2023-11-06 21:58:41,275 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-06 21:58:41,275 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-06 21:58:41,276 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-06 21:58:41,276 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-06 21:58:41,276 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-06 21:58:41,277 INFO L87 Difference]: Start difference. First operand 933 states and 1387 transitions. cyclomatic complexity: 455 Second operand has 3 states, 3 states have (on average 34.666666666666664) internal successors, (104), 3 states have internal predecessors, (104), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-06 21:58:41,303 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-06 21:58:41,303 INFO L93 Difference]: Finished difference Result 933 states and 1386 transitions. [2023-11-06 21:58:41,303 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 933 states and 1386 transitions. [2023-11-06 21:58:41,312 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 820 [2023-11-06 21:58:41,320 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 933 states to 933 states and 1386 transitions. [2023-11-06 21:58:41,321 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 933 [2023-11-06 21:58:41,323 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 933 [2023-11-06 21:58:41,323 INFO L73 IsDeterministic]: Start isDeterministic. Operand 933 states and 1386 transitions. [2023-11-06 21:58:41,325 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-06 21:58:41,325 INFO L218 hiAutomatonCegarLoop]: Abstraction has 933 states and 1386 transitions. [2023-11-06 21:58:41,327 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 933 states and 1386 transitions. [2023-11-06 21:58:41,342 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 933 to 933. [2023-11-06 21:58:41,344 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 933 states, 933 states have (on average 1.4855305466237942) internal successors, (1386), 932 states have internal predecessors, (1386), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-06 21:58:41,351 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 933 states to 933 states and 1386 transitions. [2023-11-06 21:58:41,356 INFO L240 hiAutomatonCegarLoop]: Abstraction has 933 states and 1386 transitions. [2023-11-06 21:58:41,356 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-06 21:58:41,358 INFO L428 stractBuchiCegarLoop]: Abstraction has 933 states and 1386 transitions. [2023-11-06 21:58:41,360 INFO L335 stractBuchiCegarLoop]: ======== Iteration 4 ============ [2023-11-06 21:58:41,360 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 933 states and 1386 transitions. [2023-11-06 21:58:41,367 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 820 [2023-11-06 21:58:41,368 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-06 21:58:41,368 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-06 21:58:41,371 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-06 21:58:41,371 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-06 21:58:41,374 INFO L748 eck$LassoCheckResult]: Stem: 5885#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2; 5886#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~10#1;havoc main_~__retres1~10#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; 6512#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret24#1, start_simulation_#t~ret25#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 6513#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 6514#L581 assume 1 == ~m_i~0;~m_st~0 := 0; 6004#L581-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 6005#L586-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 6510#L591-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 6506#L596-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 6076#L601-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 6077#L606-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 6311#L611-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 6312#L616-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 6160#L621-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 6161#L838 assume !(0 == ~M_E~0); 6319#L838-2 assume !(0 == ~T1_E~0); 5684#L843-1 assume !(0 == ~T2_E~0); 5685#L848-1 assume !(0 == ~T3_E~0); 5805#L853-1 assume !(0 == ~T4_E~0); 6147#L858-1 assume 0 == ~T5_E~0;~T5_E~0 := 1; 5635#L863-1 assume !(0 == ~T6_E~0); 5636#L868-1 assume !(0 == ~T7_E~0); 6542#L873-1 assume !(0 == ~T8_E~0); 6540#L878-1 assume !(0 == ~E_1~0); 6531#L883-1 assume !(0 == ~E_2~0); 6532#L888-1 assume !(0 == ~E_3~0); 6280#L893-1 assume !(0 == ~E_4~0); 6281#L898-1 assume 0 == ~E_5~0;~E_5~0 := 1; 6552#L903-1 assume !(0 == ~E_6~0); 6529#L908-1 assume !(0 == ~E_7~0); 6410#L913-1 assume !(0 == ~E_8~0); 5696#L918-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 5697#L402 assume !(1 == ~m_pc~0); 5908#L402-2 is_master_triggered_~__retres1~0#1 := 0; 5829#L413 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 5830#is_master_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 6082#L1035 assume !(0 != activate_threads_~tmp~1#1); 6083#L1035-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 6135#L421 assume 1 == ~t1_pc~0; 6525#L422 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 6543#L432 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 5699#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 5700#L1043 assume !(0 != activate_threads_~tmp___0~0#1); 6189#L1043-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 6550#L440 assume 1 == ~t2_pc~0; 5668#L441 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 5669#L451 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 5839#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 6030#L1051 assume !(0 != activate_threads_~tmp___1~0#1); 6425#L1051-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 6033#L459 assume !(1 == ~t3_pc~0); 6034#L459-2 is_transmit3_triggered_~__retres1~3#1 := 0; 6523#L470 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 5657#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 5658#L1059 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 5824#L1059-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 5833#L478 assume 1 == ~t4_pc~0; 5834#L479 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 6285#L489 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 5777#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 5778#L1067 assume !(0 != activate_threads_~tmp___3~0#1); 5738#L1067-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 5739#L497 assume !(1 == ~t5_pc~0); 5788#L497-2 is_transmit5_triggered_~__retres1~5#1 := 0; 5789#L508 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 6356#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 6462#L1075 assume !(0 != activate_threads_~tmp___4~0#1); 6519#L1075-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 6520#L516 assume 1 == ~t6_pc~0; 6566#L517 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 6310#L527 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 6013#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 5879#L1083 assume !(0 != activate_threads_~tmp___5~0#1); 5880#L1083-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 6299#L535 assume !(1 == ~t7_pc~0); 6300#L535-2 is_transmit7_triggered_~__retres1~7#1 := 0; 6370#L546 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 6371#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 6402#L1091 assume !(0 != activate_threads_~tmp___6~0#1); 6392#L1091-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 6393#L554 assume 1 == ~t8_pc~0; 6335#L555 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 5660#L565 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 6418#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 5967#L1099 assume !(0 != activate_threads_~tmp___7~0#1); 5968#L1099-2 havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 5646#L931 assume !(1 == ~M_E~0); 5647#L931-2 assume 1 == ~T1_E~0;~T1_E~0 := 2; 6538#L936-1 assume !(1 == ~T2_E~0); 6557#L941-1 assume !(1 == ~T3_E~0); 6136#L946-1 assume !(1 == ~T4_E~0); 6137#L951-1 assume !(1 == ~T5_E~0); 5894#L956-1 assume !(1 == ~T6_E~0); 5895#L961-1 assume !(1 == ~T7_E~0); 6282#L966-1 assume !(1 == ~T8_E~0); 6283#L971-1 assume 1 == ~E_1~0;~E_1~0 := 2; 6395#L976-1 assume !(1 == ~E_2~0); 6360#L981-1 assume !(1 == ~E_3~0); 6140#L986-1 assume !(1 == ~E_4~0); 5921#L991-1 assume !(1 == ~E_5~0); 5922#L996-1 assume !(1 == ~E_6~0); 6547#L1001-1 assume !(1 == ~E_7~0); 6330#L1006-1 assume !(1 == ~E_8~0); 6331#L1011-1 assume { :end_inline_reset_delta_events } true; 5707#L1272-2 [2023-11-06 21:58:41,375 INFO L750 eck$LassoCheckResult]: Loop: 5707#L1272-2 assume !false; 5708#L1273 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 5944#L813-1 assume !false; 6480#L692 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 6481#L634 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 5710#L681 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 6049#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 6050#L696 assume !(0 != eval_~tmp~0#1); 6423#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 6190#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 6191#L838-3 assume 0 == ~M_E~0;~M_E~0 := 1; 6379#L838-5 assume !(0 == ~T1_E~0); 6380#L843-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 6233#L848-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 6234#L853-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 6284#L858-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 6349#L863-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 6339#L868-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 6340#L873-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 5948#L878-3 assume !(0 == ~E_1~0); 5671#L883-3 assume 0 == ~E_2~0;~E_2~0 := 1; 5672#L888-3 assume 0 == ~E_3~0;~E_3~0 := 1; 5673#L893-3 assume 0 == ~E_4~0;~E_4~0 := 1; 5674#L898-3 assume 0 == ~E_5~0;~E_5~0 := 1; 6166#L903-3 assume 0 == ~E_6~0;~E_6~0 := 1; 6482#L908-3 assume 0 == ~E_7~0;~E_7~0 := 1; 6174#L913-3 assume 0 == ~E_8~0;~E_8~0 := 1; 5712#L918-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 5713#L402-27 assume 1 == ~m_pc~0; 5661#L403-9 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 5662#L413-9 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 6372#is_master_triggered_returnLabel#10 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 6373#L1035-27 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 6499#L1035-29 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 6500#L421-27 assume !(1 == ~t1_pc~0); 5938#L421-29 is_transmit1_triggered_~__retres1~1#1 := 0; 5939#L432-9 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 6258#is_transmit1_triggered_returnLabel#10 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 6259#L1043-27 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 6548#L1043-29 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 6302#L440-27 assume 1 == ~t2_pc~0; 6304#L441-9 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 6477#L451-9 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 6344#is_transmit2_triggered_returnLabel#10 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 6209#L1051-27 assume !(0 != activate_threads_~tmp___1~0#1); 6210#L1051-29 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 5924#L459-27 assume 1 == ~t3_pc~0; 5925#L460-9 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 6365#L470-9 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 6186#is_transmit3_triggered_returnLabel#10 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 6187#L1059-27 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 6298#L1059-29 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 6541#L478-27 assume 1 == ~t4_pc~0; 6560#L479-9 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 5914#L489-9 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 6097#is_transmit4_triggered_returnLabel#10 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 6098#L1067-27 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 6447#L1067-29 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 6483#L497-27 assume 1 == ~t5_pc~0; 6484#L498-9 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 5957#L508-9 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 5958#is_transmit5_triggered_returnLabel#10 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 5900#L1075-27 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 5901#L1075-29 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 6168#L516-27 assume !(1 == ~t6_pc~0); 6169#L516-29 is_transmit6_triggered_~__retres1~6#1 := 0; 6021#L527-9 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 6022#is_transmit6_triggered_returnLabel#10 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 6321#L1083-27 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 6322#L1083-29 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 6101#L535-27 assume 1 == ~t7_pc~0; 6102#L536-9 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 6431#L546-9 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 5981#is_transmit7_triggered_returnLabel#10 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 5982#L1091-27 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 6052#L1091-29 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 6053#L554-27 assume !(1 == ~t8_pc~0); 5686#L554-29 is_transmit8_triggered_~__retres1~8#1 := 0; 5687#L565-9 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 5838#is_transmit8_triggered_returnLabel#10 activate_threads_#t~ret22#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 6218#L1099-27 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 5945#L1099-29 havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 5946#L931-3 assume 1 == ~M_E~0;~M_E~0 := 2; 5820#L931-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 5821#L936-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 6051#L941-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 6185#L946-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 5961#L951-3 assume !(1 == ~T5_E~0); 5962#L956-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 6256#L961-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 6061#L966-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 6062#L971-3 assume 1 == ~E_1~0;~E_1~0 := 2; 6309#L976-3 assume 1 == ~E_2~0;~E_2~0 := 2; 5705#L981-3 assume 1 == ~E_3~0;~E_3~0 := 2; 5706#L986-3 assume 1 == ~E_4~0;~E_4~0 := 2; 5694#L991-3 assume !(1 == ~E_5~0); 5695#L996-3 assume 1 == ~E_6~0;~E_6~0 := 2; 6385#L1001-3 assume 1 == ~E_7~0;~E_7~0 := 2; 6038#L1006-3 assume 1 == ~E_8~0;~E_8~0 := 2; 6039#L1011-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 5733#L634-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 5734#L681-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 5987#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret24#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret24#1;havoc start_simulation_#t~ret24#1; 5988#L1291 assume !(0 == start_simulation_~tmp~3#1); 6253#L1291-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 6156#L634-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 5639#L681-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 5640#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret23#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret23#1;havoc stop_simulation_#t~ret23#1; 5698#L1246 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 6122#L1253 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 6123#stop_simulation_returnLabel#1 start_simulation_#t~ret25#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret25#1;havoc start_simulation_#t~ret25#1; 6208#L1304 assume !(0 != start_simulation_~tmp___0~1#1); 5707#L1272-2 [2023-11-06 21:58:41,376 INFO L145 PredicateUnifier]: Initialized classic predicate unifier [2023-11-06 21:58:41,376 INFO L85 PathProgramCache]: Analyzing trace with hash 805546652, now seen corresponding path program 1 times [2023-11-06 21:58:41,376 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-06 21:58:41,376 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [345238029] [2023-11-06 21:58:41,377 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-06 21:58:41,377 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-06 21:58:41,415 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-06 21:58:41,452 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-06 21:58:41,453 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-06 21:58:41,453 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [345238029] [2023-11-06 21:58:41,453 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [345238029] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-06 21:58:41,454 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-06 21:58:41,454 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-06 21:58:41,454 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [138254686] [2023-11-06 21:58:41,454 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-06 21:58:41,455 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-06 21:58:41,455 INFO L145 PredicateUnifier]: Initialized classic predicate unifier [2023-11-06 21:58:41,455 INFO L85 PathProgramCache]: Analyzing trace with hash -1847000368, now seen corresponding path program 1 times [2023-11-06 21:58:41,456 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-06 21:58:41,456 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1205107330] [2023-11-06 21:58:41,456 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-06 21:58:41,456 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-06 21:58:41,477 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-06 21:58:41,576 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-06 21:58:41,577 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-06 21:58:41,577 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1205107330] [2023-11-06 21:58:41,577 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1205107330] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-06 21:58:41,577 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-06 21:58:41,578 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-06 21:58:41,578 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1054239571] [2023-11-06 21:58:41,578 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-06 21:58:41,579 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-06 21:58:41,579 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-06 21:58:41,579 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-06 21:58:41,580 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-06 21:58:41,580 INFO L87 Difference]: Start difference. First operand 933 states and 1386 transitions. cyclomatic complexity: 454 Second operand has 3 states, 3 states have (on average 34.666666666666664) internal successors, (104), 3 states have internal predecessors, (104), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-06 21:58:41,611 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-06 21:58:41,611 INFO L93 Difference]: Finished difference Result 933 states and 1385 transitions. [2023-11-06 21:58:41,611 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 933 states and 1385 transitions. [2023-11-06 21:58:41,621 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 820 [2023-11-06 21:58:41,629 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 933 states to 933 states and 1385 transitions. [2023-11-06 21:58:41,630 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 933 [2023-11-06 21:58:41,631 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 933 [2023-11-06 21:58:41,631 INFO L73 IsDeterministic]: Start isDeterministic. Operand 933 states and 1385 transitions. [2023-11-06 21:58:41,633 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-06 21:58:41,633 INFO L218 hiAutomatonCegarLoop]: Abstraction has 933 states and 1385 transitions. [2023-11-06 21:58:41,635 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 933 states and 1385 transitions. [2023-11-06 21:58:41,652 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 933 to 933. [2023-11-06 21:58:41,654 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 933 states, 933 states have (on average 1.4844587352625938) internal successors, (1385), 932 states have internal predecessors, (1385), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-06 21:58:41,659 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 933 states to 933 states and 1385 transitions. [2023-11-06 21:58:41,660 INFO L240 hiAutomatonCegarLoop]: Abstraction has 933 states and 1385 transitions. [2023-11-06 21:58:41,660 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-06 21:58:41,663 INFO L428 stractBuchiCegarLoop]: Abstraction has 933 states and 1385 transitions. [2023-11-06 21:58:41,667 INFO L335 stractBuchiCegarLoop]: ======== Iteration 5 ============ [2023-11-06 21:58:41,667 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 933 states and 1385 transitions. [2023-11-06 21:58:41,674 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 820 [2023-11-06 21:58:41,675 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-06 21:58:41,675 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-06 21:58:41,677 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-06 21:58:41,677 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-06 21:58:41,678 INFO L748 eck$LassoCheckResult]: Stem: 7758#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2; 7759#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~10#1;havoc main_~__retres1~10#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; 8385#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret24#1, start_simulation_#t~ret25#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 8386#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 8387#L581 assume 1 == ~m_i~0;~m_st~0 := 0; 7877#L581-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 7878#L586-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 8383#L591-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 8379#L596-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 7949#L601-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 7950#L606-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 8184#L611-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 8185#L616-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 8033#L621-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 8034#L838 assume !(0 == ~M_E~0); 8192#L838-2 assume !(0 == ~T1_E~0); 7557#L843-1 assume !(0 == ~T2_E~0); 7558#L848-1 assume !(0 == ~T3_E~0); 7678#L853-1 assume !(0 == ~T4_E~0); 8020#L858-1 assume 0 == ~T5_E~0;~T5_E~0 := 1; 7508#L863-1 assume !(0 == ~T6_E~0); 7509#L868-1 assume !(0 == ~T7_E~0); 8415#L873-1 assume !(0 == ~T8_E~0); 8413#L878-1 assume !(0 == ~E_1~0); 8404#L883-1 assume !(0 == ~E_2~0); 8405#L888-1 assume !(0 == ~E_3~0); 8153#L893-1 assume !(0 == ~E_4~0); 8154#L898-1 assume 0 == ~E_5~0;~E_5~0 := 1; 8425#L903-1 assume !(0 == ~E_6~0); 8402#L908-1 assume !(0 == ~E_7~0); 8283#L913-1 assume !(0 == ~E_8~0); 7569#L918-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 7570#L402 assume !(1 == ~m_pc~0); 7781#L402-2 is_master_triggered_~__retres1~0#1 := 0; 7702#L413 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 7703#is_master_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 7955#L1035 assume !(0 != activate_threads_~tmp~1#1); 7956#L1035-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 8008#L421 assume 1 == ~t1_pc~0; 8398#L422 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 8416#L432 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 7572#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 7573#L1043 assume !(0 != activate_threads_~tmp___0~0#1); 8062#L1043-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 8423#L440 assume 1 == ~t2_pc~0; 7541#L441 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 7542#L451 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 7712#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 7903#L1051 assume !(0 != activate_threads_~tmp___1~0#1); 8298#L1051-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 7906#L459 assume !(1 == ~t3_pc~0); 7907#L459-2 is_transmit3_triggered_~__retres1~3#1 := 0; 8396#L470 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 7530#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 7531#L1059 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 7697#L1059-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 7706#L478 assume 1 == ~t4_pc~0; 7707#L479 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 8158#L489 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 7650#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 7651#L1067 assume !(0 != activate_threads_~tmp___3~0#1); 7611#L1067-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 7612#L497 assume !(1 == ~t5_pc~0); 7661#L497-2 is_transmit5_triggered_~__retres1~5#1 := 0; 7662#L508 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 8229#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 8335#L1075 assume !(0 != activate_threads_~tmp___4~0#1); 8392#L1075-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 8393#L516 assume 1 == ~t6_pc~0; 8439#L517 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 8183#L527 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 7886#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 7752#L1083 assume !(0 != activate_threads_~tmp___5~0#1); 7753#L1083-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 8172#L535 assume !(1 == ~t7_pc~0); 8173#L535-2 is_transmit7_triggered_~__retres1~7#1 := 0; 8243#L546 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 8244#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 8275#L1091 assume !(0 != activate_threads_~tmp___6~0#1); 8265#L1091-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 8266#L554 assume 1 == ~t8_pc~0; 8208#L555 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 7533#L565 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 8291#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 7840#L1099 assume !(0 != activate_threads_~tmp___7~0#1); 7841#L1099-2 havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 7519#L931 assume !(1 == ~M_E~0); 7520#L931-2 assume 1 == ~T1_E~0;~T1_E~0 := 2; 8411#L936-1 assume !(1 == ~T2_E~0); 8430#L941-1 assume !(1 == ~T3_E~0); 8009#L946-1 assume !(1 == ~T4_E~0); 8010#L951-1 assume !(1 == ~T5_E~0); 7767#L956-1 assume !(1 == ~T6_E~0); 7768#L961-1 assume !(1 == ~T7_E~0); 8155#L966-1 assume !(1 == ~T8_E~0); 8156#L971-1 assume 1 == ~E_1~0;~E_1~0 := 2; 8268#L976-1 assume !(1 == ~E_2~0); 8233#L981-1 assume !(1 == ~E_3~0); 8013#L986-1 assume !(1 == ~E_4~0); 7794#L991-1 assume !(1 == ~E_5~0); 7795#L996-1 assume !(1 == ~E_6~0); 8420#L1001-1 assume !(1 == ~E_7~0); 8203#L1006-1 assume !(1 == ~E_8~0); 8204#L1011-1 assume { :end_inline_reset_delta_events } true; 7580#L1272-2 [2023-11-06 21:58:41,679 INFO L750 eck$LassoCheckResult]: Loop: 7580#L1272-2 assume !false; 7581#L1273 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 7817#L813-1 assume !false; 8353#L692 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 8354#L634 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 7583#L681 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 7922#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 7923#L696 assume !(0 != eval_~tmp~0#1); 8296#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 8063#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 8064#L838-3 assume 0 == ~M_E~0;~M_E~0 := 1; 8252#L838-5 assume !(0 == ~T1_E~0); 8253#L843-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 8106#L848-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 8107#L853-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 8157#L858-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 8222#L863-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 8212#L868-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 8213#L873-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 7821#L878-3 assume !(0 == ~E_1~0); 7544#L883-3 assume 0 == ~E_2~0;~E_2~0 := 1; 7545#L888-3 assume 0 == ~E_3~0;~E_3~0 := 1; 7546#L893-3 assume 0 == ~E_4~0;~E_4~0 := 1; 7547#L898-3 assume 0 == ~E_5~0;~E_5~0 := 1; 8039#L903-3 assume 0 == ~E_6~0;~E_6~0 := 1; 8355#L908-3 assume 0 == ~E_7~0;~E_7~0 := 1; 8047#L913-3 assume 0 == ~E_8~0;~E_8~0 := 1; 7585#L918-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 7586#L402-27 assume !(1 == ~m_pc~0); 7536#L402-29 is_master_triggered_~__retres1~0#1 := 0; 7535#L413-9 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 8245#is_master_triggered_returnLabel#10 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 8246#L1035-27 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 8372#L1035-29 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 8373#L421-27 assume !(1 == ~t1_pc~0); 7811#L421-29 is_transmit1_triggered_~__retres1~1#1 := 0; 7812#L432-9 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 8131#is_transmit1_triggered_returnLabel#10 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 8132#L1043-27 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 8421#L1043-29 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 8175#L440-27 assume !(1 == ~t2_pc~0); 8176#L440-29 is_transmit2_triggered_~__retres1~2#1 := 0; 8350#L451-9 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 8217#is_transmit2_triggered_returnLabel#10 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 8082#L1051-27 assume !(0 != activate_threads_~tmp___1~0#1); 8083#L1051-29 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 7797#L459-27 assume 1 == ~t3_pc~0; 7798#L460-9 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 8238#L470-9 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 8059#is_transmit3_triggered_returnLabel#10 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 8060#L1059-27 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 8171#L1059-29 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 8414#L478-27 assume 1 == ~t4_pc~0; 8433#L479-9 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 7787#L489-9 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 7970#is_transmit4_triggered_returnLabel#10 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 7971#L1067-27 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 8320#L1067-29 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 8356#L497-27 assume 1 == ~t5_pc~0; 8357#L498-9 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 7830#L508-9 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 7831#is_transmit5_triggered_returnLabel#10 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 7773#L1075-27 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 7774#L1075-29 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 8041#L516-27 assume !(1 == ~t6_pc~0); 8042#L516-29 is_transmit6_triggered_~__retres1~6#1 := 0; 7894#L527-9 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 7895#is_transmit6_triggered_returnLabel#10 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 8194#L1083-27 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 8195#L1083-29 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 7974#L535-27 assume 1 == ~t7_pc~0; 7975#L536-9 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 8304#L546-9 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 7854#is_transmit7_triggered_returnLabel#10 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 7855#L1091-27 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 7925#L1091-29 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 7926#L554-27 assume 1 == ~t8_pc~0; 8128#L555-9 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 7560#L565-9 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 7711#is_transmit8_triggered_returnLabel#10 activate_threads_#t~ret22#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 8091#L1099-27 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 7818#L1099-29 havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 7819#L931-3 assume 1 == ~M_E~0;~M_E~0 := 2; 7693#L931-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 7694#L936-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 7924#L941-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 8058#L946-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 7834#L951-3 assume !(1 == ~T5_E~0); 7835#L956-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 8129#L961-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 7934#L966-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 7935#L971-3 assume 1 == ~E_1~0;~E_1~0 := 2; 8182#L976-3 assume 1 == ~E_2~0;~E_2~0 := 2; 7578#L981-3 assume 1 == ~E_3~0;~E_3~0 := 2; 7579#L986-3 assume 1 == ~E_4~0;~E_4~0 := 2; 7567#L991-3 assume !(1 == ~E_5~0); 7568#L996-3 assume 1 == ~E_6~0;~E_6~0 := 2; 8258#L1001-3 assume 1 == ~E_7~0;~E_7~0 := 2; 7911#L1006-3 assume 1 == ~E_8~0;~E_8~0 := 2; 7912#L1011-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 7606#L634-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 7607#L681-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 7860#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret24#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret24#1;havoc start_simulation_#t~ret24#1; 7861#L1291 assume !(0 == start_simulation_~tmp~3#1); 8126#L1291-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 8029#L634-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 7512#L681-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 7513#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret23#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret23#1;havoc stop_simulation_#t~ret23#1; 7571#L1246 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 7995#L1253 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 7996#stop_simulation_returnLabel#1 start_simulation_#t~ret25#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret25#1;havoc start_simulation_#t~ret25#1; 8081#L1304 assume !(0 != start_simulation_~tmp___0~1#1); 7580#L1272-2 [2023-11-06 21:58:41,680 INFO L145 PredicateUnifier]: Initialized classic predicate unifier [2023-11-06 21:58:41,685 INFO L85 PathProgramCache]: Analyzing trace with hash 1862277854, now seen corresponding path program 1 times [2023-11-06 21:58:41,685 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-06 21:58:41,686 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1636450241] [2023-11-06 21:58:41,686 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-06 21:58:41,686 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-06 21:58:41,705 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-06 21:58:41,745 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-06 21:58:41,746 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-06 21:58:41,746 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1636450241] [2023-11-06 21:58:41,746 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1636450241] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-06 21:58:41,746 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-06 21:58:41,747 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-06 21:58:41,747 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2053608993] [2023-11-06 21:58:41,747 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-06 21:58:41,748 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-06 21:58:41,748 INFO L145 PredicateUnifier]: Initialized classic predicate unifier [2023-11-06 21:58:41,749 INFO L85 PathProgramCache]: Analyzing trace with hash -1022505361, now seen corresponding path program 1 times [2023-11-06 21:58:41,749 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-06 21:58:41,749 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1881987939] [2023-11-06 21:58:41,749 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-06 21:58:41,750 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-06 21:58:41,773 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-06 21:58:41,830 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-06 21:58:41,830 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-06 21:58:41,831 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1881987939] [2023-11-06 21:58:41,831 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1881987939] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-06 21:58:41,831 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-06 21:58:41,831 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-06 21:58:41,832 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1421849419] [2023-11-06 21:58:41,832 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-06 21:58:41,832 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-06 21:58:41,833 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-06 21:58:41,833 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-06 21:58:41,833 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-06 21:58:41,834 INFO L87 Difference]: Start difference. First operand 933 states and 1385 transitions. cyclomatic complexity: 453 Second operand has 3 states, 3 states have (on average 34.666666666666664) internal successors, (104), 3 states have internal predecessors, (104), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-06 21:58:41,860 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-06 21:58:41,861 INFO L93 Difference]: Finished difference Result 933 states and 1384 transitions. [2023-11-06 21:58:41,862 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 933 states and 1384 transitions. [2023-11-06 21:58:41,870 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 820 [2023-11-06 21:58:41,878 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 933 states to 933 states and 1384 transitions. [2023-11-06 21:58:41,878 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 933 [2023-11-06 21:58:41,880 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 933 [2023-11-06 21:58:41,880 INFO L73 IsDeterministic]: Start isDeterministic. Operand 933 states and 1384 transitions. [2023-11-06 21:58:41,881 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-06 21:58:41,882 INFO L218 hiAutomatonCegarLoop]: Abstraction has 933 states and 1384 transitions. [2023-11-06 21:58:41,883 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 933 states and 1384 transitions. [2023-11-06 21:58:41,897 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 933 to 933. [2023-11-06 21:58:41,899 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 933 states, 933 states have (on average 1.4833869239013933) internal successors, (1384), 932 states have internal predecessors, (1384), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-06 21:58:41,903 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 933 states to 933 states and 1384 transitions. [2023-11-06 21:58:41,904 INFO L240 hiAutomatonCegarLoop]: Abstraction has 933 states and 1384 transitions. [2023-11-06 21:58:41,904 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-06 21:58:41,907 INFO L428 stractBuchiCegarLoop]: Abstraction has 933 states and 1384 transitions. [2023-11-06 21:58:41,907 INFO L335 stractBuchiCegarLoop]: ======== Iteration 6 ============ [2023-11-06 21:58:41,907 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 933 states and 1384 transitions. [2023-11-06 21:58:41,920 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 820 [2023-11-06 21:58:41,920 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-06 21:58:41,920 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-06 21:58:41,922 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-06 21:58:41,922 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-06 21:58:41,923 INFO L748 eck$LassoCheckResult]: Stem: 9631#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2; 9632#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~10#1;havoc main_~__retres1~10#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; 10258#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret24#1, start_simulation_#t~ret25#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 10259#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 10260#L581 assume 1 == ~m_i~0;~m_st~0 := 0; 9750#L581-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 9751#L586-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 10256#L591-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 10252#L596-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 9822#L601-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 9823#L606-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 10057#L611-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 10058#L616-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 9906#L621-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 9907#L838 assume !(0 == ~M_E~0); 10065#L838-2 assume !(0 == ~T1_E~0); 9430#L843-1 assume !(0 == ~T2_E~0); 9431#L848-1 assume !(0 == ~T3_E~0); 9551#L853-1 assume !(0 == ~T4_E~0); 9893#L858-1 assume 0 == ~T5_E~0;~T5_E~0 := 1; 9381#L863-1 assume !(0 == ~T6_E~0); 9382#L868-1 assume !(0 == ~T7_E~0); 10288#L873-1 assume !(0 == ~T8_E~0); 10286#L878-1 assume !(0 == ~E_1~0); 10277#L883-1 assume !(0 == ~E_2~0); 10278#L888-1 assume !(0 == ~E_3~0); 10026#L893-1 assume !(0 == ~E_4~0); 10027#L898-1 assume 0 == ~E_5~0;~E_5~0 := 1; 10298#L903-1 assume !(0 == ~E_6~0); 10275#L908-1 assume !(0 == ~E_7~0); 10156#L913-1 assume !(0 == ~E_8~0); 9442#L918-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 9443#L402 assume !(1 == ~m_pc~0); 9654#L402-2 is_master_triggered_~__retres1~0#1 := 0; 9575#L413 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 9576#is_master_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 9828#L1035 assume !(0 != activate_threads_~tmp~1#1); 9829#L1035-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 9881#L421 assume 1 == ~t1_pc~0; 10271#L422 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 10289#L432 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 9445#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 9446#L1043 assume !(0 != activate_threads_~tmp___0~0#1); 9935#L1043-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 10296#L440 assume 1 == ~t2_pc~0; 9414#L441 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 9415#L451 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 9585#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 9776#L1051 assume !(0 != activate_threads_~tmp___1~0#1); 10171#L1051-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 9779#L459 assume !(1 == ~t3_pc~0); 9780#L459-2 is_transmit3_triggered_~__retres1~3#1 := 0; 10269#L470 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 9403#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 9404#L1059 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 9570#L1059-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 9579#L478 assume 1 == ~t4_pc~0; 9580#L479 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 10031#L489 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 9523#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 9524#L1067 assume !(0 != activate_threads_~tmp___3~0#1); 9484#L1067-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 9485#L497 assume !(1 == ~t5_pc~0); 9534#L497-2 is_transmit5_triggered_~__retres1~5#1 := 0; 9535#L508 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 10102#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 10208#L1075 assume !(0 != activate_threads_~tmp___4~0#1); 10265#L1075-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 10266#L516 assume 1 == ~t6_pc~0; 10312#L517 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 10056#L527 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 9759#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 9625#L1083 assume !(0 != activate_threads_~tmp___5~0#1); 9626#L1083-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 10045#L535 assume !(1 == ~t7_pc~0); 10046#L535-2 is_transmit7_triggered_~__retres1~7#1 := 0; 10116#L546 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 10117#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 10148#L1091 assume !(0 != activate_threads_~tmp___6~0#1); 10138#L1091-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 10139#L554 assume 1 == ~t8_pc~0; 10081#L555 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 9406#L565 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 10164#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 9713#L1099 assume !(0 != activate_threads_~tmp___7~0#1); 9714#L1099-2 havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 9392#L931 assume !(1 == ~M_E~0); 9393#L931-2 assume 1 == ~T1_E~0;~T1_E~0 := 2; 10284#L936-1 assume !(1 == ~T2_E~0); 10303#L941-1 assume !(1 == ~T3_E~0); 9882#L946-1 assume !(1 == ~T4_E~0); 9883#L951-1 assume !(1 == ~T5_E~0); 9640#L956-1 assume !(1 == ~T6_E~0); 9641#L961-1 assume !(1 == ~T7_E~0); 10028#L966-1 assume !(1 == ~T8_E~0); 10029#L971-1 assume 1 == ~E_1~0;~E_1~0 := 2; 10141#L976-1 assume !(1 == ~E_2~0); 10106#L981-1 assume !(1 == ~E_3~0); 9886#L986-1 assume !(1 == ~E_4~0); 9667#L991-1 assume !(1 == ~E_5~0); 9668#L996-1 assume !(1 == ~E_6~0); 10293#L1001-1 assume !(1 == ~E_7~0); 10076#L1006-1 assume !(1 == ~E_8~0); 10077#L1011-1 assume { :end_inline_reset_delta_events } true; 9453#L1272-2 [2023-11-06 21:58:41,923 INFO L750 eck$LassoCheckResult]: Loop: 9453#L1272-2 assume !false; 9454#L1273 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 9690#L813-1 assume !false; 10226#L692 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 10227#L634 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 9456#L681 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 9795#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 9796#L696 assume !(0 != eval_~tmp~0#1); 10169#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 9936#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 9937#L838-3 assume 0 == ~M_E~0;~M_E~0 := 1; 10125#L838-5 assume !(0 == ~T1_E~0); 10126#L843-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 9979#L848-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 9980#L853-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 10030#L858-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 10095#L863-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 10085#L868-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 10086#L873-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 9694#L878-3 assume !(0 == ~E_1~0); 9417#L883-3 assume 0 == ~E_2~0;~E_2~0 := 1; 9418#L888-3 assume 0 == ~E_3~0;~E_3~0 := 1; 9419#L893-3 assume 0 == ~E_4~0;~E_4~0 := 1; 9420#L898-3 assume 0 == ~E_5~0;~E_5~0 := 1; 9912#L903-3 assume 0 == ~E_6~0;~E_6~0 := 1; 10228#L908-3 assume 0 == ~E_7~0;~E_7~0 := 1; 9920#L913-3 assume 0 == ~E_8~0;~E_8~0 := 1; 9458#L918-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 9459#L402-27 assume !(1 == ~m_pc~0); 9409#L402-29 is_master_triggered_~__retres1~0#1 := 0; 9408#L413-9 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 10118#is_master_triggered_returnLabel#10 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 10119#L1035-27 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 10245#L1035-29 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 10246#L421-27 assume !(1 == ~t1_pc~0); 9684#L421-29 is_transmit1_triggered_~__retres1~1#1 := 0; 9685#L432-9 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 10004#is_transmit1_triggered_returnLabel#10 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 10005#L1043-27 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 10294#L1043-29 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 10048#L440-27 assume !(1 == ~t2_pc~0); 10049#L440-29 is_transmit2_triggered_~__retres1~2#1 := 0; 10223#L451-9 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 10090#is_transmit2_triggered_returnLabel#10 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 9955#L1051-27 assume !(0 != activate_threads_~tmp___1~0#1); 9956#L1051-29 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 9670#L459-27 assume 1 == ~t3_pc~0; 9671#L460-9 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 10111#L470-9 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 9932#is_transmit3_triggered_returnLabel#10 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 9933#L1059-27 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 10044#L1059-29 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 10287#L478-27 assume 1 == ~t4_pc~0; 10306#L479-9 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 9660#L489-9 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 9843#is_transmit4_triggered_returnLabel#10 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 9844#L1067-27 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 10193#L1067-29 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 10229#L497-27 assume 1 == ~t5_pc~0; 10230#L498-9 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 9703#L508-9 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 9704#is_transmit5_triggered_returnLabel#10 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 9646#L1075-27 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 9647#L1075-29 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 9914#L516-27 assume !(1 == ~t6_pc~0); 9915#L516-29 is_transmit6_triggered_~__retres1~6#1 := 0; 9767#L527-9 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 9768#is_transmit6_triggered_returnLabel#10 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 10067#L1083-27 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 10068#L1083-29 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 9847#L535-27 assume 1 == ~t7_pc~0; 9848#L536-9 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 10177#L546-9 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 9727#is_transmit7_triggered_returnLabel#10 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 9728#L1091-27 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 9798#L1091-29 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 9799#L554-27 assume 1 == ~t8_pc~0; 10001#L555-9 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 9433#L565-9 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 9584#is_transmit8_triggered_returnLabel#10 activate_threads_#t~ret22#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 9964#L1099-27 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 9691#L1099-29 havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 9692#L931-3 assume 1 == ~M_E~0;~M_E~0 := 2; 9566#L931-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 9567#L936-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 9797#L941-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 9931#L946-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 9707#L951-3 assume !(1 == ~T5_E~0); 9708#L956-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 10002#L961-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 9807#L966-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 9808#L971-3 assume 1 == ~E_1~0;~E_1~0 := 2; 10055#L976-3 assume 1 == ~E_2~0;~E_2~0 := 2; 9451#L981-3 assume 1 == ~E_3~0;~E_3~0 := 2; 9452#L986-3 assume 1 == ~E_4~0;~E_4~0 := 2; 9440#L991-3 assume !(1 == ~E_5~0); 9441#L996-3 assume 1 == ~E_6~0;~E_6~0 := 2; 10131#L1001-3 assume 1 == ~E_7~0;~E_7~0 := 2; 9784#L1006-3 assume 1 == ~E_8~0;~E_8~0 := 2; 9785#L1011-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 9479#L634-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 9480#L681-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 9733#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret24#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret24#1;havoc start_simulation_#t~ret24#1; 9734#L1291 assume !(0 == start_simulation_~tmp~3#1); 9999#L1291-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 9902#L634-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 9385#L681-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 9386#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret23#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret23#1;havoc stop_simulation_#t~ret23#1; 9444#L1246 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 9868#L1253 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 9869#stop_simulation_returnLabel#1 start_simulation_#t~ret25#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret25#1;havoc start_simulation_#t~ret25#1; 9954#L1304 assume !(0 != start_simulation_~tmp___0~1#1); 9453#L1272-2 [2023-11-06 21:58:41,925 INFO L145 PredicateUnifier]: Initialized classic predicate unifier [2023-11-06 21:58:41,925 INFO L85 PathProgramCache]: Analyzing trace with hash 510892636, now seen corresponding path program 1 times [2023-11-06 21:58:41,926 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-06 21:58:41,926 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [354131795] [2023-11-06 21:58:41,926 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-06 21:58:41,926 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-06 21:58:41,941 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-06 21:58:41,977 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-06 21:58:41,977 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-06 21:58:41,978 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [354131795] [2023-11-06 21:58:41,978 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [354131795] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-06 21:58:41,978 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-06 21:58:41,978 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-06 21:58:41,979 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [81620957] [2023-11-06 21:58:41,980 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-06 21:58:41,980 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-06 21:58:41,981 INFO L145 PredicateUnifier]: Initialized classic predicate unifier [2023-11-06 21:58:41,981 INFO L85 PathProgramCache]: Analyzing trace with hash -1022505361, now seen corresponding path program 2 times [2023-11-06 21:58:41,982 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-06 21:58:41,986 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1941403486] [2023-11-06 21:58:41,986 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-06 21:58:41,986 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-06 21:58:42,006 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-06 21:58:42,054 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-06 21:58:42,054 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-06 21:58:42,055 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1941403486] [2023-11-06 21:58:42,055 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1941403486] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-06 21:58:42,055 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-06 21:58:42,055 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-06 21:58:42,055 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [901998318] [2023-11-06 21:58:42,056 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-06 21:58:42,056 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-06 21:58:42,057 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-06 21:58:42,057 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-06 21:58:42,057 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-06 21:58:42,057 INFO L87 Difference]: Start difference. First operand 933 states and 1384 transitions. cyclomatic complexity: 452 Second operand has 3 states, 3 states have (on average 34.666666666666664) internal successors, (104), 3 states have internal predecessors, (104), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-06 21:58:42,082 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-06 21:58:42,082 INFO L93 Difference]: Finished difference Result 933 states and 1383 transitions. [2023-11-06 21:58:42,082 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 933 states and 1383 transitions. [2023-11-06 21:58:42,090 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 820 [2023-11-06 21:58:42,098 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 933 states to 933 states and 1383 transitions. [2023-11-06 21:58:42,098 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 933 [2023-11-06 21:58:42,099 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 933 [2023-11-06 21:58:42,100 INFO L73 IsDeterministic]: Start isDeterministic. Operand 933 states and 1383 transitions. [2023-11-06 21:58:42,101 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-06 21:58:42,102 INFO L218 hiAutomatonCegarLoop]: Abstraction has 933 states and 1383 transitions. [2023-11-06 21:58:42,104 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 933 states and 1383 transitions. [2023-11-06 21:58:42,117 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 933 to 933. [2023-11-06 21:58:42,119 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 933 states, 933 states have (on average 1.482315112540193) internal successors, (1383), 932 states have internal predecessors, (1383), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-06 21:58:42,123 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 933 states to 933 states and 1383 transitions. [2023-11-06 21:58:42,123 INFO L240 hiAutomatonCegarLoop]: Abstraction has 933 states and 1383 transitions. [2023-11-06 21:58:42,124 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-06 21:58:42,125 INFO L428 stractBuchiCegarLoop]: Abstraction has 933 states and 1383 transitions. [2023-11-06 21:58:42,126 INFO L335 stractBuchiCegarLoop]: ======== Iteration 7 ============ [2023-11-06 21:58:42,126 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 933 states and 1383 transitions. [2023-11-06 21:58:42,132 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 820 [2023-11-06 21:58:42,132 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-06 21:58:42,132 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-06 21:58:42,134 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-06 21:58:42,134 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-06 21:58:42,135 INFO L748 eck$LassoCheckResult]: Stem: 11504#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2; 11505#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~10#1;havoc main_~__retres1~10#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; 12131#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret24#1, start_simulation_#t~ret25#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 12132#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 12133#L581 assume 1 == ~m_i~0;~m_st~0 := 0; 11623#L581-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 11624#L586-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 12129#L591-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 12125#L596-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 11695#L601-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 11696#L606-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 11930#L611-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 11931#L616-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 11779#L621-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 11780#L838 assume !(0 == ~M_E~0); 11938#L838-2 assume !(0 == ~T1_E~0); 11303#L843-1 assume !(0 == ~T2_E~0); 11304#L848-1 assume !(0 == ~T3_E~0); 11424#L853-1 assume !(0 == ~T4_E~0); 11766#L858-1 assume 0 == ~T5_E~0;~T5_E~0 := 1; 11254#L863-1 assume !(0 == ~T6_E~0); 11255#L868-1 assume !(0 == ~T7_E~0); 12161#L873-1 assume !(0 == ~T8_E~0); 12159#L878-1 assume !(0 == ~E_1~0); 12150#L883-1 assume !(0 == ~E_2~0); 12151#L888-1 assume !(0 == ~E_3~0); 11899#L893-1 assume !(0 == ~E_4~0); 11900#L898-1 assume 0 == ~E_5~0;~E_5~0 := 1; 12171#L903-1 assume !(0 == ~E_6~0); 12148#L908-1 assume !(0 == ~E_7~0); 12029#L913-1 assume !(0 == ~E_8~0); 11315#L918-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 11316#L402 assume !(1 == ~m_pc~0); 11527#L402-2 is_master_triggered_~__retres1~0#1 := 0; 11448#L413 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 11449#is_master_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 11701#L1035 assume !(0 != activate_threads_~tmp~1#1); 11702#L1035-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 11754#L421 assume 1 == ~t1_pc~0; 12144#L422 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 12162#L432 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 11318#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 11319#L1043 assume !(0 != activate_threads_~tmp___0~0#1); 11808#L1043-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 12169#L440 assume 1 == ~t2_pc~0; 11287#L441 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 11288#L451 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 11458#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 11649#L1051 assume !(0 != activate_threads_~tmp___1~0#1); 12044#L1051-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 11652#L459 assume !(1 == ~t3_pc~0); 11653#L459-2 is_transmit3_triggered_~__retres1~3#1 := 0; 12142#L470 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 11276#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 11277#L1059 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 11443#L1059-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 11452#L478 assume 1 == ~t4_pc~0; 11453#L479 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 11904#L489 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 11396#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 11397#L1067 assume !(0 != activate_threads_~tmp___3~0#1); 11357#L1067-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 11358#L497 assume !(1 == ~t5_pc~0); 11407#L497-2 is_transmit5_triggered_~__retres1~5#1 := 0; 11408#L508 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 11975#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 12081#L1075 assume !(0 != activate_threads_~tmp___4~0#1); 12138#L1075-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 12139#L516 assume 1 == ~t6_pc~0; 12185#L517 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 11929#L527 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 11632#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 11498#L1083 assume !(0 != activate_threads_~tmp___5~0#1); 11499#L1083-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 11918#L535 assume !(1 == ~t7_pc~0); 11919#L535-2 is_transmit7_triggered_~__retres1~7#1 := 0; 11989#L546 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 11990#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 12021#L1091 assume !(0 != activate_threads_~tmp___6~0#1); 12011#L1091-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 12012#L554 assume 1 == ~t8_pc~0; 11954#L555 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 11279#L565 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 12037#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 11586#L1099 assume !(0 != activate_threads_~tmp___7~0#1); 11587#L1099-2 havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 11265#L931 assume !(1 == ~M_E~0); 11266#L931-2 assume 1 == ~T1_E~0;~T1_E~0 := 2; 12157#L936-1 assume !(1 == ~T2_E~0); 12176#L941-1 assume !(1 == ~T3_E~0); 11755#L946-1 assume !(1 == ~T4_E~0); 11756#L951-1 assume !(1 == ~T5_E~0); 11513#L956-1 assume !(1 == ~T6_E~0); 11514#L961-1 assume !(1 == ~T7_E~0); 11901#L966-1 assume !(1 == ~T8_E~0); 11902#L971-1 assume 1 == ~E_1~0;~E_1~0 := 2; 12014#L976-1 assume !(1 == ~E_2~0); 11979#L981-1 assume !(1 == ~E_3~0); 11759#L986-1 assume !(1 == ~E_4~0); 11540#L991-1 assume !(1 == ~E_5~0); 11541#L996-1 assume !(1 == ~E_6~0); 12166#L1001-1 assume !(1 == ~E_7~0); 11949#L1006-1 assume !(1 == ~E_8~0); 11950#L1011-1 assume { :end_inline_reset_delta_events } true; 11326#L1272-2 [2023-11-06 21:58:42,136 INFO L750 eck$LassoCheckResult]: Loop: 11326#L1272-2 assume !false; 11327#L1273 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 11563#L813-1 assume !false; 12099#L692 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 12100#L634 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 11329#L681 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 11668#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 11669#L696 assume !(0 != eval_~tmp~0#1); 12042#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 11809#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 11810#L838-3 assume 0 == ~M_E~0;~M_E~0 := 1; 11998#L838-5 assume !(0 == ~T1_E~0); 11999#L843-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 11852#L848-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 11853#L853-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 11903#L858-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 11968#L863-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 11958#L868-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 11959#L873-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 11567#L878-3 assume !(0 == ~E_1~0); 11290#L883-3 assume 0 == ~E_2~0;~E_2~0 := 1; 11291#L888-3 assume 0 == ~E_3~0;~E_3~0 := 1; 11292#L893-3 assume 0 == ~E_4~0;~E_4~0 := 1; 11293#L898-3 assume 0 == ~E_5~0;~E_5~0 := 1; 11785#L903-3 assume 0 == ~E_6~0;~E_6~0 := 1; 12101#L908-3 assume 0 == ~E_7~0;~E_7~0 := 1; 11793#L913-3 assume 0 == ~E_8~0;~E_8~0 := 1; 11331#L918-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 11332#L402-27 assume 1 == ~m_pc~0; 11280#L403-9 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 11281#L413-9 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 11991#is_master_triggered_returnLabel#10 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 11992#L1035-27 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 12118#L1035-29 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 12119#L421-27 assume !(1 == ~t1_pc~0); 11557#L421-29 is_transmit1_triggered_~__retres1~1#1 := 0; 11558#L432-9 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 11877#is_transmit1_triggered_returnLabel#10 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 11878#L1043-27 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 12167#L1043-29 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 11921#L440-27 assume !(1 == ~t2_pc~0); 11922#L440-29 is_transmit2_triggered_~__retres1~2#1 := 0; 12096#L451-9 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 11963#is_transmit2_triggered_returnLabel#10 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 11828#L1051-27 assume !(0 != activate_threads_~tmp___1~0#1); 11829#L1051-29 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 11543#L459-27 assume 1 == ~t3_pc~0; 11544#L460-9 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 11984#L470-9 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 11805#is_transmit3_triggered_returnLabel#10 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 11806#L1059-27 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 11917#L1059-29 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 12160#L478-27 assume 1 == ~t4_pc~0; 12179#L479-9 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 11533#L489-9 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 11716#is_transmit4_triggered_returnLabel#10 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 11717#L1067-27 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 12066#L1067-29 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 12102#L497-27 assume 1 == ~t5_pc~0; 12103#L498-9 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 11576#L508-9 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 11577#is_transmit5_triggered_returnLabel#10 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 11519#L1075-27 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 11520#L1075-29 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 11787#L516-27 assume !(1 == ~t6_pc~0); 11788#L516-29 is_transmit6_triggered_~__retres1~6#1 := 0; 11640#L527-9 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 11641#is_transmit6_triggered_returnLabel#10 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 11940#L1083-27 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 11941#L1083-29 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 11720#L535-27 assume 1 == ~t7_pc~0; 11721#L536-9 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 12050#L546-9 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 11600#is_transmit7_triggered_returnLabel#10 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 11601#L1091-27 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 11671#L1091-29 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 11672#L554-27 assume 1 == ~t8_pc~0; 11874#L555-9 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 11306#L565-9 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 11457#is_transmit8_triggered_returnLabel#10 activate_threads_#t~ret22#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 11837#L1099-27 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 11564#L1099-29 havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 11565#L931-3 assume 1 == ~M_E~0;~M_E~0 := 2; 11439#L931-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 11440#L936-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 11670#L941-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 11804#L946-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 11580#L951-3 assume !(1 == ~T5_E~0); 11581#L956-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 11875#L961-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 11680#L966-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 11681#L971-3 assume 1 == ~E_1~0;~E_1~0 := 2; 11928#L976-3 assume 1 == ~E_2~0;~E_2~0 := 2; 11324#L981-3 assume 1 == ~E_3~0;~E_3~0 := 2; 11325#L986-3 assume 1 == ~E_4~0;~E_4~0 := 2; 11313#L991-3 assume !(1 == ~E_5~0); 11314#L996-3 assume 1 == ~E_6~0;~E_6~0 := 2; 12004#L1001-3 assume 1 == ~E_7~0;~E_7~0 := 2; 11657#L1006-3 assume 1 == ~E_8~0;~E_8~0 := 2; 11658#L1011-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 11352#L634-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 11353#L681-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 11606#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret24#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret24#1;havoc start_simulation_#t~ret24#1; 11607#L1291 assume !(0 == start_simulation_~tmp~3#1); 11872#L1291-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 11775#L634-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 11258#L681-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 11259#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret23#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret23#1;havoc stop_simulation_#t~ret23#1; 11317#L1246 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 11741#L1253 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 11742#stop_simulation_returnLabel#1 start_simulation_#t~ret25#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret25#1;havoc start_simulation_#t~ret25#1; 11827#L1304 assume !(0 != start_simulation_~tmp___0~1#1); 11326#L1272-2 [2023-11-06 21:58:42,136 INFO L145 PredicateUnifier]: Initialized classic predicate unifier [2023-11-06 21:58:42,137 INFO L85 PathProgramCache]: Analyzing trace with hash 2129867550, now seen corresponding path program 1 times [2023-11-06 21:58:42,137 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-06 21:58:42,137 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2028466287] [2023-11-06 21:58:42,139 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-06 21:58:42,139 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-06 21:58:42,158 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-06 21:58:42,214 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-06 21:58:42,214 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-06 21:58:42,215 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2028466287] [2023-11-06 21:58:42,215 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2028466287] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-06 21:58:42,215 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-06 21:58:42,215 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-06 21:58:42,215 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [241960209] [2023-11-06 21:58:42,216 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-06 21:58:42,216 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-06 21:58:42,216 INFO L145 PredicateUnifier]: Initialized classic predicate unifier [2023-11-06 21:58:42,217 INFO L85 PathProgramCache]: Analyzing trace with hash -567599280, now seen corresponding path program 1 times [2023-11-06 21:58:42,217 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-06 21:58:42,217 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [860164508] [2023-11-06 21:58:42,217 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-06 21:58:42,217 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-06 21:58:42,232 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-06 21:58:42,280 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-06 21:58:42,280 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-06 21:58:42,280 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [860164508] [2023-11-06 21:58:42,281 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [860164508] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-06 21:58:42,281 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-06 21:58:42,281 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-06 21:58:42,281 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1336753124] [2023-11-06 21:58:42,281 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-06 21:58:42,282 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-06 21:58:42,282 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-06 21:58:42,282 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-06 21:58:42,282 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-06 21:58:42,283 INFO L87 Difference]: Start difference. First operand 933 states and 1383 transitions. cyclomatic complexity: 451 Second operand has 3 states, 3 states have (on average 34.666666666666664) internal successors, (104), 3 states have internal predecessors, (104), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-06 21:58:42,309 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-06 21:58:42,309 INFO L93 Difference]: Finished difference Result 933 states and 1382 transitions. [2023-11-06 21:58:42,309 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 933 states and 1382 transitions. [2023-11-06 21:58:42,317 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 820 [2023-11-06 21:58:42,325 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 933 states to 933 states and 1382 transitions. [2023-11-06 21:58:42,325 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 933 [2023-11-06 21:58:42,326 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 933 [2023-11-06 21:58:42,327 INFO L73 IsDeterministic]: Start isDeterministic. Operand 933 states and 1382 transitions. [2023-11-06 21:58:42,328 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-06 21:58:42,328 INFO L218 hiAutomatonCegarLoop]: Abstraction has 933 states and 1382 transitions. [2023-11-06 21:58:42,331 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 933 states and 1382 transitions. [2023-11-06 21:58:42,344 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 933 to 933. [2023-11-06 21:58:42,346 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 933 states, 933 states have (on average 1.4812433011789925) internal successors, (1382), 932 states have internal predecessors, (1382), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-06 21:58:42,350 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 933 states to 933 states and 1382 transitions. [2023-11-06 21:58:42,351 INFO L240 hiAutomatonCegarLoop]: Abstraction has 933 states and 1382 transitions. [2023-11-06 21:58:42,351 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-06 21:58:42,353 INFO L428 stractBuchiCegarLoop]: Abstraction has 933 states and 1382 transitions. [2023-11-06 21:58:42,353 INFO L335 stractBuchiCegarLoop]: ======== Iteration 8 ============ [2023-11-06 21:58:42,353 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 933 states and 1382 transitions. [2023-11-06 21:58:42,359 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 820 [2023-11-06 21:58:42,359 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-06 21:58:42,359 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-06 21:58:42,361 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-06 21:58:42,361 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-06 21:58:42,362 INFO L748 eck$LassoCheckResult]: Stem: 13377#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2; 13378#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~10#1;havoc main_~__retres1~10#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; 14004#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret24#1, start_simulation_#t~ret25#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 14005#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 14006#L581 assume 1 == ~m_i~0;~m_st~0 := 0; 13496#L581-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 13497#L586-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 14002#L591-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 13998#L596-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 13568#L601-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 13569#L606-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 13803#L611-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 13804#L616-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 13652#L621-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 13653#L838 assume !(0 == ~M_E~0); 13812#L838-2 assume !(0 == ~T1_E~0); 13176#L843-1 assume !(0 == ~T2_E~0); 13177#L848-1 assume !(0 == ~T3_E~0); 13297#L853-1 assume !(0 == ~T4_E~0); 13641#L858-1 assume 0 == ~T5_E~0;~T5_E~0 := 1; 13129#L863-1 assume !(0 == ~T6_E~0); 13130#L868-1 assume !(0 == ~T7_E~0); 14034#L873-1 assume !(0 == ~T8_E~0); 14032#L878-1 assume !(0 == ~E_1~0); 14023#L883-1 assume !(0 == ~E_2~0); 14024#L888-1 assume !(0 == ~E_3~0); 13775#L893-1 assume !(0 == ~E_4~0); 13776#L898-1 assume 0 == ~E_5~0;~E_5~0 := 1; 14044#L903-1 assume !(0 == ~E_6~0); 14021#L908-1 assume !(0 == ~E_7~0); 13903#L913-1 assume !(0 == ~E_8~0); 13189#L918-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 13190#L402 assume !(1 == ~m_pc~0); 13404#L402-2 is_master_triggered_~__retres1~0#1 := 0; 13321#L413 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 13322#is_master_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 13574#L1035 assume !(0 != activate_threads_~tmp~1#1); 13575#L1035-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 13629#L421 assume 1 == ~t1_pc~0; 14017#L422 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 14038#L432 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 13191#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 13192#L1043 assume !(0 != activate_threads_~tmp___0~0#1); 13683#L1043-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 14042#L440 assume 1 == ~t2_pc~0; 13160#L441 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 13161#L451 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 13331#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 13522#L1051 assume !(0 != activate_threads_~tmp___1~0#1); 13917#L1051-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 13529#L459 assume !(1 == ~t3_pc~0); 13530#L459-2 is_transmit3_triggered_~__retres1~3#1 := 0; 14015#L470 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 13149#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 13150#L1059 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 13316#L1059-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 13325#L478 assume 1 == ~t4_pc~0; 13326#L479 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 13777#L489 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 13269#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 13270#L1067 assume !(0 != activate_threads_~tmp___3~0#1); 13232#L1067-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 13233#L497 assume !(1 == ~t5_pc~0); 13280#L497-2 is_transmit5_triggered_~__retres1~5#1 := 0; 13281#L508 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 13848#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 13954#L1075 assume !(0 != activate_threads_~tmp___4~0#1); 14011#L1075-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 14012#L516 assume 1 == ~t6_pc~0; 14058#L517 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 13802#L527 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 13505#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 13371#L1083 assume !(0 != activate_threads_~tmp___5~0#1); 13372#L1083-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 13791#L535 assume !(1 == ~t7_pc~0); 13792#L535-2 is_transmit7_triggered_~__retres1~7#1 := 0; 13862#L546 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 13863#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 13894#L1091 assume !(0 != activate_threads_~tmp___6~0#1); 13885#L1091-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 13886#L554 assume 1 == ~t8_pc~0; 13827#L555 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 13152#L565 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 13911#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 13462#L1099 assume !(0 != activate_threads_~tmp___7~0#1); 13463#L1099-2 havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 13138#L931 assume !(1 == ~M_E~0); 13139#L931-2 assume 1 == ~T1_E~0;~T1_E~0 := 2; 14030#L936-1 assume !(1 == ~T2_E~0); 14049#L941-1 assume !(1 == ~T3_E~0); 13627#L946-1 assume !(1 == ~T4_E~0); 13628#L951-1 assume !(1 == ~T5_E~0); 13386#L956-1 assume !(1 == ~T6_E~0); 13387#L961-1 assume !(1 == ~T7_E~0); 13772#L966-1 assume !(1 == ~T8_E~0); 13773#L971-1 assume 1 == ~E_1~0;~E_1~0 := 2; 13887#L976-1 assume !(1 == ~E_2~0); 13852#L981-1 assume !(1 == ~E_3~0); 13632#L986-1 assume !(1 == ~E_4~0); 13413#L991-1 assume !(1 == ~E_5~0); 13414#L996-1 assume !(1 == ~E_6~0); 14039#L1001-1 assume !(1 == ~E_7~0); 13822#L1006-1 assume !(1 == ~E_8~0); 13823#L1011-1 assume { :end_inline_reset_delta_events } true; 13199#L1272-2 [2023-11-06 21:58:42,363 INFO L750 eck$LassoCheckResult]: Loop: 13199#L1272-2 assume !false; 13200#L1273 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 13436#L813-1 assume !false; 13972#L692 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 13973#L634 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 13202#L681 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 13541#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 13542#L696 assume !(0 != eval_~tmp~0#1); 13915#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 13681#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 13682#L838-3 assume 0 == ~M_E~0;~M_E~0 := 1; 13871#L838-5 assume !(0 == ~T1_E~0); 13872#L843-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 13725#L848-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 13726#L853-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 13774#L858-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 13841#L863-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 13831#L868-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 13832#L873-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 13440#L878-3 assume !(0 == ~E_1~0); 13163#L883-3 assume 0 == ~E_2~0;~E_2~0 := 1; 13164#L888-3 assume 0 == ~E_3~0;~E_3~0 := 1; 13165#L893-3 assume 0 == ~E_4~0;~E_4~0 := 1; 13166#L898-3 assume 0 == ~E_5~0;~E_5~0 := 1; 13658#L903-3 assume 0 == ~E_6~0;~E_6~0 := 1; 13974#L908-3 assume 0 == ~E_7~0;~E_7~0 := 1; 13666#L913-3 assume 0 == ~E_8~0;~E_8~0 := 1; 13204#L918-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 13205#L402-27 assume 1 == ~m_pc~0; 13153#L403-9 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 13154#L413-9 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 13864#is_master_triggered_returnLabel#10 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 13865#L1035-27 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 13991#L1035-29 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 13992#L421-27 assume !(1 == ~t1_pc~0); 13430#L421-29 is_transmit1_triggered_~__retres1~1#1 := 0; 13431#L432-9 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 13750#is_transmit1_triggered_returnLabel#10 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 13751#L1043-27 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 14040#L1043-29 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 13794#L440-27 assume !(1 == ~t2_pc~0); 13795#L440-29 is_transmit2_triggered_~__retres1~2#1 := 0; 13968#L451-9 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 13836#is_transmit2_triggered_returnLabel#10 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 13701#L1051-27 assume !(0 != activate_threads_~tmp___1~0#1); 13702#L1051-29 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 13416#L459-27 assume 1 == ~t3_pc~0; 13417#L460-9 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 13857#L470-9 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 13678#is_transmit3_triggered_returnLabel#10 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 13679#L1059-27 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 13790#L1059-29 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 14033#L478-27 assume 1 == ~t4_pc~0; 14052#L479-9 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 13406#L489-9 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 13589#is_transmit4_triggered_returnLabel#10 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 13590#L1067-27 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 13939#L1067-29 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 13975#L497-27 assume 1 == ~t5_pc~0; 13976#L498-9 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 13449#L508-9 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 13450#is_transmit5_triggered_returnLabel#10 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 13392#L1075-27 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 13393#L1075-29 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 13660#L516-27 assume !(1 == ~t6_pc~0); 13661#L516-29 is_transmit6_triggered_~__retres1~6#1 := 0; 13513#L527-9 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 13514#is_transmit6_triggered_returnLabel#10 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 13813#L1083-27 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 13814#L1083-29 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 13593#L535-27 assume 1 == ~t7_pc~0; 13594#L536-9 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 13923#L546-9 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 13473#is_transmit7_triggered_returnLabel#10 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 13474#L1091-27 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 13544#L1091-29 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 13545#L554-27 assume 1 == ~t8_pc~0; 13747#L555-9 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 13179#L565-9 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 13330#is_transmit8_triggered_returnLabel#10 activate_threads_#t~ret22#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 13710#L1099-27 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 13437#L1099-29 havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 13438#L931-3 assume 1 == ~M_E~0;~M_E~0 := 2; 13312#L931-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 13313#L936-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 13543#L941-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 13677#L946-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 13453#L951-3 assume !(1 == ~T5_E~0); 13454#L956-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 13748#L961-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 13553#L966-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 13554#L971-3 assume 1 == ~E_1~0;~E_1~0 := 2; 13801#L976-3 assume 1 == ~E_2~0;~E_2~0 := 2; 13197#L981-3 assume 1 == ~E_3~0;~E_3~0 := 2; 13198#L986-3 assume 1 == ~E_4~0;~E_4~0 := 2; 13186#L991-3 assume !(1 == ~E_5~0); 13187#L996-3 assume 1 == ~E_6~0;~E_6~0 := 2; 13877#L1001-3 assume 1 == ~E_7~0;~E_7~0 := 2; 13527#L1006-3 assume 1 == ~E_8~0;~E_8~0 := 2; 13528#L1011-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 13225#L634-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 13226#L681-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 13479#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret24#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret24#1;havoc start_simulation_#t~ret24#1; 13480#L1291 assume !(0 == start_simulation_~tmp~3#1); 13745#L1291-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 13648#L634-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 13131#L681-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 13132#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret23#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret23#1;havoc stop_simulation_#t~ret23#1; 13188#L1246 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 13614#L1253 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 13615#stop_simulation_returnLabel#1 start_simulation_#t~ret25#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret25#1;havoc start_simulation_#t~ret25#1; 13700#L1304 assume !(0 != start_simulation_~tmp___0~1#1); 13199#L1272-2 [2023-11-06 21:58:42,364 INFO L145 PredicateUnifier]: Initialized classic predicate unifier [2023-11-06 21:58:42,364 INFO L85 PathProgramCache]: Analyzing trace with hash -1281590756, now seen corresponding path program 1 times [2023-11-06 21:58:42,364 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-06 21:58:42,364 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2059106232] [2023-11-06 21:58:42,365 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-06 21:58:42,365 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-06 21:58:42,378 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-06 21:58:42,412 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-06 21:58:42,412 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-06 21:58:42,413 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2059106232] [2023-11-06 21:58:42,414 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2059106232] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-06 21:58:42,414 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-06 21:58:42,414 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-06 21:58:42,419 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1576178281] [2023-11-06 21:58:42,419 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-06 21:58:42,420 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-06 21:58:42,420 INFO L145 PredicateUnifier]: Initialized classic predicate unifier [2023-11-06 21:58:42,420 INFO L85 PathProgramCache]: Analyzing trace with hash -567599280, now seen corresponding path program 2 times [2023-11-06 21:58:42,421 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-06 21:58:42,423 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [849095331] [2023-11-06 21:58:42,423 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-06 21:58:42,423 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-06 21:58:42,442 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-06 21:58:42,490 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-06 21:58:42,491 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-06 21:58:42,491 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [849095331] [2023-11-06 21:58:42,491 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [849095331] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-06 21:58:42,491 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-06 21:58:42,491 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-06 21:58:42,492 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [69066019] [2023-11-06 21:58:42,492 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-06 21:58:42,492 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-06 21:58:42,492 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-06 21:58:42,493 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-06 21:58:42,493 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-06 21:58:42,493 INFO L87 Difference]: Start difference. First operand 933 states and 1382 transitions. cyclomatic complexity: 450 Second operand has 3 states, 3 states have (on average 34.666666666666664) internal successors, (104), 3 states have internal predecessors, (104), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-06 21:58:42,519 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-06 21:58:42,520 INFO L93 Difference]: Finished difference Result 933 states and 1381 transitions. [2023-11-06 21:58:42,520 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 933 states and 1381 transitions. [2023-11-06 21:58:42,528 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 820 [2023-11-06 21:58:42,537 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 933 states to 933 states and 1381 transitions. [2023-11-06 21:58:42,537 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 933 [2023-11-06 21:58:42,538 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 933 [2023-11-06 21:58:42,538 INFO L73 IsDeterministic]: Start isDeterministic. Operand 933 states and 1381 transitions. [2023-11-06 21:58:42,540 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-06 21:58:42,540 INFO L218 hiAutomatonCegarLoop]: Abstraction has 933 states and 1381 transitions. [2023-11-06 21:58:42,543 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 933 states and 1381 transitions. [2023-11-06 21:58:42,556 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 933 to 933. [2023-11-06 21:58:42,559 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 933 states, 933 states have (on average 1.480171489817792) internal successors, (1381), 932 states have internal predecessors, (1381), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-06 21:58:42,563 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 933 states to 933 states and 1381 transitions. [2023-11-06 21:58:42,563 INFO L240 hiAutomatonCegarLoop]: Abstraction has 933 states and 1381 transitions. [2023-11-06 21:58:42,564 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-06 21:58:42,566 INFO L428 stractBuchiCegarLoop]: Abstraction has 933 states and 1381 transitions. [2023-11-06 21:58:42,566 INFO L335 stractBuchiCegarLoop]: ======== Iteration 9 ============ [2023-11-06 21:58:42,567 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 933 states and 1381 transitions. [2023-11-06 21:58:42,573 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 820 [2023-11-06 21:58:42,573 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-06 21:58:42,573 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-06 21:58:42,575 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-06 21:58:42,575 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-06 21:58:42,576 INFO L748 eck$LassoCheckResult]: Stem: 15250#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2; 15251#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~10#1;havoc main_~__retres1~10#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; 15877#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret24#1, start_simulation_#t~ret25#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 15878#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 15879#L581 assume 1 == ~m_i~0;~m_st~0 := 0; 15369#L581-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 15370#L586-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 15875#L591-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 15871#L596-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 15441#L601-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 15442#L606-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 15676#L611-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 15677#L616-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 15525#L621-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 15526#L838 assume !(0 == ~M_E~0); 15685#L838-2 assume !(0 == ~T1_E~0); 15049#L843-1 assume !(0 == ~T2_E~0); 15050#L848-1 assume !(0 == ~T3_E~0); 15170#L853-1 assume !(0 == ~T4_E~0); 15514#L858-1 assume 0 == ~T5_E~0;~T5_E~0 := 1; 15002#L863-1 assume !(0 == ~T6_E~0); 15003#L868-1 assume !(0 == ~T7_E~0); 15907#L873-1 assume !(0 == ~T8_E~0); 15905#L878-1 assume !(0 == ~E_1~0); 15896#L883-1 assume !(0 == ~E_2~0); 15897#L888-1 assume !(0 == ~E_3~0); 15645#L893-1 assume !(0 == ~E_4~0); 15646#L898-1 assume 0 == ~E_5~0;~E_5~0 := 1; 15917#L903-1 assume !(0 == ~E_6~0); 15894#L908-1 assume !(0 == ~E_7~0); 15776#L913-1 assume !(0 == ~E_8~0); 15062#L918-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 15063#L402 assume !(1 == ~m_pc~0); 15277#L402-2 is_master_triggered_~__retres1~0#1 := 0; 15194#L413 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 15195#is_master_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 15447#L1035 assume !(0 != activate_threads_~tmp~1#1); 15448#L1035-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 15500#L421 assume 1 == ~t1_pc~0; 15890#L422 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 15911#L432 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 15064#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 15065#L1043 assume !(0 != activate_threads_~tmp___0~0#1); 15554#L1043-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 15915#L440 assume 1 == ~t2_pc~0; 15033#L441 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 15034#L451 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 15204#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 15395#L1051 assume !(0 != activate_threads_~tmp___1~0#1); 15790#L1051-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 15402#L459 assume !(1 == ~t3_pc~0); 15403#L459-2 is_transmit3_triggered_~__retres1~3#1 := 0; 15888#L470 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 15022#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 15023#L1059 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 15189#L1059-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 15198#L478 assume 1 == ~t4_pc~0; 15199#L479 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 15650#L489 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 15142#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 15143#L1067 assume !(0 != activate_threads_~tmp___3~0#1); 15105#L1067-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 15106#L497 assume !(1 == ~t5_pc~0); 15153#L497-2 is_transmit5_triggered_~__retres1~5#1 := 0; 15154#L508 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 15721#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 15827#L1075 assume !(0 != activate_threads_~tmp___4~0#1); 15884#L1075-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 15885#L516 assume 1 == ~t6_pc~0; 15931#L517 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 15675#L527 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 15378#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 15244#L1083 assume !(0 != activate_threads_~tmp___5~0#1); 15245#L1083-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 15664#L535 assume !(1 == ~t7_pc~0); 15665#L535-2 is_transmit7_triggered_~__retres1~7#1 := 0; 15735#L546 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 15736#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 15767#L1091 assume !(0 != activate_threads_~tmp___6~0#1); 15758#L1091-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 15759#L554 assume 1 == ~t8_pc~0; 15700#L555 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 15025#L565 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 15783#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 15335#L1099 assume !(0 != activate_threads_~tmp___7~0#1); 15336#L1099-2 havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 15011#L931 assume !(1 == ~M_E~0); 15012#L931-2 assume 1 == ~T1_E~0;~T1_E~0 := 2; 15903#L936-1 assume !(1 == ~T2_E~0); 15922#L941-1 assume !(1 == ~T3_E~0); 15501#L946-1 assume !(1 == ~T4_E~0); 15502#L951-1 assume !(1 == ~T5_E~0); 15259#L956-1 assume !(1 == ~T6_E~0); 15260#L961-1 assume !(1 == ~T7_E~0); 15647#L966-1 assume !(1 == ~T8_E~0); 15648#L971-1 assume 1 == ~E_1~0;~E_1~0 := 2; 15761#L976-1 assume !(1 == ~E_2~0); 15725#L981-1 assume !(1 == ~E_3~0); 15505#L986-1 assume !(1 == ~E_4~0); 15286#L991-1 assume !(1 == ~E_5~0); 15287#L996-1 assume !(1 == ~E_6~0); 15912#L1001-1 assume !(1 == ~E_7~0); 15695#L1006-1 assume !(1 == ~E_8~0); 15696#L1011-1 assume { :end_inline_reset_delta_events } true; 15072#L1272-2 [2023-11-06 21:58:42,576 INFO L750 eck$LassoCheckResult]: Loop: 15072#L1272-2 assume !false; 15073#L1273 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 15311#L813-1 assume !false; 15845#L692 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 15846#L634 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 15075#L681 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 15414#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 15415#L696 assume !(0 != eval_~tmp~0#1); 15788#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 15555#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 15556#L838-3 assume 0 == ~M_E~0;~M_E~0 := 1; 15744#L838-5 assume !(0 == ~T1_E~0); 15745#L843-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 15599#L848-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 15600#L853-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 15649#L858-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 15714#L863-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 15705#L868-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 15706#L873-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 15315#L878-3 assume !(0 == ~E_1~0); 15038#L883-3 assume 0 == ~E_2~0;~E_2~0 := 1; 15039#L888-3 assume 0 == ~E_3~0;~E_3~0 := 1; 15036#L893-3 assume 0 == ~E_4~0;~E_4~0 := 1; 15037#L898-3 assume 0 == ~E_5~0;~E_5~0 := 1; 15531#L903-3 assume 0 == ~E_6~0;~E_6~0 := 1; 15847#L908-3 assume 0 == ~E_7~0;~E_7~0 := 1; 15539#L913-3 assume 0 == ~E_8~0;~E_8~0 := 1; 15077#L918-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 15078#L402-27 assume 1 == ~m_pc~0; 15026#L403-9 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 15027#L413-9 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 15737#is_master_triggered_returnLabel#10 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 15738#L1035-27 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 15864#L1035-29 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 15865#L421-27 assume !(1 == ~t1_pc~0); 15303#L421-29 is_transmit1_triggered_~__retres1~1#1 := 0; 15304#L432-9 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 15623#is_transmit1_triggered_returnLabel#10 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 15624#L1043-27 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 15913#L1043-29 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 15667#L440-27 assume !(1 == ~t2_pc~0); 15668#L440-29 is_transmit2_triggered_~__retres1~2#1 := 0; 15841#L451-9 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 15709#is_transmit2_triggered_returnLabel#10 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 15574#L1051-27 assume !(0 != activate_threads_~tmp___1~0#1); 15575#L1051-29 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 15289#L459-27 assume 1 == ~t3_pc~0; 15290#L460-9 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 15730#L470-9 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 15551#is_transmit3_triggered_returnLabel#10 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 15552#L1059-27 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 15663#L1059-29 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 15906#L478-27 assume 1 == ~t4_pc~0; 15925#L479-9 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 15279#L489-9 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 15462#is_transmit4_triggered_returnLabel#10 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 15463#L1067-27 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 15812#L1067-29 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 15848#L497-27 assume !(1 == ~t5_pc~0); 15456#L497-29 is_transmit5_triggered_~__retres1~5#1 := 0; 15322#L508-9 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 15323#is_transmit5_triggered_returnLabel#10 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 15265#L1075-27 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 15266#L1075-29 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 15532#L516-27 assume !(1 == ~t6_pc~0); 15533#L516-29 is_transmit6_triggered_~__retres1~6#1 := 0; 15383#L527-9 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 15384#is_transmit6_triggered_returnLabel#10 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 15686#L1083-27 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 15687#L1083-29 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 15466#L535-27 assume 1 == ~t7_pc~0; 15467#L536-9 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 15796#L546-9 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 15346#is_transmit7_triggered_returnLabel#10 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 15347#L1091-27 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 15417#L1091-29 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 15418#L554-27 assume 1 == ~t8_pc~0; 15620#L555-9 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 15052#L565-9 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 15203#is_transmit8_triggered_returnLabel#10 activate_threads_#t~ret22#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 15580#L1099-27 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 15308#L1099-29 havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 15309#L931-3 assume 1 == ~M_E~0;~M_E~0 := 2; 15185#L931-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 15186#L936-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 15416#L941-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 15550#L946-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 15326#L951-3 assume !(1 == ~T5_E~0); 15327#L956-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 15621#L961-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 15426#L966-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 15427#L971-3 assume 1 == ~E_1~0;~E_1~0 := 2; 15674#L976-3 assume 1 == ~E_2~0;~E_2~0 := 2; 15070#L981-3 assume 1 == ~E_3~0;~E_3~0 := 2; 15071#L986-3 assume 1 == ~E_4~0;~E_4~0 := 2; 15059#L991-3 assume !(1 == ~E_5~0); 15060#L996-3 assume 1 == ~E_6~0;~E_6~0 := 2; 15750#L1001-3 assume 1 == ~E_7~0;~E_7~0 := 2; 15400#L1006-3 assume 1 == ~E_8~0;~E_8~0 := 2; 15401#L1011-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 15098#L634-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 15099#L681-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 15348#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret24#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret24#1;havoc start_simulation_#t~ret24#1; 15349#L1291 assume !(0 == start_simulation_~tmp~3#1); 15618#L1291-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 15521#L634-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 15004#L681-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 15005#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret23#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret23#1;havoc stop_simulation_#t~ret23#1; 15061#L1246 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 15487#L1253 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 15488#stop_simulation_returnLabel#1 start_simulation_#t~ret25#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret25#1;havoc start_simulation_#t~ret25#1; 15573#L1304 assume !(0 != start_simulation_~tmp___0~1#1); 15072#L1272-2 [2023-11-06 21:58:42,577 INFO L145 PredicateUnifier]: Initialized classic predicate unifier [2023-11-06 21:58:42,577 INFO L85 PathProgramCache]: Analyzing trace with hash -1253090466, now seen corresponding path program 1 times [2023-11-06 21:58:42,578 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-06 21:58:42,578 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [327956780] [2023-11-06 21:58:42,578 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-06 21:58:42,578 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-06 21:58:42,594 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-06 21:58:42,660 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-06 21:58:42,661 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-06 21:58:42,661 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [327956780] [2023-11-06 21:58:42,661 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [327956780] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-06 21:58:42,661 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-06 21:58:42,661 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2023-11-06 21:58:42,662 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [97754622] [2023-11-06 21:58:42,662 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-06 21:58:42,662 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-06 21:58:42,663 INFO L145 PredicateUnifier]: Initialized classic predicate unifier [2023-11-06 21:58:42,663 INFO L85 PathProgramCache]: Analyzing trace with hash -464798033, now seen corresponding path program 1 times [2023-11-06 21:58:42,663 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-06 21:58:42,663 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [568594236] [2023-11-06 21:58:42,664 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-06 21:58:42,664 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-06 21:58:42,679 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-06 21:58:42,722 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-06 21:58:42,722 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-06 21:58:42,722 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [568594236] [2023-11-06 21:58:42,722 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [568594236] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-06 21:58:42,722 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-06 21:58:42,723 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-06 21:58:42,723 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1890350334] [2023-11-06 21:58:42,723 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-06 21:58:42,723 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-06 21:58:42,724 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-06 21:58:42,724 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-06 21:58:42,724 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-06 21:58:42,724 INFO L87 Difference]: Start difference. First operand 933 states and 1381 transitions. cyclomatic complexity: 449 Second operand has 3 states, 3 states have (on average 34.666666666666664) internal successors, (104), 2 states have internal predecessors, (104), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-06 21:58:42,755 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-06 21:58:42,755 INFO L93 Difference]: Finished difference Result 933 states and 1376 transitions. [2023-11-06 21:58:42,755 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 933 states and 1376 transitions. [2023-11-06 21:58:42,764 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 820 [2023-11-06 21:58:42,771 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 933 states to 933 states and 1376 transitions. [2023-11-06 21:58:42,772 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 933 [2023-11-06 21:58:42,773 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 933 [2023-11-06 21:58:42,773 INFO L73 IsDeterministic]: Start isDeterministic. Operand 933 states and 1376 transitions. [2023-11-06 21:58:42,775 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-06 21:58:42,775 INFO L218 hiAutomatonCegarLoop]: Abstraction has 933 states and 1376 transitions. [2023-11-06 21:58:42,777 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 933 states and 1376 transitions. [2023-11-06 21:58:42,791 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 933 to 933. [2023-11-06 21:58:42,794 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 933 states, 933 states have (on average 1.47481243301179) internal successors, (1376), 932 states have internal predecessors, (1376), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-06 21:58:42,830 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 933 states to 933 states and 1376 transitions. [2023-11-06 21:58:42,830 INFO L240 hiAutomatonCegarLoop]: Abstraction has 933 states and 1376 transitions. [2023-11-06 21:58:42,830 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-06 21:58:42,831 INFO L428 stractBuchiCegarLoop]: Abstraction has 933 states and 1376 transitions. [2023-11-06 21:58:42,831 INFO L335 stractBuchiCegarLoop]: ======== Iteration 10 ============ [2023-11-06 21:58:42,831 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 933 states and 1376 transitions. [2023-11-06 21:58:42,837 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 820 [2023-11-06 21:58:42,837 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-06 21:58:42,837 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-06 21:58:42,839 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-06 21:58:42,839 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-06 21:58:42,840 INFO L748 eck$LassoCheckResult]: Stem: 17123#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2; 17124#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~10#1;havoc main_~__retres1~10#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; 17750#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret24#1, start_simulation_#t~ret25#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 17751#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 17752#L581 assume 1 == ~m_i~0;~m_st~0 := 0; 17242#L581-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 17243#L586-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 17748#L591-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 17744#L596-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 17314#L601-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 17315#L606-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 17549#L611-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 17550#L616-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 17398#L621-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 17399#L838 assume !(0 == ~M_E~0); 17558#L838-2 assume !(0 == ~T1_E~0); 16922#L843-1 assume !(0 == ~T2_E~0); 16923#L848-1 assume !(0 == ~T3_E~0); 17043#L853-1 assume !(0 == ~T4_E~0); 17387#L858-1 assume !(0 == ~T5_E~0); 16873#L863-1 assume !(0 == ~T6_E~0); 16874#L868-1 assume !(0 == ~T7_E~0); 17780#L873-1 assume !(0 == ~T8_E~0); 17778#L878-1 assume !(0 == ~E_1~0); 17769#L883-1 assume !(0 == ~E_2~0); 17770#L888-1 assume !(0 == ~E_3~0); 17518#L893-1 assume !(0 == ~E_4~0); 17519#L898-1 assume 0 == ~E_5~0;~E_5~0 := 1; 17790#L903-1 assume !(0 == ~E_6~0); 17767#L908-1 assume !(0 == ~E_7~0); 17648#L913-1 assume !(0 == ~E_8~0); 16935#L918-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 16936#L402 assume !(1 == ~m_pc~0); 17148#L402-2 is_master_triggered_~__retres1~0#1 := 0; 17067#L413 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 17068#is_master_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 17320#L1035 assume !(0 != activate_threads_~tmp~1#1); 17321#L1035-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 17373#L421 assume 1 == ~t1_pc~0; 17763#L422 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 17784#L432 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 16937#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 16938#L1043 assume !(0 != activate_threads_~tmp___0~0#1); 17427#L1043-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 17788#L440 assume 1 == ~t2_pc~0; 16906#L441 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 16907#L451 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 17077#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 17268#L1051 assume !(0 != activate_threads_~tmp___1~0#1); 17663#L1051-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 17275#L459 assume !(1 == ~t3_pc~0); 17276#L459-2 is_transmit3_triggered_~__retres1~3#1 := 0; 17761#L470 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 16895#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 16896#L1059 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 17062#L1059-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 17071#L478 assume 1 == ~t4_pc~0; 17072#L479 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 17523#L489 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 17015#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 17016#L1067 assume !(0 != activate_threads_~tmp___3~0#1); 16978#L1067-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 16979#L497 assume !(1 == ~t5_pc~0); 17026#L497-2 is_transmit5_triggered_~__retres1~5#1 := 0; 17027#L508 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 17594#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 17700#L1075 assume !(0 != activate_threads_~tmp___4~0#1); 17757#L1075-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 17758#L516 assume 1 == ~t6_pc~0; 17804#L517 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 17548#L527 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 17251#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 17117#L1083 assume !(0 != activate_threads_~tmp___5~0#1); 17118#L1083-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 17537#L535 assume !(1 == ~t7_pc~0); 17538#L535-2 is_transmit7_triggered_~__retres1~7#1 := 0; 17608#L546 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 17609#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 17640#L1091 assume !(0 != activate_threads_~tmp___6~0#1); 17630#L1091-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 17631#L554 assume 1 == ~t8_pc~0; 17573#L555 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 16898#L565 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 17656#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 17208#L1099 assume !(0 != activate_threads_~tmp___7~0#1); 17209#L1099-2 havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 16884#L931 assume !(1 == ~M_E~0); 16885#L931-2 assume 1 == ~T1_E~0;~T1_E~0 := 2; 17776#L936-1 assume !(1 == ~T2_E~0); 17795#L941-1 assume !(1 == ~T3_E~0); 17374#L946-1 assume !(1 == ~T4_E~0); 17375#L951-1 assume !(1 == ~T5_E~0); 17132#L956-1 assume !(1 == ~T6_E~0); 17133#L961-1 assume !(1 == ~T7_E~0); 17520#L966-1 assume !(1 == ~T8_E~0); 17521#L971-1 assume 1 == ~E_1~0;~E_1~0 := 2; 17633#L976-1 assume !(1 == ~E_2~0); 17598#L981-1 assume !(1 == ~E_3~0); 17378#L986-1 assume !(1 == ~E_4~0); 17159#L991-1 assume !(1 == ~E_5~0); 17160#L996-1 assume !(1 == ~E_6~0); 17785#L1001-1 assume !(1 == ~E_7~0); 17568#L1006-1 assume !(1 == ~E_8~0); 17569#L1011-1 assume { :end_inline_reset_delta_events } true; 16945#L1272-2 [2023-11-06 21:58:42,840 INFO L750 eck$LassoCheckResult]: Loop: 16945#L1272-2 assume !false; 16946#L1273 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 17184#L813-1 assume !false; 17718#L692 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 17719#L634 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 16948#L681 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 17287#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 17288#L696 assume !(0 != eval_~tmp~0#1); 17661#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 17428#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 17429#L838-3 assume 0 == ~M_E~0;~M_E~0 := 1; 17617#L838-5 assume !(0 == ~T1_E~0); 17618#L843-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 17471#L848-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 17472#L853-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 17522#L858-3 assume !(0 == ~T5_E~0); 17587#L863-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 17578#L868-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 17579#L873-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 17188#L878-3 assume !(0 == ~E_1~0); 16909#L883-3 assume 0 == ~E_2~0;~E_2~0 := 1; 16910#L888-3 assume 0 == ~E_3~0;~E_3~0 := 1; 16911#L893-3 assume 0 == ~E_4~0;~E_4~0 := 1; 16912#L898-3 assume 0 == ~E_5~0;~E_5~0 := 1; 17404#L903-3 assume 0 == ~E_6~0;~E_6~0 := 1; 17722#L908-3 assume 0 == ~E_7~0;~E_7~0 := 1; 17412#L913-3 assume 0 == ~E_8~0;~E_8~0 := 1; 16950#L918-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 16951#L402-27 assume 1 == ~m_pc~0; 16899#L403-9 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 16900#L413-9 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 17610#is_master_triggered_returnLabel#10 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 17611#L1035-27 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 17737#L1035-29 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 17738#L421-27 assume !(1 == ~t1_pc~0); 17176#L421-29 is_transmit1_triggered_~__retres1~1#1 := 0; 17177#L432-9 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 17496#is_transmit1_triggered_returnLabel#10 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 17497#L1043-27 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 17786#L1043-29 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 17540#L440-27 assume !(1 == ~t2_pc~0); 17541#L440-29 is_transmit2_triggered_~__retres1~2#1 := 0; 17714#L451-9 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 17582#is_transmit2_triggered_returnLabel#10 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 17447#L1051-27 assume !(0 != activate_threads_~tmp___1~0#1); 17448#L1051-29 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 17162#L459-27 assume 1 == ~t3_pc~0; 17163#L460-9 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 17603#L470-9 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 17424#is_transmit3_triggered_returnLabel#10 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 17425#L1059-27 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 17536#L1059-29 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 17779#L478-27 assume 1 == ~t4_pc~0; 17798#L479-9 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 17152#L489-9 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 17335#is_transmit4_triggered_returnLabel#10 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 17336#L1067-27 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 17685#L1067-29 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 17720#L497-27 assume 1 == ~t5_pc~0; 17721#L498-9 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 17195#L508-9 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 17196#is_transmit5_triggered_returnLabel#10 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 17138#L1075-27 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 17139#L1075-29 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 17405#L516-27 assume !(1 == ~t6_pc~0); 17406#L516-29 is_transmit6_triggered_~__retres1~6#1 := 0; 17252#L527-9 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 17253#is_transmit6_triggered_returnLabel#10 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 17559#L1083-27 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 17560#L1083-29 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 17339#L535-27 assume 1 == ~t7_pc~0; 17340#L536-9 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 17667#L546-9 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 17219#is_transmit7_triggered_returnLabel#10 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 17220#L1091-27 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 17290#L1091-29 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 17291#L554-27 assume 1 == ~t8_pc~0; 17493#L555-9 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 16925#L565-9 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 17076#is_transmit8_triggered_returnLabel#10 activate_threads_#t~ret22#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 17453#L1099-27 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 17181#L1099-29 havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 17182#L931-3 assume 1 == ~M_E~0;~M_E~0 := 2; 17058#L931-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 17059#L936-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 17289#L941-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 17423#L946-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 17199#L951-3 assume !(1 == ~T5_E~0); 17200#L956-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 17494#L961-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 17299#L966-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 17300#L971-3 assume 1 == ~E_1~0;~E_1~0 := 2; 17547#L976-3 assume 1 == ~E_2~0;~E_2~0 := 2; 16943#L981-3 assume 1 == ~E_3~0;~E_3~0 := 2; 16944#L986-3 assume 1 == ~E_4~0;~E_4~0 := 2; 16932#L991-3 assume !(1 == ~E_5~0); 16933#L996-3 assume 1 == ~E_6~0;~E_6~0 := 2; 17623#L1001-3 assume 1 == ~E_7~0;~E_7~0 := 2; 17273#L1006-3 assume 1 == ~E_8~0;~E_8~0 := 2; 17274#L1011-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 16971#L634-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 16972#L681-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 17221#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret24#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret24#1;havoc start_simulation_#t~ret24#1; 17222#L1291 assume !(0 == start_simulation_~tmp~3#1); 17491#L1291-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 17392#L634-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 16877#L681-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 16878#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret23#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret23#1;havoc stop_simulation_#t~ret23#1; 16934#L1246 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 17359#L1253 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 17360#stop_simulation_returnLabel#1 start_simulation_#t~ret25#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret25#1;havoc start_simulation_#t~ret25#1; 17446#L1304 assume !(0 != start_simulation_~tmp___0~1#1); 16945#L1272-2 [2023-11-06 21:58:42,841 INFO L145 PredicateUnifier]: Initialized classic predicate unifier [2023-11-06 21:58:42,841 INFO L85 PathProgramCache]: Analyzing trace with hash 623392352, now seen corresponding path program 1 times [2023-11-06 21:58:42,841 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-06 21:58:42,841 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [908343402] [2023-11-06 21:58:42,841 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-06 21:58:42,842 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-06 21:58:42,855 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-06 21:58:42,936 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-06 21:58:42,936 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-06 21:58:42,936 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [908343402] [2023-11-06 21:58:42,936 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [908343402] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-06 21:58:42,937 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-06 21:58:42,937 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-06 21:58:42,937 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [946282380] [2023-11-06 21:58:42,937 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-06 21:58:42,938 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-06 21:58:42,939 INFO L145 PredicateUnifier]: Initialized classic predicate unifier [2023-11-06 21:58:42,939 INFO L85 PathProgramCache]: Analyzing trace with hash 1033471826, now seen corresponding path program 1 times [2023-11-06 21:58:42,939 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-06 21:58:42,939 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [867705600] [2023-11-06 21:58:42,939 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-06 21:58:42,940 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-06 21:58:42,954 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-06 21:58:42,995 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-06 21:58:42,995 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-06 21:58:42,995 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [867705600] [2023-11-06 21:58:42,995 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [867705600] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-06 21:58:42,996 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-06 21:58:42,996 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-06 21:58:42,996 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1693352892] [2023-11-06 21:58:42,996 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-06 21:58:42,996 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-06 21:58:42,997 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-06 21:58:42,997 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2023-11-06 21:58:42,997 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2023-11-06 21:58:42,997 INFO L87 Difference]: Start difference. First operand 933 states and 1376 transitions. cyclomatic complexity: 444 Second operand has 4 states, 4 states have (on average 26.0) internal successors, (104), 3 states have internal predecessors, (104), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-06 21:58:43,211 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-06 21:58:43,211 INFO L93 Difference]: Finished difference Result 1704 states and 2511 transitions. [2023-11-06 21:58:43,211 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1704 states and 2511 transitions. [2023-11-06 21:58:43,224 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 1575 [2023-11-06 21:58:43,239 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1704 states to 1704 states and 2511 transitions. [2023-11-06 21:58:43,239 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1704 [2023-11-06 21:58:43,241 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1704 [2023-11-06 21:58:43,241 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1704 states and 2511 transitions. [2023-11-06 21:58:43,245 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-06 21:58:43,245 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1704 states and 2511 transitions. [2023-11-06 21:58:43,248 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1704 states and 2511 transitions. [2023-11-06 21:58:43,278 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1704 to 1703. [2023-11-06 21:58:43,282 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1703 states, 1703 states have (on average 1.473869641808573) internal successors, (2510), 1702 states have internal predecessors, (2510), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-06 21:58:43,289 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1703 states to 1703 states and 2510 transitions. [2023-11-06 21:58:43,290 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1703 states and 2510 transitions. [2023-11-06 21:58:43,290 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2023-11-06 21:58:43,290 INFO L428 stractBuchiCegarLoop]: Abstraction has 1703 states and 2510 transitions. [2023-11-06 21:58:43,291 INFO L335 stractBuchiCegarLoop]: ======== Iteration 11 ============ [2023-11-06 21:58:43,291 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1703 states and 2510 transitions. [2023-11-06 21:58:43,300 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 1575 [2023-11-06 21:58:43,300 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-06 21:58:43,300 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-06 21:58:43,302 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-06 21:58:43,302 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-06 21:58:43,303 INFO L748 eck$LassoCheckResult]: Stem: 19770#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2; 19771#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~10#1;havoc main_~__retres1~10#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; 20417#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret24#1, start_simulation_#t~ret25#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 20418#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 20419#L581 assume 1 == ~m_i~0;~m_st~0 := 0; 19889#L581-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 19890#L586-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 20415#L591-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 20409#L596-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 19963#L601-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 19964#L606-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 20207#L611-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 20208#L616-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 20048#L621-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 20049#L838 assume !(0 == ~M_E~0); 20215#L838-2 assume !(0 == ~T1_E~0); 19569#L843-1 assume !(0 == ~T2_E~0); 19570#L848-1 assume !(0 == ~T3_E~0); 19690#L853-1 assume !(0 == ~T4_E~0); 20035#L858-1 assume !(0 == ~T5_E~0); 19520#L863-1 assume !(0 == ~T6_E~0); 19521#L868-1 assume !(0 == ~T7_E~0); 20452#L873-1 assume !(0 == ~T8_E~0); 20450#L878-1 assume !(0 == ~E_1~0); 20438#L883-1 assume !(0 == ~E_2~0); 20439#L888-1 assume !(0 == ~E_3~0); 20175#L893-1 assume !(0 == ~E_4~0); 20176#L898-1 assume !(0 == ~E_5~0); 20464#L903-1 assume !(0 == ~E_6~0); 20436#L908-1 assume !(0 == ~E_7~0); 20306#L913-1 assume !(0 == ~E_8~0); 19581#L918-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 19582#L402 assume !(1 == ~m_pc~0); 19793#L402-2 is_master_triggered_~__retres1~0#1 := 0; 19714#L413 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 19715#is_master_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 19969#L1035 assume !(0 != activate_threads_~tmp~1#1); 19970#L1035-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 20023#L421 assume 1 == ~t1_pc~0; 20432#L422 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 20453#L432 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 19584#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 19585#L1043 assume !(0 != activate_threads_~tmp___0~0#1); 20079#L1043-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 20462#L440 assume 1 == ~t2_pc~0; 19553#L441 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 19554#L451 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 19724#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 19915#L1051 assume !(0 != activate_threads_~tmp___1~0#1); 20325#L1051-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 19918#L459 assume !(1 == ~t3_pc~0); 19919#L459-2 is_transmit3_triggered_~__retres1~3#1 := 0; 20428#L470 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 19542#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 19543#L1059 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 19709#L1059-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 19718#L478 assume 1 == ~t4_pc~0; 19719#L479 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 20180#L489 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 19662#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 19663#L1067 assume !(0 != activate_threads_~tmp___3~0#1); 19623#L1067-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 19624#L497 assume !(1 == ~t5_pc~0); 19673#L497-2 is_transmit5_triggered_~__retres1~5#1 := 0; 19674#L508 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 20252#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 20363#L1075 assume !(0 != activate_threads_~tmp___4~0#1); 20424#L1075-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 20425#L516 assume 1 == ~t6_pc~0; 20486#L517 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 20206#L527 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 19898#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 19764#L1083 assume !(0 != activate_threads_~tmp___5~0#1); 19765#L1083-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 20195#L535 assume !(1 == ~t7_pc~0); 20196#L535-2 is_transmit7_triggered_~__retres1~7#1 := 0; 20266#L546 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 20267#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 20298#L1091 assume !(0 != activate_threads_~tmp___6~0#1); 20288#L1091-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 20289#L554 assume 1 == ~t8_pc~0; 20231#L555 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 19545#L565 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 20316#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 19852#L1099 assume !(0 != activate_threads_~tmp___7~0#1); 19853#L1099-2 havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 19531#L931 assume !(1 == ~M_E~0); 19532#L931-2 assume 1 == ~T1_E~0;~T1_E~0 := 2; 20447#L936-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 20473#L941-1 assume !(1 == ~T3_E~0); 20024#L946-1 assume !(1 == ~T4_E~0); 20025#L951-1 assume !(1 == ~T5_E~0); 19779#L956-1 assume !(1 == ~T6_E~0); 19780#L961-1 assume !(1 == ~T7_E~0); 20177#L966-1 assume !(1 == ~T8_E~0); 20178#L971-1 assume 1 == ~E_1~0;~E_1~0 := 2; 20291#L976-1 assume !(1 == ~E_2~0); 20256#L981-1 assume !(1 == ~E_3~0); 20028#L986-1 assume !(1 == ~E_4~0); 19806#L991-1 assume !(1 == ~E_5~0); 19807#L996-1 assume !(1 == ~E_6~0); 20457#L1001-1 assume !(1 == ~E_7~0); 20226#L1006-1 assume !(1 == ~E_8~0); 20227#L1011-1 assume { :end_inline_reset_delta_events } true; 20505#L1272-2 [2023-11-06 21:58:43,303 INFO L750 eck$LassoCheckResult]: Loop: 20505#L1272-2 assume !false; 20501#L1273 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 20476#L813-1 assume !false; 20477#L692 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 20499#L634 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 20172#L681 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 19934#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 19935#L696 assume !(0 != eval_~tmp~0#1); 20322#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 20323#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 20412#L838-3 assume 0 == ~M_E~0;~M_E~0 := 1; 20413#L838-5 assume !(0 == ~T1_E~0); 20489#L843-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 20123#L848-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 20124#L853-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 20179#L858-3 assume !(0 == ~T5_E~0); 20245#L863-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 20235#L868-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 20236#L873-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 19833#L878-3 assume !(0 == ~E_1~0); 19556#L883-3 assume 0 == ~E_2~0;~E_2~0 := 1; 19557#L888-3 assume 0 == ~E_3~0;~E_3~0 := 1; 19558#L893-3 assume 0 == ~E_4~0;~E_4~0 := 1; 19559#L898-3 assume !(0 == ~E_5~0); 20054#L903-3 assume 0 == ~E_6~0;~E_6~0 := 1; 20383#L908-3 assume 0 == ~E_7~0;~E_7~0 := 1; 20063#L913-3 assume 0 == ~E_8~0;~E_8~0 := 1; 19597#L918-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 19598#L402-27 assume 1 == ~m_pc~0; 19546#L403-9 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 19547#L413-9 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 20268#is_master_triggered_returnLabel#10 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 20269#L1035-27 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 20402#L1035-29 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 20403#L421-27 assume 1 == ~t1_pc~0; 20304#L422-9 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 19824#L432-9 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 20151#is_transmit1_triggered_returnLabel#10 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 20152#L1043-27 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 20458#L1043-29 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 20198#L440-27 assume !(1 == ~t2_pc~0); 20199#L440-29 is_transmit2_triggered_~__retres1~2#1 := 0; 20378#L451-9 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 20240#is_transmit2_triggered_returnLabel#10 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 20099#L1051-27 assume !(0 != activate_threads_~tmp___1~0#1); 20100#L1051-29 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 19809#L459-27 assume 1 == ~t3_pc~0; 19810#L460-9 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 20261#L470-9 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 20075#is_transmit3_triggered_returnLabel#10 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 20076#L1059-27 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 20194#L1059-29 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 20451#L478-27 assume !(1 == ~t4_pc~0); 19798#L478-29 is_transmit4_triggered_~__retres1~4#1 := 0; 19799#L489-9 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 19984#is_transmit4_triggered_returnLabel#10 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 19985#L1067-27 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 20347#L1067-29 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 20384#L497-27 assume 1 == ~t5_pc~0; 20385#L498-9 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 19842#L508-9 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 19843#is_transmit5_triggered_returnLabel#10 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 19785#L1075-27 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 19786#L1075-29 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 20056#L516-27 assume !(1 == ~t6_pc~0); 20057#L516-29 is_transmit6_triggered_~__retres1~6#1 := 0; 19906#L527-9 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 19907#is_transmit6_triggered_returnLabel#10 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 20217#L1083-27 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 20218#L1083-29 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 19988#L535-27 assume 1 == ~t7_pc~0; 19989#L536-9 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 20331#L546-9 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 19866#is_transmit7_triggered_returnLabel#10 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 19867#L1091-27 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 19938#L1091-29 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 19939#L554-27 assume !(1 == ~t8_pc~0); 19571#L554-29 is_transmit8_triggered_~__retres1~8#1 := 0; 19572#L565-9 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 19723#is_transmit8_triggered_returnLabel#10 activate_threads_#t~ret22#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 20108#L1099-27 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 19830#L1099-29 havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 19831#L931-3 assume 1 == ~M_E~0;~M_E~0 := 2; 19705#L931-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 19706#L936-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 19937#L941-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 20074#L946-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 19846#L951-3 assume !(1 == ~T5_E~0); 19847#L956-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 20149#L961-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 19948#L966-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 19949#L971-3 assume 1 == ~E_1~0;~E_1~0 := 2; 20205#L976-3 assume 1 == ~E_2~0;~E_2~0 := 2; 19590#L981-3 assume 1 == ~E_3~0;~E_3~0 := 2; 19591#L986-3 assume 1 == ~E_4~0;~E_4~0 := 2; 19579#L991-3 assume !(1 == ~E_5~0); 19580#L996-3 assume 1 == ~E_6~0;~E_6~0 := 2; 20281#L1001-3 assume 1 == ~E_7~0;~E_7~0 := 2; 19923#L1006-3 assume 1 == ~E_8~0;~E_8~0 := 2; 19924#L1011-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 19618#L634-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 19619#L681-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 20078#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret24#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret24#1;havoc start_simulation_#t~ret24#1; 20537#L1291 assume !(0 == start_simulation_~tmp~3#1); 20535#L1291-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 20534#L634-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 20524#L681-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 20523#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret23#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret23#1;havoc stop_simulation_#t~ret23#1; 20442#L1246 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 20009#L1253 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 20010#stop_simulation_returnLabel#1 start_simulation_#t~ret25#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret25#1;havoc start_simulation_#t~ret25#1; 20098#L1304 assume !(0 != start_simulation_~tmp___0~1#1); 20505#L1272-2 [2023-11-06 21:58:43,304 INFO L145 PredicateUnifier]: Initialized classic predicate unifier [2023-11-06 21:58:43,304 INFO L85 PathProgramCache]: Analyzing trace with hash 1671526308, now seen corresponding path program 1 times [2023-11-06 21:58:43,304 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-06 21:58:43,304 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2130291043] [2023-11-06 21:58:43,304 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-06 21:58:43,305 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-06 21:58:43,317 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-06 21:58:43,377 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-06 21:58:43,377 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-06 21:58:43,378 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2130291043] [2023-11-06 21:58:43,378 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2130291043] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-06 21:58:43,378 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-06 21:58:43,378 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-06 21:58:43,378 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [800863047] [2023-11-06 21:58:43,378 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-06 21:58:43,379 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-06 21:58:43,379 INFO L145 PredicateUnifier]: Initialized classic predicate unifier [2023-11-06 21:58:43,379 INFO L85 PathProgramCache]: Analyzing trace with hash -2131409869, now seen corresponding path program 1 times [2023-11-06 21:58:43,379 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-06 21:58:43,379 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [105242011] [2023-11-06 21:58:43,379 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-06 21:58:43,380 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-06 21:58:43,394 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-06 21:58:43,428 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-06 21:58:43,428 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-06 21:58:43,429 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [105242011] [2023-11-06 21:58:43,429 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [105242011] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-06 21:58:43,429 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-06 21:58:43,429 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-06 21:58:43,429 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1043764443] [2023-11-06 21:58:43,429 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-06 21:58:43,430 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-06 21:58:43,430 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-06 21:58:43,430 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2023-11-06 21:58:43,430 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2023-11-06 21:58:43,431 INFO L87 Difference]: Start difference. First operand 1703 states and 2510 transitions. cyclomatic complexity: 809 Second operand has 4 states, 4 states have (on average 26.0) internal successors, (104), 3 states have internal predecessors, (104), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-06 21:58:43,729 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-06 21:58:43,729 INFO L93 Difference]: Finished difference Result 4644 states and 6747 transitions. [2023-11-06 21:58:43,729 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 4644 states and 6747 transitions. [2023-11-06 21:58:43,765 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 4374 [2023-11-06 21:58:43,804 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 4644 states to 4644 states and 6747 transitions. [2023-11-06 21:58:43,805 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 4644 [2023-11-06 21:58:43,810 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 4644 [2023-11-06 21:58:43,810 INFO L73 IsDeterministic]: Start isDeterministic. Operand 4644 states and 6747 transitions. [2023-11-06 21:58:43,818 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-06 21:58:43,818 INFO L218 hiAutomatonCegarLoop]: Abstraction has 4644 states and 6747 transitions. [2023-11-06 21:58:43,825 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 4644 states and 6747 transitions. [2023-11-06 21:58:43,911 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 4644 to 4396. [2023-11-06 21:58:43,920 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 4396 states, 4396 states have (on average 1.4574613284804367) internal successors, (6407), 4395 states have internal predecessors, (6407), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-06 21:58:43,938 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 4396 states to 4396 states and 6407 transitions. [2023-11-06 21:58:43,938 INFO L240 hiAutomatonCegarLoop]: Abstraction has 4396 states and 6407 transitions. [2023-11-06 21:58:43,939 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2023-11-06 21:58:43,939 INFO L428 stractBuchiCegarLoop]: Abstraction has 4396 states and 6407 transitions. [2023-11-06 21:58:43,939 INFO L335 stractBuchiCegarLoop]: ======== Iteration 12 ============ [2023-11-06 21:58:43,939 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 4396 states and 6407 transitions. [2023-11-06 21:58:43,963 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 4260 [2023-11-06 21:58:43,963 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-06 21:58:43,963 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-06 21:58:43,965 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-06 21:58:43,965 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-06 21:58:43,965 INFO L748 eck$LassoCheckResult]: Stem: 26131#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2; 26132#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~10#1;havoc main_~__retres1~10#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; 26827#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret24#1, start_simulation_#t~ret25#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 26828#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 26829#L581 assume 1 == ~m_i~0;~m_st~0 := 0; 26248#L581-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 26249#L586-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 26823#L591-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 26816#L596-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 26329#L601-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 26330#L606-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 26576#L611-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 26577#L616-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 26416#L621-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 26417#L838 assume !(0 == ~M_E~0); 26586#L838-2 assume !(0 == ~T1_E~0); 25928#L843-1 assume !(0 == ~T2_E~0); 25929#L848-1 assume !(0 == ~T3_E~0); 26050#L853-1 assume !(0 == ~T4_E~0); 26403#L858-1 assume !(0 == ~T5_E~0); 25877#L863-1 assume !(0 == ~T6_E~0); 25878#L868-1 assume !(0 == ~T7_E~0); 26875#L873-1 assume !(0 == ~T8_E~0); 26872#L878-1 assume !(0 == ~E_1~0); 26848#L883-1 assume !(0 == ~E_2~0); 26849#L888-1 assume !(0 == ~E_3~0); 26545#L893-1 assume !(0 == ~E_4~0); 26546#L898-1 assume !(0 == ~E_5~0); 26895#L903-1 assume !(0 == ~E_6~0); 26846#L908-1 assume !(0 == ~E_7~0); 26691#L913-1 assume !(0 == ~E_8~0); 25942#L918-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 25943#L402 assume !(1 == ~m_pc~0); 26383#L402-2 is_master_triggered_~__retres1~0#1 := 0; 26075#L413 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 26076#is_master_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 26335#L1035 assume !(0 != activate_threads_~tmp~1#1); 26336#L1035-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 26391#L421 assume !(1 == ~t1_pc~0); 26843#L421-2 is_transmit1_triggered_~__retres1~1#1 := 0; 26877#L432 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 25944#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 25945#L1043 assume !(0 != activate_threads_~tmp___0~0#1); 26450#L1043-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 26886#L440 assume 1 == ~t2_pc~0; 25912#L441 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 25913#L451 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 26085#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 26274#L1051 assume !(0 != activate_threads_~tmp___1~0#1); 26713#L1051-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 26280#L459 assume !(1 == ~t3_pc~0); 26281#L459-2 is_transmit3_triggered_~__retres1~3#1 := 0; 26839#L470 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 25899#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 25900#L1059 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 26069#L1059-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 26079#L478 assume 1 == ~t4_pc~0; 26080#L479 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 26550#L489 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 26022#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 26023#L1067 assume !(0 != activate_threads_~tmp___3~0#1); 25984#L1067-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 25985#L497 assume !(1 == ~t5_pc~0); 26033#L497-2 is_transmit5_triggered_~__retres1~5#1 := 0; 26034#L508 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 26629#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 26757#L1075 assume !(0 != activate_threads_~tmp___4~0#1); 26834#L1075-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 26835#L516 assume 1 == ~t6_pc~0; 26926#L517 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 26575#L527 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 26257#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 26125#L1083 assume !(0 != activate_threads_~tmp___5~0#1); 26126#L1083-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 26564#L535 assume !(1 == ~t7_pc~0); 26565#L535-2 is_transmit7_triggered_~__retres1~7#1 := 0; 26644#L546 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 26645#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 26682#L1091 assume !(0 != activate_threads_~tmp___6~0#1); 26671#L1091-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 26672#L554 assume 1 == ~t8_pc~0; 26605#L555 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 25902#L565 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 26706#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 26210#L1099 assume !(0 != activate_threads_~tmp___7~0#1); 26211#L1099-2 havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 25888#L931 assume !(1 == ~M_E~0); 25889#L931-2 assume 1 == ~T1_E~0;~T1_E~0 := 2; 26866#L936-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 26902#L941-1 assume !(1 == ~T3_E~0); 26392#L946-1 assume !(1 == ~T4_E~0); 26393#L951-1 assume !(1 == ~T5_E~0); 26141#L956-1 assume !(1 == ~T6_E~0); 26142#L961-1 assume !(1 == ~T7_E~0); 26547#L966-1 assume !(1 == ~T8_E~0); 26548#L971-1 assume 1 == ~E_1~0;~E_1~0 := 2; 26676#L976-1 assume !(1 == ~E_2~0); 26634#L981-1 assume !(1 == ~E_3~0); 26396#L986-1 assume !(1 == ~E_4~0); 26166#L991-1 assume !(1 == ~E_5~0); 26167#L996-1 assume !(1 == ~E_6~0); 26881#L1001-1 assume !(1 == ~E_7~0); 26599#L1006-1 assume !(1 == ~E_8~0); 26600#L1011-1 assume { :end_inline_reset_delta_events } true; 29019#L1272-2 [2023-11-06 21:58:43,966 INFO L750 eck$LassoCheckResult]: Loop: 29019#L1272-2 assume !false; 28844#L1273 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 28843#L813-1 assume !false; 28842#L692 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 28840#L634 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 28831#L681 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 28830#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 26788#L696 assume !(0 != eval_~tmp~0#1); 26790#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 29865#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 29864#L838-3 assume 0 == ~M_E~0;~M_E~0 := 1; 29863#L838-5 assume !(0 == ~T1_E~0); 29862#L843-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 29861#L848-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 29860#L853-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 29859#L858-3 assume !(0 == ~T5_E~0); 29858#L863-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 29857#L868-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 29855#L873-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 29853#L878-3 assume !(0 == ~E_1~0); 29851#L883-3 assume 0 == ~E_2~0;~E_2~0 := 1; 29849#L888-3 assume 0 == ~E_3~0;~E_3~0 := 1; 29847#L893-3 assume 0 == ~E_4~0;~E_4~0 := 1; 29845#L898-3 assume !(0 == ~E_5~0); 29843#L903-3 assume 0 == ~E_6~0;~E_6~0 := 1; 29841#L908-3 assume 0 == ~E_7~0;~E_7~0 := 1; 29839#L913-3 assume 0 == ~E_8~0;~E_8~0 := 1; 29837#L918-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 29835#L402-27 assume !(1 == ~m_pc~0); 29833#L402-29 is_master_triggered_~__retres1~0#1 := 0; 29831#L413-9 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 29828#is_master_triggered_returnLabel#10 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 29826#L1035-27 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 29824#L1035-29 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 29822#L421-27 assume !(1 == ~t1_pc~0); 29820#L421-29 is_transmit1_triggered_~__retres1~1#1 := 0; 29818#L432-9 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 29815#is_transmit1_triggered_returnLabel#10 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 29813#L1043-27 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 29811#L1043-29 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 29809#L440-27 assume 1 == ~t2_pc~0; 29806#L441-9 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 29804#L451-9 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 29801#is_transmit2_triggered_returnLabel#10 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 29799#L1051-27 assume !(0 != activate_threads_~tmp___1~0#1); 29797#L1051-29 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 29795#L459-27 assume 1 == ~t3_pc~0; 29792#L460-9 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 29790#L470-9 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 29787#is_transmit3_triggered_returnLabel#10 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 29785#L1059-27 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 29783#L1059-29 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 29781#L478-27 assume 1 == ~t4_pc~0; 29778#L479-9 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 29776#L489-9 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 29773#is_transmit4_triggered_returnLabel#10 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 29771#L1067-27 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 29769#L1067-29 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 29767#L497-27 assume 1 == ~t5_pc~0; 29764#L498-9 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 29762#L508-9 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 29759#is_transmit5_triggered_returnLabel#10 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 29757#L1075-27 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 29755#L1075-29 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 29753#L516-27 assume !(1 == ~t6_pc~0); 29750#L516-29 is_transmit6_triggered_~__retres1~6#1 := 0; 29748#L527-9 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 29745#is_transmit6_triggered_returnLabel#10 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 29743#L1083-27 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 29741#L1083-29 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 29739#L535-27 assume 1 == ~t7_pc~0; 29736#L536-9 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 29734#L546-9 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 29732#is_transmit7_triggered_returnLabel#10 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 29730#L1091-27 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 29729#L1091-29 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 29727#L554-27 assume !(1 == ~t8_pc~0); 29724#L554-29 is_transmit8_triggered_~__retres1~8#1 := 0; 29722#L565-9 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 29720#is_transmit8_triggered_returnLabel#10 activate_threads_#t~ret22#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 29718#L1099-27 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 29716#L1099-29 havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 29714#L931-3 assume 1 == ~M_E~0;~M_E~0 := 2; 29712#L931-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 29710#L936-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 26298#L941-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 29708#L946-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 29706#L951-3 assume !(1 == ~T5_E~0); 29704#L956-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 29703#L961-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 29702#L966-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 29701#L971-3 assume 1 == ~E_1~0;~E_1~0 := 2; 29700#L976-3 assume 1 == ~E_2~0;~E_2~0 := 2; 29699#L981-3 assume 1 == ~E_3~0;~E_3~0 := 2; 29698#L986-3 assume 1 == ~E_4~0;~E_4~0 := 2; 29697#L991-3 assume !(1 == ~E_5~0); 25940#L996-3 assume 1 == ~E_6~0;~E_6~0 := 2; 29696#L1001-3 assume 1 == ~E_7~0;~E_7~0 := 2; 29695#L1006-3 assume 1 == ~E_8~0;~E_8~0 := 2; 29694#L1011-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 29692#L634-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 29684#L681-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 29683#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret24#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret24#1;havoc start_simulation_#t~ret24#1; 29681#L1291 assume !(0 == start_simulation_~tmp~3#1); 29679#L1291-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 26410#L634-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 26002#L681-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 28032#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret23#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret23#1;havoc stop_simulation_#t~ret23#1; 26854#L1246 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 26375#L1253 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 26376#stop_simulation_returnLabel#1 start_simulation_#t~ret25#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret25#1;havoc start_simulation_#t~ret25#1; 29020#L1304 assume !(0 != start_simulation_~tmp___0~1#1); 29019#L1272-2 [2023-11-06 21:58:43,967 INFO L145 PredicateUnifier]: Initialized classic predicate unifier [2023-11-06 21:58:43,967 INFO L85 PathProgramCache]: Analyzing trace with hash 493551747, now seen corresponding path program 1 times [2023-11-06 21:58:43,967 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-06 21:58:43,967 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [784070690] [2023-11-06 21:58:43,967 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-06 21:58:43,967 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-06 21:58:43,983 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-06 21:58:44,057 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-06 21:58:44,057 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-06 21:58:44,058 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [784070690] [2023-11-06 21:58:44,058 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [784070690] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-06 21:58:44,058 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-06 21:58:44,058 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-06 21:58:44,058 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1013067762] [2023-11-06 21:58:44,058 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-06 21:58:44,059 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-06 21:58:44,059 INFO L145 PredicateUnifier]: Initialized classic predicate unifier [2023-11-06 21:58:44,059 INFO L85 PathProgramCache]: Analyzing trace with hash -1471568909, now seen corresponding path program 1 times [2023-11-06 21:58:44,059 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-06 21:58:44,059 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [351630461] [2023-11-06 21:58:44,060 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-06 21:58:44,060 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-06 21:58:44,074 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-06 21:58:44,107 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-06 21:58:44,107 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-06 21:58:44,107 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [351630461] [2023-11-06 21:58:44,107 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [351630461] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-06 21:58:44,108 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-06 21:58:44,108 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-06 21:58:44,108 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1652687233] [2023-11-06 21:58:44,108 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-06 21:58:44,108 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-06 21:58:44,109 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-06 21:58:44,109 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2023-11-06 21:58:44,109 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2023-11-06 21:58:44,109 INFO L87 Difference]: Start difference. First operand 4396 states and 6407 transitions. cyclomatic complexity: 2015 Second operand has 4 states, 4 states have (on average 26.0) internal successors, (104), 3 states have internal predecessors, (104), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-06 21:58:44,491 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-06 21:58:44,491 INFO L93 Difference]: Finished difference Result 12317 states and 17768 transitions. [2023-11-06 21:58:44,491 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 12317 states and 17768 transitions. [2023-11-06 21:58:44,584 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 11868 [2023-11-06 21:58:44,669 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 12317 states to 12317 states and 17768 transitions. [2023-11-06 21:58:44,670 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 12317 [2023-11-06 21:58:44,685 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 12317 [2023-11-06 21:58:44,685 INFO L73 IsDeterministic]: Start isDeterministic. Operand 12317 states and 17768 transitions. [2023-11-06 21:58:44,706 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-06 21:58:44,706 INFO L218 hiAutomatonCegarLoop]: Abstraction has 12317 states and 17768 transitions. [2023-11-06 21:58:44,722 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 12317 states and 17768 transitions. [2023-11-06 21:58:44,951 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 12317 to 11723. [2023-11-06 21:58:44,982 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 11723 states, 11723 states have (on average 1.4468992578691462) internal successors, (16962), 11722 states have internal predecessors, (16962), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-06 21:58:45,025 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 11723 states to 11723 states and 16962 transitions. [2023-11-06 21:58:45,025 INFO L240 hiAutomatonCegarLoop]: Abstraction has 11723 states and 16962 transitions. [2023-11-06 21:58:45,025 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2023-11-06 21:58:45,026 INFO L428 stractBuchiCegarLoop]: Abstraction has 11723 states and 16962 transitions. [2023-11-06 21:58:45,026 INFO L335 stractBuchiCegarLoop]: ======== Iteration 13 ============ [2023-11-06 21:58:45,026 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 11723 states and 16962 transitions. [2023-11-06 21:58:45,112 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 11568 [2023-11-06 21:58:45,113 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-06 21:58:45,113 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-06 21:58:45,115 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-06 21:58:45,115 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-06 21:58:45,115 INFO L748 eck$LassoCheckResult]: Stem: 42851#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2; 42852#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~10#1;havoc main_~__retres1~10#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; 43551#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret24#1, start_simulation_#t~ret25#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 43552#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 43553#L581 assume 1 == ~m_i~0;~m_st~0 := 0; 42965#L581-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 42966#L586-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 43548#L591-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 43541#L596-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 43047#L601-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 43048#L606-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 43301#L611-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 43302#L616-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 43134#L621-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 43135#L838 assume !(0 == ~M_E~0); 43310#L838-2 assume !(0 == ~T1_E~0); 42648#L843-1 assume !(0 == ~T2_E~0); 42649#L848-1 assume !(0 == ~T3_E~0); 42768#L853-1 assume !(0 == ~T4_E~0); 43123#L858-1 assume !(0 == ~T5_E~0); 42602#L863-1 assume !(0 == ~T6_E~0); 42603#L868-1 assume !(0 == ~T7_E~0); 43603#L873-1 assume !(0 == ~T8_E~0); 43601#L878-1 assume !(0 == ~E_1~0); 43578#L883-1 assume !(0 == ~E_2~0); 43579#L888-1 assume !(0 == ~E_3~0); 43271#L893-1 assume !(0 == ~E_4~0); 43272#L898-1 assume !(0 == ~E_5~0); 43626#L903-1 assume !(0 == ~E_6~0); 43575#L908-1 assume !(0 == ~E_7~0); 43417#L913-1 assume !(0 == ~E_8~0); 42662#L918-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 42663#L402 assume !(1 == ~m_pc~0); 43100#L402-2 is_master_triggered_~__retres1~0#1 := 0; 42793#L413 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 42794#is_master_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 43054#L1035 assume !(0 != activate_threads_~tmp~1#1); 43055#L1035-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 43108#L421 assume !(1 == ~t1_pc~0); 43571#L421-2 is_transmit1_triggered_~__retres1~1#1 := 0; 43608#L432 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 42664#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 42665#L1043 assume !(0 != activate_threads_~tmp___0~0#1); 43170#L1043-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 43617#L440 assume !(1 == ~t2_pc~0); 43659#L440-2 is_transmit2_triggered_~__retres1~2#1 := 0; 42803#L451 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 42804#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 42991#L1051 assume !(0 != activate_threads_~tmp___1~0#1); 43436#L1051-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 42999#L459 assume !(1 == ~t3_pc~0); 43000#L459-2 is_transmit3_triggered_~__retres1~3#1 := 0; 43566#L470 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 42622#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 42623#L1059 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 42787#L1059-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 42797#L478 assume 1 == ~t4_pc~0; 42798#L479 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 43275#L489 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 42740#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 42741#L1067 assume !(0 != activate_threads_~tmp___3~0#1); 42704#L1067-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 42705#L497 assume !(1 == ~t5_pc~0); 42751#L497-2 is_transmit5_triggered_~__retres1~5#1 := 0; 42752#L508 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 43353#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 43482#L1075 assume !(0 != activate_threads_~tmp___4~0#1); 43559#L1075-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 43560#L516 assume 1 == ~t6_pc~0; 43652#L517 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 43300#L527 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 42975#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 42845#L1083 assume !(0 != activate_threads_~tmp___5~0#1); 42846#L1083-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 43290#L535 assume !(1 == ~t7_pc~0); 43291#L535-2 is_transmit7_triggered_~__retres1~7#1 := 0; 43370#L546 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 43371#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 43407#L1091 assume !(0 != activate_threads_~tmp___6~0#1); 43395#L1091-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 43396#L554 assume 1 == ~t8_pc~0; 43327#L555 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 42625#L565 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 43430#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 42933#L1099 assume !(0 != activate_threads_~tmp___7~0#1); 42934#L1099-2 havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 42611#L931 assume !(1 == ~M_E~0); 42612#L931-2 assume 1 == ~T1_E~0;~T1_E~0 := 2; 43593#L936-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 43635#L941-1 assume !(1 == ~T3_E~0); 43109#L946-1 assume !(1 == ~T4_E~0); 43110#L951-1 assume !(1 == ~T5_E~0); 42860#L956-1 assume !(1 == ~T6_E~0); 42861#L961-1 assume !(1 == ~T7_E~0); 43273#L966-1 assume !(1 == ~T8_E~0); 43274#L971-1 assume 1 == ~E_1~0;~E_1~0 := 2; 43641#L976-1 assume !(1 == ~E_2~0); 43642#L981-1 assume !(1 == ~E_3~0); 43113#L986-1 assume !(1 == ~E_4~0); 43114#L991-1 assume !(1 == ~E_5~0); 42886#L996-1 assume !(1 == ~E_6~0); 43647#L1001-1 assume !(1 == ~E_7~0); 43321#L1006-1 assume !(1 == ~E_8~0); 43322#L1011-1 assume { :end_inline_reset_delta_events } true; 49532#L1272-2 [2023-11-06 21:58:45,116 INFO L750 eck$LassoCheckResult]: Loop: 49532#L1272-2 assume !false; 49533#L1273 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 49517#L813-1 assume !false; 49518#L692 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 49478#L634 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 49465#L681 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 49457#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 49446#L696 assume !(0 != eval_~tmp~0#1); 49448#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 50568#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 50566#L838-3 assume 0 == ~M_E~0;~M_E~0 := 1; 50564#L838-5 assume !(0 == ~T1_E~0); 50562#L843-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 50559#L848-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 50557#L853-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 50555#L858-3 assume !(0 == ~T5_E~0); 50553#L863-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 50552#L868-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 50551#L873-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 50550#L878-3 assume !(0 == ~E_1~0); 50549#L883-3 assume 0 == ~E_2~0;~E_2~0 := 1; 50548#L888-3 assume 0 == ~E_3~0;~E_3~0 := 1; 50547#L893-3 assume 0 == ~E_4~0;~E_4~0 := 1; 50546#L898-3 assume !(0 == ~E_5~0); 50545#L903-3 assume 0 == ~E_6~0;~E_6~0 := 1; 50544#L908-3 assume 0 == ~E_7~0;~E_7~0 := 1; 50542#L913-3 assume 0 == ~E_8~0;~E_8~0 := 1; 50540#L918-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 50538#L402-27 assume !(1 == ~m_pc~0); 50536#L402-29 is_master_triggered_~__retres1~0#1 := 0; 50534#L413-9 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 50532#is_master_triggered_returnLabel#10 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 50530#L1035-27 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 50528#L1035-29 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 50526#L421-27 assume !(1 == ~t1_pc~0); 50524#L421-29 is_transmit1_triggered_~__retres1~1#1 := 0; 50522#L432-9 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 50520#is_transmit1_triggered_returnLabel#10 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 50518#L1043-27 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 50516#L1043-29 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 50514#L440-27 assume !(1 == ~t2_pc~0); 50512#L440-29 is_transmit2_triggered_~__retres1~2#1 := 0; 50510#L451-9 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 50508#is_transmit2_triggered_returnLabel#10 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 50506#L1051-27 assume !(0 != activate_threads_~tmp___1~0#1); 50503#L1051-29 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 50501#L459-27 assume 1 == ~t3_pc~0; 50498#L460-9 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 50496#L470-9 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 50494#is_transmit3_triggered_returnLabel#10 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 50492#L1059-27 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 50489#L1059-29 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 50487#L478-27 assume 1 == ~t4_pc~0; 50484#L479-9 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 50482#L489-9 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 50481#is_transmit4_triggered_returnLabel#10 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 50480#L1067-27 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 50479#L1067-29 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 50478#L497-27 assume 1 == ~t5_pc~0; 50476#L498-9 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 50475#L508-9 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 50466#is_transmit5_triggered_returnLabel#10 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 50464#L1075-27 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 50462#L1075-29 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 50458#L516-27 assume !(1 == ~t6_pc~0); 50455#L516-29 is_transmit6_triggered_~__retres1~6#1 := 0; 50454#L527-9 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 50453#is_transmit6_triggered_returnLabel#10 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 50443#L1083-27 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 50441#L1083-29 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 50439#L535-27 assume 1 == ~t7_pc~0; 50434#L536-9 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 50432#L546-9 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 50430#is_transmit7_triggered_returnLabel#10 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 50428#L1091-27 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 50426#L1091-29 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 50424#L554-27 assume !(1 == ~t8_pc~0); 50421#L554-29 is_transmit8_triggered_~__retres1~8#1 := 0; 50419#L565-9 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 50417#is_transmit8_triggered_returnLabel#10 activate_threads_#t~ret22#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 50415#L1099-27 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 50413#L1099-29 havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 50411#L931-3 assume 1 == ~M_E~0;~M_E~0 := 2; 50409#L931-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 50407#L936-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 50131#L941-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 50403#L946-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 50401#L951-3 assume !(1 == ~T5_E~0); 50399#L956-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 50397#L961-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 50395#L966-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 50393#L971-3 assume 1 == ~E_1~0;~E_1~0 := 2; 50390#L976-3 assume 1 == ~E_2~0;~E_2~0 := 2; 50296#L981-3 assume 1 == ~E_3~0;~E_3~0 := 2; 50291#L986-3 assume 1 == ~E_4~0;~E_4~0 := 2; 50074#L991-3 assume !(1 == ~E_5~0); 50067#L996-3 assume 1 == ~E_6~0;~E_6~0 := 2; 50062#L1001-3 assume 1 == ~E_7~0;~E_7~0 := 2; 50049#L1006-3 assume 1 == ~E_8~0;~E_8~0 := 2; 50046#L1011-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 49932#L634-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 49918#L681-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 49912#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret24#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret24#1;havoc start_simulation_#t~ret24#1; 49905#L1291 assume !(0 == start_simulation_~tmp~3#1); 49897#L1291-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 49754#L634-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 49745#L681-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 49741#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret23#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret23#1;havoc stop_simulation_#t~ret23#1; 49679#L1246 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 49661#L1253 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 49634#stop_simulation_returnLabel#1 start_simulation_#t~ret25#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret25#1;havoc start_simulation_#t~ret25#1; 49635#L1304 assume !(0 != start_simulation_~tmp___0~1#1); 49532#L1272-2 [2023-11-06 21:58:45,117 INFO L145 PredicateUnifier]: Initialized classic predicate unifier [2023-11-06 21:58:45,117 INFO L85 PathProgramCache]: Analyzing trace with hash -1412932446, now seen corresponding path program 1 times [2023-11-06 21:58:45,117 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-06 21:58:45,118 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [621341375] [2023-11-06 21:58:45,118 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-06 21:58:45,118 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-06 21:58:45,134 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-06 21:58:45,196 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-06 21:58:45,196 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-06 21:58:45,197 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [621341375] [2023-11-06 21:58:45,197 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [621341375] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-06 21:58:45,197 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-06 21:58:45,197 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2023-11-06 21:58:45,197 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1884061596] [2023-11-06 21:58:45,197 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-06 21:58:45,199 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-06 21:58:45,199 INFO L145 PredicateUnifier]: Initialized classic predicate unifier [2023-11-06 21:58:45,199 INFO L85 PathProgramCache]: Analyzing trace with hash -1956984430, now seen corresponding path program 1 times [2023-11-06 21:58:45,199 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-06 21:58:45,200 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1089333776] [2023-11-06 21:58:45,200 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-06 21:58:45,200 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-06 21:58:45,214 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-06 21:58:45,248 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-06 21:58:45,248 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-06 21:58:45,249 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1089333776] [2023-11-06 21:58:45,249 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1089333776] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-06 21:58:45,249 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-06 21:58:45,249 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-06 21:58:45,249 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [58836702] [2023-11-06 21:58:45,250 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-06 21:58:45,250 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-06 21:58:45,250 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-06 21:58:45,251 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2023-11-06 21:58:45,251 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2023-11-06 21:58:45,252 INFO L87 Difference]: Start difference. First operand 11723 states and 16962 transitions. cyclomatic complexity: 5247 Second operand has 5 states, 5 states have (on average 20.8) internal successors, (104), 5 states have internal predecessors, (104), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-06 21:58:45,642 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-06 21:58:45,642 INFO L93 Difference]: Finished difference Result 27950 states and 40066 transitions. [2023-11-06 21:58:45,642 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 27950 states and 40066 transitions. [2023-11-06 21:58:45,923 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 27657 [2023-11-06 21:58:46,034 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 27950 states to 27950 states and 40066 transitions. [2023-11-06 21:58:46,035 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 27950 [2023-11-06 21:58:46,065 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 27950 [2023-11-06 21:58:46,066 INFO L73 IsDeterministic]: Start isDeterministic. Operand 27950 states and 40066 transitions. [2023-11-06 21:58:46,101 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-06 21:58:46,101 INFO L218 hiAutomatonCegarLoop]: Abstraction has 27950 states and 40066 transitions. [2023-11-06 21:58:46,138 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 27950 states and 40066 transitions. [2023-11-06 21:58:46,562 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 27950 to 12137. [2023-11-06 21:58:46,580 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 12137 states, 12137 states have (on average 1.4316552690121118) internal successors, (17376), 12136 states have internal predecessors, (17376), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-06 21:58:46,615 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 12137 states to 12137 states and 17376 transitions. [2023-11-06 21:58:46,616 INFO L240 hiAutomatonCegarLoop]: Abstraction has 12137 states and 17376 transitions. [2023-11-06 21:58:46,616 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2023-11-06 21:58:46,617 INFO L428 stractBuchiCegarLoop]: Abstraction has 12137 states and 17376 transitions. [2023-11-06 21:58:46,617 INFO L335 stractBuchiCegarLoop]: ======== Iteration 14 ============ [2023-11-06 21:58:46,618 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 12137 states and 17376 transitions. [2023-11-06 21:58:46,734 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 11979 [2023-11-06 21:58:46,735 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-06 21:58:46,735 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-06 21:58:46,737 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-06 21:58:46,737 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-06 21:58:46,738 INFO L748 eck$LassoCheckResult]: Stem: 82537#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2; 82538#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~10#1;havoc main_~__retres1~10#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; 83349#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret24#1, start_simulation_#t~ret25#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 83350#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 83352#L581 assume 1 == ~m_i~0;~m_st~0 := 0; 82661#L581-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 82662#L586-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 83341#L591-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 83324#L596-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 82752#L601-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 82753#L606-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 83037#L611-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 83038#L616-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 82841#L621-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 82842#L838 assume !(0 == ~M_E~0); 83048#L838-2 assume !(0 == ~T1_E~0); 82332#L843-1 assume !(0 == ~T2_E~0); 82333#L848-1 assume !(0 == ~T3_E~0); 82452#L853-1 assume !(0 == ~T4_E~0); 82830#L858-1 assume !(0 == ~T5_E~0); 82286#L863-1 assume !(0 == ~T6_E~0); 82287#L868-1 assume !(0 == ~T7_E~0); 83437#L873-1 assume !(0 == ~T8_E~0); 83433#L878-1 assume !(0 == ~E_1~0); 83390#L883-1 assume !(0 == ~E_2~0); 83391#L888-1 assume !(0 == ~E_3~0); 83001#L893-1 assume !(0 == ~E_4~0); 83002#L898-1 assume !(0 == ~E_5~0); 83465#L903-1 assume !(0 == ~E_6~0); 83384#L908-1 assume !(0 == ~E_7~0); 83168#L913-1 assume !(0 == ~E_8~0); 82345#L918-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 82346#L402 assume !(1 == ~m_pc~0); 82805#L402-2 is_master_triggered_~__retres1~0#1 := 0; 82478#L413 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 82479#is_master_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 82758#L1035 assume !(0 != activate_threads_~tmp~1#1); 82759#L1035-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 82816#L421 assume !(1 == ~t1_pc~0); 83378#L421-2 is_transmit1_triggered_~__retres1~1#1 := 0; 83443#L432 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 82347#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 82348#L1043 assume !(0 != activate_threads_~tmp___0~0#1); 82875#L1043-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 83459#L440 assume !(1 == ~t2_pc~0); 83530#L440-2 is_transmit2_triggered_~__retres1~2#1 := 0; 82488#L451 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 82489#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 82690#L1051 assume !(0 != activate_threads_~tmp___1~0#1); 83190#L1051-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 82698#L459 assume !(1 == ~t3_pc~0); 82699#L459-2 is_transmit3_triggered_~__retres1~3#1 := 0; 83373#L470 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 83457#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 82471#L1059 assume !(0 != activate_threads_~tmp___2~0#1); 82472#L1059-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 82482#L478 assume 1 == ~t4_pc~0; 82483#L479 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 83005#L489 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 82424#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 82425#L1067 assume !(0 != activate_threads_~tmp___3~0#1); 82387#L1067-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 82388#L497 assume !(1 == ~t5_pc~0); 82435#L497-2 is_transmit5_triggered_~__retres1~5#1 := 0; 82436#L508 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 83101#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 83248#L1075 assume !(0 != activate_threads_~tmp___4~0#1); 83364#L1075-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 83365#L516 assume 1 == ~t6_pc~0; 83521#L517 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 83036#L527 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 82671#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 82530#L1083 assume !(0 != activate_threads_~tmp___5~0#1); 82531#L1083-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 83024#L535 assume !(1 == ~t7_pc~0); 83025#L535-2 is_transmit7_triggered_~__retres1~7#1 := 0; 83119#L546 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 83120#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 83159#L1091 assume !(0 != activate_threads_~tmp___6~0#1); 83145#L1091-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 83146#L554 assume 1 == ~t8_pc~0; 83068#L555 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 82311#L565 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 83181#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 82626#L1099 assume !(0 != activate_threads_~tmp___7~0#1); 82627#L1099-2 havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 82297#L931 assume !(1 == ~M_E~0); 82298#L931-2 assume 1 == ~T1_E~0;~T1_E~0 := 2; 83416#L936-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 83481#L941-1 assume !(1 == ~T3_E~0); 88885#L946-1 assume !(1 == ~T4_E~0); 88884#L951-1 assume !(1 == ~T5_E~0); 88883#L956-1 assume !(1 == ~T6_E~0); 88882#L961-1 assume !(1 == ~T7_E~0); 88881#L966-1 assume !(1 == ~T8_E~0); 88880#L971-1 assume 1 == ~E_1~0;~E_1~0 := 2; 88879#L976-1 assume !(1 == ~E_2~0); 88878#L981-1 assume !(1 == ~E_3~0); 88877#L986-1 assume !(1 == ~E_4~0); 88876#L991-1 assume !(1 == ~E_5~0); 82576#L996-1 assume !(1 == ~E_6~0); 88875#L1001-1 assume !(1 == ~E_7~0); 88874#L1006-1 assume !(1 == ~E_8~0); 88872#L1011-1 assume { :end_inline_reset_delta_events } true; 88869#L1272-2 [2023-11-06 21:58:46,738 INFO L750 eck$LassoCheckResult]: Loop: 88869#L1272-2 assume !false; 88847#L1273 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 88846#L813-1 assume !false; 88845#L692 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 88600#L634 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 88593#L681 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 88583#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 88584#L696 assume !(0 != eval_~tmp~0#1); 88738#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 90207#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 90206#L838-3 assume 0 == ~M_E~0;~M_E~0 := 1; 90205#L838-5 assume !(0 == ~T1_E~0); 90204#L843-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 90203#L848-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 90202#L853-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 90201#L858-3 assume !(0 == ~T5_E~0); 90200#L863-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 90199#L868-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 90198#L873-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 90197#L878-3 assume !(0 == ~E_1~0); 90196#L883-3 assume 0 == ~E_2~0;~E_2~0 := 1; 90195#L888-3 assume 0 == ~E_3~0;~E_3~0 := 1; 90194#L893-3 assume 0 == ~E_4~0;~E_4~0 := 1; 90193#L898-3 assume !(0 == ~E_5~0); 90192#L903-3 assume 0 == ~E_6~0;~E_6~0 := 1; 90191#L908-3 assume 0 == ~E_7~0;~E_7~0 := 1; 90190#L913-3 assume 0 == ~E_8~0;~E_8~0 := 1; 90189#L918-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 90188#L402-27 assume !(1 == ~m_pc~0); 90187#L402-29 is_master_triggered_~__retres1~0#1 := 0; 90186#L413-9 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 90185#is_master_triggered_returnLabel#10 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 90184#L1035-27 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 90183#L1035-29 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 90182#L421-27 assume !(1 == ~t1_pc~0); 90181#L421-29 is_transmit1_triggered_~__retres1~1#1 := 0; 90180#L432-9 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 90179#is_transmit1_triggered_returnLabel#10 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 90178#L1043-27 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 90177#L1043-29 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 90176#L440-27 assume !(1 == ~t2_pc~0); 90175#L440-29 is_transmit2_triggered_~__retres1~2#1 := 0; 90174#L451-9 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 90173#is_transmit2_triggered_returnLabel#10 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 90172#L1051-27 assume !(0 != activate_threads_~tmp___1~0#1); 90171#L1051-29 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 90170#L459-27 assume !(1 == ~t3_pc~0); 90169#L459-29 is_transmit3_triggered_~__retres1~3#1 := 0; 90167#L470-9 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 90165#is_transmit3_triggered_returnLabel#10 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 90163#L1059-27 assume !(0 != activate_threads_~tmp___2~0#1); 90158#L1059-29 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 90154#L478-27 assume !(1 == ~t4_pc~0); 90105#L478-29 is_transmit4_triggered_~__retres1~4#1 := 0; 90100#L489-9 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 90096#is_transmit4_triggered_returnLabel#10 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 90091#L1067-27 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 90086#L1067-29 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 90081#L497-27 assume !(1 == ~t5_pc~0); 90077#L497-29 is_transmit5_triggered_~__retres1~5#1 := 0; 89565#L508-9 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 89562#is_transmit5_triggered_returnLabel#10 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 89518#L1075-27 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 89516#L1075-29 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 89514#L516-27 assume 1 == ~t6_pc~0; 89511#L517-9 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 89508#L527-9 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 89506#is_transmit6_triggered_returnLabel#10 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 89504#L1083-27 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 89502#L1083-29 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 89500#L535-27 assume !(1 == ~t7_pc~0); 89497#L535-29 is_transmit7_triggered_~__retres1~7#1 := 0; 89494#L546-9 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 89492#is_transmit7_triggered_returnLabel#10 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 89490#L1091-27 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 89488#L1091-29 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 89486#L554-27 assume 1 == ~t8_pc~0; 89483#L555-9 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 89480#L565-9 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 89478#is_transmit8_triggered_returnLabel#10 activate_threads_#t~ret22#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 89476#L1099-27 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 88999#L1099-29 havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 88997#L931-3 assume 1 == ~M_E~0;~M_E~0 := 2; 88995#L931-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 88993#L936-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 88991#L941-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 88989#L946-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 88987#L951-3 assume !(1 == ~T5_E~0); 88985#L956-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 88983#L961-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 88981#L966-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 88979#L971-3 assume 1 == ~E_1~0;~E_1~0 := 2; 88977#L976-3 assume 1 == ~E_2~0;~E_2~0 := 2; 88975#L981-3 assume 1 == ~E_3~0;~E_3~0 := 2; 88973#L986-3 assume 1 == ~E_4~0;~E_4~0 := 2; 88969#L991-3 assume !(1 == ~E_5~0); 88968#L996-3 assume 1 == ~E_6~0;~E_6~0 := 2; 88967#L1001-3 assume 1 == ~E_7~0;~E_7~0 := 2; 88966#L1006-3 assume 1 == ~E_8~0;~E_8~0 := 2; 88965#L1011-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 88931#L634-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 88922#L681-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 88920#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret24#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret24#1;havoc start_simulation_#t~ret24#1; 88918#L1291 assume !(0 == start_simulation_~tmp~3#1); 88916#L1291-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 88905#L634-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 88895#L681-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 88893#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret23#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret23#1;havoc stop_simulation_#t~ret23#1; 88889#L1246 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 88887#L1253 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 88886#stop_simulation_returnLabel#1 start_simulation_#t~ret25#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret25#1;havoc start_simulation_#t~ret25#1; 88871#L1304 assume !(0 != start_simulation_~tmp___0~1#1); 88869#L1272-2 [2023-11-06 21:58:46,739 INFO L145 PredicateUnifier]: Initialized classic predicate unifier [2023-11-06 21:58:46,739 INFO L85 PathProgramCache]: Analyzing trace with hash -1894012704, now seen corresponding path program 1 times [2023-11-06 21:58:46,740 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-06 21:58:46,740 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1001607133] [2023-11-06 21:58:46,740 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-06 21:58:46,740 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-06 21:58:46,757 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-06 21:58:46,814 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-06 21:58:46,815 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-06 21:58:46,815 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1001607133] [2023-11-06 21:58:46,816 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1001607133] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-06 21:58:46,816 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-06 21:58:46,816 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2023-11-06 21:58:46,816 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2048884702] [2023-11-06 21:58:46,817 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-06 21:58:46,818 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-06 21:58:46,820 INFO L145 PredicateUnifier]: Initialized classic predicate unifier [2023-11-06 21:58:46,820 INFO L85 PathProgramCache]: Analyzing trace with hash -1787934898, now seen corresponding path program 1 times [2023-11-06 21:58:46,821 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-06 21:58:46,821 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2079046273] [2023-11-06 21:58:46,821 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-06 21:58:46,821 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-06 21:58:46,840 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-06 21:58:46,910 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-06 21:58:46,910 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-06 21:58:46,911 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2079046273] [2023-11-06 21:58:46,911 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2079046273] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-06 21:58:46,911 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-06 21:58:46,911 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2023-11-06 21:58:46,912 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1724811693] [2023-11-06 21:58:46,912 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-06 21:58:46,912 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-06 21:58:46,913 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-06 21:58:46,913 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-06 21:58:46,913 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-06 21:58:46,914 INFO L87 Difference]: Start difference. First operand 12137 states and 17376 transitions. cyclomatic complexity: 5247 Second operand has 3 states, 3 states have (on average 34.666666666666664) internal successors, (104), 2 states have internal predecessors, (104), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-06 21:58:47,111 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-06 21:58:47,111 INFO L93 Difference]: Finished difference Result 23404 states and 33332 transitions. [2023-11-06 21:58:47,111 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 23404 states and 33332 transitions. [2023-11-06 21:58:47,257 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 23181 [2023-11-06 21:58:47,369 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 23404 states to 23404 states and 33332 transitions. [2023-11-06 21:58:47,369 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 23404 [2023-11-06 21:58:47,399 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 23404 [2023-11-06 21:58:47,399 INFO L73 IsDeterministic]: Start isDeterministic. Operand 23404 states and 33332 transitions. [2023-11-06 21:58:47,434 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-06 21:58:47,435 INFO L218 hiAutomatonCegarLoop]: Abstraction has 23404 states and 33332 transitions. [2023-11-06 21:58:47,460 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 23404 states and 33332 transitions. [2023-11-06 21:58:47,983 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 23404 to 23368. [2023-11-06 21:58:48,045 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 23368 states, 23368 states have (on average 1.4248545018829168) internal successors, (33296), 23367 states have internal predecessors, (33296), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-06 21:58:48,124 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 23368 states to 23368 states and 33296 transitions. [2023-11-06 21:58:48,124 INFO L240 hiAutomatonCegarLoop]: Abstraction has 23368 states and 33296 transitions. [2023-11-06 21:58:48,124 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-06 21:58:48,125 INFO L428 stractBuchiCegarLoop]: Abstraction has 23368 states and 33296 transitions. [2023-11-06 21:58:48,125 INFO L335 stractBuchiCegarLoop]: ======== Iteration 15 ============ [2023-11-06 21:58:48,125 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 23368 states and 33296 transitions. [2023-11-06 21:58:48,202 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 23145 [2023-11-06 21:58:48,202 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-06 21:58:48,202 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-06 21:58:48,204 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-06 21:58:48,204 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-06 21:58:48,205 INFO L748 eck$LassoCheckResult]: Stem: 118084#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2; 118085#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~10#1;havoc main_~__retres1~10#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; 118782#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret24#1, start_simulation_#t~ret25#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 118783#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 118785#L581 assume 1 == ~m_i~0;~m_st~0 := 0; 118200#L581-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 118201#L586-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 118779#L591-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 118771#L596-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 118279#L601-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 118280#L606-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 118529#L611-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 118530#L616-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 118367#L621-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 118368#L838 assume !(0 == ~M_E~0); 118538#L838-2 assume !(0 == ~T1_E~0); 117884#L843-1 assume !(0 == ~T2_E~0); 117885#L848-1 assume !(0 == ~T3_E~0); 118003#L853-1 assume !(0 == ~T4_E~0); 118356#L858-1 assume !(0 == ~T5_E~0); 117838#L863-1 assume !(0 == ~T6_E~0); 117839#L868-1 assume !(0 == ~T7_E~0); 118830#L873-1 assume !(0 == ~T8_E~0); 118828#L878-1 assume !(0 == ~E_1~0); 118809#L883-1 assume !(0 == ~E_2~0); 118810#L888-1 assume !(0 == ~E_3~0); 118497#L893-1 assume !(0 == ~E_4~0); 118498#L898-1 assume !(0 == ~E_5~0); 118849#L903-1 assume !(0 == ~E_6~0); 118807#L908-1 assume !(0 == ~E_7~0); 118638#L913-1 assume !(0 == ~E_8~0); 117897#L918-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 117898#L402 assume !(1 == ~m_pc~0); 118333#L402-2 is_master_triggered_~__retres1~0#1 := 0; 118028#L413 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 118029#is_master_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 118287#L1035 assume !(0 != activate_threads_~tmp~1#1); 118288#L1035-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 118341#L421 assume !(1 == ~t1_pc~0); 118803#L421-2 is_transmit1_triggered_~__retres1~1#1 := 0; 118834#L432 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 117899#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 117900#L1043 assume !(0 != activate_threads_~tmp___0~0#1); 118402#L1043-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 118843#L440 assume !(1 == ~t2_pc~0); 118884#L440-2 is_transmit2_triggered_~__retres1~2#1 := 0; 118037#L451 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 118038#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 118226#L1051 assume !(0 != activate_threads_~tmp___1~0#1); 118656#L1051-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 118233#L459 assume !(1 == ~t3_pc~0); 118234#L459-2 is_transmit3_triggered_~__retres1~3#1 := 0; 118798#L470 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 117858#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 117859#L1059 assume !(0 != activate_threads_~tmp___2~0#1); 118022#L1059-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 118032#L478 assume !(1 == ~t4_pc~0); 118033#L478-2 is_transmit4_triggered_~__retres1~4#1 := 0; 118708#L489 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 117975#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 117976#L1067 assume !(0 != activate_threads_~tmp___3~0#1); 117939#L1067-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 117940#L497 assume !(1 == ~t5_pc~0); 117986#L497-2 is_transmit5_triggered_~__retres1~5#1 := 0; 117987#L508 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 118578#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 118702#L1075 assume !(0 != activate_threads_~tmp___4~0#1); 118792#L1075-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 118793#L516 assume 1 == ~t6_pc~0; 118878#L517 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 118528#L527 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 118210#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 118078#L1083 assume !(0 != activate_threads_~tmp___5~0#1); 118079#L1083-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 118517#L535 assume !(1 == ~t7_pc~0); 118518#L535-2 is_transmit7_triggered_~__retres1~7#1 := 0; 118592#L546 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 118593#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 118627#L1091 assume !(0 != activate_threads_~tmp___6~0#1); 118617#L1091-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 118618#L554 assume 1 == ~t8_pc~0; 118554#L555 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 117861#L565 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 118648#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 118168#L1099 assume !(0 != activate_threads_~tmp___7~0#1); 118169#L1099-2 havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 117847#L931 assume !(1 == ~M_E~0); 117848#L931-2 assume 1 == ~T1_E~0;~T1_E~0 := 2; 118821#L936-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 118855#L941-1 assume !(1 == ~T3_E~0); 118342#L946-1 assume !(1 == ~T4_E~0); 118343#L951-1 assume !(1 == ~T5_E~0); 118093#L956-1 assume !(1 == ~T6_E~0); 118094#L961-1 assume !(1 == ~T7_E~0); 118499#L966-1 assume !(1 == ~T8_E~0); 118500#L971-1 assume 1 == ~E_1~0;~E_1~0 := 2; 118620#L976-1 assume !(1 == ~E_2~0); 127975#L981-1 assume !(1 == ~E_3~0); 127973#L986-1 assume !(1 == ~E_4~0); 118120#L991-1 assume !(1 == ~E_5~0); 118121#L996-1 assume !(1 == ~E_6~0); 118838#L1001-1 assume !(1 == ~E_7~0); 118839#L1006-1 assume !(1 == ~E_8~0); 127904#L1011-1 assume { :end_inline_reset_delta_events } true; 127870#L1272-2 [2023-11-06 21:58:48,205 INFO L750 eck$LassoCheckResult]: Loop: 127870#L1272-2 assume !false; 127859#L1273 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 127855#L813-1 assume !false; 127851#L692 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 127711#L634 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 127697#L681 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 127693#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 127691#L696 assume !(0 != eval_~tmp~0#1); 127692#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 129064#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 129062#L838-3 assume 0 == ~M_E~0;~M_E~0 := 1; 129060#L838-5 assume !(0 == ~T1_E~0); 129058#L843-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 129056#L848-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 129054#L853-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 129052#L858-3 assume !(0 == ~T5_E~0); 129050#L863-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 129048#L868-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 129045#L873-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 129043#L878-3 assume !(0 == ~E_1~0); 129041#L883-3 assume 0 == ~E_2~0;~E_2~0 := 1; 129039#L888-3 assume 0 == ~E_3~0;~E_3~0 := 1; 129037#L893-3 assume 0 == ~E_4~0;~E_4~0 := 1; 129035#L898-3 assume !(0 == ~E_5~0); 129032#L903-3 assume 0 == ~E_6~0;~E_6~0 := 1; 129030#L908-3 assume 0 == ~E_7~0;~E_7~0 := 1; 129028#L913-3 assume 0 == ~E_8~0;~E_8~0 := 1; 129026#L918-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 129024#L402-27 assume !(1 == ~m_pc~0); 129022#L402-29 is_master_triggered_~__retres1~0#1 := 0; 129019#L413-9 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 129017#is_master_triggered_returnLabel#10 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 129015#L1035-27 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 129013#L1035-29 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 129011#L421-27 assume !(1 == ~t1_pc~0); 129009#L421-29 is_transmit1_triggered_~__retres1~1#1 := 0; 129006#L432-9 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 129004#is_transmit1_triggered_returnLabel#10 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 129002#L1043-27 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 129000#L1043-29 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 128998#L440-27 assume !(1 == ~t2_pc~0); 128996#L440-29 is_transmit2_triggered_~__retres1~2#1 := 0; 128994#L451-9 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 128990#is_transmit2_triggered_returnLabel#10 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 128988#L1051-27 assume !(0 != activate_threads_~tmp___1~0#1); 128986#L1051-29 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 128984#L459-27 assume !(1 == ~t3_pc~0); 128980#L459-29 is_transmit3_triggered_~__retres1~3#1 := 0; 128978#L470-9 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 128976#is_transmit3_triggered_returnLabel#10 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 128974#L1059-27 assume !(0 != activate_threads_~tmp___2~0#1); 128971#L1059-29 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 128969#L478-27 assume !(1 == ~t4_pc~0); 128967#L478-29 is_transmit4_triggered_~__retres1~4#1 := 0; 128963#L489-9 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 128961#is_transmit4_triggered_returnLabel#10 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 128959#L1067-27 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 128957#L1067-29 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 128956#L497-27 assume !(1 == ~t5_pc~0); 128955#L497-29 is_transmit5_triggered_~__retres1~5#1 := 0; 128953#L508-9 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 128952#is_transmit5_triggered_returnLabel#10 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 128951#L1075-27 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 128950#L1075-29 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 128949#L516-27 assume !(1 == ~t6_pc~0); 128947#L516-29 is_transmit6_triggered_~__retres1~6#1 := 0; 128946#L527-9 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 128945#is_transmit6_triggered_returnLabel#10 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 128944#L1083-27 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 128943#L1083-29 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 128942#L535-27 assume 1 == ~t7_pc~0; 128939#L536-9 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 128937#L546-9 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 128935#is_transmit7_triggered_returnLabel#10 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 128933#L1091-27 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 128931#L1091-29 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 128929#L554-27 assume 1 == ~t8_pc~0; 128927#L555-9 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 128924#L565-9 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 128922#is_transmit8_triggered_returnLabel#10 activate_threads_#t~ret22#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 128920#L1099-27 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 128918#L1099-29 havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 128916#L931-3 assume 1 == ~M_E~0;~M_E~0 := 2; 128914#L931-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 128912#L936-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 128794#L941-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 128909#L946-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 128907#L951-3 assume !(1 == ~T5_E~0); 128905#L956-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 128903#L961-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 128901#L966-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 128899#L971-3 assume 1 == ~E_1~0;~E_1~0 := 2; 128897#L976-3 assume 1 == ~E_2~0;~E_2~0 := 2; 128895#L981-3 assume 1 == ~E_3~0;~E_3~0 := 2; 128893#L986-3 assume 1 == ~E_4~0;~E_4~0 := 2; 128767#L991-3 assume !(1 == ~E_5~0); 128765#L996-3 assume 1 == ~E_6~0;~E_6~0 := 2; 128763#L1001-3 assume 1 == ~E_7~0;~E_7~0 := 2; 128761#L1006-3 assume 1 == ~E_8~0;~E_8~0 := 2; 128759#L1011-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 128752#L634-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 128743#L681-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 128742#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret24#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret24#1;havoc start_simulation_#t~ret24#1; 128737#L1291 assume !(0 == start_simulation_~tmp~3#1); 128734#L1291-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 128580#L634-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 128568#L681-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 128563#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret23#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret23#1;havoc stop_simulation_#t~ret23#1; 128561#L1246 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 128559#L1253 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 128558#stop_simulation_returnLabel#1 start_simulation_#t~ret25#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret25#1;havoc start_simulation_#t~ret25#1; 127903#L1304 assume !(0 != start_simulation_~tmp___0~1#1); 127870#L1272-2 [2023-11-06 21:58:48,205 INFO L145 PredicateUnifier]: Initialized classic predicate unifier [2023-11-06 21:58:48,206 INFO L85 PathProgramCache]: Analyzing trace with hash -461177985, now seen corresponding path program 1 times [2023-11-06 21:58:48,206 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-06 21:58:48,206 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [5842354] [2023-11-06 21:58:48,206 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-06 21:58:48,206 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-06 21:58:48,223 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-06 21:58:48,417 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-06 21:58:48,417 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-06 21:58:48,417 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [5842354] [2023-11-06 21:58:48,418 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [5842354] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-06 21:58:48,418 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-06 21:58:48,418 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-06 21:58:48,418 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [592663952] [2023-11-06 21:58:48,418 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-06 21:58:48,419 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-06 21:58:48,419 INFO L145 PredicateUnifier]: Initialized classic predicate unifier [2023-11-06 21:58:48,419 INFO L85 PathProgramCache]: Analyzing trace with hash 1800414222, now seen corresponding path program 1 times [2023-11-06 21:58:48,420 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-06 21:58:48,420 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1145140734] [2023-11-06 21:58:48,420 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-06 21:58:48,420 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-06 21:58:48,441 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-06 21:58:48,519 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-06 21:58:48,519 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-06 21:58:48,519 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1145140734] [2023-11-06 21:58:48,520 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1145140734] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-06 21:58:48,520 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-06 21:58:48,520 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2023-11-06 21:58:48,520 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [994757192] [2023-11-06 21:58:48,520 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-06 21:58:48,521 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-06 21:58:48,522 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-06 21:58:48,522 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2023-11-06 21:58:48,522 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2023-11-06 21:58:48,523 INFO L87 Difference]: Start difference. First operand 23368 states and 33296 transitions. cyclomatic complexity: 9944 Second operand has 4 states, 4 states have (on average 26.0) internal successors, (104), 3 states have internal predecessors, (104), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-06 21:58:49,184 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-06 21:58:49,184 INFO L93 Difference]: Finished difference Result 65183 states and 92255 transitions. [2023-11-06 21:58:49,184 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 65183 states and 92255 transitions. [2023-11-06 21:58:49,774 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 63513 [2023-11-06 21:58:50,063 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 65183 states to 65183 states and 92255 transitions. [2023-11-06 21:58:50,064 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 65183 [2023-11-06 21:58:50,231 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 65183 [2023-11-06 21:58:50,231 INFO L73 IsDeterministic]: Start isDeterministic. Operand 65183 states and 92255 transitions. [2023-11-06 21:58:50,276 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-06 21:58:50,276 INFO L218 hiAutomatonCegarLoop]: Abstraction has 65183 states and 92255 transitions. [2023-11-06 21:58:50,348 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 65183 states and 92255 transitions. [2023-11-06 21:58:51,278 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 65183 to 63095. [2023-11-06 21:58:51,359 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 63095 states, 63095 states have (on average 1.4190506379269356) internal successors, (89535), 63094 states have internal predecessors, (89535), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-06 21:58:51,788 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 63095 states to 63095 states and 89535 transitions. [2023-11-06 21:58:51,789 INFO L240 hiAutomatonCegarLoop]: Abstraction has 63095 states and 89535 transitions. [2023-11-06 21:58:51,789 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2023-11-06 21:58:51,791 INFO L428 stractBuchiCegarLoop]: Abstraction has 63095 states and 89535 transitions. [2023-11-06 21:58:51,791 INFO L335 stractBuchiCegarLoop]: ======== Iteration 16 ============ [2023-11-06 21:58:51,791 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 63095 states and 89535 transitions. [2023-11-06 21:58:52,016 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 62721 [2023-11-06 21:58:52,016 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-06 21:58:52,017 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-06 21:58:52,018 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-06 21:58:52,019 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-06 21:58:52,019 INFO L748 eck$LassoCheckResult]: Stem: 206649#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2; 206650#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~10#1;havoc main_~__retres1~10#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; 207407#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret24#1, start_simulation_#t~ret25#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 207408#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 207410#L581 assume 1 == ~m_i~0;~m_st~0 := 0; 206762#L581-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 206763#L586-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 207402#L591-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 207387#L596-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 206843#L601-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 206844#L606-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 207115#L611-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 207116#L616-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 206939#L621-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 206940#L838 assume !(0 == ~M_E~0); 207124#L838-2 assume !(0 == ~T1_E~0); 206447#L843-1 assume !(0 == ~T2_E~0); 206448#L848-1 assume !(0 == ~T3_E~0); 206568#L853-1 assume !(0 == ~T4_E~0); 206925#L858-1 assume !(0 == ~T5_E~0); 206399#L863-1 assume !(0 == ~T6_E~0); 206400#L868-1 assume !(0 == ~T7_E~0); 207470#L873-1 assume !(0 == ~T8_E~0); 207467#L878-1 assume !(0 == ~E_1~0); 207441#L883-1 assume !(0 == ~E_2~0); 207442#L888-1 assume !(0 == ~E_3~0); 207079#L893-1 assume !(0 == ~E_4~0); 207080#L898-1 assume !(0 == ~E_5~0); 207496#L903-1 assume !(0 == ~E_6~0); 207439#L908-1 assume !(0 == ~E_7~0); 207237#L913-1 assume !(0 == ~E_8~0); 206459#L918-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 206460#L402 assume !(1 == ~m_pc~0); 206901#L402-2 is_master_triggered_~__retres1~0#1 := 0; 206592#L413 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 206593#is_master_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 206850#L1035 assume !(0 != activate_threads_~tmp~1#1); 206851#L1035-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 206912#L421 assume !(1 == ~t1_pc~0); 207434#L421-2 is_transmit1_triggered_~__retres1~1#1 := 0; 207471#L432 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 206463#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 206464#L1043 assume !(0 != activate_threads_~tmp___0~0#1); 206970#L1043-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 207484#L440 assume !(1 == ~t2_pc~0); 207569#L440-2 is_transmit2_triggered_~__retres1~2#1 := 0; 206602#L451 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 206603#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 206789#L1051 assume !(0 != activate_threads_~tmp___1~0#1); 207261#L1051-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 206792#L459 assume !(1 == ~t3_pc~0); 206793#L459-2 is_transmit3_triggered_~__retres1~3#1 := 0; 207426#L470 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 206421#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 206422#L1059 assume !(0 != activate_threads_~tmp___2~0#1); 206587#L1059-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 206596#L478 assume !(1 == ~t4_pc~0); 206597#L478-2 is_transmit4_triggered_~__retres1~4#1 := 0; 207320#L489 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 206540#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 206541#L1067 assume !(0 != activate_threads_~tmp___3~0#1); 206501#L1067-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 206502#L497 assume !(1 == ~t5_pc~0); 206551#L497-2 is_transmit5_triggered_~__retres1~5#1 := 0; 206552#L508 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 207173#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 207315#L1075 assume !(0 != activate_threads_~tmp___4~0#1); 207419#L1075-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 207420#L516 assume !(1 == ~t6_pc~0); 207338#L516-2 is_transmit6_triggered_~__retres1~6#1 := 0; 207114#L527 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 206772#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 206643#L1083 assume !(0 != activate_threads_~tmp___5~0#1); 206644#L1083-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 207102#L535 assume !(1 == ~t7_pc~0); 207103#L535-2 is_transmit7_triggered_~__retres1~7#1 := 0; 207191#L546 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 207192#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 207228#L1091 assume !(0 != activate_threads_~tmp___6~0#1); 207217#L1091-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 207218#L554 assume 1 == ~t8_pc~0; 207145#L555 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 206424#L565 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 207248#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 206725#L1099 assume !(0 != activate_threads_~tmp___7~0#1); 206726#L1099-2 havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 206410#L931 assume !(1 == ~M_E~0); 206411#L931-2 assume 1 == ~T1_E~0;~T1_E~0 := 2; 207458#L936-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 207512#L941-1 assume !(1 == ~T3_E~0); 207566#L946-1 assume !(1 == ~T4_E~0); 207429#L951-1 assume !(1 == ~T5_E~0); 207430#L956-1 assume !(1 == ~T6_E~0); 207558#L961-1 assume !(1 == ~T7_E~0); 207559#L966-1 assume !(1 == ~T8_E~0); 207220#L971-1 assume 1 == ~E_1~0;~E_1~0 := 2; 207221#L976-1 assume !(1 == ~E_2~0); 207179#L981-1 assume !(1 == ~E_3~0); 207180#L986-1 assume !(1 == ~E_4~0); 206683#L991-1 assume !(1 == ~E_5~0); 206684#L996-1 assume !(1 == ~E_6~0); 207478#L1001-1 assume !(1 == ~E_7~0); 207479#L1006-1 assume !(1 == ~E_8~0); 207431#L1011-1 assume { :end_inline_reset_delta_events } true; 207432#L1272-2 [2023-11-06 21:58:52,020 INFO L750 eck$LassoCheckResult]: Loop: 207432#L1272-2 assume !false; 262444#L1273 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 262443#L813-1 assume !false; 262442#L692 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 262440#L634 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 262432#L681 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 262431#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 262429#L696 assume !(0 != eval_~tmp~0#1); 262430#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 262802#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 262800#L838-3 assume 0 == ~M_E~0;~M_E~0 := 1; 262799#L838-5 assume !(0 == ~T1_E~0); 262798#L843-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 262797#L848-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 262796#L853-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 262795#L858-3 assume !(0 == ~T5_E~0); 262794#L863-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 262793#L868-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 262792#L873-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 262791#L878-3 assume !(0 == ~E_1~0); 262790#L883-3 assume 0 == ~E_2~0;~E_2~0 := 1; 262789#L888-3 assume 0 == ~E_3~0;~E_3~0 := 1; 262788#L893-3 assume 0 == ~E_4~0;~E_4~0 := 1; 262787#L898-3 assume !(0 == ~E_5~0); 262786#L903-3 assume 0 == ~E_6~0;~E_6~0 := 1; 262785#L908-3 assume 0 == ~E_7~0;~E_7~0 := 1; 262784#L913-3 assume 0 == ~E_8~0;~E_8~0 := 1; 262783#L918-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 262782#L402-27 assume !(1 == ~m_pc~0); 262781#L402-29 is_master_triggered_~__retres1~0#1 := 0; 262780#L413-9 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 262779#is_master_triggered_returnLabel#10 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 262778#L1035-27 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 262775#L1035-29 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 262772#L421-27 assume !(1 == ~t1_pc~0); 262769#L421-29 is_transmit1_triggered_~__retres1~1#1 := 0; 262766#L432-9 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 262763#is_transmit1_triggered_returnLabel#10 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 262760#L1043-27 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 262757#L1043-29 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 262754#L440-27 assume !(1 == ~t2_pc~0); 262751#L440-29 is_transmit2_triggered_~__retres1~2#1 := 0; 262748#L451-9 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 262745#is_transmit2_triggered_returnLabel#10 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 262742#L1051-27 assume !(0 != activate_threads_~tmp___1~0#1); 262739#L1051-29 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 262736#L459-27 assume 1 == ~t3_pc~0; 262732#L460-9 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 262728#L470-9 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 262724#is_transmit3_triggered_returnLabel#10 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 262720#L1059-27 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 262717#L1059-29 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 262712#L478-27 assume !(1 == ~t4_pc~0); 262707#L478-29 is_transmit4_triggered_~__retres1~4#1 := 0; 262702#L489-9 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 262697#is_transmit4_triggered_returnLabel#10 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 262694#L1067-27 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 262691#L1067-29 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 262688#L497-27 assume 1 == ~t5_pc~0; 262684#L498-9 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 262681#L508-9 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 262678#is_transmit5_triggered_returnLabel#10 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 262674#L1075-27 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 262670#L1075-29 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 262664#L516-27 assume !(1 == ~t6_pc~0); 262660#L516-29 is_transmit6_triggered_~__retres1~6#1 := 0; 262656#L527-9 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 262652#is_transmit6_triggered_returnLabel#10 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 262648#L1083-27 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 262644#L1083-29 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 262640#L535-27 assume !(1 == ~t7_pc~0); 262636#L535-29 is_transmit7_triggered_~__retres1~7#1 := 0; 262631#L546-9 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 262627#is_transmit7_triggered_returnLabel#10 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 262623#L1091-27 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 262619#L1091-29 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 262613#L554-27 assume !(1 == ~t8_pc~0); 262608#L554-29 is_transmit8_triggered_~__retres1~8#1 := 0; 262604#L565-9 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 262600#is_transmit8_triggered_returnLabel#10 activate_threads_#t~ret22#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 262596#L1099-27 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 262591#L1099-29 havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 262584#L931-3 assume 1 == ~M_E~0;~M_E~0 := 2; 262579#L931-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 262574#L936-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 261265#L941-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 262567#L946-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 262563#L951-3 assume !(1 == ~T5_E~0); 262559#L956-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 262555#L961-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 262551#L966-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 262547#L971-3 assume 1 == ~E_1~0;~E_1~0 := 2; 262543#L976-3 assume 1 == ~E_2~0;~E_2~0 := 2; 262538#L981-3 assume 1 == ~E_3~0;~E_3~0 := 2; 262534#L986-3 assume 1 == ~E_4~0;~E_4~0 := 2; 262530#L991-3 assume !(1 == ~E_5~0); 261240#L996-3 assume 1 == ~E_6~0;~E_6~0 := 2; 262523#L1001-3 assume 1 == ~E_7~0;~E_7~0 := 2; 262519#L1006-3 assume 1 == ~E_8~0;~E_8~0 := 2; 262515#L1011-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 262510#L634-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 262500#L681-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 262497#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret24#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret24#1;havoc start_simulation_#t~ret24#1; 262493#L1291 assume !(0 == start_simulation_~tmp~3#1); 262490#L1291-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 262487#L634-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 262477#L681-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 262475#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret23#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret23#1;havoc stop_simulation_#t~ret23#1; 262473#L1246 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 262471#L1253 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 262469#stop_simulation_returnLabel#1 start_simulation_#t~ret25#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret25#1;havoc start_simulation_#t~ret25#1; 262466#L1304 assume !(0 != start_simulation_~tmp___0~1#1); 207432#L1272-2 [2023-11-06 21:58:52,020 INFO L145 PredicateUnifier]: Initialized classic predicate unifier [2023-11-06 21:58:52,020 INFO L85 PathProgramCache]: Analyzing trace with hash 2068972702, now seen corresponding path program 1 times [2023-11-06 21:58:52,021 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-06 21:58:52,021 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [800443058] [2023-11-06 21:58:52,021 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-06 21:58:52,021 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-06 21:58:52,037 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-06 21:58:52,084 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-06 21:58:52,084 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-06 21:58:52,085 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [800443058] [2023-11-06 21:58:52,085 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [800443058] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-06 21:58:52,085 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-06 21:58:52,085 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2023-11-06 21:58:52,085 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [928463804] [2023-11-06 21:58:52,086 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-06 21:58:52,086 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-06 21:58:52,086 INFO L145 PredicateUnifier]: Initialized classic predicate unifier [2023-11-06 21:58:52,087 INFO L85 PathProgramCache]: Analyzing trace with hash -1724015728, now seen corresponding path program 1 times [2023-11-06 21:58:52,087 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-06 21:58:52,087 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [854642974] [2023-11-06 21:58:52,087 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-06 21:58:52,087 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-06 21:58:52,103 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-06 21:58:52,134 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-06 21:58:52,134 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-06 21:58:52,134 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [854642974] [2023-11-06 21:58:52,134 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [854642974] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-06 21:58:52,134 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-06 21:58:52,135 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-06 21:58:52,135 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [904357410] [2023-11-06 21:58:52,135 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-06 21:58:52,135 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-06 21:58:52,136 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-06 21:58:52,136 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-06 21:58:52,136 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-06 21:58:52,136 INFO L87 Difference]: Start difference. First operand 63095 states and 89535 transitions. cyclomatic complexity: 26472 Second operand has 3 states, 3 states have (on average 34.666666666666664) internal successors, (104), 2 states have internal predecessors, (104), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-06 21:58:53,113 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-06 21:58:53,113 INFO L93 Difference]: Finished difference Result 125248 states and 176651 transitions. [2023-11-06 21:58:53,113 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 125248 states and 176651 transitions. [2023-11-06 21:58:53,875 INFO L131 ngComponentsAnalysis]: Automaton has 64 accepting balls. 124411 [2023-11-06 21:58:54,456 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 125248 states to 125248 states and 176651 transitions. [2023-11-06 21:58:54,457 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 125248 [2023-11-06 21:58:54,898 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 125248 [2023-11-06 21:58:54,898 INFO L73 IsDeterministic]: Start isDeterministic. Operand 125248 states and 176651 transitions. [2023-11-06 21:58:55,044 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-06 21:58:55,064 INFO L218 hiAutomatonCegarLoop]: Abstraction has 125248 states and 176651 transitions. [2023-11-06 21:58:55,193 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 125248 states and 176651 transitions. [2023-11-06 21:58:56,494 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 125248 to 124816. [2023-11-06 21:58:56,606 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 124816 states, 124816 states have (on average 1.4109649403922575) internal successors, (176111), 124815 states have internal predecessors, (176111), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-06 21:58:57,517 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 124816 states to 124816 states and 176111 transitions. [2023-11-06 21:58:57,517 INFO L240 hiAutomatonCegarLoop]: Abstraction has 124816 states and 176111 transitions. [2023-11-06 21:58:57,518 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-06 21:58:57,518 INFO L428 stractBuchiCegarLoop]: Abstraction has 124816 states and 176111 transitions. [2023-11-06 21:58:57,518 INFO L335 stractBuchiCegarLoop]: ======== Iteration 17 ============ [2023-11-06 21:58:57,519 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 124816 states and 176111 transitions. [2023-11-06 21:58:57,824 INFO L131 ngComponentsAnalysis]: Automaton has 64 accepting balls. 124195 [2023-11-06 21:58:57,824 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-06 21:58:57,824 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-06 21:58:57,826 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-06 21:58:57,826 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-06 21:58:57,827 INFO L748 eck$LassoCheckResult]: Stem: 394999#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2; 395000#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~10#1;havoc main_~__retres1~10#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; 395724#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret24#1, start_simulation_#t~ret25#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 395725#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 395727#L581 assume 1 == ~m_i~0;~m_st~0 := 0; 395114#L581-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 395115#L586-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 395717#L591-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 395706#L596-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 395194#L601-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 395195#L606-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 395455#L611-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 395456#L616-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 395284#L621-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 395285#L838 assume !(0 == ~M_E~0); 395464#L838-2 assume !(0 == ~T1_E~0); 394795#L843-1 assume !(0 == ~T2_E~0); 394796#L848-1 assume !(0 == ~T3_E~0); 394916#L853-1 assume !(0 == ~T4_E~0); 395271#L858-1 assume !(0 == ~T5_E~0); 394749#L863-1 assume !(0 == ~T6_E~0); 394750#L868-1 assume !(0 == ~T7_E~0); 395781#L873-1 assume !(0 == ~T8_E~0); 395778#L878-1 assume !(0 == ~E_1~0); 395757#L883-1 assume !(0 == ~E_2~0); 395758#L888-1 assume !(0 == ~E_3~0); 395422#L893-1 assume !(0 == ~E_4~0); 395423#L898-1 assume !(0 == ~E_5~0); 395800#L903-1 assume !(0 == ~E_6~0); 395755#L908-1 assume !(0 == ~E_7~0); 395571#L913-1 assume !(0 == ~E_8~0); 394808#L918-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 394809#L402 assume !(1 == ~m_pc~0); 395248#L402-2 is_master_triggered_~__retres1~0#1 := 0; 394943#L413 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 394944#is_master_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 395201#L1035 assume !(0 != activate_threads_~tmp~1#1); 395202#L1035-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 395258#L421 assume !(1 == ~t1_pc~0); 395751#L421-2 is_transmit1_triggered_~__retres1~1#1 := 0; 395782#L432 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 394811#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 394812#L1043 assume !(0 != activate_threads_~tmp___0~0#1); 395314#L1043-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 395790#L440 assume !(1 == ~t2_pc~0); 395862#L440-2 is_transmit2_triggered_~__retres1~2#1 := 0; 394953#L451 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 394954#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 395141#L1051 assume !(0 != activate_threads_~tmp___1~0#1); 395592#L1051-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 395144#L459 assume !(1 == ~t3_pc~0); 395145#L459-2 is_transmit3_triggered_~__retres1~3#1 := 0; 395745#L470 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 394771#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 394772#L1059 assume !(0 != activate_threads_~tmp___2~0#1); 394937#L1059-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 394947#L478 assume !(1 == ~t4_pc~0); 394948#L478-2 is_transmit4_triggered_~__retres1~4#1 := 0; 395649#L489 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 394888#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 394889#L1067 assume !(0 != activate_threads_~tmp___3~0#1); 394849#L1067-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 394850#L497 assume !(1 == ~t5_pc~0); 394899#L497-2 is_transmit5_triggered_~__retres1~5#1 := 0; 394900#L508 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 395508#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 395644#L1075 assume !(0 != activate_threads_~tmp___4~0#1); 395739#L1075-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 395740#L516 assume !(1 == ~t6_pc~0); 395664#L516-2 is_transmit6_triggered_~__retres1~6#1 := 0; 395454#L527 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 395124#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 394993#L1083 assume !(0 != activate_threads_~tmp___5~0#1); 394994#L1083-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 395443#L535 assume !(1 == ~t7_pc~0); 395444#L535-2 is_transmit7_triggered_~__retres1~7#1 := 0; 395524#L546 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 395525#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 395561#L1091 assume !(0 != activate_threads_~tmp___6~0#1); 395550#L1091-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 395551#L554 assume !(1 == ~t8_pc~0); 394773#L554-2 is_transmit8_triggered_~__retres1~8#1 := 0; 394774#L565 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 395585#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 395078#L1099 assume !(0 != activate_threads_~tmp___7~0#1); 395079#L1099-2 havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 394760#L931 assume !(1 == ~M_E~0); 394761#L931-2 assume 1 == ~T1_E~0;~T1_E~0 := 2; 395769#L936-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 395812#L941-1 assume !(1 == ~T3_E~0); 395861#L946-1 assume !(1 == ~T4_E~0); 395746#L951-1 assume !(1 == ~T5_E~0); 395747#L956-1 assume !(1 == ~T6_E~0); 395849#L961-1 assume !(1 == ~T7_E~0); 395850#L966-1 assume !(1 == ~T8_E~0); 395553#L971-1 assume 1 == ~E_1~0;~E_1~0 := 2; 395554#L976-1 assume !(1 == ~E_2~0); 395513#L981-1 assume !(1 == ~E_3~0); 395514#L986-1 assume !(1 == ~E_4~0); 395035#L991-1 assume !(1 == ~E_5~0); 395036#L996-1 assume !(1 == ~E_6~0); 395786#L1001-1 assume !(1 == ~E_7~0); 395787#L1006-1 assume !(1 == ~E_8~0); 395748#L1011-1 assume { :end_inline_reset_delta_events } true; 395749#L1272-2 [2023-11-06 21:58:57,827 INFO L750 eck$LassoCheckResult]: Loop: 395749#L1272-2 assume !false; 413954#L1273 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 462459#L813-1 assume !false; 413777#L692 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 413662#L634 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 413655#L681 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 413639#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 413640#L696 assume !(0 != eval_~tmp~0#1); 462248#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 464306#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 464305#L838-3 assume 0 == ~M_E~0;~M_E~0 := 1; 464304#L838-5 assume !(0 == ~T1_E~0); 464303#L843-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 464302#L848-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 464301#L853-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 464300#L858-3 assume !(0 == ~T5_E~0); 464299#L863-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 464298#L868-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 464297#L873-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 464296#L878-3 assume !(0 == ~E_1~0); 464295#L883-3 assume 0 == ~E_2~0;~E_2~0 := 1; 464294#L888-3 assume 0 == ~E_3~0;~E_3~0 := 1; 464293#L893-3 assume 0 == ~E_4~0;~E_4~0 := 1; 464292#L898-3 assume !(0 == ~E_5~0); 464291#L903-3 assume 0 == ~E_6~0;~E_6~0 := 1; 464290#L908-3 assume 0 == ~E_7~0;~E_7~0 := 1; 464289#L913-3 assume 0 == ~E_8~0;~E_8~0 := 1; 464288#L918-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 464287#L402-27 assume !(1 == ~m_pc~0); 464286#L402-29 is_master_triggered_~__retres1~0#1 := 0; 464285#L413-9 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 464284#is_master_triggered_returnLabel#10 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 464283#L1035-27 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 464282#L1035-29 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 464281#L421-27 assume !(1 == ~t1_pc~0); 464280#L421-29 is_transmit1_triggered_~__retres1~1#1 := 0; 464279#L432-9 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 464278#is_transmit1_triggered_returnLabel#10 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 464277#L1043-27 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 464276#L1043-29 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 464275#L440-27 assume !(1 == ~t2_pc~0); 464274#L440-29 is_transmit2_triggered_~__retres1~2#1 := 0; 464273#L451-9 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 464272#is_transmit2_triggered_returnLabel#10 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 464271#L1051-27 assume !(0 != activate_threads_~tmp___1~0#1); 464270#L1051-29 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 464269#L459-27 assume 1 == ~t3_pc~0; 464267#L460-9 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 464268#L470-9 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 464307#is_transmit3_triggered_returnLabel#10 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 463324#L1059-27 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 463320#L1059-29 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 463318#L478-27 assume !(1 == ~t4_pc~0); 463319#L478-29 is_transmit4_triggered_~__retres1~4#1 := 0; 464248#L489-9 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 464246#is_transmit4_triggered_returnLabel#10 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 463309#L1067-27 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 463307#L1067-29 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 463305#L497-27 assume !(1 == ~t5_pc~0); 463303#L497-29 is_transmit5_triggered_~__retres1~5#1 := 0; 463300#L508-9 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 463298#is_transmit5_triggered_returnLabel#10 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 463295#L1075-27 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 463296#L1075-29 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 464218#L516-27 assume !(1 == ~t6_pc~0); 464216#L516-29 is_transmit6_triggered_~__retres1~6#1 := 0; 464214#L527-9 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 463287#is_transmit6_triggered_returnLabel#10 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 414106#L1083-27 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 414104#L1083-29 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 414102#L535-27 assume !(1 == ~t7_pc~0); 414100#L535-29 is_transmit7_triggered_~__retres1~7#1 := 0; 414097#L546-9 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 414094#is_transmit7_triggered_returnLabel#10 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 414091#L1091-27 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 414088#L1091-29 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 414084#L554-27 assume !(1 == ~t8_pc~0); 414080#L554-29 is_transmit8_triggered_~__retres1~8#1 := 0; 414077#L565-9 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 414073#is_transmit8_triggered_returnLabel#10 activate_threads_#t~ret22#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 414074#L1099-27 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 414065#L1099-29 havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 414066#L931-3 assume 1 == ~M_E~0;~M_E~0 := 2; 414057#L931-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 414058#L936-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 414049#L941-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 414050#L946-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 414041#L951-3 assume !(1 == ~T5_E~0); 414042#L956-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 462950#L961-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 462949#L966-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 462948#L971-3 assume 1 == ~E_1~0;~E_1~0 := 2; 462947#L976-3 assume 1 == ~E_2~0;~E_2~0 := 2; 462946#L981-3 assume 1 == ~E_3~0;~E_3~0 := 2; 462945#L986-3 assume 1 == ~E_4~0;~E_4~0 := 2; 462944#L991-3 assume !(1 == ~E_5~0); 451458#L996-3 assume 1 == ~E_6~0;~E_6~0 := 2; 462943#L1001-3 assume 1 == ~E_7~0;~E_7~0 := 2; 462942#L1006-3 assume 1 == ~E_8~0;~E_8~0 := 2; 414004#L1011-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 414005#L634-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 462513#L681-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 462512#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret24#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret24#1;havoc start_simulation_#t~ret24#1; 462510#L1291 assume !(0 == start_simulation_~tmp~3#1); 462508#L1291-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 462507#L634-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 462498#L681-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 462497#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret23#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret23#1;havoc stop_simulation_#t~ret23#1; 462493#L1246 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 462491#L1253 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 413959#stop_simulation_returnLabel#1 start_simulation_#t~ret25#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret25#1;havoc start_simulation_#t~ret25#1; 413960#L1304 assume !(0 != start_simulation_~tmp___0~1#1); 395749#L1272-2 [2023-11-06 21:58:57,828 INFO L145 PredicateUnifier]: Initialized classic predicate unifier [2023-11-06 21:58:57,828 INFO L85 PathProgramCache]: Analyzing trace with hash 478577725, now seen corresponding path program 1 times [2023-11-06 21:58:57,828 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-06 21:58:57,829 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2091866843] [2023-11-06 21:58:57,829 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-06 21:58:57,829 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-06 21:58:57,842 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-06 21:58:57,890 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-06 21:58:57,890 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-06 21:58:57,890 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2091866843] [2023-11-06 21:58:57,890 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2091866843] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-06 21:58:57,890 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-06 21:58:57,891 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2023-11-06 21:58:57,891 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [290085028] [2023-11-06 21:58:57,891 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-06 21:58:57,891 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-06 21:58:57,892 INFO L145 PredicateUnifier]: Initialized classic predicate unifier [2023-11-06 21:58:57,892 INFO L85 PathProgramCache]: Analyzing trace with hash -1621214481, now seen corresponding path program 1 times [2023-11-06 21:58:57,892 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-06 21:58:57,892 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [404510510] [2023-11-06 21:58:57,892 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-06 21:58:57,893 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-06 21:58:57,905 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-06 21:58:57,956 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-06 21:58:57,957 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-06 21:58:57,957 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [404510510] [2023-11-06 21:58:57,957 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [404510510] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-06 21:58:57,957 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-06 21:58:57,957 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2023-11-06 21:58:57,957 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [671875477] [2023-11-06 21:58:57,958 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-06 21:58:57,958 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-06 21:58:57,958 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-06 21:58:57,959 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-06 21:58:57,959 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-06 21:58:57,959 INFO L87 Difference]: Start difference. First operand 124816 states and 176111 transitions. cyclomatic complexity: 51359 Second operand has 3 states, 3 states have (on average 34.666666666666664) internal successors, (104), 2 states have internal predecessors, (104), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-06 21:58:58,815 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-06 21:58:58,816 INFO L93 Difference]: Finished difference Result 124816 states and 175461 transitions. [2023-11-06 21:58:58,816 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 124816 states and 175461 transitions. [2023-11-06 21:58:59,344 INFO L131 ngComponentsAnalysis]: Automaton has 64 accepting balls. 124195 [2023-11-06 21:58:59,790 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 124816 states to 124816 states and 175461 transitions. [2023-11-06 21:58:59,791 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 124816 [2023-11-06 21:58:59,867 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 124816 [2023-11-06 21:58:59,868 INFO L73 IsDeterministic]: Start isDeterministic. Operand 124816 states and 175461 transitions. [2023-11-06 21:59:00,009 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-06 21:59:00,010 INFO L218 hiAutomatonCegarLoop]: Abstraction has 124816 states and 175461 transitions. [2023-11-06 21:59:00,099 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 124816 states and 175461 transitions. [2023-11-06 21:59:02,134 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 124816 to 124816. [2023-11-06 21:59:02,237 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 124816 states, 124816 states have (on average 1.4057572747083706) internal successors, (175461), 124815 states have internal predecessors, (175461), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-06 21:59:02,576 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 124816 states to 124816 states and 175461 transitions. [2023-11-06 21:59:02,576 INFO L240 hiAutomatonCegarLoop]: Abstraction has 124816 states and 175461 transitions. [2023-11-06 21:59:02,576 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-06 21:59:02,577 INFO L428 stractBuchiCegarLoop]: Abstraction has 124816 states and 175461 transitions. [2023-11-06 21:59:02,577 INFO L335 stractBuchiCegarLoop]: ======== Iteration 18 ============ [2023-11-06 21:59:02,577 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 124816 states and 175461 transitions. [2023-11-06 21:59:02,873 INFO L131 ngComponentsAnalysis]: Automaton has 64 accepting balls. 124195 [2023-11-06 21:59:02,873 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-06 21:59:02,873 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-06 21:59:02,875 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-06 21:59:02,875 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-06 21:59:02,875 INFO L748 eck$LassoCheckResult]: Stem: 644640#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2; 644641#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~10#1;havoc main_~__retres1~10#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; 645379#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret24#1, start_simulation_#t~ret25#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 645380#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 645383#L581 assume 1 == ~m_i~0;~m_st~0 := 0; 644753#L581-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 644754#L586-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 645373#L591-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 645364#L596-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 644834#L601-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 644835#L606-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 645094#L611-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 645095#L616-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 644924#L621-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 644925#L838 assume !(0 == ~M_E~0); 645106#L838-2 assume !(0 == ~T1_E~0); 644438#L843-1 assume !(0 == ~T2_E~0); 644439#L848-1 assume !(0 == ~T3_E~0); 644557#L853-1 assume !(0 == ~T4_E~0); 644913#L858-1 assume !(0 == ~T5_E~0); 644392#L863-1 assume !(0 == ~T6_E~0); 644393#L868-1 assume !(0 == ~T7_E~0); 645453#L873-1 assume !(0 == ~T8_E~0); 645451#L878-1 assume !(0 == ~E_1~0); 645418#L883-1 assume !(0 == ~E_2~0); 645419#L888-1 assume !(0 == ~E_3~0); 645062#L893-1 assume !(0 == ~E_4~0); 645063#L898-1 assume !(0 == ~E_5~0); 645474#L903-1 assume !(0 == ~E_6~0); 645414#L908-1 assume !(0 == ~E_7~0); 645215#L913-1 assume !(0 == ~E_8~0); 644451#L918-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 644452#L402 assume !(1 == ~m_pc~0); 644888#L402-2 is_master_triggered_~__retres1~0#1 := 0; 644584#L413 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 644585#is_master_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 644841#L1035 assume !(0 != activate_threads_~tmp~1#1); 644842#L1035-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 644897#L421 assume !(1 == ~t1_pc~0); 645407#L421-2 is_transmit1_triggered_~__retres1~1#1 := 0; 645456#L432 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 644453#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 644454#L1043 assume !(0 != activate_threads_~tmp___0~0#1); 644956#L1043-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 645465#L440 assume !(1 == ~t2_pc~0); 645533#L440-2 is_transmit2_triggered_~__retres1~2#1 := 0; 644594#L451 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 644595#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 644780#L1051 assume !(0 != activate_threads_~tmp___1~0#1); 645234#L1051-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 644787#L459 assume !(1 == ~t3_pc~0); 644788#L459-2 is_transmit3_triggered_~__retres1~3#1 := 0; 645400#L470 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 644412#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 644413#L1059 assume !(0 != activate_threads_~tmp___2~0#1); 644578#L1059-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 644588#L478 assume !(1 == ~t4_pc~0); 644589#L478-2 is_transmit4_triggered_~__retres1~4#1 := 0; 645297#L489 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 644529#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 644530#L1067 assume !(0 != activate_threads_~tmp___3~0#1); 644493#L1067-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 644494#L497 assume !(1 == ~t5_pc~0); 644540#L497-2 is_transmit5_triggered_~__retres1~5#1 := 0; 644541#L508 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 645152#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 645292#L1075 assume !(0 != activate_threads_~tmp___4~0#1); 645394#L1075-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 645395#L516 assume !(1 == ~t6_pc~0); 645312#L516-2 is_transmit6_triggered_~__retres1~6#1 := 0; 645093#L527 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 644763#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 644634#L1083 assume !(0 != activate_threads_~tmp___5~0#1); 644635#L1083-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 645082#L535 assume !(1 == ~t7_pc~0); 645083#L535-2 is_transmit7_triggered_~__retres1~7#1 := 0; 645170#L546 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 645171#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 645205#L1091 assume !(0 != activate_threads_~tmp___6~0#1); 645195#L1091-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 645196#L554 assume !(1 == ~t8_pc~0); 644414#L554-2 is_transmit8_triggered_~__retres1~8#1 := 0; 644415#L565 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 645226#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 644719#L1099 assume !(0 != activate_threads_~tmp___7~0#1); 644720#L1099-2 havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 644401#L931 assume !(1 == ~M_E~0); 644402#L931-2 assume !(1 == ~T1_E~0); 645437#L936-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 645484#L941-1 assume !(1 == ~T3_E~0); 645532#L946-1 assume !(1 == ~T4_E~0); 645402#L951-1 assume !(1 == ~T5_E~0); 645403#L956-1 assume !(1 == ~T6_E~0); 645524#L961-1 assume !(1 == ~T7_E~0); 645525#L966-1 assume !(1 == ~T8_E~0); 645198#L971-1 assume 1 == ~E_1~0;~E_1~0 := 2; 645199#L976-1 assume !(1 == ~E_2~0); 645159#L981-1 assume !(1 == ~E_3~0); 645160#L986-1 assume !(1 == ~E_4~0); 644674#L991-1 assume !(1 == ~E_5~0); 644675#L996-1 assume !(1 == ~E_6~0); 645458#L1001-1 assume !(1 == ~E_7~0); 645459#L1006-1 assume !(1 == ~E_8~0); 645404#L1011-1 assume { :end_inline_reset_delta_events } true; 645405#L1272-2 [2023-11-06 21:59:02,876 INFO L750 eck$LassoCheckResult]: Loop: 645405#L1272-2 assume !false; 661686#L1273 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 708356#L813-1 assume !false; 708354#L692 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 708348#L634 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 708339#L681 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 708337#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 708334#L696 assume !(0 != eval_~tmp~0#1); 708335#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 713911#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 713909#L838-3 assume 0 == ~M_E~0;~M_E~0 := 1; 713907#L838-5 assume !(0 == ~T1_E~0); 713905#L843-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 713904#L848-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 713903#L853-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 713901#L858-3 assume !(0 == ~T5_E~0); 713899#L863-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 713897#L868-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 713895#L873-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 713893#L878-3 assume !(0 == ~E_1~0); 713891#L883-3 assume 0 == ~E_2~0;~E_2~0 := 1; 713889#L888-3 assume 0 == ~E_3~0;~E_3~0 := 1; 713888#L893-3 assume 0 == ~E_4~0;~E_4~0 := 1; 713886#L898-3 assume !(0 == ~E_5~0); 713884#L903-3 assume 0 == ~E_6~0;~E_6~0 := 1; 713882#L908-3 assume 0 == ~E_7~0;~E_7~0 := 1; 713880#L913-3 assume 0 == ~E_8~0;~E_8~0 := 1; 713878#L918-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 713876#L402-27 assume !(1 == ~m_pc~0); 713874#L402-29 is_master_triggered_~__retres1~0#1 := 0; 712579#L413-9 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 712577#is_master_triggered_returnLabel#10 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 712563#L1035-27 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 712557#L1035-29 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 712551#L421-27 assume !(1 == ~t1_pc~0); 712546#L421-29 is_transmit1_triggered_~__retres1~1#1 := 0; 712541#L432-9 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 712535#is_transmit1_triggered_returnLabel#10 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 712530#L1043-27 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 712524#L1043-29 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 712519#L440-27 assume !(1 == ~t2_pc~0); 712512#L440-29 is_transmit2_triggered_~__retres1~2#1 := 0; 712507#L451-9 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 712501#is_transmit2_triggered_returnLabel#10 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 712496#L1051-27 assume !(0 != activate_threads_~tmp___1~0#1); 712491#L1051-29 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 712486#L459-27 assume 1 == ~t3_pc~0; 712479#L460-9 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 712472#L470-9 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 712465#is_transmit3_triggered_returnLabel#10 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 712452#L1059-27 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 712444#L1059-29 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 712437#L478-27 assume !(1 == ~t4_pc~0); 712431#L478-29 is_transmit4_triggered_~__retres1~4#1 := 0; 712425#L489-9 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 712417#is_transmit4_triggered_returnLabel#10 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 712410#L1067-27 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 712403#L1067-29 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 712396#L497-27 assume !(1 == ~t5_pc~0); 712390#L497-29 is_transmit5_triggered_~__retres1~5#1 := 0; 712382#L508-9 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 712377#is_transmit5_triggered_returnLabel#10 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 712365#L1075-27 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 712351#L1075-29 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 712350#L516-27 assume !(1 == ~t6_pc~0); 712348#L516-29 is_transmit6_triggered_~__retres1~6#1 := 0; 712340#L527-9 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 712336#is_transmit6_triggered_returnLabel#10 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 712330#L1083-27 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 712325#L1083-29 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 712254#L535-27 assume 1 == ~t7_pc~0; 712246#L536-9 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 712240#L546-9 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 712233#is_transmit7_triggered_returnLabel#10 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 712227#L1091-27 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 712221#L1091-29 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 712214#L554-27 assume !(1 == ~t8_pc~0); 712208#L554-29 is_transmit8_triggered_~__retres1~8#1 := 0; 712200#L565-9 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 712192#is_transmit8_triggered_returnLabel#10 activate_threads_#t~ret22#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 712112#L1099-27 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 712086#L1099-29 havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 712080#L931-3 assume 1 == ~M_E~0;~M_E~0 := 2; 661917#L931-5 assume !(1 == ~T1_E~0); 661914#L936-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 661911#L941-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 661908#L946-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 661905#L951-3 assume !(1 == ~T5_E~0); 661902#L956-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 661899#L961-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 661896#L966-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 661892#L971-3 assume 1 == ~E_1~0;~E_1~0 := 2; 661889#L976-3 assume 1 == ~E_2~0;~E_2~0 := 2; 661886#L981-3 assume 1 == ~E_3~0;~E_3~0 := 2; 661883#L986-3 assume 1 == ~E_4~0;~E_4~0 := 2; 661880#L991-3 assume !(1 == ~E_5~0); 661876#L996-3 assume 1 == ~E_6~0;~E_6~0 := 2; 661873#L1001-3 assume 1 == ~E_7~0;~E_7~0 := 2; 661870#L1006-3 assume 1 == ~E_8~0;~E_8~0 := 2; 661867#L1011-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 661805#L634-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 661794#L681-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 661790#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret24#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret24#1;havoc start_simulation_#t~ret24#1; 661785#L1291 assume !(0 == start_simulation_~tmp~3#1); 661781#L1291-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 661738#L634-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 661724#L681-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 661717#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret23#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret23#1;havoc stop_simulation_#t~ret23#1; 661711#L1246 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 661704#L1253 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 661698#stop_simulation_returnLabel#1 start_simulation_#t~ret25#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret25#1;havoc start_simulation_#t~ret25#1; 661692#L1304 assume !(0 != start_simulation_~tmp___0~1#1); 645405#L1272-2 [2023-11-06 21:59:02,876 INFO L145 PredicateUnifier]: Initialized classic predicate unifier [2023-11-06 21:59:02,877 INFO L85 PathProgramCache]: Analyzing trace with hash -1109770177, now seen corresponding path program 1 times [2023-11-06 21:59:02,877 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-06 21:59:02,877 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [925768535] [2023-11-06 21:59:02,877 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-06 21:59:02,877 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-06 21:59:02,890 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-06 21:59:02,939 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-06 21:59:02,940 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-06 21:59:02,940 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [925768535] [2023-11-06 21:59:02,940 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [925768535] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-06 21:59:02,940 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-06 21:59:02,940 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2023-11-06 21:59:02,940 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [778216568] [2023-11-06 21:59:02,941 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-06 21:59:02,941 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-06 21:59:02,941 INFO L145 PredicateUnifier]: Initialized classic predicate unifier [2023-11-06 21:59:02,941 INFO L85 PathProgramCache]: Analyzing trace with hash 1920503314, now seen corresponding path program 1 times [2023-11-06 21:59:02,942 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-06 21:59:02,942 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [752781749] [2023-11-06 21:59:02,942 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-06 21:59:02,942 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-06 21:59:02,955 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-06 21:59:03,008 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-06 21:59:03,008 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-06 21:59:03,008 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [752781749] [2023-11-06 21:59:03,008 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [752781749] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-06 21:59:03,008 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-06 21:59:03,009 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2023-11-06 21:59:03,009 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2101240654] [2023-11-06 21:59:03,009 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-06 21:59:03,009 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-06 21:59:03,010 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-06 21:59:03,010 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-06 21:59:03,010 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-06 21:59:03,010 INFO L87 Difference]: Start difference. First operand 124816 states and 175461 transitions. cyclomatic complexity: 50709 Second operand has 3 states, 3 states have (on average 34.666666666666664) internal successors, (104), 2 states have internal predecessors, (104), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-06 21:59:04,061 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-06 21:59:04,061 INFO L93 Difference]: Finished difference Result 124805 states and 174899 transitions. [2023-11-06 21:59:04,061 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 124805 states and 174899 transitions. [2023-11-06 21:59:04,648 INFO L131 ngComponentsAnalysis]: Automaton has 64 accepting balls. 124195 [2023-11-06 21:59:04,942 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 124805 states to 124805 states and 174899 transitions. [2023-11-06 21:59:04,942 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 124805 [2023-11-06 21:59:05,006 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 124805 [2023-11-06 21:59:05,006 INFO L73 IsDeterministic]: Start isDeterministic. Operand 124805 states and 174899 transitions. [2023-11-06 21:59:05,051 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-06 21:59:05,051 INFO L218 hiAutomatonCegarLoop]: Abstraction has 124805 states and 174899 transitions. [2023-11-06 21:59:05,134 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 124805 states and 174899 transitions. [2023-11-06 21:59:06,405 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 124805 to 64205. [2023-11-06 21:59:06,454 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 64205 states, 64205 states have (on average 1.3990810684526127) internal successors, (89828), 64204 states have internal predecessors, (89828), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-06 21:59:06,656 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 64205 states to 64205 states and 89828 transitions. [2023-11-06 21:59:06,656 INFO L240 hiAutomatonCegarLoop]: Abstraction has 64205 states and 89828 transitions. [2023-11-06 21:59:06,657 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-06 21:59:06,657 INFO L428 stractBuchiCegarLoop]: Abstraction has 64205 states and 89828 transitions. [2023-11-06 21:59:06,657 INFO L335 stractBuchiCegarLoop]: ======== Iteration 19 ============ [2023-11-06 21:59:06,657 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 64205 states and 89828 transitions. [2023-11-06 21:59:06,868 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 63847 [2023-11-06 21:59:06,868 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-06 21:59:06,868 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-06 21:59:06,871 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-06 21:59:06,871 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-06 21:59:06,871 INFO L748 eck$LassoCheckResult]: Stem: 894268#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2; 894269#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~10#1;havoc main_~__retres1~10#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; 894968#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret24#1, start_simulation_#t~ret25#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 894969#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 894971#L581 assume 1 == ~m_i~0;~m_st~0 := 0; 894382#L581-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 894383#L586-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 894963#L591-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 894955#L596-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 894460#L601-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 894461#L606-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 894717#L611-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 894718#L616-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 894550#L621-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 894551#L838 assume !(0 == ~M_E~0); 894728#L838-2 assume !(0 == ~T1_E~0); 894068#L843-1 assume !(0 == ~T2_E~0); 894069#L848-1 assume !(0 == ~T3_E~0); 894188#L853-1 assume !(0 == ~T4_E~0); 894539#L858-1 assume !(0 == ~T5_E~0); 894022#L863-1 assume !(0 == ~T6_E~0); 894023#L868-1 assume !(0 == ~T7_E~0); 895021#L873-1 assume !(0 == ~T8_E~0); 895018#L878-1 assume !(0 == ~E_1~0); 894997#L883-1 assume !(0 == ~E_2~0); 894998#L888-1 assume !(0 == ~E_3~0); 894687#L893-1 assume !(0 == ~E_4~0); 894688#L898-1 assume !(0 == ~E_5~0); 895043#L903-1 assume !(0 == ~E_6~0); 894994#L908-1 assume !(0 == ~E_7~0); 894826#L913-1 assume !(0 == ~E_8~0); 894081#L918-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 894082#L402 assume !(1 == ~m_pc~0); 894516#L402-2 is_master_triggered_~__retres1~0#1 := 0; 894213#L413 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 894214#is_master_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 894467#L1035 assume !(0 != activate_threads_~tmp~1#1); 894468#L1035-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 894525#L421 assume !(1 == ~t1_pc~0); 894986#L421-2 is_transmit1_triggered_~__retres1~1#1 := 0; 895024#L432 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 894083#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 894084#L1043 assume !(0 != activate_threads_~tmp___0~0#1); 894586#L1043-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 895036#L440 assume !(1 == ~t2_pc~0); 895082#L440-2 is_transmit2_triggered_~__retres1~2#1 := 0; 894223#L451 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 894224#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 894408#L1051 assume !(0 != activate_threads_~tmp___1~0#1); 894842#L1051-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 894416#L459 assume !(1 == ~t3_pc~0); 894417#L459-2 is_transmit3_triggered_~__retres1~3#1 := 0; 894983#L470 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 894042#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 894043#L1059 assume !(0 != activate_threads_~tmp___2~0#1); 894207#L1059-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 894217#L478 assume !(1 == ~t4_pc~0); 894218#L478-2 is_transmit4_triggered_~__retres1~4#1 := 0; 894898#L489 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 894159#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 894160#L1067 assume !(0 != activate_threads_~tmp___3~0#1); 894123#L1067-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 894124#L497 assume !(1 == ~t5_pc~0); 894170#L497-2 is_transmit5_triggered_~__retres1~5#1 := 0; 894171#L508 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 894767#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 894892#L1075 assume !(0 != activate_threads_~tmp___4~0#1); 894978#L1075-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 894979#L516 assume !(1 == ~t6_pc~0); 894912#L516-2 is_transmit6_triggered_~__retres1~6#1 := 0; 894716#L527 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 894392#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 894262#L1083 assume !(0 != activate_threads_~tmp___5~0#1); 894263#L1083-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 894705#L535 assume !(1 == ~t7_pc~0); 894706#L535-2 is_transmit7_triggered_~__retres1~7#1 := 0; 894781#L546 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 894782#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 894816#L1091 assume !(0 != activate_threads_~tmp___6~0#1); 894807#L1091-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 894808#L554 assume !(1 == ~t8_pc~0); 894044#L554-2 is_transmit8_triggered_~__retres1~8#1 := 0; 894045#L565 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 894834#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 894347#L1099 assume !(0 != activate_threads_~tmp___7~0#1); 894348#L1099-2 havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 894031#L931 assume !(1 == ~M_E~0); 894032#L931-2 assume !(1 == ~T1_E~0); 895011#L936-1 assume !(1 == ~T2_E~0); 895049#L941-1 assume !(1 == ~T3_E~0); 894526#L946-1 assume !(1 == ~T4_E~0); 894527#L951-1 assume !(1 == ~T5_E~0); 894277#L956-1 assume !(1 == ~T6_E~0); 894278#L961-1 assume !(1 == ~T7_E~0); 894689#L966-1 assume !(1 == ~T8_E~0); 894690#L971-1 assume 1 == ~E_1~0;~E_1~0 := 2; 894810#L976-1 assume !(1 == ~E_2~0); 894771#L981-1 assume !(1 == ~E_3~0); 894530#L986-1 assume !(1 == ~E_4~0); 894302#L991-1 assume !(1 == ~E_5~0); 894303#L996-1 assume !(1 == ~E_6~0); 895028#L1001-1 assume !(1 == ~E_7~0); 894737#L1006-1 assume !(1 == ~E_8~0); 894738#L1011-1 assume { :end_inline_reset_delta_events } true; 894984#L1272-2 [2023-11-06 21:59:06,872 INFO L750 eck$LassoCheckResult]: Loop: 894984#L1272-2 assume !false; 927419#L1273 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 927417#L813-1 assume !false; 927415#L692 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 927256#L634 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 927248#L681 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 927247#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 927245#L696 assume !(0 != eval_~tmp~0#1); 927246#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 927769#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 927767#L838-3 assume 0 == ~M_E~0;~M_E~0 := 1; 927764#L838-5 assume !(0 == ~T1_E~0); 927762#L843-3 assume !(0 == ~T2_E~0); 927760#L848-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 927758#L853-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 927756#L858-3 assume !(0 == ~T5_E~0); 927754#L863-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 927752#L868-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 927750#L873-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 927748#L878-3 assume !(0 == ~E_1~0); 927746#L883-3 assume 0 == ~E_2~0;~E_2~0 := 1; 927744#L888-3 assume 0 == ~E_3~0;~E_3~0 := 1; 927742#L893-3 assume 0 == ~E_4~0;~E_4~0 := 1; 927739#L898-3 assume !(0 == ~E_5~0); 927737#L903-3 assume 0 == ~E_6~0;~E_6~0 := 1; 927735#L908-3 assume 0 == ~E_7~0;~E_7~0 := 1; 927733#L913-3 assume 0 == ~E_8~0;~E_8~0 := 1; 927731#L918-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 927729#L402-27 assume !(1 == ~m_pc~0); 927727#L402-29 is_master_triggered_~__retres1~0#1 := 0; 927725#L413-9 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 927723#is_master_triggered_returnLabel#10 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 927721#L1035-27 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 927719#L1035-29 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 927717#L421-27 assume !(1 == ~t1_pc~0); 927715#L421-29 is_transmit1_triggered_~__retres1~1#1 := 0; 927713#L432-9 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 927711#is_transmit1_triggered_returnLabel#10 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 927709#L1043-27 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 927707#L1043-29 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 927705#L440-27 assume !(1 == ~t2_pc~0); 927703#L440-29 is_transmit2_triggered_~__retres1~2#1 := 0; 927701#L451-9 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 927699#is_transmit2_triggered_returnLabel#10 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 927697#L1051-27 assume !(0 != activate_threads_~tmp___1~0#1); 927695#L1051-29 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 927693#L459-27 assume 1 == ~t3_pc~0; 927691#L460-9 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 927692#L470-9 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 927776#is_transmit3_triggered_returnLabel#10 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 927682#L1059-27 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 927681#L1059-29 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 927680#L478-27 assume !(1 == ~t4_pc~0); 927679#L478-29 is_transmit4_triggered_~__retres1~4#1 := 0; 927678#L489-9 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 927677#is_transmit4_triggered_returnLabel#10 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 927676#L1067-27 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 927675#L1067-29 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 927674#L497-27 assume 1 == ~t5_pc~0; 927672#L498-9 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 927670#L508-9 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 927668#is_transmit5_triggered_returnLabel#10 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 927667#L1075-27 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 927666#L1075-29 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 927665#L516-27 assume !(1 == ~t6_pc~0); 927663#L516-29 is_transmit6_triggered_~__retres1~6#1 := 0; 927661#L527-9 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 927659#is_transmit6_triggered_returnLabel#10 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 927657#L1083-27 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 927655#L1083-29 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 927653#L535-27 assume 1 == ~t7_pc~0; 927650#L536-9 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 927649#L546-9 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 927647#is_transmit7_triggered_returnLabel#10 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 927645#L1091-27 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 927643#L1091-29 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 927641#L554-27 assume !(1 == ~t8_pc~0); 927639#L554-29 is_transmit8_triggered_~__retres1~8#1 := 0; 927637#L565-9 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 927635#is_transmit8_triggered_returnLabel#10 activate_threads_#t~ret22#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 927633#L1099-27 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 927631#L1099-29 havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 927629#L931-3 assume 1 == ~M_E~0;~M_E~0 := 2; 927627#L931-5 assume !(1 == ~T1_E~0); 927624#L936-3 assume !(1 == ~T2_E~0); 927622#L941-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 927620#L946-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 927617#L951-3 assume !(1 == ~T5_E~0); 927615#L956-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 927613#L961-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 927611#L966-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 927609#L971-3 assume 1 == ~E_1~0;~E_1~0 := 2; 927607#L976-3 assume 1 == ~E_2~0;~E_2~0 := 2; 927605#L981-3 assume 1 == ~E_3~0;~E_3~0 := 2; 927603#L986-3 assume 1 == ~E_4~0;~E_4~0 := 2; 927601#L991-3 assume !(1 == ~E_5~0); 927598#L996-3 assume 1 == ~E_6~0;~E_6~0 := 2; 927596#L1001-3 assume 1 == ~E_7~0;~E_7~0 := 2; 927594#L1006-3 assume 1 == ~E_8~0;~E_8~0 := 2; 927592#L1011-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 927584#L634-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 927575#L681-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 927573#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret24#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret24#1;havoc start_simulation_#t~ret24#1; 927570#L1291 assume !(0 == start_simulation_~tmp~3#1); 927567#L1291-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 927562#L634-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 927552#L681-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 927551#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret23#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret23#1;havoc stop_simulation_#t~ret23#1; 927550#L1246 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 927548#L1253 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 927546#stop_simulation_returnLabel#1 start_simulation_#t~ret25#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret25#1;havoc start_simulation_#t~ret25#1; 927544#L1304 assume !(0 != start_simulation_~tmp___0~1#1); 894984#L1272-2 [2023-11-06 21:59:06,873 INFO L145 PredicateUnifier]: Initialized classic predicate unifier [2023-11-06 21:59:06,873 INFO L85 PathProgramCache]: Analyzing trace with hash -2130838531, now seen corresponding path program 1 times [2023-11-06 21:59:06,873 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-06 21:59:06,873 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [248963302] [2023-11-06 21:59:06,874 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-06 21:59:06,874 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-06 21:59:06,889 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-06 21:59:06,954 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-06 21:59:06,955 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-06 21:59:06,955 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [248963302] [2023-11-06 21:59:06,955 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [248963302] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-06 21:59:06,955 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-06 21:59:06,956 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-06 21:59:06,956 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1036336225] [2023-11-06 21:59:06,956 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-06 21:59:06,957 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-06 21:59:06,958 INFO L145 PredicateUnifier]: Initialized classic predicate unifier [2023-11-06 21:59:06,958 INFO L85 PathProgramCache]: Analyzing trace with hash -1089241553, now seen corresponding path program 1 times [2023-11-06 21:59:06,958 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-06 21:59:06,958 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [660529308] [2023-11-06 21:59:06,958 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-06 21:59:06,959 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-06 21:59:06,976 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-06 21:59:07,006 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-06 21:59:07,006 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-06 21:59:07,007 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [660529308] [2023-11-06 21:59:07,007 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [660529308] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-06 21:59:07,007 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-06 21:59:07,007 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-06 21:59:07,007 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [585647392] [2023-11-06 21:59:07,008 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-06 21:59:07,009 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-06 21:59:07,009 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-06 21:59:07,009 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2023-11-06 21:59:07,010 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2023-11-06 21:59:07,010 INFO L87 Difference]: Start difference. First operand 64205 states and 89828 transitions. cyclomatic complexity: 25655 Second operand has 4 states, 4 states have (on average 26.0) internal successors, (104), 3 states have internal predecessors, (104), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-06 21:59:07,627 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-06 21:59:07,628 INFO L93 Difference]: Finished difference Result 135810 states and 189203 transitions. [2023-11-06 21:59:07,628 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 135810 states and 189203 transitions. [2023-11-06 21:59:08,847 INFO L131 ngComponentsAnalysis]: Automaton has 64 accepting balls. 135082 [2023-11-06 21:59:09,128 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 135810 states to 135810 states and 189203 transitions. [2023-11-06 21:59:09,128 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 135810 [2023-11-06 21:59:09,185 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 135810 [2023-11-06 21:59:09,185 INFO L73 IsDeterministic]: Start isDeterministic. Operand 135810 states and 189203 transitions. [2023-11-06 21:59:09,227 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-06 21:59:09,227 INFO L218 hiAutomatonCegarLoop]: Abstraction has 135810 states and 189203 transitions. [2023-11-06 21:59:09,288 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 135810 states and 189203 transitions. [2023-11-06 21:59:10,469 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 135810 to 72919. [2023-11-06 21:59:10,509 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 72919 states, 72919 states have (on average 1.3935325498155489) internal successors, (101615), 72918 states have internal predecessors, (101615), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-06 21:59:10,644 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 72919 states to 72919 states and 101615 transitions. [2023-11-06 21:59:10,644 INFO L240 hiAutomatonCegarLoop]: Abstraction has 72919 states and 101615 transitions. [2023-11-06 21:59:10,644 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2023-11-06 21:59:10,645 INFO L428 stractBuchiCegarLoop]: Abstraction has 72919 states and 101615 transitions. [2023-11-06 21:59:10,645 INFO L335 stractBuchiCegarLoop]: ======== Iteration 20 ============ [2023-11-06 21:59:10,645 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 72919 states and 101615 transitions. [2023-11-06 21:59:10,820 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 72483 [2023-11-06 21:59:10,820 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-06 21:59:10,820 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-06 21:59:10,822 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-06 21:59:10,822 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-06 21:59:10,822 INFO L748 eck$LassoCheckResult]: Stem: 1094292#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2; 1094293#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~10#1;havoc main_~__retres1~10#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; 1095027#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret24#1, start_simulation_#t~ret25#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 1095028#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 1095030#L581 assume 1 == ~m_i~0;~m_st~0 := 0; 1094407#L581-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 1094408#L586-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 1095022#L591-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 1095010#L596-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 1094488#L601-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 1094489#L606-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 1094752#L611-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 1094753#L616-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 1094576#L621-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 1094577#L838 assume !(0 == ~M_E~0); 1094760#L838-2 assume !(0 == ~T1_E~0); 1094090#L843-1 assume !(0 == ~T2_E~0); 1094091#L848-1 assume !(0 == ~T3_E~0); 1094209#L853-1 assume !(0 == ~T4_E~0); 1094563#L858-1 assume !(0 == ~T5_E~0); 1094047#L863-1 assume !(0 == ~T6_E~0); 1094048#L868-1 assume !(0 == ~T7_E~0); 1095087#L873-1 assume !(0 == ~T8_E~0); 1095084#L878-1 assume 0 == ~E_1~0;~E_1~0 := 1; 1095085#L883-1 assume !(0 == ~E_2~0); 1095116#L888-1 assume !(0 == ~E_3~0); 1095117#L893-1 assume !(0 == ~E_4~0); 1095114#L898-1 assume !(0 == ~E_5~0); 1095115#L903-1 assume !(0 == ~E_6~0); 1095173#L908-1 assume !(0 == ~E_7~0); 1095206#L913-1 assume !(0 == ~E_8~0); 1095205#L918-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1094882#L402 assume !(1 == ~m_pc~0); 1094883#L402-2 is_master_triggered_~__retres1~0#1 := 0; 1094235#L413 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1094236#is_master_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 1095204#L1035 assume !(0 != activate_threads_~tmp~1#1); 1094550#L1035-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1094551#L421 assume !(1 == ~t1_pc~0); 1095089#L421-2 is_transmit1_triggered_~__retres1~1#1 := 0; 1095090#L432 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1095203#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 1094609#L1043 assume !(0 != activate_threads_~tmp___0~0#1); 1094610#L1043-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1095202#L440 assume !(1 == ~t2_pc~0); 1095167#L440-2 is_transmit2_triggered_~__retres1~2#1 := 0; 1095168#L451 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1094436#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 1094437#L1051 assume !(0 != activate_threads_~tmp___1~0#1); 1094885#L1051-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1094886#L459 assume !(1 == ~t3_pc~0); 1095045#L459-2 is_transmit3_triggered_~__retres1~3#1 := 0; 1095046#L470 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1095103#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 1094228#L1059 assume !(0 != activate_threads_~tmp___2~0#1); 1094229#L1059-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1095176#L478 assume !(1 == ~t4_pc~0); 1094945#L478-2 is_transmit4_triggered_~__retres1~4#1 := 0; 1094946#L489 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1094181#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1094182#L1067 assume !(0 != activate_threads_~tmp___3~0#1); 1094143#L1067-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1094144#L497 assume !(1 == ~t5_pc~0); 1094192#L497-2 is_transmit5_triggered_~__retres1~5#1 := 0; 1094193#L508 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1094939#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1094940#L1075 assume !(0 != activate_threads_~tmp___4~0#1); 1095039#L1075-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1095040#L516 assume !(1 == ~t6_pc~0); 1094965#L516-2 is_transmit6_triggered_~__retres1~6#1 := 0; 1094966#L527 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1094419#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1094286#L1083 assume !(0 != activate_threads_~tmp___5~0#1); 1094287#L1083-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1094827#L535 assume !(1 == ~t7_pc~0); 1094995#L535-2 is_transmit7_triggered_~__retres1~7#1 := 0; 1094823#L546 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1094824#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1095191#L1091 assume !(0 != activate_threads_~tmp___6~0#1); 1095190#L1091-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 1095031#L554 assume !(1 == ~t8_pc~0); 1095032#L554-2 is_transmit8_triggered_~__retres1~8#1 := 0; 1095127#L565 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 1095128#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 1094372#L1099 assume !(0 != activate_threads_~tmp___7~0#1); 1094373#L1099-2 havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1094055#L931 assume !(1 == ~M_E~0); 1094056#L931-2 assume !(1 == ~T1_E~0); 1095123#L936-1 assume !(1 == ~T2_E~0); 1095124#L941-1 assume !(1 == ~T3_E~0); 1095166#L946-1 assume !(1 == ~T4_E~0); 1095047#L951-1 assume !(1 == ~T5_E~0); 1094302#L956-1 assume !(1 == ~T6_E~0); 1094303#L961-1 assume !(1 == ~T7_E~0); 1095160#L966-1 assume !(1 == ~T8_E~0); 1095184#L971-1 assume 1 == ~E_1~0;~E_1~0 := 2; 1094852#L976-1 assume !(1 == ~E_2~0); 1094813#L981-1 assume !(1 == ~E_3~0); 1094556#L986-1 assume !(1 == ~E_4~0); 1094328#L991-1 assume !(1 == ~E_5~0); 1094329#L996-1 assume !(1 == ~E_6~0); 1095095#L1001-1 assume !(1 == ~E_7~0); 1094774#L1006-1 assume !(1 == ~E_8~0); 1094775#L1011-1 assume { :end_inline_reset_delta_events } true; 1095048#L1272-2 [2023-11-06 21:59:10,823 INFO L750 eck$LassoCheckResult]: Loop: 1095048#L1272-2 assume !false; 1131420#L1273 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 1131419#L813-1 assume !false; 1131418#L692 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 1130431#L634 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 1130422#L681 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 1130420#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 1130417#L696 assume !(0 != eval_~tmp~0#1); 1130418#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 1131955#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 1131949#L838-3 assume 0 == ~M_E~0;~M_E~0 := 1; 1131943#L838-5 assume !(0 == ~T1_E~0); 1131937#L843-3 assume !(0 == ~T2_E~0); 1131931#L848-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 1131924#L853-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 1131917#L858-3 assume !(0 == ~T5_E~0); 1131909#L863-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 1131902#L868-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 1131896#L873-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 1131889#L878-3 assume 0 == ~E_1~0;~E_1~0 := 1; 1131888#L883-3 assume 0 == ~E_2~0;~E_2~0 := 1; 1131887#L888-3 assume 0 == ~E_3~0;~E_3~0 := 1; 1131886#L893-3 assume 0 == ~E_4~0;~E_4~0 := 1; 1131885#L898-3 assume !(0 == ~E_5~0); 1131884#L903-3 assume 0 == ~E_6~0;~E_6~0 := 1; 1131883#L908-3 assume 0 == ~E_7~0;~E_7~0 := 1; 1131882#L913-3 assume 0 == ~E_8~0;~E_8~0 := 1; 1131881#L918-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1131880#L402-27 assume !(1 == ~m_pc~0); 1131879#L402-29 is_master_triggered_~__retres1~0#1 := 0; 1131878#L413-9 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1131877#is_master_triggered_returnLabel#10 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 1131876#L1035-27 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 1131875#L1035-29 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1131874#L421-27 assume !(1 == ~t1_pc~0); 1131873#L421-29 is_transmit1_triggered_~__retres1~1#1 := 0; 1131872#L432-9 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1131871#is_transmit1_triggered_returnLabel#10 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 1131870#L1043-27 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 1131869#L1043-29 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1131868#L440-27 assume !(1 == ~t2_pc~0); 1131867#L440-29 is_transmit2_triggered_~__retres1~2#1 := 0; 1131866#L451-9 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1131865#is_transmit2_triggered_returnLabel#10 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 1131864#L1051-27 assume !(0 != activate_threads_~tmp___1~0#1); 1131863#L1051-29 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1131862#L459-27 assume !(1 == ~t3_pc~0); 1131861#L459-29 is_transmit3_triggered_~__retres1~3#1 := 0; 1131859#L470-9 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1131857#is_transmit3_triggered_returnLabel#10 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 1131855#L1059-27 assume !(0 != activate_threads_~tmp___2~0#1); 1131853#L1059-29 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1131852#L478-27 assume !(1 == ~t4_pc~0); 1131851#L478-29 is_transmit4_triggered_~__retres1~4#1 := 0; 1131850#L489-9 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1131849#is_transmit4_triggered_returnLabel#10 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1131848#L1067-27 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 1131847#L1067-29 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1131846#L497-27 assume !(1 == ~t5_pc~0); 1131845#L497-29 is_transmit5_triggered_~__retres1~5#1 := 0; 1131843#L508-9 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1131842#is_transmit5_triggered_returnLabel#10 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1131841#L1075-27 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 1131840#L1075-29 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1131839#L516-27 assume !(1 == ~t6_pc~0); 1131838#L516-29 is_transmit6_triggered_~__retres1~6#1 := 0; 1131837#L527-9 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1131836#is_transmit6_triggered_returnLabel#10 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1131835#L1083-27 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 1131834#L1083-29 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1131833#L535-27 assume 1 == ~t7_pc~0; 1131831#L536-9 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 1131830#L546-9 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1131829#is_transmit7_triggered_returnLabel#10 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1131828#L1091-27 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 1131827#L1091-29 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 1131826#L554-27 assume !(1 == ~t8_pc~0); 1131825#L554-29 is_transmit8_triggered_~__retres1~8#1 := 0; 1131824#L565-9 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 1131823#is_transmit8_triggered_returnLabel#10 activate_threads_#t~ret22#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 1131822#L1099-27 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 1131821#L1099-29 havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1131820#L931-3 assume 1 == ~M_E~0;~M_E~0 := 2; 1131819#L931-5 assume !(1 == ~T1_E~0); 1131818#L936-3 assume !(1 == ~T2_E~0); 1131817#L941-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 1131816#L946-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 1131815#L951-3 assume !(1 == ~T5_E~0); 1131814#L956-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 1131813#L961-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 1131812#L966-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 1131810#L971-3 assume 1 == ~E_1~0;~E_1~0 := 2; 1131805#L976-3 assume 1 == ~E_2~0;~E_2~0 := 2; 1131800#L981-3 assume 1 == ~E_3~0;~E_3~0 := 2; 1131795#L986-3 assume 1 == ~E_4~0;~E_4~0 := 2; 1131790#L991-3 assume !(1 == ~E_5~0); 1131784#L996-3 assume 1 == ~E_6~0;~E_6~0 := 2; 1131778#L1001-3 assume 1 == ~E_7~0;~E_7~0 := 2; 1131771#L1006-3 assume 1 == ~E_8~0;~E_8~0 := 2; 1131768#L1011-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 1131724#L634-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 1131712#L681-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 1131707#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret24#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret24#1;havoc start_simulation_#t~ret24#1; 1131702#L1291 assume !(0 == start_simulation_~tmp~3#1); 1131699#L1291-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 1131516#L634-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 1131505#L681-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 1131503#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret23#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret23#1;havoc stop_simulation_#t~ret23#1; 1131501#L1246 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 1131488#L1253 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 1131483#stop_simulation_returnLabel#1 start_simulation_#t~ret25#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret25#1;havoc start_simulation_#t~ret25#1; 1131477#L1304 assume !(0 != start_simulation_~tmp___0~1#1); 1095048#L1272-2 [2023-11-06 21:59:10,823 INFO L145 PredicateUnifier]: Initialized classic predicate unifier [2023-11-06 21:59:10,824 INFO L85 PathProgramCache]: Analyzing trace with hash -1073000453, now seen corresponding path program 1 times [2023-11-06 21:59:10,824 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-06 21:59:10,824 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1145434576] [2023-11-06 21:59:10,824 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-06 21:59:10,824 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-06 21:59:10,835 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-06 21:59:10,875 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-06 21:59:10,876 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-06 21:59:10,876 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1145434576] [2023-11-06 21:59:10,876 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1145434576] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-06 21:59:10,876 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-06 21:59:10,876 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-06 21:59:10,876 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1048952323] [2023-11-06 21:59:10,877 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-06 21:59:10,877 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-06 21:59:10,877 INFO L145 PredicateUnifier]: Initialized classic predicate unifier [2023-11-06 21:59:10,878 INFO L85 PathProgramCache]: Analyzing trace with hash -601633623, now seen corresponding path program 1 times [2023-11-06 21:59:10,878 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-06 21:59:10,878 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1148148587] [2023-11-06 21:59:10,878 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-06 21:59:10,878 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-06 21:59:10,890 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-06 21:59:10,934 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-06 21:59:10,935 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-06 21:59:10,935 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1148148587] [2023-11-06 21:59:10,935 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1148148587] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-06 21:59:10,935 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-06 21:59:10,935 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2023-11-06 21:59:10,935 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1177531412] [2023-11-06 21:59:10,936 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-06 21:59:10,936 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-06 21:59:10,936 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-06 21:59:10,936 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2023-11-06 21:59:10,937 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2023-11-06 21:59:10,937 INFO L87 Difference]: Start difference. First operand 72919 states and 101615 transitions. cyclomatic complexity: 28728 Second operand has 4 states, 4 states have (on average 26.0) internal successors, (104), 3 states have internal predecessors, (104), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-06 21:59:11,291 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-06 21:59:11,291 INFO L93 Difference]: Finished difference Result 84109 states and 117236 transitions. [2023-11-06 21:59:11,291 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 84109 states and 117236 transitions. [2023-11-06 21:59:11,619 INFO L131 ngComponentsAnalysis]: Automaton has 36 accepting balls. 83655 [2023-11-06 21:59:12,478 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 84109 states to 84109 states and 117236 transitions. [2023-11-06 21:59:12,479 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 84109 [2023-11-06 21:59:12,505 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 84109 [2023-11-06 21:59:12,505 INFO L73 IsDeterministic]: Start isDeterministic. Operand 84109 states and 117236 transitions. [2023-11-06 21:59:12,528 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-06 21:59:12,528 INFO L218 hiAutomatonCegarLoop]: Abstraction has 84109 states and 117236 transitions. [2023-11-06 21:59:12,562 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 84109 states and 117236 transitions. [2023-11-06 21:59:12,997 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 84109 to 64205. [2023-11-06 21:59:13,032 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 64205 states, 64205 states have (on average 1.389985203644576) internal successors, (89244), 64204 states have internal predecessors, (89244), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-06 21:59:13,145 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 64205 states to 64205 states and 89244 transitions. [2023-11-06 21:59:13,145 INFO L240 hiAutomatonCegarLoop]: Abstraction has 64205 states and 89244 transitions. [2023-11-06 21:59:13,146 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2023-11-06 21:59:13,146 INFO L428 stractBuchiCegarLoop]: Abstraction has 64205 states and 89244 transitions. [2023-11-06 21:59:13,146 INFO L335 stractBuchiCegarLoop]: ======== Iteration 21 ============ [2023-11-06 21:59:13,146 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 64205 states and 89244 transitions. [2023-11-06 21:59:13,300 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 63847 [2023-11-06 21:59:13,300 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-06 21:59:13,300 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-06 21:59:13,301 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-06 21:59:13,301 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-06 21:59:13,302 INFO L748 eck$LassoCheckResult]: Stem: 1251330#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2; 1251331#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~10#1;havoc main_~__retres1~10#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; 1252046#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret24#1, start_simulation_#t~ret25#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 1252047#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 1252049#L581 assume 1 == ~m_i~0;~m_st~0 := 0; 1251442#L581-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 1251443#L586-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 1252040#L591-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 1252028#L596-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 1251526#L601-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 1251527#L606-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 1251781#L611-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 1251782#L616-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 1251616#L621-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 1251617#L838 assume !(0 == ~M_E~0); 1251791#L838-2 assume !(0 == ~T1_E~0); 1251131#L843-1 assume !(0 == ~T2_E~0); 1251132#L848-1 assume !(0 == ~T3_E~0); 1251249#L853-1 assume !(0 == ~T4_E~0); 1251605#L858-1 assume !(0 == ~T5_E~0); 1251087#L863-1 assume !(0 == ~T6_E~0); 1251088#L868-1 assume !(0 == ~T7_E~0); 1252098#L873-1 assume !(0 == ~T8_E~0); 1252093#L878-1 assume !(0 == ~E_1~0); 1252077#L883-1 assume !(0 == ~E_2~0); 1252078#L888-1 assume !(0 == ~E_3~0); 1251750#L893-1 assume !(0 == ~E_4~0); 1251751#L898-1 assume !(0 == ~E_5~0); 1252120#L903-1 assume !(0 == ~E_6~0); 1252074#L908-1 assume !(0 == ~E_7~0); 1251893#L913-1 assume !(0 == ~E_8~0); 1251144#L918-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1251145#L402 assume !(1 == ~m_pc~0); 1251580#L402-2 is_master_triggered_~__retres1~0#1 := 0; 1251276#L413 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1251277#is_master_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 1251534#L1035 assume !(0 != activate_threads_~tmp~1#1); 1251535#L1035-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1251590#L421 assume !(1 == ~t1_pc~0); 1252065#L421-2 is_transmit1_triggered_~__retres1~1#1 := 0; 1252102#L432 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1251146#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 1251147#L1043 assume !(0 != activate_threads_~tmp___0~0#1); 1251647#L1043-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1252114#L440 assume !(1 == ~t2_pc~0); 1252161#L440-2 is_transmit2_triggered_~__retres1~2#1 := 0; 1251286#L451 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1251287#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 1251470#L1051 assume !(0 != activate_threads_~tmp___1~0#1); 1251910#L1051-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1251479#L459 assume !(1 == ~t3_pc~0); 1251480#L459-2 is_transmit3_triggered_~__retres1~3#1 := 0; 1252062#L470 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1251105#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 1251106#L1059 assume !(0 != activate_threads_~tmp___2~0#1); 1251270#L1059-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1251280#L478 assume !(1 == ~t4_pc~0); 1251281#L478-2 is_transmit4_triggered_~__retres1~4#1 := 0; 1251968#L489 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1251221#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1251222#L1067 assume !(0 != activate_threads_~tmp___3~0#1); 1251186#L1067-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1251187#L497 assume !(1 == ~t5_pc~0); 1251232#L497-2 is_transmit5_triggered_~__retres1~5#1 := 0; 1251233#L508 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1251831#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1251963#L1075 assume !(0 != activate_threads_~tmp___4~0#1); 1252056#L1075-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1252057#L516 assume !(1 == ~t6_pc~0); 1251986#L516-2 is_transmit6_triggered_~__retres1~6#1 := 0; 1251780#L527 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1251452#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1251324#L1083 assume !(0 != activate_threads_~tmp___5~0#1); 1251325#L1083-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1251769#L535 assume !(1 == ~t7_pc~0); 1251770#L535-2 is_transmit7_triggered_~__retres1~7#1 := 0; 1251845#L546 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1251846#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1251884#L1091 assume !(0 != activate_threads_~tmp___6~0#1); 1251875#L1091-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 1251876#L554 assume !(1 == ~t8_pc~0); 1251107#L554-2 is_transmit8_triggered_~__retres1~8#1 := 0; 1251108#L565 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 1251904#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 1251409#L1099 assume !(0 != activate_threads_~tmp___7~0#1); 1251410#L1099-2 havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1251095#L931 assume !(1 == ~M_E~0); 1251096#L931-2 assume !(1 == ~T1_E~0); 1252087#L936-1 assume !(1 == ~T2_E~0); 1252128#L941-1 assume !(1 == ~T3_E~0); 1251591#L946-1 assume !(1 == ~T4_E~0); 1251592#L951-1 assume !(1 == ~T5_E~0); 1251339#L956-1 assume !(1 == ~T6_E~0); 1251340#L961-1 assume !(1 == ~T7_E~0); 1251752#L966-1 assume !(1 == ~T8_E~0); 1251753#L971-1 assume !(1 == ~E_1~0); 1251878#L976-1 assume !(1 == ~E_2~0); 1251835#L981-1 assume !(1 == ~E_3~0); 1251596#L986-1 assume !(1 == ~E_4~0); 1251364#L991-1 assume !(1 == ~E_5~0); 1251365#L996-1 assume !(1 == ~E_6~0); 1252106#L1001-1 assume !(1 == ~E_7~0); 1251802#L1006-1 assume !(1 == ~E_8~0); 1251803#L1011-1 assume { :end_inline_reset_delta_events } true; 1252063#L1272-2 [2023-11-06 21:59:13,302 INFO L750 eck$LassoCheckResult]: Loop: 1252063#L1272-2 assume !false; 1279106#L1273 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 1279105#L813-1 assume !false; 1279104#L692 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 1279102#L634 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 1279094#L681 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 1279093#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 1279091#L696 assume !(0 != eval_~tmp~0#1); 1279092#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 1271565#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 1271566#L838-3 assume 0 == ~M_E~0;~M_E~0 := 1; 1271561#L838-5 assume !(0 == ~T1_E~0); 1271562#L843-3 assume !(0 == ~T2_E~0); 1271557#L848-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 1271558#L853-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 1271553#L858-3 assume !(0 == ~T5_E~0); 1271554#L863-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 1271549#L868-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 1271550#L873-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 1271545#L878-3 assume !(0 == ~E_1~0); 1271546#L883-3 assume 0 == ~E_2~0;~E_2~0 := 1; 1271541#L888-3 assume 0 == ~E_3~0;~E_3~0 := 1; 1271542#L893-3 assume 0 == ~E_4~0;~E_4~0 := 1; 1271537#L898-3 assume !(0 == ~E_5~0); 1271538#L903-3 assume 0 == ~E_6~0;~E_6~0 := 1; 1271533#L908-3 assume 0 == ~E_7~0;~E_7~0 := 1; 1271534#L913-3 assume 0 == ~E_8~0;~E_8~0 := 1; 1271529#L918-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1271530#L402-27 assume !(1 == ~m_pc~0); 1271524#L402-29 is_master_triggered_~__retres1~0#1 := 0; 1271525#L413-9 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1271518#is_master_triggered_returnLabel#10 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 1271519#L1035-27 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 1271512#L1035-29 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1271513#L421-27 assume !(1 == ~t1_pc~0); 1271507#L421-29 is_transmit1_triggered_~__retres1~1#1 := 0; 1271508#L432-9 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1271502#is_transmit1_triggered_returnLabel#10 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 1271503#L1043-27 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 1271496#L1043-29 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1271497#L440-27 assume !(1 == ~t2_pc~0); 1261244#L440-29 is_transmit2_triggered_~__retres1~2#1 := 0; 1261245#L451-9 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1271420#is_transmit2_triggered_returnLabel#10 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 1271421#L1051-27 assume !(0 != activate_threads_~tmp___1~0#1); 1271414#L1051-29 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1271415#L459-27 assume 1 == ~t3_pc~0; 1261227#L460-9 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 1261228#L470-9 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1261273#is_transmit3_triggered_returnLabel#10 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 1261274#L1059-27 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 1261211#L1059-29 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1261212#L478-27 assume !(1 == ~t4_pc~0); 1261203#L478-29 is_transmit4_triggered_~__retres1~4#1 := 0; 1261204#L489-9 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1261197#is_transmit4_triggered_returnLabel#10 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1261198#L1067-27 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 1261190#L1067-29 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1261191#L497-27 assume !(1 == ~t5_pc~0); 1261184#L497-29 is_transmit5_triggered_~__retres1~5#1 := 0; 1261183#L508-9 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1261176#is_transmit5_triggered_returnLabel#10 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1261177#L1075-27 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 1261170#L1075-29 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1261171#L516-27 assume !(1 == ~t6_pc~0); 1261164#L516-29 is_transmit6_triggered_~__retres1~6#1 := 0; 1261165#L527-9 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1261157#is_transmit6_triggered_returnLabel#10 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1261158#L1083-27 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 1271328#L1083-29 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1271329#L535-27 assume !(1 == ~t7_pc~0); 1271323#L535-29 is_transmit7_triggered_~__retres1~7#1 := 0; 1271322#L546-9 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1271317#is_transmit7_triggered_returnLabel#10 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1271318#L1091-27 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 1271313#L1091-29 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 1271314#L554-27 assume !(1 == ~t8_pc~0); 1271309#L554-29 is_transmit8_triggered_~__retres1~8#1 := 0; 1271310#L565-9 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 1271305#is_transmit8_triggered_returnLabel#10 activate_threads_#t~ret22#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 1271306#L1099-27 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 1271301#L1099-29 havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1271302#L931-3 assume 1 == ~M_E~0;~M_E~0 := 2; 1271297#L931-5 assume !(1 == ~T1_E~0); 1271298#L936-3 assume !(1 == ~T2_E~0); 1271293#L941-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 1271294#L946-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 1271289#L951-3 assume !(1 == ~T5_E~0); 1271290#L956-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 1271285#L961-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 1271286#L966-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 1271281#L971-3 assume !(1 == ~E_1~0); 1271282#L976-3 assume 1 == ~E_2~0;~E_2~0 := 2; 1271277#L981-3 assume 1 == ~E_3~0;~E_3~0 := 2; 1271278#L986-3 assume 1 == ~E_4~0;~E_4~0 := 2; 1271273#L991-3 assume !(1 == ~E_5~0); 1271274#L996-3 assume 1 == ~E_6~0;~E_6~0 := 2; 1261064#L1001-3 assume 1 == ~E_7~0;~E_7~0 := 2; 1261065#L1006-3 assume 1 == ~E_8~0;~E_8~0 := 2; 1261058#L1011-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 1261059#L634-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 1279327#L681-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 1279326#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret24#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret24#1;havoc start_simulation_#t~ret24#1; 1279324#L1291 assume !(0 == start_simulation_~tmp~3#1); 1279322#L1291-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 1279321#L634-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 1279312#L681-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 1279311#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret23#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret23#1;havoc stop_simulation_#t~ret23#1; 1279310#L1246 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 1279309#L1253 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 1279308#stop_simulation_returnLabel#1 start_simulation_#t~ret25#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret25#1;havoc start_simulation_#t~ret25#1; 1279307#L1304 assume !(0 != start_simulation_~tmp___0~1#1); 1252063#L1272-2 [2023-11-06 21:59:13,303 INFO L145 PredicateUnifier]: Initialized classic predicate unifier [2023-11-06 21:59:13,303 INFO L85 PathProgramCache]: Analyzing trace with hash -1450780161, now seen corresponding path program 1 times [2023-11-06 21:59:13,303 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-06 21:59:13,303 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1985428899] [2023-11-06 21:59:13,304 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-06 21:59:13,304 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-06 21:59:13,316 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-06 21:59:13,317 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-06 21:59:13,325 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-06 21:59:13,403 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-06 21:59:13,404 INFO L145 PredicateUnifier]: Initialized classic predicate unifier [2023-11-06 21:59:13,404 INFO L85 PathProgramCache]: Analyzing trace with hash 1575714415, now seen corresponding path program 1 times [2023-11-06 21:59:13,404 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-06 21:59:13,405 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [617233933] [2023-11-06 21:59:13,405 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-06 21:59:13,405 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-06 21:59:13,425 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-06 21:59:13,478 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-06 21:59:13,478 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-06 21:59:13,479 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [617233933] [2023-11-06 21:59:13,479 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [617233933] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-06 21:59:13,479 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-06 21:59:13,479 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2023-11-06 21:59:13,479 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [312001091] [2023-11-06 21:59:13,479 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-06 21:59:13,480 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-06 21:59:13,480 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-06 21:59:13,480 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2023-11-06 21:59:13,480 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2023-11-06 21:59:13,481 INFO L87 Difference]: Start difference. First operand 64205 states and 89244 transitions. cyclomatic complexity: 25071 Second operand has 5 states, 5 states have (on average 22.4) internal successors, (112), 5 states have internal predecessors, (112), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-06 21:59:14,479 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-06 21:59:14,479 INFO L93 Difference]: Finished difference Result 116172 states and 159377 transitions. [2023-11-06 21:59:14,480 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 116172 states and 159377 transitions. [2023-11-06 21:59:14,994 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 115566 [2023-11-06 21:59:15,310 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 116172 states to 116172 states and 159377 transitions. [2023-11-06 21:59:15,311 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 116172 [2023-11-06 21:59:15,371 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 116172 [2023-11-06 21:59:15,371 INFO L73 IsDeterministic]: Start isDeterministic. Operand 116172 states and 159377 transitions. [2023-11-06 21:59:15,424 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-06 21:59:15,425 INFO L218 hiAutomatonCegarLoop]: Abstraction has 116172 states and 159377 transitions. [2023-11-06 21:59:15,491 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 116172 states and 159377 transitions. [2023-11-06 21:59:16,756 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 116172 to 64529. [2023-11-06 21:59:16,795 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 64529 states, 64529 states have (on average 1.3880270885958252) internal successors, (89568), 64528 states have internal predecessors, (89568), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-06 21:59:16,929 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 64529 states to 64529 states and 89568 transitions. [2023-11-06 21:59:16,929 INFO L240 hiAutomatonCegarLoop]: Abstraction has 64529 states and 89568 transitions. [2023-11-06 21:59:16,929 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 9 states. [2023-11-06 21:59:16,930 INFO L428 stractBuchiCegarLoop]: Abstraction has 64529 states and 89568 transitions. [2023-11-06 21:59:16,930 INFO L335 stractBuchiCegarLoop]: ======== Iteration 22 ============ [2023-11-06 21:59:16,930 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 64529 states and 89568 transitions. [2023-11-06 21:59:17,096 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 64171 [2023-11-06 21:59:17,096 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-06 21:59:17,096 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-06 21:59:17,098 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-06 21:59:17,098 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-06 21:59:17,099 INFO L748 eck$LassoCheckResult]: Stem: 1431726#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2; 1431727#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~10#1;havoc main_~__retres1~10#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; 1432459#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret24#1, start_simulation_#t~ret25#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 1432460#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 1432462#L581 assume 1 == ~m_i~0;~m_st~0 := 0; 1431839#L581-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 1431840#L586-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 1432456#L591-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 1432445#L596-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 1431920#L601-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 1431921#L606-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 1432184#L611-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 1432185#L616-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 1432008#L621-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 1432009#L838 assume !(0 == ~M_E~0); 1432196#L838-2 assume !(0 == ~T1_E~0); 1431524#L843-1 assume !(0 == ~T2_E~0); 1431525#L848-1 assume !(0 == ~T3_E~0); 1431642#L853-1 assume !(0 == ~T4_E~0); 1431994#L858-1 assume !(0 == ~T5_E~0); 1431479#L863-1 assume !(0 == ~T6_E~0); 1431480#L868-1 assume !(0 == ~T7_E~0); 1432521#L873-1 assume !(0 == ~T8_E~0); 1432517#L878-1 assume !(0 == ~E_1~0); 1432489#L883-1 assume !(0 == ~E_2~0); 1432490#L888-1 assume !(0 == ~E_3~0); 1432154#L893-1 assume !(0 == ~E_4~0); 1432155#L898-1 assume !(0 == ~E_5~0); 1432543#L903-1 assume !(0 == ~E_6~0); 1432487#L908-1 assume !(0 == ~E_7~0); 1432307#L913-1 assume !(0 == ~E_8~0); 1431536#L918-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1431537#L402 assume !(1 == ~m_pc~0); 1431974#L402-2 is_master_triggered_~__retres1~0#1 := 0; 1431669#L413 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1431670#is_master_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 1431927#L1035 assume !(0 != activate_threads_~tmp~1#1); 1431928#L1035-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1431982#L421 assume !(1 == ~t1_pc~0); 1432477#L421-2 is_transmit1_triggered_~__retres1~1#1 := 0; 1432522#L432 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1431539#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 1431540#L1043 assume !(0 != activate_threads_~tmp___0~0#1); 1432042#L1043-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1432534#L440 assume !(1 == ~t2_pc~0); 1432596#L440-2 is_transmit2_triggered_~__retres1~2#1 := 0; 1431679#L451 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1431680#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 1431867#L1051 assume !(0 != activate_threads_~tmp___1~0#1); 1432327#L1051-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1431870#L459 assume !(1 == ~t3_pc~0); 1431871#L459-2 is_transmit3_triggered_~__retres1~3#1 := 0; 1432474#L470 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1431499#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 1431500#L1059 assume !(0 != activate_threads_~tmp___2~0#1); 1431663#L1059-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1431673#L478 assume !(1 == ~t4_pc~0); 1431674#L478-2 is_transmit4_triggered_~__retres1~4#1 := 0; 1432382#L489 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1431614#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1431615#L1067 assume !(0 != activate_threads_~tmp___3~0#1); 1431577#L1067-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1431578#L497 assume !(1 == ~t5_pc~0); 1431625#L497-2 is_transmit5_triggered_~__retres1~5#1 := 0; 1431626#L508 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1432241#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1432377#L1075 assume !(0 != activate_threads_~tmp___4~0#1); 1432469#L1075-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1432470#L516 assume !(1 == ~t6_pc~0); 1432395#L516-2 is_transmit6_triggered_~__retres1~6#1 := 0; 1432183#L527 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1431849#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1431720#L1083 assume !(0 != activate_threads_~tmp___5~0#1); 1431721#L1083-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1432172#L535 assume !(1 == ~t7_pc~0); 1432173#L535-2 is_transmit7_triggered_~__retres1~7#1 := 0; 1432257#L546 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1432258#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1432299#L1091 assume !(0 != activate_threads_~tmp___6~0#1); 1432288#L1091-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 1432289#L554 assume !(1 == ~t8_pc~0); 1431501#L554-2 is_transmit8_triggered_~__retres1~8#1 := 0; 1431502#L565 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 1432318#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 1431803#L1099 assume !(0 != activate_threads_~tmp___7~0#1); 1431804#L1099-2 havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1431489#L931 assume !(1 == ~M_E~0); 1431490#L931-2 assume !(1 == ~T1_E~0); 1432509#L936-1 assume !(1 == ~T2_E~0); 1432553#L941-1 assume !(1 == ~T3_E~0); 1431983#L946-1 assume !(1 == ~T4_E~0); 1431984#L951-1 assume !(1 == ~T5_E~0); 1431735#L956-1 assume !(1 == ~T6_E~0); 1431736#L961-1 assume !(1 == ~T7_E~0); 1432156#L966-1 assume !(1 == ~T8_E~0); 1432157#L971-1 assume !(1 == ~E_1~0); 1432291#L976-1 assume !(1 == ~E_2~0); 1432247#L981-1 assume !(1 == ~E_3~0); 1431987#L986-1 assume !(1 == ~E_4~0); 1431761#L991-1 assume !(1 == ~E_5~0); 1431762#L996-1 assume !(1 == ~E_6~0); 1432528#L1001-1 assume !(1 == ~E_7~0); 1432211#L1006-1 assume !(1 == ~E_8~0); 1432212#L1011-1 assume { :end_inline_reset_delta_events } true; 1432475#L1272-2 [2023-11-06 21:59:17,099 INFO L750 eck$LassoCheckResult]: Loop: 1432475#L1272-2 assume !false; 1466148#L1273 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 1465218#L813-1 assume !false; 1465196#L692 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 1465194#L634 assume !(0 == ~m_st~0); 1465195#L638 assume !(0 == ~t1_st~0); 1465188#L642 assume !(0 == ~t2_st~0); 1465189#L646 assume !(0 == ~t3_st~0); 1465193#L650 assume !(0 == ~t4_st~0); 1465186#L654 assume !(0 == ~t5_st~0); 1465187#L658 assume !(0 == ~t6_st~0); 1465192#L662 assume !(0 == ~t7_st~0); 1465190#L666 assume !(0 == ~t8_st~0);exists_runnable_thread_~__retres1~9#1 := 0; 1465191#L681 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 1463219#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 1463220#L696 assume !(0 != eval_~tmp~0#1); 1466298#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 1466297#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 1466296#L838-3 assume 0 == ~M_E~0;~M_E~0 := 1; 1466295#L838-5 assume !(0 == ~T1_E~0); 1466294#L843-3 assume !(0 == ~T2_E~0); 1466293#L848-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 1466292#L853-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 1466291#L858-3 assume !(0 == ~T5_E~0); 1466290#L863-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 1466289#L868-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 1466288#L873-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 1466287#L878-3 assume !(0 == ~E_1~0); 1466286#L883-3 assume 0 == ~E_2~0;~E_2~0 := 1; 1466285#L888-3 assume 0 == ~E_3~0;~E_3~0 := 1; 1466284#L893-3 assume 0 == ~E_4~0;~E_4~0 := 1; 1466283#L898-3 assume !(0 == ~E_5~0); 1466282#L903-3 assume 0 == ~E_6~0;~E_6~0 := 1; 1466281#L908-3 assume 0 == ~E_7~0;~E_7~0 := 1; 1466280#L913-3 assume 0 == ~E_8~0;~E_8~0 := 1; 1466279#L918-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1466278#L402-27 assume !(1 == ~m_pc~0); 1466277#L402-29 is_master_triggered_~__retres1~0#1 := 0; 1466276#L413-9 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1466275#is_master_triggered_returnLabel#10 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 1466274#L1035-27 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 1466273#L1035-29 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1466272#L421-27 assume !(1 == ~t1_pc~0); 1466271#L421-29 is_transmit1_triggered_~__retres1~1#1 := 0; 1466270#L432-9 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1466269#is_transmit1_triggered_returnLabel#10 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 1466268#L1043-27 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 1466267#L1043-29 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1466266#L440-27 assume !(1 == ~t2_pc~0); 1466265#L440-29 is_transmit2_triggered_~__retres1~2#1 := 0; 1466264#L451-9 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1466263#is_transmit2_triggered_returnLabel#10 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 1466262#L1051-27 assume !(0 != activate_threads_~tmp___1~0#1); 1466261#L1051-29 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1466260#L459-27 assume 1 == ~t3_pc~0; 1466258#L460-9 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 1466256#L470-9 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1466254#is_transmit3_triggered_returnLabel#10 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 1466252#L1059-27 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 1466251#L1059-29 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1466250#L478-27 assume !(1 == ~t4_pc~0); 1466249#L478-29 is_transmit4_triggered_~__retres1~4#1 := 0; 1466248#L489-9 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1466247#is_transmit4_triggered_returnLabel#10 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1466246#L1067-27 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 1466245#L1067-29 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1466244#L497-27 assume 1 == ~t5_pc~0; 1466242#L498-9 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 1466241#L508-9 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1466240#is_transmit5_triggered_returnLabel#10 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1466239#L1075-27 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 1466238#L1075-29 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1466237#L516-27 assume !(1 == ~t6_pc~0); 1466236#L516-29 is_transmit6_triggered_~__retres1~6#1 := 0; 1466235#L527-9 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1466234#is_transmit6_triggered_returnLabel#10 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1466233#L1083-27 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 1466232#L1083-29 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1466231#L535-27 assume !(1 == ~t7_pc~0); 1466230#L535-29 is_transmit7_triggered_~__retres1~7#1 := 0; 1466228#L546-9 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1466227#is_transmit7_triggered_returnLabel#10 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1466226#L1091-27 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 1466225#L1091-29 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 1466224#L554-27 assume !(1 == ~t8_pc~0); 1466223#L554-29 is_transmit8_triggered_~__retres1~8#1 := 0; 1466222#L565-9 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 1466221#is_transmit8_triggered_returnLabel#10 activate_threads_#t~ret22#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 1466220#L1099-27 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 1466219#L1099-29 havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1466218#L931-3 assume 1 == ~M_E~0;~M_E~0 := 2; 1466217#L931-5 assume !(1 == ~T1_E~0); 1466216#L936-3 assume !(1 == ~T2_E~0); 1466215#L941-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 1466214#L946-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 1466213#L951-3 assume !(1 == ~T5_E~0); 1466212#L956-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 1466211#L961-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 1466210#L966-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 1466209#L971-3 assume !(1 == ~E_1~0); 1466208#L976-3 assume 1 == ~E_2~0;~E_2~0 := 2; 1466207#L981-3 assume 1 == ~E_3~0;~E_3~0 := 2; 1466206#L986-3 assume 1 == ~E_4~0;~E_4~0 := 2; 1466205#L991-3 assume !(1 == ~E_5~0); 1466204#L996-3 assume 1 == ~E_6~0;~E_6~0 := 2; 1466203#L1001-3 assume 1 == ~E_7~0;~E_7~0 := 2; 1466202#L1006-3 assume 1 == ~E_8~0;~E_8~0 := 2; 1466201#L1011-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 1466199#L634-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 1466189#L681-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 1466186#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret24#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret24#1;havoc start_simulation_#t~ret24#1; 1466182#L1291 assume !(0 == start_simulation_~tmp~3#1); 1466179#L1291-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 1466178#L634-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 1466168#L681-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 1466166#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret23#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret23#1;havoc stop_simulation_#t~ret23#1; 1466162#L1246 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 1466160#L1253 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 1466158#stop_simulation_returnLabel#1 start_simulation_#t~ret25#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret25#1;havoc start_simulation_#t~ret25#1; 1466155#L1304 assume !(0 != start_simulation_~tmp___0~1#1); 1432475#L1272-2 [2023-11-06 21:59:17,100 INFO L145 PredicateUnifier]: Initialized classic predicate unifier [2023-11-06 21:59:17,100 INFO L85 PathProgramCache]: Analyzing trace with hash -1450780161, now seen corresponding path program 2 times [2023-11-06 21:59:17,100 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-06 21:59:17,100 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [296876543] [2023-11-06 21:59:17,100 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-06 21:59:17,101 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-06 21:59:17,114 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-06 21:59:17,114 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-06 21:59:17,122 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-06 21:59:17,154 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-06 21:59:17,155 INFO L145 PredicateUnifier]: Initialized classic predicate unifier [2023-11-06 21:59:17,155 INFO L85 PathProgramCache]: Analyzing trace with hash 1342151226, now seen corresponding path program 1 times [2023-11-06 21:59:17,156 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-06 21:59:17,156 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1402056279] [2023-11-06 21:59:17,156 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-06 21:59:17,156 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-06 21:59:17,169 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-06 21:59:17,195 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-06 21:59:17,196 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-06 21:59:17,197 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1402056279] [2023-11-06 21:59:17,198 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1402056279] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-06 21:59:17,198 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-06 21:59:17,198 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-06 21:59:17,198 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1074014656] [2023-11-06 21:59:17,198 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-06 21:59:17,199 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-06 21:59:17,199 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-06 21:59:17,199 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-06 21:59:17,199 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-06 21:59:17,200 INFO L87 Difference]: Start difference. First operand 64529 states and 89568 transitions. cyclomatic complexity: 25071 Second operand has 3 states, 3 states have (on average 40.0) internal successors, (120), 3 states have internal predecessors, (120), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-06 21:59:17,625 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-06 21:59:17,625 INFO L93 Difference]: Finished difference Result 117174 states and 161230 transitions. [2023-11-06 21:59:17,625 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 117174 states and 161230 transitions. [2023-11-06 21:59:18,077 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 116531 [2023-11-06 21:59:19,179 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 117174 states to 117174 states and 161230 transitions. [2023-11-06 21:59:19,179 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 117174 [2023-11-06 21:59:19,232 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 117174 [2023-11-06 21:59:19,232 INFO L73 IsDeterministic]: Start isDeterministic. Operand 117174 states and 161230 transitions. [2023-11-06 21:59:19,269 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-06 21:59:19,269 INFO L218 hiAutomatonCegarLoop]: Abstraction has 117174 states and 161230 transitions. [2023-11-06 21:59:19,320 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 117174 states and 161230 transitions. [2023-11-06 21:59:20,669 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 117174 to 117120. [2023-11-06 21:59:20,764 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 117120 states, 117120 states have (on average 1.3761612021857923) internal successors, (161176), 117119 states have internal predecessors, (161176), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-06 21:59:21,061 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 117120 states to 117120 states and 161176 transitions. [2023-11-06 21:59:21,061 INFO L240 hiAutomatonCegarLoop]: Abstraction has 117120 states and 161176 transitions. [2023-11-06 21:59:21,062 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-06 21:59:21,062 INFO L428 stractBuchiCegarLoop]: Abstraction has 117120 states and 161176 transitions. [2023-11-06 21:59:21,062 INFO L335 stractBuchiCegarLoop]: ======== Iteration 23 ============ [2023-11-06 21:59:21,062 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 117120 states and 161176 transitions. [2023-11-06 21:59:21,337 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 116477 [2023-11-06 21:59:21,337 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-06 21:59:21,337 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-06 21:59:21,339 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-06 21:59:21,339 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-06 21:59:21,339 INFO L748 eck$LassoCheckResult]: Stem: 1613433#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2; 1613434#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~10#1;havoc main_~__retres1~10#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; 1614185#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret24#1, start_simulation_#t~ret25#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 1614186#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 1614189#L581 assume 1 == ~m_i~0;~m_st~0 := 0; 1613548#L581-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 1613549#L586-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 1614180#L591-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 1614169#L596-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 1613631#L601-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 1613632#L606-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 1613897#L611-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 1613898#L616-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 1613720#L621-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 1613721#L838 assume !(0 == ~M_E~0); 1613906#L838-2 assume !(0 == ~T1_E~0); 1613233#L843-1 assume !(0 == ~T2_E~0); 1613234#L848-1 assume !(0 == ~T3_E~0); 1613351#L853-1 assume !(0 == ~T4_E~0); 1613707#L858-1 assume !(0 == ~T5_E~0); 1613190#L863-1 assume !(0 == ~T6_E~0); 1613191#L868-1 assume !(0 == ~T7_E~0); 1614251#L873-1 assume !(0 == ~T8_E~0); 1614249#L878-1 assume !(0 == ~E_1~0); 1614224#L883-1 assume !(0 == ~E_2~0); 1614225#L888-1 assume !(0 == ~E_3~0); 1613863#L893-1 assume !(0 == ~E_4~0); 1613864#L898-1 assume !(0 == ~E_5~0); 1614278#L903-1 assume !(0 == ~E_6~0); 1614221#L908-1 assume !(0 == ~E_7~0); 1614017#L913-1 assume !(0 == ~E_8~0); 1613246#L918-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1613247#L402 assume !(1 == ~m_pc~0); 1613682#L402-2 is_master_triggered_~__retres1~0#1 := 0; 1613377#L413 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1613378#is_master_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 1613638#L1035 assume !(0 != activate_threads_~tmp~1#1); 1613639#L1035-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1613692#L421 assume !(1 == ~t1_pc~0); 1614213#L421-2 is_transmit1_triggered_~__retres1~1#1 := 0; 1614254#L432 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1613248#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 1613249#L1043 assume !(0 != activate_threads_~tmp___0~0#1); 1613751#L1043-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1614268#L440 assume !(1 == ~t2_pc~0); 1614345#L440-2 is_transmit2_triggered_~__retres1~2#1 := 0; 1613387#L451 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1613388#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 1613577#L1051 assume !(0 != activate_threads_~tmp___1~0#1); 1614037#L1051-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1613582#L459 assume !(1 == ~t3_pc~0); 1613583#L459-2 is_transmit3_triggered_~__retres1~3#1 := 0; 1614207#L470 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1614267#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 1613370#L1059 assume !(0 != activate_threads_~tmp___2~0#1); 1613371#L1059-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1613381#L478 assume !(1 == ~t4_pc~0); 1613382#L478-2 is_transmit4_triggered_~__retres1~4#1 := 0; 1614094#L489 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1613323#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1613324#L1067 assume !(0 != activate_threads_~tmp___3~0#1); 1613286#L1067-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1613287#L497 assume !(1 == ~t5_pc~0); 1613334#L497-2 is_transmit5_triggered_~__retres1~5#1 := 0; 1613818#L508 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1614089#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1614090#L1075 assume !(0 != activate_threads_~tmp___4~0#1); 1614200#L1075-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1614201#L516 assume !(1 == ~t6_pc~0); 1614113#L516-2 is_transmit6_triggered_~__retres1~6#1 := 0; 1614114#L527 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1613558#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1613559#L1083 assume !(0 != activate_threads_~tmp___5~0#1); 1613967#L1083-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1613968#L535 assume !(1 == ~t7_pc~0); 1614147#L535-2 is_transmit7_triggered_~__retres1~7#1 := 0; 1614146#L546 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1614320#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1614006#L1091 assume !(0 != activate_threads_~tmp___6~0#1); 1613996#L1091-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 1613997#L554 assume !(1 == ~t8_pc~0); 1613210#L554-2 is_transmit8_triggered_~__retres1~8#1 := 0; 1613211#L565 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 1614365#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 1613510#L1099 assume !(0 != activate_threads_~tmp___7~0#1); 1613511#L1099-2 havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1613198#L931 assume !(1 == ~M_E~0); 1613199#L931-2 assume !(1 == ~T1_E~0); 1614288#L936-1 assume !(1 == ~T2_E~0); 1614289#L941-1 assume !(1 == ~T3_E~0); 1613693#L946-1 assume !(1 == ~T4_E~0); 1613694#L951-1 assume !(1 == ~T5_E~0); 1614362#L956-1 assume !(1 == ~T6_E~0); 1614333#L961-1 assume !(1 == ~T7_E~0); 1614334#L966-1 assume !(1 == ~T8_E~0); 1614361#L971-1 assume !(1 == ~E_1~0); 1614301#L976-1 assume !(1 == ~E_2~0); 1613953#L981-1 assume !(1 == ~E_3~0); 1613698#L986-1 assume !(1 == ~E_4~0); 1613699#L991-1 assume !(1 == ~E_5~0); 1613469#L996-1 assume !(1 == ~E_6~0); 1614261#L1001-1 assume !(1 == ~E_7~0); 1613919#L1006-1 assume !(1 == ~E_8~0); 1613920#L1011-1 assume { :end_inline_reset_delta_events } true; 1614211#L1272-2 [2023-11-06 21:59:21,340 INFO L750 eck$LassoCheckResult]: Loop: 1614211#L1272-2 assume !false; 1681875#L1273 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 1679022#L813-1 assume !false; 1681874#L692 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 1681872#L634 assume !(0 == ~m_st~0); 1681873#L638 assume !(0 == ~t1_st~0); 1681866#L642 assume !(0 == ~t2_st~0); 1681867#L646 assume !(0 == ~t3_st~0); 1681871#L650 assume !(0 == ~t4_st~0); 1681864#L654 assume !(0 == ~t5_st~0); 1681865#L658 assume !(0 == ~t6_st~0); 1681870#L662 assume !(0 == ~t7_st~0); 1681868#L666 assume !(0 == ~t8_st~0);exists_runnable_thread_~__retres1~9#1 := 0; 1681869#L681 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 1681860#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 1681861#L696 assume !(0 != eval_~tmp~0#1); 1682102#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 1682100#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 1682098#L838-3 assume 0 == ~M_E~0;~M_E~0 := 1; 1682096#L838-5 assume !(0 == ~T1_E~0); 1682094#L843-3 assume !(0 == ~T2_E~0); 1682092#L848-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 1682090#L853-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 1682088#L858-3 assume !(0 == ~T5_E~0); 1682086#L863-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 1682084#L868-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 1682082#L873-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 1682080#L878-3 assume !(0 == ~E_1~0); 1682078#L883-3 assume 0 == ~E_2~0;~E_2~0 := 1; 1682076#L888-3 assume 0 == ~E_3~0;~E_3~0 := 1; 1682074#L893-3 assume 0 == ~E_4~0;~E_4~0 := 1; 1682072#L898-3 assume !(0 == ~E_5~0); 1682070#L903-3 assume 0 == ~E_6~0;~E_6~0 := 1; 1682068#L908-3 assume 0 == ~E_7~0;~E_7~0 := 1; 1682066#L913-3 assume 0 == ~E_8~0;~E_8~0 := 1; 1682064#L918-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1682062#L402-27 assume !(1 == ~m_pc~0); 1682060#L402-29 is_master_triggered_~__retres1~0#1 := 0; 1682058#L413-9 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1682056#is_master_triggered_returnLabel#10 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 1682054#L1035-27 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 1682052#L1035-29 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1682050#L421-27 assume !(1 == ~t1_pc~0); 1682048#L421-29 is_transmit1_triggered_~__retres1~1#1 := 0; 1682046#L432-9 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1682044#is_transmit1_triggered_returnLabel#10 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 1682042#L1043-27 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 1682040#L1043-29 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1682038#L440-27 assume !(1 == ~t2_pc~0); 1682036#L440-29 is_transmit2_triggered_~__retres1~2#1 := 0; 1682034#L451-9 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1682032#is_transmit2_triggered_returnLabel#10 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 1682030#L1051-27 assume !(0 != activate_threads_~tmp___1~0#1); 1682028#L1051-29 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1682026#L459-27 assume !(1 == ~t3_pc~0); 1682023#L459-29 is_transmit3_triggered_~__retres1~3#1 := 0; 1682019#L470-9 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1682015#is_transmit3_triggered_returnLabel#10 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 1682011#L1059-27 assume !(0 != activate_threads_~tmp___2~0#1); 1682008#L1059-29 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1682006#L478-27 assume !(1 == ~t4_pc~0); 1682004#L478-29 is_transmit4_triggered_~__retres1~4#1 := 0; 1682002#L489-9 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1682000#is_transmit4_triggered_returnLabel#10 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1681998#L1067-27 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 1681996#L1067-29 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1681994#L497-27 assume 1 == ~t5_pc~0; 1681993#L498-9 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 1681989#L508-9 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1681987#is_transmit5_triggered_returnLabel#10 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1681985#L1075-27 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 1681983#L1075-29 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1681981#L516-27 assume !(1 == ~t6_pc~0); 1681979#L516-29 is_transmit6_triggered_~__retres1~6#1 := 0; 1681977#L527-9 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1681975#is_transmit6_triggered_returnLabel#10 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1681973#L1083-27 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 1681971#L1083-29 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1681969#L535-27 assume !(1 == ~t7_pc~0); 1681967#L535-29 is_transmit7_triggered_~__retres1~7#1 := 0; 1681963#L546-9 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1681961#is_transmit7_triggered_returnLabel#10 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1681959#L1091-27 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 1681957#L1091-29 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 1681955#L554-27 assume !(1 == ~t8_pc~0); 1681953#L554-29 is_transmit8_triggered_~__retres1~8#1 := 0; 1681951#L565-9 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 1681949#is_transmit8_triggered_returnLabel#10 activate_threads_#t~ret22#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 1681947#L1099-27 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 1681945#L1099-29 havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1681943#L931-3 assume 1 == ~M_E~0;~M_E~0 := 2; 1681941#L931-5 assume !(1 == ~T1_E~0); 1681939#L936-3 assume !(1 == ~T2_E~0); 1681937#L941-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 1681935#L946-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 1681933#L951-3 assume !(1 == ~T5_E~0); 1681931#L956-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 1681929#L961-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 1681927#L966-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 1681925#L971-3 assume !(1 == ~E_1~0); 1681923#L976-3 assume 1 == ~E_2~0;~E_2~0 := 2; 1681921#L981-3 assume 1 == ~E_3~0;~E_3~0 := 2; 1681919#L986-3 assume 1 == ~E_4~0;~E_4~0 := 2; 1681917#L991-3 assume 1 == ~E_5~0;~E_5~0 := 2; 1681915#L996-3 assume 1 == ~E_6~0;~E_6~0 := 2; 1681914#L1001-3 assume 1 == ~E_7~0;~E_7~0 := 2; 1681913#L1006-3 assume 1 == ~E_8~0;~E_8~0 := 2; 1681912#L1011-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 1681907#L634-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 1681898#L681-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 1681896#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret24#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret24#1;havoc start_simulation_#t~ret24#1; 1681893#L1291 assume !(0 == start_simulation_~tmp~3#1); 1681891#L1291-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 1681890#L634-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 1681881#L681-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 1681880#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret23#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret23#1;havoc stop_simulation_#t~ret23#1; 1681879#L1246 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 1681878#L1253 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 1681877#stop_simulation_returnLabel#1 start_simulation_#t~ret25#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret25#1;havoc start_simulation_#t~ret25#1; 1681876#L1304 assume !(0 != start_simulation_~tmp___0~1#1); 1614211#L1272-2 [2023-11-06 21:59:21,340 INFO L145 PredicateUnifier]: Initialized classic predicate unifier [2023-11-06 21:59:21,341 INFO L85 PathProgramCache]: Analyzing trace with hash -1450780161, now seen corresponding path program 3 times [2023-11-06 21:59:21,341 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-06 21:59:21,341 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1919184620] [2023-11-06 21:59:21,341 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-06 21:59:21,341 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-06 21:59:21,363 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-06 21:59:21,376 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-06 21:59:21,383 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-06 21:59:21,427 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-06 21:59:21,427 INFO L145 PredicateUnifier]: Initialized classic predicate unifier [2023-11-06 21:59:21,428 INFO L85 PathProgramCache]: Analyzing trace with hash -1863170475, now seen corresponding path program 1 times [2023-11-06 21:59:21,428 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-06 21:59:21,428 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1650106258] [2023-11-06 21:59:21,428 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-06 21:59:21,428 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-06 21:59:21,448 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-06 21:59:21,538 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-06 21:59:21,538 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-06 21:59:21,538 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1650106258] [2023-11-06 21:59:21,538 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1650106258] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-06 21:59:21,538 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-06 21:59:21,539 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2023-11-06 21:59:21,539 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [705776478] [2023-11-06 21:59:21,539 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-06 21:59:21,539 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-06 21:59:21,540 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-06 21:59:21,540 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2023-11-06 21:59:21,540 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2023-11-06 21:59:21,541 INFO L87 Difference]: Start difference. First operand 117120 states and 161176 transitions. cyclomatic complexity: 44088 Second operand has 5 states, 5 states have (on average 24.0) internal successors, (120), 5 states have internal predecessors, (120), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-06 21:59:22,279 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-06 21:59:22,279 INFO L93 Difference]: Finished difference Result 183792 states and 250029 transitions. [2023-11-06 21:59:22,279 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 183792 states and 250029 transitions. [2023-11-06 21:59:23,889 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 183085 [2023-11-06 21:59:24,308 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 183792 states to 183792 states and 250029 transitions. [2023-11-06 21:59:24,308 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 183792 [2023-11-06 21:59:24,375 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 183792 [2023-11-06 21:59:24,375 INFO L73 IsDeterministic]: Start isDeterministic. Operand 183792 states and 250029 transitions. [2023-11-06 21:59:24,443 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-06 21:59:24,443 INFO L218 hiAutomatonCegarLoop]: Abstraction has 183792 states and 250029 transitions. [2023-11-06 21:59:24,517 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 183792 states and 250029 transitions.