./Ultimate.py --spec ../../sv-benchmarks/c/properties/termination.prp --file ../../sv-benchmarks/c/termination-restricted-15/NarrowKonv.c --full-output --architecture 64bit -------------------------------------------------------------------------------- Checking for termination Using default analysis Version cf1a7837 Calling Ultimate with: /usr/lib/jvm/java-1.11.0-openjdk-amd64/bin/java -Dosgi.configuration.area=/tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1deda2bf-224c-4242-8866-e899ae47e0d0/bin/uautomizer-verify-uTZkv6EMXl/data/config -Xmx15G -Xms4m -jar /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1deda2bf-224c-4242-8866-e899ae47e0d0/bin/uautomizer-verify-uTZkv6EMXl/plugins/org.eclipse.equinox.launcher_1.5.800.v20200727-1323.jar -data @noDefault -ultimatedata /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1deda2bf-224c-4242-8866-e899ae47e0d0/bin/uautomizer-verify-uTZkv6EMXl/data -tc /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1deda2bf-224c-4242-8866-e899ae47e0d0/bin/uautomizer-verify-uTZkv6EMXl/config/AutomizerTermination.xml -i ../../sv-benchmarks/c/termination-restricted-15/NarrowKonv.c -s /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1deda2bf-224c-4242-8866-e899ae47e0d0/bin/uautomizer-verify-uTZkv6EMXl/config/svcomp-Termination-64bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1deda2bf-224c-4242-8866-e899ae47e0d0/bin/uautomizer-verify-uTZkv6EMXl --witnessprinter.witness.filename witness --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(F end) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 64bit --witnessprinter.graph.data.programhash 2c8d79b985e49ac5d6f27b4e25f4e3597dadc4ec57e262caec7782b796e874b7 --- Real Ultimate output --- This is Ultimate 0.2.3-dev-cf1a783 [2023-11-12 02:32:43,263 INFO L188 SettingsManager]: Resetting all preferences to default values... [2023-11-12 02:32:43,329 INFO L114 SettingsManager]: Loading settings from /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1deda2bf-224c-4242-8866-e899ae47e0d0/bin/uautomizer-verify-uTZkv6EMXl/config/svcomp-Termination-64bit-Automizer_Default.epf [2023-11-12 02:32:43,334 WARN L101 SettingsManager]: Preference file contains the following unknown settings: [2023-11-12 02:32:43,335 WARN L103 SettingsManager]: * de.uni_freiburg.informatik.ultimate.core.Log level for class [2023-11-12 02:32:43,359 INFO L130 SettingsManager]: Preferences different from defaults after loading the file: [2023-11-12 02:32:43,360 INFO L151 SettingsManager]: Preferences of UltimateCore differ from their defaults: [2023-11-12 02:32:43,361 INFO L153 SettingsManager]: * Log level for class=de.uni_freiburg.informatik.ultimate.lib.smtlibutils.quantifier.QuantifierPusher=ERROR; [2023-11-12 02:32:43,362 INFO L151 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2023-11-12 02:32:43,362 INFO L153 SettingsManager]: * Create parallel compositions if possible=false [2023-11-12 02:32:43,363 INFO L153 SettingsManager]: * Use SBE=true [2023-11-12 02:32:43,364 INFO L151 SettingsManager]: Preferences of BuchiAutomizer differ from their defaults: [2023-11-12 02:32:43,364 INFO L153 SettingsManager]: * NCSB implementation=INTSET_LAZY3 [2023-11-12 02:32:43,365 INFO L153 SettingsManager]: * Use old map elimination=false [2023-11-12 02:32:43,365 INFO L153 SettingsManager]: * Use external solver (rank synthesis)=false [2023-11-12 02:32:43,366 INFO L153 SettingsManager]: * Use only trivial implications for array writes=true [2023-11-12 02:32:43,366 INFO L153 SettingsManager]: * Rank analysis=LINEAR_WITH_GUESSES [2023-11-12 02:32:43,367 INFO L151 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2023-11-12 02:32:43,368 INFO L153 SettingsManager]: * Pointer base address is valid at dereference=ASSUME [2023-11-12 02:32:43,368 INFO L153 SettingsManager]: * Overapproximate operations on floating types=true [2023-11-12 02:32:43,369 INFO L153 SettingsManager]: * Check division by zero=IGNORE [2023-11-12 02:32:43,370 INFO L153 SettingsManager]: * Pointer to allocated memory at dereference=ASSUME [2023-11-12 02:32:43,370 INFO L153 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=ASSUME [2023-11-12 02:32:43,371 INFO L153 SettingsManager]: * Check array bounds for arrays that are off heap=ASSUME [2023-11-12 02:32:43,371 INFO L153 SettingsManager]: * Check unreachability of reach_error function=false [2023-11-12 02:32:43,372 INFO L153 SettingsManager]: * Check if freed pointer was valid=false [2023-11-12 02:32:43,372 INFO L153 SettingsManager]: * Assume nondeterminstic values are in range=false [2023-11-12 02:32:43,373 INFO L153 SettingsManager]: * Use constant arrays=true [2023-11-12 02:32:43,373 INFO L151 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2023-11-12 02:32:43,374 INFO L153 SettingsManager]: * Size of a code block=SequenceOfStatements [2023-11-12 02:32:43,374 INFO L151 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2023-11-12 02:32:43,375 INFO L153 SettingsManager]: * Trace refinement strategy=CAMEL [2023-11-12 02:32:43,375 INFO L151 SettingsManager]: Preferences of IcfgTransformer differ from their defaults: [2023-11-12 02:32:43,376 INFO L153 SettingsManager]: * TransformationType=MODULO_NEIGHBOR WARNING: An illegal reflective access operation has occurred WARNING: Illegal reflective access by com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 (file:/tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1deda2bf-224c-4242-8866-e899ae47e0d0/bin/uautomizer-verify-uTZkv6EMXl/plugins/com.sun.xml.bind_2.2.0.v201505121915.jar) to method java.lang.ClassLoader.defineClass(java.lang.String,byte[],int,int) WARNING: Please consider reporting this to the maintainers of com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 WARNING: Use --illegal-access=warn to enable warnings of further illegal reflective access operations WARNING: All illegal access operations will be denied in a future release Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1deda2bf-224c-4242-8866-e899ae47e0d0/bin/uautomizer-verify-uTZkv6EMXl Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(F end) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 64bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> 2c8d79b985e49ac5d6f27b4e25f4e3597dadc4ec57e262caec7782b796e874b7 [2023-11-12 02:32:43,600 INFO L75 nceAwareModelManager]: Repository-Root is: /tmp [2023-11-12 02:32:43,633 INFO L261 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2023-11-12 02:32:43,636 INFO L217 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2023-11-12 02:32:43,637 INFO L270 PluginConnector]: Initializing CDTParser... [2023-11-12 02:32:43,638 INFO L274 PluginConnector]: CDTParser initialized [2023-11-12 02:32:43,639 INFO L431 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1deda2bf-224c-4242-8866-e899ae47e0d0/bin/uautomizer-verify-uTZkv6EMXl/../../sv-benchmarks/c/termination-restricted-15/NarrowKonv.c [2023-11-12 02:32:46,831 INFO L533 CDTParser]: Created temporary CDT project at NULL [2023-11-12 02:32:47,093 INFO L384 CDTParser]: Found 1 translation units. [2023-11-12 02:32:47,094 INFO L180 CDTParser]: Scanning /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1deda2bf-224c-4242-8866-e899ae47e0d0/sv-benchmarks/c/termination-restricted-15/NarrowKonv.c [2023-11-12 02:32:47,102 INFO L427 CDTParser]: About to delete temporary CDT project at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1deda2bf-224c-4242-8866-e899ae47e0d0/bin/uautomizer-verify-uTZkv6EMXl/data/614ca1d8c/92068357e6044b6785903be0c8bdc64c/FLAGc40d460a5 [2023-11-12 02:32:47,117 INFO L435 CDTParser]: Successfully deleted /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1deda2bf-224c-4242-8866-e899ae47e0d0/bin/uautomizer-verify-uTZkv6EMXl/data/614ca1d8c/92068357e6044b6785903be0c8bdc64c [2023-11-12 02:32:47,119 INFO L299 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2023-11-12 02:32:47,122 INFO L133 ToolchainWalker]: Walking toolchain with 6 elements. [2023-11-12 02:32:47,123 INFO L112 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2023-11-12 02:32:47,123 INFO L270 PluginConnector]: Initializing CACSL2BoogieTranslator... [2023-11-12 02:32:47,129 INFO L274 PluginConnector]: CACSL2BoogieTranslator initialized [2023-11-12 02:32:47,130 INFO L184 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 12.11 02:32:47" (1/1) ... [2023-11-12 02:32:47,131 INFO L204 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@1fab800c and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 12.11 02:32:47, skipping insertion in model container [2023-11-12 02:32:47,131 INFO L184 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 12.11 02:32:47" (1/1) ... [2023-11-12 02:32:47,154 INFO L177 MainTranslator]: Built tables and reachable declarations [2023-11-12 02:32:47,306 INFO L209 PostProcessor]: Analyzing one entry point: main [2023-11-12 02:32:47,310 INFO L202 MainTranslator]: Completed pre-run [2023-11-12 02:32:47,321 INFO L209 PostProcessor]: Analyzing one entry point: main [2023-11-12 02:32:47,332 INFO L206 MainTranslator]: Completed translation [2023-11-12 02:32:47,332 INFO L201 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 12.11 02:32:47 WrapperNode [2023-11-12 02:32:47,333 INFO L131 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2023-11-12 02:32:47,334 INFO L112 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2023-11-12 02:32:47,334 INFO L270 PluginConnector]: Initializing Boogie Procedure Inliner... [2023-11-12 02:32:47,334 INFO L274 PluginConnector]: Boogie Procedure Inliner initialized [2023-11-12 02:32:47,340 INFO L184 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 12.11 02:32:47" (1/1) ... [2023-11-12 02:32:47,345 INFO L184 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 12.11 02:32:47" (1/1) ... [2023-11-12 02:32:47,361 INFO L138 Inliner]: procedures = 4, calls = 2, calls flagged for inlining = 2, calls inlined = 2, statements flattened = 19 [2023-11-12 02:32:47,361 INFO L131 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2023-11-12 02:32:47,362 INFO L112 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2023-11-12 02:32:47,362 INFO L270 PluginConnector]: Initializing Boogie Preprocessor... [2023-11-12 02:32:47,362 INFO L274 PluginConnector]: Boogie Preprocessor initialized [2023-11-12 02:32:47,371 INFO L184 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 12.11 02:32:47" (1/1) ... [2023-11-12 02:32:47,371 INFO L184 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 12.11 02:32:47" (1/1) ... [2023-11-12 02:32:47,372 INFO L184 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 12.11 02:32:47" (1/1) ... [2023-11-12 02:32:47,372 INFO L184 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 12.11 02:32:47" (1/1) ... [2023-11-12 02:32:47,374 INFO L184 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 12.11 02:32:47" (1/1) ... [2023-11-12 02:32:47,378 INFO L184 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 12.11 02:32:47" (1/1) ... [2023-11-12 02:32:47,378 INFO L184 PluginConnector]: Executing the observer LTLStepAnnotator from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 12.11 02:32:47" (1/1) ... [2023-11-12 02:32:47,379 INFO L184 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 12.11 02:32:47" (1/1) ... [2023-11-12 02:32:47,380 INFO L131 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2023-11-12 02:32:47,381 INFO L112 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2023-11-12 02:32:47,381 INFO L270 PluginConnector]: Initializing RCFGBuilder... [2023-11-12 02:32:47,381 INFO L274 PluginConnector]: RCFGBuilder initialized [2023-11-12 02:32:47,382 INFO L184 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 12.11 02:32:47" (1/1) ... [2023-11-12 02:32:47,388 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2023-11-12 02:32:47,399 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1deda2bf-224c-4242-8866-e899ae47e0d0/bin/uautomizer-verify-uTZkv6EMXl/z3 [2023-11-12 02:32:47,412 INFO L229 MonitoredProcess]: Starting monitored process 1 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1deda2bf-224c-4242-8866-e899ae47e0d0/bin/uautomizer-verify-uTZkv6EMXl/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2023-11-12 02:32:47,436 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1deda2bf-224c-4242-8866-e899ae47e0d0/bin/uautomizer-verify-uTZkv6EMXl/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (1)] Waiting until timeout for monitored process [2023-11-12 02:32:47,460 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2023-11-12 02:32:47,461 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2023-11-12 02:32:47,537 INFO L236 CfgBuilder]: Building ICFG [2023-11-12 02:32:47,539 INFO L262 CfgBuilder]: Building CFG for each procedure with an implementation [2023-11-12 02:32:47,616 INFO L277 CfgBuilder]: Performing block encoding [2023-11-12 02:32:47,622 INFO L297 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2023-11-12 02:32:47,622 INFO L302 CfgBuilder]: Removed 1 assume(true) statements. [2023-11-12 02:32:47,624 INFO L201 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 12.11 02:32:47 BoogieIcfgContainer [2023-11-12 02:32:47,625 INFO L131 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2023-11-12 02:32:47,626 INFO L112 PluginConnector]: ------------------------BuchiAutomizer---------------------------- [2023-11-12 02:32:47,626 INFO L270 PluginConnector]: Initializing BuchiAutomizer... [2023-11-12 02:32:47,630 INFO L274 PluginConnector]: BuchiAutomizer initialized [2023-11-12 02:32:47,631 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2023-11-12 02:32:47,631 INFO L184 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "CDTParser AST 12.11 02:32:47" (1/3) ... [2023-11-12 02:32:47,632 INFO L204 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@726db858 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 12.11 02:32:47, skipping insertion in model container [2023-11-12 02:32:47,632 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2023-11-12 02:32:47,633 INFO L184 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 12.11 02:32:47" (2/3) ... [2023-11-12 02:32:47,633 INFO L204 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@726db858 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 12.11 02:32:47, skipping insertion in model container [2023-11-12 02:32:47,633 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2023-11-12 02:32:47,634 INFO L184 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 12.11 02:32:47" (3/3) ... [2023-11-12 02:32:47,635 INFO L332 chiAutomizerObserver]: Analyzing ICFG NarrowKonv.c [2023-11-12 02:32:47,687 INFO L303 stractBuchiCegarLoop]: Interprodecural is true [2023-11-12 02:32:47,687 INFO L304 stractBuchiCegarLoop]: Hoare is false [2023-11-12 02:32:47,687 INFO L305 stractBuchiCegarLoop]: Compute interpolants for ForwardPredicates [2023-11-12 02:32:47,688 INFO L306 stractBuchiCegarLoop]: Backedges is STRAIGHT_LINE [2023-11-12 02:32:47,688 INFO L307 stractBuchiCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2023-11-12 02:32:47,688 INFO L308 stractBuchiCegarLoop]: Difference is false [2023-11-12 02:32:47,688 INFO L309 stractBuchiCegarLoop]: Minimize is MINIMIZE_SEVPA [2023-11-12 02:32:47,688 INFO L313 stractBuchiCegarLoop]: ======== Iteration 0 == of CEGAR loop == BuchiAutomatonCegarLoop ======== [2023-11-12 02:32:47,693 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 9 states, 8 states have (on average 1.5) internal successors, (12), 8 states have internal predecessors, (12), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-12 02:32:47,707 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 3 [2023-11-12 02:32:47,707 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-12 02:32:47,708 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-12 02:32:47,712 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1] [2023-11-12 02:32:47,713 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1] [2023-11-12 02:32:47,713 INFO L335 stractBuchiCegarLoop]: ======== Iteration 1 ============ [2023-11-12 02:32:47,713 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 9 states, 8 states have (on average 1.5) internal successors, (12), 8 states have internal predecessors, (12), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-12 02:32:47,714 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 3 [2023-11-12 02:32:47,714 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-12 02:32:47,715 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-12 02:32:47,715 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1] [2023-11-12 02:32:47,715 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1] [2023-11-12 02:32:47,721 INFO L748 eck$LassoCheckResult]: Stem: 6#$Ultimate##0true assume { :begin_inline_ULTIMATE.init } true; 7#L-1true assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet0#1, main_~i~0#1, main_~range~0#1;havoc main_~i~0#1;havoc main_~range~0#1;havoc main_#t~nondet0#1;main_~i~0#1 := main_#t~nondet0#1;havoc main_#t~nondet0#1;main_~range~0#1 := 20; 3#L12-1true [2023-11-12 02:32:47,721 INFO L750 eck$LassoCheckResult]: Loop: 3#L12-1true assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 9#L12true assume !!(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 3#L12-1true [2023-11-12 02:32:47,726 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-12 02:32:47,727 INFO L85 PathProgramCache]: Analyzing trace with hash 963, now seen corresponding path program 1 times [2023-11-12 02:32:47,735 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-12 02:32:47,736 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [922874722] [2023-11-12 02:32:47,736 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-12 02:32:47,737 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-12 02:32:47,802 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-12 02:32:47,803 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-12 02:32:47,806 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-12 02:32:47,821 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-12 02:32:47,824 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-12 02:32:47,824 INFO L85 PathProgramCache]: Analyzing trace with hash 1324, now seen corresponding path program 1 times [2023-11-12 02:32:47,825 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-12 02:32:47,825 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1974834813] [2023-11-12 02:32:47,825 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-12 02:32:47,825 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-12 02:32:47,835 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-12 02:32:47,835 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-12 02:32:47,839 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-12 02:32:47,840 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-12 02:32:47,851 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-12 02:32:47,851 INFO L85 PathProgramCache]: Analyzing trace with hash 925806, now seen corresponding path program 1 times [2023-11-12 02:32:47,852 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-12 02:32:47,852 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1388579385] [2023-11-12 02:32:47,852 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-12 02:32:47,853 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-12 02:32:47,863 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-12 02:32:47,969 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-12 02:32:47,969 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-12 02:32:47,969 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1388579385] [2023-11-12 02:32:47,970 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1388579385] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-12 02:32:47,970 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-12 02:32:47,970 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2023-11-12 02:32:47,971 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [584984788] [2023-11-12 02:32:47,971 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-12 02:32:48,019 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-12 02:32:48,066 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-12 02:32:48,067 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-12 02:32:48,068 INFO L87 Difference]: Start difference. First operand has 9 states, 8 states have (on average 1.5) internal successors, (12), 8 states have internal predecessors, (12), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand has 3 states, 2 states have (on average 2.0) internal successors, (4), 3 states have internal predecessors, (4), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-12 02:32:48,121 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-12 02:32:48,121 INFO L93 Difference]: Finished difference Result 14 states and 18 transitions. [2023-11-12 02:32:48,123 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 14 states and 18 transitions. [2023-11-12 02:32:48,124 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 6 [2023-11-12 02:32:48,128 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 14 states to 8 states and 11 transitions. [2023-11-12 02:32:48,129 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 8 [2023-11-12 02:32:48,129 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 8 [2023-11-12 02:32:48,130 INFO L73 IsDeterministic]: Start isDeterministic. Operand 8 states and 11 transitions. [2023-11-12 02:32:48,130 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-12 02:32:48,130 INFO L218 hiAutomatonCegarLoop]: Abstraction has 8 states and 11 transitions. [2023-11-12 02:32:48,143 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 8 states and 11 transitions. [2023-11-12 02:32:48,150 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 8 to 8. [2023-11-12 02:32:48,151 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 8 states, 8 states have (on average 1.375) internal successors, (11), 7 states have internal predecessors, (11), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-12 02:32:48,151 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 8 states to 8 states and 11 transitions. [2023-11-12 02:32:48,152 INFO L240 hiAutomatonCegarLoop]: Abstraction has 8 states and 11 transitions. [2023-11-12 02:32:48,160 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-12 02:32:48,164 INFO L428 stractBuchiCegarLoop]: Abstraction has 8 states and 11 transitions. [2023-11-12 02:32:48,164 INFO L335 stractBuchiCegarLoop]: ======== Iteration 2 ============ [2023-11-12 02:32:48,164 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 8 states and 11 transitions. [2023-11-12 02:32:48,165 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 6 [2023-11-12 02:32:48,165 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-12 02:32:48,165 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-12 02:32:48,165 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1] [2023-11-12 02:32:48,166 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1] [2023-11-12 02:32:48,166 INFO L748 eck$LassoCheckResult]: Stem: 37#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true; 38#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet0#1, main_~i~0#1, main_~range~0#1;havoc main_~i~0#1;havoc main_~range~0#1;havoc main_#t~nondet0#1;main_~i~0#1 := main_#t~nondet0#1;havoc main_#t~nondet0#1;main_~range~0#1 := 20; 39#L12-1 [2023-11-12 02:32:48,166 INFO L750 eck$LassoCheckResult]: Loop: 39#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 40#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 41#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 39#L12-1 [2023-11-12 02:32:48,167 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-12 02:32:48,167 INFO L85 PathProgramCache]: Analyzing trace with hash 963, now seen corresponding path program 2 times [2023-11-12 02:32:48,167 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-12 02:32:48,168 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [267774810] [2023-11-12 02:32:48,168 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-12 02:32:48,168 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-12 02:32:48,173 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-12 02:32:48,173 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-12 02:32:48,176 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-12 02:32:48,177 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-12 02:32:48,178 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-12 02:32:48,178 INFO L85 PathProgramCache]: Analyzing trace with hash 40815, now seen corresponding path program 1 times [2023-11-12 02:32:48,178 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-12 02:32:48,179 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [916233235] [2023-11-12 02:32:48,179 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-12 02:32:48,179 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-12 02:32:48,188 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-12 02:32:48,189 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-12 02:32:48,194 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-12 02:32:48,195 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-12 02:32:48,196 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-12 02:32:48,196 INFO L85 PathProgramCache]: Analyzing trace with hash 28699757, now seen corresponding path program 1 times [2023-11-12 02:32:48,196 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-12 02:32:48,197 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1677220899] [2023-11-12 02:32:48,197 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-12 02:32:48,197 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-12 02:32:48,205 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-12 02:32:48,205 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-12 02:32:48,210 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-12 02:32:48,212 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-12 02:32:48,268 INFO L210 LassoAnalysis]: Preferences: [2023-11-12 02:32:48,269 INFO L126 ssoRankerPreferences]: Compute integeral hull: false [2023-11-12 02:32:48,269 INFO L127 ssoRankerPreferences]: Enable LassoPartitioneer: true [2023-11-12 02:32:48,270 INFO L128 ssoRankerPreferences]: Term annotations enabled: false [2023-11-12 02:32:48,270 INFO L129 ssoRankerPreferences]: Use exernal solver: true [2023-11-12 02:32:48,270 INFO L130 ssoRankerPreferences]: SMT solver command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2023-11-12 02:32:48,270 INFO L131 ssoRankerPreferences]: Dump SMT script to file: false [2023-11-12 02:32:48,270 INFO L132 ssoRankerPreferences]: Path of dumped script: [2023-11-12 02:32:48,270 INFO L133 ssoRankerPreferences]: Filename of dumped script: NarrowKonv.c_Iteration2_Loop [2023-11-12 02:32:48,271 INFO L134 ssoRankerPreferences]: MapElimAlgo: Frank [2023-11-12 02:32:48,271 INFO L276 LassoAnalysis]: Starting lasso preprocessing... [2023-11-12 02:32:48,290 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-12 02:32:48,303 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-12 02:32:48,307 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-12 02:32:48,436 INFO L294 LassoAnalysis]: Preprocessing complete. [2023-11-12 02:32:48,436 INFO L404 LassoAnalysis]: Checking for nontermination... [2023-11-12 02:32:48,439 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2023-11-12 02:32:48,440 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1deda2bf-224c-4242-8866-e899ae47e0d0/bin/uautomizer-verify-uTZkv6EMXl/z3 [2023-11-12 02:32:48,446 INFO L229 MonitoredProcess]: Starting monitored process 2 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1deda2bf-224c-4242-8866-e899ae47e0d0/bin/uautomizer-verify-uTZkv6EMXl/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2023-11-12 02:32:48,458 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2023-11-12 02:32:48,459 INFO L160 nArgumentSynthesizer]: Using integer mode. [2023-11-12 02:32:48,459 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1deda2bf-224c-4242-8866-e899ae47e0d0/bin/uautomizer-verify-uTZkv6EMXl/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (2)] Waiting until timeout for monitored process [2023-11-12 02:32:48,486 INFO L437 LassoAnalysis]: Proved nontermination for one component. [2023-11-12 02:32:48,486 INFO L440 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {v_rep~unnamed0~0~true_1=1} Honda state: {v_rep~unnamed0~0~true_1=1} Generalized eigenvectors: [] Lambdas: [] Nus: [] [2023-11-12 02:32:48,498 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1deda2bf-224c-4242-8866-e899ae47e0d0/bin/uautomizer-verify-uTZkv6EMXl/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (2)] Forceful destruction successful, exit code 0 [2023-11-12 02:32:48,500 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2023-11-12 02:32:48,500 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1deda2bf-224c-4242-8866-e899ae47e0d0/bin/uautomizer-verify-uTZkv6EMXl/z3 [2023-11-12 02:32:48,501 INFO L229 MonitoredProcess]: Starting monitored process 3 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1deda2bf-224c-4242-8866-e899ae47e0d0/bin/uautomizer-verify-uTZkv6EMXl/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2023-11-12 02:32:48,516 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2023-11-12 02:32:48,516 INFO L160 nArgumentSynthesizer]: Using integer mode. [2023-11-12 02:32:48,530 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1deda2bf-224c-4242-8866-e899ae47e0d0/bin/uautomizer-verify-uTZkv6EMXl/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (3)] Waiting until timeout for monitored process [2023-11-12 02:32:48,546 INFO L437 LassoAnalysis]: Proved nontermination for one component. [2023-11-12 02:32:48,546 INFO L440 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {v_rep~unnamed0~0~false_1=0} Honda state: {v_rep~unnamed0~0~false_1=0} Generalized eigenvectors: [] Lambdas: [] Nus: [] [2023-11-12 02:32:48,555 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1deda2bf-224c-4242-8866-e899ae47e0d0/bin/uautomizer-verify-uTZkv6EMXl/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (3)] Forceful destruction successful, exit code 0 [2023-11-12 02:32:48,555 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2023-11-12 02:32:48,556 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1deda2bf-224c-4242-8866-e899ae47e0d0/bin/uautomizer-verify-uTZkv6EMXl/z3 [2023-11-12 02:32:48,557 INFO L229 MonitoredProcess]: Starting monitored process 4 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1deda2bf-224c-4242-8866-e899ae47e0d0/bin/uautomizer-verify-uTZkv6EMXl/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2023-11-12 02:32:48,563 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1deda2bf-224c-4242-8866-e899ae47e0d0/bin/uautomizer-verify-uTZkv6EMXl/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (4)] Waiting until timeout for monitored process [2023-11-12 02:32:48,564 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2023-11-12 02:32:48,564 INFO L160 nArgumentSynthesizer]: Using integer mode. [2023-11-12 02:32:48,594 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1deda2bf-224c-4242-8866-e899ae47e0d0/bin/uautomizer-verify-uTZkv6EMXl/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (4)] Forceful destruction successful, exit code 0 [2023-11-12 02:32:48,594 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2023-11-12 02:32:48,594 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1deda2bf-224c-4242-8866-e899ae47e0d0/bin/uautomizer-verify-uTZkv6EMXl/z3 [2023-11-12 02:32:48,596 INFO L229 MonitoredProcess]: Starting monitored process 5 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1deda2bf-224c-4242-8866-e899ae47e0d0/bin/uautomizer-verify-uTZkv6EMXl/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2023-11-12 02:32:48,606 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 3 Nilpotent components: true [2023-11-12 02:32:48,606 INFO L160 nArgumentSynthesizer]: Using integer mode. [2023-11-12 02:32:48,605 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1deda2bf-224c-4242-8866-e899ae47e0d0/bin/uautomizer-verify-uTZkv6EMXl/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (5)] Waiting until timeout for monitored process [2023-11-12 02:32:48,658 INFO L444 LassoAnalysis]: Proving nontermination failed: No geometric nontermination argument exists. [2023-11-12 02:32:48,664 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1deda2bf-224c-4242-8866-e899ae47e0d0/bin/uautomizer-verify-uTZkv6EMXl/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (5)] Ended with exit code 0 [2023-11-12 02:32:48,664 INFO L210 LassoAnalysis]: Preferences: [2023-11-12 02:32:48,664 INFO L126 ssoRankerPreferences]: Compute integeral hull: false [2023-11-12 02:32:48,664 INFO L127 ssoRankerPreferences]: Enable LassoPartitioneer: true [2023-11-12 02:32:48,664 INFO L128 ssoRankerPreferences]: Term annotations enabled: false [2023-11-12 02:32:48,665 INFO L129 ssoRankerPreferences]: Use exernal solver: false [2023-11-12 02:32:48,665 INFO L130 ssoRankerPreferences]: SMT solver command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2023-11-12 02:32:48,665 INFO L131 ssoRankerPreferences]: Dump SMT script to file: false [2023-11-12 02:32:48,665 INFO L132 ssoRankerPreferences]: Path of dumped script: [2023-11-12 02:32:48,665 INFO L133 ssoRankerPreferences]: Filename of dumped script: NarrowKonv.c_Iteration2_Loop [2023-11-12 02:32:48,665 INFO L134 ssoRankerPreferences]: MapElimAlgo: Frank [2023-11-12 02:32:48,665 INFO L276 LassoAnalysis]: Starting lasso preprocessing... [2023-11-12 02:32:48,667 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-12 02:32:48,672 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-12 02:32:48,680 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-12 02:32:48,773 INFO L294 LassoAnalysis]: Preprocessing complete. [2023-11-12 02:32:48,778 INFO L490 LassoAnalysis]: Using template 'affine'. [2023-11-12 02:32:48,780 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2023-11-12 02:32:48,780 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1deda2bf-224c-4242-8866-e899ae47e0d0/bin/uautomizer-verify-uTZkv6EMXl/z3 [2023-11-12 02:32:48,781 INFO L229 MonitoredProcess]: Starting monitored process 6 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1deda2bf-224c-4242-8866-e899ae47e0d0/bin/uautomizer-verify-uTZkv6EMXl/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2023-11-12 02:32:48,795 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1deda2bf-224c-4242-8866-e899ae47e0d0/bin/uautomizer-verify-uTZkv6EMXl/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (6)] Waiting until timeout for monitored process [2023-11-12 02:32:48,798 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2023-11-12 02:32:48,809 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2023-11-12 02:32:48,810 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2023-11-12 02:32:48,810 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2023-11-12 02:32:48,810 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2023-11-12 02:32:48,815 INFO L401 nArgumentSynthesizer]: We have 6 Motzkin's Theorem applications. [2023-11-12 02:32:48,816 INFO L402 nArgumentSynthesizer]: A total of 2 supporting invariants were added. [2023-11-12 02:32:48,830 INFO L527 LassoAnalysis]: Proving termination failed for this template and these settings. [2023-11-12 02:32:48,838 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1deda2bf-224c-4242-8866-e899ae47e0d0/bin/uautomizer-verify-uTZkv6EMXl/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (6)] Forceful destruction successful, exit code 0 [2023-11-12 02:32:48,838 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2023-11-12 02:32:48,839 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1deda2bf-224c-4242-8866-e899ae47e0d0/bin/uautomizer-verify-uTZkv6EMXl/z3 [2023-11-12 02:32:48,840 INFO L229 MonitoredProcess]: Starting monitored process 7 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1deda2bf-224c-4242-8866-e899ae47e0d0/bin/uautomizer-verify-uTZkv6EMXl/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2023-11-12 02:32:48,844 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2023-11-12 02:32:48,856 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2023-11-12 02:32:48,857 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2023-11-12 02:32:48,857 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2023-11-12 02:32:48,857 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2023-11-12 02:32:48,862 INFO L401 nArgumentSynthesizer]: We have 6 Motzkin's Theorem applications. [2023-11-12 02:32:48,863 INFO L402 nArgumentSynthesizer]: A total of 2 supporting invariants were added. [2023-11-12 02:32:48,869 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1deda2bf-224c-4242-8866-e899ae47e0d0/bin/uautomizer-verify-uTZkv6EMXl/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (7)] Waiting until timeout for monitored process [2023-11-12 02:32:48,880 INFO L527 LassoAnalysis]: Proving termination failed for this template and these settings. [2023-11-12 02:32:48,885 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1deda2bf-224c-4242-8866-e899ae47e0d0/bin/uautomizer-verify-uTZkv6EMXl/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (7)] Forceful destruction successful, exit code 0 [2023-11-12 02:32:48,886 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2023-11-12 02:32:48,886 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1deda2bf-224c-4242-8866-e899ae47e0d0/bin/uautomizer-verify-uTZkv6EMXl/z3 [2023-11-12 02:32:48,887 INFO L229 MonitoredProcess]: Starting monitored process 8 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1deda2bf-224c-4242-8866-e899ae47e0d0/bin/uautomizer-verify-uTZkv6EMXl/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2023-11-12 02:32:48,893 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1deda2bf-224c-4242-8866-e899ae47e0d0/bin/uautomizer-verify-uTZkv6EMXl/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (8)] Waiting until timeout for monitored process [2023-11-12 02:32:48,894 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2023-11-12 02:32:48,907 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2023-11-12 02:32:48,907 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2023-11-12 02:32:48,907 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2023-11-12 02:32:48,907 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2023-11-12 02:32:48,908 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2023-11-12 02:32:48,909 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2023-11-12 02:32:48,909 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2023-11-12 02:32:48,923 INFO L420 nArgumentSynthesizer]: Found a termination argument, trying to simplify. [2023-11-12 02:32:48,954 INFO L443 ModelExtractionUtils]: Simplification made 3 calls to the SMT solver. [2023-11-12 02:32:48,955 INFO L444 ModelExtractionUtils]: 1 out of 4 variables were initially zero. Simplification set additionally 0 variables to zero. [2023-11-12 02:32:48,956 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2023-11-12 02:32:48,956 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1deda2bf-224c-4242-8866-e899ae47e0d0/bin/uautomizer-verify-uTZkv6EMXl/z3 [2023-11-12 02:32:48,980 INFO L229 MonitoredProcess]: Starting monitored process 9 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1deda2bf-224c-4242-8866-e899ae47e0d0/bin/uautomizer-verify-uTZkv6EMXl/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2023-11-12 02:32:48,987 INFO L435 nArgumentSynthesizer]: Simplifying supporting invariants... [2023-11-12 02:32:48,987 INFO L438 nArgumentSynthesizer]: Removed 0 redundant supporting invariants from a total of 0. [2023-11-12 02:32:48,988 INFO L513 LassoAnalysis]: Proved termination. [2023-11-12 02:32:48,988 INFO L515 LassoAnalysis]: Termination argument consisting of: Ranking function f(ULTIMATE.start_main_~range~0#1, ULTIMATE.start_main_~i~0#1) = 1*ULTIMATE.start_main_~range~0#1 - 1*ULTIMATE.start_main_~i~0#1 Supporting invariants [] [2023-11-12 02:32:48,991 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1deda2bf-224c-4242-8866-e899ae47e0d0/bin/uautomizer-verify-uTZkv6EMXl/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (9)] Waiting until timeout for monitored process [2023-11-12 02:32:48,997 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1deda2bf-224c-4242-8866-e899ae47e0d0/bin/uautomizer-verify-uTZkv6EMXl/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (8)] Forceful destruction successful, exit code 0 [2023-11-12 02:32:49,001 INFO L156 tatePredicateManager]: 0 out of 0 supporting invariants were superfluous and have been removed [2023-11-12 02:32:49,034 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-12 02:32:49,047 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-12 02:32:49,048 INFO L262 TraceCheckSpWp]: Trace formula consists of 5 conjuncts, 2 conjunts are in the unsatisfiable core [2023-11-12 02:32:49,051 INFO L285 TraceCheckSpWp]: Computing forward predicates... [2023-11-12 02:32:49,065 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-12 02:32:49,066 WARN L260 TraceCheckSpWp]: Trace formula consists of 8 conjuncts, 5 conjunts are in the unsatisfiable core [2023-11-12 02:32:49,068 INFO L285 TraceCheckSpWp]: Computing forward predicates... [2023-11-12 02:32:49,115 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-12 02:32:49,120 INFO L141 lantAutomatonBouncer]: Defining deterministic Buchi interpolant automaton with honda bouncer for stem and without honda bouncer for loop.1 stem predicates 2 loop predicates [2023-11-12 02:32:49,121 INFO L71 iDifferenceNCSBLazy3]: Start buchiDifferenceNCSBLazy3. First operand 8 states and 11 transitions. cyclomatic complexity: 5 Second operand has 3 states, 3 states have (on average 1.6666666666666667) internal successors, (5), 3 states have internal predecessors, (5), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-12 02:32:49,172 INFO L75 iDifferenceNCSBLazy3]: Finished buchiDifferenceNCSBLazy3. First operand 8 states and 11 transitions. cyclomatic complexity: 5. Second operand has 3 states, 3 states have (on average 1.6666666666666667) internal successors, (5), 3 states have internal predecessors, (5), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Result 11 states and 15 transitions. Complement of second has 5 states. [2023-11-12 02:32:49,174 INFO L141 InterpolantAutomaton]: Switched to read-only mode: Buchi interpolant automaton has 3 states 1 stem states 1 non-accepting loop states 1 accepting loop states [2023-11-12 02:32:49,175 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 3 states, 3 states have (on average 1.6666666666666667) internal successors, (5), 3 states have internal predecessors, (5), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-12 02:32:49,176 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3 states to 3 states and 5 transitions. [2023-11-12 02:32:49,177 INFO L84 BuchiAccepts]: Start buchiAccepts Operand 3 states and 5 transitions. Stem has 2 letters. Loop has 3 letters. [2023-11-12 02:32:49,178 INFO L116 BuchiAccepts]: Finished buchiAccepts. [2023-11-12 02:32:49,178 INFO L84 BuchiAccepts]: Start buchiAccepts Operand 3 states and 5 transitions. Stem has 5 letters. Loop has 3 letters. [2023-11-12 02:32:49,178 INFO L116 BuchiAccepts]: Finished buchiAccepts. [2023-11-12 02:32:49,178 INFO L84 BuchiAccepts]: Start buchiAccepts Operand 3 states and 5 transitions. Stem has 2 letters. Loop has 6 letters. [2023-11-12 02:32:49,179 INFO L116 BuchiAccepts]: Finished buchiAccepts. [2023-11-12 02:32:49,179 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 11 states and 15 transitions. [2023-11-12 02:32:49,180 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 3 [2023-11-12 02:32:49,182 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 11 states to 11 states and 15 transitions. [2023-11-12 02:32:49,182 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 7 [2023-11-12 02:32:49,183 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 8 [2023-11-12 02:32:49,183 INFO L73 IsDeterministic]: Start isDeterministic. Operand 11 states and 15 transitions. [2023-11-12 02:32:49,183 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2023-11-12 02:32:49,183 INFO L218 hiAutomatonCegarLoop]: Abstraction has 11 states and 15 transitions. [2023-11-12 02:32:49,184 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 11 states and 15 transitions. [2023-11-12 02:32:49,185 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 11 to 11. [2023-11-12 02:32:49,186 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 11 states, 11 states have (on average 1.3636363636363635) internal successors, (15), 10 states have internal predecessors, (15), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-12 02:32:49,187 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 11 states to 11 states and 15 transitions. [2023-11-12 02:32:49,187 INFO L240 hiAutomatonCegarLoop]: Abstraction has 11 states and 15 transitions. [2023-11-12 02:32:49,187 INFO L428 stractBuchiCegarLoop]: Abstraction has 11 states and 15 transitions. [2023-11-12 02:32:49,189 INFO L335 stractBuchiCegarLoop]: ======== Iteration 3 ============ [2023-11-12 02:32:49,190 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 11 states and 15 transitions. [2023-11-12 02:32:49,190 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 3 [2023-11-12 02:32:49,191 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-12 02:32:49,191 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-12 02:32:49,191 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1] [2023-11-12 02:32:49,191 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1] [2023-11-12 02:32:49,192 INFO L748 eck$LassoCheckResult]: Stem: 95#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true; 96#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet0#1, main_~i~0#1, main_~range~0#1;havoc main_~i~0#1;havoc main_~range~0#1;havoc main_#t~nondet0#1;main_~i~0#1 := main_#t~nondet0#1;havoc main_#t~nondet0#1;main_~range~0#1 := 20; 97#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 92#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 93#L13 assume main_~i~0#1 == main_~range~0#1;main_~i~0#1 := 0;main_~range~0#1 := main_~range~0#1 - 1; 88#L12-1 [2023-11-12 02:32:49,192 INFO L750 eck$LassoCheckResult]: Loop: 88#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 89#L12 assume !!(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 88#L12-1 [2023-11-12 02:32:49,192 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-12 02:32:49,192 INFO L85 PathProgramCache]: Analyzing trace with hash 28699755, now seen corresponding path program 1 times [2023-11-12 02:32:49,193 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-12 02:32:49,193 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1195048366] [2023-11-12 02:32:49,193 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-12 02:32:49,193 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-12 02:32:49,200 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-12 02:32:49,200 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-12 02:32:49,205 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-12 02:32:49,206 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-12 02:32:49,207 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-12 02:32:49,207 INFO L85 PathProgramCache]: Analyzing trace with hash 1324, now seen corresponding path program 2 times [2023-11-12 02:32:49,207 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-12 02:32:49,207 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1849255822] [2023-11-12 02:32:49,207 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-12 02:32:49,208 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-12 02:32:49,212 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-12 02:32:49,212 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-12 02:32:49,214 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-12 02:32:49,215 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-12 02:32:49,215 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-12 02:32:49,216 INFO L85 PathProgramCache]: Analyzing trace with hash 1810661142, now seen corresponding path program 1 times [2023-11-12 02:32:49,216 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-12 02:32:49,216 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2097549857] [2023-11-12 02:32:49,216 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-12 02:32:49,216 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-12 02:32:49,223 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-12 02:32:49,269 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-12 02:32:49,270 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-12 02:32:49,270 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2097549857] [2023-11-12 02:32:49,270 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2097549857] provided 0 perfect and 1 imperfect interpolant sequences [2023-11-12 02:32:49,270 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1389245] [2023-11-12 02:32:49,270 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-12 02:32:49,271 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2023-11-12 02:32:49,271 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1deda2bf-224c-4242-8866-e899ae47e0d0/bin/uautomizer-verify-uTZkv6EMXl/z3 [2023-11-12 02:32:49,272 INFO L229 MonitoredProcess]: Starting monitored process 10 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1deda2bf-224c-4242-8866-e899ae47e0d0/bin/uautomizer-verify-uTZkv6EMXl/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2023-11-12 02:32:49,293 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1deda2bf-224c-4242-8866-e899ae47e0d0/bin/uautomizer-verify-uTZkv6EMXl/z3 -smt2 -in SMTLIB2_COMPLIANT=true (10)] Waiting until timeout for monitored process [2023-11-12 02:32:49,315 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-12 02:32:49,316 INFO L262 TraceCheckSpWp]: Trace formula consists of 20 conjuncts, 4 conjunts are in the unsatisfiable core [2023-11-12 02:32:49,317 INFO L285 TraceCheckSpWp]: Computing forward predicates... [2023-11-12 02:32:49,387 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-12 02:32:49,387 INFO L327 TraceCheckSpWp]: Computing backward predicates... [2023-11-12 02:32:49,420 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-12 02:32:49,421 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1389245] provided 0 perfect and 2 imperfect interpolant sequences [2023-11-12 02:32:49,421 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2023-11-12 02:32:49,421 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [3, 3, 3] total 6 [2023-11-12 02:32:49,421 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1975013289] [2023-11-12 02:32:49,422 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2023-11-12 02:32:49,448 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-12 02:32:49,449 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 7 interpolants. [2023-11-12 02:32:49,449 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=16, Invalid=26, Unknown=0, NotChecked=0, Total=42 [2023-11-12 02:32:49,449 INFO L87 Difference]: Start difference. First operand 11 states and 15 transitions. cyclomatic complexity: 6 Second operand has 7 states, 6 states have (on average 2.6666666666666665) internal successors, (16), 7 states have internal predecessors, (16), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-12 02:32:49,520 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-12 02:32:49,520 INFO L93 Difference]: Finished difference Result 23 states and 28 transitions. [2023-11-12 02:32:49,521 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 23 states and 28 transitions. [2023-11-12 02:32:49,525 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 6 [2023-11-12 02:32:49,528 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 23 states to 23 states and 28 transitions. [2023-11-12 02:32:49,528 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 20 [2023-11-12 02:32:49,529 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 20 [2023-11-12 02:32:49,529 INFO L73 IsDeterministic]: Start isDeterministic. Operand 23 states and 28 transitions. [2023-11-12 02:32:49,529 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2023-11-12 02:32:49,529 INFO L218 hiAutomatonCegarLoop]: Abstraction has 23 states and 28 transitions. [2023-11-12 02:32:49,530 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 23 states and 28 transitions. [2023-11-12 02:32:49,534 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 23 to 23. [2023-11-12 02:32:49,535 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 23 states, 23 states have (on average 1.2173913043478262) internal successors, (28), 22 states have internal predecessors, (28), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-12 02:32:49,539 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 23 states to 23 states and 28 transitions. [2023-11-12 02:32:49,539 INFO L240 hiAutomatonCegarLoop]: Abstraction has 23 states and 28 transitions. [2023-11-12 02:32:49,539 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2023-11-12 02:32:49,541 INFO L428 stractBuchiCegarLoop]: Abstraction has 23 states and 28 transitions. [2023-11-12 02:32:49,541 INFO L335 stractBuchiCegarLoop]: ======== Iteration 4 ============ [2023-11-12 02:32:49,541 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 23 states and 28 transitions. [2023-11-12 02:32:49,543 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 6 [2023-11-12 02:32:49,543 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-12 02:32:49,544 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-12 02:32:49,544 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [3, 3, 2, 1, 1, 1] [2023-11-12 02:32:49,544 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1] [2023-11-12 02:32:49,545 INFO L748 eck$LassoCheckResult]: Stem: 180#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true; 181#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet0#1, main_~i~0#1, main_~range~0#1;havoc main_~i~0#1;havoc main_~range~0#1;havoc main_#t~nondet0#1;main_~i~0#1 := main_#t~nondet0#1;havoc main_#t~nondet0#1;main_~range~0#1 := 20; 182#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 176#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 183#L13 assume main_~i~0#1 == main_~range~0#1;main_~i~0#1 := 0;main_~range~0#1 := main_~range~0#1 - 1; 172#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 173#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 177#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 178#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 194#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 193#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 186#L12-1 [2023-11-12 02:32:49,545 INFO L750 eck$LassoCheckResult]: Loop: 186#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 191#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 184#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 186#L12-1 [2023-11-12 02:32:49,545 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-12 02:32:49,545 INFO L85 PathProgramCache]: Analyzing trace with hash -1805445589, now seen corresponding path program 1 times [2023-11-12 02:32:49,546 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-12 02:32:49,546 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [376373951] [2023-11-12 02:32:49,546 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-12 02:32:49,546 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-12 02:32:49,570 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-12 02:32:49,584 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-12 02:32:49,590 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-12 02:32:49,597 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-12 02:32:49,597 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-12 02:32:49,597 INFO L85 PathProgramCache]: Analyzing trace with hash 40815, now seen corresponding path program 2 times [2023-11-12 02:32:49,598 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-12 02:32:49,598 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [634642269] [2023-11-12 02:32:49,598 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-12 02:32:49,598 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-12 02:32:49,602 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-12 02:32:49,607 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-12 02:32:49,611 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-12 02:32:49,626 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-12 02:32:49,627 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-12 02:32:49,627 INFO L85 PathProgramCache]: Analyzing trace with hash -154083067, now seen corresponding path program 2 times [2023-11-12 02:32:49,627 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-12 02:32:49,628 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [654871978] [2023-11-12 02:32:49,628 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-12 02:32:49,628 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-12 02:32:49,648 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-12 02:32:49,651 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-12 02:32:49,664 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-12 02:32:49,668 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-12 02:32:49,714 INFO L210 LassoAnalysis]: Preferences: [2023-11-12 02:32:49,715 INFO L126 ssoRankerPreferences]: Compute integeral hull: false [2023-11-12 02:32:49,715 INFO L127 ssoRankerPreferences]: Enable LassoPartitioneer: true [2023-11-12 02:32:49,715 INFO L128 ssoRankerPreferences]: Term annotations enabled: false [2023-11-12 02:32:49,715 INFO L129 ssoRankerPreferences]: Use exernal solver: true [2023-11-12 02:32:49,715 INFO L130 ssoRankerPreferences]: SMT solver command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2023-11-12 02:32:49,715 INFO L131 ssoRankerPreferences]: Dump SMT script to file: false [2023-11-12 02:32:49,716 INFO L132 ssoRankerPreferences]: Path of dumped script: [2023-11-12 02:32:49,716 INFO L133 ssoRankerPreferences]: Filename of dumped script: NarrowKonv.c_Iteration4_Loop [2023-11-12 02:32:49,717 INFO L134 ssoRankerPreferences]: MapElimAlgo: Frank [2023-11-12 02:32:49,719 INFO L276 LassoAnalysis]: Starting lasso preprocessing... [2023-11-12 02:32:49,721 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-12 02:32:49,724 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-12 02:32:49,729 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-12 02:32:49,801 INFO L294 LassoAnalysis]: Preprocessing complete. [2023-11-12 02:32:49,801 INFO L404 LassoAnalysis]: Checking for nontermination... [2023-11-12 02:32:49,801 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2023-11-12 02:32:49,802 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1deda2bf-224c-4242-8866-e899ae47e0d0/bin/uautomizer-verify-uTZkv6EMXl/z3 [2023-11-12 02:32:49,809 INFO L229 MonitoredProcess]: Starting monitored process 11 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1deda2bf-224c-4242-8866-e899ae47e0d0/bin/uautomizer-verify-uTZkv6EMXl/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2023-11-12 02:32:49,834 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2023-11-12 02:32:49,834 INFO L160 nArgumentSynthesizer]: Using integer mode. [2023-11-12 02:32:49,845 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1deda2bf-224c-4242-8866-e899ae47e0d0/bin/uautomizer-verify-uTZkv6EMXl/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (11)] Waiting until timeout for monitored process [2023-11-12 02:32:49,856 INFO L437 LassoAnalysis]: Proved nontermination for one component. [2023-11-12 02:32:49,856 INFO L440 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {v_rep~unnamed0~0~false_3=0} Honda state: {v_rep~unnamed0~0~false_3=0} Generalized eigenvectors: [] Lambdas: [] Nus: [] [2023-11-12 02:32:49,865 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1deda2bf-224c-4242-8866-e899ae47e0d0/bin/uautomizer-verify-uTZkv6EMXl/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (11)] Forceful destruction successful, exit code 0 [2023-11-12 02:32:49,865 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2023-11-12 02:32:49,865 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1deda2bf-224c-4242-8866-e899ae47e0d0/bin/uautomizer-verify-uTZkv6EMXl/z3 [2023-11-12 02:32:49,867 INFO L229 MonitoredProcess]: Starting monitored process 12 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1deda2bf-224c-4242-8866-e899ae47e0d0/bin/uautomizer-verify-uTZkv6EMXl/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2023-11-12 02:32:49,880 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2023-11-12 02:32:49,880 INFO L160 nArgumentSynthesizer]: Using integer mode. [2023-11-12 02:32:49,893 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1deda2bf-224c-4242-8866-e899ae47e0d0/bin/uautomizer-verify-uTZkv6EMXl/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (12)] Waiting until timeout for monitored process [2023-11-12 02:32:49,909 INFO L437 LassoAnalysis]: Proved nontermination for one component. [2023-11-12 02:32:49,909 INFO L440 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {v_rep~unnamed0~0~true_3=1} Honda state: {v_rep~unnamed0~0~true_3=1} Generalized eigenvectors: [] Lambdas: [] Nus: [] [2023-11-12 02:32:49,917 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1deda2bf-224c-4242-8866-e899ae47e0d0/bin/uautomizer-verify-uTZkv6EMXl/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (12)] Forceful destruction successful, exit code 0 [2023-11-12 02:32:49,918 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2023-11-12 02:32:49,918 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1deda2bf-224c-4242-8866-e899ae47e0d0/bin/uautomizer-verify-uTZkv6EMXl/z3 [2023-11-12 02:32:49,919 INFO L229 MonitoredProcess]: Starting monitored process 13 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1deda2bf-224c-4242-8866-e899ae47e0d0/bin/uautomizer-verify-uTZkv6EMXl/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2023-11-12 02:32:49,923 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2023-11-12 02:32:49,923 INFO L160 nArgumentSynthesizer]: Using integer mode. [2023-11-12 02:32:49,923 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1deda2bf-224c-4242-8866-e899ae47e0d0/bin/uautomizer-verify-uTZkv6EMXl/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (13)] Waiting until timeout for monitored process [2023-11-12 02:32:49,954 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1deda2bf-224c-4242-8866-e899ae47e0d0/bin/uautomizer-verify-uTZkv6EMXl/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (13)] Forceful destruction successful, exit code 0 [2023-11-12 02:32:49,954 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2023-11-12 02:32:49,954 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1deda2bf-224c-4242-8866-e899ae47e0d0/bin/uautomizer-verify-uTZkv6EMXl/z3 [2023-11-12 02:32:49,955 INFO L229 MonitoredProcess]: Starting monitored process 14 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1deda2bf-224c-4242-8866-e899ae47e0d0/bin/uautomizer-verify-uTZkv6EMXl/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2023-11-12 02:32:49,958 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1deda2bf-224c-4242-8866-e899ae47e0d0/bin/uautomizer-verify-uTZkv6EMXl/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (14)] Waiting until timeout for monitored process [2023-11-12 02:32:49,958 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 3 Nilpotent components: true [2023-11-12 02:32:49,959 INFO L160 nArgumentSynthesizer]: Using integer mode. [2023-11-12 02:32:50,019 INFO L444 LassoAnalysis]: Proving nontermination failed: No geometric nontermination argument exists. [2023-11-12 02:32:50,030 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1deda2bf-224c-4242-8866-e899ae47e0d0/bin/uautomizer-verify-uTZkv6EMXl/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (14)] Forceful destruction successful, exit code 0 [2023-11-12 02:32:50,030 INFO L210 LassoAnalysis]: Preferences: [2023-11-12 02:32:50,030 INFO L126 ssoRankerPreferences]: Compute integeral hull: false [2023-11-12 02:32:50,030 INFO L127 ssoRankerPreferences]: Enable LassoPartitioneer: true [2023-11-12 02:32:50,030 INFO L128 ssoRankerPreferences]: Term annotations enabled: false [2023-11-12 02:32:50,030 INFO L129 ssoRankerPreferences]: Use exernal solver: false [2023-11-12 02:32:50,031 INFO L130 ssoRankerPreferences]: SMT solver command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2023-11-12 02:32:50,031 INFO L131 ssoRankerPreferences]: Dump SMT script to file: false [2023-11-12 02:32:50,031 INFO L132 ssoRankerPreferences]: Path of dumped script: [2023-11-12 02:32:50,031 INFO L133 ssoRankerPreferences]: Filename of dumped script: NarrowKonv.c_Iteration4_Loop [2023-11-12 02:32:50,031 INFO L134 ssoRankerPreferences]: MapElimAlgo: Frank [2023-11-12 02:32:50,031 INFO L276 LassoAnalysis]: Starting lasso preprocessing... [2023-11-12 02:32:50,032 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-12 02:32:50,036 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-12 02:32:50,051 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-12 02:32:50,112 INFO L294 LassoAnalysis]: Preprocessing complete. [2023-11-12 02:32:50,112 INFO L490 LassoAnalysis]: Using template 'affine'. [2023-11-12 02:32:50,112 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2023-11-12 02:32:50,112 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1deda2bf-224c-4242-8866-e899ae47e0d0/bin/uautomizer-verify-uTZkv6EMXl/z3 [2023-11-12 02:32:50,114 INFO L229 MonitoredProcess]: Starting monitored process 15 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1deda2bf-224c-4242-8866-e899ae47e0d0/bin/uautomizer-verify-uTZkv6EMXl/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2023-11-12 02:32:50,128 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2023-11-12 02:32:50,140 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2023-11-12 02:32:50,140 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2023-11-12 02:32:50,140 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2023-11-12 02:32:50,140 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2023-11-12 02:32:50,143 INFO L401 nArgumentSynthesizer]: We have 6 Motzkin's Theorem applications. [2023-11-12 02:32:50,143 INFO L402 nArgumentSynthesizer]: A total of 2 supporting invariants were added. [2023-11-12 02:32:50,145 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1deda2bf-224c-4242-8866-e899ae47e0d0/bin/uautomizer-verify-uTZkv6EMXl/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (15)] Waiting until timeout for monitored process [2023-11-12 02:32:50,155 INFO L527 LassoAnalysis]: Proving termination failed for this template and these settings. [2023-11-12 02:32:50,168 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1deda2bf-224c-4242-8866-e899ae47e0d0/bin/uautomizer-verify-uTZkv6EMXl/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (15)] Forceful destruction successful, exit code 0 [2023-11-12 02:32:50,168 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2023-11-12 02:32:50,168 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1deda2bf-224c-4242-8866-e899ae47e0d0/bin/uautomizer-verify-uTZkv6EMXl/z3 [2023-11-12 02:32:50,169 INFO L229 MonitoredProcess]: Starting monitored process 16 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1deda2bf-224c-4242-8866-e899ae47e0d0/bin/uautomizer-verify-uTZkv6EMXl/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2023-11-12 02:32:50,175 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1deda2bf-224c-4242-8866-e899ae47e0d0/bin/uautomizer-verify-uTZkv6EMXl/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (16)] Waiting until timeout for monitored process [2023-11-12 02:32:50,176 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2023-11-12 02:32:50,188 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2023-11-12 02:32:50,188 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2023-11-12 02:32:50,188 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2023-11-12 02:32:50,189 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2023-11-12 02:32:50,189 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2023-11-12 02:32:50,190 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2023-11-12 02:32:50,190 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2023-11-12 02:32:50,200 INFO L420 nArgumentSynthesizer]: Found a termination argument, trying to simplify. [2023-11-12 02:32:50,203 INFO L443 ModelExtractionUtils]: Simplification made 3 calls to the SMT solver. [2023-11-12 02:32:50,203 INFO L444 ModelExtractionUtils]: 1 out of 4 variables were initially zero. Simplification set additionally 0 variables to zero. [2023-11-12 02:32:50,204 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2023-11-12 02:32:50,204 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1deda2bf-224c-4242-8866-e899ae47e0d0/bin/uautomizer-verify-uTZkv6EMXl/z3 [2023-11-12 02:32:50,210 INFO L229 MonitoredProcess]: Starting monitored process 17 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1deda2bf-224c-4242-8866-e899ae47e0d0/bin/uautomizer-verify-uTZkv6EMXl/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2023-11-12 02:32:50,217 INFO L435 nArgumentSynthesizer]: Simplifying supporting invariants... [2023-11-12 02:32:50,217 INFO L438 nArgumentSynthesizer]: Removed 0 redundant supporting invariants from a total of 0. [2023-11-12 02:32:50,217 INFO L513 LassoAnalysis]: Proved termination. [2023-11-12 02:32:50,218 INFO L515 LassoAnalysis]: Termination argument consisting of: Ranking function f(ULTIMATE.start_main_~range~0#1, ULTIMATE.start_main_~i~0#1) = 1*ULTIMATE.start_main_~range~0#1 - 1*ULTIMATE.start_main_~i~0#1 Supporting invariants [] [2023-11-12 02:32:50,220 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1deda2bf-224c-4242-8866-e899ae47e0d0/bin/uautomizer-verify-uTZkv6EMXl/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (17)] Waiting until timeout for monitored process [2023-11-12 02:32:50,226 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1deda2bf-224c-4242-8866-e899ae47e0d0/bin/uautomizer-verify-uTZkv6EMXl/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (16)] Forceful destruction successful, exit code 0 [2023-11-12 02:32:50,227 INFO L156 tatePredicateManager]: 0 out of 0 supporting invariants were superfluous and have been removed [2023-11-12 02:32:50,242 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-12 02:32:50,253 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-12 02:32:50,254 INFO L262 TraceCheckSpWp]: Trace formula consists of 26 conjuncts, 2 conjunts are in the unsatisfiable core [2023-11-12 02:32:50,254 INFO L285 TraceCheckSpWp]: Computing forward predicates... [2023-11-12 02:32:50,276 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-12 02:32:50,277 WARN L260 TraceCheckSpWp]: Trace formula consists of 8 conjuncts, 5 conjunts are in the unsatisfiable core [2023-11-12 02:32:50,278 INFO L285 TraceCheckSpWp]: Computing forward predicates... [2023-11-12 02:32:50,316 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1deda2bf-224c-4242-8866-e899ae47e0d0/bin/uautomizer-verify-uTZkv6EMXl/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (9)] Forceful destruction successful, exit code 0 [2023-11-12 02:32:50,326 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1deda2bf-224c-4242-8866-e899ae47e0d0/bin/uautomizer-verify-uTZkv6EMXl/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (17)] Forceful destruction successful, exit code 0 [2023-11-12 02:32:50,338 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-12 02:32:50,338 INFO L141 lantAutomatonBouncer]: Defining deterministic Buchi interpolant automaton with honda bouncer for stem and without honda bouncer for loop.1 stem predicates 2 loop predicates [2023-11-12 02:32:50,339 INFO L71 iDifferenceNCSBLazy3]: Start buchiDifferenceNCSBLazy3. First operand 23 states and 28 transitions. cyclomatic complexity: 8 Second operand has 3 states, 3 states have (on average 3.3333333333333335) internal successors, (10), 3 states have internal predecessors, (10), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-12 02:32:50,393 INFO L75 iDifferenceNCSBLazy3]: Finished buchiDifferenceNCSBLazy3. First operand 23 states and 28 transitions. cyclomatic complexity: 8. Second operand has 3 states, 3 states have (on average 3.3333333333333335) internal successors, (10), 3 states have internal predecessors, (10), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Result 44 states and 50 transitions. Complement of second has 5 states. [2023-11-12 02:32:50,393 INFO L141 InterpolantAutomaton]: Switched to read-only mode: Buchi interpolant automaton has 3 states 1 stem states 1 non-accepting loop states 1 accepting loop states [2023-11-12 02:32:50,394 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 3 states, 3 states have (on average 3.3333333333333335) internal successors, (10), 3 states have internal predecessors, (10), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-12 02:32:50,395 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3 states to 3 states and 9 transitions. [2023-11-12 02:32:50,395 INFO L84 BuchiAccepts]: Start buchiAccepts Operand 3 states and 9 transitions. Stem has 11 letters. Loop has 3 letters. [2023-11-12 02:32:50,395 INFO L116 BuchiAccepts]: Finished buchiAccepts. [2023-11-12 02:32:50,396 INFO L84 BuchiAccepts]: Start buchiAccepts Operand 3 states and 9 transitions. Stem has 14 letters. Loop has 3 letters. [2023-11-12 02:32:50,396 INFO L116 BuchiAccepts]: Finished buchiAccepts. [2023-11-12 02:32:50,396 INFO L84 BuchiAccepts]: Start buchiAccepts Operand 3 states and 9 transitions. Stem has 11 letters. Loop has 6 letters. [2023-11-12 02:32:50,397 INFO L116 BuchiAccepts]: Finished buchiAccepts. [2023-11-12 02:32:50,397 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 44 states and 50 transitions. [2023-11-12 02:32:50,399 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 6 [2023-11-12 02:32:50,400 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 44 states to 38 states and 44 transitions. [2023-11-12 02:32:50,401 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 27 [2023-11-12 02:32:50,401 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 28 [2023-11-12 02:32:50,401 INFO L73 IsDeterministic]: Start isDeterministic. Operand 38 states and 44 transitions. [2023-11-12 02:32:50,401 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2023-11-12 02:32:50,401 INFO L218 hiAutomatonCegarLoop]: Abstraction has 38 states and 44 transitions. [2023-11-12 02:32:50,402 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 38 states and 44 transitions. [2023-11-12 02:32:50,404 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 38 to 34. [2023-11-12 02:32:50,414 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 34 states, 34 states have (on average 1.1764705882352942) internal successors, (40), 33 states have internal predecessors, (40), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-12 02:32:50,415 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 34 states to 34 states and 40 transitions. [2023-11-12 02:32:50,415 INFO L240 hiAutomatonCegarLoop]: Abstraction has 34 states and 40 transitions. [2023-11-12 02:32:50,415 INFO L428 stractBuchiCegarLoop]: Abstraction has 34 states and 40 transitions. [2023-11-12 02:32:50,415 INFO L335 stractBuchiCegarLoop]: ======== Iteration 5 ============ [2023-11-12 02:32:50,415 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 34 states and 40 transitions. [2023-11-12 02:32:50,417 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 6 [2023-11-12 02:32:50,417 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-12 02:32:50,417 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-12 02:32:50,417 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [4, 4, 3, 1, 1, 1] [2023-11-12 02:32:50,418 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1] [2023-11-12 02:32:50,418 INFO L748 eck$LassoCheckResult]: Stem: 309#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true; 310#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet0#1, main_~i~0#1, main_~range~0#1;havoc main_~i~0#1;havoc main_~range~0#1;havoc main_#t~nondet0#1;main_~i~0#1 := main_#t~nondet0#1;havoc main_#t~nondet0#1;main_~range~0#1 := 20; 311#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 305#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 308#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 303#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 304#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 320#L13 assume main_~i~0#1 == main_~range~0#1;main_~i~0#1 := 0;main_~range~0#1 := main_~range~0#1 - 1; 301#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 302#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 306#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 307#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 333#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 331#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 323#L12-1 [2023-11-12 02:32:50,418 INFO L750 eck$LassoCheckResult]: Loop: 323#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 329#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 321#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 323#L12-1 [2023-11-12 02:32:50,418 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-12 02:32:50,419 INFO L85 PathProgramCache]: Analyzing trace with hash 1972849857, now seen corresponding path program 3 times [2023-11-12 02:32:50,419 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-12 02:32:50,419 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [999007546] [2023-11-12 02:32:50,419 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-12 02:32:50,419 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-12 02:32:50,430 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-12 02:32:50,445 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-12 02:32:50,453 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-12 02:32:50,455 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-12 02:32:50,456 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-12 02:32:50,457 INFO L85 PathProgramCache]: Analyzing trace with hash 40815, now seen corresponding path program 3 times [2023-11-12 02:32:50,458 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-12 02:32:50,458 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1465930077] [2023-11-12 02:32:50,461 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-12 02:32:50,462 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-12 02:32:50,465 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-12 02:32:50,466 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-12 02:32:50,468 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-12 02:32:50,468 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-12 02:32:50,469 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-12 02:32:50,469 INFO L85 PathProgramCache]: Analyzing trace with hash 837622447, now seen corresponding path program 4 times [2023-11-12 02:32:50,469 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-12 02:32:50,469 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1991564993] [2023-11-12 02:32:50,470 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-12 02:32:50,470 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-12 02:32:50,484 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-12 02:32:50,484 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-12 02:32:50,505 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-12 02:32:50,507 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-12 02:32:50,548 INFO L210 LassoAnalysis]: Preferences: [2023-11-12 02:32:50,548 INFO L126 ssoRankerPreferences]: Compute integeral hull: false [2023-11-12 02:32:50,548 INFO L127 ssoRankerPreferences]: Enable LassoPartitioneer: true [2023-11-12 02:32:50,548 INFO L128 ssoRankerPreferences]: Term annotations enabled: false [2023-11-12 02:32:50,548 INFO L129 ssoRankerPreferences]: Use exernal solver: true [2023-11-12 02:32:50,548 INFO L130 ssoRankerPreferences]: SMT solver command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2023-11-12 02:32:50,548 INFO L131 ssoRankerPreferences]: Dump SMT script to file: false [2023-11-12 02:32:50,549 INFO L132 ssoRankerPreferences]: Path of dumped script: [2023-11-12 02:32:50,549 INFO L133 ssoRankerPreferences]: Filename of dumped script: NarrowKonv.c_Iteration5_Loop [2023-11-12 02:32:50,549 INFO L134 ssoRankerPreferences]: MapElimAlgo: Frank [2023-11-12 02:32:50,549 INFO L276 LassoAnalysis]: Starting lasso preprocessing... [2023-11-12 02:32:50,550 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-12 02:32:50,554 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-12 02:32:50,563 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-12 02:32:50,615 INFO L294 LassoAnalysis]: Preprocessing complete. [2023-11-12 02:32:50,615 INFO L404 LassoAnalysis]: Checking for nontermination... [2023-11-12 02:32:50,615 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2023-11-12 02:32:50,615 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1deda2bf-224c-4242-8866-e899ae47e0d0/bin/uautomizer-verify-uTZkv6EMXl/z3 [2023-11-12 02:32:50,616 INFO L229 MonitoredProcess]: Starting monitored process 18 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1deda2bf-224c-4242-8866-e899ae47e0d0/bin/uautomizer-verify-uTZkv6EMXl/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2023-11-12 02:32:50,623 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2023-11-12 02:32:50,623 INFO L160 nArgumentSynthesizer]: Using integer mode. [2023-11-12 02:32:50,636 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1deda2bf-224c-4242-8866-e899ae47e0d0/bin/uautomizer-verify-uTZkv6EMXl/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (18)] Waiting until timeout for monitored process [2023-11-12 02:32:50,646 INFO L437 LassoAnalysis]: Proved nontermination for one component. [2023-11-12 02:32:50,646 INFO L440 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {v_rep~unnamed0~0~true_5=1} Honda state: {v_rep~unnamed0~0~true_5=1} Generalized eigenvectors: [] Lambdas: [] Nus: [] [2023-11-12 02:32:50,655 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1deda2bf-224c-4242-8866-e899ae47e0d0/bin/uautomizer-verify-uTZkv6EMXl/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (18)] Forceful destruction successful, exit code 0 [2023-11-12 02:32:50,655 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2023-11-12 02:32:50,655 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1deda2bf-224c-4242-8866-e899ae47e0d0/bin/uautomizer-verify-uTZkv6EMXl/z3 [2023-11-12 02:32:50,658 INFO L229 MonitoredProcess]: Starting monitored process 19 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1deda2bf-224c-4242-8866-e899ae47e0d0/bin/uautomizer-verify-uTZkv6EMXl/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2023-11-12 02:32:50,668 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2023-11-12 02:32:50,668 INFO L160 nArgumentSynthesizer]: Using integer mode. [2023-11-12 02:32:50,675 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1deda2bf-224c-4242-8866-e899ae47e0d0/bin/uautomizer-verify-uTZkv6EMXl/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (19)] Waiting until timeout for monitored process [2023-11-12 02:32:50,697 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1deda2bf-224c-4242-8866-e899ae47e0d0/bin/uautomizer-verify-uTZkv6EMXl/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (19)] Forceful destruction successful, exit code 0 [2023-11-12 02:32:50,698 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2023-11-12 02:32:50,698 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1deda2bf-224c-4242-8866-e899ae47e0d0/bin/uautomizer-verify-uTZkv6EMXl/z3 [2023-11-12 02:32:50,699 INFO L229 MonitoredProcess]: Starting monitored process 20 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1deda2bf-224c-4242-8866-e899ae47e0d0/bin/uautomizer-verify-uTZkv6EMXl/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2023-11-12 02:32:50,706 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 3 Nilpotent components: true [2023-11-12 02:32:50,706 INFO L160 nArgumentSynthesizer]: Using integer mode. [2023-11-12 02:32:50,719 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1deda2bf-224c-4242-8866-e899ae47e0d0/bin/uautomizer-verify-uTZkv6EMXl/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (20)] Waiting until timeout for monitored process [2023-11-12 02:32:50,774 INFO L444 LassoAnalysis]: Proving nontermination failed: No geometric nontermination argument exists. [2023-11-12 02:32:50,783 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1deda2bf-224c-4242-8866-e899ae47e0d0/bin/uautomizer-verify-uTZkv6EMXl/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (20)] Forceful destruction successful, exit code 0 [2023-11-12 02:32:50,783 INFO L210 LassoAnalysis]: Preferences: [2023-11-12 02:32:50,783 INFO L126 ssoRankerPreferences]: Compute integeral hull: false [2023-11-12 02:32:50,783 INFO L127 ssoRankerPreferences]: Enable LassoPartitioneer: true [2023-11-12 02:32:50,783 INFO L128 ssoRankerPreferences]: Term annotations enabled: false [2023-11-12 02:32:50,783 INFO L129 ssoRankerPreferences]: Use exernal solver: false [2023-11-12 02:32:50,784 INFO L130 ssoRankerPreferences]: SMT solver command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2023-11-12 02:32:50,784 INFO L131 ssoRankerPreferences]: Dump SMT script to file: false [2023-11-12 02:32:50,784 INFO L132 ssoRankerPreferences]: Path of dumped script: [2023-11-12 02:32:50,784 INFO L133 ssoRankerPreferences]: Filename of dumped script: NarrowKonv.c_Iteration5_Loop [2023-11-12 02:32:50,784 INFO L134 ssoRankerPreferences]: MapElimAlgo: Frank [2023-11-12 02:32:50,784 INFO L276 LassoAnalysis]: Starting lasso preprocessing... [2023-11-12 02:32:50,785 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-12 02:32:50,797 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-12 02:32:50,800 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-12 02:32:50,856 INFO L294 LassoAnalysis]: Preprocessing complete. [2023-11-12 02:32:50,856 INFO L490 LassoAnalysis]: Using template 'affine'. [2023-11-12 02:32:50,856 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2023-11-12 02:32:50,856 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1deda2bf-224c-4242-8866-e899ae47e0d0/bin/uautomizer-verify-uTZkv6EMXl/z3 [2023-11-12 02:32:50,858 INFO L229 MonitoredProcess]: Starting monitored process 21 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1deda2bf-224c-4242-8866-e899ae47e0d0/bin/uautomizer-verify-uTZkv6EMXl/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2023-11-12 02:32:50,864 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2023-11-12 02:32:50,876 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2023-11-12 02:32:50,876 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2023-11-12 02:32:50,876 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2023-11-12 02:32:50,876 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2023-11-12 02:32:50,876 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2023-11-12 02:32:50,877 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1deda2bf-224c-4242-8866-e899ae47e0d0/bin/uautomizer-verify-uTZkv6EMXl/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (21)] Waiting until timeout for monitored process [2023-11-12 02:32:50,878 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2023-11-12 02:32:50,878 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2023-11-12 02:32:50,887 INFO L420 nArgumentSynthesizer]: Found a termination argument, trying to simplify. [2023-11-12 02:32:50,893 INFO L443 ModelExtractionUtils]: Simplification made 3 calls to the SMT solver. [2023-11-12 02:32:50,893 INFO L444 ModelExtractionUtils]: 0 out of 4 variables were initially zero. Simplification set additionally 1 variables to zero. [2023-11-12 02:32:50,893 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2023-11-12 02:32:50,893 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1deda2bf-224c-4242-8866-e899ae47e0d0/bin/uautomizer-verify-uTZkv6EMXl/z3 [2023-11-12 02:32:50,894 INFO L229 MonitoredProcess]: Starting monitored process 22 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1deda2bf-224c-4242-8866-e899ae47e0d0/bin/uautomizer-verify-uTZkv6EMXl/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2023-11-12 02:32:50,907 INFO L435 nArgumentSynthesizer]: Simplifying supporting invariants... [2023-11-12 02:32:50,908 INFO L438 nArgumentSynthesizer]: Removed 0 redundant supporting invariants from a total of 0. [2023-11-12 02:32:50,908 INFO L513 LassoAnalysis]: Proved termination. [2023-11-12 02:32:50,908 INFO L515 LassoAnalysis]: Termination argument consisting of: Ranking function f(ULTIMATE.start_main_~i~0#1, ULTIMATE.start_main_~range~0#1) = -1*ULTIMATE.start_main_~i~0#1 + 1*ULTIMATE.start_main_~range~0#1 Supporting invariants [] [2023-11-12 02:32:50,911 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1deda2bf-224c-4242-8866-e899ae47e0d0/bin/uautomizer-verify-uTZkv6EMXl/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (22)] Waiting until timeout for monitored process [2023-11-12 02:32:50,913 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1deda2bf-224c-4242-8866-e899ae47e0d0/bin/uautomizer-verify-uTZkv6EMXl/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (21)] Forceful destruction successful, exit code 0 [2023-11-12 02:32:50,914 INFO L156 tatePredicateManager]: 0 out of 0 supporting invariants were superfluous and have been removed [2023-11-12 02:32:50,932 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-12 02:32:50,944 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-12 02:32:50,945 INFO L262 TraceCheckSpWp]: Trace formula consists of 32 conjuncts, 2 conjunts are in the unsatisfiable core [2023-11-12 02:32:50,946 INFO L285 TraceCheckSpWp]: Computing forward predicates... [2023-11-12 02:32:50,981 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-12 02:32:50,982 WARN L260 TraceCheckSpWp]: Trace formula consists of 8 conjuncts, 5 conjunts are in the unsatisfiable core [2023-11-12 02:32:50,983 INFO L285 TraceCheckSpWp]: Computing forward predicates... [2023-11-12 02:32:51,011 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-12 02:32:51,012 INFO L141 lantAutomatonBouncer]: Defining deterministic Buchi interpolant automaton with honda bouncer for stem and without honda bouncer for loop.1 stem predicates 2 loop predicates [2023-11-12 02:32:51,013 INFO L71 iDifferenceNCSBLazy3]: Start buchiDifferenceNCSBLazy3. First operand 34 states and 40 transitions. cyclomatic complexity: 10 Second operand has 3 states, 3 states have (on average 3.3333333333333335) internal successors, (10), 3 states have internal predecessors, (10), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-12 02:32:51,042 INFO L75 iDifferenceNCSBLazy3]: Finished buchiDifferenceNCSBLazy3. First operand 34 states and 40 transitions. cyclomatic complexity: 10. Second operand has 3 states, 3 states have (on average 3.3333333333333335) internal successors, (10), 3 states have internal predecessors, (10), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Result 44 states and 51 transitions. Complement of second has 5 states. [2023-11-12 02:32:51,043 INFO L141 InterpolantAutomaton]: Switched to read-only mode: Buchi interpolant automaton has 3 states 1 stem states 1 non-accepting loop states 1 accepting loop states [2023-11-12 02:32:51,046 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 3 states, 3 states have (on average 3.3333333333333335) internal successors, (10), 3 states have internal predecessors, (10), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-12 02:32:51,046 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3 states to 3 states and 9 transitions. [2023-11-12 02:32:51,046 INFO L84 BuchiAccepts]: Start buchiAccepts Operand 3 states and 9 transitions. Stem has 14 letters. Loop has 3 letters. [2023-11-12 02:32:51,046 INFO L116 BuchiAccepts]: Finished buchiAccepts. [2023-11-12 02:32:51,046 INFO L681 stractBuchiCegarLoop]: Bad chosen interpolant automaton: word not accepted [2023-11-12 02:32:51,064 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-12 02:32:51,073 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-12 02:32:51,074 INFO L262 TraceCheckSpWp]: Trace formula consists of 32 conjuncts, 2 conjunts are in the unsatisfiable core [2023-11-12 02:32:51,075 INFO L285 TraceCheckSpWp]: Computing forward predicates... [2023-11-12 02:32:51,106 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-12 02:32:51,107 WARN L260 TraceCheckSpWp]: Trace formula consists of 8 conjuncts, 5 conjunts are in the unsatisfiable core [2023-11-12 02:32:51,107 INFO L285 TraceCheckSpWp]: Computing forward predicates... [2023-11-12 02:32:51,131 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-12 02:32:51,132 INFO L141 lantAutomatonBouncer]: Defining deterministic Buchi interpolant automaton with honda bouncer for stem and with honda bouncer for loop.1 stem predicates 2 loop predicates [2023-11-12 02:32:51,132 INFO L71 iDifferenceNCSBLazy3]: Start buchiDifferenceNCSBLazy3. First operand 34 states and 40 transitions. cyclomatic complexity: 10 Second operand has 3 states, 3 states have (on average 3.3333333333333335) internal successors, (10), 3 states have internal predecessors, (10), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-12 02:32:51,160 INFO L75 iDifferenceNCSBLazy3]: Finished buchiDifferenceNCSBLazy3. First operand 34 states and 40 transitions. cyclomatic complexity: 10. Second operand has 3 states, 3 states have (on average 3.3333333333333335) internal successors, (10), 3 states have internal predecessors, (10), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Result 44 states and 51 transitions. Complement of second has 5 states. [2023-11-12 02:32:51,161 INFO L141 InterpolantAutomaton]: Switched to read-only mode: Buchi interpolant automaton has 3 states 1 stem states 1 non-accepting loop states 1 accepting loop states [2023-11-12 02:32:51,164 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 3 states, 3 states have (on average 3.3333333333333335) internal successors, (10), 3 states have internal predecessors, (10), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-12 02:32:51,164 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3 states to 3 states and 9 transitions. [2023-11-12 02:32:51,164 INFO L84 BuchiAccepts]: Start buchiAccepts Operand 3 states and 9 transitions. Stem has 14 letters. Loop has 3 letters. [2023-11-12 02:32:51,165 INFO L116 BuchiAccepts]: Finished buchiAccepts. [2023-11-12 02:32:51,165 INFO L681 stractBuchiCegarLoop]: Bad chosen interpolant automaton: word not accepted [2023-11-12 02:32:51,177 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-12 02:32:51,187 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-12 02:32:51,187 INFO L262 TraceCheckSpWp]: Trace formula consists of 32 conjuncts, 2 conjunts are in the unsatisfiable core [2023-11-12 02:32:51,188 INFO L285 TraceCheckSpWp]: Computing forward predicates... [2023-11-12 02:32:51,225 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-12 02:32:51,226 WARN L260 TraceCheckSpWp]: Trace formula consists of 8 conjuncts, 5 conjunts are in the unsatisfiable core [2023-11-12 02:32:51,226 INFO L285 TraceCheckSpWp]: Computing forward predicates... [2023-11-12 02:32:51,256 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-12 02:32:51,257 INFO L141 lantAutomatonBouncer]: Defining Buchi interpolant automaton with scrooge nondeterminism in stemwith honda bouncer for stem and without honda bouncer for loop.1 stem predicates 2 loop predicates [2023-11-12 02:32:51,257 INFO L71 iDifferenceNCSBLazy3]: Start buchiDifferenceNCSBLazy3. First operand 34 states and 40 transitions. cyclomatic complexity: 10 Second operand has 3 states, 3 states have (on average 3.3333333333333335) internal successors, (10), 3 states have internal predecessors, (10), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-12 02:32:51,283 INFO L75 iDifferenceNCSBLazy3]: Finished buchiDifferenceNCSBLazy3. First operand 34 states and 40 transitions. cyclomatic complexity: 10. Second operand has 3 states, 3 states have (on average 3.3333333333333335) internal successors, (10), 3 states have internal predecessors, (10), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Result 57 states and 69 transitions. Complement of second has 4 states. [2023-11-12 02:32:51,283 INFO L141 InterpolantAutomaton]: Switched to read-only mode: Buchi interpolant automaton has 3 states 1 stem states 1 non-accepting loop states 1 accepting loop states [2023-11-12 02:32:51,284 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 3 states, 3 states have (on average 3.3333333333333335) internal successors, (10), 3 states have internal predecessors, (10), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-12 02:32:51,284 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3 states to 3 states and 13 transitions. [2023-11-12 02:32:51,284 INFO L84 BuchiAccepts]: Start buchiAccepts Operand 3 states and 13 transitions. Stem has 14 letters. Loop has 3 letters. [2023-11-12 02:32:51,285 INFO L116 BuchiAccepts]: Finished buchiAccepts. [2023-11-12 02:32:51,285 INFO L84 BuchiAccepts]: Start buchiAccepts Operand 3 states and 13 transitions. Stem has 17 letters. Loop has 3 letters. [2023-11-12 02:32:51,285 INFO L116 BuchiAccepts]: Finished buchiAccepts. [2023-11-12 02:32:51,285 INFO L84 BuchiAccepts]: Start buchiAccepts Operand 3 states and 13 transitions. Stem has 14 letters. Loop has 6 letters. [2023-11-12 02:32:51,286 INFO L116 BuchiAccepts]: Finished buchiAccepts. [2023-11-12 02:32:51,286 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 57 states and 69 transitions. [2023-11-12 02:32:51,288 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 12 [2023-11-12 02:32:51,289 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 57 states to 47 states and 58 transitions. [2023-11-12 02:32:51,289 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 27 [2023-11-12 02:32:51,289 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 30 [2023-11-12 02:32:51,289 INFO L73 IsDeterministic]: Start isDeterministic. Operand 47 states and 58 transitions. [2023-11-12 02:32:51,289 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2023-11-12 02:32:51,290 INFO L218 hiAutomatonCegarLoop]: Abstraction has 47 states and 58 transitions. [2023-11-12 02:32:51,290 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 47 states and 58 transitions. [2023-11-12 02:32:51,292 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 47 to 31. [2023-11-12 02:32:51,293 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 31 states, 31 states have (on average 1.2903225806451613) internal successors, (40), 30 states have internal predecessors, (40), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-12 02:32:51,293 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 31 states to 31 states and 40 transitions. [2023-11-12 02:32:51,294 INFO L240 hiAutomatonCegarLoop]: Abstraction has 31 states and 40 transitions. [2023-11-12 02:32:51,294 INFO L428 stractBuchiCegarLoop]: Abstraction has 31 states and 40 transitions. [2023-11-12 02:32:51,294 INFO L335 stractBuchiCegarLoop]: ======== Iteration 6 ============ [2023-11-12 02:32:51,294 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 31 states and 40 transitions. [2023-11-12 02:32:51,295 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 11 [2023-11-12 02:32:51,295 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-12 02:32:51,295 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-12 02:32:51,296 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [5, 5, 3, 2, 1, 1] [2023-11-12 02:32:51,296 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [2, 2, 1, 1] [2023-11-12 02:32:51,296 INFO L748 eck$LassoCheckResult]: Stem: 671#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true; 672#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet0#1, main_~i~0#1, main_~range~0#1;havoc main_~i~0#1;havoc main_~range~0#1;havoc main_#t~nondet0#1;main_~i~0#1 := main_#t~nondet0#1;havoc main_#t~nondet0#1;main_~range~0#1 := 20; 673#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 665#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 692#L13 assume main_~i~0#1 == main_~range~0#1;main_~i~0#1 := 0;main_~range~0#1 := main_~range~0#1 - 1; 662#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 663#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 667#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 668#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 674#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 669#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 670#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 690#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 684#L13 assume main_~i~0#1 == main_~range~0#1;main_~i~0#1 := 0;main_~range~0#1 := main_~range~0#1 - 1; 683#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 682#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 680#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 678#L12-1 [2023-11-12 02:32:51,296 INFO L750 eck$LassoCheckResult]: Loop: 678#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 679#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 688#L13 assume main_~i~0#1 == main_~range~0#1;main_~i~0#1 := 0;main_~range~0#1 := main_~range~0#1 - 1; 686#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 687#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 685#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 678#L12-1 [2023-11-12 02:32:51,297 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-12 02:32:51,297 INFO L85 PathProgramCache]: Analyzing trace with hash 1031341869, now seen corresponding path program 5 times [2023-11-12 02:32:51,297 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-12 02:32:51,297 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1317834399] [2023-11-12 02:32:51,298 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-12 02:32:51,298 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-12 02:32:51,307 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-12 02:32:51,409 INFO L134 CoverageAnalysis]: Checked inductivity of 30 backedges. 12 proven. 18 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-12 02:32:51,409 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-12 02:32:51,410 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1317834399] [2023-11-12 02:32:51,410 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1317834399] provided 0 perfect and 1 imperfect interpolant sequences [2023-11-12 02:32:51,410 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1415761767] [2023-11-12 02:32:51,410 INFO L93 rtionOrderModulation]: Changing assertion order to INSIDE_LOOP_FIRST1 [2023-11-12 02:32:51,410 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2023-11-12 02:32:51,411 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1deda2bf-224c-4242-8866-e899ae47e0d0/bin/uautomizer-verify-uTZkv6EMXl/z3 [2023-11-12 02:32:51,412 INFO L229 MonitoredProcess]: Starting monitored process 23 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1deda2bf-224c-4242-8866-e899ae47e0d0/bin/uautomizer-verify-uTZkv6EMXl/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2023-11-12 02:32:51,418 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1deda2bf-224c-4242-8866-e899ae47e0d0/bin/uautomizer-verify-uTZkv6EMXl/z3 -smt2 -in SMTLIB2_COMPLIANT=true (23)] Waiting until timeout for monitored process [2023-11-12 02:32:51,461 INFO L228 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 5 check-sat command(s) [2023-11-12 02:32:51,461 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2023-11-12 02:32:51,462 INFO L262 TraceCheckSpWp]: Trace formula consists of 41 conjuncts, 6 conjunts are in the unsatisfiable core [2023-11-12 02:32:51,463 INFO L285 TraceCheckSpWp]: Computing forward predicates... [2023-11-12 02:32:51,555 INFO L134 CoverageAnalysis]: Checked inductivity of 30 backedges. 12 proven. 18 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-12 02:32:51,555 INFO L327 TraceCheckSpWp]: Computing backward predicates... [2023-11-12 02:32:51,626 INFO L134 CoverageAnalysis]: Checked inductivity of 30 backedges. 12 proven. 18 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-12 02:32:51,626 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1415761767] provided 0 perfect and 2 imperfect interpolant sequences [2023-11-12 02:32:51,626 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2023-11-12 02:32:51,626 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [6, 6, 6] total 13 [2023-11-12 02:32:51,629 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1103738546] [2023-11-12 02:32:51,630 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2023-11-12 02:32:51,631 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-12 02:32:51,631 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-12 02:32:51,632 INFO L85 PathProgramCache]: Analyzing trace with hash 1215871107, now seen corresponding path program 1 times [2023-11-12 02:32:51,632 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-12 02:32:51,632 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1845232833] [2023-11-12 02:32:51,633 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-12 02:32:51,633 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-12 02:32:51,643 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-12 02:32:51,643 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-12 02:32:51,655 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-12 02:32:51,657 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-12 02:32:51,713 INFO L210 LassoAnalysis]: Preferences: [2023-11-12 02:32:51,713 INFO L126 ssoRankerPreferences]: Compute integeral hull: false [2023-11-12 02:32:51,713 INFO L127 ssoRankerPreferences]: Enable LassoPartitioneer: true [2023-11-12 02:32:51,713 INFO L128 ssoRankerPreferences]: Term annotations enabled: false [2023-11-12 02:32:51,713 INFO L129 ssoRankerPreferences]: Use exernal solver: true [2023-11-12 02:32:51,713 INFO L130 ssoRankerPreferences]: SMT solver command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2023-11-12 02:32:51,713 INFO L131 ssoRankerPreferences]: Dump SMT script to file: false [2023-11-12 02:32:51,714 INFO L132 ssoRankerPreferences]: Path of dumped script: [2023-11-12 02:32:51,714 INFO L133 ssoRankerPreferences]: Filename of dumped script: NarrowKonv.c_Iteration6_Loop [2023-11-12 02:32:51,714 INFO L134 ssoRankerPreferences]: MapElimAlgo: Frank [2023-11-12 02:32:51,714 INFO L276 LassoAnalysis]: Starting lasso preprocessing... [2023-11-12 02:32:51,716 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-12 02:32:51,726 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-12 02:32:51,728 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-12 02:32:51,808 INFO L294 LassoAnalysis]: Preprocessing complete. [2023-11-12 02:32:51,808 INFO L404 LassoAnalysis]: Checking for nontermination... [2023-11-12 02:32:51,808 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2023-11-12 02:32:51,808 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1deda2bf-224c-4242-8866-e899ae47e0d0/bin/uautomizer-verify-uTZkv6EMXl/z3 [2023-11-12 02:32:51,810 INFO L229 MonitoredProcess]: Starting monitored process 24 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1deda2bf-224c-4242-8866-e899ae47e0d0/bin/uautomizer-verify-uTZkv6EMXl/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2023-11-12 02:32:51,819 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2023-11-12 02:32:51,819 INFO L160 nArgumentSynthesizer]: Using integer mode. [2023-11-12 02:32:51,827 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1deda2bf-224c-4242-8866-e899ae47e0d0/bin/uautomizer-verify-uTZkv6EMXl/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (24)] Waiting until timeout for monitored process [2023-11-12 02:32:51,858 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1deda2bf-224c-4242-8866-e899ae47e0d0/bin/uautomizer-verify-uTZkv6EMXl/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (24)] Forceful destruction successful, exit code 0 [2023-11-12 02:32:51,859 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2023-11-12 02:32:51,859 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1deda2bf-224c-4242-8866-e899ae47e0d0/bin/uautomizer-verify-uTZkv6EMXl/z3 [2023-11-12 02:32:51,860 INFO L229 MonitoredProcess]: Starting monitored process 25 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1deda2bf-224c-4242-8866-e899ae47e0d0/bin/uautomizer-verify-uTZkv6EMXl/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2023-11-12 02:32:51,866 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 3 Nilpotent components: true [2023-11-12 02:32:51,866 INFO L160 nArgumentSynthesizer]: Using integer mode. [2023-11-12 02:32:51,881 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1deda2bf-224c-4242-8866-e899ae47e0d0/bin/uautomizer-verify-uTZkv6EMXl/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (25)] Waiting until timeout for monitored process [2023-11-12 02:32:52,000 INFO L444 LassoAnalysis]: Proving nontermination failed: No geometric nontermination argument exists. [2023-11-12 02:32:52,010 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1deda2bf-224c-4242-8866-e899ae47e0d0/bin/uautomizer-verify-uTZkv6EMXl/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (25)] Forceful destruction successful, exit code 0 [2023-11-12 02:32:52,010 INFO L210 LassoAnalysis]: Preferences: [2023-11-12 02:32:52,010 INFO L126 ssoRankerPreferences]: Compute integeral hull: false [2023-11-12 02:32:52,010 INFO L127 ssoRankerPreferences]: Enable LassoPartitioneer: true [2023-11-12 02:32:52,010 INFO L128 ssoRankerPreferences]: Term annotations enabled: false [2023-11-12 02:32:52,010 INFO L129 ssoRankerPreferences]: Use exernal solver: false [2023-11-12 02:32:52,010 INFO L130 ssoRankerPreferences]: SMT solver command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2023-11-12 02:32:52,010 INFO L131 ssoRankerPreferences]: Dump SMT script to file: false [2023-11-12 02:32:52,010 INFO L132 ssoRankerPreferences]: Path of dumped script: [2023-11-12 02:32:52,010 INFO L133 ssoRankerPreferences]: Filename of dumped script: NarrowKonv.c_Iteration6_Loop [2023-11-12 02:32:52,011 INFO L134 ssoRankerPreferences]: MapElimAlgo: Frank [2023-11-12 02:32:52,011 INFO L276 LassoAnalysis]: Starting lasso preprocessing... [2023-11-12 02:32:52,012 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-12 02:32:52,024 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-12 02:32:52,027 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-12 02:32:52,106 INFO L294 LassoAnalysis]: Preprocessing complete. [2023-11-12 02:32:52,107 INFO L490 LassoAnalysis]: Using template 'affine'. [2023-11-12 02:32:52,107 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2023-11-12 02:32:52,107 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1deda2bf-224c-4242-8866-e899ae47e0d0/bin/uautomizer-verify-uTZkv6EMXl/z3 [2023-11-12 02:32:52,110 INFO L229 MonitoredProcess]: Starting monitored process 26 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1deda2bf-224c-4242-8866-e899ae47e0d0/bin/uautomizer-verify-uTZkv6EMXl/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2023-11-12 02:32:52,118 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2023-11-12 02:32:52,131 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2023-11-12 02:32:52,131 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2023-11-12 02:32:52,131 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2023-11-12 02:32:52,131 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2023-11-12 02:32:52,131 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2023-11-12 02:32:52,133 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2023-11-12 02:32:52,133 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2023-11-12 02:32:52,134 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1deda2bf-224c-4242-8866-e899ae47e0d0/bin/uautomizer-verify-uTZkv6EMXl/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (26)] Waiting until timeout for monitored process [2023-11-12 02:32:52,157 INFO L420 nArgumentSynthesizer]: Found a termination argument, trying to simplify. [2023-11-12 02:32:52,161 INFO L443 ModelExtractionUtils]: Simplification made 3 calls to the SMT solver. [2023-11-12 02:32:52,162 INFO L444 ModelExtractionUtils]: 1 out of 4 variables were initially zero. Simplification set additionally 1 variables to zero. [2023-11-12 02:32:52,162 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2023-11-12 02:32:52,162 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1deda2bf-224c-4242-8866-e899ae47e0d0/bin/uautomizer-verify-uTZkv6EMXl/z3 [2023-11-12 02:32:52,165 INFO L229 MonitoredProcess]: Starting monitored process 27 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1deda2bf-224c-4242-8866-e899ae47e0d0/bin/uautomizer-verify-uTZkv6EMXl/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2023-11-12 02:32:52,167 INFO L435 nArgumentSynthesizer]: Simplifying supporting invariants... [2023-11-12 02:32:52,167 INFO L438 nArgumentSynthesizer]: Removed 0 redundant supporting invariants from a total of 0. [2023-11-12 02:32:52,167 INFO L513 LassoAnalysis]: Proved termination. [2023-11-12 02:32:52,168 INFO L515 LassoAnalysis]: Termination argument consisting of: Ranking function f(ULTIMATE.start_main_~i~0#1) = 1*ULTIMATE.start_main_~i~0#1 Supporting invariants [] [2023-11-12 02:32:52,170 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1deda2bf-224c-4242-8866-e899ae47e0d0/bin/uautomizer-verify-uTZkv6EMXl/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (27)] Waiting until timeout for monitored process [2023-11-12 02:32:52,176 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1deda2bf-224c-4242-8866-e899ae47e0d0/bin/uautomizer-verify-uTZkv6EMXl/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (26)] Forceful destruction successful, exit code 0 [2023-11-12 02:32:52,177 INFO L156 tatePredicateManager]: 0 out of 0 supporting invariants were superfluous and have been removed [2023-11-12 02:32:52,190 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-12 02:32:52,201 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-12 02:32:52,202 INFO L262 TraceCheckSpWp]: Trace formula consists of 41 conjuncts, 2 conjunts are in the unsatisfiable core [2023-11-12 02:32:52,203 INFO L285 TraceCheckSpWp]: Computing forward predicates... [2023-11-12 02:32:52,234 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-12 02:32:52,251 INFO L262 TraceCheckSpWp]: Trace formula consists of 17 conjuncts, 8 conjunts are in the unsatisfiable core [2023-11-12 02:32:52,252 INFO L285 TraceCheckSpWp]: Computing forward predicates... [2023-11-12 02:32:52,292 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1deda2bf-224c-4242-8866-e899ae47e0d0/bin/uautomizer-verify-uTZkv6EMXl/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (22)] Forceful destruction successful, exit code 0 [2023-11-12 02:32:52,299 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1deda2bf-224c-4242-8866-e899ae47e0d0/bin/uautomizer-verify-uTZkv6EMXl/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (27)] Forceful destruction successful, exit code 0 [2023-11-12 02:32:52,304 INFO L134 CoverageAnalysis]: Checked inductivity of 3 backedges. 2 proven. 1 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-12 02:32:52,304 INFO L141 lantAutomatonBouncer]: Defining deterministic Buchi interpolant automaton with honda bouncer for stem and without honda bouncer for loop.1 stem predicates 3 loop predicates [2023-11-12 02:32:52,305 INFO L71 iDifferenceNCSBLazy3]: Start buchiDifferenceNCSBLazy3. First operand 31 states and 40 transitions. cyclomatic complexity: 12 Second operand has 5 states, 5 states have (on average 2.6) internal successors, (13), 5 states have internal predecessors, (13), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-12 02:32:52,332 INFO L75 iDifferenceNCSBLazy3]: Finished buchiDifferenceNCSBLazy3. First operand 31 states and 40 transitions. cyclomatic complexity: 12. Second operand has 5 states, 5 states have (on average 2.6) internal successors, (13), 5 states have internal predecessors, (13), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Result 57 states and 67 transitions. Complement of second has 7 states. [2023-11-12 02:32:52,333 INFO L141 InterpolantAutomaton]: Switched to read-only mode: Buchi interpolant automaton has 4 states 1 stem states 2 non-accepting loop states 1 accepting loop states [2023-11-12 02:32:52,333 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 5 states, 5 states have (on average 2.6) internal successors, (13), 5 states have internal predecessors, (13), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-12 02:32:52,334 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 4 states to 4 states and 11 transitions. [2023-11-12 02:32:52,334 INFO L84 BuchiAccepts]: Start buchiAccepts Operand 4 states and 11 transitions. Stem has 17 letters. Loop has 6 letters. [2023-11-12 02:32:52,334 INFO L116 BuchiAccepts]: Finished buchiAccepts. [2023-11-12 02:32:52,334 INFO L681 stractBuchiCegarLoop]: Bad chosen interpolant automaton: word not accepted [2023-11-12 02:32:52,346 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-12 02:32:52,363 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-12 02:32:52,364 INFO L262 TraceCheckSpWp]: Trace formula consists of 41 conjuncts, 2 conjunts are in the unsatisfiable core [2023-11-12 02:32:52,365 INFO L285 TraceCheckSpWp]: Computing forward predicates... [2023-11-12 02:32:52,403 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-12 02:32:52,403 INFO L262 TraceCheckSpWp]: Trace formula consists of 17 conjuncts, 8 conjunts are in the unsatisfiable core [2023-11-12 02:32:52,404 INFO L285 TraceCheckSpWp]: Computing forward predicates... [2023-11-12 02:32:52,454 INFO L134 CoverageAnalysis]: Checked inductivity of 3 backedges. 2 proven. 1 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-12 02:32:52,454 INFO L141 lantAutomatonBouncer]: Defining deterministic Buchi interpolant automaton with honda bouncer for stem and with honda bouncer for loop.1 stem predicates 3 loop predicates [2023-11-12 02:32:52,454 INFO L71 iDifferenceNCSBLazy3]: Start buchiDifferenceNCSBLazy3. First operand 31 states and 40 transitions. cyclomatic complexity: 12 Second operand has 5 states, 5 states have (on average 2.6) internal successors, (13), 5 states have internal predecessors, (13), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-12 02:32:52,488 INFO L75 iDifferenceNCSBLazy3]: Finished buchiDifferenceNCSBLazy3. First operand 31 states and 40 transitions. cyclomatic complexity: 12. Second operand has 5 states, 5 states have (on average 2.6) internal successors, (13), 5 states have internal predecessors, (13), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Result 59 states and 70 transitions. Complement of second has 9 states. [2023-11-12 02:32:52,489 INFO L141 InterpolantAutomaton]: Switched to read-only mode: Buchi interpolant automaton has 5 states 1 stem states 3 non-accepting loop states 1 accepting loop states [2023-11-12 02:32:52,490 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 5 states, 5 states have (on average 2.6) internal successors, (13), 5 states have internal predecessors, (13), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-12 02:32:52,490 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 5 states to 5 states and 12 transitions. [2023-11-12 02:32:52,490 INFO L84 BuchiAccepts]: Start buchiAccepts Operand 5 states and 12 transitions. Stem has 17 letters. Loop has 6 letters. [2023-11-12 02:32:52,490 INFO L116 BuchiAccepts]: Finished buchiAccepts. [2023-11-12 02:32:52,490 INFO L681 stractBuchiCegarLoop]: Bad chosen interpolant automaton: word not accepted [2023-11-12 02:32:52,502 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-12 02:32:52,512 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-12 02:32:52,513 INFO L262 TraceCheckSpWp]: Trace formula consists of 41 conjuncts, 2 conjunts are in the unsatisfiable core [2023-11-12 02:32:52,513 INFO L285 TraceCheckSpWp]: Computing forward predicates... [2023-11-12 02:32:52,540 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-12 02:32:52,541 INFO L262 TraceCheckSpWp]: Trace formula consists of 17 conjuncts, 8 conjunts are in the unsatisfiable core [2023-11-12 02:32:52,541 INFO L285 TraceCheckSpWp]: Computing forward predicates... [2023-11-12 02:32:52,586 INFO L134 CoverageAnalysis]: Checked inductivity of 3 backedges. 2 proven. 1 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-12 02:32:52,586 INFO L141 lantAutomatonBouncer]: Defining Buchi interpolant automaton with scrooge nondeterminism in stemwith honda bouncer for stem and without honda bouncer for loop.1 stem predicates 3 loop predicates [2023-11-12 02:32:52,586 INFO L71 iDifferenceNCSBLazy3]: Start buchiDifferenceNCSBLazy3. First operand 31 states and 40 transitions. cyclomatic complexity: 12 Second operand has 5 states, 5 states have (on average 2.6) internal successors, (13), 5 states have internal predecessors, (13), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-12 02:32:52,611 INFO L75 iDifferenceNCSBLazy3]: Finished buchiDifferenceNCSBLazy3. First operand 31 states and 40 transitions. cyclomatic complexity: 12. Second operand has 5 states, 5 states have (on average 2.6) internal successors, (13), 5 states have internal predecessors, (13), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Result 73 states and 94 transitions. Complement of second has 6 states. [2023-11-12 02:32:52,612 INFO L141 InterpolantAutomaton]: Switched to read-only mode: Buchi interpolant automaton has 4 states 1 stem states 2 non-accepting loop states 1 accepting loop states [2023-11-12 02:32:52,612 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 5 states, 5 states have (on average 2.6) internal successors, (13), 5 states have internal predecessors, (13), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-12 02:32:52,613 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 4 states to 4 states and 16 transitions. [2023-11-12 02:32:52,613 INFO L84 BuchiAccepts]: Start buchiAccepts Operand 4 states and 16 transitions. Stem has 17 letters. Loop has 6 letters. [2023-11-12 02:32:52,613 INFO L116 BuchiAccepts]: Finished buchiAccepts. [2023-11-12 02:32:52,613 INFO L681 stractBuchiCegarLoop]: Bad chosen interpolant automaton: word not accepted [2023-11-12 02:32:52,625 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-12 02:32:52,635 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-12 02:32:52,635 INFO L262 TraceCheckSpWp]: Trace formula consists of 41 conjuncts, 2 conjunts are in the unsatisfiable core [2023-11-12 02:32:52,636 INFO L285 TraceCheckSpWp]: Computing forward predicates... [2023-11-12 02:32:52,667 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-12 02:32:52,667 INFO L262 TraceCheckSpWp]: Trace formula consists of 17 conjuncts, 8 conjunts are in the unsatisfiable core [2023-11-12 02:32:52,668 INFO L285 TraceCheckSpWp]: Computing forward predicates... [2023-11-12 02:32:52,712 INFO L134 CoverageAnalysis]: Checked inductivity of 3 backedges. 2 proven. 1 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-12 02:32:52,712 INFO L141 lantAutomatonBouncer]: Defining Buchi interpolant automaton with scrooge nondeterminism in stemwith honda bouncer for stem and with honda bouncer for loop.1 stem predicates 3 loop predicates [2023-11-12 02:32:52,713 INFO L71 iDifferenceNCSBLazy3]: Start buchiDifferenceNCSBLazy3. First operand 31 states and 40 transitions. cyclomatic complexity: 12 Second operand has 5 states, 5 states have (on average 2.6) internal successors, (13), 5 states have internal predecessors, (13), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-12 02:32:52,761 INFO L75 iDifferenceNCSBLazy3]: Finished buchiDifferenceNCSBLazy3. First operand 31 states and 40 transitions. cyclomatic complexity: 12. Second operand has 5 states, 5 states have (on average 2.6) internal successors, (13), 5 states have internal predecessors, (13), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Result 75 states and 94 transitions. Complement of second has 10 states. [2023-11-12 02:32:52,761 INFO L141 InterpolantAutomaton]: Switched to read-only mode: Buchi interpolant automaton has 6 states 1 stem states 4 non-accepting loop states 1 accepting loop states [2023-11-12 02:32:52,762 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 5 states, 5 states have (on average 2.6) internal successors, (13), 5 states have internal predecessors, (13), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-12 02:32:52,762 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 6 states to 6 states and 20 transitions. [2023-11-12 02:32:52,762 INFO L84 BuchiAccepts]: Start buchiAccepts Operand 6 states and 20 transitions. Stem has 17 letters. Loop has 6 letters. [2023-11-12 02:32:52,762 INFO L116 BuchiAccepts]: Finished buchiAccepts. [2023-11-12 02:32:52,762 INFO L84 BuchiAccepts]: Start buchiAccepts Operand 6 states and 20 transitions. Stem has 23 letters. Loop has 6 letters. [2023-11-12 02:32:52,763 INFO L116 BuchiAccepts]: Finished buchiAccepts. [2023-11-12 02:32:52,763 INFO L84 BuchiAccepts]: Start buchiAccepts Operand 6 states and 20 transitions. Stem has 17 letters. Loop has 12 letters. [2023-11-12 02:32:52,763 INFO L116 BuchiAccepts]: Finished buchiAccepts. [2023-11-12 02:32:52,763 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 75 states and 94 transitions. [2023-11-12 02:32:52,766 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 21 [2023-11-12 02:32:52,766 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 75 states to 53 states and 69 transitions. [2023-11-12 02:32:52,767 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 20 [2023-11-12 02:32:52,767 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 21 [2023-11-12 02:32:52,767 INFO L73 IsDeterministic]: Start isDeterministic. Operand 53 states and 69 transitions. [2023-11-12 02:32:52,767 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2023-11-12 02:32:52,767 INFO L218 hiAutomatonCegarLoop]: Abstraction has 53 states and 69 transitions. [2023-11-12 02:32:52,767 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 53 states and 69 transitions. [2023-11-12 02:32:52,770 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 53 to 41. [2023-11-12 02:32:52,771 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 41 states, 41 states have (on average 1.3170731707317074) internal successors, (54), 40 states have internal predecessors, (54), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-12 02:32:52,771 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 41 states to 41 states and 54 transitions. [2023-11-12 02:32:52,771 INFO L240 hiAutomatonCegarLoop]: Abstraction has 41 states and 54 transitions. [2023-11-12 02:32:52,772 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-12 02:32:52,772 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 13 interpolants. [2023-11-12 02:32:52,772 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=60, Invalid=96, Unknown=0, NotChecked=0, Total=156 [2023-11-12 02:32:52,772 INFO L87 Difference]: Start difference. First operand 41 states and 54 transitions. Second operand has 13 states, 13 states have (on average 3.076923076923077) internal successors, (40), 13 states have internal predecessors, (40), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-12 02:32:52,870 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-12 02:32:52,871 INFO L93 Difference]: Finished difference Result 77 states and 90 transitions. [2023-11-12 02:32:52,871 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 77 states and 90 transitions. [2023-11-12 02:32:52,872 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 15 [2023-11-12 02:32:52,873 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 77 states to 61 states and 74 transitions. [2023-11-12 02:32:52,873 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 15 [2023-11-12 02:32:52,874 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 15 [2023-11-12 02:32:52,874 INFO L73 IsDeterministic]: Start isDeterministic. Operand 61 states and 74 transitions. [2023-11-12 02:32:52,874 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2023-11-12 02:32:52,874 INFO L218 hiAutomatonCegarLoop]: Abstraction has 61 states and 74 transitions. [2023-11-12 02:32:52,874 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 61 states and 74 transitions. [2023-11-12 02:32:52,877 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 61 to 58. [2023-11-12 02:32:52,877 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 58 states, 58 states have (on average 1.2241379310344827) internal successors, (71), 57 states have internal predecessors, (71), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-12 02:32:52,878 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 58 states to 58 states and 71 transitions. [2023-11-12 02:32:52,878 INFO L240 hiAutomatonCegarLoop]: Abstraction has 58 states and 71 transitions. [2023-11-12 02:32:52,879 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 13 states. [2023-11-12 02:32:52,879 INFO L428 stractBuchiCegarLoop]: Abstraction has 58 states and 71 transitions. [2023-11-12 02:32:52,879 INFO L335 stractBuchiCegarLoop]: ======== Iteration 7 ============ [2023-11-12 02:32:52,880 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 58 states and 71 transitions. [2023-11-12 02:32:52,880 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 15 [2023-11-12 02:32:52,881 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-12 02:32:52,881 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-12 02:32:52,882 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [12, 11, 9, 2, 1, 1] [2023-11-12 02:32:52,882 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [3, 3, 2, 1] [2023-11-12 02:32:52,882 INFO L748 eck$LassoCheckResult]: Stem: 1527#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true; 1528#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet0#1, main_~i~0#1, main_~range~0#1;havoc main_~i~0#1;havoc main_~range~0#1;havoc main_#t~nondet0#1;main_~i~0#1 := main_#t~nondet0#1;havoc main_#t~nondet0#1;main_~range~0#1 := 20; 1529#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 1550#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 1548#L13 assume main_~i~0#1 == main_~range~0#1;main_~i~0#1 := 0;main_~range~0#1 := main_~range~0#1 - 1; 1547#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 1545#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 1542#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 1521#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 1522#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 1577#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 1576#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 1575#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 1574#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 1573#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 1572#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 1571#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 1570#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 1569#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 1568#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 1567#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 1540#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 1554#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 1539#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 1541#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 1564#L13 assume main_~i~0#1 == main_~range~0#1;main_~i~0#1 := 0;main_~range~0#1 := main_~range~0#1 - 1; 1563#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 1562#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 1561#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 1560#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 1559#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 1557#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 1556#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 1555#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 1553#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 1537#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 1538#L12 [2023-11-12 02:32:52,882 INFO L750 eck$LassoCheckResult]: Loop: 1538#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 1549#L13 assume main_~i~0#1 == main_~range~0#1;main_~i~0#1 := 0;main_~range~0#1 := main_~range~0#1 - 1; 1544#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 1546#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 1543#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 1534#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 1535#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 1553#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 1537#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 1538#L12 [2023-11-12 02:32:52,883 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-12 02:32:52,883 INFO L85 PathProgramCache]: Analyzing trace with hash -566648130, now seen corresponding path program 6 times [2023-11-12 02:32:52,883 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-12 02:32:52,883 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [292688348] [2023-11-12 02:32:52,883 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-12 02:32:52,883 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-12 02:32:52,896 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-12 02:32:53,070 INFO L134 CoverageAnalysis]: Checked inductivity of 176 backedges. 80 proven. 84 refuted. 0 times theorem prover too weak. 12 trivial. 0 not checked. [2023-11-12 02:32:53,070 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-12 02:32:53,070 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [292688348] [2023-11-12 02:32:53,070 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [292688348] provided 0 perfect and 1 imperfect interpolant sequences [2023-11-12 02:32:53,070 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [2001731420] [2023-11-12 02:32:53,070 INFO L93 rtionOrderModulation]: Changing assertion order to MIX_INSIDE_OUTSIDE [2023-11-12 02:32:53,070 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2023-11-12 02:32:53,071 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1deda2bf-224c-4242-8866-e899ae47e0d0/bin/uautomizer-verify-uTZkv6EMXl/z3 [2023-11-12 02:32:53,072 INFO L229 MonitoredProcess]: Starting monitored process 28 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1deda2bf-224c-4242-8866-e899ae47e0d0/bin/uautomizer-verify-uTZkv6EMXl/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2023-11-12 02:32:53,093 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1deda2bf-224c-4242-8866-e899ae47e0d0/bin/uautomizer-verify-uTZkv6EMXl/z3 -smt2 -in SMTLIB2_COMPLIANT=true (28)] Waiting until timeout for monitored process [2023-11-12 02:32:53,124 INFO L228 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued 12 check-sat command(s) [2023-11-12 02:32:53,124 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2023-11-12 02:32:53,125 INFO L262 TraceCheckSpWp]: Trace formula consists of 79 conjuncts, 10 conjunts are in the unsatisfiable core [2023-11-12 02:32:53,127 INFO L285 TraceCheckSpWp]: Computing forward predicates... [2023-11-12 02:32:53,297 INFO L134 CoverageAnalysis]: Checked inductivity of 176 backedges. 80 proven. 84 refuted. 0 times theorem prover too weak. 12 trivial. 0 not checked. [2023-11-12 02:32:53,297 INFO L327 TraceCheckSpWp]: Computing backward predicates... [2023-11-12 02:32:53,477 INFO L134 CoverageAnalysis]: Checked inductivity of 176 backedges. 80 proven. 84 refuted. 0 times theorem prover too weak. 12 trivial. 0 not checked. [2023-11-12 02:32:53,477 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [2001731420] provided 0 perfect and 2 imperfect interpolant sequences [2023-11-12 02:32:53,478 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2023-11-12 02:32:53,478 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [10, 10, 10] total 25 [2023-11-12 02:32:53,478 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1146346431] [2023-11-12 02:32:53,478 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2023-11-12 02:32:53,479 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-12 02:32:53,479 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-12 02:32:53,479 INFO L85 PathProgramCache]: Analyzing trace with hash 1423235079, now seen corresponding path program 2 times [2023-11-12 02:32:53,479 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-12 02:32:53,480 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [332467405] [2023-11-12 02:32:53,480 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-12 02:32:53,480 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-12 02:32:53,484 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-12 02:32:53,485 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-12 02:32:53,487 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-12 02:32:53,489 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-12 02:32:53,568 INFO L210 LassoAnalysis]: Preferences: [2023-11-12 02:32:53,568 INFO L126 ssoRankerPreferences]: Compute integeral hull: false [2023-11-12 02:32:53,568 INFO L127 ssoRankerPreferences]: Enable LassoPartitioneer: true [2023-11-12 02:32:53,568 INFO L128 ssoRankerPreferences]: Term annotations enabled: false [2023-11-12 02:32:53,568 INFO L129 ssoRankerPreferences]: Use exernal solver: true [2023-11-12 02:32:53,569 INFO L130 ssoRankerPreferences]: SMT solver command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2023-11-12 02:32:53,569 INFO L131 ssoRankerPreferences]: Dump SMT script to file: false [2023-11-12 02:32:53,569 INFO L132 ssoRankerPreferences]: Path of dumped script: [2023-11-12 02:32:53,569 INFO L133 ssoRankerPreferences]: Filename of dumped script: NarrowKonv.c_Iteration7_Loop [2023-11-12 02:32:53,569 INFO L134 ssoRankerPreferences]: MapElimAlgo: Frank [2023-11-12 02:32:53,569 INFO L276 LassoAnalysis]: Starting lasso preprocessing... [2023-11-12 02:32:53,570 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-12 02:32:53,573 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-12 02:32:53,576 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-12 02:32:53,643 INFO L294 LassoAnalysis]: Preprocessing complete. [2023-11-12 02:32:53,644 INFO L404 LassoAnalysis]: Checking for nontermination... [2023-11-12 02:32:53,644 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2023-11-12 02:32:53,644 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1deda2bf-224c-4242-8866-e899ae47e0d0/bin/uautomizer-verify-uTZkv6EMXl/z3 [2023-11-12 02:32:53,645 INFO L229 MonitoredProcess]: Starting monitored process 29 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1deda2bf-224c-4242-8866-e899ae47e0d0/bin/uautomizer-verify-uTZkv6EMXl/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2023-11-12 02:32:53,654 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2023-11-12 02:32:53,654 INFO L160 nArgumentSynthesizer]: Using integer mode. [2023-11-12 02:32:53,667 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1deda2bf-224c-4242-8866-e899ae47e0d0/bin/uautomizer-verify-uTZkv6EMXl/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (29)] Waiting until timeout for monitored process [2023-11-12 02:32:53,682 INFO L437 LassoAnalysis]: Proved nontermination for one component. [2023-11-12 02:32:53,682 INFO L440 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {v_rep~unnamed0~0~true_9=1} Honda state: {v_rep~unnamed0~0~true_9=1} Generalized eigenvectors: [] Lambdas: [] Nus: [] [2023-11-12 02:32:53,686 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1deda2bf-224c-4242-8866-e899ae47e0d0/bin/uautomizer-verify-uTZkv6EMXl/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (29)] Forceful destruction successful, exit code 0 [2023-11-12 02:32:53,686 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2023-11-12 02:32:53,686 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1deda2bf-224c-4242-8866-e899ae47e0d0/bin/uautomizer-verify-uTZkv6EMXl/z3 [2023-11-12 02:32:53,687 INFO L229 MonitoredProcess]: Starting monitored process 30 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1deda2bf-224c-4242-8866-e899ae47e0d0/bin/uautomizer-verify-uTZkv6EMXl/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2023-11-12 02:32:53,690 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1deda2bf-224c-4242-8866-e899ae47e0d0/bin/uautomizer-verify-uTZkv6EMXl/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (30)] Waiting until timeout for monitored process [2023-11-12 02:32:53,690 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2023-11-12 02:32:53,690 INFO L160 nArgumentSynthesizer]: Using integer mode. [2023-11-12 02:32:53,707 INFO L437 LassoAnalysis]: Proved nontermination for one component. [2023-11-12 02:32:53,707 INFO L440 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {v_rep~unnamed0~0~false_9=0} Honda state: {v_rep~unnamed0~0~false_9=0} Generalized eigenvectors: [] Lambdas: [] Nus: [] [2023-11-12 02:32:53,710 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1deda2bf-224c-4242-8866-e899ae47e0d0/bin/uautomizer-verify-uTZkv6EMXl/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (30)] Ended with exit code 0 [2023-11-12 02:32:53,710 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2023-11-12 02:32:53,710 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1deda2bf-224c-4242-8866-e899ae47e0d0/bin/uautomizer-verify-uTZkv6EMXl/z3 [2023-11-12 02:32:53,711 INFO L229 MonitoredProcess]: Starting monitored process 31 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1deda2bf-224c-4242-8866-e899ae47e0d0/bin/uautomizer-verify-uTZkv6EMXl/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2023-11-12 02:32:53,713 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1deda2bf-224c-4242-8866-e899ae47e0d0/bin/uautomizer-verify-uTZkv6EMXl/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (31)] Waiting until timeout for monitored process [2023-11-12 02:32:53,714 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2023-11-12 02:32:53,714 INFO L160 nArgumentSynthesizer]: Using integer mode. [2023-11-12 02:32:53,741 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1deda2bf-224c-4242-8866-e899ae47e0d0/bin/uautomizer-verify-uTZkv6EMXl/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (31)] Forceful destruction successful, exit code 0 [2023-11-12 02:32:53,742 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2023-11-12 02:32:53,742 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1deda2bf-224c-4242-8866-e899ae47e0d0/bin/uautomizer-verify-uTZkv6EMXl/z3 [2023-11-12 02:32:53,743 INFO L229 MonitoredProcess]: Starting monitored process 32 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1deda2bf-224c-4242-8866-e899ae47e0d0/bin/uautomizer-verify-uTZkv6EMXl/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2023-11-12 02:32:53,746 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1deda2bf-224c-4242-8866-e899ae47e0d0/bin/uautomizer-verify-uTZkv6EMXl/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (32)] Waiting until timeout for monitored process [2023-11-12 02:32:53,746 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 3 Nilpotent components: true [2023-11-12 02:32:53,747 INFO L160 nArgumentSynthesizer]: Using integer mode. [2023-11-12 02:32:53,874 INFO L444 LassoAnalysis]: Proving nontermination failed: No geometric nontermination argument exists. [2023-11-12 02:32:53,877 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1deda2bf-224c-4242-8866-e899ae47e0d0/bin/uautomizer-verify-uTZkv6EMXl/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (32)] Ended with exit code 0 [2023-11-12 02:32:53,877 INFO L210 LassoAnalysis]: Preferences: [2023-11-12 02:32:53,877 INFO L126 ssoRankerPreferences]: Compute integeral hull: false [2023-11-12 02:32:53,878 INFO L127 ssoRankerPreferences]: Enable LassoPartitioneer: true [2023-11-12 02:32:53,878 INFO L128 ssoRankerPreferences]: Term annotations enabled: false [2023-11-12 02:32:53,878 INFO L129 ssoRankerPreferences]: Use exernal solver: false [2023-11-12 02:32:53,878 INFO L130 ssoRankerPreferences]: SMT solver command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2023-11-12 02:32:53,878 INFO L131 ssoRankerPreferences]: Dump SMT script to file: false [2023-11-12 02:32:53,878 INFO L132 ssoRankerPreferences]: Path of dumped script: [2023-11-12 02:32:53,878 INFO L133 ssoRankerPreferences]: Filename of dumped script: NarrowKonv.c_Iteration7_Loop [2023-11-12 02:32:53,878 INFO L134 ssoRankerPreferences]: MapElimAlgo: Frank [2023-11-12 02:32:53,878 INFO L276 LassoAnalysis]: Starting lasso preprocessing... [2023-11-12 02:32:53,879 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-12 02:32:53,882 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-12 02:32:53,884 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-12 02:32:53,958 INFO L294 LassoAnalysis]: Preprocessing complete. [2023-11-12 02:32:53,958 INFO L490 LassoAnalysis]: Using template 'affine'. [2023-11-12 02:32:53,958 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2023-11-12 02:32:53,958 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1deda2bf-224c-4242-8866-e899ae47e0d0/bin/uautomizer-verify-uTZkv6EMXl/z3 [2023-11-12 02:32:53,959 INFO L229 MonitoredProcess]: Starting monitored process 33 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1deda2bf-224c-4242-8866-e899ae47e0d0/bin/uautomizer-verify-uTZkv6EMXl/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2023-11-12 02:32:53,962 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1deda2bf-224c-4242-8866-e899ae47e0d0/bin/uautomizer-verify-uTZkv6EMXl/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (33)] Waiting until timeout for monitored process [2023-11-12 02:32:53,963 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2023-11-12 02:32:53,973 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2023-11-12 02:32:53,973 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2023-11-12 02:32:53,973 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2023-11-12 02:32:53,973 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2023-11-12 02:32:53,982 INFO L401 nArgumentSynthesizer]: We have 6 Motzkin's Theorem applications. [2023-11-12 02:32:53,982 INFO L402 nArgumentSynthesizer]: A total of 2 supporting invariants were added. [2023-11-12 02:32:53,997 INFO L527 LassoAnalysis]: Proving termination failed for this template and these settings. [2023-11-12 02:32:54,006 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1deda2bf-224c-4242-8866-e899ae47e0d0/bin/uautomizer-verify-uTZkv6EMXl/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (33)] Forceful destruction successful, exit code 0 [2023-11-12 02:32:54,006 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2023-11-12 02:32:54,006 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1deda2bf-224c-4242-8866-e899ae47e0d0/bin/uautomizer-verify-uTZkv6EMXl/z3 [2023-11-12 02:32:54,007 INFO L229 MonitoredProcess]: Starting monitored process 34 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1deda2bf-224c-4242-8866-e899ae47e0d0/bin/uautomizer-verify-uTZkv6EMXl/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2023-11-12 02:32:54,010 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1deda2bf-224c-4242-8866-e899ae47e0d0/bin/uautomizer-verify-uTZkv6EMXl/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (34)] Waiting until timeout for monitored process [2023-11-12 02:32:54,010 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2023-11-12 02:32:54,022 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2023-11-12 02:32:54,023 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2023-11-12 02:32:54,023 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2023-11-12 02:32:54,023 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2023-11-12 02:32:54,025 INFO L401 nArgumentSynthesizer]: We have 6 Motzkin's Theorem applications. [2023-11-12 02:32:54,025 INFO L402 nArgumentSynthesizer]: A total of 2 supporting invariants were added. [2023-11-12 02:32:54,045 INFO L527 LassoAnalysis]: Proving termination failed for this template and these settings. [2023-11-12 02:32:54,049 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1deda2bf-224c-4242-8866-e899ae47e0d0/bin/uautomizer-verify-uTZkv6EMXl/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (34)] Forceful destruction successful, exit code 0 [2023-11-12 02:32:54,049 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2023-11-12 02:32:54,050 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1deda2bf-224c-4242-8866-e899ae47e0d0/bin/uautomizer-verify-uTZkv6EMXl/z3 [2023-11-12 02:32:54,051 INFO L229 MonitoredProcess]: Starting monitored process 35 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1deda2bf-224c-4242-8866-e899ae47e0d0/bin/uautomizer-verify-uTZkv6EMXl/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2023-11-12 02:32:54,058 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2023-11-12 02:32:54,070 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2023-11-12 02:32:54,071 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2023-11-12 02:32:54,071 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2023-11-12 02:32:54,071 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2023-11-12 02:32:54,071 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2023-11-12 02:32:54,072 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2023-11-12 02:32:54,072 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2023-11-12 02:32:54,074 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1deda2bf-224c-4242-8866-e899ae47e0d0/bin/uautomizer-verify-uTZkv6EMXl/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (35)] Waiting until timeout for monitored process [2023-11-12 02:32:54,093 INFO L420 nArgumentSynthesizer]: Found a termination argument, trying to simplify. [2023-11-12 02:32:54,097 INFO L443 ModelExtractionUtils]: Simplification made 3 calls to the SMT solver. [2023-11-12 02:32:54,097 INFO L444 ModelExtractionUtils]: 1 out of 4 variables were initially zero. Simplification set additionally 1 variables to zero. [2023-11-12 02:32:54,098 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2023-11-12 02:32:54,098 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1deda2bf-224c-4242-8866-e899ae47e0d0/bin/uautomizer-verify-uTZkv6EMXl/z3 [2023-11-12 02:32:54,099 INFO L229 MonitoredProcess]: Starting monitored process 36 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1deda2bf-224c-4242-8866-e899ae47e0d0/bin/uautomizer-verify-uTZkv6EMXl/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2023-11-12 02:32:54,106 INFO L435 nArgumentSynthesizer]: Simplifying supporting invariants... [2023-11-12 02:32:54,106 INFO L438 nArgumentSynthesizer]: Removed 0 redundant supporting invariants from a total of 0. [2023-11-12 02:32:54,106 INFO L513 LassoAnalysis]: Proved termination. [2023-11-12 02:32:54,106 INFO L515 LassoAnalysis]: Termination argument consisting of: Ranking function f(ULTIMATE.start_main_~range~0#1) = 1*ULTIMATE.start_main_~range~0#1 Supporting invariants [] [2023-11-12 02:32:54,109 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1deda2bf-224c-4242-8866-e899ae47e0d0/bin/uautomizer-verify-uTZkv6EMXl/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (36)] Waiting until timeout for monitored process [2023-11-12 02:32:54,111 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1deda2bf-224c-4242-8866-e899ae47e0d0/bin/uautomizer-verify-uTZkv6EMXl/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (35)] Forceful destruction successful, exit code 0 [2023-11-12 02:32:54,111 INFO L156 tatePredicateManager]: 0 out of 0 supporting invariants were superfluous and have been removed [2023-11-12 02:32:54,123 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-12 02:32:54,148 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-12 02:32:54,148 INFO L262 TraceCheckSpWp]: Trace formula consists of 79 conjuncts, 2 conjunts are in the unsatisfiable core [2023-11-12 02:32:54,150 INFO L285 TraceCheckSpWp]: Computing forward predicates... [2023-11-12 02:32:54,206 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-12 02:32:54,207 INFO L262 TraceCheckSpWp]: Trace formula consists of 23 conjuncts, 7 conjunts are in the unsatisfiable core [2023-11-12 02:32:54,207 INFO L285 TraceCheckSpWp]: Computing forward predicates... [2023-11-12 02:32:54,275 INFO L134 CoverageAnalysis]: Checked inductivity of 9 backedges. 9 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-12 02:32:54,276 INFO L141 lantAutomatonBouncer]: Defining deterministic Buchi interpolant automaton with honda bouncer for stem and without honda bouncer for loop.1 stem predicates 4 loop predicates [2023-11-12 02:32:54,276 INFO L71 iDifferenceNCSBLazy3]: Start buchiDifferenceNCSBLazy3. First operand 58 states and 71 transitions. cyclomatic complexity: 17 Second operand has 6 states, 6 states have (on average 2.6666666666666665) internal successors, (16), 6 states have internal predecessors, (16), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-12 02:32:54,304 INFO L75 iDifferenceNCSBLazy3]: Finished buchiDifferenceNCSBLazy3. First operand 58 states and 71 transitions. cyclomatic complexity: 17. Second operand has 6 states, 6 states have (on average 2.6666666666666665) internal successors, (16), 6 states have internal predecessors, (16), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Result 120 states and 152 transitions. Complement of second has 6 states. [2023-11-12 02:32:54,305 INFO L141 InterpolantAutomaton]: Switched to read-only mode: Buchi interpolant automaton has 4 states 1 stem states 2 non-accepting loop states 1 accepting loop states [2023-11-12 02:32:54,305 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 6 states, 6 states have (on average 2.6666666666666665) internal successors, (16), 6 states have internal predecessors, (16), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-12 02:32:54,306 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 4 states to 4 states and 11 transitions. [2023-11-12 02:32:54,306 INFO L84 BuchiAccepts]: Start buchiAccepts Operand 4 states and 11 transitions. Stem has 36 letters. Loop has 9 letters. [2023-11-12 02:32:54,306 INFO L116 BuchiAccepts]: Finished buchiAccepts. [2023-11-12 02:32:54,306 INFO L84 BuchiAccepts]: Start buchiAccepts Operand 4 states and 11 transitions. Stem has 45 letters. Loop has 9 letters. [2023-11-12 02:32:54,307 INFO L116 BuchiAccepts]: Finished buchiAccepts. [2023-11-12 02:32:54,307 INFO L84 BuchiAccepts]: Start buchiAccepts Operand 4 states and 11 transitions. Stem has 36 letters. Loop has 18 letters. [2023-11-12 02:32:54,307 INFO L116 BuchiAccepts]: Finished buchiAccepts. [2023-11-12 02:32:54,307 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 120 states and 152 transitions. [2023-11-12 02:32:54,309 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2023-11-12 02:32:54,311 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 120 states to 82 states and 105 transitions. [2023-11-12 02:32:54,311 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 7 [2023-11-12 02:32:54,311 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 8 [2023-11-12 02:32:54,311 INFO L73 IsDeterministic]: Start isDeterministic. Operand 82 states and 105 transitions. [2023-11-12 02:32:54,311 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2023-11-12 02:32:54,311 INFO L218 hiAutomatonCegarLoop]: Abstraction has 82 states and 105 transitions. [2023-11-12 02:32:54,316 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 82 states and 105 transitions. [2023-11-12 02:32:54,321 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 82 to 66. [2023-11-12 02:32:54,324 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 66 states, 66 states have (on average 1.2727272727272727) internal successors, (84), 65 states have internal predecessors, (84), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-12 02:32:54,327 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 66 states to 66 states and 84 transitions. [2023-11-12 02:32:54,328 INFO L240 hiAutomatonCegarLoop]: Abstraction has 66 states and 84 transitions. [2023-11-12 02:32:54,329 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-12 02:32:54,329 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 25 interpolants. [2023-11-12 02:32:54,329 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=244, Invalid=356, Unknown=0, NotChecked=0, Total=600 [2023-11-12 02:32:54,330 INFO L87 Difference]: Start difference. First operand 66 states and 84 transitions. Second operand has 25 states, 25 states have (on average 3.04) internal successors, (76), 25 states have internal predecessors, (76), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-12 02:32:54,570 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-12 02:32:54,571 INFO L93 Difference]: Finished difference Result 154 states and 172 transitions. [2023-11-12 02:32:54,571 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 154 states and 172 transitions. [2023-11-12 02:32:54,572 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2023-11-12 02:32:54,574 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 154 states to 118 states and 136 transitions. [2023-11-12 02:32:54,574 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 6 [2023-11-12 02:32:54,574 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 6 [2023-11-12 02:32:54,574 INFO L73 IsDeterministic]: Start isDeterministic. Operand 118 states and 136 transitions. [2023-11-12 02:32:54,574 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2023-11-12 02:32:54,574 INFO L218 hiAutomatonCegarLoop]: Abstraction has 118 states and 136 transitions. [2023-11-12 02:32:54,575 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 118 states and 136 transitions. [2023-11-12 02:32:54,579 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 118 to 114. [2023-11-12 02:32:54,580 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 114 states, 114 states have (on average 1.1578947368421053) internal successors, (132), 113 states have internal predecessors, (132), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-12 02:32:54,580 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 114 states to 114 states and 132 transitions. [2023-11-12 02:32:54,581 INFO L240 hiAutomatonCegarLoop]: Abstraction has 114 states and 132 transitions. [2023-11-12 02:32:54,581 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 25 states. [2023-11-12 02:32:54,582 INFO L428 stractBuchiCegarLoop]: Abstraction has 114 states and 132 transitions. [2023-11-12 02:32:54,582 INFO L335 stractBuchiCegarLoop]: ======== Iteration 8 ============ [2023-11-12 02:32:54,582 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 114 states and 132 transitions. [2023-11-12 02:32:54,583 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2023-11-12 02:32:54,583 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-12 02:32:54,583 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-12 02:32:54,585 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [24, 23, 21, 2, 1, 1] [2023-11-12 02:32:54,586 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1] [2023-11-12 02:32:54,586 INFO L748 eck$LassoCheckResult]: Stem: 2328#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true; 2329#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet0#1, main_~i~0#1, main_~range~0#1;havoc main_~i~0#1;havoc main_~range~0#1;havoc main_#t~nondet0#1;main_~i~0#1 := main_#t~nondet0#1;havoc main_#t~nondet0#1;main_~range~0#1 := 20; 2330#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 2331#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 2332#L13 assume main_~i~0#1 == main_~range~0#1;main_~i~0#1 := 0;main_~range~0#1 := main_~range~0#1 - 1; 2424#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 2423#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 2422#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 2421#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 2420#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 2419#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 2418#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 2417#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 2416#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 2415#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 2414#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 2413#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 2412#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 2411#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 2410#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 2409#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 2408#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 2407#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 2406#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 2405#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 2404#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 2403#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 2402#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 2401#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 2400#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 2399#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 2398#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 2397#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 2396#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 2395#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 2394#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 2393#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 2392#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 2391#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 2390#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 2389#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 2388#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 2387#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 2386#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 2385#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 2382#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 2383#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 2381#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 2380#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 2379#L13 assume main_~i~0#1 == main_~range~0#1;main_~i~0#1 := 0;main_~range~0#1 := main_~range~0#1 - 1; 2378#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 2376#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 2375#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 2374#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 2373#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 2372#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 2371#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 2370#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 2369#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 2368#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 2367#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 2366#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 2365#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 2364#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 2363#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 2362#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 2361#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 2360#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 2348#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 2345#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 2341#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 2339#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 2324#L12 [2023-11-12 02:32:54,586 INFO L750 eck$LassoCheckResult]: Loop: 2324#L12 assume !!(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 2323#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 2324#L12 [2023-11-12 02:32:54,586 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-12 02:32:54,587 INFO L85 PathProgramCache]: Analyzing trace with hash 1262893886, now seen corresponding path program 7 times [2023-11-12 02:32:54,587 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-12 02:32:54,587 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [375004511] [2023-11-12 02:32:54,587 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-12 02:32:54,587 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-12 02:32:54,605 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-12 02:32:54,995 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1deda2bf-224c-4242-8866-e899ae47e0d0/bin/uautomizer-verify-uTZkv6EMXl/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (36)] Forceful destruction successful, exit code 0 [2023-11-12 02:32:55,195 INFO L134 CoverageAnalysis]: Checked inductivity of 782 backedges. 352 proven. 360 refuted. 0 times theorem prover too weak. 70 trivial. 0 not checked. [2023-11-12 02:32:55,195 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-12 02:32:55,196 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [375004511] [2023-11-12 02:32:55,196 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [375004511] provided 0 perfect and 1 imperfect interpolant sequences [2023-11-12 02:32:55,196 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1173992583] [2023-11-12 02:32:55,196 INFO L93 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2023-11-12 02:32:55,196 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2023-11-12 02:32:55,196 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1deda2bf-224c-4242-8866-e899ae47e0d0/bin/uautomizer-verify-uTZkv6EMXl/z3 [2023-11-12 02:32:55,198 INFO L229 MonitoredProcess]: Starting monitored process 37 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1deda2bf-224c-4242-8866-e899ae47e0d0/bin/uautomizer-verify-uTZkv6EMXl/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2023-11-12 02:32:55,207 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1deda2bf-224c-4242-8866-e899ae47e0d0/bin/uautomizer-verify-uTZkv6EMXl/z3 -smt2 -in SMTLIB2_COMPLIANT=true (37)] Waiting until timeout for monitored process [2023-11-12 02:32:55,259 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-12 02:32:55,260 INFO L262 TraceCheckSpWp]: Trace formula consists of 151 conjuncts, 18 conjunts are in the unsatisfiable core [2023-11-12 02:32:55,270 INFO L285 TraceCheckSpWp]: Computing forward predicates... [2023-11-12 02:32:55,713 INFO L134 CoverageAnalysis]: Checked inductivity of 782 backedges. 352 proven. 360 refuted. 0 times theorem prover too weak. 70 trivial. 0 not checked. [2023-11-12 02:32:55,713 INFO L327 TraceCheckSpWp]: Computing backward predicates... [2023-11-12 02:32:56,075 INFO L134 CoverageAnalysis]: Checked inductivity of 782 backedges. 352 proven. 360 refuted. 0 times theorem prover too weak. 70 trivial. 0 not checked. [2023-11-12 02:32:56,076 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1173992583] provided 0 perfect and 2 imperfect interpolant sequences [2023-11-12 02:32:56,076 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2023-11-12 02:32:56,076 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [18, 18, 18] total 38 [2023-11-12 02:32:56,076 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [433315034] [2023-11-12 02:32:56,077 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2023-11-12 02:32:56,077 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-12 02:32:56,078 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-12 02:32:56,078 INFO L85 PathProgramCache]: Analyzing trace with hash 1654, now seen corresponding path program 3 times [2023-11-12 02:32:56,078 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-12 02:32:56,078 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [275553789] [2023-11-12 02:32:56,078 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-12 02:32:56,078 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-12 02:32:56,084 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-12 02:32:56,084 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-12 02:32:56,085 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-12 02:32:56,086 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-12 02:32:56,105 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-12 02:32:56,106 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 38 interpolants. [2023-11-12 02:32:56,106 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=545, Invalid=861, Unknown=0, NotChecked=0, Total=1406 [2023-11-12 02:32:56,107 INFO L87 Difference]: Start difference. First operand 114 states and 132 transitions. cyclomatic complexity: 24 Second operand has 38 states, 38 states have (on average 3.0526315789473686) internal successors, (116), 38 states have internal predecessors, (116), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-12 02:32:56,378 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-12 02:32:56,378 INFO L93 Difference]: Finished difference Result 231 states and 249 transitions. [2023-11-12 02:32:56,378 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 231 states and 249 transitions. [2023-11-12 02:32:56,381 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2023-11-12 02:32:56,383 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 231 states to 181 states and 199 transitions. [2023-11-12 02:32:56,383 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 6 [2023-11-12 02:32:56,383 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 6 [2023-11-12 02:32:56,383 INFO L73 IsDeterministic]: Start isDeterministic. Operand 181 states and 199 transitions. [2023-11-12 02:32:56,383 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2023-11-12 02:32:56,384 INFO L218 hiAutomatonCegarLoop]: Abstraction has 181 states and 199 transitions. [2023-11-12 02:32:56,384 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 181 states and 199 transitions. [2023-11-12 02:32:56,390 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 181 to 177. [2023-11-12 02:32:56,390 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 177 states, 177 states have (on average 1.1016949152542372) internal successors, (195), 176 states have internal predecessors, (195), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-12 02:32:56,391 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 177 states to 177 states and 195 transitions. [2023-11-12 02:32:56,392 INFO L240 hiAutomatonCegarLoop]: Abstraction has 177 states and 195 transitions. [2023-11-12 02:32:56,392 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 38 states. [2023-11-12 02:32:56,393 INFO L428 stractBuchiCegarLoop]: Abstraction has 177 states and 195 transitions. [2023-11-12 02:32:56,393 INFO L335 stractBuchiCegarLoop]: ======== Iteration 9 ============ [2023-11-12 02:32:56,393 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 177 states and 195 transitions. [2023-11-12 02:32:56,395 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2023-11-12 02:32:56,395 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-12 02:32:56,395 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-12 02:32:56,399 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [37, 36, 34, 2, 1, 1] [2023-11-12 02:32:56,400 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1] [2023-11-12 02:32:56,400 INFO L748 eck$LassoCheckResult]: Stem: 3148#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true; 3149#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet0#1, main_~i~0#1, main_~range~0#1;havoc main_~i~0#1;havoc main_~range~0#1;havoc main_#t~nondet0#1;main_~i~0#1 := main_#t~nondet0#1;havoc main_#t~nondet0#1;main_~range~0#1 := 20; 3150#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 3151#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 3152#L13 assume main_~i~0#1 == main_~range~0#1;main_~i~0#1 := 0;main_~range~0#1 := main_~range~0#1 - 1; 3282#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 3281#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 3280#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 3279#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 3278#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 3277#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 3276#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 3275#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 3274#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 3273#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 3272#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 3271#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 3270#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 3269#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 3268#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 3267#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 3266#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 3265#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 3264#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 3263#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 3262#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 3261#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 3260#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 3259#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 3258#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 3257#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 3256#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 3255#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 3254#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 3253#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 3252#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 3251#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 3250#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 3249#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 3248#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 3247#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 3246#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 3245#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 3244#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 3243#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 3242#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 3241#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 3240#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 3239#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 3238#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 3237#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 3236#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 3235#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 3234#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 3233#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 3232#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 3231#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 3230#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 3229#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 3228#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 3225#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 3226#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 3224#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 3223#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 3222#L13 assume main_~i~0#1 == main_~range~0#1;main_~i~0#1 := 0;main_~range~0#1 := main_~range~0#1 - 1; 3221#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 3220#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 3219#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 3218#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 3217#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 3216#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 3215#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 3214#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 3213#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 3212#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 3211#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 3210#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 3209#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 3208#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 3207#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 3206#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 3205#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 3204#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 3203#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 3202#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 3201#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 3200#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 3199#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 3198#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 3197#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 3196#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 3195#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 3194#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 3193#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 3192#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 3191#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 3190#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 3189#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 3188#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 3187#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 3186#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 3185#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 3184#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 3183#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 3182#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 3181#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 3180#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 3168#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 3165#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 3162#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 3159#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 3144#L12 [2023-11-12 02:32:56,401 INFO L750 eck$LassoCheckResult]: Loop: 3144#L12 assume !!(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 3143#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 3144#L12 [2023-11-12 02:32:56,401 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-12 02:32:56,401 INFO L85 PathProgramCache]: Analyzing trace with hash -1287581916, now seen corresponding path program 8 times [2023-11-12 02:32:56,401 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-12 02:32:56,402 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1780405192] [2023-11-12 02:32:56,402 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-12 02:32:56,402 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-12 02:32:56,433 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-12 02:32:56,434 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-12 02:32:56,457 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-12 02:32:56,464 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-12 02:32:56,465 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-12 02:32:56,465 INFO L85 PathProgramCache]: Analyzing trace with hash 1654, now seen corresponding path program 4 times [2023-11-12 02:32:56,465 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-12 02:32:56,465 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [280210634] [2023-11-12 02:32:56,465 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-12 02:32:56,466 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-12 02:32:56,468 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-12 02:32:56,468 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-12 02:32:56,469 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-12 02:32:56,470 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-12 02:32:56,471 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-12 02:32:56,471 INFO L85 PathProgramCache]: Analyzing trace with hash -415639335, now seen corresponding path program 1 times [2023-11-12 02:32:56,471 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-12 02:32:56,471 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [936449053] [2023-11-12 02:32:56,471 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-12 02:32:56,472 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-12 02:32:56,494 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-12 02:32:56,582 INFO L134 CoverageAnalysis]: Checked inductivity of 1999 backedges. 179 proven. 0 refuted. 0 times theorem prover too weak. 1820 trivial. 0 not checked. [2023-11-12 02:32:56,582 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-12 02:32:56,582 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [936449053] [2023-11-12 02:32:56,582 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [936449053] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-12 02:32:56,583 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-12 02:32:56,583 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2023-11-12 02:32:56,583 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1625647276] [2023-11-12 02:32:56,583 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-12 02:32:56,599 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-12 02:32:56,599 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2023-11-12 02:32:56,599 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=6, Invalid=6, Unknown=0, NotChecked=0, Total=12 [2023-11-12 02:32:56,599 INFO L87 Difference]: Start difference. First operand 177 states and 195 transitions. cyclomatic complexity: 24 Second operand has 4 states, 4 states have (on average 3.0) internal successors, (12), 4 states have internal predecessors, (12), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-12 02:32:56,615 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-12 02:32:56,616 INFO L93 Difference]: Finished difference Result 184 states and 199 transitions. [2023-11-12 02:32:56,616 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 184 states and 199 transitions. [2023-11-12 02:32:56,618 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2023-11-12 02:32:56,619 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 184 states to 135 states and 146 transitions. [2023-11-12 02:32:56,619 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 7 [2023-11-12 02:32:56,619 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 7 [2023-11-12 02:32:56,619 INFO L73 IsDeterministic]: Start isDeterministic. Operand 135 states and 146 transitions. [2023-11-12 02:32:56,619 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2023-11-12 02:32:56,619 INFO L218 hiAutomatonCegarLoop]: Abstraction has 135 states and 146 transitions. [2023-11-12 02:32:56,620 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 135 states and 146 transitions. [2023-11-12 02:32:56,622 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 135 to 127. [2023-11-12 02:32:56,623 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 127 states, 127 states have (on average 1.078740157480315) internal successors, (137), 126 states have internal predecessors, (137), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-12 02:32:56,624 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 127 states to 127 states and 137 transitions. [2023-11-12 02:32:56,624 INFO L240 hiAutomatonCegarLoop]: Abstraction has 127 states and 137 transitions. [2023-11-12 02:32:56,624 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2023-11-12 02:32:56,625 INFO L428 stractBuchiCegarLoop]: Abstraction has 127 states and 137 transitions. [2023-11-12 02:32:56,625 INFO L335 stractBuchiCegarLoop]: ======== Iteration 10 ============ [2023-11-12 02:32:56,625 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 127 states and 137 transitions. [2023-11-12 02:32:56,626 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2023-11-12 02:32:56,626 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-12 02:32:56,626 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-12 02:32:56,628 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [38, 37, 34, 3, 1, 1, 1] [2023-11-12 02:32:56,628 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1] [2023-11-12 02:32:56,628 INFO L748 eck$LassoCheckResult]: Stem: 3519#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true; 3520#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet0#1, main_~i~0#1, main_~range~0#1;havoc main_~i~0#1;havoc main_~range~0#1;havoc main_#t~nondet0#1;main_~i~0#1 := main_#t~nondet0#1;havoc main_#t~nondet0#1;main_~range~0#1 := 20; 3513#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 3515#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 3518#L13 assume main_~i~0#1 == main_~range~0#1;main_~i~0#1 := 0;main_~range~0#1 := main_~range~0#1 - 1; 3516#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 3517#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 3521#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 3639#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 3638#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 3637#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 3636#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 3635#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 3634#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 3633#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 3632#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 3631#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 3630#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 3629#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 3628#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 3627#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 3626#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 3625#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 3624#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 3623#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 3622#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 3621#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 3620#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 3619#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 3618#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 3617#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 3616#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 3615#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 3614#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 3613#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 3612#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 3611#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 3610#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 3609#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 3608#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 3607#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 3606#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 3605#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 3604#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 3603#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 3602#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 3601#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 3600#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 3599#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 3598#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 3597#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 3596#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 3595#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 3594#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 3593#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 3592#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 3591#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 3590#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 3589#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 3588#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 3586#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 3587#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 3585#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 3584#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 3583#L13 assume main_~i~0#1 == main_~range~0#1;main_~i~0#1 := 0;main_~range~0#1 := main_~range~0#1 - 1; 3582#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 3581#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 3580#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 3579#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 3578#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 3577#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 3576#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 3575#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 3574#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 3573#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 3572#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 3571#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 3570#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 3569#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 3568#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 3567#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 3566#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 3565#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 3564#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 3563#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 3562#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 3561#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 3560#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 3559#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 3558#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 3557#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 3556#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 3555#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 3554#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 3553#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 3552#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 3551#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 3550#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 3549#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 3548#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 3547#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 3546#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 3545#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 3544#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 3543#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 3542#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 3540#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 3541#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 3535#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 3532#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 3533#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 3530#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 3526#L13 assume main_~i~0#1 == main_~range~0#1;main_~i~0#1 := 0;main_~range~0#1 := main_~range~0#1 - 1; 3527#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 3524#L12 assume !!(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 3523#L12-1 [2023-11-12 02:32:56,629 INFO L750 eck$LassoCheckResult]: Loop: 3523#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 3522#L12 assume !!(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 3523#L12-1 [2023-11-12 02:32:56,629 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-12 02:32:56,629 INFO L85 PathProgramCache]: Analyzing trace with hash 2325394, now seen corresponding path program 2 times [2023-11-12 02:32:56,630 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-12 02:32:56,630 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1377565238] [2023-11-12 02:32:56,630 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-12 02:32:56,630 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-12 02:32:56,656 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-12 02:32:57,201 INFO L134 CoverageAnalysis]: Checked inductivity of 2072 backedges. 74 proven. 1428 refuted. 0 times theorem prover too weak. 570 trivial. 0 not checked. [2023-11-12 02:32:57,202 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-12 02:32:57,202 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1377565238] [2023-11-12 02:32:57,202 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1377565238] provided 0 perfect and 1 imperfect interpolant sequences [2023-11-12 02:32:57,202 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1387156839] [2023-11-12 02:32:57,202 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2023-11-12 02:32:57,202 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2023-11-12 02:32:57,202 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1deda2bf-224c-4242-8866-e899ae47e0d0/bin/uautomizer-verify-uTZkv6EMXl/z3 [2023-11-12 02:32:57,203 INFO L229 MonitoredProcess]: Starting monitored process 38 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1deda2bf-224c-4242-8866-e899ae47e0d0/bin/uautomizer-verify-uTZkv6EMXl/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2023-11-12 02:32:57,236 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1deda2bf-224c-4242-8866-e899ae47e0d0/bin/uautomizer-verify-uTZkv6EMXl/z3 -smt2 -in SMTLIB2_COMPLIANT=true (38)] Waiting until timeout for monitored process [2023-11-12 02:32:57,284 INFO L228 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2023-11-12 02:32:57,285 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2023-11-12 02:32:57,286 INFO L262 TraceCheckSpWp]: Trace formula consists of 242 conjuncts, 20 conjunts are in the unsatisfiable core [2023-11-12 02:32:57,289 INFO L285 TraceCheckSpWp]: Computing forward predicates... [2023-11-12 02:32:57,778 INFO L134 CoverageAnalysis]: Checked inductivity of 2072 backedges. 74 proven. 1428 refuted. 0 times theorem prover too weak. 570 trivial. 0 not checked. [2023-11-12 02:32:57,778 INFO L327 TraceCheckSpWp]: Computing backward predicates... [2023-11-12 02:32:58,211 INFO L134 CoverageAnalysis]: Checked inductivity of 2072 backedges. 74 proven. 1428 refuted. 0 times theorem prover too weak. 570 trivial. 0 not checked. [2023-11-12 02:32:58,211 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1387156839] provided 0 perfect and 2 imperfect interpolant sequences [2023-11-12 02:32:58,212 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2023-11-12 02:32:58,212 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [20, 20, 20] total 40 [2023-11-12 02:32:58,212 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2126430658] [2023-11-12 02:32:58,212 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2023-11-12 02:32:58,213 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-12 02:32:58,213 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-12 02:32:58,213 INFO L85 PathProgramCache]: Analyzing trace with hash 1324, now seen corresponding path program 5 times [2023-11-12 02:32:58,213 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-12 02:32:58,214 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1739307260] [2023-11-12 02:32:58,214 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-12 02:32:58,214 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-12 02:32:58,216 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-12 02:32:58,216 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-12 02:32:58,217 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-12 02:32:58,218 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-12 02:32:58,233 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-12 02:32:58,234 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 40 interpolants. [2023-11-12 02:32:58,234 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=556, Invalid=1004, Unknown=0, NotChecked=0, Total=1560 [2023-11-12 02:32:58,235 INFO L87 Difference]: Start difference. First operand 127 states and 137 transitions. cyclomatic complexity: 15 Second operand has 40 states, 40 states have (on average 3.075) internal successors, (123), 40 states have internal predecessors, (123), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-12 02:32:59,338 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-12 02:32:59,338 INFO L93 Difference]: Finished difference Result 395 states and 407 transitions. [2023-11-12 02:32:59,339 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 395 states and 407 transitions. [2023-11-12 02:32:59,342 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2023-11-12 02:32:59,344 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 395 states to 249 states and 261 transitions. [2023-11-12 02:32:59,345 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 6 [2023-11-12 02:32:59,345 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 6 [2023-11-12 02:32:59,345 INFO L73 IsDeterministic]: Start isDeterministic. Operand 249 states and 261 transitions. [2023-11-12 02:32:59,345 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2023-11-12 02:32:59,345 INFO L218 hiAutomatonCegarLoop]: Abstraction has 249 states and 261 transitions. [2023-11-12 02:32:59,346 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 249 states and 261 transitions. [2023-11-12 02:32:59,349 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 249 to 241. [2023-11-12 02:32:59,350 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 241 states, 241 states have (on average 1.049792531120332) internal successors, (253), 240 states have internal predecessors, (253), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-12 02:32:59,350 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 241 states to 241 states and 253 transitions. [2023-11-12 02:32:59,351 INFO L240 hiAutomatonCegarLoop]: Abstraction has 241 states and 253 transitions. [2023-11-12 02:32:59,353 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 76 states. [2023-11-12 02:32:59,354 INFO L428 stractBuchiCegarLoop]: Abstraction has 241 states and 253 transitions. [2023-11-12 02:32:59,354 INFO L335 stractBuchiCegarLoop]: ======== Iteration 11 ============ [2023-11-12 02:32:59,354 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 241 states and 253 transitions. [2023-11-12 02:32:59,356 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2023-11-12 02:32:59,356 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-12 02:32:59,356 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-12 02:32:59,359 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [76, 75, 70, 5, 1, 1, 1] [2023-11-12 02:32:59,360 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1] [2023-11-12 02:32:59,360 INFO L748 eck$LassoCheckResult]: Stem: 4843#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true; 4844#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet0#1, main_~i~0#1, main_~range~0#1;havoc main_~i~0#1;havoc main_~range~0#1;havoc main_#t~nondet0#1;main_~i~0#1 := main_#t~nondet0#1;havoc main_#t~nondet0#1;main_~range~0#1 := 20; 4845#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 4846#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 4847#L13 assume main_~i~0#1 == main_~range~0#1;main_~i~0#1 := 0;main_~range~0#1 := main_~range~0#1 - 1; 5078#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 4848#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 4842#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 4840#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 4841#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 5077#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 5076#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 5075#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 5074#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 5073#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 5072#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 5071#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 5070#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 5069#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 5068#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 5067#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 5066#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 5065#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 5064#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 5063#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 5062#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 5061#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 5060#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 5059#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 5058#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 5057#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 5056#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 5055#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 5054#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 5053#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 5052#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 5051#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 5050#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 5049#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 5048#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 5047#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 5046#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 5045#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 5044#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 5043#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 5042#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 5041#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 5040#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 5039#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 5038#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 5037#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 5036#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 5035#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 5034#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 5033#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 5032#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 5031#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 5030#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 5029#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 5028#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 5026#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 5027#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 5025#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 5024#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 5023#L13 assume main_~i~0#1 == main_~range~0#1;main_~i~0#1 := 0;main_~range~0#1 := main_~range~0#1 - 1; 5022#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 5021#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 5020#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 5019#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 5018#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 5017#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 5016#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 5015#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 5014#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 5013#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 5012#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 5011#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 5010#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 5009#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 5008#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 5007#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 5006#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 5005#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 5004#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 5003#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 5002#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 5001#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 5000#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 4999#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 4998#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 4997#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 4996#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 4995#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 4994#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 4993#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 4992#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 4991#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 4990#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 4989#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 4988#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 4987#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 4986#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 4985#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 4984#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 4983#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 4982#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 4981#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 4980#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 4979#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 4978#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 4977#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 4976#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 4975#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 4974#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 4973#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 4972#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 4971#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 4969#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 4970#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 4968#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 4967#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 4966#L13 assume main_~i~0#1 == main_~range~0#1;main_~i~0#1 := 0;main_~range~0#1 := main_~range~0#1 - 1; 4965#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 4964#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 4963#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 4962#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 4961#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 4960#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 4959#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 4958#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 4957#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 4956#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 4955#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 4954#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 4953#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 4952#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 4951#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 4950#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 4949#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 4948#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 4947#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 4946#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 4945#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 4944#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 4943#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 4942#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 4941#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 4940#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 4939#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 4938#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 4937#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 4936#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 4935#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 4934#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 4933#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 4932#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 4931#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 4930#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 4929#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 4928#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 4927#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 4926#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 4925#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 4924#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 4923#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 4922#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 4921#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 4920#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 4919#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 4918#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 4917#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 4915#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 4916#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 4914#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 4913#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 4912#L13 assume main_~i~0#1 == main_~range~0#1;main_~i~0#1 := 0;main_~range~0#1 := main_~range~0#1 - 1; 4911#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 4910#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 4909#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 4908#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 4907#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 4906#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 4905#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 4904#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 4903#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 4902#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 4901#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 4900#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 4899#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 4898#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 4897#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 4896#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 4895#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 4894#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 4893#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 4892#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 4891#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 4890#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 4889#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 4888#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 4887#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 4886#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 4885#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 4884#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 4883#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 4882#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 4881#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 4880#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 4879#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 4878#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 4877#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 4876#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 4875#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 4874#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 4873#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 4872#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 4871#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 4870#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 4869#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 4868#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 4866#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 4862#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 4861#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 4858#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 4859#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 4856#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 4851#L13 assume main_~i~0#1 == main_~range~0#1;main_~i~0#1 := 0;main_~range~0#1 := main_~range~0#1 - 1; 4855#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 4849#L12 assume !!(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 4838#L12-1 [2023-11-12 02:32:59,361 INFO L750 eck$LassoCheckResult]: Loop: 4838#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 4839#L12 assume !!(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 4838#L12-1 [2023-11-12 02:32:59,361 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-12 02:32:59,361 INFO L85 PathProgramCache]: Analyzing trace with hash 1383057750, now seen corresponding path program 3 times [2023-11-12 02:32:59,362 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-12 02:32:59,362 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [458013391] [2023-11-12 02:32:59,362 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-12 02:32:59,362 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-12 02:32:59,410 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-12 02:32:59,746 INFO L134 CoverageAnalysis]: Checked inductivity of 8475 backedges. 0 proven. 6525 refuted. 0 times theorem prover too weak. 1950 trivial. 0 not checked. [2023-11-12 02:32:59,746 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-12 02:32:59,746 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [458013391] [2023-11-12 02:32:59,746 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [458013391] provided 0 perfect and 1 imperfect interpolant sequences [2023-11-12 02:32:59,747 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1583712518] [2023-11-12 02:32:59,747 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 [2023-11-12 02:32:59,747 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2023-11-12 02:32:59,747 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1deda2bf-224c-4242-8866-e899ae47e0d0/bin/uautomizer-verify-uTZkv6EMXl/z3 [2023-11-12 02:32:59,753 INFO L229 MonitoredProcess]: Starting monitored process 39 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1deda2bf-224c-4242-8866-e899ae47e0d0/bin/uautomizer-verify-uTZkv6EMXl/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2023-11-12 02:32:59,778 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1deda2bf-224c-4242-8866-e899ae47e0d0/bin/uautomizer-verify-uTZkv6EMXl/z3 -smt2 -in SMTLIB2_COMPLIANT=true (39)] Waiting until timeout for monitored process [2023-11-12 02:32:59,813 INFO L228 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 6 check-sat command(s) [2023-11-12 02:32:59,813 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2023-11-12 02:32:59,814 INFO L262 TraceCheckSpWp]: Trace formula consists of 47 conjuncts, 7 conjunts are in the unsatisfiable core [2023-11-12 02:32:59,817 INFO L285 TraceCheckSpWp]: Computing forward predicates... [2023-11-12 02:32:59,884 INFO L134 CoverageAnalysis]: Checked inductivity of 8475 backedges. 730 proven. 5 refuted. 0 times theorem prover too weak. 7740 trivial. 0 not checked. [2023-11-12 02:32:59,884 INFO L327 TraceCheckSpWp]: Computing backward predicates... [2023-11-12 02:32:59,958 INFO L134 CoverageAnalysis]: Checked inductivity of 8475 backedges. 730 proven. 5 refuted. 0 times theorem prover too weak. 7740 trivial. 0 not checked. [2023-11-12 02:32:59,959 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1583712518] provided 0 perfect and 2 imperfect interpolant sequences [2023-11-12 02:32:59,959 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2023-11-12 02:32:59,959 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [7, 5, 5] total 11 [2023-11-12 02:32:59,960 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [661661159] [2023-11-12 02:32:59,960 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2023-11-12 02:32:59,961 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-12 02:32:59,961 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-12 02:32:59,961 INFO L85 PathProgramCache]: Analyzing trace with hash 1324, now seen corresponding path program 6 times [2023-11-12 02:32:59,961 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-12 02:32:59,962 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1934459406] [2023-11-12 02:32:59,962 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-12 02:32:59,962 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-12 02:32:59,964 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-12 02:32:59,964 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-12 02:32:59,964 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-12 02:32:59,966 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-12 02:32:59,981 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-12 02:32:59,981 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 12 interpolants. [2023-11-12 02:32:59,981 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=39, Invalid=93, Unknown=0, NotChecked=0, Total=132 [2023-11-12 02:32:59,982 INFO L87 Difference]: Start difference. First operand 241 states and 253 transitions. cyclomatic complexity: 19 Second operand has 12 states, 11 states have (on average 3.5454545454545454) internal successors, (39), 12 states have internal predecessors, (39), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-12 02:33:00,257 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-12 02:33:00,258 INFO L93 Difference]: Finished difference Result 278 states and 297 transitions. [2023-11-12 02:33:00,258 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 278 states and 297 transitions. [2023-11-12 02:33:00,260 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2023-11-12 02:33:00,262 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 278 states to 273 states and 292 transitions. [2023-11-12 02:33:00,263 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 8 [2023-11-12 02:33:00,263 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 8 [2023-11-12 02:33:00,263 INFO L73 IsDeterministic]: Start isDeterministic. Operand 273 states and 292 transitions. [2023-11-12 02:33:00,263 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2023-11-12 02:33:00,263 INFO L218 hiAutomatonCegarLoop]: Abstraction has 273 states and 292 transitions. [2023-11-12 02:33:00,263 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 273 states and 292 transitions. [2023-11-12 02:33:00,267 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 273 to 257. [2023-11-12 02:33:00,267 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 257 states, 257 states have (on average 1.0583657587548638) internal successors, (272), 256 states have internal predecessors, (272), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-12 02:33:00,268 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 257 states to 257 states and 272 transitions. [2023-11-12 02:33:00,268 INFO L240 hiAutomatonCegarLoop]: Abstraction has 257 states and 272 transitions. [2023-11-12 02:33:00,269 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 24 states. [2023-11-12 02:33:00,270 INFO L428 stractBuchiCegarLoop]: Abstraction has 257 states and 272 transitions. [2023-11-12 02:33:00,270 INFO L335 stractBuchiCegarLoop]: ======== Iteration 12 ============ [2023-11-12 02:33:00,271 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 257 states and 272 transitions. [2023-11-12 02:33:00,272 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2023-11-12 02:33:00,273 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-12 02:33:00,273 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-12 02:33:00,277 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [78, 77, 71, 6, 1, 1, 1] [2023-11-12 02:33:00,277 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1] [2023-11-12 02:33:00,278 INFO L748 eck$LassoCheckResult]: Stem: 6784#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true; 6785#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet0#1, main_~i~0#1, main_~range~0#1;havoc main_~i~0#1;havoc main_~range~0#1;havoc main_#t~nondet0#1;main_~i~0#1 := main_#t~nondet0#1;havoc main_#t~nondet0#1;main_~range~0#1 := 20; 6778#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 6780#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 6786#L13 assume main_~i~0#1 == main_~range~0#1;main_~i~0#1 := 0;main_~range~0#1 := main_~range~0#1 - 1; 7034#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 6787#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 6783#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 6781#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 6782#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 7033#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 7032#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 7031#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 7030#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 7029#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 7028#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 7027#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 7026#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 7025#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 7024#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 7023#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 7022#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 7021#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 7020#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 7019#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 7018#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 7017#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 7016#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 7015#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 7014#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 7013#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 7012#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 7011#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 7010#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 7009#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 7008#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 7007#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 7006#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 7005#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 7004#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 7003#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 7002#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 7001#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 7000#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 6999#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 6998#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 6997#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 6996#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 6995#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 6994#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 6993#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 6992#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 6991#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 6990#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 6989#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 6988#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 6987#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 6986#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 6985#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 6984#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 6982#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 6983#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 6981#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 6980#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 6979#L13 assume main_~i~0#1 == main_~range~0#1;main_~i~0#1 := 0;main_~range~0#1 := main_~range~0#1 - 1; 6978#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 6977#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 6976#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 6975#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 6974#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 6973#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 6972#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 6971#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 6970#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 6969#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 6968#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 6967#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 6966#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 6965#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 6964#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 6963#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 6962#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 6961#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 6960#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 6959#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 6958#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 6957#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 6956#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 6955#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 6954#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 6953#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 6952#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 6951#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 6950#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 6949#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 6948#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 6947#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 6946#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 6945#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 6944#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 6943#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 6942#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 6941#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 6940#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 6939#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 6938#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 6937#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 6936#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 6935#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 6934#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 6933#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 6932#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 6931#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 6930#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 6929#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 6928#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 6927#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 6925#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 6926#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 6924#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 6923#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 6922#L13 assume main_~i~0#1 == main_~range~0#1;main_~i~0#1 := 0;main_~range~0#1 := main_~range~0#1 - 1; 6921#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 6920#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 6919#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 6918#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 6917#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 6916#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 6915#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 6914#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 6913#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 6912#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 6911#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 6910#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 6909#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 6908#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 6907#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 6906#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 6905#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 6904#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 6903#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 6902#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 6901#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 6900#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 6899#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 6898#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 6897#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 6896#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 6895#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 6894#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 6893#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 6892#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 6891#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 6890#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 6889#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 6888#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 6887#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 6886#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 6885#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 6884#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 6883#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 6882#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 6881#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 6880#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 6879#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 6878#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 6877#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 6876#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 6875#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 6874#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 6873#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 6871#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 6872#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 6870#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 6869#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 6868#L13 assume main_~i~0#1 == main_~range~0#1;main_~i~0#1 := 0;main_~range~0#1 := main_~range~0#1 - 1; 6867#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 6866#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 6865#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 6864#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 6863#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 6862#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 6861#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 6860#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 6859#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 6858#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 6857#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 6856#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 6855#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 6854#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 6853#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 6852#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 6851#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 6850#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 6849#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 6848#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 6847#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 6846#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 6845#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 6844#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 6843#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 6842#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 6841#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 6840#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 6839#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 6838#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 6837#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 6836#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 6835#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 6834#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 6833#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 6832#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 6831#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 6830#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 6829#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 6828#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 6827#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 6826#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 6825#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 6824#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 6823#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 6822#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 6820#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 6821#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 6819#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 6818#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 6812#L13 assume main_~i~0#1 == main_~range~0#1;main_~i~0#1 := 0;main_~range~0#1 := main_~range~0#1 - 1; 6813#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 6815#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 6799#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 6800#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 6796#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 6792#L13 assume main_~i~0#1 == main_~range~0#1;main_~i~0#1 := 0;main_~range~0#1 := main_~range~0#1 - 1; 6793#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 6790#L12 assume !!(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 6789#L12-1 [2023-11-12 02:33:00,278 INFO L750 eck$LassoCheckResult]: Loop: 6789#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 6788#L12 assume !!(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 6789#L12-1 [2023-11-12 02:33:00,278 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-12 02:33:00,279 INFO L85 PathProgramCache]: Analyzing trace with hash -2031563884, now seen corresponding path program 4 times [2023-11-12 02:33:00,279 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-12 02:33:00,279 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [855510467] [2023-11-12 02:33:00,279 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-12 02:33:00,279 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-12 02:33:00,331 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-12 02:33:00,685 INFO L134 CoverageAnalysis]: Checked inductivity of 8932 backedges. 154 proven. 6828 refuted. 0 times theorem prover too weak. 1950 trivial. 0 not checked. [2023-11-12 02:33:00,686 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-12 02:33:00,686 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [855510467] [2023-11-12 02:33:00,686 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [855510467] provided 0 perfect and 1 imperfect interpolant sequences [2023-11-12 02:33:00,686 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1491163256] [2023-11-12 02:33:00,686 INFO L93 rtionOrderModulation]: Changing assertion order to TERMS_WITH_SMALL_CONSTANTS_FIRST [2023-11-12 02:33:00,686 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2023-11-12 02:33:00,687 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1deda2bf-224c-4242-8866-e899ae47e0d0/bin/uautomizer-verify-uTZkv6EMXl/z3 [2023-11-12 02:33:00,692 INFO L229 MonitoredProcess]: Starting monitored process 40 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1deda2bf-224c-4242-8866-e899ae47e0d0/bin/uautomizer-verify-uTZkv6EMXl/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2023-11-12 02:33:00,718 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1deda2bf-224c-4242-8866-e899ae47e0d0/bin/uautomizer-verify-uTZkv6EMXl/z3 -smt2 -in SMTLIB2_COMPLIANT=true (40)] Waiting until timeout for monitored process [2023-11-12 02:33:00,817 INFO L228 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2023-11-12 02:33:00,817 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2023-11-12 02:33:00,820 INFO L262 TraceCheckSpWp]: Trace formula consists of 489 conjuncts, 28 conjunts are in the unsatisfiable core [2023-11-12 02:33:00,825 INFO L285 TraceCheckSpWp]: Computing forward predicates... [2023-11-12 02:33:01,565 INFO L134 CoverageAnalysis]: Checked inductivity of 8932 backedges. 914 proven. 6638 refuted. 0 times theorem prover too weak. 1380 trivial. 0 not checked. [2023-11-12 02:33:01,565 INFO L327 TraceCheckSpWp]: Computing backward predicates... [2023-11-12 02:33:02,322 INFO L134 CoverageAnalysis]: Checked inductivity of 8932 backedges. 914 proven. 6638 refuted. 0 times theorem prover too weak. 1380 trivial. 0 not checked. [2023-11-12 02:33:02,322 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1491163256] provided 0 perfect and 2 imperfect interpolant sequences [2023-11-12 02:33:02,323 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2023-11-12 02:33:02,323 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [9, 28, 28] total 50 [2023-11-12 02:33:02,323 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1662359390] [2023-11-12 02:33:02,323 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2023-11-12 02:33:02,324 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-12 02:33:02,325 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-12 02:33:02,325 INFO L85 PathProgramCache]: Analyzing trace with hash 1324, now seen corresponding path program 7 times [2023-11-12 02:33:02,325 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-12 02:33:02,325 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [180623884] [2023-11-12 02:33:02,325 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-12 02:33:02,325 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-12 02:33:02,327 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-12 02:33:02,328 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-12 02:33:02,328 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-12 02:33:02,329 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-12 02:33:02,347 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-12 02:33:02,348 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 50 interpolants. [2023-11-12 02:33:02,349 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=683, Invalid=1767, Unknown=0, NotChecked=0, Total=2450 [2023-11-12 02:33:02,349 INFO L87 Difference]: Start difference. First operand 257 states and 272 transitions. cyclomatic complexity: 23 Second operand has 50 states, 50 states have (on average 3.18) internal successors, (159), 50 states have internal predecessors, (159), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-12 02:33:05,496 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-12 02:33:05,496 INFO L93 Difference]: Finished difference Result 1240 states and 1416 transitions. [2023-11-12 02:33:05,496 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1240 states and 1416 transitions. [2023-11-12 02:33:05,506 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2023-11-12 02:33:05,514 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1240 states to 987 states and 1104 transitions. [2023-11-12 02:33:05,515 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 25 [2023-11-12 02:33:05,515 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 25 [2023-11-12 02:33:05,515 INFO L73 IsDeterministic]: Start isDeterministic. Operand 987 states and 1104 transitions. [2023-11-12 02:33:05,515 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2023-11-12 02:33:05,515 INFO L218 hiAutomatonCegarLoop]: Abstraction has 987 states and 1104 transitions. [2023-11-12 02:33:05,516 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 987 states and 1104 transitions. [2023-11-12 02:33:05,527 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 987 to 691. [2023-11-12 02:33:05,528 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 691 states, 691 states have (on average 1.1128798842257597) internal successors, (769), 690 states have internal predecessors, (769), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-12 02:33:05,531 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 691 states to 691 states and 769 transitions. [2023-11-12 02:33:05,531 INFO L240 hiAutomatonCegarLoop]: Abstraction has 691 states and 769 transitions. [2023-11-12 02:33:05,532 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 149 states. [2023-11-12 02:33:05,532 INFO L428 stractBuchiCegarLoop]: Abstraction has 691 states and 769 transitions. [2023-11-12 02:33:05,532 INFO L335 stractBuchiCegarLoop]: ======== Iteration 13 ============ [2023-11-12 02:33:05,532 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 691 states and 769 transitions. [2023-11-12 02:33:05,536 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2023-11-12 02:33:05,537 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-12 02:33:05,537 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-12 02:33:05,541 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [95, 94, 83, 11, 1, 1, 1] [2023-11-12 02:33:05,541 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1] [2023-11-12 02:33:05,542 INFO L748 eck$LassoCheckResult]: Stem: 10155#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true; 10156#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet0#1, main_~i~0#1, main_~range~0#1;havoc main_~i~0#1;havoc main_~range~0#1;havoc main_#t~nondet0#1;main_~i~0#1 := main_#t~nondet0#1;havoc main_#t~nondet0#1;main_~range~0#1 := 20; 10150#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 10152#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 10157#L13 assume main_~i~0#1 == main_~range~0#1;main_~i~0#1 := 0;main_~range~0#1 := main_~range~0#1 - 1; 10569#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 10568#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 10567#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 10566#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 10565#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 10564#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 10563#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 10562#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 10561#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 10560#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 10559#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 10558#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 10557#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 10556#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 10555#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 10554#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 10553#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 10552#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 10551#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 10550#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 10549#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 10548#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 10547#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 10546#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 10545#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 10544#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 10543#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 10542#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 10541#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 10540#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 10539#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 10538#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 10537#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 10536#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 10535#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 10534#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 10533#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 10532#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 10531#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 10530#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 10529#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 10528#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 10527#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 10526#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 10525#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 10524#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 10523#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 10522#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 10521#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 10520#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 10519#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 10518#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 10517#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 10516#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 10515#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 10512#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 10513#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 10511#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 10510#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 10509#L13 assume main_~i~0#1 == main_~range~0#1;main_~i~0#1 := 0;main_~range~0#1 := main_~range~0#1 - 1; 10508#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 10507#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 10506#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 10505#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 10504#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 10503#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 10502#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 10501#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 10500#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 10499#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 10498#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 10497#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 10496#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 10495#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 10494#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 10493#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 10492#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 10491#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 10490#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 10489#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 10488#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 10487#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 10486#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 10485#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 10484#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 10483#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 10482#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 10481#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 10480#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 10479#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 10478#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 10477#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 10476#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 10475#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 10474#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 10473#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 10472#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 10471#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 10470#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 10469#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 10468#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 10467#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 10466#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 10465#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 10464#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 10463#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 10462#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 10461#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 10460#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 10459#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 10458#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 10457#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 10456#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 10455#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 10453#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 10452#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 10451#L13 assume main_~i~0#1 == main_~range~0#1;main_~i~0#1 := 0;main_~range~0#1 := main_~range~0#1 - 1; 10450#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 10449#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 10448#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 10447#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 10446#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 10445#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 10444#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 10443#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 10442#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 10441#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 10440#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 10439#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 10438#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 10437#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 10436#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 10435#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 10434#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 10433#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 10432#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 10431#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 10430#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 10429#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 10428#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 10427#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 10426#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 10425#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 10424#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 10423#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 10422#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 10421#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 10420#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 10419#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 10418#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 10417#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 10416#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 10415#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 10414#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 10413#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 10412#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 10411#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 10410#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 10409#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 10408#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 10407#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 10406#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 10405#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 10404#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 10403#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 10402#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 10401#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 10400#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 10398#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 10397#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 10396#L13 assume main_~i~0#1 == main_~range~0#1;main_~i~0#1 := 0;main_~range~0#1 := main_~range~0#1 - 1; 10395#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 10394#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 10393#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 10392#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 10391#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 10390#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 10389#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 10388#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 10387#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 10386#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 10385#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 10384#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 10383#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 10382#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 10381#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 10380#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 10379#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 10378#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 10376#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 10374#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 10372#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 10370#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 10368#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 10366#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 10364#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 10362#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 10360#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 10358#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 10356#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 10354#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 10352#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 10350#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 10348#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 10346#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 10344#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 10342#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 10320#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 10321#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 10338#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 10336#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 10334#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 10314#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 10312#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 10313#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 10308#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 10309#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 10270#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 10324#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 10301#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 10300#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 10299#L13 assume main_~i~0#1 == main_~range~0#1;main_~i~0#1 := 0;main_~range~0#1 := main_~range~0#1 - 1; 10298#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 10297#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 10264#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 10261#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 10258#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 10255#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 10252#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 10250#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 10248#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 10246#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 10245#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 10244#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 10243#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 10231#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 10225#L13 assume main_~i~0#1 == main_~range~0#1;main_~i~0#1 := 0;main_~range~0#1 := main_~range~0#1 - 1; 10224#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 10223#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 10222#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 10220#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 10221#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 10230#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 10219#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 10213#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 10211#L13 assume main_~i~0#1 == main_~range~0#1;main_~i~0#1 := 0;main_~range~0#1 := main_~range~0#1 - 1; 10210#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 10209#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 10208#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 10205#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 10203#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 10204#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 10206#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 10198#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 10197#L13 assume main_~i~0#1 == main_~range~0#1;main_~i~0#1 := 0;main_~range~0#1 := main_~range~0#1 - 1; 10196#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 10195#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 10193#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 10190#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 10191#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 10194#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 10192#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 10186#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 10185#L13 assume main_~i~0#1 == main_~range~0#1;main_~i~0#1 := 0;main_~range~0#1 := main_~range~0#1 - 1; 10184#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 10183#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 10182#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 10181#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 10168#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 10180#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 10178#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 10177#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 10173#L13 assume main_~i~0#1 == main_~range~0#1;main_~i~0#1 := 0;main_~range~0#1 := main_~range~0#1 - 1; 10174#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 10170#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 10166#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 10167#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 10164#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 10161#L13 assume main_~i~0#1 == main_~range~0#1;main_~i~0#1 := 0;main_~range~0#1 := main_~range~0#1 - 1; 10163#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 10158#L12 assume !!(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 10159#L12-1 [2023-11-12 02:33:05,542 INFO L750 eck$LassoCheckResult]: Loop: 10159#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 10162#L12 assume !!(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 10159#L12-1 [2023-11-12 02:33:05,542 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-12 02:33:05,543 INFO L85 PathProgramCache]: Analyzing trace with hash 2005033964, now seen corresponding path program 5 times [2023-11-12 02:33:05,543 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-12 02:33:05,543 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [274613888] [2023-11-12 02:33:05,543 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-12 02:33:05,543 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-12 02:33:05,628 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-12 02:33:06,520 INFO L134 CoverageAnalysis]: Checked inductivity of 13301 backedges. 5787 proven. 5686 refuted. 0 times theorem prover too weak. 1828 trivial. 0 not checked. [2023-11-12 02:33:06,520 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-12 02:33:06,520 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [274613888] [2023-11-12 02:33:06,520 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [274613888] provided 0 perfect and 1 imperfect interpolant sequences [2023-11-12 02:33:06,521 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1144942702] [2023-11-12 02:33:06,521 INFO L93 rtionOrderModulation]: Changing assertion order to INSIDE_LOOP_FIRST1 [2023-11-12 02:33:06,521 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2023-11-12 02:33:06,521 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1deda2bf-224c-4242-8866-e899ae47e0d0/bin/uautomizer-verify-uTZkv6EMXl/z3 [2023-11-12 02:33:06,529 INFO L229 MonitoredProcess]: Starting monitored process 41 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1deda2bf-224c-4242-8866-e899ae47e0d0/bin/uautomizer-verify-uTZkv6EMXl/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2023-11-12 02:33:06,549 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1deda2bf-224c-4242-8866-e899ae47e0d0/bin/uautomizer-verify-uTZkv6EMXl/z3 -smt2 -in SMTLIB2_COMPLIANT=true (41)] Waiting until timeout for monitored process [2023-11-12 02:33:06,755 INFO L228 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 73 check-sat command(s) [2023-11-12 02:33:06,755 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2023-11-12 02:33:06,759 INFO L262 TraceCheckSpWp]: Trace formula consists of 455 conjuncts, 25 conjunts are in the unsatisfiable core [2023-11-12 02:33:06,764 INFO L285 TraceCheckSpWp]: Computing forward predicates... [2023-11-12 02:33:07,169 INFO L134 CoverageAnalysis]: Checked inductivity of 13301 backedges. 7724 proven. 317 refuted. 0 times theorem prover too weak. 5260 trivial. 0 not checked. [2023-11-12 02:33:07,170 INFO L327 TraceCheckSpWp]: Computing backward predicates... [2023-11-12 02:33:07,574 INFO L134 CoverageAnalysis]: Checked inductivity of 13301 backedges. 7724 proven. 317 refuted. 0 times theorem prover too weak. 5260 trivial. 0 not checked. [2023-11-12 02:33:07,574 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1144942702] provided 0 perfect and 2 imperfect interpolant sequences [2023-11-12 02:33:07,574 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2023-11-12 02:33:07,575 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [21, 25, 25] total 44 [2023-11-12 02:33:07,575 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1674595234] [2023-11-12 02:33:07,575 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2023-11-12 02:33:07,576 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-12 02:33:07,576 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-12 02:33:07,576 INFO L85 PathProgramCache]: Analyzing trace with hash 1324, now seen corresponding path program 8 times [2023-11-12 02:33:07,576 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-12 02:33:07,576 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1113419513] [2023-11-12 02:33:07,576 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-12 02:33:07,576 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-12 02:33:07,580 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-12 02:33:07,580 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-12 02:33:07,581 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-12 02:33:07,581 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-12 02:33:07,597 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-12 02:33:07,597 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 44 interpolants. [2023-11-12 02:33:07,598 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=511, Invalid=1381, Unknown=0, NotChecked=0, Total=1892 [2023-11-12 02:33:07,598 INFO L87 Difference]: Start difference. First operand 691 states and 769 transitions. cyclomatic complexity: 85 Second operand has 44 states, 44 states have (on average 3.25) internal successors, (143), 44 states have internal predecessors, (143), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-12 02:33:09,435 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-12 02:33:09,435 INFO L93 Difference]: Finished difference Result 1294 states and 1395 transitions. [2023-11-12 02:33:09,436 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1294 states and 1395 transitions. [2023-11-12 02:33:09,445 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2023-11-12 02:33:09,453 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1294 states to 1184 states and 1285 transitions. [2023-11-12 02:33:09,453 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 22 [2023-11-12 02:33:09,454 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 22 [2023-11-12 02:33:09,454 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1184 states and 1285 transitions. [2023-11-12 02:33:09,454 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2023-11-12 02:33:09,454 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1184 states and 1285 transitions. [2023-11-12 02:33:09,455 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1184 states and 1285 transitions. [2023-11-12 02:33:09,465 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1184 to 526. [2023-11-12 02:33:09,466 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 526 states, 526 states have (on average 1.0874524714828897) internal successors, (572), 525 states have internal predecessors, (572), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-12 02:33:09,468 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 526 states to 526 states and 572 transitions. [2023-11-12 02:33:09,468 INFO L240 hiAutomatonCegarLoop]: Abstraction has 526 states and 572 transitions. [2023-11-12 02:33:09,469 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 96 states. [2023-11-12 02:33:09,469 INFO L428 stractBuchiCegarLoop]: Abstraction has 526 states and 572 transitions. [2023-11-12 02:33:09,469 INFO L335 stractBuchiCegarLoop]: ======== Iteration 14 ============ [2023-11-12 02:33:09,469 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 526 states and 572 transitions. [2023-11-12 02:33:09,472 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2023-11-12 02:33:09,472 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-12 02:33:09,472 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-12 02:33:09,480 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [131, 130, 115, 15, 1, 1, 1] [2023-11-12 02:33:09,480 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1] [2023-11-12 02:33:09,480 INFO L748 eck$LassoCheckResult]: Stem: 14069#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true; 14070#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet0#1, main_~i~0#1, main_~range~0#1;havoc main_~i~0#1;havoc main_~range~0#1;havoc main_#t~nondet0#1;main_~i~0#1 := main_#t~nondet0#1;havoc main_#t~nondet0#1;main_~range~0#1 := 20; 14064#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 14066#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 14071#L13 assume main_~i~0#1 == main_~range~0#1;main_~i~0#1 := 0;main_~range~0#1 := main_~range~0#1 - 1; 14547#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 14546#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 14545#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 14544#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 14543#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 14542#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 14541#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 14540#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 14539#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 14538#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 14537#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 14536#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 14535#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 14534#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 14533#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 14532#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 14531#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 14530#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 14529#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 14528#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 14527#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 14526#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 14525#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 14524#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 14523#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 14522#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 14521#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 14520#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 14519#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 14518#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 14517#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 14516#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 14515#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 14514#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 14513#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 14512#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 14511#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 14510#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 14509#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 14508#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 14507#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 14506#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 14505#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 14504#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 14503#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 14502#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 14501#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 14500#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 14499#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 14498#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 14497#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 14496#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 14495#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 14494#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 14493#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 14491#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 14492#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 14490#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 14489#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 14488#L13 assume main_~i~0#1 == main_~range~0#1;main_~i~0#1 := 0;main_~range~0#1 := main_~range~0#1 - 1; 14487#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 14486#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 14485#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 14484#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 14483#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 14482#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 14481#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 14480#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 14479#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 14478#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 14477#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 14476#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 14475#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 14474#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 14473#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 14472#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 14471#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 14470#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 14469#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 14468#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 14467#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 14466#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 14465#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 14464#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 14463#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 14462#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 14461#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 14460#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 14459#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 14458#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 14457#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 14456#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 14455#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 14454#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 14453#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 14452#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 14451#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 14450#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 14449#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 14448#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 14447#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 14446#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 14445#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 14444#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 14443#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 14442#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 14441#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 14440#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 14439#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 14438#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 14437#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 14436#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 14434#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 14435#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 14433#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 14432#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 14431#L13 assume main_~i~0#1 == main_~range~0#1;main_~i~0#1 := 0;main_~range~0#1 := main_~range~0#1 - 1; 14430#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 14429#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 14428#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 14427#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 14426#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 14425#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 14424#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 14423#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 14422#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 14421#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 14420#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 14419#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 14418#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 14417#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 14416#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 14415#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 14414#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 14413#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 14412#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 14411#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 14410#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 14409#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 14408#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 14407#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 14406#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 14405#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 14404#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 14403#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 14402#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 14401#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 14400#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 14399#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 14398#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 14397#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 14396#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 14395#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 14394#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 14393#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 14392#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 14391#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 14390#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 14389#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 14388#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 14387#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 14386#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 14385#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 14384#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 14383#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 14382#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 14380#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 14381#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 14378#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 14379#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 14587#L13 assume main_~i~0#1 == main_~range~0#1;main_~i~0#1 := 0;main_~range~0#1 := main_~range~0#1 - 1; 14586#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 14585#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 14584#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 14583#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 14582#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 14581#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 14580#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 14579#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 14578#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 14577#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 14576#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 14575#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 14574#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 14573#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 14572#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 14571#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 14570#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 14569#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 14568#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 14567#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 14566#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 14565#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 14564#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 14563#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 14562#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 14561#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 14560#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 14559#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 14556#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 14554#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 14346#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 14345#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 14344#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 14342#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 14343#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 14558#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 14337#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 14338#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 14557#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 14333#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 14332#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 14331#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 14330#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 14329#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 14328#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 14327#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 14267#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 14326#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 14325#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 14319#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 14377#L13 assume main_~i~0#1 == main_~range~0#1;main_~i~0#1 := 0;main_~range~0#1 := main_~range~0#1 - 1; 14376#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 14375#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 14374#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 14373#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 14372#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 14371#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 14370#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 14369#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 14368#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 14367#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 14366#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 14365#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 14364#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 14363#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 14362#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 14361#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 14360#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 14359#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 14358#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 14357#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 14356#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 14355#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 14354#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 14353#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 14352#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 14351#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 14350#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 14349#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 14221#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 14347#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 14348#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 14072#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 14073#L13 assume main_~i~0#1 == main_~range~0#1;main_~i~0#1 := 0;main_~range~0#1 := main_~range~0#1 - 1; 14264#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 14263#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 14262#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 14261#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 14236#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 14235#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 14233#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 14232#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 14231#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 14230#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 14229#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 14227#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 14228#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 14244#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 14222#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 14223#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 14219#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 14218#L13 assume main_~i~0#1 == main_~range~0#1;main_~i~0#1 := 0;main_~range~0#1 := main_~range~0#1 - 1; 14217#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 14216#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 14215#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 14214#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 14213#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 14212#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 14211#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 14210#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 14209#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 14208#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 14202#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 14201#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 14199#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 14197#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 14195#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 14196#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 14192#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 14191#L13 assume main_~i~0#1 == main_~range~0#1;main_~i~0#1 := 0;main_~range~0#1 := main_~range~0#1 - 1; 14190#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 14189#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 14188#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 14187#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 14186#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 14185#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 14184#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 14183#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 14182#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 14181#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 14180#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 14179#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 14175#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 14173#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 14171#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 14172#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 14168#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 14167#L13 assume main_~i~0#1 == main_~range~0#1;main_~i~0#1 := 0;main_~range~0#1 := main_~range~0#1 - 1; 14166#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 14165#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 14164#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 14163#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 14162#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 14161#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 14160#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 14159#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 14158#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 14157#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 14156#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 14155#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 14153#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 14152#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 14150#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 14151#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 14147#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 14146#L13 assume main_~i~0#1 == main_~range~0#1;main_~i~0#1 := 0;main_~range~0#1 := main_~range~0#1 - 1; 14145#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 14144#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 14143#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 14142#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 14141#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 14140#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 14139#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 14138#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 14137#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 14136#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 14135#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 14134#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 14133#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 14116#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 14132#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 14130#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 14129#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 14128#L13 assume main_~i~0#1 == main_~range~0#1;main_~i~0#1 := 0;main_~range~0#1 := main_~range~0#1 - 1; 14127#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 14126#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 14125#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 14124#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 14123#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 14122#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 14121#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 14120#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 14119#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 14118#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 14104#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 14117#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 14115#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 14114#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 14113#L13 assume main_~i~0#1 == main_~range~0#1;main_~i~0#1 := 0;main_~range~0#1 := main_~range~0#1 - 1; 14112#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 14111#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 14110#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 14109#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 14108#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 14107#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 14106#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 14095#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 14105#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 14103#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 14102#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 14101#L13 assume main_~i~0#1 == main_~range~0#1;main_~i~0#1 := 0;main_~range~0#1 := main_~range~0#1 - 1; 14100#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 14099#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 14098#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 14097#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 14084#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 14096#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 14094#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 14093#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 14089#L13 assume main_~i~0#1 == main_~range~0#1;main_~i~0#1 := 0;main_~range~0#1 := main_~range~0#1 - 1; 14090#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 14086#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 14082#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 14083#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 14080#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 14077#L13 assume main_~i~0#1 == main_~range~0#1;main_~i~0#1 := 0;main_~range~0#1 := main_~range~0#1 - 1; 14079#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 14074#L12 assume !!(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 14076#L12-1 [2023-11-12 02:33:09,481 INFO L750 eck$LassoCheckResult]: Loop: 14076#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 14078#L12 assume !!(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 14076#L12-1 [2023-11-12 02:33:09,481 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-12 02:33:09,482 INFO L85 PathProgramCache]: Analyzing trace with hash -1703910940, now seen corresponding path program 6 times [2023-11-12 02:33:09,482 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-12 02:33:09,482 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [963581341] [2023-11-12 02:33:09,482 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-12 02:33:09,482 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-12 02:33:09,584 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-12 02:33:10,977 INFO L134 CoverageAnalysis]: Checked inductivity of 25415 backedges. 12928 proven. 8663 refuted. 0 times theorem prover too weak. 3824 trivial. 0 not checked. [2023-11-12 02:33:10,978 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-12 02:33:10,978 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [963581341] [2023-11-12 02:33:10,978 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [963581341] provided 0 perfect and 1 imperfect interpolant sequences [2023-11-12 02:33:10,978 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1041925910] [2023-11-12 02:33:10,978 INFO L93 rtionOrderModulation]: Changing assertion order to MIX_INSIDE_OUTSIDE [2023-11-12 02:33:10,978 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2023-11-12 02:33:10,978 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1deda2bf-224c-4242-8866-e899ae47e0d0/bin/uautomizer-verify-uTZkv6EMXl/z3 [2023-11-12 02:33:10,985 INFO L229 MonitoredProcess]: Starting monitored process 42 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1deda2bf-224c-4242-8866-e899ae47e0d0/bin/uautomizer-verify-uTZkv6EMXl/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2023-11-12 02:33:10,990 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1deda2bf-224c-4242-8866-e899ae47e0d0/bin/uautomizer-verify-uTZkv6EMXl/z3 -smt2 -in SMTLIB2_COMPLIANT=true (42)] Waiting until timeout for monitored process [2023-11-12 02:33:11,221 INFO L228 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued 81 check-sat command(s) [2023-11-12 02:33:11,221 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2023-11-12 02:33:11,224 INFO L262 TraceCheckSpWp]: Trace formula consists of 521 conjuncts, 15 conjunts are in the unsatisfiable core [2023-11-12 02:33:11,230 INFO L285 TraceCheckSpWp]: Computing forward predicates... [2023-11-12 02:33:11,557 INFO L134 CoverageAnalysis]: Checked inductivity of 25415 backedges. 8831 proven. 411 refuted. 0 times theorem prover too weak. 16173 trivial. 0 not checked. [2023-11-12 02:33:11,557 INFO L327 TraceCheckSpWp]: Computing backward predicates... [2023-11-12 02:33:11,918 INFO L134 CoverageAnalysis]: Checked inductivity of 25415 backedges. 8831 proven. 411 refuted. 0 times theorem prover too weak. 16173 trivial. 0 not checked. [2023-11-12 02:33:11,918 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1041925910] provided 0 perfect and 2 imperfect interpolant sequences [2023-11-12 02:33:11,919 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2023-11-12 02:33:11,919 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [25, 14, 14] total 37 [2023-11-12 02:33:11,919 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1880997495] [2023-11-12 02:33:11,919 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2023-11-12 02:33:11,921 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-12 02:33:11,922 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-12 02:33:11,922 INFO L85 PathProgramCache]: Analyzing trace with hash 1324, now seen corresponding path program 9 times [2023-11-12 02:33:11,922 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-12 02:33:11,922 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [730416352] [2023-11-12 02:33:11,922 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-12 02:33:11,923 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-12 02:33:11,925 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-12 02:33:11,926 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-12 02:33:11,926 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-12 02:33:11,927 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-12 02:33:11,942 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-12 02:33:11,942 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 37 interpolants. [2023-11-12 02:33:11,943 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=192, Invalid=1140, Unknown=0, NotChecked=0, Total=1332 [2023-11-12 02:33:11,943 INFO L87 Difference]: Start difference. First operand 526 states and 572 transitions. cyclomatic complexity: 53 Second operand has 37 states, 37 states have (on average 3.324324324324324) internal successors, (123), 37 states have internal predecessors, (123), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-12 02:33:14,191 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-12 02:33:14,192 INFO L93 Difference]: Finished difference Result 686 states and 729 transitions. [2023-11-12 02:33:14,192 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 686 states and 729 transitions. [2023-11-12 02:33:14,196 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2023-11-12 02:33:14,200 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 686 states to 635 states and 675 transitions. [2023-11-12 02:33:14,200 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 17 [2023-11-12 02:33:14,201 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 63 [2023-11-12 02:33:14,201 INFO L73 IsDeterministic]: Start isDeterministic. Operand 635 states and 675 transitions. [2023-11-12 02:33:14,201 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2023-11-12 02:33:14,201 INFO L218 hiAutomatonCegarLoop]: Abstraction has 635 states and 675 transitions. [2023-11-12 02:33:14,202 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 635 states and 675 transitions. [2023-11-12 02:33:14,208 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 635 to 427. [2023-11-12 02:33:14,208 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 427 states, 427 states have (on average 1.0281030444964872) internal successors, (439), 426 states have internal predecessors, (439), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-12 02:33:14,210 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 427 states to 427 states and 439 transitions. [2023-11-12 02:33:14,210 INFO L240 hiAutomatonCegarLoop]: Abstraction has 427 states and 439 transitions. [2023-11-12 02:33:14,210 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 92 states. [2023-11-12 02:33:14,211 INFO L428 stractBuchiCegarLoop]: Abstraction has 427 states and 439 transitions. [2023-11-12 02:33:14,211 INFO L335 stractBuchiCegarLoop]: ======== Iteration 15 ============ [2023-11-12 02:33:14,211 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 427 states and 439 transitions. [2023-11-12 02:33:14,213 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2023-11-12 02:33:14,213 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-12 02:33:14,214 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-12 02:33:14,221 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [140, 140, 125, 15, 1, 1] [2023-11-12 02:33:14,222 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1] [2023-11-12 02:33:14,222 INFO L748 eck$LassoCheckResult]: Stem: 17857#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true; 17858#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet0#1, main_~i~0#1, main_~range~0#1;havoc main_~i~0#1;havoc main_~range~0#1;havoc main_#t~nondet0#1;main_~i~0#1 := main_#t~nondet0#1;havoc main_#t~nondet0#1;main_~range~0#1 := 20; 17849#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 17851#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 17859#L13 assume main_~i~0#1 == main_~range~0#1;main_~i~0#1 := 0;main_~range~0#1 := main_~range~0#1 - 1; 18275#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 17860#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 17856#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 17852#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 17853#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 18274#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 18273#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 18272#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 18271#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 18270#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 18269#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 18268#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 18267#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 18266#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 18265#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 18264#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 18263#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 18262#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 18261#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 18260#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 18259#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 18258#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 18257#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 18256#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 18255#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 18254#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 18253#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 18252#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 18251#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 18250#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 18249#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 18248#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 18247#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 18246#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 18245#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 18244#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 18243#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 18242#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 18241#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 18240#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 18239#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 18238#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 18237#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 18236#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 18235#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 18234#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 18233#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 18232#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 18231#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 18230#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 18229#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 18228#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 18227#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 18226#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 18225#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 18223#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 18224#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 18222#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 18221#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 18220#L13 assume main_~i~0#1 == main_~range~0#1;main_~i~0#1 := 0;main_~range~0#1 := main_~range~0#1 - 1; 18219#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 18218#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 18217#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 18216#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 18215#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 18214#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 18213#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 18212#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 18211#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 18210#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 18209#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 18208#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 18207#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 18206#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 18205#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 18204#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 18203#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 18202#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 18201#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 18200#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 18199#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 18198#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 18197#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 18196#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 18195#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 18194#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 18193#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 18192#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 18191#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 18190#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 18189#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 18188#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 18187#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 18186#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 18185#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 18184#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 18183#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 18182#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 18181#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 18180#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 18179#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 18178#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 18177#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 18176#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 18175#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 18174#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 18173#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 18172#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 18171#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 18170#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 18169#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 18168#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 18166#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 18167#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 18165#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 18164#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 18163#L13 assume main_~i~0#1 == main_~range~0#1;main_~i~0#1 := 0;main_~range~0#1 := main_~range~0#1 - 1; 18162#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 18161#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 18160#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 18159#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 18158#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 18157#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 18156#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 18155#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 18154#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 18153#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 18152#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 18151#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 18150#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 18149#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 18148#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 18147#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 18146#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 18145#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 18144#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 18143#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 18142#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 18141#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 18140#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 18139#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 18138#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 18137#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 18136#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 18135#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 18134#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 18133#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 18132#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 18131#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 18130#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 18129#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 18128#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 18127#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 18126#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 18125#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 18124#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 18123#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 18122#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 18121#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 18120#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 18119#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 18118#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 18117#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 18116#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 18115#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 18114#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 18112#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 18113#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 18111#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 18110#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 18109#L13 assume main_~i~0#1 == main_~range~0#1;main_~i~0#1 := 0;main_~range~0#1 := main_~range~0#1 - 1; 18108#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 18107#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 18106#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 18105#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 18104#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 18103#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 18102#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 18101#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 18100#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 18099#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 18098#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 18097#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 18096#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 18095#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 18094#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 18093#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 18092#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 18091#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 18090#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 18089#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 18088#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 18087#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 18086#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 18085#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 18084#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 18083#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 18082#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 18081#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 18080#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 18079#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 18078#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 18077#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 18076#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 18075#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 18074#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 18073#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 18072#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 18071#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 18070#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 18069#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 18068#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 18067#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 18066#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 18065#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 18064#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 18063#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 17985#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 18062#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 18059#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 18058#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 18057#L13 assume main_~i~0#1 == main_~range~0#1;main_~i~0#1 := 0;main_~range~0#1 := main_~range~0#1 - 1; 18056#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 18055#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 18054#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 18053#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 18052#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 18051#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 18050#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 18049#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 18048#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 18047#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 18046#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 18045#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 18044#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 18043#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 18042#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 18041#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 18040#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 18039#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 18038#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 18037#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 18036#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 18035#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 18034#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 18033#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 18032#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 18031#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 18030#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 18029#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 17955#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 18028#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 17984#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 17983#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 17982#L13 assume main_~i~0#1 == main_~range~0#1;main_~i~0#1 := 0;main_~range~0#1 := main_~range~0#1 - 1; 17981#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 17980#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 17979#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 17978#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 17977#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 17976#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 17975#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 17974#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 17973#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 17972#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 17971#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 17970#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 17969#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 17968#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 17967#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 17966#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 17965#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 17964#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 17963#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 17962#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 17961#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 17960#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 17959#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 17958#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 17957#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 17928#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 17956#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 17954#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 17953#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 17952#L13 assume main_~i~0#1 == main_~range~0#1;main_~i~0#1 := 0;main_~range~0#1 := main_~range~0#1 - 1; 17951#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 17950#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 17949#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 17948#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 17947#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 17946#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 17945#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 17944#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 17943#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 17942#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 17941#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 17940#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 17939#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 17938#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 17937#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 17936#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 17935#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 17934#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 17933#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 17932#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 17931#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 17930#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 17904#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 17929#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 17927#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 17926#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 17925#L13 assume main_~i~0#1 == main_~range~0#1;main_~i~0#1 := 0;main_~range~0#1 := main_~range~0#1 - 1; 17924#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 17923#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 17922#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 17921#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 17920#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 17919#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 17918#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 17917#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 17916#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 17915#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 17914#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 17913#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 17912#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 17911#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 17910#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 17909#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 17908#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 17907#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 17906#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 17883#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 17905#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 17903#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 17902#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 17901#L13 assume main_~i~0#1 == main_~range~0#1;main_~i~0#1 := 0;main_~range~0#1 := main_~range~0#1 - 1; 17900#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 17899#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 17898#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 17897#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 17896#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 17895#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 17894#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 17893#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 17892#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 17891#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 17890#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 17889#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 17888#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 17887#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 17886#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 17885#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 17864#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 17884#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 17882#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 17881#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 17880#L13 assume main_~i~0#1 == main_~range~0#1;main_~i~0#1 := 0;main_~range~0#1 := main_~range~0#1 - 1; 17879#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 17878#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 17877#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 17876#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 17875#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 17874#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 17873#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 17872#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 17871#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 17870#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 17869#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 17868#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 17867#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 17866#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 17865#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 17863#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 17861#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 17854#L13 assume main_~i~0#1 == main_~range~0#1;main_~i~0#1 := 0;main_~range~0#1 := main_~range~0#1 - 1; 17855#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 17862#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 18027#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 18026#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 18025#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 18024#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 18023#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 18022#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 18021#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 18020#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 18019#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 18018#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 18017#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 18016#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 18015#L13 assume main_~i~0#1 == main_~range~0#1;main_~i~0#1 := 0;main_~range~0#1 := main_~range~0#1 - 1; 18014#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 18013#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 18012#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 18011#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 18010#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 18009#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 18008#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 18007#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 18006#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 18005#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 18004#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 18003#L13 assume main_~i~0#1 == main_~range~0#1;main_~i~0#1 := 0;main_~range~0#1 := main_~range~0#1 - 1; 18002#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 18001#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 18000#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 17999#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 17998#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 17997#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 17996#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 17995#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 17994#L13 assume main_~i~0#1 == main_~range~0#1;main_~i~0#1 := 0;main_~range~0#1 := main_~range~0#1 - 1; 17993#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 17992#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 17991#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 17990#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 17989#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 17986#L13 assume main_~i~0#1 == main_~range~0#1;main_~i~0#1 := 0;main_~range~0#1 := main_~range~0#1 - 1; 17987#L12-1 [2023-11-12 02:33:14,223 INFO L750 eck$LassoCheckResult]: Loop: 17987#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 17988#L12 assume !!(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 17987#L12-1 [2023-11-12 02:33:14,223 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-12 02:33:14,223 INFO L85 PathProgramCache]: Analyzing trace with hash -1848898559, now seen corresponding path program 9 times [2023-11-12 02:33:14,224 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-12 02:33:14,224 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [558976570] [2023-11-12 02:33:14,224 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-12 02:33:14,224 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-12 02:33:14,344 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-12 02:33:15,192 INFO L134 CoverageAnalysis]: Checked inductivity of 29190 backedges. 13932 proven. 9015 refuted. 0 times theorem prover too weak. 6243 trivial. 0 not checked. [2023-11-12 02:33:15,193 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-12 02:33:15,193 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [558976570] [2023-11-12 02:33:15,193 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [558976570] provided 0 perfect and 1 imperfect interpolant sequences [2023-11-12 02:33:15,193 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [985907578] [2023-11-12 02:33:15,193 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 [2023-11-12 02:33:15,194 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2023-11-12 02:33:15,194 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1deda2bf-224c-4242-8866-e899ae47e0d0/bin/uautomizer-verify-uTZkv6EMXl/z3 [2023-11-12 02:33:15,200 INFO L229 MonitoredProcess]: Starting monitored process 43 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1deda2bf-224c-4242-8866-e899ae47e0d0/bin/uautomizer-verify-uTZkv6EMXl/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2023-11-12 02:33:15,217 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1deda2bf-224c-4242-8866-e899ae47e0d0/bin/uautomizer-verify-uTZkv6EMXl/z3 -smt2 -in SMTLIB2_COMPLIANT=true (43)] Waiting until timeout for monitored process [2023-11-12 02:33:15,616 INFO L228 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 117 check-sat command(s) [2023-11-12 02:33:15,616 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2023-11-12 02:33:15,620 INFO L262 TraceCheckSpWp]: Trace formula consists of 746 conjuncts, 27 conjunts are in the unsatisfiable core [2023-11-12 02:33:15,627 INFO L285 TraceCheckSpWp]: Computing forward predicates... [2023-11-12 02:33:16,517 INFO L134 CoverageAnalysis]: Checked inductivity of 29190 backedges. 14745 proven. 8053 refuted. 0 times theorem prover too weak. 6392 trivial. 0 not checked. [2023-11-12 02:33:16,517 INFO L327 TraceCheckSpWp]: Computing backward predicates... [2023-11-12 02:33:17,392 INFO L134 CoverageAnalysis]: Checked inductivity of 29190 backedges. 14745 proven. 8053 refuted. 0 times theorem prover too weak. 6392 trivial. 0 not checked. [2023-11-12 02:33:17,392 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [985907578] provided 0 perfect and 2 imperfect interpolant sequences [2023-11-12 02:33:17,393 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2023-11-12 02:33:17,393 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [18, 25, 25] total 44 [2023-11-12 02:33:17,393 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1564232253] [2023-11-12 02:33:17,393 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2023-11-12 02:33:17,395 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-12 02:33:17,395 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-12 02:33:17,395 INFO L85 PathProgramCache]: Analyzing trace with hash 1324, now seen corresponding path program 10 times [2023-11-12 02:33:17,395 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-12 02:33:17,396 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [318710490] [2023-11-12 02:33:17,396 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-12 02:33:17,396 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-12 02:33:17,398 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-12 02:33:17,398 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-12 02:33:17,399 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-12 02:33:17,400 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-12 02:33:17,417 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-12 02:33:17,418 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 44 interpolants. [2023-11-12 02:33:17,419 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=336, Invalid=1556, Unknown=0, NotChecked=0, Total=1892 [2023-11-12 02:33:17,419 INFO L87 Difference]: Start difference. First operand 427 states and 439 transitions. cyclomatic complexity: 18 Second operand has 44 states, 44 states have (on average 3.4318181818181817) internal successors, (151), 44 states have internal predecessors, (151), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-12 02:33:22,872 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-12 02:33:22,872 INFO L93 Difference]: Finished difference Result 741 states and 777 transitions. [2023-11-12 02:33:22,872 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 741 states and 777 transitions. [2023-11-12 02:33:22,880 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2023-11-12 02:33:22,885 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 741 states to 706 states and 742 transitions. [2023-11-12 02:33:22,885 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 62 [2023-11-12 02:33:22,885 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 62 [2023-11-12 02:33:22,885 INFO L73 IsDeterministic]: Start isDeterministic. Operand 706 states and 742 transitions. [2023-11-12 02:33:22,885 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2023-11-12 02:33:22,886 INFO L218 hiAutomatonCegarLoop]: Abstraction has 706 states and 742 transitions. [2023-11-12 02:33:22,886 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 706 states and 742 transitions. [2023-11-12 02:33:22,894 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 706 to 607. [2023-11-12 02:33:22,895 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 607 states, 607 states have (on average 1.031301482701812) internal successors, (626), 606 states have internal predecessors, (626), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-12 02:33:22,897 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 607 states to 607 states and 626 transitions. [2023-11-12 02:33:22,897 INFO L240 hiAutomatonCegarLoop]: Abstraction has 607 states and 626 transitions. [2023-11-12 02:33:22,897 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 177 states. [2023-11-12 02:33:22,898 INFO L428 stractBuchiCegarLoop]: Abstraction has 607 states and 626 transitions. [2023-11-12 02:33:22,898 INFO L335 stractBuchiCegarLoop]: ======== Iteration 16 ============ [2023-11-12 02:33:22,898 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 607 states and 626 transitions. [2023-11-12 02:33:22,901 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2023-11-12 02:33:22,902 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-12 02:33:22,902 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-12 02:33:22,913 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [161, 161, 144, 17, 1, 1] [2023-11-12 02:33:22,913 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1] [2023-11-12 02:33:22,914 INFO L748 eck$LassoCheckResult]: Stem: 21939#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true; 21940#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet0#1, main_~i~0#1, main_~range~0#1;havoc main_~i~0#1;havoc main_~range~0#1;havoc main_#t~nondet0#1;main_~i~0#1 := main_#t~nondet0#1;havoc main_#t~nondet0#1;main_~range~0#1 := 20; 21932#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 21934#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 21941#L13 assume main_~i~0#1 == main_~range~0#1;main_~i~0#1 := 0;main_~range~0#1 := main_~range~0#1 - 1; 22538#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 22537#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 22536#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 22535#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 22534#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 22533#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 22532#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 22531#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 22530#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 22529#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 22528#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 22527#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 22526#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 22525#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 22524#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 22523#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 22522#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 22521#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 22520#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 22519#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 22518#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 22517#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 22516#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 22515#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 22514#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 22513#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 22512#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 22511#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 22510#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 22509#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 22508#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 22507#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 22506#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 22505#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 22504#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 22503#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 22502#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 22501#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 22500#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 22499#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 22498#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 22497#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 22496#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 22495#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 22494#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 22493#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 22492#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 22491#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 22490#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 22489#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 22488#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 22487#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 22486#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 22485#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 22484#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 22482#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 22483#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 22481#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 22480#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 22479#L13 assume main_~i~0#1 == main_~range~0#1;main_~i~0#1 := 0;main_~range~0#1 := main_~range~0#1 - 1; 22478#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 22477#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 22476#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 22475#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 22474#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 22473#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 22472#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 22471#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 22470#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 22469#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 22468#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 22467#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 22466#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 22465#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 22464#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 22463#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 22462#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 22461#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 22460#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 22459#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 22458#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 22457#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 22456#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 22455#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 22454#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 22453#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 22452#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 22451#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 22450#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 22449#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 22448#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 22447#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 22446#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 22445#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 22444#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 22443#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 22442#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 22441#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 22440#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 22439#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 22438#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 22437#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 22436#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 22435#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 22434#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 22433#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 22432#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 22431#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 22430#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 22429#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 22428#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 22427#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 22425#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 22426#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 22424#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 22423#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 22422#L13 assume main_~i~0#1 == main_~range~0#1;main_~i~0#1 := 0;main_~range~0#1 := main_~range~0#1 - 1; 22421#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 22420#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 22419#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 22418#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 22417#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 22416#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 22415#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 22414#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 22413#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 22412#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 22411#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 22410#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 22409#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 22408#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 22407#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 22406#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 22405#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 22404#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 22403#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 22402#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 22401#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 22400#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 22399#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 22398#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 22397#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 22396#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 22395#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 22394#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 22393#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 22392#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 22391#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 22390#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 22389#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 22388#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 22387#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 22386#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 22385#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 22384#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 22383#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 22382#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 22381#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 22380#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 22379#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 22378#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 22377#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 22376#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 22375#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 22374#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 22373#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 22371#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 22372#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 22370#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 22369#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 22368#L13 assume main_~i~0#1 == main_~range~0#1;main_~i~0#1 := 0;main_~range~0#1 := main_~range~0#1 - 1; 22367#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 22366#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 22365#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 22364#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 22363#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 22362#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 22361#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 22360#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 22359#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 22358#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 22357#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 22356#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 22355#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 22354#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 22353#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 22352#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 22351#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 22350#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 22349#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 22348#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 22347#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 22346#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 22345#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 22344#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 22343#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 22342#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 22341#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 22340#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 22339#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 22338#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 22337#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 22336#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 22335#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 22334#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 22333#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 22332#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 22331#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 22330#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 22329#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 22328#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 22327#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 22326#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 22325#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 22324#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 22323#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 22322#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 22320#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 22321#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 22319#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 22318#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 22317#L13 assume main_~i~0#1 == main_~range~0#1;main_~i~0#1 := 0;main_~range~0#1 := main_~range~0#1 - 1; 22316#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 22315#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 22314#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 22313#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 22312#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 22311#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 22310#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 22309#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 22308#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 22307#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 22306#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 22305#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 22304#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 22303#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 22302#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 22301#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 22300#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 22299#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 22298#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 22297#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 22296#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 22295#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 22294#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 22293#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 22292#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 22291#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 22290#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 22289#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 22288#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 22287#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 22286#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 22285#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 22284#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 22283#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 22282#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 22281#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 22280#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 22190#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 22191#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 22189#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 22188#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 22187#L13 assume main_~i~0#1 == main_~range~0#1;main_~i~0#1 := 0;main_~range~0#1 := main_~range~0#1 - 1; 22186#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 22185#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 22184#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 22183#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 22182#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 22181#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 22180#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 22179#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 22178#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 22177#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 22176#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 22175#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 22174#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 22173#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 22172#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 22171#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 22170#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 22169#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 22168#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 22167#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 22166#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 22165#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 22164#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 22163#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 22162#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 22161#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 22160#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 22159#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 22158#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 22157#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 22155#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 22154#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 22153#L13 assume main_~i~0#1 == main_~range~0#1;main_~i~0#1 := 0;main_~range~0#1 := main_~range~0#1 - 1; 22152#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 22151#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 22150#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 22149#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 22148#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 22147#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 22146#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 22145#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 22144#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 22143#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 22142#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 22141#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 22140#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 22139#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 22138#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 22137#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 22136#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 22135#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 22134#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 22133#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 22132#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 22131#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 22130#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 22129#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 22128#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 22127#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 22126#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 22124#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 22123#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 22122#L13 assume main_~i~0#1 == main_~range~0#1;main_~i~0#1 := 0;main_~range~0#1 := main_~range~0#1 - 1; 22121#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 22120#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 22119#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 22118#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 22117#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 22116#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 22115#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 22114#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 22113#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 22112#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 22111#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 22110#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 22109#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 22108#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 22107#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 22106#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 22105#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 22104#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 22103#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 22102#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 22101#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 22100#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 22099#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 22098#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 22097#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 22096#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 22095#L13 assume main_~i~0#1 == main_~range~0#1;main_~i~0#1 := 0;main_~range~0#1 := main_~range~0#1 - 1; 22094#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 22093#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 22092#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 22091#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 22090#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 22089#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 22088#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 22087#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 22086#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 22085#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 22084#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 22083#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 22082#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 22081#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 22080#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 22079#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 22078#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 22077#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 22074#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 22072#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 22070#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 22068#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 22066#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 22064#L13 assume main_~i~0#1 == main_~range~0#1;main_~i~0#1 := 0;main_~range~0#1 := main_~range~0#1 - 1; 22062#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 22060#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 22058#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 22056#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 22054#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 22052#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 22050#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 22048#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 22046#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 22044#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 22042#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 22040#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 22038#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 22036#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 22034#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 22033#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 22032#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 22031#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 22030#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 22025#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 22024#L13 assume main_~i~0#1 == main_~range~0#1;main_~i~0#1 := 0;main_~range~0#1 := main_~range~0#1 - 1; 22023#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 22022#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 22021#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 22020#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 22019#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 22018#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 22017#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 22016#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 22015#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 22014#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 22013#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 22012#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 22011#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 22010#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 22009#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 22008#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 21945#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 22007#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 21963#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 21962#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 21961#L13 assume main_~i~0#1 == main_~range~0#1;main_~i~0#1 := 0;main_~range~0#1 := main_~range~0#1 - 1; 21960#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 21959#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 21958#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 21957#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 21956#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 21955#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 21954#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 21953#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 21952#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 21951#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 21950#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 21949#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 21948#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 21947#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 21946#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 21944#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 21942#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 21936#L13 assume main_~i~0#1 == main_~range~0#1;main_~i~0#1 := 0;main_~range~0#1 := main_~range~0#1 - 1; 21937#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 21943#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 22006#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 22005#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 22004#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 22003#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 22002#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 22001#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 22000#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 21999#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 21998#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 21997#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 21996#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 21995#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 21994#L13 assume main_~i~0#1 == main_~range~0#1;main_~i~0#1 := 0;main_~range~0#1 := main_~range~0#1 - 1; 21993#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 21992#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 21991#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 21990#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 21989#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 21988#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 21987#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 21986#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 21985#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 21984#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 21983#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 21982#L13 assume main_~i~0#1 == main_~range~0#1;main_~i~0#1 := 0;main_~range~0#1 := main_~range~0#1 - 1; 21981#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 21980#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 21979#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 21978#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 21977#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 21976#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 21975#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 21974#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 21973#L13 assume main_~i~0#1 == main_~range~0#1;main_~i~0#1 := 0;main_~range~0#1 := main_~range~0#1 - 1; 21972#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 21971#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 21970#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 21969#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 21968#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 21965#L13 assume main_~i~0#1 == main_~range~0#1;main_~i~0#1 := 0;main_~range~0#1 := main_~range~0#1 - 1; 21966#L12-1 [2023-11-12 02:33:22,915 INFO L750 eck$LassoCheckResult]: Loop: 21966#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 21967#L12 assume !!(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 21966#L12-1 [2023-11-12 02:33:22,915 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-12 02:33:22,915 INFO L85 PathProgramCache]: Analyzing trace with hash 2044987687, now seen corresponding path program 10 times [2023-11-12 02:33:22,915 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-12 02:33:22,916 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1990220163] [2023-11-12 02:33:22,916 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-12 02:33:22,916 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-12 02:33:23,033 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-12 02:33:24,009 INFO L134 CoverageAnalysis]: Checked inductivity of 38640 backedges. 18300 proven. 12627 refuted. 0 times theorem prover too weak. 7713 trivial. 0 not checked. [2023-11-12 02:33:24,009 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-12 02:33:24,009 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1990220163] [2023-11-12 02:33:24,009 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1990220163] provided 0 perfect and 1 imperfect interpolant sequences [2023-11-12 02:33:24,009 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [305709471] [2023-11-12 02:33:24,010 INFO L93 rtionOrderModulation]: Changing assertion order to TERMS_WITH_SMALL_CONSTANTS_FIRST [2023-11-12 02:33:24,010 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2023-11-12 02:33:24,010 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1deda2bf-224c-4242-8866-e899ae47e0d0/bin/uautomizer-verify-uTZkv6EMXl/z3 [2023-11-12 02:33:24,017 INFO L229 MonitoredProcess]: Starting monitored process 44 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1deda2bf-224c-4242-8866-e899ae47e0d0/bin/uautomizer-verify-uTZkv6EMXl/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2023-11-12 02:33:24,021 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1deda2bf-224c-4242-8866-e899ae47e0d0/bin/uautomizer-verify-uTZkv6EMXl/z3 -smt2 -in SMTLIB2_COMPLIANT=true (44)] Waiting until timeout for monitored process [2023-11-12 02:33:24,207 INFO L228 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2023-11-12 02:33:24,207 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2023-11-12 02:33:24,211 INFO L262 TraceCheckSpWp]: Trace formula consists of 1020 conjuncts, 40 conjunts are in the unsatisfiable core [2023-11-12 02:33:24,219 INFO L285 TraceCheckSpWp]: Computing forward predicates... [2023-11-12 02:33:25,464 INFO L134 CoverageAnalysis]: Checked inductivity of 38640 backedges. 20020 proven. 9572 refuted. 0 times theorem prover too weak. 9048 trivial. 0 not checked. [2023-11-12 02:33:25,464 INFO L327 TraceCheckSpWp]: Computing backward predicates... [2023-11-12 02:33:26,481 INFO L134 CoverageAnalysis]: Checked inductivity of 38640 backedges. 20020 proven. 9572 refuted. 0 times theorem prover too weak. 9048 trivial. 0 not checked. [2023-11-12 02:33:26,481 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [305709471] provided 0 perfect and 2 imperfect interpolant sequences [2023-11-12 02:33:26,482 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2023-11-12 02:33:26,482 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [19, 40, 40] total 57 [2023-11-12 02:33:26,482 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [271030813] [2023-11-12 02:33:26,482 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2023-11-12 02:33:26,483 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-12 02:33:26,484 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-12 02:33:26,484 INFO L85 PathProgramCache]: Analyzing trace with hash 1324, now seen corresponding path program 11 times [2023-11-12 02:33:26,484 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-12 02:33:26,484 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1414122017] [2023-11-12 02:33:26,485 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-12 02:33:26,485 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-12 02:33:26,487 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-12 02:33:26,487 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-12 02:33:26,488 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-12 02:33:26,489 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-12 02:33:26,505 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-12 02:33:26,505 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 57 interpolants. [2023-11-12 02:33:26,507 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=650, Invalid=2542, Unknown=0, NotChecked=0, Total=3192 [2023-11-12 02:33:26,508 INFO L87 Difference]: Start difference. First operand 607 states and 626 transitions. cyclomatic complexity: 26 Second operand has 57 states, 57 states have (on average 3.192982456140351) internal successors, (182), 57 states have internal predecessors, (182), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0)