./Ultimate.py --spec ../../sv-benchmarks/c/properties/termination.prp --file ../../sv-benchmarks/c/systemc/pc_sfifo_2.cil-1.c --full-output --architecture 32bit -------------------------------------------------------------------------------- Checking for termination Using default analysis Version cf1a7837 Calling Ultimate with: /usr/lib/jvm/java-11-openjdk-amd64/bin/java -Dosgi.configuration.area=/tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7b9c22fa-3e82-4a9e-bded-316d6416295d/bin/uautomizer-verify-uTZkv6EMXl/data/config -Xmx15G -Xms4m -jar /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7b9c22fa-3e82-4a9e-bded-316d6416295d/bin/uautomizer-verify-uTZkv6EMXl/plugins/org.eclipse.equinox.launcher_1.5.800.v20200727-1323.jar -data @noDefault -ultimatedata /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7b9c22fa-3e82-4a9e-bded-316d6416295d/bin/uautomizer-verify-uTZkv6EMXl/data -tc /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7b9c22fa-3e82-4a9e-bded-316d6416295d/bin/uautomizer-verify-uTZkv6EMXl/config/AutomizerTermination.xml -i ../../sv-benchmarks/c/systemc/pc_sfifo_2.cil-1.c -s /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7b9c22fa-3e82-4a9e-bded-316d6416295d/bin/uautomizer-verify-uTZkv6EMXl/config/svcomp-Termination-32bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7b9c22fa-3e82-4a9e-bded-316d6416295d/bin/uautomizer-verify-uTZkv6EMXl --witnessprinter.witness.filename witness --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(F end) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 32bit --witnessprinter.graph.data.programhash b74079121634b4e5d8b815834e604eed77442466d93875e78a8cab3fe135fa1f --- Real Ultimate output --- This is Ultimate 0.2.3-dev-cf1a783 [2023-11-12 02:32:11,821 INFO L188 SettingsManager]: Resetting all preferences to default values... [2023-11-12 02:32:11,891 INFO L114 SettingsManager]: Loading settings from /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7b9c22fa-3e82-4a9e-bded-316d6416295d/bin/uautomizer-verify-uTZkv6EMXl/config/svcomp-Termination-32bit-Automizer_Default.epf [2023-11-12 02:32:11,896 WARN L101 SettingsManager]: Preference file contains the following unknown settings: [2023-11-12 02:32:11,897 WARN L103 SettingsManager]: * de.uni_freiburg.informatik.ultimate.core.Log level for class [2023-11-12 02:32:11,922 INFO L130 SettingsManager]: Preferences different from defaults after loading the file: [2023-11-12 02:32:11,923 INFO L151 SettingsManager]: Preferences of UltimateCore differ from their defaults: [2023-11-12 02:32:11,924 INFO L153 SettingsManager]: * Log level for class=de.uni_freiburg.informatik.ultimate.lib.smtlibutils.quantifier.QuantifierPusher=ERROR; [2023-11-12 02:32:11,925 INFO L151 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2023-11-12 02:32:11,925 INFO L153 SettingsManager]: * Create parallel compositions if possible=false [2023-11-12 02:32:11,926 INFO L153 SettingsManager]: * Use SBE=true [2023-11-12 02:32:11,926 INFO L151 SettingsManager]: Preferences of BuchiAutomizer differ from their defaults: [2023-11-12 02:32:11,927 INFO L153 SettingsManager]: * NCSB implementation=INTSET_LAZY3 [2023-11-12 02:32:11,927 INFO L153 SettingsManager]: * Use old map elimination=false [2023-11-12 02:32:11,928 INFO L153 SettingsManager]: * Use external solver (rank synthesis)=false [2023-11-12 02:32:11,929 INFO L153 SettingsManager]: * Use only trivial implications for array writes=true [2023-11-12 02:32:11,929 INFO L153 SettingsManager]: * Rank analysis=LINEAR_WITH_GUESSES [2023-11-12 02:32:11,930 INFO L151 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2023-11-12 02:32:11,930 INFO L153 SettingsManager]: * Pointer base address is valid at dereference=ASSUME [2023-11-12 02:32:11,931 INFO L153 SettingsManager]: * sizeof long=4 [2023-11-12 02:32:11,932 INFO L153 SettingsManager]: * Overapproximate operations on floating types=true [2023-11-12 02:32:11,932 INFO L153 SettingsManager]: * sizeof POINTER=4 [2023-11-12 02:32:11,933 INFO L153 SettingsManager]: * Check division by zero=IGNORE [2023-11-12 02:32:11,933 INFO L153 SettingsManager]: * Pointer to allocated memory at dereference=ASSUME [2023-11-12 02:32:11,934 INFO L153 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=ASSUME [2023-11-12 02:32:11,934 INFO L153 SettingsManager]: * Check array bounds for arrays that are off heap=ASSUME [2023-11-12 02:32:11,935 INFO L153 SettingsManager]: * Check unreachability of reach_error function=false [2023-11-12 02:32:11,935 INFO L153 SettingsManager]: * sizeof long double=12 [2023-11-12 02:32:11,936 INFO L153 SettingsManager]: * Check if freed pointer was valid=false [2023-11-12 02:32:11,936 INFO L153 SettingsManager]: * Assume nondeterminstic values are in range=false [2023-11-12 02:32:11,937 INFO L153 SettingsManager]: * Use constant arrays=true [2023-11-12 02:32:11,937 INFO L151 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2023-11-12 02:32:11,938 INFO L153 SettingsManager]: * Size of a code block=SequenceOfStatements [2023-11-12 02:32:11,938 INFO L151 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2023-11-12 02:32:11,939 INFO L153 SettingsManager]: * Trace refinement strategy=CAMEL [2023-11-12 02:32:11,939 INFO L151 SettingsManager]: Preferences of IcfgTransformer differ from their defaults: [2023-11-12 02:32:11,940 INFO L153 SettingsManager]: * TransformationType=MODULO_NEIGHBOR WARNING: An illegal reflective access operation has occurred WARNING: Illegal reflective access by com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 (file:/tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7b9c22fa-3e82-4a9e-bded-316d6416295d/bin/uautomizer-verify-uTZkv6EMXl/plugins/com.sun.xml.bind_2.2.0.v201505121915.jar) to method java.lang.ClassLoader.defineClass(java.lang.String,byte[],int,int) WARNING: Please consider reporting this to the maintainers of com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 WARNING: Use --illegal-access=warn to enable warnings of further illegal reflective access operations WARNING: All illegal access operations will be denied in a future release Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7b9c22fa-3e82-4a9e-bded-316d6416295d/bin/uautomizer-verify-uTZkv6EMXl Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(F end) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 32bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> b74079121634b4e5d8b815834e604eed77442466d93875e78a8cab3fe135fa1f [2023-11-12 02:32:12,246 INFO L75 nceAwareModelManager]: Repository-Root is: /tmp [2023-11-12 02:32:12,289 INFO L261 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2023-11-12 02:32:12,292 INFO L217 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2023-11-12 02:32:12,294 INFO L270 PluginConnector]: Initializing CDTParser... [2023-11-12 02:32:12,295 INFO L274 PluginConnector]: CDTParser initialized [2023-11-12 02:32:12,297 INFO L431 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7b9c22fa-3e82-4a9e-bded-316d6416295d/bin/uautomizer-verify-uTZkv6EMXl/../../sv-benchmarks/c/systemc/pc_sfifo_2.cil-1.c [2023-11-12 02:32:15,405 INFO L533 CDTParser]: Created temporary CDT project at NULL [2023-11-12 02:32:15,689 INFO L384 CDTParser]: Found 1 translation units. [2023-11-12 02:32:15,691 INFO L180 CDTParser]: Scanning /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7b9c22fa-3e82-4a9e-bded-316d6416295d/sv-benchmarks/c/systemc/pc_sfifo_2.cil-1.c [2023-11-12 02:32:15,708 INFO L427 CDTParser]: About to delete temporary CDT project at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7b9c22fa-3e82-4a9e-bded-316d6416295d/bin/uautomizer-verify-uTZkv6EMXl/data/fdc7c7cb6/b2d52c12bf2548718cbc4ce179178b1a/FLAG0dcae3507 [2023-11-12 02:32:15,725 INFO L435 CDTParser]: Successfully deleted /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7b9c22fa-3e82-4a9e-bded-316d6416295d/bin/uautomizer-verify-uTZkv6EMXl/data/fdc7c7cb6/b2d52c12bf2548718cbc4ce179178b1a [2023-11-12 02:32:15,732 INFO L299 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2023-11-12 02:32:15,734 INFO L133 ToolchainWalker]: Walking toolchain with 6 elements. [2023-11-12 02:32:15,736 INFO L112 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2023-11-12 02:32:15,741 INFO L270 PluginConnector]: Initializing CACSL2BoogieTranslator... [2023-11-12 02:32:15,746 INFO L274 PluginConnector]: CACSL2BoogieTranslator initialized [2023-11-12 02:32:15,749 INFO L184 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 12.11 02:32:15" (1/1) ... [2023-11-12 02:32:15,750 INFO L204 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@1d82630a and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 12.11 02:32:15, skipping insertion in model container [2023-11-12 02:32:15,750 INFO L184 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 12.11 02:32:15" (1/1) ... [2023-11-12 02:32:15,804 INFO L177 MainTranslator]: Built tables and reachable declarations [2023-11-12 02:32:16,054 INFO L209 PostProcessor]: Analyzing one entry point: main [2023-11-12 02:32:16,068 INFO L202 MainTranslator]: Completed pre-run [2023-11-12 02:32:16,105 INFO L209 PostProcessor]: Analyzing one entry point: main [2023-11-12 02:32:16,122 INFO L206 MainTranslator]: Completed translation [2023-11-12 02:32:16,123 INFO L201 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 12.11 02:32:16 WrapperNode [2023-11-12 02:32:16,123 INFO L131 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2023-11-12 02:32:16,125 INFO L112 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2023-11-12 02:32:16,125 INFO L270 PluginConnector]: Initializing Boogie Procedure Inliner... [2023-11-12 02:32:16,125 INFO L274 PluginConnector]: Boogie Procedure Inliner initialized [2023-11-12 02:32:16,133 INFO L184 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 12.11 02:32:16" (1/1) ... [2023-11-12 02:32:16,142 INFO L184 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 12.11 02:32:16" (1/1) ... [2023-11-12 02:32:16,173 INFO L138 Inliner]: procedures = 29, calls = 32, calls flagged for inlining = 27, calls inlined = 29, statements flattened = 307 [2023-11-12 02:32:16,174 INFO L131 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2023-11-12 02:32:16,175 INFO L112 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2023-11-12 02:32:16,175 INFO L270 PluginConnector]: Initializing Boogie Preprocessor... [2023-11-12 02:32:16,175 INFO L274 PluginConnector]: Boogie Preprocessor initialized [2023-11-12 02:32:16,184 INFO L184 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 12.11 02:32:16" (1/1) ... [2023-11-12 02:32:16,184 INFO L184 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 12.11 02:32:16" (1/1) ... [2023-11-12 02:32:16,188 INFO L184 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 12.11 02:32:16" (1/1) ... [2023-11-12 02:32:16,188 INFO L184 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 12.11 02:32:16" (1/1) ... [2023-11-12 02:32:16,195 INFO L184 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 12.11 02:32:16" (1/1) ... [2023-11-12 02:32:16,202 INFO L184 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 12.11 02:32:16" (1/1) ... [2023-11-12 02:32:16,204 INFO L184 PluginConnector]: Executing the observer LTLStepAnnotator from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 12.11 02:32:16" (1/1) ... [2023-11-12 02:32:16,206 INFO L184 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 12.11 02:32:16" (1/1) ... [2023-11-12 02:32:16,210 INFO L131 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2023-11-12 02:32:16,211 INFO L112 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2023-11-12 02:32:16,211 INFO L270 PluginConnector]: Initializing RCFGBuilder... [2023-11-12 02:32:16,211 INFO L274 PluginConnector]: RCFGBuilder initialized [2023-11-12 02:32:16,212 INFO L184 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 12.11 02:32:16" (1/1) ... [2023-11-12 02:32:16,219 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2023-11-12 02:32:16,235 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7b9c22fa-3e82-4a9e-bded-316d6416295d/bin/uautomizer-verify-uTZkv6EMXl/z3 [2023-11-12 02:32:16,259 INFO L229 MonitoredProcess]: Starting monitored process 1 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7b9c22fa-3e82-4a9e-bded-316d6416295d/bin/uautomizer-verify-uTZkv6EMXl/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2023-11-12 02:32:16,300 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7b9c22fa-3e82-4a9e-bded-316d6416295d/bin/uautomizer-verify-uTZkv6EMXl/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (1)] Waiting until timeout for monitored process [2023-11-12 02:32:16,316 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocInit [2023-11-12 02:32:16,316 INFO L130 BoogieDeclarations]: Found specification of procedure write~init~int [2023-11-12 02:32:16,316 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2023-11-12 02:32:16,317 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2023-11-12 02:32:16,397 INFO L236 CfgBuilder]: Building ICFG [2023-11-12 02:32:16,400 INFO L262 CfgBuilder]: Building CFG for each procedure with an implementation [2023-11-12 02:32:16,773 INFO L277 CfgBuilder]: Performing block encoding [2023-11-12 02:32:16,781 INFO L297 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2023-11-12 02:32:16,781 INFO L302 CfgBuilder]: Removed 4 assume(true) statements. [2023-11-12 02:32:16,783 INFO L201 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 12.11 02:32:16 BoogieIcfgContainer [2023-11-12 02:32:16,783 INFO L131 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2023-11-12 02:32:16,784 INFO L112 PluginConnector]: ------------------------BuchiAutomizer---------------------------- [2023-11-12 02:32:16,785 INFO L270 PluginConnector]: Initializing BuchiAutomizer... [2023-11-12 02:32:16,794 INFO L274 PluginConnector]: BuchiAutomizer initialized [2023-11-12 02:32:16,795 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2023-11-12 02:32:16,795 INFO L184 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "CDTParser AST 12.11 02:32:15" (1/3) ... [2023-11-12 02:32:16,796 INFO L204 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@2a452560 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 12.11 02:32:16, skipping insertion in model container [2023-11-12 02:32:16,796 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2023-11-12 02:32:16,797 INFO L184 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 12.11 02:32:16" (2/3) ... [2023-11-12 02:32:16,797 INFO L204 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@2a452560 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 12.11 02:32:16, skipping insertion in model container [2023-11-12 02:32:16,797 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2023-11-12 02:32:16,797 INFO L184 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 12.11 02:32:16" (3/3) ... [2023-11-12 02:32:16,798 INFO L332 chiAutomizerObserver]: Analyzing ICFG pc_sfifo_2.cil-1.c [2023-11-12 02:32:16,889 INFO L303 stractBuchiCegarLoop]: Interprodecural is true [2023-11-12 02:32:16,890 INFO L304 stractBuchiCegarLoop]: Hoare is false [2023-11-12 02:32:16,890 INFO L305 stractBuchiCegarLoop]: Compute interpolants for ForwardPredicates [2023-11-12 02:32:16,890 INFO L306 stractBuchiCegarLoop]: Backedges is STRAIGHT_LINE [2023-11-12 02:32:16,890 INFO L307 stractBuchiCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2023-11-12 02:32:16,891 INFO L308 stractBuchiCegarLoop]: Difference is false [2023-11-12 02:32:16,891 INFO L309 stractBuchiCegarLoop]: Minimize is MINIMIZE_SEVPA [2023-11-12 02:32:16,891 INFO L313 stractBuchiCegarLoop]: ======== Iteration 0 == of CEGAR loop == BuchiAutomatonCegarLoop ======== [2023-11-12 02:32:16,897 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 105 states, 104 states have (on average 1.5288461538461537) internal successors, (159), 104 states have internal predecessors, (159), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-12 02:32:16,931 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 69 [2023-11-12 02:32:16,931 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-12 02:32:16,931 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-12 02:32:16,942 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-12 02:32:16,942 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-12 02:32:16,942 INFO L335 stractBuchiCegarLoop]: ======== Iteration 1 ============ [2023-11-12 02:32:16,944 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 105 states, 104 states have (on average 1.5288461538461537) internal successors, (159), 104 states have internal predecessors, (159), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-12 02:32:16,961 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 69 [2023-11-12 02:32:16,962 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-12 02:32:16,963 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-12 02:32:16,965 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-12 02:32:16,965 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-12 02:32:17,003 INFO L748 eck$LassoCheckResult]: Stem: 19#$Ultimate##0true assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(19, 2);call #Ultimate.allocInit(12, 3);~q_buf_0~0 := 0;~q_free~0 := 0;~q_read_ev~0 := 0;~q_write_ev~0 := 0;~q_req_up~0 := 0;~q_ev~0 := 0;~p_num_write~0 := 0;~p_last_write~0 := 0;~p_dw_st~0 := 0;~p_dw_pc~0 := 0;~p_dw_i~0 := 0;~c_num_read~0 := 0;~c_last_read~0 := 0;~c_dr_st~0 := 0;~c_dr_pc~0 := 0;~c_dr_i~0 := 0;~a_t~0 := 0; 31#L-1true assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~3#1;havoc main_~__retres1~3#1;assume { :begin_inline_init_model } true;~q_free~0 := 1;~q_write_ev~0 := 2;~q_read_ev~0 := ~q_write_ev~0;~p_num_write~0 := 0;~p_dw_pc~0 := 0;~p_dw_i~0 := 1;~c_num_read~0 := 0;~c_dr_pc~0 := 0;~c_dr_i~0 := 1; 101#init_model_returnLabel#1true assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret13#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~4#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~4#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 64#L222true assume !(1 == ~q_req_up~0); 9#L222-2true assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 80#L237true assume 1 == ~p_dw_i~0;~p_dw_st~0 := 0; 32#L237-2true assume !(1 == ~c_dr_i~0);~c_dr_st~0 := 2; 39#L242-1true assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 87#L275true assume !(0 == ~q_read_ev~0); 93#L275-2true assume !(0 == ~q_write_ev~0); 23#L280-1true assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;assume { :begin_inline_is_do_write_p_triggered } true;havoc is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;havoc is_do_write_p_triggered_~__retres1~0#1; 106#L65true assume !(1 == ~p_dw_pc~0); 30#L65-2true is_do_write_p_triggered_~__retres1~0#1 := 0; 56#L76true is_do_write_p_triggered_#res#1 := is_do_write_p_triggered_~__retres1~0#1; 74#is_do_write_p_triggered_returnLabel#1true activate_threads_#t~ret7#1 := is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;assume { :end_inline_is_do_write_p_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1; 36#L315true assume !(0 != activate_threads_~tmp~1#1); 62#L315-2true assume { :begin_inline_is_do_read_c_triggered } true;havoc is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;havoc is_do_read_c_triggered_~__retres1~1#1; 96#L84true assume 1 == ~c_dr_pc~0; 25#L85true assume 1 == ~q_write_ev~0;is_do_read_c_triggered_~__retres1~1#1 := 1; 68#L95true is_do_read_c_triggered_#res#1 := is_do_read_c_triggered_~__retres1~1#1; 21#is_do_read_c_triggered_returnLabel#1true activate_threads_#t~ret8#1 := is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;assume { :end_inline_is_do_read_c_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 4#L323true assume !(0 != activate_threads_~tmp___0~1#1); 47#L323-2true havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 97#L293true assume !(1 == ~q_read_ev~0); 2#L293-2true assume 1 == ~q_write_ev~0;~q_write_ev~0 := 2; 37#L298-1true assume { :end_inline_reset_delta_events } true; 11#L419-2true [2023-11-12 02:32:17,005 INFO L750 eck$LassoCheckResult]: Loop: 11#L419-2true assume !false; 27#L420true start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret9#1, eval_#t~nondet10#1, eval_#t~nondet11#1, eval_~tmp~2#1, eval_~tmp___0~2#1, eval_~tmp___1~0#1;havoc eval_~tmp~2#1;havoc eval_~tmp___0~2#1;havoc eval_~tmp___1~0#1; 102#L364true assume !true; 65#eval_returnLabel#1true havoc eval_#t~ret9#1, eval_#t~nondet10#1, eval_#t~nondet11#1, eval_~tmp~2#1, eval_~tmp___0~2#1, eval_~tmp___1~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 83#L222-3true assume !(1 == ~q_req_up~0); 33#L222-5true assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 79#L275-3true assume 0 == ~q_read_ev~0;~q_read_ev~0 := 1; 41#L275-5true assume 0 == ~q_write_ev~0;~q_write_ev~0 := 1; 54#L280-3true assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;assume { :begin_inline_is_do_write_p_triggered } true;havoc is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;havoc is_do_write_p_triggered_~__retres1~0#1; 61#L65-3true assume !(1 == ~p_dw_pc~0); 17#L65-5true is_do_write_p_triggered_~__retres1~0#1 := 0; 94#L76-1true is_do_write_p_triggered_#res#1 := is_do_write_p_triggered_~__retres1~0#1; 55#is_do_write_p_triggered_returnLabel#2true activate_threads_#t~ret7#1 := is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;assume { :end_inline_is_do_write_p_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1; 42#L315-3true assume !(0 != activate_threads_~tmp~1#1); 84#L315-5true assume { :begin_inline_is_do_read_c_triggered } true;havoc is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;havoc is_do_read_c_triggered_~__retres1~1#1; 59#L84-3true assume 1 == ~c_dr_pc~0; 44#L85-1true assume 1 == ~q_write_ev~0;is_do_read_c_triggered_~__retres1~1#1 := 1; 78#L95-1true is_do_read_c_triggered_#res#1 := is_do_read_c_triggered_~__retres1~1#1; 29#is_do_read_c_triggered_returnLabel#2true activate_threads_#t~ret8#1 := is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;assume { :end_inline_is_do_read_c_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 104#L323-3true assume 0 != activate_threads_~tmp___0~1#1;~c_dr_st~0 := 0; 77#L323-5true havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 91#L293-3true assume 1 == ~q_read_ev~0;~q_read_ev~0 := 2; 5#L293-5true assume 1 == ~q_write_ev~0;~q_write_ev~0 := 2; 53#L298-3true assume { :end_inline_reset_delta_events } true;assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret12#1, stop_simulation_~tmp~3#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~3#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 24#L255-1true assume 0 == ~p_dw_st~0;exists_runnable_thread_~__retres1~2#1 := 1; 26#L267-1true exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 75#exists_runnable_thread_returnLabel#2true stop_simulation_#t~ret12#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~3#1 := stop_simulation_#t~ret12#1;havoc stop_simulation_#t~ret12#1; 13#L394true assume 0 != stop_simulation_~tmp~3#1;stop_simulation_~__retres2~0#1 := 0; 7#L401true stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 103#stop_simulation_returnLabel#1true start_simulation_#t~ret13#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret12#1, stop_simulation_~tmp~3#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp~4#1 := start_simulation_#t~ret13#1;havoc start_simulation_#t~ret13#1; 28#L436true assume !(0 != start_simulation_~tmp~4#1); 11#L419-2true [2023-11-12 02:32:17,012 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-12 02:32:17,012 INFO L85 PathProgramCache]: Analyzing trace with hash -239976594, now seen corresponding path program 1 times [2023-11-12 02:32:17,023 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-12 02:32:17,024 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [375571903] [2023-11-12 02:32:17,024 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-12 02:32:17,025 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-12 02:32:17,161 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-12 02:32:17,308 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-12 02:32:17,309 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-12 02:32:17,309 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [375571903] [2023-11-12 02:32:17,310 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [375571903] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-12 02:32:17,310 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-12 02:32:17,311 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-12 02:32:17,312 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [869149669] [2023-11-12 02:32:17,313 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-12 02:32:17,318 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-12 02:32:17,319 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-12 02:32:17,319 INFO L85 PathProgramCache]: Analyzing trace with hash -573197680, now seen corresponding path program 1 times [2023-11-12 02:32:17,320 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-12 02:32:17,320 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [291210686] [2023-11-12 02:32:17,320 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-12 02:32:17,321 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-12 02:32:17,333 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-12 02:32:17,348 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-12 02:32:17,349 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-12 02:32:17,349 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [291210686] [2023-11-12 02:32:17,349 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [291210686] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-12 02:32:17,350 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-12 02:32:17,350 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2023-11-12 02:32:17,350 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1599697127] [2023-11-12 02:32:17,351 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-12 02:32:17,352 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-12 02:32:17,353 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-12 02:32:17,387 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-12 02:32:17,387 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-12 02:32:17,390 INFO L87 Difference]: Start difference. First operand has 105 states, 104 states have (on average 1.5288461538461537) internal successors, (159), 104 states have internal predecessors, (159), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand has 3 states, 3 states have (on average 8.666666666666666) internal successors, (26), 3 states have internal predecessors, (26), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-12 02:32:17,438 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-12 02:32:17,439 INFO L93 Difference]: Finished difference Result 101 states and 144 transitions. [2023-11-12 02:32:17,440 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 101 states and 144 transitions. [2023-11-12 02:32:17,453 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 63 [2023-11-12 02:32:17,460 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 101 states to 95 states and 138 transitions. [2023-11-12 02:32:17,461 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 95 [2023-11-12 02:32:17,465 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 95 [2023-11-12 02:32:17,466 INFO L73 IsDeterministic]: Start isDeterministic. Operand 95 states and 138 transitions. [2023-11-12 02:32:17,466 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-12 02:32:17,467 INFO L218 hiAutomatonCegarLoop]: Abstraction has 95 states and 138 transitions. [2023-11-12 02:32:17,482 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 95 states and 138 transitions. [2023-11-12 02:32:17,496 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 95 to 95. [2023-11-12 02:32:17,497 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 95 states, 95 states have (on average 1.4526315789473685) internal successors, (138), 94 states have internal predecessors, (138), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-12 02:32:17,499 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 95 states to 95 states and 138 transitions. [2023-11-12 02:32:17,500 INFO L240 hiAutomatonCegarLoop]: Abstraction has 95 states and 138 transitions. [2023-11-12 02:32:17,501 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-12 02:32:17,505 INFO L428 stractBuchiCegarLoop]: Abstraction has 95 states and 138 transitions. [2023-11-12 02:32:17,505 INFO L335 stractBuchiCegarLoop]: ======== Iteration 2 ============ [2023-11-12 02:32:17,505 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 95 states and 138 transitions. [2023-11-12 02:32:17,507 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 63 [2023-11-12 02:32:17,508 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-12 02:32:17,508 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-12 02:32:17,509 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-12 02:32:17,510 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-12 02:32:17,510 INFO L748 eck$LassoCheckResult]: Stem: 272#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(19, 2);call #Ultimate.allocInit(12, 3);~q_buf_0~0 := 0;~q_free~0 := 0;~q_read_ev~0 := 0;~q_write_ev~0 := 0;~q_req_up~0 := 0;~q_ev~0 := 0;~p_num_write~0 := 0;~p_last_write~0 := 0;~p_dw_st~0 := 0;~p_dw_pc~0 := 0;~p_dw_i~0 := 0;~c_num_read~0 := 0;~c_last_read~0 := 0;~c_dr_st~0 := 0;~c_dr_pc~0 := 0;~c_dr_i~0 := 0;~a_t~0 := 0; 273#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~3#1;havoc main_~__retres1~3#1;assume { :begin_inline_init_model } true;~q_free~0 := 1;~q_write_ev~0 := 2;~q_read_ev~0 := ~q_write_ev~0;~p_num_write~0 := 0;~p_dw_pc~0 := 0;~p_dw_i~0 := 1;~c_num_read~0 := 0;~c_dr_pc~0 := 0;~c_dr_i~0 := 1; 297#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret13#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~4#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~4#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 250#L222 assume !(1 == ~q_req_up~0); 239#L222-2 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 240#L237 assume 1 == ~p_dw_i~0;~p_dw_st~0 := 0; 280#L237-2 assume 1 == ~c_dr_i~0;~c_dr_st~0 := 0; 301#L242-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 299#L275 assume !(0 == ~q_read_ev~0); 300#L275-2 assume !(0 == ~q_write_ev~0); 286#L280-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;assume { :begin_inline_is_do_write_p_triggered } true;havoc is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;havoc is_do_write_p_triggered_~__retres1~0#1; 287#L65 assume !(1 == ~p_dw_pc~0); 283#L65-2 is_do_write_p_triggered_~__retres1~0#1 := 0; 282#L76 is_do_write_p_triggered_#res#1 := is_do_write_p_triggered_~__retres1~0#1; 267#is_do_write_p_triggered_returnLabel#1 activate_threads_#t~ret7#1 := is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;assume { :end_inline_is_do_write_p_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1; 268#L315 assume !(0 != activate_threads_~tmp~1#1); 245#L315-2 assume { :begin_inline_is_do_read_c_triggered } true;havoc is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;havoc is_do_read_c_triggered_~__retres1~1#1; 246#L84 assume 1 == ~c_dr_pc~0; 292#L85 assume 1 == ~q_write_ev~0;is_do_read_c_triggered_~__retres1~1#1 := 1; 259#L95 is_do_read_c_triggered_#res#1 := is_do_read_c_triggered_~__retres1~1#1; 260#is_do_read_c_triggered_returnLabel#1 activate_threads_#t~ret8#1 := is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;assume { :end_inline_is_do_read_c_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 222#L323 assume !(0 != activate_threads_~tmp___0~1#1); 223#L323-2 havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 308#L293 assume !(1 == ~q_read_ev~0); 215#L293-2 assume 1 == ~q_write_ev~0;~q_write_ev~0 := 2; 216#L298-1 assume { :end_inline_reset_delta_events } true; 241#L419-2 [2023-11-12 02:32:17,511 INFO L750 eck$LassoCheckResult]: Loop: 241#L419-2 assume !false; 242#L420 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret9#1, eval_#t~nondet10#1, eval_#t~nondet11#1, eval_~tmp~2#1, eval_~tmp___0~2#1, eval_~tmp___1~0#1;havoc eval_~tmp~2#1;havoc eval_~tmp___0~2#1;havoc eval_~tmp___1~0#1; 256#L364 assume !false; 288#L340 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 252#L255 assume 0 == ~p_dw_st~0;exists_runnable_thread_~__retres1~2#1 := 1; 218#L267 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 237#exists_runnable_thread_returnLabel#1 eval_#t~ret9#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp___1~0#1 := eval_#t~ret9#1;havoc eval_#t~ret9#1; 238#L344 assume !(0 != eval_~tmp___1~0#1); 253#eval_returnLabel#1 havoc eval_#t~ret9#1, eval_#t~nondet10#1, eval_#t~nondet11#1, eval_~tmp~2#1, eval_~tmp___0~2#1, eval_~tmp___1~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 254#L222-3 assume !(1 == ~q_req_up~0); 285#L222-5 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 278#L275-3 assume 0 == ~q_read_ev~0;~q_read_ev~0 := 1; 279#L275-5 assume 0 == ~q_write_ev~0;~q_write_ev~0 := 1; 306#L280-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;assume { :begin_inline_is_do_write_p_triggered } true;havoc is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;havoc is_do_write_p_triggered_~__retres1~0#1; 228#L65-3 assume !(1 == ~p_dw_pc~0); 229#L65-5 is_do_write_p_triggered_~__retres1~0#1 := 0; 263#L76-1 is_do_write_p_triggered_#res#1 := is_do_write_p_triggered_~__retres1~0#1; 305#is_do_write_p_triggered_returnLabel#2 activate_threads_#t~ret7#1 := is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;assume { :end_inline_is_do_write_p_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1; 307#L315-3 assume !(0 != activate_threads_~tmp~1#1); 295#L315-5 assume { :begin_inline_is_do_read_c_triggered } true;havoc is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;havoc is_do_read_c_triggered_~__retres1~1#1; 219#L84-3 assume 1 == ~c_dr_pc~0; 220#L85-1 assume 1 == ~q_write_ev~0;is_do_read_c_triggered_~__retres1~1#1 := 1; 276#L95-1 is_do_read_c_triggered_#res#1 := is_do_read_c_triggered_~__retres1~1#1; 277#is_do_read_c_triggered_returnLabel#2 activate_threads_#t~ret8#1 := is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;assume { :end_inline_is_do_read_c_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 294#L323-3 assume 0 != activate_threads_~tmp___0~1#1;~c_dr_st~0 := 0; 274#L323-5 havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 275#L293-3 assume 1 == ~q_read_ev~0;~q_read_ev~0 := 2; 226#L293-5 assume 1 == ~q_write_ev~0;~q_write_ev~0 := 2; 227#L298-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret12#1, stop_simulation_~tmp~3#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~3#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 289#L255-1 assume 0 == ~p_dw_st~0;exists_runnable_thread_~__retres1~2#1 := 1; 290#L267-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 269#exists_runnable_thread_returnLabel#2 stop_simulation_#t~ret12#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~3#1 := stop_simulation_#t~ret12#1;havoc stop_simulation_#t~ret12#1; 247#L394 assume 0 != stop_simulation_~tmp~3#1;stop_simulation_~__retres2~0#1 := 0; 233#L401 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 234#stop_simulation_returnLabel#1 start_simulation_#t~ret13#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret12#1, stop_simulation_~tmp~3#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp~4#1 := start_simulation_#t~ret13#1;havoc start_simulation_#t~ret13#1; 293#L436 assume !(0 != start_simulation_~tmp~4#1); 241#L419-2 [2023-11-12 02:32:17,511 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-12 02:32:17,512 INFO L85 PathProgramCache]: Analyzing trace with hash 577671856, now seen corresponding path program 1 times [2023-11-12 02:32:17,512 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-12 02:32:17,512 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [568052663] [2023-11-12 02:32:17,512 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-12 02:32:17,513 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-12 02:32:17,534 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-12 02:32:17,652 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-12 02:32:17,653 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-12 02:32:17,653 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [568052663] [2023-11-12 02:32:17,653 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [568052663] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-12 02:32:17,653 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-12 02:32:17,654 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2023-11-12 02:32:17,654 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1592655225] [2023-11-12 02:32:17,654 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-12 02:32:17,655 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-12 02:32:17,655 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-12 02:32:17,655 INFO L85 PathProgramCache]: Analyzing trace with hash -1808359021, now seen corresponding path program 1 times [2023-11-12 02:32:17,656 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-12 02:32:17,656 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1739558070] [2023-11-12 02:32:17,656 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-12 02:32:17,657 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-12 02:32:17,688 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-12 02:32:17,832 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-12 02:32:17,832 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-12 02:32:17,833 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1739558070] [2023-11-12 02:32:17,833 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1739558070] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-12 02:32:17,833 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-12 02:32:17,833 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2023-11-12 02:32:17,834 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1725753615] [2023-11-12 02:32:17,834 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-12 02:32:17,834 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-12 02:32:17,835 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-12 02:32:17,835 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2023-11-12 02:32:17,835 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2023-11-12 02:32:17,836 INFO L87 Difference]: Start difference. First operand 95 states and 138 transitions. cyclomatic complexity: 44 Second operand has 5 states, 5 states have (on average 5.2) internal successors, (26), 4 states have internal predecessors, (26), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-12 02:32:17,985 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-12 02:32:17,985 INFO L93 Difference]: Finished difference Result 312 states and 446 transitions. [2023-11-12 02:32:17,985 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 312 states and 446 transitions. [2023-11-12 02:32:17,991 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 283 [2023-11-12 02:32:17,996 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 312 states to 312 states and 446 transitions. [2023-11-12 02:32:17,996 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 312 [2023-11-12 02:32:17,997 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 312 [2023-11-12 02:32:17,997 INFO L73 IsDeterministic]: Start isDeterministic. Operand 312 states and 446 transitions. [2023-11-12 02:32:18,000 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-12 02:32:18,000 INFO L218 hiAutomatonCegarLoop]: Abstraction has 312 states and 446 transitions. [2023-11-12 02:32:18,001 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 312 states and 446 transitions. [2023-11-12 02:32:18,022 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 312 to 298. [2023-11-12 02:32:18,023 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 298 states, 298 states have (on average 1.4429530201342282) internal successors, (430), 297 states have internal predecessors, (430), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-12 02:32:18,026 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 298 states to 298 states and 430 transitions. [2023-11-12 02:32:18,026 INFO L240 hiAutomatonCegarLoop]: Abstraction has 298 states and 430 transitions. [2023-11-12 02:32:18,027 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2023-11-12 02:32:18,028 INFO L428 stractBuchiCegarLoop]: Abstraction has 298 states and 430 transitions. [2023-11-12 02:32:18,028 INFO L335 stractBuchiCegarLoop]: ======== Iteration 3 ============ [2023-11-12 02:32:18,028 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 298 states and 430 transitions. [2023-11-12 02:32:18,031 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 270 [2023-11-12 02:32:18,032 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-12 02:32:18,032 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-12 02:32:18,033 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-12 02:32:18,033 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-12 02:32:18,034 INFO L748 eck$LassoCheckResult]: Stem: 695#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(19, 2);call #Ultimate.allocInit(12, 3);~q_buf_0~0 := 0;~q_free~0 := 0;~q_read_ev~0 := 0;~q_write_ev~0 := 0;~q_req_up~0 := 0;~q_ev~0 := 0;~p_num_write~0 := 0;~p_last_write~0 := 0;~p_dw_st~0 := 0;~p_dw_pc~0 := 0;~p_dw_i~0 := 0;~c_num_read~0 := 0;~c_last_read~0 := 0;~c_dr_st~0 := 0;~c_dr_pc~0 := 0;~c_dr_i~0 := 0;~a_t~0 := 0; 696#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~3#1;havoc main_~__retres1~3#1;assume { :begin_inline_init_model } true;~q_free~0 := 1;~q_write_ev~0 := 2;~q_read_ev~0 := ~q_write_ev~0;~p_num_write~0 := 0;~p_dw_pc~0 := 0;~p_dw_i~0 := 1;~c_num_read~0 := 0;~c_dr_pc~0 := 0;~c_dr_i~0 := 1; 721#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret13#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~4#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~4#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 669#L222 assume !(1 == ~q_req_up~0); 660#L222-2 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 661#L237 assume 1 == ~p_dw_i~0;~p_dw_st~0 := 0; 703#L237-2 assume 1 == ~c_dr_i~0;~c_dr_st~0 := 0; 727#L242-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 724#L275 assume !(0 == ~q_read_ev~0); 725#L275-2 assume !(0 == ~q_write_ev~0); 711#L280-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;assume { :begin_inline_is_do_write_p_triggered } true;havoc is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;havoc is_do_write_p_triggered_~__retres1~0#1; 712#L65 assume !(1 == ~p_dw_pc~0); 706#L65-2 is_do_write_p_triggered_~__retres1~0#1 := 0; 705#L76 is_do_write_p_triggered_#res#1 := is_do_write_p_triggered_~__retres1~0#1; 689#is_do_write_p_triggered_returnLabel#1 activate_threads_#t~ret7#1 := is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;assume { :end_inline_is_do_write_p_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1; 690#L315 assume !(0 != activate_threads_~tmp~1#1); 666#L315-2 assume { :begin_inline_is_do_read_c_triggered } true;havoc is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;havoc is_do_read_c_triggered_~__retres1~1#1; 667#L84 assume !(1 == ~c_dr_pc~0); 684#L84-2 is_do_read_c_triggered_~__retres1~1#1 := 0; 678#L95 is_do_read_c_triggered_#res#1 := is_do_read_c_triggered_~__retres1~1#1; 679#is_do_read_c_triggered_returnLabel#1 activate_threads_#t~ret8#1 := is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;assume { :end_inline_is_do_read_c_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 643#L323 assume !(0 != activate_threads_~tmp___0~1#1); 644#L323-2 havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 738#L293 assume !(1 == ~q_read_ev~0); 637#L293-2 assume 1 == ~q_write_ev~0;~q_write_ev~0 := 2; 638#L298-1 assume { :end_inline_reset_delta_events } true; 734#L419-2 [2023-11-12 02:32:18,034 INFO L750 eck$LassoCheckResult]: Loop: 734#L419-2 assume !false; 816#L420 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret9#1, eval_#t~nondet10#1, eval_#t~nondet11#1, eval_~tmp~2#1, eval_~tmp___0~2#1, eval_~tmp___1~0#1;havoc eval_~tmp~2#1;havoc eval_~tmp___0~2#1;havoc eval_~tmp___1~0#1; 674#L364 assume !false; 815#L340 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 814#L255 assume 0 == ~p_dw_st~0;exists_runnable_thread_~__retres1~2#1 := 1; 812#L267 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 811#exists_runnable_thread_returnLabel#1 eval_#t~ret9#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp___1~0#1 := eval_#t~ret9#1;havoc eval_#t~ret9#1; 691#L344 assume !(0 != eval_~tmp___1~0#1); 693#eval_returnLabel#1 havoc eval_#t~ret9#1, eval_#t~nondet10#1, eval_#t~nondet11#1, eval_~tmp~2#1, eval_~tmp___0~2#1, eval_~tmp___1~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 905#L222-3 assume !(1 == ~q_req_up~0); 903#L222-5 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 901#L275-3 assume 0 == ~q_read_ev~0;~q_read_ev~0 := 1; 899#L275-5 assume 0 == ~q_write_ev~0;~q_write_ev~0 := 1; 896#L280-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;assume { :begin_inline_is_do_write_p_triggered } true;havoc is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;havoc is_do_write_p_triggered_~__retres1~0#1; 894#L65-3 assume 1 == ~p_dw_pc~0; 890#L66-1 assume 1 == ~q_read_ev~0;is_do_write_p_triggered_~__retres1~0#1 := 1; 888#L76-1 is_do_write_p_triggered_#res#1 := is_do_write_p_triggered_~__retres1~0#1; 886#is_do_write_p_triggered_returnLabel#2 activate_threads_#t~ret7#1 := is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;assume { :end_inline_is_do_write_p_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1; 884#L315-3 assume !(0 != activate_threads_~tmp~1#1); 882#L315-5 assume { :begin_inline_is_do_read_c_triggered } true;havoc is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;havoc is_do_read_c_triggered_~__retres1~1#1; 878#L84-3 assume !(1 == ~c_dr_pc~0); 875#L84-5 is_do_read_c_triggered_~__retres1~1#1 := 0; 872#L95-1 is_do_read_c_triggered_#res#1 := is_do_read_c_triggered_~__retres1~1#1; 869#is_do_read_c_triggered_returnLabel#2 activate_threads_#t~ret8#1 := is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;assume { :end_inline_is_do_read_c_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 866#L323-3 assume 0 != activate_threads_~tmp___0~1#1;~c_dr_st~0 := 0; 846#L323-5 havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 843#L293-3 assume 1 == ~q_read_ev~0;~q_read_ev~0 := 2; 841#L293-5 assume 1 == ~q_write_ev~0;~q_write_ev~0 := 2; 839#L298-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret12#1, stop_simulation_~tmp~3#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~3#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 837#L255-1 assume 0 == ~p_dw_st~0;exists_runnable_thread_~__retres1~2#1 := 1; 834#L267-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 832#exists_runnable_thread_returnLabel#2 stop_simulation_#t~ret12#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~3#1 := stop_simulation_#t~ret12#1;havoc stop_simulation_#t~ret12#1; 830#L394 assume 0 != stop_simulation_~tmp~3#1;stop_simulation_~__retres2~0#1 := 0; 828#L401 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 823#stop_simulation_returnLabel#1 start_simulation_#t~ret13#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret12#1, stop_simulation_~tmp~3#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp~4#1 := start_simulation_#t~ret13#1;havoc start_simulation_#t~ret13#1; 821#L436 assume !(0 != start_simulation_~tmp~4#1); 734#L419-2 [2023-11-12 02:32:18,035 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-12 02:32:18,035 INFO L85 PathProgramCache]: Analyzing trace with hash -1617647375, now seen corresponding path program 1 times [2023-11-12 02:32:18,035 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-12 02:32:18,036 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1384800208] [2023-11-12 02:32:18,036 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-12 02:32:18,036 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-12 02:32:18,050 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-12 02:32:18,137 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-12 02:32:18,138 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-12 02:32:18,138 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1384800208] [2023-11-12 02:32:18,138 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1384800208] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-12 02:32:18,139 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-12 02:32:18,139 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2023-11-12 02:32:18,139 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1364623622] [2023-11-12 02:32:18,139 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-12 02:32:18,140 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-12 02:32:18,141 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-12 02:32:18,141 INFO L85 PathProgramCache]: Analyzing trace with hash -518368045, now seen corresponding path program 1 times [2023-11-12 02:32:18,141 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-12 02:32:18,141 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [234378777] [2023-11-12 02:32:18,142 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-12 02:32:18,142 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-12 02:32:18,155 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-12 02:32:18,209 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-12 02:32:18,210 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-12 02:32:18,210 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [234378777] [2023-11-12 02:32:18,210 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [234378777] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-12 02:32:18,211 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-12 02:32:18,211 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2023-11-12 02:32:18,211 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [840725410] [2023-11-12 02:32:18,211 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-12 02:32:18,212 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-12 02:32:18,212 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-12 02:32:18,213 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2023-11-12 02:32:18,213 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2023-11-12 02:32:18,213 INFO L87 Difference]: Start difference. First operand 298 states and 430 transitions. cyclomatic complexity: 134 Second operand has 4 states, 4 states have (on average 6.5) internal successors, (26), 4 states have internal predecessors, (26), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-12 02:32:18,323 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-12 02:32:18,323 INFO L93 Difference]: Finished difference Result 683 states and 957 transitions. [2023-11-12 02:32:18,323 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 683 states and 957 transitions. [2023-11-12 02:32:18,330 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 620 [2023-11-12 02:32:18,338 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 683 states to 683 states and 957 transitions. [2023-11-12 02:32:18,338 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 683 [2023-11-12 02:32:18,339 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 683 [2023-11-12 02:32:18,339 INFO L73 IsDeterministic]: Start isDeterministic. Operand 683 states and 957 transitions. [2023-11-12 02:32:18,342 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-12 02:32:18,343 INFO L218 hiAutomatonCegarLoop]: Abstraction has 683 states and 957 transitions. [2023-11-12 02:32:18,344 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 683 states and 957 transitions. [2023-11-12 02:32:18,373 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 683 to 683. [2023-11-12 02:32:18,375 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 683 states, 683 states have (on average 1.4011713030746706) internal successors, (957), 682 states have internal predecessors, (957), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-12 02:32:18,379 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 683 states to 683 states and 957 transitions. [2023-11-12 02:32:18,379 INFO L240 hiAutomatonCegarLoop]: Abstraction has 683 states and 957 transitions. [2023-11-12 02:32:18,385 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2023-11-12 02:32:18,386 INFO L428 stractBuchiCegarLoop]: Abstraction has 683 states and 957 transitions. [2023-11-12 02:32:18,387 INFO L335 stractBuchiCegarLoop]: ======== Iteration 4 ============ [2023-11-12 02:32:18,387 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 683 states and 957 transitions. [2023-11-12 02:32:18,393 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 620 [2023-11-12 02:32:18,395 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-12 02:32:18,395 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-12 02:32:18,397 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-12 02:32:18,400 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-12 02:32:18,406 INFO L748 eck$LassoCheckResult]: Stem: 1687#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(19, 2);call #Ultimate.allocInit(12, 3);~q_buf_0~0 := 0;~q_free~0 := 0;~q_read_ev~0 := 0;~q_write_ev~0 := 0;~q_req_up~0 := 0;~q_ev~0 := 0;~p_num_write~0 := 0;~p_last_write~0 := 0;~p_dw_st~0 := 0;~p_dw_pc~0 := 0;~p_dw_i~0 := 0;~c_num_read~0 := 0;~c_last_read~0 := 0;~c_dr_st~0 := 0;~c_dr_pc~0 := 0;~c_dr_i~0 := 0;~a_t~0 := 0; 1688#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~3#1;havoc main_~__retres1~3#1;assume { :begin_inline_init_model } true;~q_free~0 := 1;~q_write_ev~0 := 2;~q_read_ev~0 := ~q_write_ev~0;~p_num_write~0 := 0;~p_dw_pc~0 := 0;~p_dw_i~0 := 1;~c_num_read~0 := 0;~c_dr_pc~0 := 0;~c_dr_i~0 := 1; 1721#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret13#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~4#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~4#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 1663#L222 assume !(1 == ~q_req_up~0); 1654#L222-2 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 1655#L237 assume 1 == ~p_dw_i~0;~p_dw_st~0 := 0; 1697#L237-2 assume 1 == ~c_dr_i~0;~c_dr_st~0 := 0; 1729#L242-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 1723#L275 assume 0 == ~q_read_ev~0;~q_read_ev~0 := 1; 1724#L275-2 assume 0 == ~q_write_ev~0;~q_write_ev~0 := 1; 1743#L280-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;assume { :begin_inline_is_do_write_p_triggered } true;havoc is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;havoc is_do_write_p_triggered_~__retres1~0#1; 1776#L65 assume !(1 == ~p_dw_pc~0); 1774#L65-2 is_do_write_p_triggered_~__retres1~0#1 := 0; 1773#L76 is_do_write_p_triggered_#res#1 := is_do_write_p_triggered_~__retres1~0#1; 1772#is_do_write_p_triggered_returnLabel#1 activate_threads_#t~ret7#1 := is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;assume { :end_inline_is_do_write_p_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1; 1771#L315 assume !(0 != activate_threads_~tmp~1#1); 1770#L315-2 assume { :begin_inline_is_do_read_c_triggered } true;havoc is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;havoc is_do_read_c_triggered_~__retres1~1#1; 1769#L84 assume !(1 == ~c_dr_pc~0); 1768#L84-2 is_do_read_c_triggered_~__retres1~1#1 := 0; 1767#L95 is_do_read_c_triggered_#res#1 := is_do_read_c_triggered_~__retres1~1#1; 1766#is_do_read_c_triggered_returnLabel#1 activate_threads_#t~ret8#1 := is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;assume { :end_inline_is_do_read_c_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 1765#L323 assume !(0 != activate_threads_~tmp___0~1#1); 1764#L323-2 havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1763#L293 assume !(1 == ~q_read_ev~0); 1762#L293-2 assume 1 == ~q_write_ev~0;~q_write_ev~0 := 2; 1739#L298-1 assume { :end_inline_reset_delta_events } true; 1740#L419-2 [2023-11-12 02:32:18,406 INFO L750 eck$LassoCheckResult]: Loop: 1740#L419-2 assume !false; 1858#L420 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret9#1, eval_#t~nondet10#1, eval_#t~nondet11#1, eval_~tmp~2#1, eval_~tmp___0~2#1, eval_~tmp___1~0#1;havoc eval_~tmp~2#1;havoc eval_~tmp___0~2#1;havoc eval_~tmp___1~0#1; 1720#L364 assume !false; 2033#L340 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 2032#L255 assume 0 == ~p_dw_st~0;exists_runnable_thread_~__retres1~2#1 := 1; 2030#L267 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 1837#exists_runnable_thread_returnLabel#1 eval_#t~ret9#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp___1~0#1 := eval_#t~ret9#1;havoc eval_#t~ret9#1; 1838#L344 assume !(0 != eval_~tmp___1~0#1); 2026#eval_returnLabel#1 havoc eval_#t~ret9#1, eval_#t~nondet10#1, eval_#t~nondet11#1, eval_~tmp~2#1, eval_~tmp___0~2#1, eval_~tmp___1~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 2089#L222-3 assume !(1 == ~q_req_up~0); 2087#L222-5 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 2085#L275-3 assume 0 == ~q_read_ev~0;~q_read_ev~0 := 1; 2080#L275-5 assume 0 == ~q_write_ev~0;~q_write_ev~0 := 1; 2081#L280-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;assume { :begin_inline_is_do_write_p_triggered } true;havoc is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;havoc is_do_write_p_triggered_~__retres1~0#1; 2093#L65-3 assume 1 == ~p_dw_pc~0; 2091#L66-1 assume 1 == ~q_read_ev~0;is_do_write_p_triggered_~__retres1~0#1 := 1; 2090#L76-1 is_do_write_p_triggered_#res#1 := is_do_write_p_triggered_~__retres1~0#1; 2088#is_do_write_p_triggered_returnLabel#2 activate_threads_#t~ret7#1 := is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;assume { :end_inline_is_do_write_p_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1; 2086#L315-3 assume !(0 != activate_threads_~tmp~1#1); 2082#L315-5 assume { :begin_inline_is_do_read_c_triggered } true;havoc is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;havoc is_do_read_c_triggered_~__retres1~1#1; 2079#L84-3 assume !(1 == ~c_dr_pc~0); 2077#L84-5 is_do_read_c_triggered_~__retres1~1#1 := 0; 2075#L95-1 is_do_read_c_triggered_#res#1 := is_do_read_c_triggered_~__retres1~1#1; 2072#is_do_read_c_triggered_returnLabel#2 activate_threads_#t~ret8#1 := is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;assume { :end_inline_is_do_read_c_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 2070#L323-3 assume 0 != activate_threads_~tmp___0~1#1;~c_dr_st~0 := 0; 2068#L323-5 havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 2066#L293-3 assume 1 == ~q_read_ev~0;~q_read_ev~0 := 2; 2050#L293-5 assume 1 == ~q_write_ev~0;~q_write_ev~0 := 2; 2049#L298-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret12#1, stop_simulation_~tmp~3#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~3#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 2048#L255-1 assume 0 == ~p_dw_st~0;exists_runnable_thread_~__retres1~2#1 := 1; 2046#L267-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 2045#exists_runnable_thread_returnLabel#2 stop_simulation_#t~ret12#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~3#1 := stop_simulation_#t~ret12#1;havoc stop_simulation_#t~ret12#1; 2044#L394 assume 0 != stop_simulation_~tmp~3#1;stop_simulation_~__retres2~0#1 := 0; 2038#L401 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 2036#stop_simulation_returnLabel#1 start_simulation_#t~ret13#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret12#1, stop_simulation_~tmp~3#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp~4#1 := start_simulation_#t~ret13#1;havoc start_simulation_#t~ret13#1; 1884#L436 assume !(0 != start_simulation_~tmp~4#1); 1740#L419-2 [2023-11-12 02:32:18,407 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-12 02:32:18,407 INFO L85 PathProgramCache]: Analyzing trace with hash 1964845233, now seen corresponding path program 1 times [2023-11-12 02:32:18,408 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-12 02:32:18,408 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [161947617] [2023-11-12 02:32:18,408 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-12 02:32:18,408 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-12 02:32:18,418 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-12 02:32:18,490 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-12 02:32:18,490 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-12 02:32:18,491 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [161947617] [2023-11-12 02:32:18,492 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [161947617] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-12 02:32:18,492 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-12 02:32:18,493 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-12 02:32:18,493 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [840278288] [2023-11-12 02:32:18,493 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-12 02:32:18,493 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-12 02:32:18,494 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-12 02:32:18,494 INFO L85 PathProgramCache]: Analyzing trace with hash -518368045, now seen corresponding path program 2 times [2023-11-12 02:32:18,495 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-12 02:32:18,499 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [133759816] [2023-11-12 02:32:18,500 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-12 02:32:18,500 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-12 02:32:18,511 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-12 02:32:18,587 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-12 02:32:18,588 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-12 02:32:18,588 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [133759816] [2023-11-12 02:32:18,588 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [133759816] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-12 02:32:18,589 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-12 02:32:18,589 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2023-11-12 02:32:18,589 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [992232408] [2023-11-12 02:32:18,590 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-12 02:32:18,590 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-12 02:32:18,591 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-12 02:32:18,591 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-12 02:32:18,592 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-12 02:32:18,592 INFO L87 Difference]: Start difference. First operand 683 states and 957 transitions. cyclomatic complexity: 278 Second operand has 3 states, 3 states have (on average 8.666666666666666) internal successors, (26), 3 states have internal predecessors, (26), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-12 02:32:18,631 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-12 02:32:18,631 INFO L93 Difference]: Finished difference Result 952 states and 1311 transitions. [2023-11-12 02:32:18,631 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 952 states and 1311 transitions. [2023-11-12 02:32:18,641 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 906 [2023-11-12 02:32:18,651 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 952 states to 952 states and 1311 transitions. [2023-11-12 02:32:18,651 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 952 [2023-11-12 02:32:18,653 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 952 [2023-11-12 02:32:18,653 INFO L73 IsDeterministic]: Start isDeterministic. Operand 952 states and 1311 transitions. [2023-11-12 02:32:18,655 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-12 02:32:18,655 INFO L218 hiAutomatonCegarLoop]: Abstraction has 952 states and 1311 transitions. [2023-11-12 02:32:18,656 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 952 states and 1311 transitions. [2023-11-12 02:32:18,674 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 952 to 680. [2023-11-12 02:32:18,675 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 680 states, 680 states have (on average 1.3794117647058823) internal successors, (938), 679 states have internal predecessors, (938), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-12 02:32:18,679 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 680 states to 680 states and 938 transitions. [2023-11-12 02:32:18,680 INFO L240 hiAutomatonCegarLoop]: Abstraction has 680 states and 938 transitions. [2023-11-12 02:32:18,680 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-12 02:32:18,684 INFO L428 stractBuchiCegarLoop]: Abstraction has 680 states and 938 transitions. [2023-11-12 02:32:18,684 INFO L335 stractBuchiCegarLoop]: ======== Iteration 5 ============ [2023-11-12 02:32:18,687 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 680 states and 938 transitions. [2023-11-12 02:32:18,692 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 636 [2023-11-12 02:32:18,693 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-12 02:32:18,693 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-12 02:32:18,696 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-12 02:32:18,696 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-12 02:32:18,697 INFO L748 eck$LassoCheckResult]: Stem: 3329#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(19, 2);call #Ultimate.allocInit(12, 3);~q_buf_0~0 := 0;~q_free~0 := 0;~q_read_ev~0 := 0;~q_write_ev~0 := 0;~q_req_up~0 := 0;~q_ev~0 := 0;~p_num_write~0 := 0;~p_last_write~0 := 0;~p_dw_st~0 := 0;~p_dw_pc~0 := 0;~p_dw_i~0 := 0;~c_num_read~0 := 0;~c_last_read~0 := 0;~c_dr_st~0 := 0;~c_dr_pc~0 := 0;~c_dr_i~0 := 0;~a_t~0 := 0; 3330#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~3#1;havoc main_~__retres1~3#1;assume { :begin_inline_init_model } true;~q_free~0 := 1;~q_write_ev~0 := 2;~q_read_ev~0 := ~q_write_ev~0;~p_num_write~0 := 0;~p_dw_pc~0 := 0;~p_dw_i~0 := 1;~c_num_read~0 := 0;~c_dr_pc~0 := 0;~c_dr_i~0 := 1; 3361#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret13#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~4#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~4#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 3307#L222 assume !(1 == ~q_req_up~0); 3296#L222-2 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 3297#L237 assume 1 == ~p_dw_i~0;~p_dw_st~0 := 0; 3342#L237-2 assume 1 == ~c_dr_i~0;~c_dr_st~0 := 0; 3369#L242-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 3367#L275 assume !(0 == ~q_read_ev~0); 3368#L275-2 assume 0 == ~q_write_ev~0;~q_write_ev~0 := 1; 3380#L280-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;assume { :begin_inline_is_do_write_p_triggered } true;havoc is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;havoc is_do_write_p_triggered_~__retres1~0#1; 3399#L65 assume !(1 == ~p_dw_pc~0); 3344#L65-2 is_do_write_p_triggered_~__retres1~0#1 := 0; 3397#L76 is_do_write_p_triggered_#res#1 := is_do_write_p_triggered_~__retres1~0#1; 3398#is_do_write_p_triggered_returnLabel#1 activate_threads_#t~ret7#1 := is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;assume { :end_inline_is_do_write_p_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1; 3377#L315 assume !(0 != activate_threads_~tmp~1#1); 3378#L315-2 assume { :begin_inline_is_do_read_c_triggered } true;havoc is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;havoc is_do_read_c_triggered_~__retres1~1#1; 3385#L84 assume !(1 == ~c_dr_pc~0); 3386#L84-2 is_do_read_c_triggered_~__retres1~1#1 := 0; 3315#L95 is_do_read_c_triggered_#res#1 := is_do_read_c_triggered_~__retres1~1#1; 3316#is_do_read_c_triggered_returnLabel#1 activate_threads_#t~ret8#1 := is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;assume { :end_inline_is_do_read_c_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 3281#L323 assume !(0 != activate_threads_~tmp___0~1#1); 3282#L323-2 havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 3387#L293 assume !(1 == ~q_read_ev~0); 3388#L293-2 assume 1 == ~q_write_ev~0;~q_write_ev~0 := 2; 3276#L298-1 assume { :end_inline_reset_delta_events } true; 3379#L419-2 [2023-11-12 02:32:18,699 INFO L750 eck$LassoCheckResult]: Loop: 3379#L419-2 assume !false; 3435#L420 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret9#1, eval_#t~nondet10#1, eval_#t~nondet11#1, eval_~tmp~2#1, eval_~tmp___0~2#1, eval_~tmp___1~0#1;havoc eval_~tmp~2#1;havoc eval_~tmp___0~2#1;havoc eval_~tmp___1~0#1; 3364#L364 assume !false; 3434#L340 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 3433#L255 assume 0 == ~p_dw_st~0;exists_runnable_thread_~__retres1~2#1 := 1; 3431#L267 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 3429#exists_runnable_thread_returnLabel#1 eval_#t~ret9#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp___1~0#1 := eval_#t~ret9#1;havoc eval_#t~ret9#1; 3426#L344 assume !(0 != eval_~tmp___1~0#1); 3427#eval_returnLabel#1 havoc eval_#t~ret9#1, eval_#t~nondet10#1, eval_#t~nondet11#1, eval_~tmp~2#1, eval_~tmp___0~2#1, eval_~tmp___1~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 3469#L222-3 assume !(1 == ~q_req_up~0); 3467#L222-5 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 3465#L275-3 assume !(0 == ~q_read_ev~0); 3462#L275-5 assume 0 == ~q_write_ev~0;~q_write_ev~0 := 1; 3461#L280-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;assume { :begin_inline_is_do_write_p_triggered } true;havoc is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;havoc is_do_write_p_triggered_~__retres1~0#1; 3460#L65-3 assume !(1 == ~p_dw_pc~0); 3458#L65-5 is_do_write_p_triggered_~__retres1~0#1 := 0; 3457#L76-1 is_do_write_p_triggered_#res#1 := is_do_write_p_triggered_~__retres1~0#1; 3456#is_do_write_p_triggered_returnLabel#2 activate_threads_#t~ret7#1 := is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;assume { :end_inline_is_do_write_p_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1; 3455#L315-3 assume !(0 != activate_threads_~tmp~1#1); 3454#L315-5 assume { :begin_inline_is_do_read_c_triggered } true;havoc is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;havoc is_do_read_c_triggered_~__retres1~1#1; 3453#L84-3 assume !(1 == ~c_dr_pc~0); 3452#L84-5 is_do_read_c_triggered_~__retres1~1#1 := 0; 3451#L95-1 is_do_read_c_triggered_#res#1 := is_do_read_c_triggered_~__retres1~1#1; 3450#is_do_read_c_triggered_returnLabel#2 activate_threads_#t~ret8#1 := is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;assume { :end_inline_is_do_read_c_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 3449#L323-3 assume 0 != activate_threads_~tmp___0~1#1;~c_dr_st~0 := 0; 3448#L323-5 havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 3447#L293-3 assume !(1 == ~q_read_ev~0); 3445#L293-5 assume 1 == ~q_write_ev~0;~q_write_ev~0 := 2; 3444#L298-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret12#1, stop_simulation_~tmp~3#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~3#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 3443#L255-1 assume 0 == ~p_dw_st~0;exists_runnable_thread_~__retres1~2#1 := 1; 3441#L267-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 3440#exists_runnable_thread_returnLabel#2 stop_simulation_#t~ret12#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~3#1 := stop_simulation_#t~ret12#1;havoc stop_simulation_#t~ret12#1; 3439#L394 assume 0 != stop_simulation_~tmp~3#1;stop_simulation_~__retres2~0#1 := 0; 3438#L401 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 3437#stop_simulation_returnLabel#1 start_simulation_#t~ret13#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret12#1, stop_simulation_~tmp~3#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp~4#1 := start_simulation_#t~ret13#1;havoc start_simulation_#t~ret13#1; 3436#L436 assume !(0 != start_simulation_~tmp~4#1); 3379#L419-2 [2023-11-12 02:32:18,700 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-12 02:32:18,707 INFO L85 PathProgramCache]: Analyzing trace with hash -29299473, now seen corresponding path program 1 times [2023-11-12 02:32:18,707 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-12 02:32:18,707 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [642226765] [2023-11-12 02:32:18,708 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-12 02:32:18,708 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-12 02:32:18,726 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-12 02:32:18,783 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-12 02:32:18,784 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-12 02:32:18,784 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [642226765] [2023-11-12 02:32:18,784 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [642226765] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-12 02:32:18,784 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-12 02:32:18,784 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2023-11-12 02:32:18,785 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [940259164] [2023-11-12 02:32:18,785 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-12 02:32:18,786 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-12 02:32:18,788 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-12 02:32:18,788 INFO L85 PathProgramCache]: Analyzing trace with hash -884233102, now seen corresponding path program 1 times [2023-11-12 02:32:18,788 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-12 02:32:18,789 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [855963988] [2023-11-12 02:32:18,789 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-12 02:32:18,789 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-12 02:32:18,813 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-12 02:32:18,856 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-12 02:32:18,856 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-12 02:32:18,856 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [855963988] [2023-11-12 02:32:18,856 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [855963988] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-12 02:32:18,857 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-12 02:32:18,857 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2023-11-12 02:32:18,857 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1862506786] [2023-11-12 02:32:18,857 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-12 02:32:18,858 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-12 02:32:18,858 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-12 02:32:18,858 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2023-11-12 02:32:18,858 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2023-11-12 02:32:18,859 INFO L87 Difference]: Start difference. First operand 680 states and 938 transitions. cyclomatic complexity: 260 Second operand has 4 states, 4 states have (on average 6.5) internal successors, (26), 4 states have internal predecessors, (26), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-12 02:32:18,922 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-12 02:32:18,922 INFO L93 Difference]: Finished difference Result 830 states and 1136 transitions. [2023-11-12 02:32:18,922 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 830 states and 1136 transitions. [2023-11-12 02:32:18,930 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 802 [2023-11-12 02:32:18,938 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 830 states to 830 states and 1136 transitions. [2023-11-12 02:32:18,938 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 830 [2023-11-12 02:32:18,939 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 830 [2023-11-12 02:32:18,940 INFO L73 IsDeterministic]: Start isDeterministic. Operand 830 states and 1136 transitions. [2023-11-12 02:32:18,941 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-12 02:32:18,941 INFO L218 hiAutomatonCegarLoop]: Abstraction has 830 states and 1136 transitions. [2023-11-12 02:32:18,942 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 830 states and 1136 transitions. [2023-11-12 02:32:18,953 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 830 to 608. [2023-11-12 02:32:18,954 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 608 states, 608 states have (on average 1.3717105263157894) internal successors, (834), 607 states have internal predecessors, (834), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-12 02:32:18,957 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 608 states to 608 states and 834 transitions. [2023-11-12 02:32:18,958 INFO L240 hiAutomatonCegarLoop]: Abstraction has 608 states and 834 transitions. [2023-11-12 02:32:18,958 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2023-11-12 02:32:18,964 INFO L428 stractBuchiCegarLoop]: Abstraction has 608 states and 834 transitions. [2023-11-12 02:32:18,964 INFO L335 stractBuchiCegarLoop]: ======== Iteration 6 ============ [2023-11-12 02:32:18,964 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 608 states and 834 transitions. [2023-11-12 02:32:18,968 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 580 [2023-11-12 02:32:18,969 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-12 02:32:18,969 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-12 02:32:18,971 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-12 02:32:18,971 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-12 02:32:18,971 INFO L748 eck$LassoCheckResult]: Stem: 4854#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(19, 2);call #Ultimate.allocInit(12, 3);~q_buf_0~0 := 0;~q_free~0 := 0;~q_read_ev~0 := 0;~q_write_ev~0 := 0;~q_req_up~0 := 0;~q_ev~0 := 0;~p_num_write~0 := 0;~p_last_write~0 := 0;~p_dw_st~0 := 0;~p_dw_pc~0 := 0;~p_dw_i~0 := 0;~c_num_read~0 := 0;~c_last_read~0 := 0;~c_dr_st~0 := 0;~c_dr_pc~0 := 0;~c_dr_i~0 := 0;~a_t~0 := 0; 4855#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~3#1;havoc main_~__retres1~3#1;assume { :begin_inline_init_model } true;~q_free~0 := 1;~q_write_ev~0 := 2;~q_read_ev~0 := ~q_write_ev~0;~p_num_write~0 := 0;~p_dw_pc~0 := 0;~p_dw_i~0 := 1;~c_num_read~0 := 0;~c_dr_pc~0 := 0;~c_dr_i~0 := 1; 4879#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret13#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~4#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~4#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 4830#L222 assume !(1 == ~q_req_up~0); 4821#L222-2 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 4822#L237 assume 1 == ~p_dw_i~0;~p_dw_st~0 := 0; 4862#L237-2 assume 1 == ~c_dr_i~0;~c_dr_st~0 := 0; 4885#L242-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 4881#L275 assume !(0 == ~q_read_ev~0); 4882#L275-2 assume !(0 == ~q_write_ev~0); 4868#L280-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;assume { :begin_inline_is_do_write_p_triggered } true;havoc is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;havoc is_do_write_p_triggered_~__retres1~0#1; 4869#L65 assume !(1 == ~p_dw_pc~0); 4866#L65-2 is_do_write_p_triggered_~__retres1~0#1 := 0; 4875#L76 is_do_write_p_triggered_#res#1 := is_do_write_p_triggered_~__retres1~0#1; 4849#is_do_write_p_triggered_returnLabel#1 activate_threads_#t~ret7#1 := is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;assume { :end_inline_is_do_write_p_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1; 4850#L315 assume !(0 != activate_threads_~tmp~1#1); 4827#L315-2 assume { :begin_inline_is_do_read_c_triggered } true;havoc is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;havoc is_do_read_c_triggered_~__retres1~1#1; 4828#L84 assume !(1 == ~c_dr_pc~0); 4845#L84-2 is_do_read_c_triggered_~__retres1~1#1 := 0; 4839#L95 is_do_read_c_triggered_#res#1 := is_do_read_c_triggered_~__retres1~1#1; 4840#is_do_read_c_triggered_returnLabel#1 activate_threads_#t~ret8#1 := is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;assume { :end_inline_is_do_read_c_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 4803#L323 assume !(0 != activate_threads_~tmp___0~1#1); 4804#L323-2 havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 4894#L293 assume !(1 == ~q_read_ev~0); 4797#L293-2 assume !(1 == ~q_write_ev~0); 4798#L298-1 assume { :end_inline_reset_delta_events } true; 4889#L419-2 [2023-11-12 02:32:18,972 INFO L750 eck$LassoCheckResult]: Loop: 4889#L419-2 assume !false; 5199#L420 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret9#1, eval_#t~nondet10#1, eval_#t~nondet11#1, eval_~tmp~2#1, eval_~tmp___0~2#1, eval_~tmp___1~0#1;havoc eval_~tmp~2#1;havoc eval_~tmp___0~2#1;havoc eval_~tmp___1~0#1; 4835#L364 assume !false; 5190#L340 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 5168#L255 assume 0 == ~p_dw_st~0;exists_runnable_thread_~__retres1~2#1 := 1; 5164#L267 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 5162#exists_runnable_thread_returnLabel#1 eval_#t~ret9#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp___1~0#1 := eval_#t~ret9#1;havoc eval_#t~ret9#1; 5159#L344 assume !(0 != eval_~tmp___1~0#1); 5160#eval_returnLabel#1 havoc eval_#t~ret9#1, eval_#t~nondet10#1, eval_#t~nondet11#1, eval_~tmp~2#1, eval_~tmp___0~2#1, eval_~tmp___1~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 5296#L222-3 assume !(1 == ~q_req_up~0); 5294#L222-5 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 5293#L275-3 assume !(0 == ~q_read_ev~0); 5291#L275-5 assume !(0 == ~q_write_ev~0); 5290#L280-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;assume { :begin_inline_is_do_write_p_triggered } true;havoc is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;havoc is_do_write_p_triggered_~__retres1~0#1; 5289#L65-3 assume !(1 == ~p_dw_pc~0); 5287#L65-5 is_do_write_p_triggered_~__retres1~0#1 := 0; 5286#L76-1 is_do_write_p_triggered_#res#1 := is_do_write_p_triggered_~__retres1~0#1; 5285#is_do_write_p_triggered_returnLabel#2 activate_threads_#t~ret7#1 := is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;assume { :end_inline_is_do_write_p_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1; 5284#L315-3 assume !(0 != activate_threads_~tmp~1#1); 5282#L315-5 assume { :begin_inline_is_do_read_c_triggered } true;havoc is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;havoc is_do_read_c_triggered_~__retres1~1#1; 5279#L84-3 assume !(1 == ~c_dr_pc~0); 5277#L84-5 is_do_read_c_triggered_~__retres1~1#1 := 0; 5275#L95-1 is_do_read_c_triggered_#res#1 := is_do_read_c_triggered_~__retres1~1#1; 5235#is_do_read_c_triggered_returnLabel#2 activate_threads_#t~ret8#1 := is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;assume { :end_inline_is_do_read_c_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 5234#L323-3 assume 0 != activate_threads_~tmp___0~1#1;~c_dr_st~0 := 0; 5233#L323-5 havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 5231#L293-3 assume !(1 == ~q_read_ev~0); 5229#L293-5 assume !(1 == ~q_write_ev~0); 5228#L298-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret12#1, stop_simulation_~tmp~3#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~3#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 5227#L255-1 assume 0 == ~p_dw_st~0;exists_runnable_thread_~__retres1~2#1 := 1; 5225#L267-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 5221#exists_runnable_thread_returnLabel#2 stop_simulation_#t~ret12#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~3#1 := stop_simulation_#t~ret12#1;havoc stop_simulation_#t~ret12#1; 5218#L394 assume 0 != stop_simulation_~tmp~3#1;stop_simulation_~__retres2~0#1 := 0; 5214#L401 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 5210#stop_simulation_returnLabel#1 start_simulation_#t~ret13#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret12#1, stop_simulation_~tmp~3#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp~4#1 := start_simulation_#t~ret13#1;havoc start_simulation_#t~ret13#1; 5206#L436 assume !(0 != start_simulation_~tmp~4#1); 4889#L419-2 [2023-11-12 02:32:18,972 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-12 02:32:18,973 INFO L85 PathProgramCache]: Analyzing trace with hash -1617647313, now seen corresponding path program 1 times [2023-11-12 02:32:18,973 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-12 02:32:18,973 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1352046470] [2023-11-12 02:32:18,973 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-12 02:32:18,973 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-12 02:32:18,985 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-12 02:32:18,986 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-12 02:32:18,995 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-12 02:32:19,025 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-12 02:32:19,025 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-12 02:32:19,026 INFO L85 PathProgramCache]: Analyzing trace with hash -338188238, now seen corresponding path program 1 times [2023-11-12 02:32:19,026 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-12 02:32:19,026 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [794005044] [2023-11-12 02:32:19,026 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-12 02:32:19,026 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-12 02:32:19,045 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-12 02:32:19,090 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-12 02:32:19,090 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-12 02:32:19,093 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [794005044] [2023-11-12 02:32:19,095 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [794005044] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-12 02:32:19,095 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-12 02:32:19,095 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2023-11-12 02:32:19,095 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [634604111] [2023-11-12 02:32:19,096 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-12 02:32:19,096 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-12 02:32:19,096 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-12 02:32:19,097 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2023-11-12 02:32:19,097 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2023-11-12 02:32:19,097 INFO L87 Difference]: Start difference. First operand 608 states and 834 transitions. cyclomatic complexity: 228 Second operand has 5 states, 5 states have (on average 7.2) internal successors, (36), 5 states have internal predecessors, (36), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-12 02:32:19,180 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-12 02:32:19,180 INFO L93 Difference]: Finished difference Result 919 states and 1251 transitions. [2023-11-12 02:32:19,180 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 919 states and 1251 transitions. [2023-11-12 02:32:19,191 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 890 [2023-11-12 02:32:19,199 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 919 states to 919 states and 1251 transitions. [2023-11-12 02:32:19,199 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 919 [2023-11-12 02:32:19,200 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 919 [2023-11-12 02:32:19,201 INFO L73 IsDeterministic]: Start isDeterministic. Operand 919 states and 1251 transitions. [2023-11-12 02:32:19,202 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-12 02:32:19,202 INFO L218 hiAutomatonCegarLoop]: Abstraction has 919 states and 1251 transitions. [2023-11-12 02:32:19,204 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 919 states and 1251 transitions. [2023-11-12 02:32:19,215 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 919 to 635. [2023-11-12 02:32:19,217 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 635 states, 635 states have (on average 1.3559055118110237) internal successors, (861), 634 states have internal predecessors, (861), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-12 02:32:19,220 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 635 states to 635 states and 861 transitions. [2023-11-12 02:32:19,220 INFO L240 hiAutomatonCegarLoop]: Abstraction has 635 states and 861 transitions. [2023-11-12 02:32:19,221 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 9 states. [2023-11-12 02:32:19,223 INFO L428 stractBuchiCegarLoop]: Abstraction has 635 states and 861 transitions. [2023-11-12 02:32:19,223 INFO L335 stractBuchiCegarLoop]: ======== Iteration 7 ============ [2023-11-12 02:32:19,223 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 635 states and 861 transitions. [2023-11-12 02:32:19,227 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 607 [2023-11-12 02:32:19,227 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-12 02:32:19,227 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-12 02:32:19,229 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-12 02:32:19,230 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-12 02:32:19,231 INFO L748 eck$LassoCheckResult]: Stem: 6401#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(19, 2);call #Ultimate.allocInit(12, 3);~q_buf_0~0 := 0;~q_free~0 := 0;~q_read_ev~0 := 0;~q_write_ev~0 := 0;~q_req_up~0 := 0;~q_ev~0 := 0;~p_num_write~0 := 0;~p_last_write~0 := 0;~p_dw_st~0 := 0;~p_dw_pc~0 := 0;~p_dw_i~0 := 0;~c_num_read~0 := 0;~c_last_read~0 := 0;~c_dr_st~0 := 0;~c_dr_pc~0 := 0;~c_dr_i~0 := 0;~a_t~0 := 0; 6402#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~3#1;havoc main_~__retres1~3#1;assume { :begin_inline_init_model } true;~q_free~0 := 1;~q_write_ev~0 := 2;~q_read_ev~0 := ~q_write_ev~0;~p_num_write~0 := 0;~p_dw_pc~0 := 0;~p_dw_i~0 := 1;~c_num_read~0 := 0;~c_dr_pc~0 := 0;~c_dr_i~0 := 1; 6429#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret13#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~4#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~4#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 6375#L222 assume !(1 == ~q_req_up~0); 6366#L222-2 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 6367#L237 assume 1 == ~p_dw_i~0;~p_dw_st~0 := 0; 6409#L237-2 assume 1 == ~c_dr_i~0;~c_dr_st~0 := 0; 6434#L242-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 6431#L275 assume !(0 == ~q_read_ev~0); 6432#L275-2 assume !(0 == ~q_write_ev~0); 6416#L280-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;assume { :begin_inline_is_do_write_p_triggered } true;havoc is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;havoc is_do_write_p_triggered_~__retres1~0#1; 6417#L65 assume !(1 == ~p_dw_pc~0); 6411#L65-2 is_do_write_p_triggered_~__retres1~0#1 := 0; 6425#L76 is_do_write_p_triggered_#res#1 := is_do_write_p_triggered_~__retres1~0#1; 6396#is_do_write_p_triggered_returnLabel#1 activate_threads_#t~ret7#1 := is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;assume { :end_inline_is_do_write_p_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1; 6397#L315 assume !(0 != activate_threads_~tmp~1#1); 6372#L315-2 assume { :begin_inline_is_do_read_c_triggered } true;havoc is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;havoc is_do_read_c_triggered_~__retres1~1#1; 6373#L84 assume !(1 == ~c_dr_pc~0); 6391#L84-2 is_do_read_c_triggered_~__retres1~1#1 := 0; 6384#L95 is_do_read_c_triggered_#res#1 := is_do_read_c_triggered_~__retres1~1#1; 6385#is_do_read_c_triggered_returnLabel#1 activate_threads_#t~ret8#1 := is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;assume { :end_inline_is_do_read_c_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 6348#L323 assume !(0 != activate_threads_~tmp___0~1#1); 6349#L323-2 havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 6453#L293 assume !(1 == ~q_read_ev~0); 6341#L293-2 assume !(1 == ~q_write_ev~0); 6342#L298-1 assume { :end_inline_reset_delta_events } true; 6444#L419-2 [2023-11-12 02:32:19,231 INFO L750 eck$LassoCheckResult]: Loop: 6444#L419-2 assume !false; 6917#L420 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret9#1, eval_#t~nondet10#1, eval_#t~nondet11#1, eval_~tmp~2#1, eval_~tmp___0~2#1, eval_~tmp___1~0#1;havoc eval_~tmp~2#1;havoc eval_~tmp___0~2#1;havoc eval_~tmp___1~0#1; 6378#L364 assume !false; 6414#L340 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 6415#L255 assume !(0 == ~p_dw_st~0); 6916#L259 assume !(0 == ~c_dr_st~0);exists_runnable_thread_~__retres1~2#1 := 0; 6913#L267 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 6910#exists_runnable_thread_returnLabel#1 eval_#t~ret9#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp___1~0#1 := eval_#t~ret9#1;havoc eval_#t~ret9#1; 6484#L344 assume !(0 != eval_~tmp___1~0#1); 6380#eval_returnLabel#1 havoc eval_#t~ret9#1, eval_#t~nondet10#1, eval_#t~nondet11#1, eval_~tmp~2#1, eval_~tmp___0~2#1, eval_~tmp___1~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 6381#L222-3 assume !(1 == ~q_req_up~0); 6945#L222-5 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 6944#L275-3 assume !(0 == ~q_read_ev~0); 6943#L275-5 assume !(0 == ~q_write_ev~0); 6942#L280-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;assume { :begin_inline_is_do_write_p_triggered } true;havoc is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;havoc is_do_write_p_triggered_~__retres1~0#1; 6941#L65-3 assume !(1 == ~p_dw_pc~0); 6939#L65-5 is_do_write_p_triggered_~__retres1~0#1 := 0; 6938#L76-1 is_do_write_p_triggered_#res#1 := is_do_write_p_triggered_~__retres1~0#1; 6937#is_do_write_p_triggered_returnLabel#2 activate_threads_#t~ret7#1 := is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;assume { :end_inline_is_do_write_p_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1; 6936#L315-3 assume !(0 != activate_threads_~tmp~1#1); 6935#L315-5 assume { :begin_inline_is_do_read_c_triggered } true;havoc is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;havoc is_do_read_c_triggered_~__retres1~1#1; 6934#L84-3 assume !(1 == ~c_dr_pc~0); 6933#L84-5 is_do_read_c_triggered_~__retres1~1#1 := 0; 6932#L95-1 is_do_read_c_triggered_#res#1 := is_do_read_c_triggered_~__retres1~1#1; 6931#is_do_read_c_triggered_returnLabel#2 activate_threads_#t~ret8#1 := is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;assume { :end_inline_is_do_read_c_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 6930#L323-3 assume 0 != activate_threads_~tmp___0~1#1;~c_dr_st~0 := 0; 6929#L323-5 havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 6928#L293-3 assume !(1 == ~q_read_ev~0); 6927#L293-5 assume !(1 == ~q_write_ev~0); 6926#L298-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret12#1, stop_simulation_~tmp~3#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~3#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 6925#L255-1 assume 0 == ~p_dw_st~0;exists_runnable_thread_~__retres1~2#1 := 1; 6923#L267-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 6922#exists_runnable_thread_returnLabel#2 stop_simulation_#t~ret12#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~3#1 := stop_simulation_#t~ret12#1;havoc stop_simulation_#t~ret12#1; 6921#L394 assume 0 != stop_simulation_~tmp~3#1;stop_simulation_~__retres2~0#1 := 0; 6920#L401 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 6919#stop_simulation_returnLabel#1 start_simulation_#t~ret13#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret12#1, stop_simulation_~tmp~3#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp~4#1 := start_simulation_#t~ret13#1;havoc start_simulation_#t~ret13#1; 6918#L436 assume !(0 != start_simulation_~tmp~4#1); 6444#L419-2 [2023-11-12 02:32:19,233 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-12 02:32:19,237 INFO L85 PathProgramCache]: Analyzing trace with hash -1617647313, now seen corresponding path program 2 times [2023-11-12 02:32:19,237 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-12 02:32:19,237 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [748956738] [2023-11-12 02:32:19,237 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-12 02:32:19,237 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-12 02:32:19,247 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-12 02:32:19,247 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-12 02:32:19,251 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-12 02:32:19,259 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-12 02:32:19,261 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-12 02:32:19,261 INFO L85 PathProgramCache]: Analyzing trace with hash 22665520, now seen corresponding path program 1 times [2023-11-12 02:32:19,261 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-12 02:32:19,261 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [172678735] [2023-11-12 02:32:19,262 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-12 02:32:19,262 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-12 02:32:19,269 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-12 02:32:19,299 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-12 02:32:19,299 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-12 02:32:19,299 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [172678735] [2023-11-12 02:32:19,299 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [172678735] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-12 02:32:19,299 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-12 02:32:19,300 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-12 02:32:19,300 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2020377726] [2023-11-12 02:32:19,300 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-12 02:32:19,300 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-12 02:32:19,300 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-12 02:32:19,301 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-12 02:32:19,301 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-12 02:32:19,301 INFO L87 Difference]: Start difference. First operand 635 states and 861 transitions. cyclomatic complexity: 228 Second operand has 3 states, 3 states have (on average 12.333333333333334) internal successors, (37), 3 states have internal predecessors, (37), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-12 02:32:19,334 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-12 02:32:19,335 INFO L93 Difference]: Finished difference Result 985 states and 1288 transitions. [2023-11-12 02:32:19,335 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 985 states and 1288 transitions. [2023-11-12 02:32:19,343 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 935 [2023-11-12 02:32:19,351 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 985 states to 985 states and 1288 transitions. [2023-11-12 02:32:19,351 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 985 [2023-11-12 02:32:19,353 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 985 [2023-11-12 02:32:19,353 INFO L73 IsDeterministic]: Start isDeterministic. Operand 985 states and 1288 transitions. [2023-11-12 02:32:19,354 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-12 02:32:19,354 INFO L218 hiAutomatonCegarLoop]: Abstraction has 985 states and 1288 transitions. [2023-11-12 02:32:19,356 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 985 states and 1288 transitions. [2023-11-12 02:32:19,371 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 985 to 985. [2023-11-12 02:32:19,373 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 985 states, 985 states have (on average 1.3076142131979696) internal successors, (1288), 984 states have internal predecessors, (1288), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-12 02:32:19,377 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 985 states to 985 states and 1288 transitions. [2023-11-12 02:32:19,378 INFO L240 hiAutomatonCegarLoop]: Abstraction has 985 states and 1288 transitions. [2023-11-12 02:32:19,378 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-12 02:32:19,380 INFO L428 stractBuchiCegarLoop]: Abstraction has 985 states and 1288 transitions. [2023-11-12 02:32:19,380 INFO L335 stractBuchiCegarLoop]: ======== Iteration 8 ============ [2023-11-12 02:32:19,380 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 985 states and 1288 transitions. [2023-11-12 02:32:19,386 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 935 [2023-11-12 02:32:19,387 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-12 02:32:19,387 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-12 02:32:19,388 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-12 02:32:19,388 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-12 02:32:19,388 INFO L748 eck$LassoCheckResult]: Stem: 8028#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(19, 2);call #Ultimate.allocInit(12, 3);~q_buf_0~0 := 0;~q_free~0 := 0;~q_read_ev~0 := 0;~q_write_ev~0 := 0;~q_req_up~0 := 0;~q_ev~0 := 0;~p_num_write~0 := 0;~p_last_write~0 := 0;~p_dw_st~0 := 0;~p_dw_pc~0 := 0;~p_dw_i~0 := 0;~c_num_read~0 := 0;~c_last_read~0 := 0;~c_dr_st~0 := 0;~c_dr_pc~0 := 0;~c_dr_i~0 := 0;~a_t~0 := 0; 8029#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~3#1;havoc main_~__retres1~3#1;assume { :begin_inline_init_model } true;~q_free~0 := 1;~q_write_ev~0 := 2;~q_read_ev~0 := ~q_write_ev~0;~p_num_write~0 := 0;~p_dw_pc~0 := 0;~p_dw_i~0 := 1;~c_num_read~0 := 0;~c_dr_pc~0 := 0;~c_dr_i~0 := 1; 8061#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret13#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~4#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~4#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 8002#L222 assume !(1 == ~q_req_up~0); 7990#L222-2 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 7991#L237 assume !(1 == ~p_dw_i~0);~p_dw_st~0 := 2; 8041#L237-2 assume 1 == ~c_dr_i~0;~c_dr_st~0 := 0; 8082#L242-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 8083#L275 assume !(0 == ~q_read_ev~0); 8084#L275-2 assume !(0 == ~q_write_ev~0); 8085#L280-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;assume { :begin_inline_is_do_write_p_triggered } true;havoc is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;havoc is_do_write_p_triggered_~__retres1~0#1; 8111#L65 assume !(1 == ~p_dw_pc~0); 8044#L65-2 is_do_write_p_triggered_~__retres1~0#1 := 0; 8109#L76 is_do_write_p_triggered_#res#1 := is_do_write_p_triggered_~__retres1~0#1; 8110#is_do_write_p_triggered_returnLabel#1 activate_threads_#t~ret7#1 := is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;assume { :end_inline_is_do_write_p_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1; 8075#L315 assume 0 != activate_threads_~tmp~1#1;~p_dw_st~0 := 0; 7998#L315-2 assume { :begin_inline_is_do_read_c_triggered } true;havoc is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;havoc is_do_read_c_triggered_~__retres1~1#1; 7999#L84 assume !(1 == ~c_dr_pc~0); 8017#L84-2 is_do_read_c_triggered_~__retres1~1#1 := 0; 8018#L95 is_do_read_c_triggered_#res#1 := is_do_read_c_triggered_~__retres1~1#1; 8035#is_do_read_c_triggered_returnLabel#1 activate_threads_#t~ret8#1 := is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;assume { :end_inline_is_do_read_c_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 8036#L323 assume !(0 != activate_threads_~tmp___0~1#1); 8103#L323-2 havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 8104#L293 assume !(1 == ~q_read_ev~0); 7967#L293-2 assume !(1 == ~q_write_ev~0); 7968#L298-1 assume { :end_inline_reset_delta_events } true; 8477#L419-2 [2023-11-12 02:32:19,388 INFO L750 eck$LassoCheckResult]: Loop: 8477#L419-2 assume !false; 8472#L420 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret9#1, eval_#t~nondet10#1, eval_#t~nondet11#1, eval_~tmp~2#1, eval_~tmp___0~2#1, eval_~tmp___1~0#1;havoc eval_~tmp~2#1;havoc eval_~tmp___0~2#1;havoc eval_~tmp___1~0#1; 8469#L364 assume !false; 8464#L340 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 8465#L255 assume !(0 == ~p_dw_st~0); 8612#L259 assume !(0 == ~c_dr_st~0);exists_runnable_thread_~__retres1~2#1 := 0; 8653#L267 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 8636#exists_runnable_thread_returnLabel#1 eval_#t~ret9#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp___1~0#1 := eval_#t~ret9#1;havoc eval_#t~ret9#1; 8637#L344 assume !(0 != eval_~tmp___1~0#1); 8732#eval_returnLabel#1 havoc eval_#t~ret9#1, eval_#t~nondet10#1, eval_#t~nondet11#1, eval_~tmp~2#1, eval_~tmp___0~2#1, eval_~tmp___1~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 8731#L222-3 assume !(1 == ~q_req_up~0); 8730#L222-5 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 8729#L275-3 assume !(0 == ~q_read_ev~0); 8728#L275-5 assume !(0 == ~q_write_ev~0); 8727#L280-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;assume { :begin_inline_is_do_write_p_triggered } true;havoc is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;havoc is_do_write_p_triggered_~__retres1~0#1; 8726#L65-3 assume !(1 == ~p_dw_pc~0); 8724#L65-5 is_do_write_p_triggered_~__retres1~0#1 := 0; 8723#L76-1 is_do_write_p_triggered_#res#1 := is_do_write_p_triggered_~__retres1~0#1; 8721#is_do_write_p_triggered_returnLabel#2 activate_threads_#t~ret7#1 := is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;assume { :end_inline_is_do_write_p_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1; 8717#L315-3 assume 0 != activate_threads_~tmp~1#1;~p_dw_st~0 := 0; 8718#L315-5 assume { :begin_inline_is_do_read_c_triggered } true;havoc is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;havoc is_do_read_c_triggered_~__retres1~1#1; 8943#L84-3 assume !(1 == ~c_dr_pc~0); 8942#L84-5 is_do_read_c_triggered_~__retres1~1#1 := 0; 8941#L95-1 is_do_read_c_triggered_#res#1 := is_do_read_c_triggered_~__retres1~1#1; 8940#is_do_read_c_triggered_returnLabel#2 activate_threads_#t~ret8#1 := is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;assume { :end_inline_is_do_read_c_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 8938#L323-3 assume 0 != activate_threads_~tmp___0~1#1;~c_dr_st~0 := 0; 8937#L323-5 havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 8936#L293-3 assume !(1 == ~q_read_ev~0); 8935#L293-5 assume !(1 == ~q_write_ev~0); 8934#L298-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret12#1, stop_simulation_~tmp~3#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~3#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 8493#L255-1 assume 0 == ~p_dw_st~0;exists_runnable_thread_~__retres1~2#1 := 1; 8494#L267-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 8487#exists_runnable_thread_returnLabel#2 stop_simulation_#t~ret12#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~3#1 := stop_simulation_#t~ret12#1;havoc stop_simulation_#t~ret12#1; 8488#L394 assume 0 != stop_simulation_~tmp~3#1;stop_simulation_~__retres2~0#1 := 0; 8482#L401 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 8483#stop_simulation_returnLabel#1 start_simulation_#t~ret13#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret12#1, stop_simulation_~tmp~3#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp~4#1 := start_simulation_#t~ret13#1;havoc start_simulation_#t~ret13#1; 8478#L436 assume !(0 != start_simulation_~tmp~4#1); 8477#L419-2 [2023-11-12 02:32:19,389 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-12 02:32:19,389 INFO L85 PathProgramCache]: Analyzing trace with hash -1896010065, now seen corresponding path program 1 times [2023-11-12 02:32:19,389 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-12 02:32:19,390 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2025540999] [2023-11-12 02:32:19,390 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-12 02:32:19,390 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-12 02:32:19,396 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-12 02:32:19,440 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-12 02:32:19,441 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-12 02:32:19,441 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2025540999] [2023-11-12 02:32:19,441 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2025540999] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-12 02:32:19,441 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-12 02:32:19,441 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-12 02:32:19,442 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1818066160] [2023-11-12 02:32:19,442 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-12 02:32:19,442 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-12 02:32:19,442 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-12 02:32:19,443 INFO L85 PathProgramCache]: Analyzing trace with hash 2016810226, now seen corresponding path program 1 times [2023-11-12 02:32:19,443 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-12 02:32:19,443 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1605510638] [2023-11-12 02:32:19,443 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-12 02:32:19,443 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-12 02:32:19,450 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-12 02:32:19,522 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-12 02:32:19,522 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-12 02:32:19,523 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1605510638] [2023-11-12 02:32:19,523 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1605510638] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-12 02:32:19,523 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-12 02:32:19,523 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2023-11-12 02:32:19,523 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [347100390] [2023-11-12 02:32:19,523 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-12 02:32:19,524 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-12 02:32:19,524 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-12 02:32:19,524 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-12 02:32:19,525 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-12 02:32:19,525 INFO L87 Difference]: Start difference. First operand 985 states and 1288 transitions. cyclomatic complexity: 305 Second operand has 3 states, 3 states have (on average 8.666666666666666) internal successors, (26), 3 states have internal predecessors, (26), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-12 02:32:19,535 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-12 02:32:19,535 INFO L93 Difference]: Finished difference Result 964 states and 1263 transitions. [2023-11-12 02:32:19,535 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 964 states and 1263 transitions. [2023-11-12 02:32:19,543 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 935 [2023-11-12 02:32:19,550 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 964 states to 964 states and 1263 transitions. [2023-11-12 02:32:19,551 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 964 [2023-11-12 02:32:19,552 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 964 [2023-11-12 02:32:19,552 INFO L73 IsDeterministic]: Start isDeterministic. Operand 964 states and 1263 transitions. [2023-11-12 02:32:19,553 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-12 02:32:19,554 INFO L218 hiAutomatonCegarLoop]: Abstraction has 964 states and 1263 transitions. [2023-11-12 02:32:19,555 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 964 states and 1263 transitions. [2023-11-12 02:32:19,593 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 964 to 964. [2023-11-12 02:32:19,596 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 964 states, 964 states have (on average 1.3101659751037344) internal successors, (1263), 963 states have internal predecessors, (1263), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-12 02:32:19,600 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 964 states to 964 states and 1263 transitions. [2023-11-12 02:32:19,600 INFO L240 hiAutomatonCegarLoop]: Abstraction has 964 states and 1263 transitions. [2023-11-12 02:32:19,600 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-12 02:32:19,601 INFO L428 stractBuchiCegarLoop]: Abstraction has 964 states and 1263 transitions. [2023-11-12 02:32:19,601 INFO L335 stractBuchiCegarLoop]: ======== Iteration 9 ============ [2023-11-12 02:32:19,601 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 964 states and 1263 transitions. [2023-11-12 02:32:19,608 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 935 [2023-11-12 02:32:19,609 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-12 02:32:19,609 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-12 02:32:19,610 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-12 02:32:19,610 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-12 02:32:19,610 INFO L748 eck$LassoCheckResult]: Stem: 9983#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(19, 2);call #Ultimate.allocInit(12, 3);~q_buf_0~0 := 0;~q_free~0 := 0;~q_read_ev~0 := 0;~q_write_ev~0 := 0;~q_req_up~0 := 0;~q_ev~0 := 0;~p_num_write~0 := 0;~p_last_write~0 := 0;~p_dw_st~0 := 0;~p_dw_pc~0 := 0;~p_dw_i~0 := 0;~c_num_read~0 := 0;~c_last_read~0 := 0;~c_dr_st~0 := 0;~c_dr_pc~0 := 0;~c_dr_i~0 := 0;~a_t~0 := 0; 9984#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~3#1;havoc main_~__retres1~3#1;assume { :begin_inline_init_model } true;~q_free~0 := 1;~q_write_ev~0 := 2;~q_read_ev~0 := ~q_write_ev~0;~p_num_write~0 := 0;~p_dw_pc~0 := 0;~p_dw_i~0 := 1;~c_num_read~0 := 0;~c_dr_pc~0 := 0;~c_dr_i~0 := 1; 10011#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret13#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~4#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~4#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 9959#L222 assume !(1 == ~q_req_up~0); 9948#L222-2 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 9949#L237 assume 1 == ~p_dw_i~0;~p_dw_st~0 := 0; 9994#L237-2 assume 1 == ~c_dr_i~0;~c_dr_st~0 := 0; 10019#L242-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 10017#L275 assume !(0 == ~q_read_ev~0); 10018#L275-2 assume !(0 == ~q_write_ev~0); 9999#L280-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;assume { :begin_inline_is_do_write_p_triggered } true;havoc is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;havoc is_do_write_p_triggered_~__retres1~0#1; 10000#L65 assume !(1 == ~p_dw_pc~0); 9996#L65-2 is_do_write_p_triggered_~__retres1~0#1 := 0; 10008#L76 is_do_write_p_triggered_#res#1 := is_do_write_p_triggered_~__retres1~0#1; 9980#is_do_write_p_triggered_returnLabel#1 activate_threads_#t~ret7#1 := is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;assume { :end_inline_is_do_write_p_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1; 9981#L315 assume !(0 != activate_threads_~tmp~1#1); 9956#L315-2 assume { :begin_inline_is_do_read_c_triggered } true;havoc is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;havoc is_do_read_c_triggered_~__retres1~1#1; 9957#L84 assume !(1 == ~c_dr_pc~0); 9974#L84-2 is_do_read_c_triggered_~__retres1~1#1 := 0; 9967#L95 is_do_read_c_triggered_#res#1 := is_do_read_c_triggered_~__retres1~1#1; 9968#is_do_read_c_triggered_returnLabel#1 activate_threads_#t~ret8#1 := is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;assume { :end_inline_is_do_read_c_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 9932#L323 assume !(0 != activate_threads_~tmp___0~1#1); 9933#L323-2 havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 10032#L293 assume !(1 == ~q_read_ev~0); 9925#L293-2 assume !(1 == ~q_write_ev~0); 9926#L298-1 assume { :end_inline_reset_delta_events } true; 10024#L419-2 [2023-11-12 02:32:19,610 INFO L750 eck$LassoCheckResult]: Loop: 10024#L419-2 assume !false; 10105#L420 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret9#1, eval_#t~nondet10#1, eval_#t~nondet11#1, eval_~tmp~2#1, eval_~tmp___0~2#1, eval_~tmp___1~0#1;havoc eval_~tmp~2#1;havoc eval_~tmp___0~2#1;havoc eval_~tmp___1~0#1; 10102#L364 assume !false; 10100#L340 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 10098#L255 assume !(0 == ~p_dw_st~0); 10097#L259 assume !(0 == ~c_dr_st~0);exists_runnable_thread_~__retres1~2#1 := 0; 10095#L267 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 10092#exists_runnable_thread_returnLabel#1 eval_#t~ret9#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp___1~0#1 := eval_#t~ret9#1;havoc eval_#t~ret9#1; 10087#L344 assume !(0 != eval_~tmp___1~0#1); 10088#eval_returnLabel#1 havoc eval_#t~ret9#1, eval_#t~nondet10#1, eval_#t~nondet11#1, eval_~tmp~2#1, eval_~tmp___0~2#1, eval_~tmp___1~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 10153#L222-3 assume !(1 == ~q_req_up~0); 10152#L222-5 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 10151#L275-3 assume !(0 == ~q_read_ev~0); 10150#L275-5 assume !(0 == ~q_write_ev~0); 10149#L280-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;assume { :begin_inline_is_do_write_p_triggered } true;havoc is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;havoc is_do_write_p_triggered_~__retres1~0#1; 10148#L65-3 assume !(1 == ~p_dw_pc~0); 10146#L65-5 is_do_write_p_triggered_~__retres1~0#1 := 0; 10145#L76-1 is_do_write_p_triggered_#res#1 := is_do_write_p_triggered_~__retres1~0#1; 10144#is_do_write_p_triggered_returnLabel#2 activate_threads_#t~ret7#1 := is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;assume { :end_inline_is_do_write_p_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1; 10142#L315-3 assume 0 != activate_threads_~tmp~1#1;~p_dw_st~0 := 0; 10140#L315-5 assume { :begin_inline_is_do_read_c_triggered } true;havoc is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;havoc is_do_read_c_triggered_~__retres1~1#1; 10138#L84-3 assume !(1 == ~c_dr_pc~0); 10136#L84-5 is_do_read_c_triggered_~__retres1~1#1 := 0; 10134#L95-1 is_do_read_c_triggered_#res#1 := is_do_read_c_triggered_~__retres1~1#1; 10132#is_do_read_c_triggered_returnLabel#2 activate_threads_#t~ret8#1 := is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;assume { :end_inline_is_do_read_c_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 10130#L323-3 assume 0 != activate_threads_~tmp___0~1#1;~c_dr_st~0 := 0; 10128#L323-5 havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 10126#L293-3 assume !(1 == ~q_read_ev~0); 10124#L293-5 assume !(1 == ~q_write_ev~0); 10122#L298-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret12#1, stop_simulation_~tmp~3#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~3#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 10120#L255-1 assume 0 == ~p_dw_st~0;exists_runnable_thread_~__retres1~2#1 := 1; 10118#L267-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 10116#exists_runnable_thread_returnLabel#2 stop_simulation_#t~ret12#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~3#1 := stop_simulation_#t~ret12#1;havoc stop_simulation_#t~ret12#1; 10114#L394 assume 0 != stop_simulation_~tmp~3#1;stop_simulation_~__retres2~0#1 := 0; 10112#L401 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 10110#stop_simulation_returnLabel#1 start_simulation_#t~ret13#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret12#1, stop_simulation_~tmp~3#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp~4#1 := start_simulation_#t~ret13#1;havoc start_simulation_#t~ret13#1; 10108#L436 assume !(0 != start_simulation_~tmp~4#1); 10024#L419-2 [2023-11-12 02:32:19,611 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-12 02:32:19,611 INFO L85 PathProgramCache]: Analyzing trace with hash -1617647313, now seen corresponding path program 3 times [2023-11-12 02:32:19,611 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-12 02:32:19,611 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [226168686] [2023-11-12 02:32:19,611 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-12 02:32:19,612 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-12 02:32:19,618 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-12 02:32:19,619 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-12 02:32:19,623 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-12 02:32:19,628 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-12 02:32:19,629 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-12 02:32:19,629 INFO L85 PathProgramCache]: Analyzing trace with hash 2016810226, now seen corresponding path program 2 times [2023-11-12 02:32:19,629 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-12 02:32:19,629 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [687305848] [2023-11-12 02:32:19,629 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-12 02:32:19,630 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-12 02:32:19,637 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-12 02:32:19,677 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-12 02:32:19,677 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-12 02:32:19,677 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [687305848] [2023-11-12 02:32:19,678 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [687305848] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-12 02:32:19,678 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-12 02:32:19,678 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2023-11-12 02:32:19,678 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [17225780] [2023-11-12 02:32:19,678 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-12 02:32:19,678 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-12 02:32:19,679 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-12 02:32:19,679 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2023-11-12 02:32:19,679 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2023-11-12 02:32:19,679 INFO L87 Difference]: Start difference. First operand 964 states and 1263 transitions. cyclomatic complexity: 301 Second operand has 5 states, 5 states have (on average 7.4) internal successors, (37), 5 states have internal predecessors, (37), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-12 02:32:19,731 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-12 02:32:19,731 INFO L93 Difference]: Finished difference Result 1346 states and 1757 transitions. [2023-11-12 02:32:19,731 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1346 states and 1757 transitions. [2023-11-12 02:32:19,742 INFO L131 ngComponentsAnalysis]: Automaton has 7 accepting balls. 1301 [2023-11-12 02:32:19,753 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1346 states to 1346 states and 1757 transitions. [2023-11-12 02:32:19,753 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1346 [2023-11-12 02:32:19,754 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1346 [2023-11-12 02:32:19,755 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1346 states and 1757 transitions. [2023-11-12 02:32:19,756 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-12 02:32:19,757 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1346 states and 1757 transitions. [2023-11-12 02:32:19,758 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1346 states and 1757 transitions. [2023-11-12 02:32:19,773 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1346 to 915. [2023-11-12 02:32:19,775 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 915 states, 915 states have (on average 1.303825136612022) internal successors, (1193), 914 states have internal predecessors, (1193), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-12 02:32:19,779 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 915 states to 915 states and 1193 transitions. [2023-11-12 02:32:19,779 INFO L240 hiAutomatonCegarLoop]: Abstraction has 915 states and 1193 transitions. [2023-11-12 02:32:19,780 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2023-11-12 02:32:19,780 INFO L428 stractBuchiCegarLoop]: Abstraction has 915 states and 1193 transitions. [2023-11-12 02:32:19,780 INFO L335 stractBuchiCegarLoop]: ======== Iteration 10 ============ [2023-11-12 02:32:19,781 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 915 states and 1193 transitions. [2023-11-12 02:32:19,786 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 879 [2023-11-12 02:32:19,786 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-12 02:32:19,786 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-12 02:32:19,787 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-12 02:32:19,787 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-12 02:32:19,787 INFO L748 eck$LassoCheckResult]: Stem: 12302#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(19, 2);call #Ultimate.allocInit(12, 3);~q_buf_0~0 := 0;~q_free~0 := 0;~q_read_ev~0 := 0;~q_write_ev~0 := 0;~q_req_up~0 := 0;~q_ev~0 := 0;~p_num_write~0 := 0;~p_last_write~0 := 0;~p_dw_st~0 := 0;~p_dw_pc~0 := 0;~p_dw_i~0 := 0;~c_num_read~0 := 0;~c_last_read~0 := 0;~c_dr_st~0 := 0;~c_dr_pc~0 := 0;~c_dr_i~0 := 0;~a_t~0 := 0; 12303#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~3#1;havoc main_~__retres1~3#1;assume { :begin_inline_init_model } true;~q_free~0 := 1;~q_write_ev~0 := 2;~q_read_ev~0 := ~q_write_ev~0;~p_num_write~0 := 0;~p_dw_pc~0 := 0;~p_dw_i~0 := 1;~c_num_read~0 := 0;~c_dr_pc~0 := 0;~c_dr_i~0 := 1; 12330#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret13#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~4#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~4#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 12281#L222 assume !(1 == ~q_req_up~0); 12270#L222-2 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 12271#L237 assume 1 == ~p_dw_i~0;~p_dw_st~0 := 0; 12312#L237-2 assume 1 == ~c_dr_i~0;~c_dr_st~0 := 0; 12337#L242-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 12335#L275 assume !(0 == ~q_read_ev~0); 12336#L275-2 assume !(0 == ~q_write_ev~0); 12317#L280-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;assume { :begin_inline_is_do_write_p_triggered } true;havoc is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;havoc is_do_write_p_triggered_~__retres1~0#1; 12318#L65 assume !(1 == ~p_dw_pc~0); 12314#L65-2 is_do_write_p_triggered_~__retres1~0#1 := 0; 12327#L76 is_do_write_p_triggered_#res#1 := is_do_write_p_triggered_~__retres1~0#1; 12299#is_do_write_p_triggered_returnLabel#1 activate_threads_#t~ret7#1 := is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;assume { :end_inline_is_do_write_p_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1; 12300#L315 assume !(0 != activate_threads_~tmp~1#1); 12278#L315-2 assume { :begin_inline_is_do_read_c_triggered } true;havoc is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;havoc is_do_read_c_triggered_~__retres1~1#1; 12279#L84 assume !(1 == ~c_dr_pc~0); 12295#L84-2 is_do_read_c_triggered_~__retres1~1#1 := 0; 12290#L95 is_do_read_c_triggered_#res#1 := is_do_read_c_triggered_~__retres1~1#1; 12291#is_do_read_c_triggered_returnLabel#1 activate_threads_#t~ret8#1 := is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;assume { :end_inline_is_do_read_c_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 12254#L323 assume !(0 != activate_threads_~tmp___0~1#1); 12255#L323-2 havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 12352#L293 assume !(1 == ~q_read_ev~0); 12247#L293-2 assume !(1 == ~q_write_ev~0); 12248#L298-1 assume { :end_inline_reset_delta_events } true; 12343#L419-2 assume !false; 12919#L420 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret9#1, eval_#t~nondet10#1, eval_#t~nondet11#1, eval_~tmp~2#1, eval_~tmp___0~2#1, eval_~tmp___1~0#1;havoc eval_~tmp~2#1;havoc eval_~tmp___0~2#1;havoc eval_~tmp___1~0#1; 12914#L364 [2023-11-12 02:32:19,788 INFO L750 eck$LassoCheckResult]: Loop: 12914#L364 assume !false; 12918#L340 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 12383#L255 assume 0 == ~p_dw_st~0;exists_runnable_thread_~__retres1~2#1 := 1; 12384#L267 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 12907#exists_runnable_thread_returnLabel#1 eval_#t~ret9#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp___1~0#1 := eval_#t~ret9#1;havoc eval_#t~ret9#1; 12906#L344 assume 0 != eval_~tmp___1~0#1; 12904#L344-1 assume 0 == ~p_dw_st~0;havoc eval_#t~nondet10#1;eval_~tmp~2#1 := eval_#t~nondet10#1;havoc eval_#t~nondet10#1; 12902#L353 assume !(0 != eval_~tmp~2#1); 12903#L349 assume !(0 == ~c_dr_st~0); 12914#L364 [2023-11-12 02:32:19,788 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-12 02:32:19,788 INFO L85 PathProgramCache]: Analyzing trace with hash 219097361, now seen corresponding path program 1 times [2023-11-12 02:32:19,788 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-12 02:32:19,788 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1768075904] [2023-11-12 02:32:19,789 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-12 02:32:19,789 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-12 02:32:19,796 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-12 02:32:19,796 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-12 02:32:19,800 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-12 02:32:19,806 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-12 02:32:19,807 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-12 02:32:19,807 INFO L85 PathProgramCache]: Analyzing trace with hash -479000197, now seen corresponding path program 1 times [2023-11-12 02:32:19,807 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-12 02:32:19,808 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [897712755] [2023-11-12 02:32:19,808 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-12 02:32:19,808 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-12 02:32:19,811 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-12 02:32:19,811 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-12 02:32:19,813 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-12 02:32:19,815 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-12 02:32:19,816 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-12 02:32:19,816 INFO L85 PathProgramCache]: Analyzing trace with hash 519639659, now seen corresponding path program 1 times [2023-11-12 02:32:19,816 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-12 02:32:19,816 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2069768792] [2023-11-12 02:32:19,817 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-12 02:32:19,817 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-12 02:32:19,824 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-12 02:32:19,844 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-12 02:32:19,844 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-12 02:32:19,844 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2069768792] [2023-11-12 02:32:19,844 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2069768792] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-12 02:32:19,845 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-12 02:32:19,845 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2023-11-12 02:32:19,845 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [466698112] [2023-11-12 02:32:19,845 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-12 02:32:19,917 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-12 02:32:19,918 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-12 02:32:19,918 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-12 02:32:19,918 INFO L87 Difference]: Start difference. First operand 915 states and 1193 transitions. cyclomatic complexity: 281 Second operand has 3 states, 2 states have (on average 18.5) internal successors, (37), 3 states have internal predecessors, (37), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-12 02:32:19,954 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-12 02:32:19,954 INFO L93 Difference]: Finished difference Result 1272 states and 1634 transitions. [2023-11-12 02:32:19,955 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1272 states and 1634 transitions. [2023-11-12 02:32:19,965 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 1236 [2023-11-12 02:32:19,975 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1272 states to 1272 states and 1634 transitions. [2023-11-12 02:32:19,975 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1272 [2023-11-12 02:32:19,977 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1272 [2023-11-12 02:32:19,977 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1272 states and 1634 transitions. [2023-11-12 02:32:19,979 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-12 02:32:19,979 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1272 states and 1634 transitions. [2023-11-12 02:32:19,980 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1272 states and 1634 transitions. [2023-11-12 02:32:20,006 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1272 to 1272. [2023-11-12 02:32:20,008 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1272 states, 1272 states have (on average 1.2845911949685536) internal successors, (1634), 1271 states have internal predecessors, (1634), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-12 02:32:20,014 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1272 states to 1272 states and 1634 transitions. [2023-11-12 02:32:20,014 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1272 states and 1634 transitions. [2023-11-12 02:32:20,014 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-12 02:32:20,015 INFO L428 stractBuchiCegarLoop]: Abstraction has 1272 states and 1634 transitions. [2023-11-12 02:32:20,015 INFO L335 stractBuchiCegarLoop]: ======== Iteration 11 ============ [2023-11-12 02:32:20,015 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1272 states and 1634 transitions. [2023-11-12 02:32:20,023 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 1236 [2023-11-12 02:32:20,023 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-12 02:32:20,023 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-12 02:32:20,024 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-12 02:32:20,024 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-12 02:32:20,024 INFO L748 eck$LassoCheckResult]: Stem: 14501#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(19, 2);call #Ultimate.allocInit(12, 3);~q_buf_0~0 := 0;~q_free~0 := 0;~q_read_ev~0 := 0;~q_write_ev~0 := 0;~q_req_up~0 := 0;~q_ev~0 := 0;~p_num_write~0 := 0;~p_last_write~0 := 0;~p_dw_st~0 := 0;~p_dw_pc~0 := 0;~p_dw_i~0 := 0;~c_num_read~0 := 0;~c_last_read~0 := 0;~c_dr_st~0 := 0;~c_dr_pc~0 := 0;~c_dr_i~0 := 0;~a_t~0 := 0; 14502#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~3#1;havoc main_~__retres1~3#1;assume { :begin_inline_init_model } true;~q_free~0 := 1;~q_write_ev~0 := 2;~q_read_ev~0 := ~q_write_ev~0;~p_num_write~0 := 0;~p_dw_pc~0 := 0;~p_dw_i~0 := 1;~c_num_read~0 := 0;~c_dr_pc~0 := 0;~c_dr_i~0 := 1; 14532#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret13#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~4#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~4#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 14475#L222 assume !(1 == ~q_req_up~0); 14466#L222-2 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 14467#L237 assume 1 == ~p_dw_i~0;~p_dw_st~0 := 0; 14511#L237-2 assume 1 == ~c_dr_i~0;~c_dr_st~0 := 0; 14538#L242-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 14535#L275 assume !(0 == ~q_read_ev~0); 14536#L275-2 assume !(0 == ~q_write_ev~0); 14517#L280-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;assume { :begin_inline_is_do_write_p_triggered } true;havoc is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;havoc is_do_write_p_triggered_~__retres1~0#1; 14518#L65 assume !(1 == ~p_dw_pc~0); 14513#L65-2 is_do_write_p_triggered_~__retres1~0#1 := 0; 14527#L76 is_do_write_p_triggered_#res#1 := is_do_write_p_triggered_~__retres1~0#1; 14496#is_do_write_p_triggered_returnLabel#1 activate_threads_#t~ret7#1 := is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;assume { :end_inline_is_do_write_p_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1; 14497#L315 assume !(0 != activate_threads_~tmp~1#1); 14472#L315-2 assume { :begin_inline_is_do_read_c_triggered } true;havoc is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;havoc is_do_read_c_triggered_~__retres1~1#1; 14473#L84 assume !(1 == ~c_dr_pc~0); 14489#L84-2 is_do_read_c_triggered_~__retres1~1#1 := 0; 14484#L95 is_do_read_c_triggered_#res#1 := is_do_read_c_triggered_~__retres1~1#1; 14485#is_do_read_c_triggered_returnLabel#1 activate_threads_#t~ret8#1 := is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;assume { :end_inline_is_do_read_c_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 14448#L323 assume !(0 != activate_threads_~tmp___0~1#1); 14449#L323-2 havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 14552#L293 assume !(1 == ~q_read_ev~0); 14442#L293-2 assume !(1 == ~q_write_ev~0); 14443#L298-1 assume { :end_inline_reset_delta_events } true; 14543#L419-2 assume !false; 14642#L420 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret9#1, eval_#t~nondet10#1, eval_#t~nondet11#1, eval_~tmp~2#1, eval_~tmp___0~2#1, eval_~tmp___1~0#1;havoc eval_~tmp~2#1;havoc eval_~tmp___0~2#1;havoc eval_~tmp___1~0#1; 14641#L364 [2023-11-12 02:32:20,024 INFO L750 eck$LassoCheckResult]: Loop: 14641#L364 assume !false; 14639#L340 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 14637#L255 assume 0 == ~p_dw_st~0;exists_runnable_thread_~__retres1~2#1 := 1; 14635#L267 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 14633#exists_runnable_thread_returnLabel#1 eval_#t~ret9#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp___1~0#1 := eval_#t~ret9#1;havoc eval_#t~ret9#1; 14630#L344 assume 0 != eval_~tmp___1~0#1; 14627#L344-1 assume 0 == ~p_dw_st~0;havoc eval_#t~nondet10#1;eval_~tmp~2#1 := eval_#t~nondet10#1;havoc eval_#t~nondet10#1; 14623#L353 assume !(0 != eval_~tmp~2#1); 14619#L349 assume 0 == ~c_dr_st~0;havoc eval_#t~nondet11#1;eval_~tmp___0~2#1 := eval_#t~nondet11#1;havoc eval_#t~nondet11#1; 14620#L368 assume !(0 != eval_~tmp___0~2#1); 14641#L364 [2023-11-12 02:32:20,025 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-12 02:32:20,025 INFO L85 PathProgramCache]: Analyzing trace with hash 219097361, now seen corresponding path program 2 times [2023-11-12 02:32:20,025 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-12 02:32:20,025 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1649219547] [2023-11-12 02:32:20,025 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-12 02:32:20,026 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-12 02:32:20,033 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-12 02:32:20,033 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-12 02:32:20,038 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-12 02:32:20,043 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-12 02:32:20,044 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-12 02:32:20,044 INFO L85 PathProgramCache]: Analyzing trace with hash -1964105996, now seen corresponding path program 1 times [2023-11-12 02:32:20,044 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-12 02:32:20,044 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [252619242] [2023-11-12 02:32:20,044 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-12 02:32:20,045 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-12 02:32:20,048 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-12 02:32:20,048 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-12 02:32:20,050 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-12 02:32:20,052 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-12 02:32:20,052 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-12 02:32:20,052 INFO L85 PathProgramCache]: Analyzing trace with hash -1071041532, now seen corresponding path program 1 times [2023-11-12 02:32:20,053 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-12 02:32:20,053 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1553653033] [2023-11-12 02:32:20,053 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-12 02:32:20,053 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-12 02:32:20,061 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-12 02:32:20,061 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-12 02:32:20,065 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-12 02:32:20,070 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-12 02:32:20,913 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-12 02:32:20,914 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-12 02:32:20,927 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-12 02:32:21,010 INFO L201 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer CFG 12.11 02:32:21 BoogieIcfgContainer [2023-11-12 02:32:21,010 INFO L131 PluginConnector]: ------------------------ END BuchiAutomizer---------------------------- [2023-11-12 02:32:21,011 INFO L112 PluginConnector]: ------------------------Witness Printer---------------------------- [2023-11-12 02:32:21,011 INFO L270 PluginConnector]: Initializing Witness Printer... [2023-11-12 02:32:21,011 INFO L274 PluginConnector]: Witness Printer initialized [2023-11-12 02:32:21,011 INFO L184 PluginConnector]: Executing the observer RCFGCatcher from plugin Witness Printer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 12.11 02:32:16" (3/4) ... [2023-11-12 02:32:21,013 INFO L134 WitnessPrinter]: Generating witness for non-termination counterexample [2023-11-12 02:32:21,070 INFO L149 WitnessManager]: Wrote witness to /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7b9c22fa-3e82-4a9e-bded-316d6416295d/bin/uautomizer-verify-uTZkv6EMXl/witness.graphml [2023-11-12 02:32:21,070 INFO L131 PluginConnector]: ------------------------ END Witness Printer---------------------------- [2023-11-12 02:32:21,071 INFO L158 Benchmark]: Toolchain (without parser) took 5336.82ms. Allocated memory was 140.5MB in the beginning and 201.3MB in the end (delta: 60.8MB). Free memory was 95.3MB in the beginning and 105.9MB in the end (delta: -10.6MB). Peak memory consumption was 53.3MB. Max. memory is 16.1GB. [2023-11-12 02:32:21,071 INFO L158 Benchmark]: CDTParser took 0.63ms. Allocated memory is still 140.5MB. Free memory is still 111.7MB. There was no memory consumed. Max. memory is 16.1GB. [2023-11-12 02:32:21,072 INFO L158 Benchmark]: CACSL2BoogieTranslator took 387.76ms. Allocated memory is still 140.5MB. Free memory was 94.7MB in the beginning and 82.2MB in the end (delta: 12.6MB). Peak memory consumption was 12.6MB. Max. memory is 16.1GB. [2023-11-12 02:32:21,072 INFO L158 Benchmark]: Boogie Procedure Inliner took 49.55ms. Allocated memory is still 140.5MB. Free memory was 82.2MB in the beginning and 79.5MB in the end (delta: 2.7MB). Peak memory consumption was 2.1MB. Max. memory is 16.1GB. [2023-11-12 02:32:21,072 INFO L158 Benchmark]: Boogie Preprocessor took 35.64ms. Allocated memory is still 140.5MB. Free memory was 79.5MB in the beginning and 78.0MB in the end (delta: 1.5MB). Peak memory consumption was 2.1MB. Max. memory is 16.1GB. [2023-11-12 02:32:21,073 INFO L158 Benchmark]: RCFGBuilder took 572.53ms. Allocated memory is still 140.5MB. Free memory was 78.0MB in the beginning and 60.1MB in the end (delta: 17.9MB). Peak memory consumption was 16.8MB. Max. memory is 16.1GB. [2023-11-12 02:32:21,073 INFO L158 Benchmark]: BuchiAutomizer took 4225.64ms. Allocated memory was 140.5MB in the beginning and 201.3MB in the end (delta: 60.8MB). Free memory was 60.1MB in the beginning and 110.1MB in the end (delta: -50.1MB). Peak memory consumption was 13.5MB. Max. memory is 16.1GB. [2023-11-12 02:32:21,074 INFO L158 Benchmark]: Witness Printer took 59.70ms. Allocated memory is still 201.3MB. Free memory was 110.1MB in the beginning and 105.9MB in the end (delta: 4.2MB). Peak memory consumption was 4.2MB. Max. memory is 16.1GB. [2023-11-12 02:32:21,076 INFO L338 ainManager$Toolchain]: ####################### End [Toolchain 1] ####################### --- Results --- * Results from de.uni_freiburg.informatik.ultimate.core: - StatisticsResult: Toolchain Benchmarks Benchmark results are: * CDTParser took 0.63ms. Allocated memory is still 140.5MB. Free memory is still 111.7MB. There was no memory consumed. Max. memory is 16.1GB. * CACSL2BoogieTranslator took 387.76ms. Allocated memory is still 140.5MB. Free memory was 94.7MB in the beginning and 82.2MB in the end (delta: 12.6MB). Peak memory consumption was 12.6MB. Max. memory is 16.1GB. * Boogie Procedure Inliner took 49.55ms. Allocated memory is still 140.5MB. Free memory was 82.2MB in the beginning and 79.5MB in the end (delta: 2.7MB). Peak memory consumption was 2.1MB. Max. memory is 16.1GB. * Boogie Preprocessor took 35.64ms. Allocated memory is still 140.5MB. Free memory was 79.5MB in the beginning and 78.0MB in the end (delta: 1.5MB). Peak memory consumption was 2.1MB. Max. memory is 16.1GB. * RCFGBuilder took 572.53ms. Allocated memory is still 140.5MB. Free memory was 78.0MB in the beginning and 60.1MB in the end (delta: 17.9MB). Peak memory consumption was 16.8MB. Max. memory is 16.1GB. * BuchiAutomizer took 4225.64ms. Allocated memory was 140.5MB in the beginning and 201.3MB in the end (delta: 60.8MB). Free memory was 60.1MB in the beginning and 110.1MB in the end (delta: -50.1MB). Peak memory consumption was 13.5MB. Max. memory is 16.1GB. * Witness Printer took 59.70ms. Allocated memory is still 201.3MB. Free memory was 110.1MB in the beginning and 105.9MB in the end (delta: 4.2MB). Peak memory consumption was 4.2MB. Max. memory is 16.1GB. * Results from de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction: - StatisticsResult: Constructed decomposition of program Your program was decomposed into 10 terminating modules (10 trivial, 0 deterministic, 0 nondeterministic) and one nonterminating remainder module.10 modules have a trivial ranking function, the largest among these consists of 5 locations. The remainder module has 1272 locations. - StatisticsResult: Timing statistics BüchiAutomizer plugin needed 4.0s and 11 iterations. TraceHistogramMax:1. Analysis of lassos took 2.6s. Construction of modules took 0.2s. Büchi inclusion checks took 0.9s. Highest rank in rank-based complementation 0. Minimization of det autom 10. Minimization of nondet autom 0. Automata minimization 0.3s AutomataMinimizationTime, 10 MinimizatonAttempts, 1223 StatesRemovedByMinimization, 5 NontrivialMinimizations. Non-live state removal took 0.1s Buchi closure took 0.0s. Biggest automaton had -1 states and ocurred in iteration -1. Nontrivial modules had stage [0, 0, 0, 0, 0]. InterpolantCoveringCapabilityFinite: 0/0 InterpolantCoveringCapabilityBuchi: 0/0 HoareTripleCheckerStatistics: 0 mSolverCounterUnknown, 1710 SdHoareTripleChecker+Valid, 0.4s IncrementalHoareTripleChecker+Time, 0 mSdLazyCounter, 1710 mSDsluCounter, 2916 SdHoareTripleChecker+Invalid, 0.3s Time, 0 mProtectedAction, 0 SdHoareTripleChecker+Unchecked, 0 IncrementalHoareTripleChecker+Unchecked, 1525 mSDsCounter, 71 IncrementalHoareTripleChecker+Valid, 0 mProtectedPredicate, 241 IncrementalHoareTripleChecker+Invalid, 312 SdHoareTripleChecker+Unknown, 0 mSolverCounterNotChecked, 71 mSolverCounterUnsat, 1391 mSDtfsCounter, 241 mSolverCounterSat, 0.0s SdHoareTripleChecker+Time, 0 IncrementalHoareTripleChecker+Unknown LassoAnalysisResults: nont1 unkn0 SFLI3 SFLT0 conc1 concLT0 SILN0 SILU0 SILI6 SILT0 lasso0 LassoPreprocessingBenchmarks: LassoTerminationAnalysisBenchmarks: not availableLassoTerminationAnalysisBenchmarks: LassoNonterminationAnalysisSatFixpoint: 0 LassoNonterminationAnalysisSatUnbounded: 0 LassoNonterminationAnalysisUnsat: 0 LassoNonterminationAnalysisUnknown: 0 LassoNonterminationAnalysisTime: 0.0s InitialAbstractionConstructionTime: 0.0s - TerminationAnalysisResult: Nontermination possible Buchi Automizer proved that your program is nonterminating for some inputs - LassoShapedNonTerminationArgument [Line: 339]: Nontermination argument in form of an infinite program execution. Nontermination argument in form of an infinite program execution. Stem: [L25] int q_buf_0 ; [L26] int q_free ; [L27] int q_read_ev ; [L28] int q_write_ev ; [L29] int q_req_up ; [L30] int q_ev ; [L51] int p_num_write ; [L52] int p_last_write ; [L53] int p_dw_st ; [L54] int p_dw_pc ; [L55] int p_dw_i ; [L56] int c_num_read ; [L57] int c_last_read ; [L58] int c_dr_st ; [L59] int c_dr_pc ; [L60] int c_dr_i ; [L164] static int a_t ; VAL [a_t=0, c_dr_i=0, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, p_dw_i=0, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=0, q_read_ev=0, q_req_up=0, q_write_ev=0] [L466] int __retres1 ; [L470] CALL init_model() [L452] q_free = 1 [L453] q_write_ev = 2 [L454] q_read_ev = q_write_ev [L455] p_num_write = 0 [L456] p_dw_pc = 0 [L457] p_dw_i = 1 [L458] c_num_read = 0 [L459] c_dr_pc = 0 [L460] c_dr_i = 1 VAL [a_t=0, c_dr_i=1, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, p_dw_i=1, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=1, q_read_ev=2, q_req_up=0, q_write_ev=2] [L470] RET init_model() [L471] CALL start_simulation() [L406] int kernel_st ; [L407] int tmp ; [L411] kernel_st = 0 [L412] CALL update_channels() [L222] COND FALSE !((int )q_req_up == 1) VAL [a_t=0, c_dr_i=1, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, p_dw_i=1, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=1, q_read_ev=2, q_req_up=0, q_write_ev=2] [L412] RET update_channels() [L413] CALL init_threads() [L237] COND TRUE (int )p_dw_i == 1 [L238] p_dw_st = 0 VAL [a_t=0, c_dr_i=1, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, p_dw_i=1, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=1, q_read_ev=2, q_req_up=0, q_write_ev=2] [L242] COND TRUE (int )c_dr_i == 1 [L243] c_dr_st = 0 VAL [a_t=0, c_dr_i=1, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, p_dw_i=1, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=1, q_read_ev=2, q_req_up=0, q_write_ev=2] [L413] RET init_threads() [L414] CALL fire_delta_events() [L275] COND FALSE !((int )q_read_ev == 0) VAL [a_t=0, c_dr_i=1, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, p_dw_i=1, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=1, q_read_ev=2, q_req_up=0, q_write_ev=2] [L280] COND FALSE !((int )q_write_ev == 0) VAL [a_t=0, c_dr_i=1, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, p_dw_i=1, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=1, q_read_ev=2, q_req_up=0, q_write_ev=2] [L414] RET fire_delta_events() [L415] CALL activate_threads() [L308] int tmp ; [L309] int tmp___0 ; [L313] CALL, EXPR is_do_write_p_triggered() [L62] int __retres1 ; VAL [a_t=0, c_dr_i=1, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, p_dw_i=1, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=1, q_read_ev=2, q_req_up=0, q_write_ev=2] [L65] COND FALSE !((int )p_dw_pc == 1) VAL [a_t=0, c_dr_i=1, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, p_dw_i=1, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=1, q_read_ev=2, q_req_up=0, q_write_ev=2] [L75] __retres1 = 0 VAL [__retres1=0, a_t=0, c_dr_i=1, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, p_dw_i=1, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=1, q_read_ev=2, q_req_up=0, q_write_ev=2] [L77] return (__retres1); VAL [\result=0, __retres1=0, a_t=0, c_dr_i=1, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, p_dw_i=1, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=1, q_read_ev=2, q_req_up=0, q_write_ev=2] [L313] RET, EXPR is_do_write_p_triggered() [L313] tmp = is_do_write_p_triggered() [L315] COND FALSE !(\read(tmp)) VAL [a_t=0, c_dr_i=1, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, p_dw_i=1, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=1, q_read_ev=2, q_req_up=0, q_write_ev=2, tmp=0] [L321] CALL, EXPR is_do_read_c_triggered() [L81] int __retres1 ; VAL [a_t=0, c_dr_i=1, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, p_dw_i=1, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=1, q_read_ev=2, q_req_up=0, q_write_ev=2] [L84] COND FALSE !((int )c_dr_pc == 1) VAL [a_t=0, c_dr_i=1, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, p_dw_i=1, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=1, q_read_ev=2, q_req_up=0, q_write_ev=2] [L94] __retres1 = 0 VAL [__retres1=0, a_t=0, c_dr_i=1, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, p_dw_i=1, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=1, q_read_ev=2, q_req_up=0, q_write_ev=2] [L96] return (__retres1); VAL [\result=0, __retres1=0, a_t=0, c_dr_i=1, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, p_dw_i=1, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=1, q_read_ev=2, q_req_up=0, q_write_ev=2] [L321] RET, EXPR is_do_read_c_triggered() [L321] tmp___0 = is_do_read_c_triggered() [L323] COND FALSE !(\read(tmp___0)) VAL [a_t=0, c_dr_i=1, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, p_dw_i=1, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=1, q_read_ev=2, q_req_up=0, q_write_ev=2, tmp=0, tmp___0=0] [L415] RET activate_threads() [L416] CALL reset_delta_events() [L293] COND FALSE !((int )q_read_ev == 1) VAL [a_t=0, c_dr_i=1, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, p_dw_i=1, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=1, q_read_ev=2, q_req_up=0, q_write_ev=2] [L298] COND FALSE !((int )q_write_ev == 1) VAL [a_t=0, c_dr_i=1, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, p_dw_i=1, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=1, q_read_ev=2, q_req_up=0, q_write_ev=2] [L416] RET reset_delta_events() [L419] COND TRUE 1 VAL [a_t=0, c_dr_i=1, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, kernel_st=0, p_dw_i=1, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=1, q_read_ev=2, q_req_up=0, q_write_ev=2] [L422] kernel_st = 1 [L423] CALL eval() [L333] int tmp ; [L334] int tmp___0 ; [L335] int tmp___1 ; VAL [a_t=0, c_dr_i=1, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, p_dw_i=1, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=1, q_read_ev=2, q_req_up=0, q_write_ev=2] Loop: [L339] COND TRUE 1 [L342] CALL, EXPR exists_runnable_thread() [L252] int __retres1 ; [L255] COND TRUE (int )p_dw_st == 0 [L256] __retres1 = 1 [L268] return (__retres1); [L342] RET, EXPR exists_runnable_thread() [L342] tmp___1 = exists_runnable_thread() [L344] COND TRUE \read(tmp___1) [L349] COND TRUE (int )p_dw_st == 0 [L351] tmp = __VERIFIER_nondet_int() [L353] COND FALSE !(\read(tmp)) [L364] COND TRUE (int )c_dr_st == 0 [L366] tmp___0 = __VERIFIER_nondet_int() [L368] COND FALSE !(\read(tmp___0)) End of lasso representation. - StatisticsResult: NonterminationArgumentStatistics Fixpoint - NonterminatingLassoResult [Line: 339]: Nonterminating execution Found a nonterminating execution for the following lasso shaped sequence of statements. Stem: [L25] int q_buf_0 ; [L26] int q_free ; [L27] int q_read_ev ; [L28] int q_write_ev ; [L29] int q_req_up ; [L30] int q_ev ; [L51] int p_num_write ; [L52] int p_last_write ; [L53] int p_dw_st ; [L54] int p_dw_pc ; [L55] int p_dw_i ; [L56] int c_num_read ; [L57] int c_last_read ; [L58] int c_dr_st ; [L59] int c_dr_pc ; [L60] int c_dr_i ; [L164] static int a_t ; VAL [a_t=0, c_dr_i=0, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, p_dw_i=0, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=0, q_read_ev=0, q_req_up=0, q_write_ev=0] [L466] int __retres1 ; [L470] CALL init_model() [L452] q_free = 1 [L453] q_write_ev = 2 [L454] q_read_ev = q_write_ev [L455] p_num_write = 0 [L456] p_dw_pc = 0 [L457] p_dw_i = 1 [L458] c_num_read = 0 [L459] c_dr_pc = 0 [L460] c_dr_i = 1 VAL [a_t=0, c_dr_i=1, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, p_dw_i=1, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=1, q_read_ev=2, q_req_up=0, q_write_ev=2] [L470] RET init_model() [L471] CALL start_simulation() [L406] int kernel_st ; [L407] int tmp ; [L411] kernel_st = 0 [L412] CALL update_channels() [L222] COND FALSE !((int )q_req_up == 1) VAL [a_t=0, c_dr_i=1, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, p_dw_i=1, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=1, q_read_ev=2, q_req_up=0, q_write_ev=2] [L412] RET update_channels() [L413] CALL init_threads() [L237] COND TRUE (int )p_dw_i == 1 [L238] p_dw_st = 0 VAL [a_t=0, c_dr_i=1, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, p_dw_i=1, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=1, q_read_ev=2, q_req_up=0, q_write_ev=2] [L242] COND TRUE (int )c_dr_i == 1 [L243] c_dr_st = 0 VAL [a_t=0, c_dr_i=1, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, p_dw_i=1, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=1, q_read_ev=2, q_req_up=0, q_write_ev=2] [L413] RET init_threads() [L414] CALL fire_delta_events() [L275] COND FALSE !((int )q_read_ev == 0) VAL [a_t=0, c_dr_i=1, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, p_dw_i=1, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=1, q_read_ev=2, q_req_up=0, q_write_ev=2] [L280] COND FALSE !((int )q_write_ev == 0) VAL [a_t=0, c_dr_i=1, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, p_dw_i=1, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=1, q_read_ev=2, q_req_up=0, q_write_ev=2] [L414] RET fire_delta_events() [L415] CALL activate_threads() [L308] int tmp ; [L309] int tmp___0 ; [L313] CALL, EXPR is_do_write_p_triggered() [L62] int __retres1 ; VAL [a_t=0, c_dr_i=1, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, p_dw_i=1, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=1, q_read_ev=2, q_req_up=0, q_write_ev=2] [L65] COND FALSE !((int )p_dw_pc == 1) VAL [a_t=0, c_dr_i=1, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, p_dw_i=1, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=1, q_read_ev=2, q_req_up=0, q_write_ev=2] [L75] __retres1 = 0 VAL [__retres1=0, a_t=0, c_dr_i=1, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, p_dw_i=1, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=1, q_read_ev=2, q_req_up=0, q_write_ev=2] [L77] return (__retres1); VAL [\result=0, __retres1=0, a_t=0, c_dr_i=1, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, p_dw_i=1, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=1, q_read_ev=2, q_req_up=0, q_write_ev=2] [L313] RET, EXPR is_do_write_p_triggered() [L313] tmp = is_do_write_p_triggered() [L315] COND FALSE !(\read(tmp)) VAL [a_t=0, c_dr_i=1, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, p_dw_i=1, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=1, q_read_ev=2, q_req_up=0, q_write_ev=2, tmp=0] [L321] CALL, EXPR is_do_read_c_triggered() [L81] int __retres1 ; VAL [a_t=0, c_dr_i=1, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, p_dw_i=1, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=1, q_read_ev=2, q_req_up=0, q_write_ev=2] [L84] COND FALSE !((int )c_dr_pc == 1) VAL [a_t=0, c_dr_i=1, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, p_dw_i=1, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=1, q_read_ev=2, q_req_up=0, q_write_ev=2] [L94] __retres1 = 0 VAL [__retres1=0, a_t=0, c_dr_i=1, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, p_dw_i=1, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=1, q_read_ev=2, q_req_up=0, q_write_ev=2] [L96] return (__retres1); VAL [\result=0, __retres1=0, a_t=0, c_dr_i=1, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, p_dw_i=1, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=1, q_read_ev=2, q_req_up=0, q_write_ev=2] [L321] RET, EXPR is_do_read_c_triggered() [L321] tmp___0 = is_do_read_c_triggered() [L323] COND FALSE !(\read(tmp___0)) VAL [a_t=0, c_dr_i=1, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, p_dw_i=1, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=1, q_read_ev=2, q_req_up=0, q_write_ev=2, tmp=0, tmp___0=0] [L415] RET activate_threads() [L416] CALL reset_delta_events() [L293] COND FALSE !((int )q_read_ev == 1) VAL [a_t=0, c_dr_i=1, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, p_dw_i=1, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=1, q_read_ev=2, q_req_up=0, q_write_ev=2] [L298] COND FALSE !((int )q_write_ev == 1) VAL [a_t=0, c_dr_i=1, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, p_dw_i=1, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=1, q_read_ev=2, q_req_up=0, q_write_ev=2] [L416] RET reset_delta_events() [L419] COND TRUE 1 VAL [a_t=0, c_dr_i=1, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, kernel_st=0, p_dw_i=1, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=1, q_read_ev=2, q_req_up=0, q_write_ev=2] [L422] kernel_st = 1 [L423] CALL eval() [L333] int tmp ; [L334] int tmp___0 ; [L335] int tmp___1 ; VAL [a_t=0, c_dr_i=1, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, p_dw_i=1, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=1, q_read_ev=2, q_req_up=0, q_write_ev=2] Loop: [L339] COND TRUE 1 [L342] CALL, EXPR exists_runnable_thread() [L252] int __retres1 ; [L255] COND TRUE (int )p_dw_st == 0 [L256] __retres1 = 1 [L268] return (__retres1); [L342] RET, EXPR exists_runnable_thread() [L342] tmp___1 = exists_runnable_thread() [L344] COND TRUE \read(tmp___1) [L349] COND TRUE (int )p_dw_st == 0 [L351] tmp = __VERIFIER_nondet_int() [L353] COND FALSE !(\read(tmp)) [L364] COND TRUE (int )c_dr_st == 0 [L366] tmp___0 = __VERIFIER_nondet_int() [L368] COND FALSE !(\read(tmp___0)) End of lasso representation. RESULT: Ultimate proved your program to be incorrect! [2023-11-12 02:32:21,137 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7b9c22fa-3e82-4a9e-bded-316d6416295d/bin/uautomizer-verify-uTZkv6EMXl/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (1)] Forceful destruction successful, exit code 0 Received shutdown request... --- End real Ultimate output --- Execution finished normally Writing output log to file Ultimate.log Writing human readable error path to file UltimateCounterExample.errorpath Result: FALSE(TERM)