./Ultimate.py --spec ../../sv-benchmarks/c/properties/termination.prp --file ../../sv-benchmarks/c/systemc/pc_sfifo_3.cil.c --full-output --architecture 32bit -------------------------------------------------------------------------------- Checking for termination Using default analysis Version cf1a7837 Calling Ultimate with: /usr/lib/jvm/java-11-openjdk-amd64/bin/java -Dosgi.configuration.area=/tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_91a087e5-1716-4e19-8e40-2ed3c2dea3c1/bin/uautomizer-verify-uTZkv6EMXl/data/config -Xmx15G -Xms4m -jar /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_91a087e5-1716-4e19-8e40-2ed3c2dea3c1/bin/uautomizer-verify-uTZkv6EMXl/plugins/org.eclipse.equinox.launcher_1.5.800.v20200727-1323.jar -data @noDefault -ultimatedata /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_91a087e5-1716-4e19-8e40-2ed3c2dea3c1/bin/uautomizer-verify-uTZkv6EMXl/data -tc /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_91a087e5-1716-4e19-8e40-2ed3c2dea3c1/bin/uautomizer-verify-uTZkv6EMXl/config/AutomizerTermination.xml -i ../../sv-benchmarks/c/systemc/pc_sfifo_3.cil.c -s /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_91a087e5-1716-4e19-8e40-2ed3c2dea3c1/bin/uautomizer-verify-uTZkv6EMXl/config/svcomp-Termination-32bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_91a087e5-1716-4e19-8e40-2ed3c2dea3c1/bin/uautomizer-verify-uTZkv6EMXl --witnessprinter.witness.filename witness --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(F end) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 32bit --witnessprinter.graph.data.programhash 677126e8d6773c92cc337bfe0a3ec155f49f784424155f33a8c9c24ee0a42113 --- Real Ultimate output --- This is Ultimate 0.2.3-dev-cf1a783 [2023-11-12 02:21:11,457 INFO L188 SettingsManager]: Resetting all preferences to default values... [2023-11-12 02:21:11,583 INFO L114 SettingsManager]: Loading settings from /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_91a087e5-1716-4e19-8e40-2ed3c2dea3c1/bin/uautomizer-verify-uTZkv6EMXl/config/svcomp-Termination-32bit-Automizer_Default.epf [2023-11-12 02:21:11,593 WARN L101 SettingsManager]: Preference file contains the following unknown settings: [2023-11-12 02:21:11,595 WARN L103 SettingsManager]: * de.uni_freiburg.informatik.ultimate.core.Log level for class [2023-11-12 02:21:11,654 INFO L130 SettingsManager]: Preferences different from defaults after loading the file: [2023-11-12 02:21:11,656 INFO L151 SettingsManager]: Preferences of UltimateCore differ from their defaults: [2023-11-12 02:21:11,656 INFO L153 SettingsManager]: * Log level for class=de.uni_freiburg.informatik.ultimate.lib.smtlibutils.quantifier.QuantifierPusher=ERROR; [2023-11-12 02:21:11,657 INFO L151 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2023-11-12 02:21:11,662 INFO L153 SettingsManager]: * Create parallel compositions if possible=false [2023-11-12 02:21:11,663 INFO L153 SettingsManager]: * Use SBE=true [2023-11-12 02:21:11,664 INFO L151 SettingsManager]: Preferences of BuchiAutomizer differ from their defaults: [2023-11-12 02:21:11,664 INFO L153 SettingsManager]: * NCSB implementation=INTSET_LAZY3 [2023-11-12 02:21:11,666 INFO L153 SettingsManager]: * Use old map elimination=false [2023-11-12 02:21:11,666 INFO L153 SettingsManager]: * Use external solver (rank synthesis)=false [2023-11-12 02:21:11,667 INFO L153 SettingsManager]: * Use only trivial implications for array writes=true [2023-11-12 02:21:11,667 INFO L153 SettingsManager]: * Rank analysis=LINEAR_WITH_GUESSES [2023-11-12 02:21:11,668 INFO L151 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2023-11-12 02:21:11,669 INFO L153 SettingsManager]: * Pointer base address is valid at dereference=ASSUME [2023-11-12 02:21:11,669 INFO L153 SettingsManager]: * sizeof long=4 [2023-11-12 02:21:11,669 INFO L153 SettingsManager]: * Overapproximate operations on floating types=true [2023-11-12 02:21:11,670 INFO L153 SettingsManager]: * sizeof POINTER=4 [2023-11-12 02:21:11,670 INFO L153 SettingsManager]: * Check division by zero=IGNORE [2023-11-12 02:21:11,671 INFO L153 SettingsManager]: * Pointer to allocated memory at dereference=ASSUME [2023-11-12 02:21:11,671 INFO L153 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=ASSUME [2023-11-12 02:21:11,672 INFO L153 SettingsManager]: * Check array bounds for arrays that are off heap=ASSUME [2023-11-12 02:21:11,672 INFO L153 SettingsManager]: * Check unreachability of reach_error function=false [2023-11-12 02:21:11,672 INFO L153 SettingsManager]: * sizeof long double=12 [2023-11-12 02:21:11,673 INFO L153 SettingsManager]: * Check if freed pointer was valid=false [2023-11-12 02:21:11,673 INFO L153 SettingsManager]: * Assume nondeterminstic values are in range=false [2023-11-12 02:21:11,674 INFO L153 SettingsManager]: * Use constant arrays=true [2023-11-12 02:21:11,687 INFO L151 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2023-11-12 02:21:11,687 INFO L153 SettingsManager]: * Size of a code block=SequenceOfStatements [2023-11-12 02:21:11,687 INFO L151 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2023-11-12 02:21:11,687 INFO L153 SettingsManager]: * Trace refinement strategy=CAMEL [2023-11-12 02:21:11,688 INFO L151 SettingsManager]: Preferences of IcfgTransformer differ from their defaults: [2023-11-12 02:21:11,688 INFO L153 SettingsManager]: * TransformationType=MODULO_NEIGHBOR WARNING: An illegal reflective access operation has occurred WARNING: Illegal reflective access by com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 (file:/tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_91a087e5-1716-4e19-8e40-2ed3c2dea3c1/bin/uautomizer-verify-uTZkv6EMXl/plugins/com.sun.xml.bind_2.2.0.v201505121915.jar) to method java.lang.ClassLoader.defineClass(java.lang.String,byte[],int,int) WARNING: Please consider reporting this to the maintainers of com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 WARNING: Use --illegal-access=warn to enable warnings of further illegal reflective access operations WARNING: All illegal access operations will be denied in a future release Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_91a087e5-1716-4e19-8e40-2ed3c2dea3c1/bin/uautomizer-verify-uTZkv6EMXl Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(F end) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 32bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> 677126e8d6773c92cc337bfe0a3ec155f49f784424155f33a8c9c24ee0a42113 [2023-11-12 02:21:11,996 INFO L75 nceAwareModelManager]: Repository-Root is: /tmp [2023-11-12 02:21:12,040 INFO L261 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2023-11-12 02:21:12,043 INFO L217 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2023-11-12 02:21:12,044 INFO L270 PluginConnector]: Initializing CDTParser... [2023-11-12 02:21:12,045 INFO L274 PluginConnector]: CDTParser initialized [2023-11-12 02:21:12,047 INFO L431 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_91a087e5-1716-4e19-8e40-2ed3c2dea3c1/bin/uautomizer-verify-uTZkv6EMXl/../../sv-benchmarks/c/systemc/pc_sfifo_3.cil.c [2023-11-12 02:21:15,100 INFO L533 CDTParser]: Created temporary CDT project at NULL [2023-11-12 02:21:15,451 INFO L384 CDTParser]: Found 1 translation units. [2023-11-12 02:21:15,453 INFO L180 CDTParser]: Scanning /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_91a087e5-1716-4e19-8e40-2ed3c2dea3c1/sv-benchmarks/c/systemc/pc_sfifo_3.cil.c [2023-11-12 02:21:15,471 INFO L427 CDTParser]: About to delete temporary CDT project at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_91a087e5-1716-4e19-8e40-2ed3c2dea3c1/bin/uautomizer-verify-uTZkv6EMXl/data/075caa9eb/1500e6723e8642ea8121b6c925fc625c/FLAGf7b049c52 [2023-11-12 02:21:15,490 INFO L435 CDTParser]: Successfully deleted /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_91a087e5-1716-4e19-8e40-2ed3c2dea3c1/bin/uautomizer-verify-uTZkv6EMXl/data/075caa9eb/1500e6723e8642ea8121b6c925fc625c [2023-11-12 02:21:15,496 INFO L299 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2023-11-12 02:21:15,499 INFO L133 ToolchainWalker]: Walking toolchain with 6 elements. [2023-11-12 02:21:15,502 INFO L112 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2023-11-12 02:21:15,503 INFO L270 PluginConnector]: Initializing CACSL2BoogieTranslator... [2023-11-12 02:21:15,509 INFO L274 PluginConnector]: CACSL2BoogieTranslator initialized [2023-11-12 02:21:15,510 INFO L184 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 12.11 02:21:15" (1/1) ... [2023-11-12 02:21:15,511 INFO L204 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@14091061 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 12.11 02:21:15, skipping insertion in model container [2023-11-12 02:21:15,512 INFO L184 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 12.11 02:21:15" (1/1) ... [2023-11-12 02:21:15,571 INFO L177 MainTranslator]: Built tables and reachable declarations [2023-11-12 02:21:15,814 INFO L209 PostProcessor]: Analyzing one entry point: main [2023-11-12 02:21:15,830 INFO L202 MainTranslator]: Completed pre-run [2023-11-12 02:21:15,877 INFO L209 PostProcessor]: Analyzing one entry point: main [2023-11-12 02:21:15,899 INFO L206 MainTranslator]: Completed translation [2023-11-12 02:21:15,900 INFO L201 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 12.11 02:21:15 WrapperNode [2023-11-12 02:21:15,900 INFO L131 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2023-11-12 02:21:15,902 INFO L112 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2023-11-12 02:21:15,902 INFO L270 PluginConnector]: Initializing Boogie Procedure Inliner... [2023-11-12 02:21:15,902 INFO L274 PluginConnector]: Boogie Procedure Inliner initialized [2023-11-12 02:21:15,912 INFO L184 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 12.11 02:21:15" (1/1) ... [2023-11-12 02:21:15,926 INFO L184 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 12.11 02:21:15" (1/1) ... [2023-11-12 02:21:15,965 INFO L138 Inliner]: procedures = 31, calls = 36, calls flagged for inlining = 31, calls inlined = 35, statements flattened = 410 [2023-11-12 02:21:15,966 INFO L131 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2023-11-12 02:21:15,967 INFO L112 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2023-11-12 02:21:15,967 INFO L270 PluginConnector]: Initializing Boogie Preprocessor... [2023-11-12 02:21:15,967 INFO L274 PluginConnector]: Boogie Preprocessor initialized [2023-11-12 02:21:15,978 INFO L184 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 12.11 02:21:15" (1/1) ... [2023-11-12 02:21:15,978 INFO L184 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 12.11 02:21:15" (1/1) ... [2023-11-12 02:21:15,983 INFO L184 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 12.11 02:21:15" (1/1) ... [2023-11-12 02:21:15,983 INFO L184 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 12.11 02:21:15" (1/1) ... [2023-11-12 02:21:15,994 INFO L184 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 12.11 02:21:15" (1/1) ... [2023-11-12 02:21:16,003 INFO L184 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 12.11 02:21:15" (1/1) ... [2023-11-12 02:21:16,006 INFO L184 PluginConnector]: Executing the observer LTLStepAnnotator from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 12.11 02:21:15" (1/1) ... [2023-11-12 02:21:16,009 INFO L184 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 12.11 02:21:15" (1/1) ... [2023-11-12 02:21:16,014 INFO L131 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2023-11-12 02:21:16,016 INFO L112 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2023-11-12 02:21:16,016 INFO L270 PluginConnector]: Initializing RCFGBuilder... [2023-11-12 02:21:16,016 INFO L274 PluginConnector]: RCFGBuilder initialized [2023-11-12 02:21:16,017 INFO L184 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 12.11 02:21:15" (1/1) ... [2023-11-12 02:21:16,025 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2023-11-12 02:21:16,043 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_91a087e5-1716-4e19-8e40-2ed3c2dea3c1/bin/uautomizer-verify-uTZkv6EMXl/z3 [2023-11-12 02:21:16,058 INFO L229 MonitoredProcess]: Starting monitored process 1 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_91a087e5-1716-4e19-8e40-2ed3c2dea3c1/bin/uautomizer-verify-uTZkv6EMXl/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2023-11-12 02:21:16,110 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_91a087e5-1716-4e19-8e40-2ed3c2dea3c1/bin/uautomizer-verify-uTZkv6EMXl/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (1)] Waiting until timeout for monitored process [2023-11-12 02:21:16,138 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocInit [2023-11-12 02:21:16,138 INFO L130 BoogieDeclarations]: Found specification of procedure write~init~int [2023-11-12 02:21:16,138 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2023-11-12 02:21:16,138 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2023-11-12 02:21:16,221 INFO L236 CfgBuilder]: Building ICFG [2023-11-12 02:21:16,223 INFO L262 CfgBuilder]: Building CFG for each procedure with an implementation [2023-11-12 02:21:16,762 INFO L770 $ProcedureCfgBuilder]: dead code at ProgramPoint $Ultimate##104: assume 1 == ~q_free~0;~c_dr_st~0 := 2;~c_dr_pc~0 := 2;~a_t~0 := do_read_c_~a~0#1; [2023-11-12 02:21:16,762 INFO L770 $ProcedureCfgBuilder]: dead code at ProgramPoint $Ultimate##105: assume !(1 == ~q_free~0); [2023-11-12 02:21:16,763 INFO L277 CfgBuilder]: Performing block encoding [2023-11-12 02:21:16,771 INFO L297 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2023-11-12 02:21:16,772 INFO L302 CfgBuilder]: Removed 4 assume(true) statements. [2023-11-12 02:21:16,785 INFO L201 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 12.11 02:21:16 BoogieIcfgContainer [2023-11-12 02:21:16,785 INFO L131 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2023-11-12 02:21:16,786 INFO L112 PluginConnector]: ------------------------BuchiAutomizer---------------------------- [2023-11-12 02:21:16,787 INFO L270 PluginConnector]: Initializing BuchiAutomizer... [2023-11-12 02:21:16,791 INFO L274 PluginConnector]: BuchiAutomizer initialized [2023-11-12 02:21:16,792 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2023-11-12 02:21:16,792 INFO L184 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "CDTParser AST 12.11 02:21:15" (1/3) ... [2023-11-12 02:21:16,793 INFO L204 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@381818ed and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 12.11 02:21:16, skipping insertion in model container [2023-11-12 02:21:16,794 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2023-11-12 02:21:16,794 INFO L184 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 12.11 02:21:15" (2/3) ... [2023-11-12 02:21:16,795 INFO L204 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@381818ed and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 12.11 02:21:16, skipping insertion in model container [2023-11-12 02:21:16,797 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2023-11-12 02:21:16,797 INFO L184 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 12.11 02:21:16" (3/3) ... [2023-11-12 02:21:16,802 INFO L332 chiAutomizerObserver]: Analyzing ICFG pc_sfifo_3.cil.c [2023-11-12 02:21:16,868 INFO L303 stractBuchiCegarLoop]: Interprodecural is true [2023-11-12 02:21:16,868 INFO L304 stractBuchiCegarLoop]: Hoare is false [2023-11-12 02:21:16,868 INFO L305 stractBuchiCegarLoop]: Compute interpolants for ForwardPredicates [2023-11-12 02:21:16,868 INFO L306 stractBuchiCegarLoop]: Backedges is STRAIGHT_LINE [2023-11-12 02:21:16,868 INFO L307 stractBuchiCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2023-11-12 02:21:16,869 INFO L308 stractBuchiCegarLoop]: Difference is false [2023-11-12 02:21:16,869 INFO L309 stractBuchiCegarLoop]: Minimize is MINIMIZE_SEVPA [2023-11-12 02:21:16,869 INFO L313 stractBuchiCegarLoop]: ======== Iteration 0 == of CEGAR loop == BuchiAutomatonCegarLoop ======== [2023-11-12 02:21:16,875 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 144 states, 143 states have (on average 1.5524475524475525) internal successors, (222), 143 states have internal predecessors, (222), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-12 02:21:16,906 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 104 [2023-11-12 02:21:16,906 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-12 02:21:16,906 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-12 02:21:16,917 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-12 02:21:16,917 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-12 02:21:16,917 INFO L335 stractBuchiCegarLoop]: ======== Iteration 1 ============ [2023-11-12 02:21:16,919 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 144 states, 143 states have (on average 1.5524475524475525) internal successors, (222), 143 states have internal predecessors, (222), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-12 02:21:16,928 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 104 [2023-11-12 02:21:16,928 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-12 02:21:16,928 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-12 02:21:16,931 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-12 02:21:16,931 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-12 02:21:16,938 INFO L748 eck$LassoCheckResult]: Stem: 22#$Ultimate##0true assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(17, 2);call #Ultimate.allocInit(12, 3);~fast_clk_edge~0 := 0;~slow_clk_edge~0 := 0;~q_buf_0~0 := 0;~q_free~0 := 0;~q_read_ev~0 := 0;~q_write_ev~0 := 0;~q_req_up~0 := 0;~q_ev~0 := 0;~p_num_write~0 := 0;~p_last_write~0 := 0;~p_dw_st~0 := 0;~p_dw_pc~0 := 0;~p_dw_i~0 := 0;~c_num_read~0 := 0;~c_last_read~0 := 0;~c_dr_st~0 := 0;~c_dr_pc~0 := 0;~c_dr_i~0 := 0;~a_t~0 := 0;~t~0 := 0; 36#L-1true assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~3#1;havoc main_~__retres1~3#1;assume { :begin_inline_init_model } true;~fast_clk_edge~0 := 2;~slow_clk_edge~0 := 2;~q_free~0 := 1;~q_write_ev~0 := 2;~q_read_ev~0 := ~q_write_ev~0;~p_num_write~0 := 0;~p_dw_pc~0 := 0;~p_dw_i~0 := 1;~c_num_read~0 := 0;~c_dr_pc~0 := 0;~c_dr_i~0 := 1; 140#init_model_returnLabel#1true assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret13#1, start_simulation_#t~ret14#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~4#1, start_simulation_~tmp___0~3#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~4#1;havoc start_simulation_~tmp___0~3#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 25#L258true assume !(1 == ~q_req_up~0); 69#L258-2true assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 60#L273true assume 1 == ~p_dw_i~0;~p_dw_st~0 := 0; 114#L273-2true assume !(1 == ~c_dr_i~0);~c_dr_st~0 := 2; 101#L278-1true assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 47#L311true assume !(0 == ~q_read_ev~0); 102#L311-2true assume !(0 == ~q_write_ev~0); 78#L316-1true assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;assume { :begin_inline_is_do_write_p_triggered } true;havoc is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;havoc is_do_write_p_triggered_~__retres1~0#1; 31#L66true assume 1 == ~p_dw_pc~0; 131#L67true assume 1 == ~fast_clk_edge~0;is_do_write_p_triggered_~__retres1~0#1 := 1; 55#L87true is_do_write_p_triggered_#res#1 := is_do_write_p_triggered_~__retres1~0#1; 98#is_do_write_p_triggered_returnLabel#1true activate_threads_#t~ret7#1 := is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;assume { :end_inline_is_do_write_p_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1; 53#L387true assume !(0 != activate_threads_~tmp~1#1); 106#L387-2true assume { :begin_inline_is_do_read_c_triggered } true;havoc is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;havoc is_do_read_c_triggered_~__retres1~1#1; 86#L95true assume 1 == ~c_dr_pc~0; 120#L96true assume 1 == ~slow_clk_edge~0;is_do_read_c_triggered_~__retres1~1#1 := 1; 21#L116true is_do_read_c_triggered_#res#1 := is_do_read_c_triggered_~__retres1~1#1; 27#is_do_read_c_triggered_returnLabel#1true activate_threads_#t~ret8#1 := is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;assume { :end_inline_is_do_read_c_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 79#L395true assume !(0 != activate_threads_~tmp___0~1#1); 11#L395-2true havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 28#L329true assume 1 == ~q_read_ev~0;~q_read_ev~0 := 2; 56#L329-2true assume !(1 == ~q_write_ev~0); 33#L334-1true assume { :end_inline_reset_delta_events } true; 128#L491-2true [2023-11-12 02:21:16,940 INFO L750 eck$LassoCheckResult]: Loop: 128#L491-2true assume !false; 129#L492true start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret9#1, eval_#t~nondet10#1, eval_#t~nondet11#1, eval_~tmp~2#1, eval_~tmp___0~2#1, eval_~tmp___1~0#1;havoc eval_~tmp~2#1;havoc eval_~tmp___0~2#1;havoc eval_~tmp___1~0#1; 97#L435true assume !true; 82#eval_returnLabel#1true havoc eval_#t~ret9#1, eval_#t~nondet10#1, eval_#t~nondet11#1, eval_~tmp~2#1, eval_~tmp___0~2#1, eval_~tmp___1~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 59#L258-3true assume !(1 == ~q_req_up~0); 109#L258-5true assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 132#L311-3true assume 0 == ~q_read_ev~0;~q_read_ev~0 := 1; 115#L311-5true assume 0 == ~q_write_ev~0;~q_write_ev~0 := 1; 70#L316-3true assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;assume { :begin_inline_is_do_write_p_triggered } true;havoc is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;havoc is_do_write_p_triggered_~__retres1~0#1; 113#L66-3true assume 1 == ~p_dw_pc~0; 94#L67-1true assume 1 == ~fast_clk_edge~0;is_do_write_p_triggered_~__retres1~0#1 := 1; 8#L87-1true is_do_write_p_triggered_#res#1 := is_do_write_p_triggered_~__retres1~0#1; 63#is_do_write_p_triggered_returnLabel#2true activate_threads_#t~ret7#1 := is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;assume { :end_inline_is_do_write_p_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1; 124#L387-3true assume 0 != activate_threads_~tmp~1#1;~p_dw_st~0 := 0; 32#L387-5true assume { :begin_inline_is_do_read_c_triggered } true;havoc is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;havoc is_do_read_c_triggered_~__retres1~1#1; 126#L95-3true assume 1 == ~c_dr_pc~0; 65#L96-1true assume 1 == ~slow_clk_edge~0;is_do_read_c_triggered_~__retres1~1#1 := 1; 104#L116-1true is_do_read_c_triggered_#res#1 := is_do_read_c_triggered_~__retres1~1#1; 35#is_do_read_c_triggered_returnLabel#2true activate_threads_#t~ret8#1 := is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;assume { :end_inline_is_do_read_c_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 133#L395-3true assume 0 != activate_threads_~tmp___0~1#1;~c_dr_st~0 := 0; 16#L395-5true havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 41#L329-3true assume 1 == ~q_read_ev~0;~q_read_ev~0 := 2; 90#L329-5true assume 1 == ~q_write_ev~0;~q_write_ev~0 := 2; 142#L334-3true assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 51#L291-1true assume 0 == ~p_dw_st~0;exists_runnable_thread_~__retres1~2#1 := 1; 105#L303-1true exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 100#exists_runnable_thread_returnLabel#2true start_simulation_#t~ret13#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~4#1 := start_simulation_#t~ret13#1;havoc start_simulation_#t~ret13#1; 80#L510true assume !(0 == start_simulation_~tmp~4#1); 6#L510-2true assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret12#1, stop_simulation_~tmp~3#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~3#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 75#L291-2true assume 0 == ~p_dw_st~0;exists_runnable_thread_~__retres1~2#1 := 1; 93#L303-2true exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 30#exists_runnable_thread_returnLabel#3true stop_simulation_#t~ret12#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~3#1 := stop_simulation_#t~ret12#1;havoc stop_simulation_#t~ret12#1; 143#L465true assume 0 != stop_simulation_~tmp~3#1;stop_simulation_~__retres2~0#1 := 0; 29#L472true stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 145#stop_simulation_returnLabel#1true start_simulation_#t~ret14#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret12#1, stop_simulation_~tmp~3#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~3#1 := start_simulation_#t~ret14#1;havoc start_simulation_#t~ret14#1; 77#L523true assume !(0 != start_simulation_~tmp___0~3#1); 128#L491-2true [2023-11-12 02:21:16,947 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-12 02:21:16,947 INFO L85 PathProgramCache]: Analyzing trace with hash 854607455, now seen corresponding path program 1 times [2023-11-12 02:21:16,958 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-12 02:21:16,959 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [381374805] [2023-11-12 02:21:16,959 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-12 02:21:16,960 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-12 02:21:17,067 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-12 02:21:17,173 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-12 02:21:17,174 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-12 02:21:17,174 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [381374805] [2023-11-12 02:21:17,175 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [381374805] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-12 02:21:17,175 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-12 02:21:17,176 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-12 02:21:17,178 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [303867582] [2023-11-12 02:21:17,179 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-12 02:21:17,184 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-12 02:21:17,187 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-12 02:21:17,187 INFO L85 PathProgramCache]: Analyzing trace with hash 1919014688, now seen corresponding path program 1 times [2023-11-12 02:21:17,187 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-12 02:21:17,188 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1599961302] [2023-11-12 02:21:17,188 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-12 02:21:17,188 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-12 02:21:17,202 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-12 02:21:17,224 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-12 02:21:17,224 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-12 02:21:17,225 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1599961302] [2023-11-12 02:21:17,225 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1599961302] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-12 02:21:17,225 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-12 02:21:17,226 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2023-11-12 02:21:17,226 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1645601415] [2023-11-12 02:21:17,226 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-12 02:21:17,228 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-12 02:21:17,229 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-12 02:21:17,265 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-12 02:21:17,266 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-12 02:21:17,269 INFO L87 Difference]: Start difference. First operand has 144 states, 143 states have (on average 1.5524475524475525) internal successors, (222), 143 states have internal predecessors, (222), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand has 3 states, 3 states have (on average 8.666666666666666) internal successors, (26), 3 states have internal predecessors, (26), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-12 02:21:17,315 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-12 02:21:17,316 INFO L93 Difference]: Finished difference Result 140 states and 207 transitions. [2023-11-12 02:21:17,317 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 140 states and 207 transitions. [2023-11-12 02:21:17,338 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 98 [2023-11-12 02:21:17,344 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 140 states to 134 states and 201 transitions. [2023-11-12 02:21:17,345 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 134 [2023-11-12 02:21:17,346 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 134 [2023-11-12 02:21:17,346 INFO L73 IsDeterministic]: Start isDeterministic. Operand 134 states and 201 transitions. [2023-11-12 02:21:17,348 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-12 02:21:17,348 INFO L218 hiAutomatonCegarLoop]: Abstraction has 134 states and 201 transitions. [2023-11-12 02:21:17,364 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 134 states and 201 transitions. [2023-11-12 02:21:17,380 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 134 to 134. [2023-11-12 02:21:17,381 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 134 states, 134 states have (on average 1.5) internal successors, (201), 133 states have internal predecessors, (201), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-12 02:21:17,384 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 134 states to 134 states and 201 transitions. [2023-11-12 02:21:17,385 INFO L240 hiAutomatonCegarLoop]: Abstraction has 134 states and 201 transitions. [2023-11-12 02:21:17,386 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-12 02:21:17,391 INFO L428 stractBuchiCegarLoop]: Abstraction has 134 states and 201 transitions. [2023-11-12 02:21:17,391 INFO L335 stractBuchiCegarLoop]: ======== Iteration 2 ============ [2023-11-12 02:21:17,391 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 134 states and 201 transitions. [2023-11-12 02:21:17,393 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 98 [2023-11-12 02:21:17,393 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-12 02:21:17,393 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-12 02:21:17,395 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-12 02:21:17,395 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-12 02:21:17,396 INFO L748 eck$LassoCheckResult]: Stem: 334#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(17, 2);call #Ultimate.allocInit(12, 3);~fast_clk_edge~0 := 0;~slow_clk_edge~0 := 0;~q_buf_0~0 := 0;~q_free~0 := 0;~q_read_ev~0 := 0;~q_write_ev~0 := 0;~q_req_up~0 := 0;~q_ev~0 := 0;~p_num_write~0 := 0;~p_last_write~0 := 0;~p_dw_st~0 := 0;~p_dw_pc~0 := 0;~p_dw_i~0 := 0;~c_num_read~0 := 0;~c_last_read~0 := 0;~c_dr_st~0 := 0;~c_dr_pc~0 := 0;~c_dr_i~0 := 0;~a_t~0 := 0;~t~0 := 0; 335#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~3#1;havoc main_~__retres1~3#1;assume { :begin_inline_init_model } true;~fast_clk_edge~0 := 2;~slow_clk_edge~0 := 2;~q_free~0 := 1;~q_write_ev~0 := 2;~q_read_ev~0 := ~q_write_ev~0;~p_num_write~0 := 0;~p_dw_pc~0 := 0;~p_dw_i~0 := 1;~c_num_read~0 := 0;~c_dr_pc~0 := 0;~c_dr_i~0 := 1; 359#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret13#1, start_simulation_#t~ret14#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~4#1, start_simulation_~tmp___0~3#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~4#1;havoc start_simulation_~tmp___0~3#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 339#L258 assume !(1 == ~q_req_up~0); 341#L258-2 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 393#L273 assume 1 == ~p_dw_i~0;~p_dw_st~0 := 0; 394#L273-2 assume 1 == ~c_dr_i~0;~c_dr_st~0 := 0; 418#L278-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 372#L311 assume !(0 == ~q_read_ev~0); 373#L311-2 assume !(0 == ~q_write_ev~0); 405#L316-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;assume { :begin_inline_is_do_write_p_triggered } true;havoc is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;havoc is_do_write_p_triggered_~__retres1~0#1; 348#L66 assume 1 == ~p_dw_pc~0; 350#L67 assume 1 == ~fast_clk_edge~0;is_do_write_p_triggered_~__retres1~0#1 := 1; 386#L87 is_do_write_p_triggered_#res#1 := is_do_write_p_triggered_~__retres1~0#1; 387#is_do_write_p_triggered_returnLabel#1 activate_threads_#t~ret7#1 := is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;assume { :end_inline_is_do_write_p_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1; 382#L387 assume !(0 != activate_threads_~tmp~1#1); 383#L387-2 assume { :begin_inline_is_do_read_c_triggered } true;havoc is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;havoc is_do_read_c_triggered_~__retres1~1#1; 411#L95 assume 1 == ~c_dr_pc~0; 413#L96 assume 1 == ~slow_clk_edge~0;is_do_read_c_triggered_~__retres1~1#1 := 1; 330#L116 is_do_read_c_triggered_#res#1 := is_do_read_c_triggered_~__retres1~1#1; 331#is_do_read_c_triggered_returnLabel#1 activate_threads_#t~ret8#1 := is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;assume { :end_inline_is_do_read_c_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 342#L395 assume !(0 != activate_threads_~tmp___0~1#1); 308#L395-2 havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 309#L329 assume 1 == ~q_read_ev~0;~q_read_ev~0 := 2; 345#L329-2 assume !(1 == ~q_write_ev~0); 353#L334-1 assume { :end_inline_reset_delta_events } true; 354#L491-2 [2023-11-12 02:21:17,396 INFO L750 eck$LassoCheckResult]: Loop: 354#L491-2 assume !false; 426#L492 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret9#1, eval_#t~nondet10#1, eval_#t~nondet11#1, eval_~tmp~2#1, eval_~tmp___0~2#1, eval_~tmp___1~0#1;havoc eval_~tmp~2#1;havoc eval_~tmp___0~2#1;havoc eval_~tmp___1~0#1; 356#L435 assume !false; 388#L411 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 389#L291 assume 0 == ~p_dw_st~0;exists_runnable_thread_~__retres1~2#1 := 1; 299#L303 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 312#exists_runnable_thread_returnLabel#1 eval_#t~ret9#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp___1~0#1 := eval_#t~ret9#1;havoc eval_#t~ret9#1; 313#L415 assume !(0 != eval_~tmp___1~0#1); 409#eval_returnLabel#1 havoc eval_#t~ret9#1, eval_#t~nondet10#1, eval_#t~nondet11#1, eval_~tmp~2#1, eval_~tmp___0~2#1, eval_~tmp___1~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 390#L258-3 assume !(1 == ~q_req_up~0); 392#L258-5 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 420#L311-3 assume 0 == ~q_read_ev~0;~q_read_ev~0 := 1; 424#L311-5 assume 0 == ~q_write_ev~0;~q_write_ev~0 := 1; 402#L316-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;assume { :begin_inline_is_do_write_p_triggered } true;havoc is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;havoc is_do_write_p_triggered_~__retres1~0#1; 403#L66-3 assume 1 == ~p_dw_pc~0; 416#L67-1 assume 1 == ~fast_clk_edge~0;is_do_write_p_triggered_~__retres1~0#1 := 1; 303#L87-1 is_do_write_p_triggered_#res#1 := is_do_write_p_triggered_~__retres1~0#1; 305#is_do_write_p_triggered_returnLabel#2 activate_threads_#t~ret7#1 := is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;assume { :end_inline_is_do_write_p_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1; 396#L387-3 assume 0 != activate_threads_~tmp~1#1;~p_dw_st~0 := 0; 351#L387-5 assume { :begin_inline_is_do_read_c_triggered } true;havoc is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;havoc is_do_read_c_triggered_~__retres1~1#1; 352#L95-3 assume 1 == ~c_dr_pc~0; 397#L96-1 assume 1 == ~slow_clk_edge~0;is_do_read_c_triggered_~__retres1~1#1 := 1; 398#L116-1 is_do_read_c_triggered_#res#1 := is_do_read_c_triggered_~__retres1~1#1; 357#is_do_read_c_triggered_returnLabel#2 activate_threads_#t~ret8#1 := is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;assume { :end_inline_is_do_read_c_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 358#L395-3 assume 0 != activate_threads_~tmp___0~1#1;~c_dr_st~0 := 0; 318#L395-5 havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 319#L329-3 assume 1 == ~q_read_ev~0;~q_read_ev~0 := 2; 366#L329-5 assume 1 == ~q_write_ev~0;~q_write_ev~0 := 2; 414#L334-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 379#L291-1 assume 0 == ~p_dw_st~0;exists_runnable_thread_~__retres1~2#1 := 1; 381#L303-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 417#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret13#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~4#1 := start_simulation_#t~ret13#1;havoc start_simulation_#t~ret13#1; 406#L510 assume !(0 == start_simulation_~tmp~4#1); 300#L510-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret12#1, stop_simulation_~tmp~3#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~3#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 301#L291-2 assume 0 == ~p_dw_st~0;exists_runnable_thread_~__retres1~2#1 := 1; 333#L303-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 346#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret12#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~3#1 := stop_simulation_#t~ret12#1;havoc stop_simulation_#t~ret12#1; 347#L465 assume 0 != stop_simulation_~tmp~3#1;stop_simulation_~__retres2~0#1 := 0; 343#L472 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 344#stop_simulation_returnLabel#1 start_simulation_#t~ret14#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret12#1, stop_simulation_~tmp~3#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~3#1 := start_simulation_#t~ret14#1;havoc start_simulation_#t~ret14#1; 404#L523 assume !(0 != start_simulation_~tmp___0~3#1); 354#L491-2 [2023-11-12 02:21:17,397 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-12 02:21:17,397 INFO L85 PathProgramCache]: Analyzing trace with hash 1672255905, now seen corresponding path program 1 times [2023-11-12 02:21:17,397 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-12 02:21:17,398 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [625958162] [2023-11-12 02:21:17,398 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-12 02:21:17,398 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-12 02:21:17,419 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-12 02:21:17,537 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-12 02:21:17,537 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-12 02:21:17,538 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [625958162] [2023-11-12 02:21:17,538 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [625958162] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-12 02:21:17,538 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-12 02:21:17,538 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2023-11-12 02:21:17,539 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1924726236] [2023-11-12 02:21:17,539 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-12 02:21:17,539 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-12 02:21:17,540 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-12 02:21:17,540 INFO L85 PathProgramCache]: Analyzing trace with hash -848315206, now seen corresponding path program 1 times [2023-11-12 02:21:17,540 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-12 02:21:17,541 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1018668720] [2023-11-12 02:21:17,541 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-12 02:21:17,541 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-12 02:21:17,560 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-12 02:21:17,661 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-12 02:21:17,661 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-12 02:21:17,661 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1018668720] [2023-11-12 02:21:17,662 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1018668720] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-12 02:21:17,662 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-12 02:21:17,662 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2023-11-12 02:21:17,662 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2038561355] [2023-11-12 02:21:17,663 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-12 02:21:17,663 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-12 02:21:17,663 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-12 02:21:17,664 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2023-11-12 02:21:17,664 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2023-11-12 02:21:17,664 INFO L87 Difference]: Start difference. First operand 134 states and 201 transitions. cyclomatic complexity: 68 Second operand has 5 states, 5 states have (on average 5.2) internal successors, (26), 4 states have internal predecessors, (26), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-12 02:21:17,890 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-12 02:21:17,891 INFO L93 Difference]: Finished difference Result 479 states and 696 transitions. [2023-11-12 02:21:17,891 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 479 states and 696 transitions. [2023-11-12 02:21:17,897 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 446 [2023-11-12 02:21:17,903 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 479 states to 479 states and 696 transitions. [2023-11-12 02:21:17,903 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 479 [2023-11-12 02:21:17,905 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 479 [2023-11-12 02:21:17,905 INFO L73 IsDeterministic]: Start isDeterministic. Operand 479 states and 696 transitions. [2023-11-12 02:21:17,908 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-12 02:21:17,909 INFO L218 hiAutomatonCegarLoop]: Abstraction has 479 states and 696 transitions. [2023-11-12 02:21:17,910 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 479 states and 696 transitions. [2023-11-12 02:21:17,936 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 479 to 466. [2023-11-12 02:21:17,937 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 466 states, 466 states have (on average 1.4656652360515021) internal successors, (683), 465 states have internal predecessors, (683), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-12 02:21:17,941 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 466 states to 466 states and 683 transitions. [2023-11-12 02:21:17,942 INFO L240 hiAutomatonCegarLoop]: Abstraction has 466 states and 683 transitions. [2023-11-12 02:21:17,942 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2023-11-12 02:21:17,944 INFO L428 stractBuchiCegarLoop]: Abstraction has 466 states and 683 transitions. [2023-11-12 02:21:17,945 INFO L335 stractBuchiCegarLoop]: ======== Iteration 3 ============ [2023-11-12 02:21:17,946 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 466 states and 683 transitions. [2023-11-12 02:21:17,975 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 435 [2023-11-12 02:21:17,976 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-12 02:21:17,976 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-12 02:21:17,977 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-12 02:21:17,978 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-12 02:21:17,978 INFO L748 eck$LassoCheckResult]: Stem: 961#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(17, 2);call #Ultimate.allocInit(12, 3);~fast_clk_edge~0 := 0;~slow_clk_edge~0 := 0;~q_buf_0~0 := 0;~q_free~0 := 0;~q_read_ev~0 := 0;~q_write_ev~0 := 0;~q_req_up~0 := 0;~q_ev~0 := 0;~p_num_write~0 := 0;~p_last_write~0 := 0;~p_dw_st~0 := 0;~p_dw_pc~0 := 0;~p_dw_i~0 := 0;~c_num_read~0 := 0;~c_last_read~0 := 0;~c_dr_st~0 := 0;~c_dr_pc~0 := 0;~c_dr_i~0 := 0;~a_t~0 := 0;~t~0 := 0; 962#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~3#1;havoc main_~__retres1~3#1;assume { :begin_inline_init_model } true;~fast_clk_edge~0 := 2;~slow_clk_edge~0 := 2;~q_free~0 := 1;~q_write_ev~0 := 2;~q_read_ev~0 := ~q_write_ev~0;~p_num_write~0 := 0;~p_dw_pc~0 := 0;~p_dw_i~0 := 1;~c_num_read~0 := 0;~c_dr_pc~0 := 0;~c_dr_i~0 := 1; 985#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret13#1, start_simulation_#t~ret14#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~4#1, start_simulation_~tmp___0~3#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~4#1;havoc start_simulation_~tmp___0~3#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 967#L258 assume !(1 == ~q_req_up~0); 968#L258-2 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 1021#L273 assume 1 == ~p_dw_i~0;~p_dw_st~0 := 0; 1022#L273-2 assume 1 == ~c_dr_i~0;~c_dr_st~0 := 0; 1058#L278-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 1001#L311 assume !(0 == ~q_read_ev~0); 1002#L311-2 assume !(0 == ~q_write_ev~0); 1037#L316-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;assume { :begin_inline_is_do_write_p_triggered } true;havoc is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;havoc is_do_write_p_triggered_~__retres1~0#1; 975#L66 assume !(1 == ~p_dw_pc~0); 976#L66-2 assume !(2 == ~p_dw_pc~0); 990#L76-1 is_do_write_p_triggered_~__retres1~0#1 := 0; 1014#L87 is_do_write_p_triggered_#res#1 := is_do_write_p_triggered_~__retres1~0#1; 1015#is_do_write_p_triggered_returnLabel#1 activate_threads_#t~ret7#1 := is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;assume { :end_inline_is_do_write_p_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1; 1010#L387 assume !(0 != activate_threads_~tmp~1#1); 1011#L387-2 assume { :begin_inline_is_do_read_c_triggered } true;havoc is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;havoc is_do_read_c_triggered_~__retres1~1#1; 1045#L95 assume 1 == ~c_dr_pc~0; 1047#L96 assume 1 == ~slow_clk_edge~0;is_do_read_c_triggered_~__retres1~1#1 := 1; 959#L116 is_do_read_c_triggered_#res#1 := is_do_read_c_triggered_~__retres1~1#1; 960#is_do_read_c_triggered_returnLabel#1 activate_threads_#t~ret8#1 := is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;assume { :end_inline_is_do_read_c_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 969#L395 assume !(0 != activate_threads_~tmp___0~1#1); 936#L395-2 havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 937#L329 assume 1 == ~q_read_ev~0;~q_read_ev~0 := 2; 970#L329-2 assume !(1 == ~q_write_ev~0); 979#L334-1 assume { :end_inline_reset_delta_events } true; 980#L491-2 [2023-11-12 02:21:17,978 INFO L750 eck$LassoCheckResult]: Loop: 980#L491-2 assume !false; 1073#L492 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret9#1, eval_#t~nondet10#1, eval_#t~nondet11#1, eval_~tmp~2#1, eval_~tmp___0~2#1, eval_~tmp___1~0#1;havoc eval_~tmp~2#1;havoc eval_~tmp___0~2#1;havoc eval_~tmp___1~0#1; 1314#L435 assume !false; 1311#L411 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 1307#L291 assume 0 == ~p_dw_st~0;exists_runnable_thread_~__retres1~2#1 := 1; 1076#L303 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 940#exists_runnable_thread_returnLabel#1 eval_#t~ret9#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp___1~0#1 := eval_#t~ret9#1;havoc eval_#t~ret9#1; 941#L415 assume !(0 != eval_~tmp___1~0#1); 1041#eval_returnLabel#1 havoc eval_#t~ret9#1, eval_#t~nondet10#1, eval_#t~nondet11#1, eval_~tmp~2#1, eval_~tmp___0~2#1, eval_~tmp___1~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 1042#L258-3 assume !(1 == ~q_req_up~0); 1287#L258-5 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 1284#L311-3 assume 0 == ~q_read_ev~0;~q_read_ev~0 := 1; 1281#L311-5 assume 0 == ~q_write_ev~0;~q_write_ev~0 := 1; 1277#L316-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;assume { :begin_inline_is_do_write_p_triggered } true;havoc is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;havoc is_do_write_p_triggered_~__retres1~0#1; 1275#L66-3 assume !(1 == ~p_dw_pc~0); 1006#L66-5 assume !(2 == ~p_dw_pc~0); 930#L76-3 is_do_write_p_triggered_~__retres1~0#1 := 0; 931#L87-1 is_do_write_p_triggered_#res#1 := is_do_write_p_triggered_~__retres1~0#1; 932#is_do_write_p_triggered_returnLabel#2 activate_threads_#t~ret7#1 := is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;assume { :end_inline_is_do_write_p_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1; 1024#L387-3 assume 0 != activate_threads_~tmp~1#1;~p_dw_st~0 := 0; 977#L387-5 assume { :begin_inline_is_do_read_c_triggered } true;havoc is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;havoc is_do_read_c_triggered_~__retres1~1#1; 978#L95-3 assume 1 == ~c_dr_pc~0; 1025#L96-1 assume 1 == ~slow_clk_edge~0;is_do_read_c_triggered_~__retres1~1#1 := 1; 1026#L116-1 is_do_read_c_triggered_#res#1 := is_do_read_c_triggered_~__retres1~1#1; 983#is_do_read_c_triggered_returnLabel#2 activate_threads_#t~ret8#1 := is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;assume { :end_inline_is_do_read_c_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 984#L395-3 assume 0 != activate_threads_~tmp___0~1#1;~c_dr_st~0 := 0; 947#L395-5 havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 948#L329-3 assume 1 == ~q_read_ev~0;~q_read_ev~0 := 2; 991#L329-5 assume 1 == ~q_write_ev~0;~q_write_ev~0 := 2; 1051#L334-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 1007#L291-1 assume 0 == ~p_dw_st~0;exists_runnable_thread_~__retres1~2#1 := 1; 1009#L303-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 1057#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret13#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~4#1 := start_simulation_#t~ret13#1;havoc start_simulation_#t~ret13#1; 1038#L510 assume !(0 == start_simulation_~tmp~4#1); 928#L510-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret12#1, stop_simulation_~tmp~3#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~3#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 929#L291-2 assume 0 == ~p_dw_st~0;exists_runnable_thread_~__retres1~2#1 := 1; 964#L303-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 973#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret12#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~3#1 := stop_simulation_#t~ret12#1;havoc stop_simulation_#t~ret12#1; 974#L465 assume 0 != stop_simulation_~tmp~3#1;stop_simulation_~__retres2~0#1 := 0; 971#L472 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 972#stop_simulation_returnLabel#1 start_simulation_#t~ret14#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret12#1, stop_simulation_~tmp~3#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~3#1 := start_simulation_#t~ret14#1;havoc start_simulation_#t~ret14#1; 1036#L523 assume !(0 != start_simulation_~tmp___0~3#1); 980#L491-2 [2023-11-12 02:21:17,979 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-12 02:21:17,979 INFO L85 PathProgramCache]: Analyzing trace with hash -841270075, now seen corresponding path program 1 times [2023-11-12 02:21:17,980 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-12 02:21:17,980 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [943438158] [2023-11-12 02:21:17,980 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-12 02:21:17,980 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-12 02:21:18,021 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-12 02:21:18,170 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-12 02:21:18,172 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-12 02:21:18,173 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [943438158] [2023-11-12 02:21:18,173 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [943438158] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-12 02:21:18,173 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-12 02:21:18,174 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2023-11-12 02:21:18,174 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1458241255] [2023-11-12 02:21:18,174 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-12 02:21:18,174 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-12 02:21:18,175 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-12 02:21:18,175 INFO L85 PathProgramCache]: Analyzing trace with hash 54589687, now seen corresponding path program 1 times [2023-11-12 02:21:18,175 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-12 02:21:18,176 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1549571739] [2023-11-12 02:21:18,176 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-12 02:21:18,176 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-12 02:21:18,196 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-12 02:21:18,284 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-12 02:21:18,285 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-12 02:21:18,285 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1549571739] [2023-11-12 02:21:18,285 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1549571739] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-12 02:21:18,285 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-12 02:21:18,286 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2023-11-12 02:21:18,286 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1305509091] [2023-11-12 02:21:18,286 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-12 02:21:18,287 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-12 02:21:18,287 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-12 02:21:18,287 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2023-11-12 02:21:18,288 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2023-11-12 02:21:18,288 INFO L87 Difference]: Start difference. First operand 466 states and 683 transitions. cyclomatic complexity: 219 Second operand has 5 states, 5 states have (on average 5.4) internal successors, (27), 4 states have internal predecessors, (27), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-12 02:21:18,442 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-12 02:21:18,443 INFO L93 Difference]: Finished difference Result 1105 states and 1581 transitions. [2023-11-12 02:21:18,443 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1105 states and 1581 transitions. [2023-11-12 02:21:18,459 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 1070 [2023-11-12 02:21:18,472 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1105 states to 1105 states and 1581 transitions. [2023-11-12 02:21:18,472 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1105 [2023-11-12 02:21:18,474 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1105 [2023-11-12 02:21:18,474 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1105 states and 1581 transitions. [2023-11-12 02:21:18,477 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-12 02:21:18,477 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1105 states and 1581 transitions. [2023-11-12 02:21:18,480 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1105 states and 1581 transitions. [2023-11-12 02:21:18,525 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1105 to 1072. [2023-11-12 02:21:18,528 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1072 states, 1072 states have (on average 1.4347014925373134) internal successors, (1538), 1071 states have internal predecessors, (1538), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-12 02:21:18,534 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1072 states to 1072 states and 1538 transitions. [2023-11-12 02:21:18,535 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1072 states and 1538 transitions. [2023-11-12 02:21:18,535 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2023-11-12 02:21:18,537 INFO L428 stractBuchiCegarLoop]: Abstraction has 1072 states and 1538 transitions. [2023-11-12 02:21:18,538 INFO L335 stractBuchiCegarLoop]: ======== Iteration 4 ============ [2023-11-12 02:21:18,538 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1072 states and 1538 transitions. [2023-11-12 02:21:18,548 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 1038 [2023-11-12 02:21:18,548 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-12 02:21:18,548 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-12 02:21:18,550 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-12 02:21:18,551 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-12 02:21:18,551 INFO L748 eck$LassoCheckResult]: Stem: 2551#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(17, 2);call #Ultimate.allocInit(12, 3);~fast_clk_edge~0 := 0;~slow_clk_edge~0 := 0;~q_buf_0~0 := 0;~q_free~0 := 0;~q_read_ev~0 := 0;~q_write_ev~0 := 0;~q_req_up~0 := 0;~q_ev~0 := 0;~p_num_write~0 := 0;~p_last_write~0 := 0;~p_dw_st~0 := 0;~p_dw_pc~0 := 0;~p_dw_i~0 := 0;~c_num_read~0 := 0;~c_last_read~0 := 0;~c_dr_st~0 := 0;~c_dr_pc~0 := 0;~c_dr_i~0 := 0;~a_t~0 := 0;~t~0 := 0; 2552#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~3#1;havoc main_~__retres1~3#1;assume { :begin_inline_init_model } true;~fast_clk_edge~0 := 2;~slow_clk_edge~0 := 2;~q_free~0 := 1;~q_write_ev~0 := 2;~q_read_ev~0 := ~q_write_ev~0;~p_num_write~0 := 0;~p_dw_pc~0 := 0;~p_dw_i~0 := 1;~c_num_read~0 := 0;~c_dr_pc~0 := 0;~c_dr_i~0 := 1; 2574#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret13#1, start_simulation_#t~ret14#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~4#1, start_simulation_~tmp___0~3#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~4#1;havoc start_simulation_~tmp___0~3#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 2555#L258 assume !(1 == ~q_req_up~0); 2556#L258-2 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 2611#L273 assume 1 == ~p_dw_i~0;~p_dw_st~0 := 0; 2612#L273-2 assume 1 == ~c_dr_i~0;~c_dr_st~0 := 0; 2655#L278-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 2588#L311 assume !(0 == ~q_read_ev~0); 2589#L311-2 assume !(0 == ~q_write_ev~0); 2630#L316-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;assume { :begin_inline_is_do_write_p_triggered } true;havoc is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;havoc is_do_write_p_triggered_~__retres1~0#1; 2565#L66 assume !(1 == ~p_dw_pc~0); 2566#L66-2 assume !(2 == ~p_dw_pc~0); 2579#L76-1 is_do_write_p_triggered_~__retres1~0#1 := 0; 2606#L87 is_do_write_p_triggered_#res#1 := is_do_write_p_triggered_~__retres1~0#1; 2607#is_do_write_p_triggered_returnLabel#1 activate_threads_#t~ret7#1 := is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;assume { :end_inline_is_do_write_p_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1; 2600#L387 assume !(0 != activate_threads_~tmp~1#1); 2601#L387-2 assume { :begin_inline_is_do_read_c_triggered } true;havoc is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;havoc is_do_read_c_triggered_~__retres1~1#1; 2641#L95 assume !(1 == ~c_dr_pc~0); 2642#L95-2 assume !(2 == ~c_dr_pc~0); 2613#L105-1 is_do_read_c_triggered_~__retres1~1#1 := 0; 2547#L116 is_do_read_c_triggered_#res#1 := is_do_read_c_triggered_~__retres1~1#1; 2548#is_do_read_c_triggered_returnLabel#1 activate_threads_#t~ret8#1 := is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;assume { :end_inline_is_do_read_c_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 2557#L395 assume !(0 != activate_threads_~tmp___0~1#1); 2525#L395-2 havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 2526#L329 assume 1 == ~q_read_ev~0;~q_read_ev~0 := 2; 2560#L329-2 assume !(1 == ~q_write_ev~0); 2570#L334-1 assume { :end_inline_reset_delta_events } true; 2571#L491-2 [2023-11-12 02:21:18,552 INFO L750 eck$LassoCheckResult]: Loop: 2571#L491-2 assume !false; 2945#L492 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret9#1, eval_#t~nondet10#1, eval_#t~nondet11#1, eval_~tmp~2#1, eval_~tmp___0~2#1, eval_~tmp___1~0#1;havoc eval_~tmp~2#1;havoc eval_~tmp___0~2#1;havoc eval_~tmp___1~0#1; 2941#L435 assume !false; 2939#L411 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 2934#L291 assume 0 == ~p_dw_st~0;exists_runnable_thread_~__retres1~2#1 := 1; 2932#L303 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 2930#exists_runnable_thread_returnLabel#1 eval_#t~ret9#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp___1~0#1 := eval_#t~ret9#1;havoc eval_#t~ret9#1; 2926#L415 assume !(0 != eval_~tmp___1~0#1); 2927#eval_returnLabel#1 havoc eval_#t~ret9#1, eval_#t~nondet10#1, eval_#t~nondet11#1, eval_~tmp~2#1, eval_~tmp___0~2#1, eval_~tmp___1~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 3139#L258-3 assume !(1 == ~q_req_up~0); 3137#L258-5 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 3135#L311-3 assume 0 == ~q_read_ev~0;~q_read_ev~0 := 1; 3134#L311-5 assume 0 == ~q_write_ev~0;~q_write_ev~0 := 1; 3133#L316-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;assume { :begin_inline_is_do_write_p_triggered } true;havoc is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;havoc is_do_write_p_triggered_~__retres1~0#1; 3129#L66-3 assume !(1 == ~p_dw_pc~0); 3127#L66-5 assume !(2 == ~p_dw_pc~0); 3125#L76-3 is_do_write_p_triggered_~__retres1~0#1 := 0; 3123#L87-1 is_do_write_p_triggered_#res#1 := is_do_write_p_triggered_~__retres1~0#1; 3008#is_do_write_p_triggered_returnLabel#2 activate_threads_#t~ret7#1 := is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;assume { :end_inline_is_do_write_p_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1; 3004#L387-3 assume 0 != activate_threads_~tmp~1#1;~p_dw_st~0 := 0; 3002#L387-5 assume { :begin_inline_is_do_read_c_triggered } true;havoc is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;havoc is_do_read_c_triggered_~__retres1~1#1; 2999#L95-3 assume !(1 == ~c_dr_pc~0); 2997#L95-5 assume !(2 == ~c_dr_pc~0); 2995#L105-3 is_do_read_c_triggered_~__retres1~1#1 := 0; 2993#L116-1 is_do_read_c_triggered_#res#1 := is_do_read_c_triggered_~__retres1~1#1; 2991#is_do_read_c_triggered_returnLabel#2 activate_threads_#t~ret8#1 := is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;assume { :end_inline_is_do_read_c_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 2989#L395-3 assume 0 != activate_threads_~tmp___0~1#1;~c_dr_st~0 := 0; 2987#L395-5 havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 2985#L329-3 assume 1 == ~q_read_ev~0;~q_read_ev~0 := 2; 2982#L329-5 assume 1 == ~q_write_ev~0;~q_write_ev~0 := 2; 2980#L334-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 2978#L291-1 assume 0 == ~p_dw_st~0;exists_runnable_thread_~__retres1~2#1 := 1; 2973#L303-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 2971#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret13#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~4#1 := start_simulation_#t~ret13#1;havoc start_simulation_#t~ret13#1; 2967#L510 assume !(0 == start_simulation_~tmp~4#1); 2964#L510-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret12#1, stop_simulation_~tmp~3#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~3#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 2962#L291-2 assume 0 == ~p_dw_st~0;exists_runnable_thread_~__retres1~2#1 := 1; 2959#L303-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 2957#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret12#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~3#1 := stop_simulation_#t~ret12#1;havoc stop_simulation_#t~ret12#1; 2955#L465 assume 0 != stop_simulation_~tmp~3#1;stop_simulation_~__retres2~0#1 := 0; 2953#L472 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 2951#stop_simulation_returnLabel#1 start_simulation_#t~ret14#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret12#1, stop_simulation_~tmp~3#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~3#1 := start_simulation_#t~ret14#1;havoc start_simulation_#t~ret14#1; 2950#L523 assume !(0 != start_simulation_~tmp___0~3#1); 2571#L491-2 [2023-11-12 02:21:18,552 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-12 02:21:18,553 INFO L85 PathProgramCache]: Analyzing trace with hash 156116973, now seen corresponding path program 1 times [2023-11-12 02:21:18,553 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-12 02:21:18,553 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2135743558] [2023-11-12 02:21:18,554 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-12 02:21:18,554 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-12 02:21:18,578 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-12 02:21:18,624 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-12 02:21:18,625 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-12 02:21:18,625 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2135743558] [2023-11-12 02:21:18,625 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2135743558] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-12 02:21:18,625 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-12 02:21:18,625 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-12 02:21:18,626 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1981167955] [2023-11-12 02:21:18,626 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-12 02:21:18,626 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-12 02:21:18,627 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-12 02:21:18,627 INFO L85 PathProgramCache]: Analyzing trace with hash 1152921834, now seen corresponding path program 1 times [2023-11-12 02:21:18,627 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-12 02:21:18,627 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1517326278] [2023-11-12 02:21:18,628 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-12 02:21:18,628 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-12 02:21:18,648 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-12 02:21:18,716 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-12 02:21:18,716 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-12 02:21:18,717 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1517326278] [2023-11-12 02:21:18,717 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1517326278] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-12 02:21:18,717 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-12 02:21:18,717 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2023-11-12 02:21:18,718 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1023585703] [2023-11-12 02:21:18,718 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-12 02:21:18,719 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-12 02:21:18,720 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-12 02:21:18,720 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-12 02:21:18,721 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-12 02:21:18,721 INFO L87 Difference]: Start difference. First operand 1072 states and 1538 transitions. cyclomatic complexity: 470 Second operand has 3 states, 3 states have (on average 9.333333333333334) internal successors, (28), 3 states have internal predecessors, (28), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-12 02:21:18,765 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-12 02:21:18,766 INFO L93 Difference]: Finished difference Result 1742 states and 2482 transitions. [2023-11-12 02:21:18,766 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1742 states and 2482 transitions. [2023-11-12 02:21:18,784 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 1708 [2023-11-12 02:21:18,801 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1742 states to 1742 states and 2482 transitions. [2023-11-12 02:21:18,801 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1742 [2023-11-12 02:21:18,803 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1742 [2023-11-12 02:21:18,804 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1742 states and 2482 transitions. [2023-11-12 02:21:18,807 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-12 02:21:18,807 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1742 states and 2482 transitions. [2023-11-12 02:21:18,809 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1742 states and 2482 transitions. [2023-11-12 02:21:18,837 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1742 to 1742. [2023-11-12 02:21:18,841 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1742 states, 1742 states have (on average 1.4247990815154994) internal successors, (2482), 1741 states have internal predecessors, (2482), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-12 02:21:18,850 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1742 states to 1742 states and 2482 transitions. [2023-11-12 02:21:18,851 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1742 states and 2482 transitions. [2023-11-12 02:21:18,852 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-12 02:21:18,857 INFO L428 stractBuchiCegarLoop]: Abstraction has 1742 states and 2482 transitions. [2023-11-12 02:21:18,858 INFO L335 stractBuchiCegarLoop]: ======== Iteration 5 ============ [2023-11-12 02:21:18,858 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1742 states and 2482 transitions. [2023-11-12 02:21:18,873 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 1708 [2023-11-12 02:21:18,873 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-12 02:21:18,873 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-12 02:21:18,878 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-12 02:21:18,878 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-12 02:21:18,878 INFO L748 eck$LassoCheckResult]: Stem: 5373#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(17, 2);call #Ultimate.allocInit(12, 3);~fast_clk_edge~0 := 0;~slow_clk_edge~0 := 0;~q_buf_0~0 := 0;~q_free~0 := 0;~q_read_ev~0 := 0;~q_write_ev~0 := 0;~q_req_up~0 := 0;~q_ev~0 := 0;~p_num_write~0 := 0;~p_last_write~0 := 0;~p_dw_st~0 := 0;~p_dw_pc~0 := 0;~p_dw_i~0 := 0;~c_num_read~0 := 0;~c_last_read~0 := 0;~c_dr_st~0 := 0;~c_dr_pc~0 := 0;~c_dr_i~0 := 0;~a_t~0 := 0;~t~0 := 0; 5374#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~3#1;havoc main_~__retres1~3#1;assume { :begin_inline_init_model } true;~fast_clk_edge~0 := 2;~slow_clk_edge~0 := 2;~q_free~0 := 1;~q_write_ev~0 := 2;~q_read_ev~0 := ~q_write_ev~0;~p_num_write~0 := 0;~p_dw_pc~0 := 0;~p_dw_i~0 := 1;~c_num_read~0 := 0;~c_dr_pc~0 := 0;~c_dr_i~0 := 1; 5396#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret13#1, start_simulation_#t~ret14#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~4#1, start_simulation_~tmp___0~3#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~4#1;havoc start_simulation_~tmp___0~3#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 5377#L258 assume !(1 == ~q_req_up~0); 5378#L258-2 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 5431#L273 assume 1 == ~p_dw_i~0;~p_dw_st~0 := 0; 5432#L273-2 assume 1 == ~c_dr_i~0;~c_dr_st~0 := 0; 5475#L278-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 5410#L311 assume !(0 == ~q_read_ev~0); 5411#L311-2 assume !(0 == ~q_write_ev~0); 5451#L316-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;assume { :begin_inline_is_do_write_p_triggered } true;havoc is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;havoc is_do_write_p_triggered_~__retres1~0#1; 5387#L66 assume !(1 == ~p_dw_pc~0); 5388#L66-2 assume !(2 == ~p_dw_pc~0); 5401#L76-1 is_do_write_p_triggered_~__retres1~0#1 := 0; 5425#L87 is_do_write_p_triggered_#res#1 := is_do_write_p_triggered_~__retres1~0#1; 5426#is_do_write_p_triggered_returnLabel#1 activate_threads_#t~ret7#1 := is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;assume { :end_inline_is_do_write_p_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1; 5419#L387 assume !(0 != activate_threads_~tmp~1#1); 5420#L387-2 assume { :begin_inline_is_do_read_c_triggered } true;havoc is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;havoc is_do_read_c_triggered_~__retres1~1#1; 5463#L95 assume !(1 == ~c_dr_pc~0); 5464#L95-2 assume !(2 == ~c_dr_pc~0); 5433#L105-1 is_do_read_c_triggered_~__retres1~1#1 := 0; 5369#L116 is_do_read_c_triggered_#res#1 := is_do_read_c_triggered_~__retres1~1#1; 5370#is_do_read_c_triggered_returnLabel#1 activate_threads_#t~ret8#1 := is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;assume { :end_inline_is_do_read_c_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 5379#L395 assume !(0 != activate_threads_~tmp___0~1#1); 5347#L395-2 havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 5348#L329 assume !(1 == ~q_read_ev~0); 5382#L329-2 assume !(1 == ~q_write_ev~0); 5392#L334-1 assume { :end_inline_reset_delta_events } true; 5393#L491-2 [2023-11-12 02:21:18,883 INFO L750 eck$LassoCheckResult]: Loop: 5393#L491-2 assume !false; 5633#L492 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret9#1, eval_#t~nondet10#1, eval_#t~nondet11#1, eval_~tmp~2#1, eval_~tmp___0~2#1, eval_~tmp___1~0#1;havoc eval_~tmp~2#1;havoc eval_~tmp___0~2#1;havoc eval_~tmp___1~0#1; 5428#L435 assume !false; 5618#L411 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 5613#L291 assume 0 == ~p_dw_st~0;exists_runnable_thread_~__retres1~2#1 := 1; 5609#L303 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 5606#exists_runnable_thread_returnLabel#1 eval_#t~ret9#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp___1~0#1 := eval_#t~ret9#1;havoc eval_#t~ret9#1; 5601#L415 assume !(0 != eval_~tmp___1~0#1); 5602#eval_returnLabel#1 havoc eval_#t~ret9#1, eval_#t~nondet10#1, eval_#t~nondet11#1, eval_~tmp~2#1, eval_~tmp___0~2#1, eval_~tmp___1~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 5765#L258-3 assume !(1 == ~q_req_up~0); 5761#L258-5 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 5757#L311-3 assume !(0 == ~q_read_ev~0); 5754#L311-5 assume 0 == ~q_write_ev~0;~q_write_ev~0 := 1; 5749#L316-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;assume { :begin_inline_is_do_write_p_triggered } true;havoc is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;havoc is_do_write_p_triggered_~__retres1~0#1; 5744#L66-3 assume !(1 == ~p_dw_pc~0); 5743#L66-5 assume !(2 == ~p_dw_pc~0); 5742#L76-3 is_do_write_p_triggered_~__retres1~0#1 := 0; 5741#L87-1 is_do_write_p_triggered_#res#1 := is_do_write_p_triggered_~__retres1~0#1; 5739#is_do_write_p_triggered_returnLabel#2 activate_threads_#t~ret7#1 := is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;assume { :end_inline_is_do_write_p_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1; 5737#L387-3 assume 0 != activate_threads_~tmp~1#1;~p_dw_st~0 := 0; 5735#L387-5 assume { :begin_inline_is_do_read_c_triggered } true;havoc is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;havoc is_do_read_c_triggered_~__retres1~1#1; 5733#L95-3 assume !(1 == ~c_dr_pc~0); 5731#L95-5 assume !(2 == ~c_dr_pc~0); 5729#L105-3 is_do_read_c_triggered_~__retres1~1#1 := 0; 5727#L116-1 is_do_read_c_triggered_#res#1 := is_do_read_c_triggered_~__retres1~1#1; 5725#is_do_read_c_triggered_returnLabel#2 activate_threads_#t~ret8#1 := is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;assume { :end_inline_is_do_read_c_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 5723#L395-3 assume 0 != activate_threads_~tmp___0~1#1;~c_dr_st~0 := 0; 5721#L395-5 havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 5719#L329-3 assume !(1 == ~q_read_ev~0); 5717#L329-5 assume 1 == ~q_write_ev~0;~q_write_ev~0 := 2; 5715#L334-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 5713#L291-1 assume 0 == ~p_dw_st~0;exists_runnable_thread_~__retres1~2#1 := 1; 5690#L303-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 5684#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret13#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~4#1 := start_simulation_#t~ret13#1;havoc start_simulation_#t~ret13#1; 5677#L510 assume !(0 == start_simulation_~tmp~4#1); 5670#L510-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret12#1, stop_simulation_~tmp~3#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~3#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 5664#L291-2 assume 0 == ~p_dw_st~0;exists_runnable_thread_~__retres1~2#1 := 1; 5658#L303-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 5654#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret12#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~3#1 := stop_simulation_#t~ret12#1;havoc stop_simulation_#t~ret12#1; 5645#L465 assume 0 != stop_simulation_~tmp~3#1;stop_simulation_~__retres2~0#1 := 0; 5642#L472 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 5640#stop_simulation_returnLabel#1 start_simulation_#t~ret14#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret12#1, stop_simulation_~tmp~3#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~3#1 := start_simulation_#t~ret14#1;havoc start_simulation_#t~ret14#1; 5638#L523 assume !(0 != start_simulation_~tmp___0~3#1); 5393#L491-2 [2023-11-12 02:21:18,883 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-12 02:21:18,884 INFO L85 PathProgramCache]: Analyzing trace with hash 156118895, now seen corresponding path program 1 times [2023-11-12 02:21:18,884 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-12 02:21:18,884 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1284251519] [2023-11-12 02:21:18,884 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-12 02:21:18,884 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-12 02:21:18,894 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-12 02:21:18,894 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-12 02:21:18,908 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-12 02:21:18,943 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-12 02:21:18,943 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-12 02:21:18,943 INFO L85 PathProgramCache]: Analyzing trace with hash 147817770, now seen corresponding path program 1 times [2023-11-12 02:21:18,944 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-12 02:21:18,944 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1070368002] [2023-11-12 02:21:18,945 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-12 02:21:18,945 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-12 02:21:18,963 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-12 02:21:19,014 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-12 02:21:19,015 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-12 02:21:19,015 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1070368002] [2023-11-12 02:21:19,015 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1070368002] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-12 02:21:19,015 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-12 02:21:19,015 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2023-11-12 02:21:19,016 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1158121992] [2023-11-12 02:21:19,016 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-12 02:21:19,016 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-12 02:21:19,016 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-12 02:21:19,017 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2023-11-12 02:21:19,017 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2023-11-12 02:21:19,017 INFO L87 Difference]: Start difference. First operand 1742 states and 2482 transitions. cyclomatic complexity: 744 Second operand has 5 states, 5 states have (on average 8.6) internal successors, (43), 5 states have internal predecessors, (43), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-12 02:21:19,154 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-12 02:21:19,155 INFO L93 Difference]: Finished difference Result 2947 states and 4108 transitions. [2023-11-12 02:21:19,155 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2947 states and 4108 transitions. [2023-11-12 02:21:19,218 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 2907 [2023-11-12 02:21:19,247 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2947 states to 2947 states and 4108 transitions. [2023-11-12 02:21:19,247 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2947 [2023-11-12 02:21:19,251 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2947 [2023-11-12 02:21:19,251 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2947 states and 4108 transitions. [2023-11-12 02:21:19,257 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-12 02:21:19,257 INFO L218 hiAutomatonCegarLoop]: Abstraction has 2947 states and 4108 transitions. [2023-11-12 02:21:19,260 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2947 states and 4108 transitions. [2023-11-12 02:21:19,297 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2947 to 1805. [2023-11-12 02:21:19,301 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1805 states, 1805 states have (on average 1.4099722991689752) internal successors, (2545), 1804 states have internal predecessors, (2545), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-12 02:21:19,311 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1805 states to 1805 states and 2545 transitions. [2023-11-12 02:21:19,312 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1805 states and 2545 transitions. [2023-11-12 02:21:19,312 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 9 states. [2023-11-12 02:21:19,315 INFO L428 stractBuchiCegarLoop]: Abstraction has 1805 states and 2545 transitions. [2023-11-12 02:21:19,315 INFO L335 stractBuchiCegarLoop]: ======== Iteration 6 ============ [2023-11-12 02:21:19,315 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1805 states and 2545 transitions. [2023-11-12 02:21:19,328 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 1771 [2023-11-12 02:21:19,329 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-12 02:21:19,329 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-12 02:21:19,330 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-12 02:21:19,331 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-12 02:21:19,331 INFO L748 eck$LassoCheckResult]: Stem: 10080#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(17, 2);call #Ultimate.allocInit(12, 3);~fast_clk_edge~0 := 0;~slow_clk_edge~0 := 0;~q_buf_0~0 := 0;~q_free~0 := 0;~q_read_ev~0 := 0;~q_write_ev~0 := 0;~q_req_up~0 := 0;~q_ev~0 := 0;~p_num_write~0 := 0;~p_last_write~0 := 0;~p_dw_st~0 := 0;~p_dw_pc~0 := 0;~p_dw_i~0 := 0;~c_num_read~0 := 0;~c_last_read~0 := 0;~c_dr_st~0 := 0;~c_dr_pc~0 := 0;~c_dr_i~0 := 0;~a_t~0 := 0;~t~0 := 0; 10081#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~3#1;havoc main_~__retres1~3#1;assume { :begin_inline_init_model } true;~fast_clk_edge~0 := 2;~slow_clk_edge~0 := 2;~q_free~0 := 1;~q_write_ev~0 := 2;~q_read_ev~0 := ~q_write_ev~0;~p_num_write~0 := 0;~p_dw_pc~0 := 0;~p_dw_i~0 := 1;~c_num_read~0 := 0;~c_dr_pc~0 := 0;~c_dr_i~0 := 1; 10102#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret13#1, start_simulation_#t~ret14#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~4#1, start_simulation_~tmp___0~3#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~4#1;havoc start_simulation_~tmp___0~3#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 10084#L258 assume !(1 == ~q_req_up~0); 10085#L258-2 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 10139#L273 assume 1 == ~p_dw_i~0;~p_dw_st~0 := 0; 10140#L273-2 assume 1 == ~c_dr_i~0;~c_dr_st~0 := 0; 10183#L278-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 10116#L311 assume !(0 == ~q_read_ev~0); 10117#L311-2 assume !(0 == ~q_write_ev~0); 10160#L316-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;assume { :begin_inline_is_do_write_p_triggered } true;havoc is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;havoc is_do_write_p_triggered_~__retres1~0#1; 10094#L66 assume !(1 == ~p_dw_pc~0); 10095#L66-2 assume !(2 == ~p_dw_pc~0); 10108#L76-1 is_do_write_p_triggered_~__retres1~0#1 := 0; 10132#L87 is_do_write_p_triggered_#res#1 := is_do_write_p_triggered_~__retres1~0#1; 10133#is_do_write_p_triggered_returnLabel#1 activate_threads_#t~ret7#1 := is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;assume { :end_inline_is_do_write_p_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1; 10126#L387 assume !(0 != activate_threads_~tmp~1#1); 10127#L387-2 assume { :begin_inline_is_do_read_c_triggered } true;havoc is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;havoc is_do_read_c_triggered_~__retres1~1#1; 10172#L95 assume !(1 == ~c_dr_pc~0); 10173#L95-2 assume !(2 == ~c_dr_pc~0); 10141#L105-1 is_do_read_c_triggered_~__retres1~1#1 := 0; 10076#L116 is_do_read_c_triggered_#res#1 := is_do_read_c_triggered_~__retres1~1#1; 10077#is_do_read_c_triggered_returnLabel#1 activate_threads_#t~ret8#1 := is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;assume { :end_inline_is_do_read_c_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 10086#L395 assume !(0 != activate_threads_~tmp___0~1#1); 10054#L395-2 havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 10055#L329 assume !(1 == ~q_read_ev~0); 10089#L329-2 assume !(1 == ~q_write_ev~0); 10098#L334-1 assume { :end_inline_reset_delta_events } true; 10099#L491-2 [2023-11-12 02:21:19,333 INFO L750 eck$LassoCheckResult]: Loop: 10099#L491-2 assume !false; 10365#L492 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret9#1, eval_#t~nondet10#1, eval_#t~nondet11#1, eval_~tmp~2#1, eval_~tmp___0~2#1, eval_~tmp___1~0#1;havoc eval_~tmp~2#1;havoc eval_~tmp___0~2#1;havoc eval_~tmp___1~0#1; 10297#L435 assume !false; 10294#L411 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 10292#L291 assume !(0 == ~p_dw_st~0); 10288#L295 assume !(0 == ~c_dr_st~0);exists_runnable_thread_~__retres1~2#1 := 0; 10286#L303 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 10275#exists_runnable_thread_returnLabel#1 eval_#t~ret9#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp___1~0#1 := eval_#t~ret9#1;havoc eval_#t~ret9#1; 10273#L415 assume !(0 != eval_~tmp___1~0#1); 10272#eval_returnLabel#1 havoc eval_#t~ret9#1, eval_#t~nondet10#1, eval_#t~nondet11#1, eval_~tmp~2#1, eval_~tmp___0~2#1, eval_~tmp___1~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 10271#L258-3 assume !(1 == ~q_req_up~0); 10270#L258-5 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 10269#L311-3 assume !(0 == ~q_read_ev~0); 10268#L311-5 assume 0 == ~q_write_ev~0;~q_write_ev~0 := 1; 10267#L316-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;assume { :begin_inline_is_do_write_p_triggered } true;havoc is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;havoc is_do_write_p_triggered_~__retres1~0#1; 10266#L66-3 assume !(1 == ~p_dw_pc~0); 10264#L66-5 assume !(2 == ~p_dw_pc~0); 10265#L76-3 is_do_write_p_triggered_~__retres1~0#1 := 0; 10240#L87-1 is_do_write_p_triggered_#res#1 := is_do_write_p_triggered_~__retres1~0#1; 10241#is_do_write_p_triggered_returnLabel#2 activate_threads_#t~ret7#1 := is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;assume { :end_inline_is_do_write_p_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1; 10236#L387-3 assume 0 != activate_threads_~tmp~1#1;~p_dw_st~0 := 0; 10237#L387-5 assume { :begin_inline_is_do_read_c_triggered } true;havoc is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;havoc is_do_read_c_triggered_~__retres1~1#1; 10232#L95-3 assume !(1 == ~c_dr_pc~0); 10233#L95-5 assume !(2 == ~c_dr_pc~0); 10397#L105-3 is_do_read_c_triggered_~__retres1~1#1 := 0; 10396#L116-1 is_do_read_c_triggered_#res#1 := is_do_read_c_triggered_~__retres1~1#1; 10395#is_do_read_c_triggered_returnLabel#2 activate_threads_#t~ret8#1 := is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;assume { :end_inline_is_do_read_c_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 10394#L395-3 assume 0 != activate_threads_~tmp___0~1#1;~c_dr_st~0 := 0; 10393#L395-5 havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 10392#L329-3 assume !(1 == ~q_read_ev~0); 10391#L329-5 assume 1 == ~q_write_ev~0;~q_write_ev~0 := 2; 10390#L334-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 10389#L291-1 assume 0 == ~p_dw_st~0;exists_runnable_thread_~__retres1~2#1 := 1; 10386#L303-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 10384#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret13#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~4#1 := start_simulation_#t~ret13#1;havoc start_simulation_#t~ret13#1; 10381#L510 assume !(0 == start_simulation_~tmp~4#1); 10379#L510-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret12#1, stop_simulation_~tmp~3#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~3#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 10378#L291-2 assume 0 == ~p_dw_st~0;exists_runnable_thread_~__retres1~2#1 := 1; 10376#L303-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 10375#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret12#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~3#1 := stop_simulation_#t~ret12#1;havoc stop_simulation_#t~ret12#1; 10374#L465 assume 0 != stop_simulation_~tmp~3#1;stop_simulation_~__retres2~0#1 := 0; 10373#L472 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 10372#stop_simulation_returnLabel#1 start_simulation_#t~ret14#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret12#1, stop_simulation_~tmp~3#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~3#1 := start_simulation_#t~ret14#1;havoc start_simulation_#t~ret14#1; 10369#L523 assume !(0 != start_simulation_~tmp___0~3#1); 10099#L491-2 [2023-11-12 02:21:19,333 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-12 02:21:19,334 INFO L85 PathProgramCache]: Analyzing trace with hash 156118895, now seen corresponding path program 2 times [2023-11-12 02:21:19,334 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-12 02:21:19,335 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [795809880] [2023-11-12 02:21:19,335 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-12 02:21:19,335 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-12 02:21:19,349 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-12 02:21:19,349 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-12 02:21:19,356 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-12 02:21:19,366 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-12 02:21:19,367 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-12 02:21:19,367 INFO L85 PathProgramCache]: Analyzing trace with hash 657647766, now seen corresponding path program 1 times [2023-11-12 02:21:19,367 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-12 02:21:19,368 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1169749960] [2023-11-12 02:21:19,368 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-12 02:21:19,369 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-12 02:21:19,388 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-12 02:21:19,492 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-12 02:21:19,493 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-12 02:21:19,493 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1169749960] [2023-11-12 02:21:19,493 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1169749960] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-12 02:21:19,493 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-12 02:21:19,494 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2023-11-12 02:21:19,494 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1810629062] [2023-11-12 02:21:19,494 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-12 02:21:19,495 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-12 02:21:19,495 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-12 02:21:19,496 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2023-11-12 02:21:19,501 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2023-11-12 02:21:19,501 INFO L87 Difference]: Start difference. First operand 1805 states and 2545 transitions. cyclomatic complexity: 744 Second operand has 5 states, 5 states have (on average 8.8) internal successors, (44), 5 states have internal predecessors, (44), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-12 02:21:19,597 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-12 02:21:19,597 INFO L93 Difference]: Finished difference Result 3283 states and 4585 transitions. [2023-11-12 02:21:19,598 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 3283 states and 4585 transitions. [2023-11-12 02:21:19,634 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 3247 [2023-11-12 02:21:19,667 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 3283 states to 3283 states and 4585 transitions. [2023-11-12 02:21:19,667 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 3283 [2023-11-12 02:21:19,671 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 3283 [2023-11-12 02:21:19,671 INFO L73 IsDeterministic]: Start isDeterministic. Operand 3283 states and 4585 transitions. [2023-11-12 02:21:19,677 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-12 02:21:19,677 INFO L218 hiAutomatonCegarLoop]: Abstraction has 3283 states and 4585 transitions. [2023-11-12 02:21:19,681 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3283 states and 4585 transitions. [2023-11-12 02:21:19,723 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3283 to 1883. [2023-11-12 02:21:19,727 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1883 states, 1883 states have (on average 1.3839617631439194) internal successors, (2606), 1882 states have internal predecessors, (2606), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-12 02:21:19,737 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1883 states to 1883 states and 2606 transitions. [2023-11-12 02:21:19,737 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1883 states and 2606 transitions. [2023-11-12 02:21:19,738 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2023-11-12 02:21:19,740 INFO L428 stractBuchiCegarLoop]: Abstraction has 1883 states and 2606 transitions. [2023-11-12 02:21:19,740 INFO L335 stractBuchiCegarLoop]: ======== Iteration 7 ============ [2023-11-12 02:21:19,741 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1883 states and 2606 transitions. [2023-11-12 02:21:19,756 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 1849 [2023-11-12 02:21:19,756 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-12 02:21:19,756 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-12 02:21:19,757 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-12 02:21:19,758 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-12 02:21:19,760 INFO L748 eck$LassoCheckResult]: Stem: 15179#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(17, 2);call #Ultimate.allocInit(12, 3);~fast_clk_edge~0 := 0;~slow_clk_edge~0 := 0;~q_buf_0~0 := 0;~q_free~0 := 0;~q_read_ev~0 := 0;~q_write_ev~0 := 0;~q_req_up~0 := 0;~q_ev~0 := 0;~p_num_write~0 := 0;~p_last_write~0 := 0;~p_dw_st~0 := 0;~p_dw_pc~0 := 0;~p_dw_i~0 := 0;~c_num_read~0 := 0;~c_last_read~0 := 0;~c_dr_st~0 := 0;~c_dr_pc~0 := 0;~c_dr_i~0 := 0;~a_t~0 := 0;~t~0 := 0; 15180#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~3#1;havoc main_~__retres1~3#1;assume { :begin_inline_init_model } true;~fast_clk_edge~0 := 2;~slow_clk_edge~0 := 2;~q_free~0 := 1;~q_write_ev~0 := 2;~q_read_ev~0 := ~q_write_ev~0;~p_num_write~0 := 0;~p_dw_pc~0 := 0;~p_dw_i~0 := 1;~c_num_read~0 := 0;~c_dr_pc~0 := 0;~c_dr_i~0 := 1; 15204#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret13#1, start_simulation_#t~ret14#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~4#1, start_simulation_~tmp___0~3#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~4#1;havoc start_simulation_~tmp___0~3#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 15185#L258 assume !(1 == ~q_req_up~0); 15186#L258-2 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 15240#L273 assume 1 == ~p_dw_i~0;~p_dw_st~0 := 0; 15241#L273-2 assume 1 == ~c_dr_i~0;~c_dr_st~0 := 0; 15288#L278-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 15218#L311 assume !(0 == ~q_read_ev~0); 15219#L311-2 assume !(0 == ~q_write_ev~0); 15260#L316-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;assume { :begin_inline_is_do_write_p_triggered } true;havoc is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;havoc is_do_write_p_triggered_~__retres1~0#1; 15193#L66 assume !(1 == ~p_dw_pc~0); 15194#L66-2 assume !(2 == ~p_dw_pc~0); 15209#L76-1 is_do_write_p_triggered_~__retres1~0#1 := 0; 15232#L87 is_do_write_p_triggered_#res#1 := is_do_write_p_triggered_~__retres1~0#1; 15233#is_do_write_p_triggered_returnLabel#1 activate_threads_#t~ret7#1 := is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;assume { :end_inline_is_do_write_p_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1; 15228#L387 assume !(0 != activate_threads_~tmp~1#1); 15229#L387-2 assume { :begin_inline_is_do_read_c_triggered } true;havoc is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;havoc is_do_read_c_triggered_~__retres1~1#1; 15271#L95 assume !(1 == ~c_dr_pc~0); 15272#L95-2 assume !(2 == ~c_dr_pc~0); 15242#L105-1 is_do_read_c_triggered_~__retres1~1#1 := 0; 15177#L116 is_do_read_c_triggered_#res#1 := is_do_read_c_triggered_~__retres1~1#1; 15178#is_do_read_c_triggered_returnLabel#1 activate_threads_#t~ret8#1 := is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;assume { :end_inline_is_do_read_c_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 15187#L395 assume !(0 != activate_threads_~tmp___0~1#1); 15153#L395-2 havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 15154#L329 assume !(1 == ~q_read_ev~0); 15188#L329-2 assume !(1 == ~q_write_ev~0); 15197#L334-1 assume { :end_inline_reset_delta_events } true; 15198#L491-2 [2023-11-12 02:21:19,760 INFO L750 eck$LassoCheckResult]: Loop: 15198#L491-2 assume !false; 15502#L492 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret9#1, eval_#t~nondet10#1, eval_#t~nondet11#1, eval_~tmp~2#1, eval_~tmp___0~2#1, eval_~tmp___1~0#1;havoc eval_~tmp~2#1;havoc eval_~tmp___0~2#1;havoc eval_~tmp___1~0#1; 15405#L435 assume !false; 15499#L411 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 15496#L291 assume !(0 == ~p_dw_st~0); 15497#L295 assume !(0 == ~c_dr_st~0);exists_runnable_thread_~__retres1~2#1 := 0; 15491#L303 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 15490#exists_runnable_thread_returnLabel#1 eval_#t~ret9#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp___1~0#1 := eval_#t~ret9#1;havoc eval_#t~ret9#1; 15488#L415 assume !(0 != eval_~tmp___1~0#1); 15487#eval_returnLabel#1 havoc eval_#t~ret9#1, eval_#t~nondet10#1, eval_#t~nondet11#1, eval_~tmp~2#1, eval_~tmp___0~2#1, eval_~tmp___1~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 15485#L258-3 assume !(1 == ~q_req_up~0); 15483#L258-5 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 15481#L311-3 assume !(0 == ~q_read_ev~0); 15479#L311-5 assume 0 == ~q_write_ev~0;~q_write_ev~0 := 1; 15477#L316-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;assume { :begin_inline_is_do_write_p_triggered } true;havoc is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;havoc is_do_write_p_triggered_~__retres1~0#1; 15296#L66-3 assume !(1 == ~p_dw_pc~0); 15297#L66-5 assume !(2 == ~p_dw_pc~0); 15467#L76-3 is_do_write_p_triggered_~__retres1~0#1 := 0; 15465#L87-1 is_do_write_p_triggered_#res#1 := is_do_write_p_triggered_~__retres1~0#1; 15463#is_do_write_p_triggered_returnLabel#2 activate_threads_#t~ret7#1 := is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;assume { :end_inline_is_do_write_p_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1; 15461#L387-3 assume !(0 != activate_threads_~tmp~1#1); 15459#L387-5 assume { :begin_inline_is_do_read_c_triggered } true;havoc is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;havoc is_do_read_c_triggered_~__retres1~1#1; 15457#L95-3 assume !(1 == ~c_dr_pc~0); 15456#L95-5 assume !(2 == ~c_dr_pc~0); 15357#L105-3 is_do_read_c_triggered_~__retres1~1#1 := 0; 15353#L116-1 is_do_read_c_triggered_#res#1 := is_do_read_c_triggered_~__retres1~1#1; 15351#is_do_read_c_triggered_returnLabel#2 activate_threads_#t~ret8#1 := is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;assume { :end_inline_is_do_read_c_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 15352#L395-3 assume 0 != activate_threads_~tmp___0~1#1;~c_dr_st~0 := 0; 15552#L395-5 havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 15525#L329-3 assume !(1 == ~q_read_ev~0); 15522#L329-5 assume 1 == ~q_write_ev~0;~q_write_ev~0 := 2; 15520#L334-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 15519#L291-1 assume 0 == ~p_dw_st~0;exists_runnable_thread_~__retres1~2#1 := 1; 15517#L303-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 15516#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret13#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~4#1 := start_simulation_#t~ret13#1;havoc start_simulation_#t~ret13#1; 15338#L510 assume !(0 == start_simulation_~tmp~4#1); 15339#L510-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret12#1, stop_simulation_~tmp~3#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~3#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 15524#L291-2 assume 0 == ~p_dw_st~0;exists_runnable_thread_~__retres1~2#1 := 1; 15521#L303-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 15514#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret12#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~3#1 := stop_simulation_#t~ret12#1;havoc stop_simulation_#t~ret12#1; 15512#L465 assume 0 != stop_simulation_~tmp~3#1;stop_simulation_~__retres2~0#1 := 0; 15510#L472 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 15507#stop_simulation_returnLabel#1 start_simulation_#t~ret14#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret12#1, stop_simulation_~tmp~3#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~3#1 := start_simulation_#t~ret14#1;havoc start_simulation_#t~ret14#1; 15505#L523 assume !(0 != start_simulation_~tmp___0~3#1); 15198#L491-2 [2023-11-12 02:21:19,761 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-12 02:21:19,761 INFO L85 PathProgramCache]: Analyzing trace with hash 156118895, now seen corresponding path program 3 times [2023-11-12 02:21:19,762 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-12 02:21:19,762 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [232416132] [2023-11-12 02:21:19,763 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-12 02:21:19,766 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-12 02:21:19,776 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-12 02:21:19,777 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-12 02:21:19,782 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-12 02:21:19,800 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-12 02:21:19,800 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-12 02:21:19,801 INFO L85 PathProgramCache]: Analyzing trace with hash 523634260, now seen corresponding path program 1 times [2023-11-12 02:21:19,801 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-12 02:21:19,801 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1232011393] [2023-11-12 02:21:19,802 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-12 02:21:19,802 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-12 02:21:19,812 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-12 02:21:19,864 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-12 02:21:19,868 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-12 02:21:19,868 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1232011393] [2023-11-12 02:21:19,869 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1232011393] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-12 02:21:19,869 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-12 02:21:19,869 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-12 02:21:19,869 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1748388159] [2023-11-12 02:21:19,869 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-12 02:21:19,870 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-12 02:21:19,870 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-12 02:21:19,870 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-12 02:21:19,871 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-12 02:21:19,871 INFO L87 Difference]: Start difference. First operand 1883 states and 2606 transitions. cyclomatic complexity: 727 Second operand has 3 states, 3 states have (on average 14.666666666666666) internal successors, (44), 3 states have internal predecessors, (44), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-12 02:21:19,921 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-12 02:21:19,921 INFO L93 Difference]: Finished difference Result 2972 states and 4013 transitions. [2023-11-12 02:21:19,921 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2972 states and 4013 transitions. [2023-11-12 02:21:19,953 INFO L131 ngComponentsAnalysis]: Automaton has 7 accepting balls. 2910 [2023-11-12 02:21:19,981 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2972 states to 2972 states and 4013 transitions. [2023-11-12 02:21:19,982 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2972 [2023-11-12 02:21:19,986 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2972 [2023-11-12 02:21:19,986 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2972 states and 4013 transitions. [2023-11-12 02:21:19,991 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-12 02:21:19,992 INFO L218 hiAutomatonCegarLoop]: Abstraction has 2972 states and 4013 transitions. [2023-11-12 02:21:19,995 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2972 states and 4013 transitions. [2023-11-12 02:21:20,045 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2972 to 2972. [2023-11-12 02:21:20,051 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2972 states, 2972 states have (on average 1.3502691790040378) internal successors, (4013), 2971 states have internal predecessors, (4013), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-12 02:21:20,065 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2972 states to 2972 states and 4013 transitions. [2023-11-12 02:21:20,065 INFO L240 hiAutomatonCegarLoop]: Abstraction has 2972 states and 4013 transitions. [2023-11-12 02:21:20,066 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-12 02:21:20,067 INFO L428 stractBuchiCegarLoop]: Abstraction has 2972 states and 4013 transitions. [2023-11-12 02:21:20,067 INFO L335 stractBuchiCegarLoop]: ======== Iteration 8 ============ [2023-11-12 02:21:20,067 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2972 states and 4013 transitions. [2023-11-12 02:21:20,084 INFO L131 ngComponentsAnalysis]: Automaton has 7 accepting balls. 2910 [2023-11-12 02:21:20,084 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-12 02:21:20,084 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-12 02:21:20,085 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-12 02:21:20,085 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-12 02:21:20,085 INFO L748 eck$LassoCheckResult]: Stem: 20037#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(17, 2);call #Ultimate.allocInit(12, 3);~fast_clk_edge~0 := 0;~slow_clk_edge~0 := 0;~q_buf_0~0 := 0;~q_free~0 := 0;~q_read_ev~0 := 0;~q_write_ev~0 := 0;~q_req_up~0 := 0;~q_ev~0 := 0;~p_num_write~0 := 0;~p_last_write~0 := 0;~p_dw_st~0 := 0;~p_dw_pc~0 := 0;~p_dw_i~0 := 0;~c_num_read~0 := 0;~c_last_read~0 := 0;~c_dr_st~0 := 0;~c_dr_pc~0 := 0;~c_dr_i~0 := 0;~a_t~0 := 0;~t~0 := 0; 20038#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~3#1;havoc main_~__retres1~3#1;assume { :begin_inline_init_model } true;~fast_clk_edge~0 := 2;~slow_clk_edge~0 := 2;~q_free~0 := 1;~q_write_ev~0 := 2;~q_read_ev~0 := ~q_write_ev~0;~p_num_write~0 := 0;~p_dw_pc~0 := 0;~p_dw_i~0 := 1;~c_num_read~0 := 0;~c_dr_pc~0 := 0;~c_dr_i~0 := 1; 20062#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret13#1, start_simulation_#t~ret14#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~4#1, start_simulation_~tmp___0~3#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~4#1;havoc start_simulation_~tmp___0~3#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 20043#L258 assume !(1 == ~q_req_up~0); 20044#L258-2 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 20095#L273 assume !(1 == ~p_dw_i~0);~p_dw_st~0 := 2; 20096#L273-2 assume 1 == ~c_dr_i~0;~c_dr_st~0 := 0; 20229#L278-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 20228#L311 assume !(0 == ~q_read_ev~0); 20227#L311-2 assume !(0 == ~q_write_ev~0); 20226#L316-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;assume { :begin_inline_is_do_write_p_triggered } true;havoc is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;havoc is_do_write_p_triggered_~__retres1~0#1; 20225#L66 assume !(1 == ~p_dw_pc~0); 20224#L66-2 assume !(2 == ~p_dw_pc~0); 20223#L76-1 is_do_write_p_triggered_~__retres1~0#1 := 0; 20222#L87 is_do_write_p_triggered_#res#1 := is_do_write_p_triggered_~__retres1~0#1; 20221#is_do_write_p_triggered_returnLabel#1 activate_threads_#t~ret7#1 := is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;assume { :end_inline_is_do_write_p_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1; 20220#L387 assume !(0 != activate_threads_~tmp~1#1); 20219#L387-2 assume { :begin_inline_is_do_read_c_triggered } true;havoc is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;havoc is_do_read_c_triggered_~__retres1~1#1; 20218#L95 assume !(1 == ~c_dr_pc~0); 20217#L95-2 assume !(2 == ~c_dr_pc~0); 20216#L105-1 is_do_read_c_triggered_~__retres1~1#1 := 0; 20215#L116 is_do_read_c_triggered_#res#1 := is_do_read_c_triggered_~__retres1~1#1; 20214#is_do_read_c_triggered_returnLabel#1 activate_threads_#t~ret8#1 := is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;assume { :end_inline_is_do_read_c_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 20213#L395 assume !(0 != activate_threads_~tmp___0~1#1); 20212#L395-2 havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 20046#L329 assume !(1 == ~q_read_ev~0); 20047#L329-2 assume !(1 == ~q_write_ev~0); 20056#L334-1 assume { :end_inline_reset_delta_events } true; 20057#L491-2 [2023-11-12 02:21:20,086 INFO L750 eck$LassoCheckResult]: Loop: 20057#L491-2 assume !false; 20282#L492 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret9#1, eval_#t~nondet10#1, eval_#t~nondet11#1, eval_~tmp~2#1, eval_~tmp___0~2#1, eval_~tmp___1~0#1;havoc eval_~tmp~2#1;havoc eval_~tmp___0~2#1;havoc eval_~tmp___1~0#1; 20271#L435 assume !false; 20281#L411 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 20280#L291 assume !(0 == ~p_dw_st~0); 20194#L295 assume !(0 == ~c_dr_st~0);exists_runnable_thread_~__retres1~2#1 := 0; 20279#L303 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 20277#exists_runnable_thread_returnLabel#1 eval_#t~ret9#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp___1~0#1 := eval_#t~ret9#1;havoc eval_#t~ret9#1; 20274#L415 assume !(0 != eval_~tmp___1~0#1); 20275#eval_returnLabel#1 havoc eval_#t~ret9#1, eval_#t~nondet10#1, eval_#t~nondet11#1, eval_~tmp~2#1, eval_~tmp___0~2#1, eval_~tmp___1~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 20337#L258-3 assume !(1 == ~q_req_up~0); 20336#L258-5 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 20335#L311-3 assume !(0 == ~q_read_ev~0); 20334#L311-5 assume 0 == ~q_write_ev~0;~q_write_ev~0 := 1; 20333#L316-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;assume { :begin_inline_is_do_write_p_triggered } true;havoc is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;havoc is_do_write_p_triggered_~__retres1~0#1; 20332#L66-3 assume !(1 == ~p_dw_pc~0); 20331#L66-5 assume !(2 == ~p_dw_pc~0); 20330#L76-3 is_do_write_p_triggered_~__retres1~0#1 := 0; 20329#L87-1 is_do_write_p_triggered_#res#1 := is_do_write_p_triggered_~__retres1~0#1; 20328#is_do_write_p_triggered_returnLabel#2 activate_threads_#t~ret7#1 := is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;assume { :end_inline_is_do_write_p_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1; 20326#L387-3 assume !(0 != activate_threads_~tmp~1#1); 20324#L387-5 assume { :begin_inline_is_do_read_c_triggered } true;havoc is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;havoc is_do_read_c_triggered_~__retres1~1#1; 20322#L95-3 assume !(1 == ~c_dr_pc~0); 20320#L95-5 assume !(2 == ~c_dr_pc~0); 20318#L105-3 is_do_read_c_triggered_~__retres1~1#1 := 0; 20316#L116-1 is_do_read_c_triggered_#res#1 := is_do_read_c_triggered_~__retres1~1#1; 20314#is_do_read_c_triggered_returnLabel#2 activate_threads_#t~ret8#1 := is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;assume { :end_inline_is_do_read_c_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 20312#L395-3 assume 0 != activate_threads_~tmp___0~1#1;~c_dr_st~0 := 0; 20310#L395-5 havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 20308#L329-3 assume !(1 == ~q_read_ev~0); 20306#L329-5 assume 1 == ~q_write_ev~0;~q_write_ev~0 := 2; 20304#L334-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 20302#L291-1 assume !(0 == ~p_dw_st~0); 20300#L295-1 assume 0 == ~c_dr_st~0;exists_runnable_thread_~__retres1~2#1 := 1; 20298#L303-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 20296#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret13#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~4#1 := start_simulation_#t~ret13#1;havoc start_simulation_#t~ret13#1; 20293#L510 assume !(0 == start_simulation_~tmp~4#1); 20291#L510-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret12#1, stop_simulation_~tmp~3#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~3#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 20290#L291-2 assume !(0 == ~p_dw_st~0); 20289#L295-2 assume 0 == ~c_dr_st~0;exists_runnable_thread_~__retres1~2#1 := 1; 20288#L303-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 20287#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret12#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~3#1 := stop_simulation_#t~ret12#1;havoc stop_simulation_#t~ret12#1; 20286#L465 assume 0 != stop_simulation_~tmp~3#1;stop_simulation_~__retres2~0#1 := 0; 20285#L472 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 20284#stop_simulation_returnLabel#1 start_simulation_#t~ret14#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret12#1, stop_simulation_~tmp~3#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~3#1 := start_simulation_#t~ret14#1;havoc start_simulation_#t~ret14#1; 20283#L523 assume !(0 != start_simulation_~tmp___0~3#1); 20057#L491-2 [2023-11-12 02:21:20,086 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-12 02:21:20,086 INFO L85 PathProgramCache]: Analyzing trace with hash -1649319439, now seen corresponding path program 1 times [2023-11-12 02:21:20,086 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-12 02:21:20,086 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [799481972] [2023-11-12 02:21:20,087 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-12 02:21:20,087 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-12 02:21:20,093 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-12 02:21:20,116 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-12 02:21:20,116 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-12 02:21:20,116 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [799481972] [2023-11-12 02:21:20,119 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [799481972] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-12 02:21:20,119 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-12 02:21:20,120 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-12 02:21:20,120 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2035943218] [2023-11-12 02:21:20,120 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-12 02:21:20,120 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-12 02:21:20,135 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-12 02:21:20,136 INFO L85 PathProgramCache]: Analyzing trace with hash -1954829134, now seen corresponding path program 1 times [2023-11-12 02:21:20,136 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-12 02:21:20,136 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [348580631] [2023-11-12 02:21:20,136 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-12 02:21:20,136 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-12 02:21:20,145 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-12 02:21:20,198 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-12 02:21:20,199 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-12 02:21:20,199 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [348580631] [2023-11-12 02:21:20,199 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [348580631] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-12 02:21:20,199 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-12 02:21:20,199 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2023-11-12 02:21:20,200 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2017171166] [2023-11-12 02:21:20,203 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-12 02:21:20,203 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-12 02:21:20,203 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-12 02:21:20,204 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-12 02:21:20,204 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-12 02:21:20,204 INFO L87 Difference]: Start difference. First operand 2972 states and 4013 transitions. cyclomatic complexity: 1048 Second operand has 3 states, 3 states have (on average 9.333333333333334) internal successors, (28), 3 states have internal predecessors, (28), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-12 02:21:20,228 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-12 02:21:20,228 INFO L93 Difference]: Finished difference Result 2950 states and 3987 transitions. [2023-11-12 02:21:20,229 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2950 states and 3987 transitions. [2023-11-12 02:21:20,251 INFO L131 ngComponentsAnalysis]: Automaton has 7 accepting balls. 2910 [2023-11-12 02:21:20,277 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2950 states to 2950 states and 3987 transitions. [2023-11-12 02:21:20,277 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2950 [2023-11-12 02:21:20,281 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2950 [2023-11-12 02:21:20,281 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2950 states and 3987 transitions. [2023-11-12 02:21:20,286 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-12 02:21:20,286 INFO L218 hiAutomatonCegarLoop]: Abstraction has 2950 states and 3987 transitions. [2023-11-12 02:21:20,289 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2950 states and 3987 transitions. [2023-11-12 02:21:20,343 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2950 to 2950. [2023-11-12 02:21:20,349 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2950 states, 2950 states have (on average 1.3515254237288135) internal successors, (3987), 2949 states have internal predecessors, (3987), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-12 02:21:20,362 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2950 states to 2950 states and 3987 transitions. [2023-11-12 02:21:20,362 INFO L240 hiAutomatonCegarLoop]: Abstraction has 2950 states and 3987 transitions. [2023-11-12 02:21:20,363 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-12 02:21:20,365 INFO L428 stractBuchiCegarLoop]: Abstraction has 2950 states and 3987 transitions. [2023-11-12 02:21:20,366 INFO L335 stractBuchiCegarLoop]: ======== Iteration 9 ============ [2023-11-12 02:21:20,366 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2950 states and 3987 transitions. [2023-11-12 02:21:20,382 INFO L131 ngComponentsAnalysis]: Automaton has 7 accepting balls. 2910 [2023-11-12 02:21:20,382 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-12 02:21:20,382 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-12 02:21:20,384 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-12 02:21:20,384 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-12 02:21:20,385 INFO L748 eck$LassoCheckResult]: Stem: 25969#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(17, 2);call #Ultimate.allocInit(12, 3);~fast_clk_edge~0 := 0;~slow_clk_edge~0 := 0;~q_buf_0~0 := 0;~q_free~0 := 0;~q_read_ev~0 := 0;~q_write_ev~0 := 0;~q_req_up~0 := 0;~q_ev~0 := 0;~p_num_write~0 := 0;~p_last_write~0 := 0;~p_dw_st~0 := 0;~p_dw_pc~0 := 0;~p_dw_i~0 := 0;~c_num_read~0 := 0;~c_last_read~0 := 0;~c_dr_st~0 := 0;~c_dr_pc~0 := 0;~c_dr_i~0 := 0;~a_t~0 := 0;~t~0 := 0; 25970#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~3#1;havoc main_~__retres1~3#1;assume { :begin_inline_init_model } true;~fast_clk_edge~0 := 2;~slow_clk_edge~0 := 2;~q_free~0 := 1;~q_write_ev~0 := 2;~q_read_ev~0 := ~q_write_ev~0;~p_num_write~0 := 0;~p_dw_pc~0 := 0;~p_dw_i~0 := 1;~c_num_read~0 := 0;~c_dr_pc~0 := 0;~c_dr_i~0 := 1; 25991#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret13#1, start_simulation_#t~ret14#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~4#1, start_simulation_~tmp___0~3#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~4#1;havoc start_simulation_~tmp___0~3#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 25973#L258 assume !(1 == ~q_req_up~0); 25974#L258-2 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 26025#L273 assume 1 == ~p_dw_i~0;~p_dw_st~0 := 0; 26026#L273-2 assume 1 == ~c_dr_i~0;~c_dr_st~0 := 0; 26068#L278-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 26005#L311 assume !(0 == ~q_read_ev~0); 26006#L311-2 assume !(0 == ~q_write_ev~0); 26046#L316-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;assume { :begin_inline_is_do_write_p_triggered } true;havoc is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;havoc is_do_write_p_triggered_~__retres1~0#1; 25983#L66 assume !(1 == ~p_dw_pc~0); 25984#L66-2 assume !(2 == ~p_dw_pc~0); 25995#L76-1 is_do_write_p_triggered_~__retres1~0#1 := 0; 26021#L87 is_do_write_p_triggered_#res#1 := is_do_write_p_triggered_~__retres1~0#1; 26022#is_do_write_p_triggered_returnLabel#1 activate_threads_#t~ret7#1 := is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;assume { :end_inline_is_do_write_p_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1; 26015#L387 assume !(0 != activate_threads_~tmp~1#1); 26016#L387-2 assume { :begin_inline_is_do_read_c_triggered } true;havoc is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;havoc is_do_read_c_triggered_~__retres1~1#1; 26056#L95 assume !(1 == ~c_dr_pc~0); 26057#L95-2 assume !(2 == ~c_dr_pc~0); 26027#L105-1 is_do_read_c_triggered_~__retres1~1#1 := 0; 25965#L116 is_do_read_c_triggered_#res#1 := is_do_read_c_triggered_~__retres1~1#1; 25966#is_do_read_c_triggered_returnLabel#1 activate_threads_#t~ret8#1 := is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;assume { :end_inline_is_do_read_c_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 25975#L395 assume !(0 != activate_threads_~tmp___0~1#1); 25945#L395-2 havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 25946#L329 assume !(1 == ~q_read_ev~0); 25978#L329-2 assume !(1 == ~q_write_ev~0); 25987#L334-1 assume { :end_inline_reset_delta_events } true; 25988#L491-2 assume !false; 27287#L492 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret9#1, eval_#t~nondet10#1, eval_#t~nondet11#1, eval_~tmp~2#1, eval_~tmp___0~2#1, eval_~tmp___1~0#1;havoc eval_~tmp~2#1;havoc eval_~tmp___0~2#1;havoc eval_~tmp___1~0#1; 27259#L435 [2023-11-12 02:21:20,385 INFO L750 eck$LassoCheckResult]: Loop: 27259#L435 assume !false; 27285#L411 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 27281#L291 assume 0 == ~p_dw_st~0;exists_runnable_thread_~__retres1~2#1 := 1; 27278#L303 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 27276#exists_runnable_thread_returnLabel#1 eval_#t~ret9#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp___1~0#1 := eval_#t~ret9#1;havoc eval_#t~ret9#1; 27274#L415 assume 0 != eval_~tmp___1~0#1; 27215#L415-1 assume 0 == ~p_dw_st~0;havoc eval_#t~nondet10#1;eval_~tmp~2#1 := eval_#t~nondet10#1;havoc eval_#t~nondet10#1; 26468#L424 assume !(0 != eval_~tmp~2#1); 26469#L420 assume !(0 == ~c_dr_st~0); 27259#L435 [2023-11-12 02:21:20,385 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-12 02:21:20,386 INFO L85 PathProgramCache]: Analyzing trace with hash -293592559, now seen corresponding path program 1 times [2023-11-12 02:21:20,386 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-12 02:21:20,388 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1038726897] [2023-11-12 02:21:20,388 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-12 02:21:20,393 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-12 02:21:20,401 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-12 02:21:20,402 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-12 02:21:20,407 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-12 02:21:20,418 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-12 02:21:20,419 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-12 02:21:20,419 INFO L85 PathProgramCache]: Analyzing trace with hash 1094877041, now seen corresponding path program 1 times [2023-11-12 02:21:20,419 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-12 02:21:20,419 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1236645243] [2023-11-12 02:21:20,419 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-12 02:21:20,419 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-12 02:21:20,423 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-12 02:21:20,423 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-12 02:21:20,425 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-12 02:21:20,427 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-12 02:21:20,427 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-12 02:21:20,427 INFO L85 PathProgramCache]: Analyzing trace with hash -1470124191, now seen corresponding path program 1 times [2023-11-12 02:21:20,427 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-12 02:21:20,428 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [260567958] [2023-11-12 02:21:20,428 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-12 02:21:20,428 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-12 02:21:20,436 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-12 02:21:20,460 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-12 02:21:20,460 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-12 02:21:20,460 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [260567958] [2023-11-12 02:21:20,461 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [260567958] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-12 02:21:20,461 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-12 02:21:20,461 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2023-11-12 02:21:20,461 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1998101911] [2023-11-12 02:21:20,461 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-12 02:21:20,538 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-12 02:21:20,538 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-12 02:21:20,538 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-12 02:21:20,539 INFO L87 Difference]: Start difference. First operand 2950 states and 3987 transitions. cyclomatic complexity: 1044 Second operand has 3 states, 2 states have (on average 19.5) internal successors, (39), 3 states have internal predecessors, (39), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-12 02:21:20,590 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-12 02:21:20,590 INFO L93 Difference]: Finished difference Result 4412 states and 5918 transitions. [2023-11-12 02:21:20,591 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 4412 states and 5918 transitions. [2023-11-12 02:21:20,619 INFO L131 ngComponentsAnalysis]: Automaton has 6 accepting balls. 4373 [2023-11-12 02:21:20,650 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 4412 states to 4412 states and 5918 transitions. [2023-11-12 02:21:20,651 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 4412 [2023-11-12 02:21:20,656 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 4412 [2023-11-12 02:21:20,656 INFO L73 IsDeterministic]: Start isDeterministic. Operand 4412 states and 5918 transitions. [2023-11-12 02:21:20,663 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-12 02:21:20,663 INFO L218 hiAutomatonCegarLoop]: Abstraction has 4412 states and 5918 transitions. [2023-11-12 02:21:20,669 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 4412 states and 5918 transitions. [2023-11-12 02:21:20,730 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 4412 to 3868. [2023-11-12 02:21:20,738 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 3868 states, 3868 states have (on average 1.3495346432264737) internal successors, (5220), 3867 states have internal predecessors, (5220), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-12 02:21:20,750 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3868 states to 3868 states and 5220 transitions. [2023-11-12 02:21:20,750 INFO L240 hiAutomatonCegarLoop]: Abstraction has 3868 states and 5220 transitions. [2023-11-12 02:21:20,750 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-12 02:21:20,751 INFO L428 stractBuchiCegarLoop]: Abstraction has 3868 states and 5220 transitions. [2023-11-12 02:21:20,751 INFO L335 stractBuchiCegarLoop]: ======== Iteration 10 ============ [2023-11-12 02:21:20,751 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 3868 states and 5220 transitions. [2023-11-12 02:21:20,771 INFO L131 ngComponentsAnalysis]: Automaton has 6 accepting balls. 3829 [2023-11-12 02:21:20,771 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-12 02:21:20,772 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-12 02:21:20,772 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-12 02:21:20,772 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-12 02:21:20,773 INFO L748 eck$LassoCheckResult]: Stem: 33338#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(17, 2);call #Ultimate.allocInit(12, 3);~fast_clk_edge~0 := 0;~slow_clk_edge~0 := 0;~q_buf_0~0 := 0;~q_free~0 := 0;~q_read_ev~0 := 0;~q_write_ev~0 := 0;~q_req_up~0 := 0;~q_ev~0 := 0;~p_num_write~0 := 0;~p_last_write~0 := 0;~p_dw_st~0 := 0;~p_dw_pc~0 := 0;~p_dw_i~0 := 0;~c_num_read~0 := 0;~c_last_read~0 := 0;~c_dr_st~0 := 0;~c_dr_pc~0 := 0;~c_dr_i~0 := 0;~a_t~0 := 0;~t~0 := 0; 33339#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~3#1;havoc main_~__retres1~3#1;assume { :begin_inline_init_model } true;~fast_clk_edge~0 := 2;~slow_clk_edge~0 := 2;~q_free~0 := 1;~q_write_ev~0 := 2;~q_read_ev~0 := ~q_write_ev~0;~p_num_write~0 := 0;~p_dw_pc~0 := 0;~p_dw_i~0 := 1;~c_num_read~0 := 0;~c_dr_pc~0 := 0;~c_dr_i~0 := 1; 33362#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret13#1, start_simulation_#t~ret14#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~4#1, start_simulation_~tmp___0~3#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~4#1;havoc start_simulation_~tmp___0~3#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 33344#L258 assume !(1 == ~q_req_up~0); 33345#L258-2 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 33396#L273 assume 1 == ~p_dw_i~0;~p_dw_st~0 := 0; 33397#L273-2 assume 1 == ~c_dr_i~0;~c_dr_st~0 := 0; 33439#L278-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 33375#L311 assume !(0 == ~q_read_ev~0); 33376#L311-2 assume !(0 == ~q_write_ev~0); 33417#L316-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;assume { :begin_inline_is_do_write_p_triggered } true;havoc is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;havoc is_do_write_p_triggered_~__retres1~0#1; 33352#L66 assume !(1 == ~p_dw_pc~0); 33353#L66-2 assume !(2 == ~p_dw_pc~0); 33365#L76-1 is_do_write_p_triggered_~__retres1~0#1 := 0; 33390#L87 is_do_write_p_triggered_#res#1 := is_do_write_p_triggered_~__retres1~0#1; 33391#is_do_write_p_triggered_returnLabel#1 activate_threads_#t~ret7#1 := is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;assume { :end_inline_is_do_write_p_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1; 33384#L387 assume !(0 != activate_threads_~tmp~1#1); 33385#L387-2 assume { :begin_inline_is_do_read_c_triggered } true;havoc is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;havoc is_do_read_c_triggered_~__retres1~1#1; 33425#L95 assume !(1 == ~c_dr_pc~0); 33426#L95-2 assume !(2 == ~c_dr_pc~0); 33398#L105-1 is_do_read_c_triggered_~__retres1~1#1 := 0; 33336#L116 is_do_read_c_triggered_#res#1 := is_do_read_c_triggered_~__retres1~1#1; 33337#is_do_read_c_triggered_returnLabel#1 activate_threads_#t~ret8#1 := is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;assume { :end_inline_is_do_read_c_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 33346#L395 assume !(0 != activate_threads_~tmp___0~1#1); 33313#L395-2 havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 33314#L329 assume !(1 == ~q_read_ev~0); 33349#L329-2 assume !(1 == ~q_write_ev~0); 33358#L334-1 assume { :end_inline_reset_delta_events } true; 33359#L491-2 assume !false; 33605#L492 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret9#1, eval_#t~nondet10#1, eval_#t~nondet11#1, eval_~tmp~2#1, eval_~tmp___0~2#1, eval_~tmp___1~0#1;havoc eval_~tmp~2#1;havoc eval_~tmp___0~2#1;havoc eval_~tmp___1~0#1; 33575#L435 [2023-11-12 02:21:20,773 INFO L750 eck$LassoCheckResult]: Loop: 33575#L435 assume !false; 33603#L411 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 33601#L291 assume 0 == ~p_dw_st~0;exists_runnable_thread_~__retres1~2#1 := 1; 33598#L303 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 33594#exists_runnable_thread_returnLabel#1 eval_#t~ret9#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp___1~0#1 := eval_#t~ret9#1;havoc eval_#t~ret9#1; 33591#L415 assume 0 != eval_~tmp___1~0#1; 33586#L415-1 assume 0 == ~p_dw_st~0;havoc eval_#t~nondet10#1;eval_~tmp~2#1 := eval_#t~nondet10#1;havoc eval_#t~nondet10#1; 33583#L424 assume !(0 != eval_~tmp~2#1); 33580#L420 assume 0 == ~c_dr_st~0;havoc eval_#t~nondet11#1;eval_~tmp___0~2#1 := eval_#t~nondet11#1;havoc eval_#t~nondet11#1; 33574#L439 assume !(0 != eval_~tmp___0~2#1); 33575#L435 [2023-11-12 02:21:20,773 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-12 02:21:20,774 INFO L85 PathProgramCache]: Analyzing trace with hash -293592559, now seen corresponding path program 2 times [2023-11-12 02:21:20,774 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-12 02:21:20,774 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [326160682] [2023-11-12 02:21:20,774 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-12 02:21:20,774 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-12 02:21:20,782 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-12 02:21:20,783 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-12 02:21:20,787 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-12 02:21:20,793 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-12 02:21:20,793 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-12 02:21:20,794 INFO L85 PathProgramCache]: Analyzing trace with hash -418551845, now seen corresponding path program 1 times [2023-11-12 02:21:20,794 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-12 02:21:20,794 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1141610112] [2023-11-12 02:21:20,794 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-12 02:21:20,794 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-12 02:21:20,798 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-12 02:21:20,798 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-12 02:21:20,800 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-12 02:21:20,802 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-12 02:21:20,802 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-12 02:21:20,802 INFO L85 PathProgramCache]: Analyzing trace with hash 1670788587, now seen corresponding path program 1 times [2023-11-12 02:21:20,803 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-12 02:21:20,803 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [913171116] [2023-11-12 02:21:20,803 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-12 02:21:20,803 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-12 02:21:20,811 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-12 02:21:20,812 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-12 02:21:20,817 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-12 02:21:20,823 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-12 02:21:21,893 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-12 02:21:21,893 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-12 02:21:21,908 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-12 02:21:22,010 INFO L201 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer CFG 12.11 02:21:22 BoogieIcfgContainer [2023-11-12 02:21:22,011 INFO L131 PluginConnector]: ------------------------ END BuchiAutomizer---------------------------- [2023-11-12 02:21:22,011 INFO L112 PluginConnector]: ------------------------Witness Printer---------------------------- [2023-11-12 02:21:22,011 INFO L270 PluginConnector]: Initializing Witness Printer... [2023-11-12 02:21:22,012 INFO L274 PluginConnector]: Witness Printer initialized [2023-11-12 02:21:22,012 INFO L184 PluginConnector]: Executing the observer RCFGCatcher from plugin Witness Printer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 12.11 02:21:16" (3/4) ... [2023-11-12 02:21:22,014 INFO L134 WitnessPrinter]: Generating witness for non-termination counterexample [2023-11-12 02:21:22,116 INFO L149 WitnessManager]: Wrote witness to /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_91a087e5-1716-4e19-8e40-2ed3c2dea3c1/bin/uautomizer-verify-uTZkv6EMXl/witness.graphml [2023-11-12 02:21:22,116 INFO L131 PluginConnector]: ------------------------ END Witness Printer---------------------------- [2023-11-12 02:21:22,117 INFO L158 Benchmark]: Toolchain (without parser) took 6617.87ms. Allocated memory was 178.3MB in the beginning and 220.2MB in the end (delta: 41.9MB). Free memory was 148.6MB in the beginning and 62.2MB in the end (delta: 86.3MB). Peak memory consumption was 127.2MB. Max. memory is 16.1GB. [2023-11-12 02:21:22,117 INFO L158 Benchmark]: CDTParser took 0.31ms. Allocated memory is still 134.2MB. Free memory was 106.8MB in the beginning and 106.7MB in the end (delta: 139.9kB). There was no memory consumed. Max. memory is 16.1GB. [2023-11-12 02:21:22,117 INFO L158 Benchmark]: CACSL2BoogieTranslator took 398.55ms. Allocated memory is still 178.3MB. Free memory was 148.4MB in the beginning and 138.1MB in the end (delta: 10.3MB). Peak memory consumption was 12.8MB. Max. memory is 16.1GB. [2023-11-12 02:21:22,118 INFO L158 Benchmark]: Boogie Procedure Inliner took 64.45ms. Allocated memory is still 178.3MB. Free memory was 138.1MB in the beginning and 136.0MB in the end (delta: 2.1MB). Peak memory consumption was 2.1MB. Max. memory is 16.1GB. [2023-11-12 02:21:22,118 INFO L158 Benchmark]: Boogie Preprocessor took 47.90ms. Allocated memory is still 178.3MB. Free memory was 136.0MB in the beginning and 133.9MB in the end (delta: 2.1MB). Peak memory consumption was 2.1MB. Max. memory is 16.1GB. [2023-11-12 02:21:22,118 INFO L158 Benchmark]: RCFGBuilder took 769.69ms. Allocated memory is still 178.3MB. Free memory was 133.9MB in the beginning and 133.6MB in the end (delta: 265.1kB). Peak memory consumption was 14.7MB. Max. memory is 16.1GB. [2023-11-12 02:21:22,119 INFO L158 Benchmark]: BuchiAutomizer took 5224.49ms. Allocated memory was 178.3MB in the beginning and 220.2MB in the end (delta: 41.9MB). Free memory was 133.6MB in the beginning and 66.4MB in the end (delta: 67.2MB). Peak memory consumption was 110.0MB. Max. memory is 16.1GB. [2023-11-12 02:21:22,119 INFO L158 Benchmark]: Witness Printer took 104.79ms. Allocated memory is still 220.2MB. Free memory was 66.4MB in the beginning and 62.2MB in the end (delta: 4.2MB). Peak memory consumption was 4.2MB. Max. memory is 16.1GB. [2023-11-12 02:21:22,121 INFO L338 ainManager$Toolchain]: ####################### End [Toolchain 1] ####################### --- Results --- * Results from de.uni_freiburg.informatik.ultimate.core: - StatisticsResult: Toolchain Benchmarks Benchmark results are: * CDTParser took 0.31ms. Allocated memory is still 134.2MB. Free memory was 106.8MB in the beginning and 106.7MB in the end (delta: 139.9kB). There was no memory consumed. Max. memory is 16.1GB. * CACSL2BoogieTranslator took 398.55ms. Allocated memory is still 178.3MB. Free memory was 148.4MB in the beginning and 138.1MB in the end (delta: 10.3MB). Peak memory consumption was 12.8MB. Max. memory is 16.1GB. * Boogie Procedure Inliner took 64.45ms. Allocated memory is still 178.3MB. Free memory was 138.1MB in the beginning and 136.0MB in the end (delta: 2.1MB). Peak memory consumption was 2.1MB. Max. memory is 16.1GB. * Boogie Preprocessor took 47.90ms. Allocated memory is still 178.3MB. Free memory was 136.0MB in the beginning and 133.9MB in the end (delta: 2.1MB). Peak memory consumption was 2.1MB. Max. memory is 16.1GB. * RCFGBuilder took 769.69ms. Allocated memory is still 178.3MB. Free memory was 133.9MB in the beginning and 133.6MB in the end (delta: 265.1kB). Peak memory consumption was 14.7MB. Max. memory is 16.1GB. * BuchiAutomizer took 5224.49ms. Allocated memory was 178.3MB in the beginning and 220.2MB in the end (delta: 41.9MB). Free memory was 133.6MB in the beginning and 66.4MB in the end (delta: 67.2MB). Peak memory consumption was 110.0MB. Max. memory is 16.1GB. * Witness Printer took 104.79ms. Allocated memory is still 220.2MB. Free memory was 66.4MB in the beginning and 62.2MB in the end (delta: 4.2MB). Peak memory consumption was 4.2MB. Max. memory is 16.1GB. * Results from de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction: - StatisticsResult: Constructed decomposition of program Your program was decomposed into 9 terminating modules (9 trivial, 0 deterministic, 0 nondeterministic) and one nonterminating remainder module.9 modules have a trivial ranking function, the largest among these consists of 5 locations. The remainder module has 3868 locations. - StatisticsResult: Timing statistics BüchiAutomizer plugin needed 5.0s and 10 iterations. TraceHistogramMax:1. Analysis of lassos took 2.8s. Construction of modules took 0.3s. Büchi inclusion checks took 1.5s. Highest rank in rank-based complementation 0. Minimization of det autom 9. Minimization of nondet autom 0. Automata minimization 0.5s AutomataMinimizationTime, 9 MinimizatonAttempts, 3132 StatesRemovedByMinimization, 5 NontrivialMinimizations. Non-live state removal took 0.4s Buchi closure took 0.0s. Biggest automaton had -1 states and ocurred in iteration -1. Nontrivial modules had stage [0, 0, 0, 0, 0]. InterpolantCoveringCapabilityFinite: 0/0 InterpolantCoveringCapabilityBuchi: 0/0 HoareTripleCheckerStatistics: 0 mSolverCounterUnknown, 2703 SdHoareTripleChecker+Valid, 0.4s IncrementalHoareTripleChecker+Time, 0 mSdLazyCounter, 2703 mSDsluCounter, 4091 SdHoareTripleChecker+Invalid, 0.3s Time, 0 mProtectedAction, 0 SdHoareTripleChecker+Unchecked, 0 IncrementalHoareTripleChecker+Unchecked, 2468 mSDsCounter, 105 IncrementalHoareTripleChecker+Valid, 0 mProtectedPredicate, 276 IncrementalHoareTripleChecker+Invalid, 381 SdHoareTripleChecker+Unknown, 0 mSolverCounterNotChecked, 105 mSolverCounterUnsat, 1623 mSDtfsCounter, 276 mSolverCounterSat, 0.1s SdHoareTripleChecker+Time, 0 IncrementalHoareTripleChecker+Unknown LassoAnalysisResults: nont1 unkn0 SFLI3 SFLT0 conc1 concLT0 SILN0 SILU0 SILI5 SILT0 lasso0 LassoPreprocessingBenchmarks: LassoTerminationAnalysisBenchmarks: not availableLassoTerminationAnalysisBenchmarks: LassoNonterminationAnalysisSatFixpoint: 0 LassoNonterminationAnalysisSatUnbounded: 0 LassoNonterminationAnalysisUnsat: 0 LassoNonterminationAnalysisUnknown: 0 LassoNonterminationAnalysisTime: 0.0s InitialAbstractionConstructionTime: 0.0s - TerminationAnalysisResult: Nontermination possible Buchi Automizer proved that your program is nonterminating for some inputs - LassoShapedNonTerminationArgument [Line: 410]: Nontermination argument in form of an infinite program execution. Nontermination argument in form of an infinite program execution. Stem: [L24] int fast_clk_edge ; [L25] int slow_clk_edge ; [L26] int q_buf_0 ; [L27] int q_free ; [L28] int q_read_ev ; [L29] int q_write_ev ; [L30] int q_req_up ; [L31] int q_ev ; [L52] int p_num_write ; [L53] int p_last_write ; [L54] int p_dw_st ; [L55] int p_dw_pc ; [L56] int p_dw_i ; [L57] int c_num_read ; [L58] int c_last_read ; [L59] int c_dr_st ; [L60] int c_dr_pc ; [L61] int c_dr_i ; [L194] static int a_t ; [L344] static int t = 0; VAL [a_t=0, c_dr_i=0, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, fast_clk_edge=0, p_dw_i=0, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=0, q_read_ev=0, q_req_up=0, q_write_ev=0, slow_clk_edge=0, t=0] [L555] int __retres1 ; [L559] CALL init_model() [L539] fast_clk_edge = 2 [L540] slow_clk_edge = 2 [L541] q_free = 1 [L542] q_write_ev = 2 [L543] q_read_ev = q_write_ev [L544] p_num_write = 0 [L545] p_dw_pc = 0 [L546] p_dw_i = 1 [L547] c_num_read = 0 [L548] c_dr_pc = 0 [L549] c_dr_i = 1 VAL [a_t=0, c_dr_i=1, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, fast_clk_edge=2, p_dw_i=1, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=1, q_read_ev=2, q_req_up=0, q_write_ev=2, slow_clk_edge=2, t=0] [L559] RET init_model() [L560] CALL start_simulation() [L477] int kernel_st ; [L478] int tmp ; [L479] int tmp___0 ; [L483] kernel_st = 0 [L484] CALL update_channels() [L258] COND FALSE !((int )q_req_up == 1) VAL [a_t=0, c_dr_i=1, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, fast_clk_edge=2, p_dw_i=1, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=1, q_read_ev=2, q_req_up=0, q_write_ev=2, slow_clk_edge=2, t=0] [L484] RET update_channels() [L485] CALL init_threads() [L273] COND TRUE (int )p_dw_i == 1 [L274] p_dw_st = 0 VAL [a_t=0, c_dr_i=1, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, fast_clk_edge=2, p_dw_i=1, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=1, q_read_ev=2, q_req_up=0, q_write_ev=2, slow_clk_edge=2, t=0] [L278] COND TRUE (int )c_dr_i == 1 [L279] c_dr_st = 0 VAL [a_t=0, c_dr_i=1, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, fast_clk_edge=2, p_dw_i=1, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=1, q_read_ev=2, q_req_up=0, q_write_ev=2, slow_clk_edge=2, t=0] [L485] RET init_threads() [L486] CALL fire_delta_events() [L311] COND FALSE !((int )q_read_ev == 0) VAL [a_t=0, c_dr_i=1, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, fast_clk_edge=2, p_dw_i=1, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=1, q_read_ev=2, q_req_up=0, q_write_ev=2, slow_clk_edge=2, t=0] [L316] COND FALSE !((int )q_write_ev == 0) VAL [a_t=0, c_dr_i=1, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, fast_clk_edge=2, p_dw_i=1, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=1, q_read_ev=2, q_req_up=0, q_write_ev=2, slow_clk_edge=2, t=0] [L486] RET fire_delta_events() [L487] CALL activate_threads() [L380] int tmp ; [L381] int tmp___0 ; [L385] CALL, EXPR is_do_write_p_triggered() [L63] int __retres1 ; VAL [a_t=0, c_dr_i=1, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, fast_clk_edge=2, p_dw_i=1, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=1, q_read_ev=2, q_req_up=0, q_write_ev=2, slow_clk_edge=2, t=0] [L66] COND FALSE !((int )p_dw_pc == 1) VAL [a_t=0, c_dr_i=1, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, fast_clk_edge=2, p_dw_i=1, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=1, q_read_ev=2, q_req_up=0, q_write_ev=2, slow_clk_edge=2, t=0] [L76] COND FALSE !((int )p_dw_pc == 2) VAL [a_t=0, c_dr_i=1, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, fast_clk_edge=2, p_dw_i=1, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=1, q_read_ev=2, q_req_up=0, q_write_ev=2, slow_clk_edge=2, t=0] [L86] __retres1 = 0 VAL [__retres1=0, a_t=0, c_dr_i=1, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, fast_clk_edge=2, p_dw_i=1, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=1, q_read_ev=2, q_req_up=0, q_write_ev=2, slow_clk_edge=2, t=0] [L88] return (__retres1); VAL [\result=0, __retres1=0, a_t=0, c_dr_i=1, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, fast_clk_edge=2, p_dw_i=1, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=1, q_read_ev=2, q_req_up=0, q_write_ev=2, slow_clk_edge=2, t=0] [L385] RET, EXPR is_do_write_p_triggered() [L385] tmp = is_do_write_p_triggered() [L387] COND FALSE !(\read(tmp)) VAL [a_t=0, c_dr_i=1, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, fast_clk_edge=2, p_dw_i=1, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=1, q_read_ev=2, q_req_up=0, q_write_ev=2, slow_clk_edge=2, t=0, tmp=0] [L393] CALL, EXPR is_do_read_c_triggered() [L92] int __retres1 ; VAL [a_t=0, c_dr_i=1, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, fast_clk_edge=2, p_dw_i=1, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=1, q_read_ev=2, q_req_up=0, q_write_ev=2, slow_clk_edge=2, t=0] [L95] COND FALSE !((int )c_dr_pc == 1) VAL [a_t=0, c_dr_i=1, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, fast_clk_edge=2, p_dw_i=1, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=1, q_read_ev=2, q_req_up=0, q_write_ev=2, slow_clk_edge=2, t=0] [L105] COND FALSE !((int )c_dr_pc == 2) VAL [a_t=0, c_dr_i=1, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, fast_clk_edge=2, p_dw_i=1, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=1, q_read_ev=2, q_req_up=0, q_write_ev=2, slow_clk_edge=2, t=0] [L115] __retres1 = 0 VAL [__retres1=0, a_t=0, c_dr_i=1, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, fast_clk_edge=2, p_dw_i=1, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=1, q_read_ev=2, q_req_up=0, q_write_ev=2, slow_clk_edge=2, t=0] [L117] return (__retres1); VAL [\result=0, __retres1=0, a_t=0, c_dr_i=1, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, fast_clk_edge=2, p_dw_i=1, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=1, q_read_ev=2, q_req_up=0, q_write_ev=2, slow_clk_edge=2, t=0] [L393] RET, EXPR is_do_read_c_triggered() [L393] tmp___0 = is_do_read_c_triggered() [L395] COND FALSE !(\read(tmp___0)) VAL [a_t=0, c_dr_i=1, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, fast_clk_edge=2, p_dw_i=1, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=1, q_read_ev=2, q_req_up=0, q_write_ev=2, slow_clk_edge=2, t=0, tmp=0, tmp___0=0] [L487] RET activate_threads() [L488] CALL reset_delta_events() [L329] COND FALSE !((int )q_read_ev == 1) VAL [a_t=0, c_dr_i=1, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, fast_clk_edge=2, p_dw_i=1, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=1, q_read_ev=2, q_req_up=0, q_write_ev=2, slow_clk_edge=2, t=0] [L334] COND FALSE !((int )q_write_ev == 1) VAL [a_t=0, c_dr_i=1, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, fast_clk_edge=2, p_dw_i=1, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=1, q_read_ev=2, q_req_up=0, q_write_ev=2, slow_clk_edge=2, t=0] [L488] RET reset_delta_events() [L491] COND TRUE 1 VAL [a_t=0, c_dr_i=1, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, fast_clk_edge=2, kernel_st=0, p_dw_i=1, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=1, q_read_ev=2, q_req_up=0, q_write_ev=2, slow_clk_edge=2, t=0] [L494] kernel_st = 1 [L495] CALL eval() [L405] int tmp ; [L406] int tmp___0 ; [L407] int tmp___1 ; VAL [a_t=0, c_dr_i=1, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, fast_clk_edge=2, p_dw_i=1, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=1, q_read_ev=2, q_req_up=0, q_write_ev=2, slow_clk_edge=2, t=0] Loop: [L410] COND TRUE 1 [L413] CALL, EXPR exists_runnable_thread() [L288] int __retres1 ; [L291] COND TRUE (int )p_dw_st == 0 [L292] __retres1 = 1 [L304] return (__retres1); [L413] RET, EXPR exists_runnable_thread() [L413] tmp___1 = exists_runnable_thread() [L415] COND TRUE \read(tmp___1) [L420] COND TRUE (int )p_dw_st == 0 [L422] tmp = __VERIFIER_nondet_int() [L424] COND FALSE !(\read(tmp)) [L435] COND TRUE (int )c_dr_st == 0 [L437] tmp___0 = __VERIFIER_nondet_int() [L439] COND FALSE !(\read(tmp___0)) End of lasso representation. - StatisticsResult: NonterminationArgumentStatistics Fixpoint - NonterminatingLassoResult [Line: 410]: Nonterminating execution Found a nonterminating execution for the following lasso shaped sequence of statements. Stem: [L24] int fast_clk_edge ; [L25] int slow_clk_edge ; [L26] int q_buf_0 ; [L27] int q_free ; [L28] int q_read_ev ; [L29] int q_write_ev ; [L30] int q_req_up ; [L31] int q_ev ; [L52] int p_num_write ; [L53] int p_last_write ; [L54] int p_dw_st ; [L55] int p_dw_pc ; [L56] int p_dw_i ; [L57] int c_num_read ; [L58] int c_last_read ; [L59] int c_dr_st ; [L60] int c_dr_pc ; [L61] int c_dr_i ; [L194] static int a_t ; [L344] static int t = 0; VAL [a_t=0, c_dr_i=0, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, fast_clk_edge=0, p_dw_i=0, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=0, q_read_ev=0, q_req_up=0, q_write_ev=0, slow_clk_edge=0, t=0] [L555] int __retres1 ; [L559] CALL init_model() [L539] fast_clk_edge = 2 [L540] slow_clk_edge = 2 [L541] q_free = 1 [L542] q_write_ev = 2 [L543] q_read_ev = q_write_ev [L544] p_num_write = 0 [L545] p_dw_pc = 0 [L546] p_dw_i = 1 [L547] c_num_read = 0 [L548] c_dr_pc = 0 [L549] c_dr_i = 1 VAL [a_t=0, c_dr_i=1, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, fast_clk_edge=2, p_dw_i=1, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=1, q_read_ev=2, q_req_up=0, q_write_ev=2, slow_clk_edge=2, t=0] [L559] RET init_model() [L560] CALL start_simulation() [L477] int kernel_st ; [L478] int tmp ; [L479] int tmp___0 ; [L483] kernel_st = 0 [L484] CALL update_channels() [L258] COND FALSE !((int )q_req_up == 1) VAL [a_t=0, c_dr_i=1, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, fast_clk_edge=2, p_dw_i=1, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=1, q_read_ev=2, q_req_up=0, q_write_ev=2, slow_clk_edge=2, t=0] [L484] RET update_channels() [L485] CALL init_threads() [L273] COND TRUE (int )p_dw_i == 1 [L274] p_dw_st = 0 VAL [a_t=0, c_dr_i=1, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, fast_clk_edge=2, p_dw_i=1, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=1, q_read_ev=2, q_req_up=0, q_write_ev=2, slow_clk_edge=2, t=0] [L278] COND TRUE (int )c_dr_i == 1 [L279] c_dr_st = 0 VAL [a_t=0, c_dr_i=1, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, fast_clk_edge=2, p_dw_i=1, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=1, q_read_ev=2, q_req_up=0, q_write_ev=2, slow_clk_edge=2, t=0] [L485] RET init_threads() [L486] CALL fire_delta_events() [L311] COND FALSE !((int )q_read_ev == 0) VAL [a_t=0, c_dr_i=1, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, fast_clk_edge=2, p_dw_i=1, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=1, q_read_ev=2, q_req_up=0, q_write_ev=2, slow_clk_edge=2, t=0] [L316] COND FALSE !((int )q_write_ev == 0) VAL [a_t=0, c_dr_i=1, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, fast_clk_edge=2, p_dw_i=1, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=1, q_read_ev=2, q_req_up=0, q_write_ev=2, slow_clk_edge=2, t=0] [L486] RET fire_delta_events() [L487] CALL activate_threads() [L380] int tmp ; [L381] int tmp___0 ; [L385] CALL, EXPR is_do_write_p_triggered() [L63] int __retres1 ; VAL [a_t=0, c_dr_i=1, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, fast_clk_edge=2, p_dw_i=1, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=1, q_read_ev=2, q_req_up=0, q_write_ev=2, slow_clk_edge=2, t=0] [L66] COND FALSE !((int )p_dw_pc == 1) VAL [a_t=0, c_dr_i=1, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, fast_clk_edge=2, p_dw_i=1, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=1, q_read_ev=2, q_req_up=0, q_write_ev=2, slow_clk_edge=2, t=0] [L76] COND FALSE !((int )p_dw_pc == 2) VAL [a_t=0, c_dr_i=1, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, fast_clk_edge=2, p_dw_i=1, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=1, q_read_ev=2, q_req_up=0, q_write_ev=2, slow_clk_edge=2, t=0] [L86] __retres1 = 0 VAL [__retres1=0, a_t=0, c_dr_i=1, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, fast_clk_edge=2, p_dw_i=1, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=1, q_read_ev=2, q_req_up=0, q_write_ev=2, slow_clk_edge=2, t=0] [L88] return (__retres1); VAL [\result=0, __retres1=0, a_t=0, c_dr_i=1, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, fast_clk_edge=2, p_dw_i=1, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=1, q_read_ev=2, q_req_up=0, q_write_ev=2, slow_clk_edge=2, t=0] [L385] RET, EXPR is_do_write_p_triggered() [L385] tmp = is_do_write_p_triggered() [L387] COND FALSE !(\read(tmp)) VAL [a_t=0, c_dr_i=1, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, fast_clk_edge=2, p_dw_i=1, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=1, q_read_ev=2, q_req_up=0, q_write_ev=2, slow_clk_edge=2, t=0, tmp=0] [L393] CALL, EXPR is_do_read_c_triggered() [L92] int __retres1 ; VAL [a_t=0, c_dr_i=1, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, fast_clk_edge=2, p_dw_i=1, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=1, q_read_ev=2, q_req_up=0, q_write_ev=2, slow_clk_edge=2, t=0] [L95] COND FALSE !((int )c_dr_pc == 1) VAL [a_t=0, c_dr_i=1, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, fast_clk_edge=2, p_dw_i=1, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=1, q_read_ev=2, q_req_up=0, q_write_ev=2, slow_clk_edge=2, t=0] [L105] COND FALSE !((int )c_dr_pc == 2) VAL [a_t=0, c_dr_i=1, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, fast_clk_edge=2, p_dw_i=1, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=1, q_read_ev=2, q_req_up=0, q_write_ev=2, slow_clk_edge=2, t=0] [L115] __retres1 = 0 VAL [__retres1=0, a_t=0, c_dr_i=1, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, fast_clk_edge=2, p_dw_i=1, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=1, q_read_ev=2, q_req_up=0, q_write_ev=2, slow_clk_edge=2, t=0] [L117] return (__retres1); VAL [\result=0, __retres1=0, a_t=0, c_dr_i=1, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, fast_clk_edge=2, p_dw_i=1, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=1, q_read_ev=2, q_req_up=0, q_write_ev=2, slow_clk_edge=2, t=0] [L393] RET, EXPR is_do_read_c_triggered() [L393] tmp___0 = is_do_read_c_triggered() [L395] COND FALSE !(\read(tmp___0)) VAL [a_t=0, c_dr_i=1, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, fast_clk_edge=2, p_dw_i=1, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=1, q_read_ev=2, q_req_up=0, q_write_ev=2, slow_clk_edge=2, t=0, tmp=0, tmp___0=0] [L487] RET activate_threads() [L488] CALL reset_delta_events() [L329] COND FALSE !((int )q_read_ev == 1) VAL [a_t=0, c_dr_i=1, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, fast_clk_edge=2, p_dw_i=1, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=1, q_read_ev=2, q_req_up=0, q_write_ev=2, slow_clk_edge=2, t=0] [L334] COND FALSE !((int )q_write_ev == 1) VAL [a_t=0, c_dr_i=1, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, fast_clk_edge=2, p_dw_i=1, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=1, q_read_ev=2, q_req_up=0, q_write_ev=2, slow_clk_edge=2, t=0] [L488] RET reset_delta_events() [L491] COND TRUE 1 VAL [a_t=0, c_dr_i=1, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, fast_clk_edge=2, kernel_st=0, p_dw_i=1, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=1, q_read_ev=2, q_req_up=0, q_write_ev=2, slow_clk_edge=2, t=0] [L494] kernel_st = 1 [L495] CALL eval() [L405] int tmp ; [L406] int tmp___0 ; [L407] int tmp___1 ; VAL [a_t=0, c_dr_i=1, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, fast_clk_edge=2, p_dw_i=1, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=1, q_read_ev=2, q_req_up=0, q_write_ev=2, slow_clk_edge=2, t=0] Loop: [L410] COND TRUE 1 [L413] CALL, EXPR exists_runnable_thread() [L288] int __retres1 ; [L291] COND TRUE (int )p_dw_st == 0 [L292] __retres1 = 1 [L304] return (__retres1); [L413] RET, EXPR exists_runnable_thread() [L413] tmp___1 = exists_runnable_thread() [L415] COND TRUE \read(tmp___1) [L420] COND TRUE (int )p_dw_st == 0 [L422] tmp = __VERIFIER_nondet_int() [L424] COND FALSE !(\read(tmp)) [L435] COND TRUE (int )c_dr_st == 0 [L437] tmp___0 = __VERIFIER_nondet_int() [L439] COND FALSE !(\read(tmp___0)) End of lasso representation. RESULT: Ultimate proved your program to be incorrect! [2023-11-12 02:21:22,205 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_91a087e5-1716-4e19-8e40-2ed3c2dea3c1/bin/uautomizer-verify-uTZkv6EMXl/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (1)] Ended with exit code 0 Received shutdown request... --- End real Ultimate output --- Execution finished normally Writing output log to file Ultimate.log Writing human readable error path to file UltimateCounterExample.errorpath Result: FALSE(TERM)