./Ultimate.py --spec ../../sv-benchmarks/c/properties/termination.prp --file ../../sv-benchmarks/c/loop-invgen/string_concat-noarr.i --full-output --architecture 32bit -------------------------------------------------------------------------------- Checking for termination Using default analysis Version cf1a7837 Calling Ultimate with: /usr/lib/jvm/java-1.11.0-openjdk-amd64/bin/java -Dosgi.configuration.area=/tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_13489a2e-8a24-4e25-8b20-2091353b9675/bin/uautomizer-verify-uTZkv6EMXl/data/config -Xmx15G -Xms4m -jar /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_13489a2e-8a24-4e25-8b20-2091353b9675/bin/uautomizer-verify-uTZkv6EMXl/plugins/org.eclipse.equinox.launcher_1.5.800.v20200727-1323.jar -data @noDefault -ultimatedata /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_13489a2e-8a24-4e25-8b20-2091353b9675/bin/uautomizer-verify-uTZkv6EMXl/data -tc /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_13489a2e-8a24-4e25-8b20-2091353b9675/bin/uautomizer-verify-uTZkv6EMXl/config/AutomizerTermination.xml -i ../../sv-benchmarks/c/loop-invgen/string_concat-noarr.i -s /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_13489a2e-8a24-4e25-8b20-2091353b9675/bin/uautomizer-verify-uTZkv6EMXl/config/svcomp-Termination-32bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_13489a2e-8a24-4e25-8b20-2091353b9675/bin/uautomizer-verify-uTZkv6EMXl --witnessprinter.witness.filename witness --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(F end) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 32bit --witnessprinter.graph.data.programhash 30a4b942034eaa47a8fcc8fdf4549d1d63a9a60d59b585da2a353c9626604750 --- Real Ultimate output --- This is Ultimate 0.2.3-dev-cf1a783 [2023-11-12 02:12:29,585 INFO L188 SettingsManager]: Resetting all preferences to default values... [2023-11-12 02:12:29,728 INFO L114 SettingsManager]: Loading settings from /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_13489a2e-8a24-4e25-8b20-2091353b9675/bin/uautomizer-verify-uTZkv6EMXl/config/svcomp-Termination-32bit-Automizer_Default.epf [2023-11-12 02:12:29,734 WARN L101 SettingsManager]: Preference file contains the following unknown settings: [2023-11-12 02:12:29,734 WARN L103 SettingsManager]: * de.uni_freiburg.informatik.ultimate.core.Log level for class [2023-11-12 02:12:29,779 INFO L130 SettingsManager]: Preferences different from defaults after loading the file: [2023-11-12 02:12:29,781 INFO L151 SettingsManager]: Preferences of UltimateCore differ from their defaults: [2023-11-12 02:12:29,782 INFO L153 SettingsManager]: * Log level for class=de.uni_freiburg.informatik.ultimate.lib.smtlibutils.quantifier.QuantifierPusher=ERROR; [2023-11-12 02:12:29,784 INFO L151 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2023-11-12 02:12:29,790 INFO L153 SettingsManager]: * Create parallel compositions if possible=false [2023-11-12 02:12:29,790 INFO L153 SettingsManager]: * Use SBE=true [2023-11-12 02:12:29,791 INFO L151 SettingsManager]: Preferences of BuchiAutomizer differ from their defaults: [2023-11-12 02:12:29,791 INFO L153 SettingsManager]: * NCSB implementation=INTSET_LAZY3 [2023-11-12 02:12:29,793 INFO L153 SettingsManager]: * Use old map elimination=false [2023-11-12 02:12:29,794 INFO L153 SettingsManager]: * Use external solver (rank synthesis)=false [2023-11-12 02:12:29,794 INFO L153 SettingsManager]: * Use only trivial implications for array writes=true [2023-11-12 02:12:29,795 INFO L153 SettingsManager]: * Rank analysis=LINEAR_WITH_GUESSES [2023-11-12 02:12:29,796 INFO L151 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2023-11-12 02:12:29,796 INFO L153 SettingsManager]: * Pointer base address is valid at dereference=ASSUME [2023-11-12 02:12:29,797 INFO L153 SettingsManager]: * sizeof long=4 [2023-11-12 02:12:29,797 INFO L153 SettingsManager]: * Overapproximate operations on floating types=true [2023-11-12 02:12:29,798 INFO L153 SettingsManager]: * sizeof POINTER=4 [2023-11-12 02:12:29,799 INFO L153 SettingsManager]: * Check division by zero=IGNORE [2023-11-12 02:12:29,799 INFO L153 SettingsManager]: * Pointer to allocated memory at dereference=ASSUME [2023-11-12 02:12:29,800 INFO L153 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=ASSUME [2023-11-12 02:12:29,800 INFO L153 SettingsManager]: * Check array bounds for arrays that are off heap=ASSUME [2023-11-12 02:12:29,801 INFO L153 SettingsManager]: * Check unreachability of reach_error function=false [2023-11-12 02:12:29,801 INFO L153 SettingsManager]: * sizeof long double=12 [2023-11-12 02:12:29,802 INFO L153 SettingsManager]: * Check if freed pointer was valid=false [2023-11-12 02:12:29,802 INFO L153 SettingsManager]: * Assume nondeterminstic values are in range=false [2023-11-12 02:12:29,804 INFO L153 SettingsManager]: * Use constant arrays=true [2023-11-12 02:12:29,804 INFO L151 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2023-11-12 02:12:29,804 INFO L153 SettingsManager]: * Size of a code block=SequenceOfStatements [2023-11-12 02:12:29,805 INFO L151 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2023-11-12 02:12:29,805 INFO L153 SettingsManager]: * Trace refinement strategy=CAMEL [2023-11-12 02:12:29,806 INFO L151 SettingsManager]: Preferences of IcfgTransformer differ from their defaults: [2023-11-12 02:12:29,806 INFO L153 SettingsManager]: * TransformationType=MODULO_NEIGHBOR WARNING: An illegal reflective access operation has occurred WARNING: Illegal reflective access by com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 (file:/tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_13489a2e-8a24-4e25-8b20-2091353b9675/bin/uautomizer-verify-uTZkv6EMXl/plugins/com.sun.xml.bind_2.2.0.v201505121915.jar) to method java.lang.ClassLoader.defineClass(java.lang.String,byte[],int,int) WARNING: Please consider reporting this to the maintainers of com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 WARNING: Use --illegal-access=warn to enable warnings of further illegal reflective access operations WARNING: All illegal access operations will be denied in a future release Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_13489a2e-8a24-4e25-8b20-2091353b9675/bin/uautomizer-verify-uTZkv6EMXl Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(F end) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 32bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> 30a4b942034eaa47a8fcc8fdf4549d1d63a9a60d59b585da2a353c9626604750 [2023-11-12 02:12:30,169 INFO L75 nceAwareModelManager]: Repository-Root is: /tmp [2023-11-12 02:12:30,206 INFO L261 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2023-11-12 02:12:30,210 INFO L217 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2023-11-12 02:12:30,211 INFO L270 PluginConnector]: Initializing CDTParser... [2023-11-12 02:12:30,214 INFO L274 PluginConnector]: CDTParser initialized [2023-11-12 02:12:30,216 INFO L431 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_13489a2e-8a24-4e25-8b20-2091353b9675/bin/uautomizer-verify-uTZkv6EMXl/../../sv-benchmarks/c/loop-invgen/string_concat-noarr.i [2023-11-12 02:12:33,708 INFO L533 CDTParser]: Created temporary CDT project at NULL [2023-11-12 02:12:33,936 INFO L384 CDTParser]: Found 1 translation units. [2023-11-12 02:12:33,937 INFO L180 CDTParser]: Scanning /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_13489a2e-8a24-4e25-8b20-2091353b9675/sv-benchmarks/c/loop-invgen/string_concat-noarr.i [2023-11-12 02:12:33,945 INFO L427 CDTParser]: About to delete temporary CDT project at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_13489a2e-8a24-4e25-8b20-2091353b9675/bin/uautomizer-verify-uTZkv6EMXl/data/ed380296a/1168fd8ed7bb4ec387f07be99f1774f4/FLAG14319814d [2023-11-12 02:12:33,959 INFO L435 CDTParser]: Successfully deleted /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_13489a2e-8a24-4e25-8b20-2091353b9675/bin/uautomizer-verify-uTZkv6EMXl/data/ed380296a/1168fd8ed7bb4ec387f07be99f1774f4 [2023-11-12 02:12:33,962 INFO L299 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2023-11-12 02:12:33,964 INFO L133 ToolchainWalker]: Walking toolchain with 6 elements. [2023-11-12 02:12:33,966 INFO L112 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2023-11-12 02:12:33,966 INFO L270 PluginConnector]: Initializing CACSL2BoogieTranslator... [2023-11-12 02:12:33,972 INFO L274 PluginConnector]: CACSL2BoogieTranslator initialized [2023-11-12 02:12:33,973 INFO L184 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 12.11 02:12:33" (1/1) ... [2023-11-12 02:12:33,974 INFO L204 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@13adbe63 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 12.11 02:12:33, skipping insertion in model container [2023-11-12 02:12:33,974 INFO L184 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 12.11 02:12:33" (1/1) ... [2023-11-12 02:12:33,999 INFO L177 MainTranslator]: Built tables and reachable declarations [2023-11-12 02:12:34,197 INFO L209 PostProcessor]: Analyzing one entry point: main [2023-11-12 02:12:34,215 INFO L202 MainTranslator]: Completed pre-run [2023-11-12 02:12:34,243 INFO L209 PostProcessor]: Analyzing one entry point: main [2023-11-12 02:12:34,264 INFO L206 MainTranslator]: Completed translation [2023-11-12 02:12:34,264 INFO L201 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 12.11 02:12:34 WrapperNode [2023-11-12 02:12:34,265 INFO L131 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2023-11-12 02:12:34,267 INFO L112 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2023-11-12 02:12:34,267 INFO L270 PluginConnector]: Initializing Boogie Procedure Inliner... [2023-11-12 02:12:34,267 INFO L274 PluginConnector]: Boogie Procedure Inliner initialized [2023-11-12 02:12:34,277 INFO L184 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 12.11 02:12:34" (1/1) ... [2023-11-12 02:12:34,285 INFO L184 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 12.11 02:12:34" (1/1) ... [2023-11-12 02:12:34,307 INFO L138 Inliner]: procedures = 16, calls = 8, calls flagged for inlining = 4, calls inlined = 4, statements flattened = 55 [2023-11-12 02:12:34,308 INFO L131 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2023-11-12 02:12:34,309 INFO L112 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2023-11-12 02:12:34,309 INFO L270 PluginConnector]: Initializing Boogie Preprocessor... [2023-11-12 02:12:34,309 INFO L274 PluginConnector]: Boogie Preprocessor initialized [2023-11-12 02:12:34,319 INFO L184 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 12.11 02:12:34" (1/1) ... [2023-11-12 02:12:34,320 INFO L184 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 12.11 02:12:34" (1/1) ... [2023-11-12 02:12:34,321 INFO L184 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 12.11 02:12:34" (1/1) ... [2023-11-12 02:12:34,322 INFO L184 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 12.11 02:12:34" (1/1) ... [2023-11-12 02:12:34,325 INFO L184 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 12.11 02:12:34" (1/1) ... [2023-11-12 02:12:34,330 INFO L184 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 12.11 02:12:34" (1/1) ... [2023-11-12 02:12:34,331 INFO L184 PluginConnector]: Executing the observer LTLStepAnnotator from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 12.11 02:12:34" (1/1) ... [2023-11-12 02:12:34,332 INFO L184 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 12.11 02:12:34" (1/1) ... [2023-11-12 02:12:34,334 INFO L131 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2023-11-12 02:12:34,335 INFO L112 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2023-11-12 02:12:34,335 INFO L270 PluginConnector]: Initializing RCFGBuilder... [2023-11-12 02:12:34,335 INFO L274 PluginConnector]: RCFGBuilder initialized [2023-11-12 02:12:34,336 INFO L184 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 12.11 02:12:34" (1/1) ... [2023-11-12 02:12:34,347 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2023-11-12 02:12:34,360 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_13489a2e-8a24-4e25-8b20-2091353b9675/bin/uautomizer-verify-uTZkv6EMXl/z3 [2023-11-12 02:12:34,388 INFO L229 MonitoredProcess]: Starting monitored process 1 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_13489a2e-8a24-4e25-8b20-2091353b9675/bin/uautomizer-verify-uTZkv6EMXl/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2023-11-12 02:12:34,418 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_13489a2e-8a24-4e25-8b20-2091353b9675/bin/uautomizer-verify-uTZkv6EMXl/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (1)] Waiting until timeout for monitored process [2023-11-12 02:12:34,460 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocInit [2023-11-12 02:12:34,460 INFO L130 BoogieDeclarations]: Found specification of procedure write~init~int [2023-11-12 02:12:34,461 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2023-11-12 02:12:34,461 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2023-11-12 02:12:34,554 INFO L236 CfgBuilder]: Building ICFG [2023-11-12 02:12:34,557 INFO L262 CfgBuilder]: Building CFG for each procedure with an implementation [2023-11-12 02:12:34,780 INFO L277 CfgBuilder]: Performing block encoding [2023-11-12 02:12:34,791 INFO L297 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2023-11-12 02:12:34,792 INFO L302 CfgBuilder]: Removed 2 assume(true) statements. [2023-11-12 02:12:34,794 INFO L201 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 12.11 02:12:34 BoogieIcfgContainer [2023-11-12 02:12:34,795 INFO L131 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2023-11-12 02:12:34,796 INFO L112 PluginConnector]: ------------------------BuchiAutomizer---------------------------- [2023-11-12 02:12:34,797 INFO L270 PluginConnector]: Initializing BuchiAutomizer... [2023-11-12 02:12:34,802 INFO L274 PluginConnector]: BuchiAutomizer initialized [2023-11-12 02:12:34,803 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2023-11-12 02:12:34,804 INFO L184 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "CDTParser AST 12.11 02:12:33" (1/3) ... [2023-11-12 02:12:34,805 INFO L204 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@407a648d and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 12.11 02:12:34, skipping insertion in model container [2023-11-12 02:12:34,805 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2023-11-12 02:12:34,806 INFO L184 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 12.11 02:12:34" (2/3) ... [2023-11-12 02:12:34,806 INFO L204 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@407a648d and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 12.11 02:12:34, skipping insertion in model container [2023-11-12 02:12:34,806 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2023-11-12 02:12:34,807 INFO L184 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 12.11 02:12:34" (3/3) ... [2023-11-12 02:12:34,808 INFO L332 chiAutomizerObserver]: Analyzing ICFG string_concat-noarr.i [2023-11-12 02:12:34,883 INFO L303 stractBuchiCegarLoop]: Interprodecural is true [2023-11-12 02:12:34,883 INFO L304 stractBuchiCegarLoop]: Hoare is false [2023-11-12 02:12:34,883 INFO L305 stractBuchiCegarLoop]: Compute interpolants for ForwardPredicates [2023-11-12 02:12:34,883 INFO L306 stractBuchiCegarLoop]: Backedges is STRAIGHT_LINE [2023-11-12 02:12:34,884 INFO L307 stractBuchiCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2023-11-12 02:12:34,884 INFO L308 stractBuchiCegarLoop]: Difference is false [2023-11-12 02:12:34,884 INFO L309 stractBuchiCegarLoop]: Minimize is MINIMIZE_SEVPA [2023-11-12 02:12:34,885 INFO L313 stractBuchiCegarLoop]: ======== Iteration 0 == of CEGAR loop == BuchiAutomatonCegarLoop ======== [2023-11-12 02:12:34,891 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 18 states, 17 states have (on average 1.4705882352941178) internal successors, (25), 17 states have internal predecessors, (25), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-12 02:12:34,915 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 5 [2023-11-12 02:12:34,916 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-12 02:12:34,916 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-12 02:12:34,923 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1] [2023-11-12 02:12:34,923 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1] [2023-11-12 02:12:34,924 INFO L335 stractBuchiCegarLoop]: ======== Iteration 1 ============ [2023-11-12 02:12:34,924 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 18 states, 17 states have (on average 1.4705882352941178) internal successors, (25), 17 states have internal predecessors, (25), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-12 02:12:34,927 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 5 [2023-11-12 02:12:34,927 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-12 02:12:34,927 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-12 02:12:34,928 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1] [2023-11-12 02:12:34,928 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1] [2023-11-12 02:12:34,936 INFO L748 eck$LassoCheckResult]: Stem: 13#$Ultimate##0true assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(9, 2); 6#L-1true assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~post2#1, main_#t~nondet1#1, main_#t~post4#1, main_#t~post5#1, main_#t~nondet3#1, main_~i~0#1, main_~j~0#1;havoc main_~i~0#1;havoc main_~j~0#1; 5#L26true main_~i~0#1 := 0; 16#L29-2true [2023-11-12 02:12:34,937 INFO L750 eck$LassoCheckResult]: Loop: 16#L29-2true havoc main_#t~nondet1#1; 4#L29true assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 16#L29-2true [2023-11-12 02:12:34,944 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-12 02:12:34,944 INFO L85 PathProgramCache]: Analyzing trace with hash 29857, now seen corresponding path program 1 times [2023-11-12 02:12:34,957 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-12 02:12:34,958 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [538373186] [2023-11-12 02:12:34,958 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-12 02:12:34,959 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-12 02:12:35,066 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-12 02:12:35,067 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-12 02:12:35,075 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-12 02:12:35,097 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-12 02:12:35,101 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-12 02:12:35,102 INFO L85 PathProgramCache]: Analyzing trace with hash 1254, now seen corresponding path program 1 times [2023-11-12 02:12:35,102 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-12 02:12:35,102 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [69866015] [2023-11-12 02:12:35,103 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-12 02:12:35,103 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-12 02:12:35,115 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-12 02:12:35,115 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-12 02:12:35,119 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-12 02:12:35,121 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-12 02:12:35,123 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-12 02:12:35,124 INFO L85 PathProgramCache]: Analyzing trace with hash 28692870, now seen corresponding path program 1 times [2023-11-12 02:12:35,124 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-12 02:12:35,125 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [60044887] [2023-11-12 02:12:35,125 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-12 02:12:35,125 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-12 02:12:35,140 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-12 02:12:35,141 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-12 02:12:35,149 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-12 02:12:35,152 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-12 02:12:35,240 INFO L210 LassoAnalysis]: Preferences: [2023-11-12 02:12:35,241 INFO L126 ssoRankerPreferences]: Compute integeral hull: false [2023-11-12 02:12:35,241 INFO L127 ssoRankerPreferences]: Enable LassoPartitioneer: true [2023-11-12 02:12:35,241 INFO L128 ssoRankerPreferences]: Term annotations enabled: false [2023-11-12 02:12:35,242 INFO L129 ssoRankerPreferences]: Use exernal solver: true [2023-11-12 02:12:35,242 INFO L130 ssoRankerPreferences]: SMT solver command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2023-11-12 02:12:35,242 INFO L131 ssoRankerPreferences]: Dump SMT script to file: false [2023-11-12 02:12:35,242 INFO L132 ssoRankerPreferences]: Path of dumped script: [2023-11-12 02:12:35,243 INFO L133 ssoRankerPreferences]: Filename of dumped script: string_concat-noarr.i_Iteration1_Loop [2023-11-12 02:12:35,243 INFO L134 ssoRankerPreferences]: MapElimAlgo: Frank [2023-11-12 02:12:35,243 INFO L276 LassoAnalysis]: Starting lasso preprocessing... [2023-11-12 02:12:35,263 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-12 02:12:35,289 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-12 02:12:35,293 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-12 02:12:35,341 INFO L294 LassoAnalysis]: Preprocessing complete. [2023-11-12 02:12:35,341 INFO L404 LassoAnalysis]: Checking for nontermination... [2023-11-12 02:12:35,344 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2023-11-12 02:12:35,344 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_13489a2e-8a24-4e25-8b20-2091353b9675/bin/uautomizer-verify-uTZkv6EMXl/z3 [2023-11-12 02:12:35,355 INFO L229 MonitoredProcess]: Starting monitored process 2 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_13489a2e-8a24-4e25-8b20-2091353b9675/bin/uautomizer-verify-uTZkv6EMXl/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2023-11-12 02:12:35,361 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_13489a2e-8a24-4e25-8b20-2091353b9675/bin/uautomizer-verify-uTZkv6EMXl/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (2)] Waiting until timeout for monitored process [2023-11-12 02:12:35,372 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2023-11-12 02:12:35,373 INFO L160 nArgumentSynthesizer]: Using integer mode. [2023-11-12 02:12:35,392 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_13489a2e-8a24-4e25-8b20-2091353b9675/bin/uautomizer-verify-uTZkv6EMXl/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (2)] Ended with exit code 0 [2023-11-12 02:12:35,393 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2023-11-12 02:12:35,394 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_13489a2e-8a24-4e25-8b20-2091353b9675/bin/uautomizer-verify-uTZkv6EMXl/z3 [2023-11-12 02:12:35,395 INFO L229 MonitoredProcess]: Starting monitored process 3 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_13489a2e-8a24-4e25-8b20-2091353b9675/bin/uautomizer-verify-uTZkv6EMXl/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2023-11-12 02:12:35,399 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_13489a2e-8a24-4e25-8b20-2091353b9675/bin/uautomizer-verify-uTZkv6EMXl/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (3)] Waiting until timeout for monitored process [2023-11-12 02:12:35,401 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 3 Nilpotent components: true [2023-11-12 02:12:35,402 INFO L160 nArgumentSynthesizer]: Using integer mode. [2023-11-12 02:12:35,442 INFO L444 LassoAnalysis]: Proving nontermination failed: No geometric nontermination argument exists. [2023-11-12 02:12:35,446 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_13489a2e-8a24-4e25-8b20-2091353b9675/bin/uautomizer-verify-uTZkv6EMXl/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (3)] Forceful destruction successful, exit code 0 [2023-11-12 02:12:35,446 INFO L210 LassoAnalysis]: Preferences: [2023-11-12 02:12:35,447 INFO L126 ssoRankerPreferences]: Compute integeral hull: false [2023-11-12 02:12:35,447 INFO L127 ssoRankerPreferences]: Enable LassoPartitioneer: true [2023-11-12 02:12:35,447 INFO L128 ssoRankerPreferences]: Term annotations enabled: false [2023-11-12 02:12:35,447 INFO L129 ssoRankerPreferences]: Use exernal solver: false [2023-11-12 02:12:35,447 INFO L130 ssoRankerPreferences]: SMT solver command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2023-11-12 02:12:35,447 INFO L131 ssoRankerPreferences]: Dump SMT script to file: false [2023-11-12 02:12:35,448 INFO L132 ssoRankerPreferences]: Path of dumped script: [2023-11-12 02:12:35,448 INFO L133 ssoRankerPreferences]: Filename of dumped script: string_concat-noarr.i_Iteration1_Loop [2023-11-12 02:12:35,448 INFO L134 ssoRankerPreferences]: MapElimAlgo: Frank [2023-11-12 02:12:35,448 INFO L276 LassoAnalysis]: Starting lasso preprocessing... [2023-11-12 02:12:35,450 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-12 02:12:35,469 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-12 02:12:35,478 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-12 02:12:35,516 INFO L294 LassoAnalysis]: Preprocessing complete. [2023-11-12 02:12:35,522 INFO L490 LassoAnalysis]: Using template 'affine'. [2023-11-12 02:12:35,524 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2023-11-12 02:12:35,524 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_13489a2e-8a24-4e25-8b20-2091353b9675/bin/uautomizer-verify-uTZkv6EMXl/z3 [2023-11-12 02:12:35,526 INFO L229 MonitoredProcess]: Starting monitored process 4 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_13489a2e-8a24-4e25-8b20-2091353b9675/bin/uautomizer-verify-uTZkv6EMXl/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2023-11-12 02:12:35,541 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_13489a2e-8a24-4e25-8b20-2091353b9675/bin/uautomizer-verify-uTZkv6EMXl/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (4)] Waiting until timeout for monitored process [2023-11-12 02:12:35,545 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2023-11-12 02:12:35,559 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2023-11-12 02:12:35,560 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2023-11-12 02:12:35,560 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2023-11-12 02:12:35,561 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2023-11-12 02:12:35,561 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2023-11-12 02:12:35,564 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2023-11-12 02:12:35,565 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2023-11-12 02:12:35,584 INFO L420 nArgumentSynthesizer]: Found a termination argument, trying to simplify. [2023-11-12 02:12:35,598 INFO L443 ModelExtractionUtils]: Simplification made 3 calls to the SMT solver. [2023-11-12 02:12:35,598 INFO L444 ModelExtractionUtils]: 0 out of 3 variables were initially zero. Simplification set additionally 0 variables to zero. [2023-11-12 02:12:35,616 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2023-11-12 02:12:35,617 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_13489a2e-8a24-4e25-8b20-2091353b9675/bin/uautomizer-verify-uTZkv6EMXl/z3 [2023-11-12 02:12:35,664 INFO L229 MonitoredProcess]: Starting monitored process 5 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_13489a2e-8a24-4e25-8b20-2091353b9675/bin/uautomizer-verify-uTZkv6EMXl/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2023-11-12 02:12:35,669 INFO L435 nArgumentSynthesizer]: Simplifying supporting invariants... [2023-11-12 02:12:35,670 INFO L438 nArgumentSynthesizer]: Removed 0 redundant supporting invariants from a total of 0. [2023-11-12 02:12:35,670 INFO L513 LassoAnalysis]: Proved termination. [2023-11-12 02:12:35,671 INFO L515 LassoAnalysis]: Termination argument consisting of: Ranking function f(ULTIMATE.start_main_~i~0#1) = -2*ULTIMATE.start_main_~i~0#1 + 1999999 Supporting invariants [] [2023-11-12 02:12:35,674 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_13489a2e-8a24-4e25-8b20-2091353b9675/bin/uautomizer-verify-uTZkv6EMXl/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (5)] Waiting until timeout for monitored process [2023-11-12 02:12:35,684 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_13489a2e-8a24-4e25-8b20-2091353b9675/bin/uautomizer-verify-uTZkv6EMXl/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (4)] Forceful destruction successful, exit code 0 [2023-11-12 02:12:35,690 INFO L156 tatePredicateManager]: 0 out of 0 supporting invariants were superfluous and have been removed [2023-11-12 02:12:35,736 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-12 02:12:35,760 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_13489a2e-8a24-4e25-8b20-2091353b9675/bin/uautomizer-verify-uTZkv6EMXl/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (5)] Forceful destruction successful, exit code 0 [2023-11-12 02:12:35,785 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-12 02:12:35,790 INFO L262 TraceCheckSpWp]: Trace formula consists of 20 conjuncts, 2 conjunts are in the unsatisfiable core [2023-11-12 02:12:35,792 INFO L285 TraceCheckSpWp]: Computing forward predicates... [2023-11-12 02:12:35,830 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-12 02:12:35,832 WARN L260 TraceCheckSpWp]: Trace formula consists of 7 conjuncts, 4 conjunts are in the unsatisfiable core [2023-11-12 02:12:35,833 INFO L285 TraceCheckSpWp]: Computing forward predicates... [2023-11-12 02:12:35,841 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-12 02:12:35,900 INFO L141 lantAutomatonBouncer]: Defining deterministic Buchi interpolant automaton with honda bouncer for stem and without honda bouncer for loop.1 stem predicates 1 loop predicates [2023-11-12 02:12:35,906 INFO L71 iDifferenceNCSBLazy3]: Start buchiDifferenceNCSBLazy3. First operand has 18 states, 17 states have (on average 1.4705882352941178) internal successors, (25), 17 states have internal predecessors, (25), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand has 3 states, 3 states have (on average 1.6666666666666667) internal successors, (5), 3 states have internal predecessors, (5), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-12 02:12:36,017 INFO L75 iDifferenceNCSBLazy3]: Finished buchiDifferenceNCSBLazy3. First operand has 18 states, 17 states have (on average 1.4705882352941178) internal successors, (25), 17 states have internal predecessors, (25), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0). Second operand has 3 states, 3 states have (on average 1.6666666666666667) internal successors, (5), 3 states have internal predecessors, (5), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Result 44 states and 62 transitions. Complement of second has 6 states. [2023-11-12 02:12:36,019 INFO L141 InterpolantAutomaton]: Switched to read-only mode: Buchi interpolant automaton has 4 states 1 stem states 1 non-accepting loop states 1 accepting loop states [2023-11-12 02:12:36,032 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 3 states, 3 states have (on average 1.6666666666666667) internal successors, (5), 3 states have internal predecessors, (5), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-12 02:12:36,033 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 4 states to 4 states and 42 transitions. [2023-11-12 02:12:36,036 INFO L84 BuchiAccepts]: Start buchiAccepts Operand 4 states and 42 transitions. Stem has 3 letters. Loop has 2 letters. [2023-11-12 02:12:36,039 INFO L116 BuchiAccepts]: Finished buchiAccepts. [2023-11-12 02:12:36,039 INFO L84 BuchiAccepts]: Start buchiAccepts Operand 4 states and 42 transitions. Stem has 5 letters. Loop has 2 letters. [2023-11-12 02:12:36,040 INFO L116 BuchiAccepts]: Finished buchiAccepts. [2023-11-12 02:12:36,048 INFO L84 BuchiAccepts]: Start buchiAccepts Operand 4 states and 42 transitions. Stem has 3 letters. Loop has 4 letters. [2023-11-12 02:12:36,048 INFO L116 BuchiAccepts]: Finished buchiAccepts. [2023-11-12 02:12:36,049 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 44 states and 62 transitions. [2023-11-12 02:12:36,059 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1 [2023-11-12 02:12:36,064 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 44 states to 17 states and 22 transitions. [2023-11-12 02:12:36,066 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 9 [2023-11-12 02:12:36,066 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 11 [2023-11-12 02:12:36,067 INFO L73 IsDeterministic]: Start isDeterministic. Operand 17 states and 22 transitions. [2023-11-12 02:12:36,067 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2023-11-12 02:12:36,068 INFO L218 hiAutomatonCegarLoop]: Abstraction has 17 states and 22 transitions. [2023-11-12 02:12:36,090 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 17 states and 22 transitions. [2023-11-12 02:12:36,100 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 17 to 16. [2023-11-12 02:12:36,101 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 16 states, 16 states have (on average 1.3125) internal successors, (21), 15 states have internal predecessors, (21), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-12 02:12:36,103 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 16 states to 16 states and 21 transitions. [2023-11-12 02:12:36,105 INFO L240 hiAutomatonCegarLoop]: Abstraction has 16 states and 21 transitions. [2023-11-12 02:12:36,105 INFO L428 stractBuchiCegarLoop]: Abstraction has 16 states and 21 transitions. [2023-11-12 02:12:36,105 INFO L335 stractBuchiCegarLoop]: ======== Iteration 2 ============ [2023-11-12 02:12:36,105 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 16 states and 21 transitions. [2023-11-12 02:12:36,109 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1 [2023-11-12 02:12:36,110 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-12 02:12:36,110 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-12 02:12:36,110 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1] [2023-11-12 02:12:36,111 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1] [2023-11-12 02:12:36,111 INFO L748 eck$LassoCheckResult]: Stem: 105#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(9, 2); 106#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~post2#1, main_#t~nondet1#1, main_#t~post4#1, main_#t~post5#1, main_#t~nondet3#1, main_~i~0#1, main_~j~0#1;havoc main_~i~0#1;havoc main_~j~0#1; 112#L26 main_~i~0#1 := 0; 113#L29-2 havoc main_#t~nondet1#1; 107#L29 assume !(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1; 100#L29-3 assume main_~i~0#1 >= 100; 101#L32 [2023-11-12 02:12:36,111 INFO L750 eck$LassoCheckResult]: Loop: 101#L32 assume true; 101#L32 [2023-11-12 02:12:36,114 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-12 02:12:36,115 INFO L85 PathProgramCache]: Analyzing trace with hash 889478928, now seen corresponding path program 1 times [2023-11-12 02:12:36,115 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-12 02:12:36,115 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1709801396] [2023-11-12 02:12:36,116 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-12 02:12:36,117 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-12 02:12:36,144 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-12 02:12:36,243 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-12 02:12:36,244 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-12 02:12:36,245 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1709801396] [2023-11-12 02:12:36,247 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1709801396] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-12 02:12:36,247 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-12 02:12:36,248 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2023-11-12 02:12:36,248 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [772238888] [2023-11-12 02:12:36,250 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-12 02:12:36,253 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-12 02:12:36,254 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-12 02:12:36,254 INFO L85 PathProgramCache]: Analyzing trace with hash 93, now seen corresponding path program 1 times [2023-11-12 02:12:36,255 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-12 02:12:36,255 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [867056702] [2023-11-12 02:12:36,256 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-12 02:12:36,256 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-12 02:12:36,265 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-12 02:12:36,265 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-12 02:12:36,267 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-12 02:12:36,268 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-12 02:12:36,272 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-12 02:12:36,275 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-12 02:12:36,276 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-12 02:12:36,277 INFO L87 Difference]: Start difference. First operand 16 states and 21 transitions. cyclomatic complexity: 8 Second operand has 3 states, 2 states have (on average 3.0) internal successors, (6), 3 states have internal predecessors, (6), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-12 02:12:36,319 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-12 02:12:36,319 INFO L93 Difference]: Finished difference Result 26 states and 32 transitions. [2023-11-12 02:12:36,320 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 26 states and 32 transitions. [2023-11-12 02:12:36,324 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 2 [2023-11-12 02:12:36,326 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 26 states to 26 states and 32 transitions. [2023-11-12 02:12:36,326 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 16 [2023-11-12 02:12:36,326 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 16 [2023-11-12 02:12:36,327 INFO L73 IsDeterministic]: Start isDeterministic. Operand 26 states and 32 transitions. [2023-11-12 02:12:36,327 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2023-11-12 02:12:36,329 INFO L218 hiAutomatonCegarLoop]: Abstraction has 26 states and 32 transitions. [2023-11-12 02:12:36,330 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 26 states and 32 transitions. [2023-11-12 02:12:36,334 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 26 to 18. [2023-11-12 02:12:36,334 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 18 states, 18 states have (on average 1.2777777777777777) internal successors, (23), 17 states have internal predecessors, (23), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-12 02:12:36,341 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 18 states to 18 states and 23 transitions. [2023-11-12 02:12:36,341 INFO L240 hiAutomatonCegarLoop]: Abstraction has 18 states and 23 transitions. [2023-11-12 02:12:36,342 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-12 02:12:36,343 INFO L428 stractBuchiCegarLoop]: Abstraction has 18 states and 23 transitions. [2023-11-12 02:12:36,343 INFO L335 stractBuchiCegarLoop]: ======== Iteration 3 ============ [2023-11-12 02:12:36,344 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 18 states and 23 transitions. [2023-11-12 02:12:36,346 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1 [2023-11-12 02:12:36,346 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-12 02:12:36,347 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-12 02:12:36,347 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [2, 1, 1, 1, 1, 1, 1] [2023-11-12 02:12:36,348 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1] [2023-11-12 02:12:36,348 INFO L748 eck$LassoCheckResult]: Stem: 156#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(9, 2); 157#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~post2#1, main_#t~nondet1#1, main_#t~post4#1, main_#t~post5#1, main_#t~nondet3#1, main_~i~0#1, main_~j~0#1;havoc main_~i~0#1;havoc main_~j~0#1; 160#L26 main_~i~0#1 := 0; 161#L29-2 havoc main_#t~nondet1#1; 154#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 155#L29-2 havoc main_#t~nondet1#1; 152#L29 assume !(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1; 153#L29-3 assume main_~i~0#1 >= 100; 162#L32 [2023-11-12 02:12:36,348 INFO L750 eck$LassoCheckResult]: Loop: 162#L32 assume true; 162#L32 [2023-11-12 02:12:36,349 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-12 02:12:36,349 INFO L85 PathProgramCache]: Analyzing trace with hash 90807307, now seen corresponding path program 1 times [2023-11-12 02:12:36,349 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-12 02:12:36,350 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1487952290] [2023-11-12 02:12:36,350 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-12 02:12:36,350 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-12 02:12:36,371 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-12 02:12:36,449 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-12 02:12:36,450 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-12 02:12:36,450 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1487952290] [2023-11-12 02:12:36,450 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1487952290] provided 0 perfect and 1 imperfect interpolant sequences [2023-11-12 02:12:36,450 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1433585465] [2023-11-12 02:12:36,451 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-12 02:12:36,451 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2023-11-12 02:12:36,451 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_13489a2e-8a24-4e25-8b20-2091353b9675/bin/uautomizer-verify-uTZkv6EMXl/z3 [2023-11-12 02:12:36,453 INFO L229 MonitoredProcess]: Starting monitored process 6 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_13489a2e-8a24-4e25-8b20-2091353b9675/bin/uautomizer-verify-uTZkv6EMXl/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2023-11-12 02:12:36,470 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_13489a2e-8a24-4e25-8b20-2091353b9675/bin/uautomizer-verify-uTZkv6EMXl/z3 -smt2 -in SMTLIB2_COMPLIANT=true (6)] Waiting until timeout for monitored process [2023-11-12 02:12:36,503 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-12 02:12:36,504 INFO L262 TraceCheckSpWp]: Trace formula consists of 28 conjuncts, 3 conjunts are in the unsatisfiable core [2023-11-12 02:12:36,506 INFO L285 TraceCheckSpWp]: Computing forward predicates... [2023-11-12 02:12:36,532 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-12 02:12:36,532 INFO L327 TraceCheckSpWp]: Computing backward predicates... [2023-11-12 02:12:36,571 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-12 02:12:36,571 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1433585465] provided 0 perfect and 2 imperfect interpolant sequences [2023-11-12 02:12:36,571 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2023-11-12 02:12:36,572 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [3, 3, 3] total 6 [2023-11-12 02:12:36,572 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1162773446] [2023-11-12 02:12:36,572 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2023-11-12 02:12:36,573 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-12 02:12:36,574 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-12 02:12:36,574 INFO L85 PathProgramCache]: Analyzing trace with hash 93, now seen corresponding path program 2 times [2023-11-12 02:12:36,574 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-12 02:12:36,574 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1858717672] [2023-11-12 02:12:36,575 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-12 02:12:36,575 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-12 02:12:36,578 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-12 02:12:36,578 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-12 02:12:36,579 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-12 02:12:36,580 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-12 02:12:36,587 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-12 02:12:36,588 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 7 interpolants. [2023-11-12 02:12:36,588 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=21, Invalid=21, Unknown=0, NotChecked=0, Total=42 [2023-11-12 02:12:36,589 INFO L87 Difference]: Start difference. First operand 18 states and 23 transitions. cyclomatic complexity: 8 Second operand has 7 states, 6 states have (on average 2.8333333333333335) internal successors, (17), 7 states have internal predecessors, (17), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-12 02:12:36,658 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-12 02:12:36,658 INFO L93 Difference]: Finished difference Result 60 states and 75 transitions. [2023-11-12 02:12:36,658 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 60 states and 75 transitions. [2023-11-12 02:12:36,660 INFO L131 ngComponentsAnalysis]: Automaton has 5 accepting balls. 5 [2023-11-12 02:12:36,662 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 60 states to 60 states and 75 transitions. [2023-11-12 02:12:36,662 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 33 [2023-11-12 02:12:36,662 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 33 [2023-11-12 02:12:36,663 INFO L73 IsDeterministic]: Start isDeterministic. Operand 60 states and 75 transitions. [2023-11-12 02:12:36,663 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2023-11-12 02:12:36,663 INFO L218 hiAutomatonCegarLoop]: Abstraction has 60 states and 75 transitions. [2023-11-12 02:12:36,663 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 60 states and 75 transitions. [2023-11-12 02:12:36,666 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 60 to 24. [2023-11-12 02:12:36,667 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 24 states, 24 states have (on average 1.4583333333333333) internal successors, (35), 23 states have internal predecessors, (35), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-12 02:12:36,667 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 24 states to 24 states and 35 transitions. [2023-11-12 02:12:36,668 INFO L240 hiAutomatonCegarLoop]: Abstraction has 24 states and 35 transitions. [2023-11-12 02:12:36,668 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2023-11-12 02:12:36,669 INFO L428 stractBuchiCegarLoop]: Abstraction has 24 states and 35 transitions. [2023-11-12 02:12:36,670 INFO L335 stractBuchiCegarLoop]: ======== Iteration 4 ============ [2023-11-12 02:12:36,670 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 24 states and 35 transitions. [2023-11-12 02:12:36,671 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1 [2023-11-12 02:12:36,671 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-12 02:12:36,671 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-12 02:12:36,673 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-12 02:12:36,673 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1] [2023-11-12 02:12:36,674 INFO L748 eck$LassoCheckResult]: Stem: 285#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(9, 2); 286#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~post2#1, main_#t~nondet1#1, main_#t~post4#1, main_#t~post5#1, main_#t~nondet3#1, main_~i~0#1, main_~j~0#1;havoc main_~i~0#1;havoc main_~j~0#1; 289#L26 main_~i~0#1 := 0; 290#L29-2 havoc main_#t~nondet1#1; 282#L29 assume !(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1; 278#L29-3 assume !(main_~i~0#1 >= 100);main_~j~0#1 := 0; 279#L35-2 havoc main_#t~nondet3#1; 287#L35 assume !(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1; 292#L35-3 assume main_~j~0#1 >= 100; 291#L32 [2023-11-12 02:12:36,674 INFO L750 eck$LassoCheckResult]: Loop: 291#L32 assume true; 291#L32 [2023-11-12 02:12:36,674 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-12 02:12:36,675 INFO L85 PathProgramCache]: Analyzing trace with hash -1481354991, now seen corresponding path program 1 times [2023-11-12 02:12:36,675 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-12 02:12:36,675 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2055958977] [2023-11-12 02:12:36,676 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-12 02:12:36,676 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-12 02:12:36,684 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-12 02:12:36,728 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-12 02:12:36,728 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-12 02:12:36,729 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2055958977] [2023-11-12 02:12:36,729 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2055958977] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-12 02:12:36,729 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-12 02:12:36,729 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2023-11-12 02:12:36,730 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [171548528] [2023-11-12 02:12:36,730 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-12 02:12:36,730 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-12 02:12:36,731 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-12 02:12:36,731 INFO L85 PathProgramCache]: Analyzing trace with hash 93, now seen corresponding path program 3 times [2023-11-12 02:12:36,732 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-12 02:12:36,732 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1581556663] [2023-11-12 02:12:36,733 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-12 02:12:36,734 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-12 02:12:36,736 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-12 02:12:36,738 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-12 02:12:36,739 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-12 02:12:36,740 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-12 02:12:36,743 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-12 02:12:36,745 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-12 02:12:36,745 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-12 02:12:36,745 INFO L87 Difference]: Start difference. First operand 24 states and 35 transitions. cyclomatic complexity: 14 Second operand has 3 states, 2 states have (on average 4.5) internal successors, (9), 3 states have internal predecessors, (9), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-12 02:12:36,762 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-12 02:12:36,762 INFO L93 Difference]: Finished difference Result 27 states and 37 transitions. [2023-11-12 02:12:36,763 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 27 states and 37 transitions. [2023-11-12 02:12:36,765 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1 [2023-11-12 02:12:36,765 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 27 states to 22 states and 28 transitions. [2023-11-12 02:12:36,766 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 9 [2023-11-12 02:12:36,766 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 9 [2023-11-12 02:12:36,766 INFO L73 IsDeterministic]: Start isDeterministic. Operand 22 states and 28 transitions. [2023-11-12 02:12:36,766 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2023-11-12 02:12:36,766 INFO L218 hiAutomatonCegarLoop]: Abstraction has 22 states and 28 transitions. [2023-11-12 02:12:36,767 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 22 states and 28 transitions. [2023-11-12 02:12:36,769 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 22 to 21. [2023-11-12 02:12:36,770 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 21 states, 21 states have (on average 1.2857142857142858) internal successors, (27), 20 states have internal predecessors, (27), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-12 02:12:36,770 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 21 states to 21 states and 27 transitions. [2023-11-12 02:12:36,770 INFO L240 hiAutomatonCegarLoop]: Abstraction has 21 states and 27 transitions. [2023-11-12 02:12:36,771 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-12 02:12:36,773 INFO L428 stractBuchiCegarLoop]: Abstraction has 21 states and 27 transitions. [2023-11-12 02:12:36,773 INFO L335 stractBuchiCegarLoop]: ======== Iteration 5 ============ [2023-11-12 02:12:36,773 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 21 states and 27 transitions. [2023-11-12 02:12:36,774 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1 [2023-11-12 02:12:36,774 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-12 02:12:36,775 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-12 02:12:36,776 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [2, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-12 02:12:36,776 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1] [2023-11-12 02:12:36,777 INFO L748 eck$LassoCheckResult]: Stem: 342#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(9, 2); 343#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~post2#1, main_#t~nondet1#1, main_#t~post4#1, main_#t~post5#1, main_#t~nondet3#1, main_~i~0#1, main_~j~0#1;havoc main_~i~0#1;havoc main_~j~0#1; 345#L26 main_~i~0#1 := 0; 346#L29-2 havoc main_#t~nondet1#1; 340#L29 assume !(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1; 337#L29-3 assume !(main_~i~0#1 >= 100);main_~j~0#1 := 0; 338#L35-2 havoc main_#t~nondet3#1; 344#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 349#L35-2 havoc main_#t~nondet3#1; 348#L35 assume !(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1; 347#L35-3 assume main_~j~0#1 >= 100; 336#L32 [2023-11-12 02:12:36,777 INFO L750 eck$LassoCheckResult]: Loop: 336#L32 assume true; 336#L32 [2023-11-12 02:12:36,778 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-12 02:12:36,778 INFO L85 PathProgramCache]: Analyzing trace with hash -1947921364, now seen corresponding path program 1 times [2023-11-12 02:12:36,778 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-12 02:12:36,779 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [642433321] [2023-11-12 02:12:36,779 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-12 02:12:36,780 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-12 02:12:36,791 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-12 02:12:36,879 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-12 02:12:36,879 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-12 02:12:36,880 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [642433321] [2023-11-12 02:12:36,880 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [642433321] provided 0 perfect and 1 imperfect interpolant sequences [2023-11-12 02:12:36,881 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [196943135] [2023-11-12 02:12:36,881 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-12 02:12:36,882 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2023-11-12 02:12:36,882 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_13489a2e-8a24-4e25-8b20-2091353b9675/bin/uautomizer-verify-uTZkv6EMXl/z3 [2023-11-12 02:12:36,883 INFO L229 MonitoredProcess]: Starting monitored process 7 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_13489a2e-8a24-4e25-8b20-2091353b9675/bin/uautomizer-verify-uTZkv6EMXl/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2023-11-12 02:12:36,912 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_13489a2e-8a24-4e25-8b20-2091353b9675/bin/uautomizer-verify-uTZkv6EMXl/z3 -smt2 -in SMTLIB2_COMPLIANT=true (7)] Waiting until timeout for monitored process [2023-11-12 02:12:36,962 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-12 02:12:36,963 INFO L262 TraceCheckSpWp]: Trace formula consists of 35 conjuncts, 3 conjunts are in the unsatisfiable core [2023-11-12 02:12:36,965 INFO L285 TraceCheckSpWp]: Computing forward predicates... [2023-11-12 02:12:36,996 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-12 02:12:36,996 INFO L327 TraceCheckSpWp]: Computing backward predicates... [2023-11-12 02:12:37,035 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-12 02:12:37,036 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [196943135] provided 0 perfect and 2 imperfect interpolant sequences [2023-11-12 02:12:37,036 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2023-11-12 02:12:37,036 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [3, 3, 3] total 6 [2023-11-12 02:12:37,037 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [111776074] [2023-11-12 02:12:37,037 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2023-11-12 02:12:37,038 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-12 02:12:37,038 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-12 02:12:37,039 INFO L85 PathProgramCache]: Analyzing trace with hash 93, now seen corresponding path program 4 times [2023-11-12 02:12:37,039 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-12 02:12:37,039 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1304889266] [2023-11-12 02:12:37,039 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-12 02:12:37,040 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-12 02:12:37,044 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-12 02:12:37,044 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-12 02:12:37,047 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-12 02:12:37,047 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-12 02:12:37,051 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-12 02:12:37,051 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 7 interpolants. [2023-11-12 02:12:37,052 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=21, Invalid=21, Unknown=0, NotChecked=0, Total=42 [2023-11-12 02:12:37,052 INFO L87 Difference]: Start difference. First operand 21 states and 27 transitions. cyclomatic complexity: 9 Second operand has 7 states, 6 states have (on average 3.3333333333333335) internal successors, (20), 7 states have internal predecessors, (20), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-12 02:12:37,074 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-12 02:12:37,074 INFO L93 Difference]: Finished difference Result 34 states and 40 transitions. [2023-11-12 02:12:37,074 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 34 states and 40 transitions. [2023-11-12 02:12:37,076 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1 [2023-11-12 02:12:37,078 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 34 states to 28 states and 34 transitions. [2023-11-12 02:12:37,079 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 9 [2023-11-12 02:12:37,079 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 9 [2023-11-12 02:12:37,079 INFO L73 IsDeterministic]: Start isDeterministic. Operand 28 states and 34 transitions. [2023-11-12 02:12:37,079 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2023-11-12 02:12:37,080 INFO L218 hiAutomatonCegarLoop]: Abstraction has 28 states and 34 transitions. [2023-11-12 02:12:37,080 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 28 states and 34 transitions. [2023-11-12 02:12:37,083 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 28 to 27. [2023-11-12 02:12:37,084 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 27 states, 27 states have (on average 1.2222222222222223) internal successors, (33), 26 states have internal predecessors, (33), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-12 02:12:37,085 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 27 states to 27 states and 33 transitions. [2023-11-12 02:12:37,085 INFO L240 hiAutomatonCegarLoop]: Abstraction has 27 states and 33 transitions. [2023-11-12 02:12:37,086 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2023-11-12 02:12:37,089 INFO L428 stractBuchiCegarLoop]: Abstraction has 27 states and 33 transitions. [2023-11-12 02:12:37,089 INFO L335 stractBuchiCegarLoop]: ======== Iteration 6 ============ [2023-11-12 02:12:37,089 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 27 states and 33 transitions. [2023-11-12 02:12:37,090 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1 [2023-11-12 02:12:37,090 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-12 02:12:37,090 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-12 02:12:37,091 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [5, 4, 1, 1, 1, 1, 1] [2023-11-12 02:12:37,092 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1] [2023-11-12 02:12:37,092 INFO L748 eck$LassoCheckResult]: Stem: 467#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(9, 2); 468#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~post2#1, main_#t~nondet1#1, main_#t~post4#1, main_#t~post5#1, main_#t~nondet3#1, main_~i~0#1, main_~j~0#1;havoc main_~i~0#1;havoc main_~j~0#1; 470#L26 main_~i~0#1 := 0; 471#L29-2 havoc main_#t~nondet1#1; 465#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 466#L29-2 havoc main_#t~nondet1#1; 475#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 482#L29-2 havoc main_#t~nondet1#1; 481#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 480#L29-2 havoc main_#t~nondet1#1; 479#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 478#L29-2 havoc main_#t~nondet1#1; 464#L29 assume !(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1; 460#L29-3 assume main_~i~0#1 >= 100; 461#L32 [2023-11-12 02:12:37,092 INFO L750 eck$LassoCheckResult]: Loop: 461#L32 assume true; 461#L32 [2023-11-12 02:12:37,093 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-12 02:12:37,093 INFO L85 PathProgramCache]: Analyzing trace with hash -957341060, now seen corresponding path program 2 times [2023-11-12 02:12:37,093 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-12 02:12:37,094 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1358936005] [2023-11-12 02:12:37,094 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-12 02:12:37,094 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-12 02:12:37,124 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-12 02:12:37,274 INFO L134 CoverageAnalysis]: Checked inductivity of 20 backedges. 0 proven. 20 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-12 02:12:37,275 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-12 02:12:37,275 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1358936005] [2023-11-12 02:12:37,276 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1358936005] provided 0 perfect and 1 imperfect interpolant sequences [2023-11-12 02:12:37,276 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [2115478017] [2023-11-12 02:12:37,276 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2023-11-12 02:12:37,276 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2023-11-12 02:12:37,277 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_13489a2e-8a24-4e25-8b20-2091353b9675/bin/uautomizer-verify-uTZkv6EMXl/z3 [2023-11-12 02:12:37,284 INFO L229 MonitoredProcess]: Starting monitored process 8 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_13489a2e-8a24-4e25-8b20-2091353b9675/bin/uautomizer-verify-uTZkv6EMXl/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2023-11-12 02:12:37,312 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_13489a2e-8a24-4e25-8b20-2091353b9675/bin/uautomizer-verify-uTZkv6EMXl/z3 -smt2 -in SMTLIB2_COMPLIANT=true (8)] Waiting until timeout for monitored process [2023-11-12 02:12:37,350 INFO L228 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2023-11-12 02:12:37,350 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2023-11-12 02:12:37,351 INFO L262 TraceCheckSpWp]: Trace formula consists of 43 conjuncts, 6 conjunts are in the unsatisfiable core [2023-11-12 02:12:37,353 INFO L285 TraceCheckSpWp]: Computing forward predicates... [2023-11-12 02:12:37,411 INFO L134 CoverageAnalysis]: Checked inductivity of 20 backedges. 0 proven. 20 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-12 02:12:37,411 INFO L327 TraceCheckSpWp]: Computing backward predicates... [2023-11-12 02:12:37,526 INFO L134 CoverageAnalysis]: Checked inductivity of 20 backedges. 0 proven. 20 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-12 02:12:37,527 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [2115478017] provided 0 perfect and 2 imperfect interpolant sequences [2023-11-12 02:12:37,527 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2023-11-12 02:12:37,527 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [6, 6, 6] total 12 [2023-11-12 02:12:37,527 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1255278165] [2023-11-12 02:12:37,528 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2023-11-12 02:12:37,528 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-12 02:12:37,529 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-12 02:12:37,529 INFO L85 PathProgramCache]: Analyzing trace with hash 93, now seen corresponding path program 5 times [2023-11-12 02:12:37,529 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-12 02:12:37,529 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1610867662] [2023-11-12 02:12:37,530 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-12 02:12:37,530 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-12 02:12:37,532 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-12 02:12:37,533 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-12 02:12:37,534 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-12 02:12:37,534 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-12 02:12:37,537 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-12 02:12:37,538 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 13 interpolants. [2023-11-12 02:12:37,538 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=78, Invalid=78, Unknown=0, NotChecked=0, Total=156 [2023-11-12 02:12:37,539 INFO L87 Difference]: Start difference. First operand 27 states and 33 transitions. cyclomatic complexity: 9 Second operand has 13 states, 12 states have (on average 2.4166666666666665) internal successors, (29), 13 states have internal predecessors, (29), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-12 02:12:37,677 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-12 02:12:37,677 INFO L93 Difference]: Finished difference Result 152 states and 171 transitions. [2023-11-12 02:12:37,677 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 152 states and 171 transitions. [2023-11-12 02:12:37,680 INFO L131 ngComponentsAnalysis]: Automaton has 7 accepting balls. 7 [2023-11-12 02:12:37,682 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 152 states to 140 states and 159 transitions. [2023-11-12 02:12:37,682 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 27 [2023-11-12 02:12:37,682 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 27 [2023-11-12 02:12:37,682 INFO L73 IsDeterministic]: Start isDeterministic. Operand 140 states and 159 transitions. [2023-11-12 02:12:37,683 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2023-11-12 02:12:37,683 INFO L218 hiAutomatonCegarLoop]: Abstraction has 140 states and 159 transitions. [2023-11-12 02:12:37,683 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 140 states and 159 transitions. [2023-11-12 02:12:37,689 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 140 to 39. [2023-11-12 02:12:37,690 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 39 states, 39 states have (on average 1.3076923076923077) internal successors, (51), 38 states have internal predecessors, (51), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-12 02:12:37,690 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 39 states to 39 states and 51 transitions. [2023-11-12 02:12:37,691 INFO L240 hiAutomatonCegarLoop]: Abstraction has 39 states and 51 transitions. [2023-11-12 02:12:37,692 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 12 states. [2023-11-12 02:12:37,693 INFO L428 stractBuchiCegarLoop]: Abstraction has 39 states and 51 transitions. [2023-11-12 02:12:37,693 INFO L335 stractBuchiCegarLoop]: ======== Iteration 7 ============ [2023-11-12 02:12:37,694 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 39 states and 51 transitions. [2023-11-12 02:12:37,694 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1 [2023-11-12 02:12:37,694 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-12 02:12:37,695 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-12 02:12:37,695 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [5, 4, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-12 02:12:37,695 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1] [2023-11-12 02:12:37,696 INFO L748 eck$LassoCheckResult]: Stem: 737#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(9, 2); 738#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~post2#1, main_#t~nondet1#1, main_#t~post4#1, main_#t~post5#1, main_#t~nondet3#1, main_~i~0#1, main_~j~0#1;havoc main_~i~0#1;havoc main_~j~0#1; 743#L26 main_~i~0#1 := 0; 744#L29-2 havoc main_#t~nondet1#1; 746#L29 assume !(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1; 735#L29-3 assume !(main_~i~0#1 >= 100);main_~j~0#1 := 0; 736#L35-2 havoc main_#t~nondet3#1; 742#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 749#L35-2 havoc main_#t~nondet3#1; 771#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 770#L35-2 havoc main_#t~nondet3#1; 769#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 768#L35-2 havoc main_#t~nondet3#1; 767#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 766#L35-2 havoc main_#t~nondet3#1; 748#L35 assume !(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1; 745#L35-3 assume main_~j~0#1 >= 100; 734#L32 [2023-11-12 02:12:37,696 INFO L750 eck$LassoCheckResult]: Loop: 734#L32 assume true; 734#L32 [2023-11-12 02:12:37,696 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-12 02:12:37,696 INFO L85 PathProgramCache]: Analyzing trace with hash 606076157, now seen corresponding path program 2 times [2023-11-12 02:12:37,697 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-12 02:12:37,697 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1077844662] [2023-11-12 02:12:37,697 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-12 02:12:37,697 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-12 02:12:37,706 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-12 02:12:37,776 INFO L134 CoverageAnalysis]: Checked inductivity of 20 backedges. 0 proven. 20 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-12 02:12:37,776 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-12 02:12:37,777 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1077844662] [2023-11-12 02:12:37,777 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1077844662] provided 0 perfect and 1 imperfect interpolant sequences [2023-11-12 02:12:37,777 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1379248609] [2023-11-12 02:12:37,777 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2023-11-12 02:12:37,777 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2023-11-12 02:12:37,778 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_13489a2e-8a24-4e25-8b20-2091353b9675/bin/uautomizer-verify-uTZkv6EMXl/z3 [2023-11-12 02:12:37,781 INFO L229 MonitoredProcess]: Starting monitored process 9 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_13489a2e-8a24-4e25-8b20-2091353b9675/bin/uautomizer-verify-uTZkv6EMXl/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2023-11-12 02:12:37,796 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_13489a2e-8a24-4e25-8b20-2091353b9675/bin/uautomizer-verify-uTZkv6EMXl/z3 -smt2 -in SMTLIB2_COMPLIANT=true (9)] Waiting until timeout for monitored process [2023-11-12 02:12:37,833 INFO L228 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2023-11-12 02:12:37,833 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2023-11-12 02:12:37,834 INFO L262 TraceCheckSpWp]: Trace formula consists of 56 conjuncts, 6 conjunts are in the unsatisfiable core [2023-11-12 02:12:37,836 INFO L285 TraceCheckSpWp]: Computing forward predicates... [2023-11-12 02:12:37,876 INFO L134 CoverageAnalysis]: Checked inductivity of 20 backedges. 0 proven. 20 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-12 02:12:37,876 INFO L327 TraceCheckSpWp]: Computing backward predicates... [2023-11-12 02:12:37,968 INFO L134 CoverageAnalysis]: Checked inductivity of 20 backedges. 0 proven. 20 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-12 02:12:37,968 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1379248609] provided 0 perfect and 2 imperfect interpolant sequences [2023-11-12 02:12:37,968 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2023-11-12 02:12:37,968 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [6, 6, 6] total 12 [2023-11-12 02:12:37,972 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [268487558] [2023-11-12 02:12:37,972 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2023-11-12 02:12:37,972 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-12 02:12:37,973 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-12 02:12:37,973 INFO L85 PathProgramCache]: Analyzing trace with hash 93, now seen corresponding path program 6 times [2023-11-12 02:12:37,973 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-12 02:12:37,973 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1577913768] [2023-11-12 02:12:37,973 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-12 02:12:37,973 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-12 02:12:37,975 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-12 02:12:37,976 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-12 02:12:37,976 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-12 02:12:37,977 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-12 02:12:37,985 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-12 02:12:37,985 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 13 interpolants. [2023-11-12 02:12:37,986 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=78, Invalid=78, Unknown=0, NotChecked=0, Total=156 [2023-11-12 02:12:37,989 INFO L87 Difference]: Start difference. First operand 39 states and 51 transitions. cyclomatic complexity: 15 Second operand has 13 states, 12 states have (on average 2.6666666666666665) internal successors, (32), 13 states have internal predecessors, (32), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-12 02:12:38,030 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-12 02:12:38,030 INFO L93 Difference]: Finished difference Result 64 states and 76 transitions. [2023-11-12 02:12:38,030 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 64 states and 76 transitions. [2023-11-12 02:12:38,033 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1 [2023-11-12 02:12:38,036 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 64 states to 52 states and 64 transitions. [2023-11-12 02:12:38,036 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 9 [2023-11-12 02:12:38,036 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 9 [2023-11-12 02:12:38,036 INFO L73 IsDeterministic]: Start isDeterministic. Operand 52 states and 64 transitions. [2023-11-12 02:12:38,037 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2023-11-12 02:12:38,037 INFO L218 hiAutomatonCegarLoop]: Abstraction has 52 states and 64 transitions. [2023-11-12 02:12:38,038 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 52 states and 64 transitions. [2023-11-12 02:12:38,046 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 52 to 51. [2023-11-12 02:12:38,047 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 51 states, 51 states have (on average 1.2352941176470589) internal successors, (63), 50 states have internal predecessors, (63), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-12 02:12:38,052 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 51 states to 51 states and 63 transitions. [2023-11-12 02:12:38,052 INFO L240 hiAutomatonCegarLoop]: Abstraction has 51 states and 63 transitions. [2023-11-12 02:12:38,053 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 12 states. [2023-11-12 02:12:38,054 INFO L428 stractBuchiCegarLoop]: Abstraction has 51 states and 63 transitions. [2023-11-12 02:12:38,055 INFO L335 stractBuchiCegarLoop]: ======== Iteration 8 ============ [2023-11-12 02:12:38,055 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 51 states and 63 transitions. [2023-11-12 02:12:38,055 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1 [2023-11-12 02:12:38,056 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-12 02:12:38,056 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-12 02:12:38,057 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [11, 10, 1, 1, 1, 1, 1] [2023-11-12 02:12:38,057 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1] [2023-11-12 02:12:38,057 INFO L748 eck$LassoCheckResult]: Stem: 955#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(9, 2); 956#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~post2#1, main_#t~nondet1#1, main_#t~post4#1, main_#t~post5#1, main_#t~nondet3#1, main_~i~0#1, main_~j~0#1;havoc main_~i~0#1;havoc main_~j~0#1; 959#L26 main_~i~0#1 := 0; 960#L29-2 havoc main_#t~nondet1#1; 953#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 954#L29-2 havoc main_#t~nondet1#1; 964#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 983#L29-2 havoc main_#t~nondet1#1; 982#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 981#L29-2 havoc main_#t~nondet1#1; 980#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 979#L29-2 havoc main_#t~nondet1#1; 978#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 977#L29-2 havoc main_#t~nondet1#1; 976#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 975#L29-2 havoc main_#t~nondet1#1; 974#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 973#L29-2 havoc main_#t~nondet1#1; 972#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 971#L29-2 havoc main_#t~nondet1#1; 970#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 969#L29-2 havoc main_#t~nondet1#1; 968#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 967#L29-2 havoc main_#t~nondet1#1; 952#L29 assume !(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1; 948#L29-3 assume main_~i~0#1 >= 100; 949#L32 [2023-11-12 02:12:38,057 INFO L750 eck$LassoCheckResult]: Loop: 949#L32 assume true; 949#L32 [2023-11-12 02:12:38,058 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-12 02:12:38,058 INFO L85 PathProgramCache]: Analyzing trace with hash 777893150, now seen corresponding path program 3 times [2023-11-12 02:12:38,058 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-12 02:12:38,058 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1060814109] [2023-11-12 02:12:38,058 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-12 02:12:38,059 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-12 02:12:38,087 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-12 02:12:38,275 INFO L134 CoverageAnalysis]: Checked inductivity of 110 backedges. 0 proven. 110 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-12 02:12:38,275 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-12 02:12:38,275 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1060814109] [2023-11-12 02:12:38,275 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1060814109] provided 0 perfect and 1 imperfect interpolant sequences [2023-11-12 02:12:38,276 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [101325581] [2023-11-12 02:12:38,276 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 [2023-11-12 02:12:38,276 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2023-11-12 02:12:38,276 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_13489a2e-8a24-4e25-8b20-2091353b9675/bin/uautomizer-verify-uTZkv6EMXl/z3 [2023-11-12 02:12:38,280 INFO L229 MonitoredProcess]: Starting monitored process 10 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_13489a2e-8a24-4e25-8b20-2091353b9675/bin/uautomizer-verify-uTZkv6EMXl/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2023-11-12 02:12:38,293 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_13489a2e-8a24-4e25-8b20-2091353b9675/bin/uautomizer-verify-uTZkv6EMXl/z3 -smt2 -in SMTLIB2_COMPLIANT=true (10)] Waiting until timeout for monitored process [2023-11-12 02:12:38,345 INFO L228 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 11 check-sat command(s) [2023-11-12 02:12:38,345 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2023-11-12 02:12:38,346 INFO L262 TraceCheckSpWp]: Trace formula consists of 73 conjuncts, 12 conjunts are in the unsatisfiable core [2023-11-12 02:12:38,348 INFO L285 TraceCheckSpWp]: Computing forward predicates... [2023-11-12 02:12:38,425 INFO L134 CoverageAnalysis]: Checked inductivity of 110 backedges. 0 proven. 110 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-12 02:12:38,425 INFO L327 TraceCheckSpWp]: Computing backward predicates... [2023-11-12 02:12:38,710 INFO L134 CoverageAnalysis]: Checked inductivity of 110 backedges. 0 proven. 110 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-12 02:12:38,710 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [101325581] provided 0 perfect and 2 imperfect interpolant sequences [2023-11-12 02:12:38,710 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2023-11-12 02:12:38,710 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [12, 12, 12] total 24 [2023-11-12 02:12:38,711 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [437892248] [2023-11-12 02:12:38,711 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2023-11-12 02:12:38,711 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-12 02:12:38,712 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-12 02:12:38,712 INFO L85 PathProgramCache]: Analyzing trace with hash 93, now seen corresponding path program 7 times [2023-11-12 02:12:38,712 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-12 02:12:38,712 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [597869321] [2023-11-12 02:12:38,712 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-12 02:12:38,712 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-12 02:12:38,714 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-12 02:12:38,714 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-12 02:12:38,715 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-12 02:12:38,715 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-12 02:12:38,718 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-12 02:12:38,719 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 25 interpolants. [2023-11-12 02:12:38,719 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=300, Invalid=300, Unknown=0, NotChecked=0, Total=600 [2023-11-12 02:12:38,719 INFO L87 Difference]: Start difference. First operand 51 states and 63 transitions. cyclomatic complexity: 15 Second operand has 25 states, 24 states have (on average 2.2083333333333335) internal successors, (53), 25 states have internal predecessors, (53), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-12 02:12:38,959 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-12 02:12:38,959 INFO L93 Difference]: Finished difference Result 518 states and 555 transitions. [2023-11-12 02:12:38,959 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 518 states and 555 transitions. [2023-11-12 02:12:38,964 INFO L131 ngComponentsAnalysis]: Automaton has 13 accepting balls. 13 [2023-11-12 02:12:38,969 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 518 states to 494 states and 531 transitions. [2023-11-12 02:12:38,969 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 45 [2023-11-12 02:12:38,969 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 45 [2023-11-12 02:12:38,969 INFO L73 IsDeterministic]: Start isDeterministic. Operand 494 states and 531 transitions. [2023-11-12 02:12:38,970 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2023-11-12 02:12:38,971 INFO L218 hiAutomatonCegarLoop]: Abstraction has 494 states and 531 transitions. [2023-11-12 02:12:38,971 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 494 states and 531 transitions. [2023-11-12 02:12:38,977 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 494 to 75. [2023-11-12 02:12:38,978 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 75 states, 75 states have (on average 1.32) internal successors, (99), 74 states have internal predecessors, (99), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-12 02:12:38,978 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 75 states to 75 states and 99 transitions. [2023-11-12 02:12:38,979 INFO L240 hiAutomatonCegarLoop]: Abstraction has 75 states and 99 transitions. [2023-11-12 02:12:38,979 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 24 states. [2023-11-12 02:12:38,980 INFO L428 stractBuchiCegarLoop]: Abstraction has 75 states and 99 transitions. [2023-11-12 02:12:38,980 INFO L335 stractBuchiCegarLoop]: ======== Iteration 9 ============ [2023-11-12 02:12:38,980 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 75 states and 99 transitions. [2023-11-12 02:12:38,981 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1 [2023-11-12 02:12:38,981 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-12 02:12:38,981 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-12 02:12:38,982 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [11, 10, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-12 02:12:38,982 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1] [2023-11-12 02:12:38,982 INFO L748 eck$LassoCheckResult]: Stem: 1699#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(9, 2); 1700#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~post2#1, main_#t~nondet1#1, main_#t~post4#1, main_#t~post5#1, main_#t~nondet3#1, main_~i~0#1, main_~j~0#1;havoc main_~i~0#1;havoc main_~j~0#1; 1705#L26 main_~i~0#1 := 0; 1706#L29-2 havoc main_#t~nondet1#1; 1708#L29 assume !(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1; 1697#L29-3 assume !(main_~i~0#1 >= 100);main_~j~0#1 := 0; 1698#L35-2 havoc main_#t~nondet3#1; 1704#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 1711#L35-2 havoc main_#t~nondet3#1; 1769#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 1768#L35-2 havoc main_#t~nondet3#1; 1767#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 1766#L35-2 havoc main_#t~nondet3#1; 1765#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 1764#L35-2 havoc main_#t~nondet3#1; 1763#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 1762#L35-2 havoc main_#t~nondet3#1; 1761#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 1760#L35-2 havoc main_#t~nondet3#1; 1759#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 1758#L35-2 havoc main_#t~nondet3#1; 1757#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 1756#L35-2 havoc main_#t~nondet3#1; 1755#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 1754#L35-2 havoc main_#t~nondet3#1; 1753#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 1752#L35-2 havoc main_#t~nondet3#1; 1710#L35 assume !(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1; 1707#L35-3 assume main_~j~0#1 >= 100; 1696#L32 [2023-11-12 02:12:38,982 INFO L750 eck$LassoCheckResult]: Loop: 1696#L32 assume true; 1696#L32 [2023-11-12 02:12:38,983 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-12 02:12:38,983 INFO L85 PathProgramCache]: Analyzing trace with hash -2036695969, now seen corresponding path program 3 times [2023-11-12 02:12:38,983 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-12 02:12:38,983 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [110770260] [2023-11-12 02:12:38,983 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-12 02:12:38,984 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-12 02:12:38,996 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-12 02:12:39,183 INFO L134 CoverageAnalysis]: Checked inductivity of 110 backedges. 0 proven. 110 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-12 02:12:39,183 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-12 02:12:39,183 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [110770260] [2023-11-12 02:12:39,184 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [110770260] provided 0 perfect and 1 imperfect interpolant sequences [2023-11-12 02:12:39,184 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [703919678] [2023-11-12 02:12:39,184 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 [2023-11-12 02:12:39,184 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2023-11-12 02:12:39,184 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_13489a2e-8a24-4e25-8b20-2091353b9675/bin/uautomizer-verify-uTZkv6EMXl/z3 [2023-11-12 02:12:39,188 INFO L229 MonitoredProcess]: Starting monitored process 11 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_13489a2e-8a24-4e25-8b20-2091353b9675/bin/uautomizer-verify-uTZkv6EMXl/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2023-11-12 02:12:39,216 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_13489a2e-8a24-4e25-8b20-2091353b9675/bin/uautomizer-verify-uTZkv6EMXl/z3 -smt2 -in SMTLIB2_COMPLIANT=true (11)] Waiting until timeout for monitored process [2023-11-12 02:12:39,257 INFO L228 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 11 check-sat command(s) [2023-11-12 02:12:39,257 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2023-11-12 02:12:39,258 INFO L262 TraceCheckSpWp]: Trace formula consists of 98 conjuncts, 12 conjunts are in the unsatisfiable core [2023-11-12 02:12:39,260 INFO L285 TraceCheckSpWp]: Computing forward predicates... [2023-11-12 02:12:39,319 INFO L134 CoverageAnalysis]: Checked inductivity of 110 backedges. 0 proven. 110 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-12 02:12:39,320 INFO L327 TraceCheckSpWp]: Computing backward predicates... [2023-11-12 02:12:39,562 INFO L134 CoverageAnalysis]: Checked inductivity of 110 backedges. 0 proven. 110 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-12 02:12:39,562 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [703919678] provided 0 perfect and 2 imperfect interpolant sequences [2023-11-12 02:12:39,562 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2023-11-12 02:12:39,562 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [12, 12, 12] total 24 [2023-11-12 02:12:39,562 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [64626598] [2023-11-12 02:12:39,563 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2023-11-12 02:12:39,563 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-12 02:12:39,563 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-12 02:12:39,563 INFO L85 PathProgramCache]: Analyzing trace with hash 93, now seen corresponding path program 8 times [2023-11-12 02:12:39,564 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-12 02:12:39,564 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [130782163] [2023-11-12 02:12:39,564 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-12 02:12:39,564 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-12 02:12:39,565 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-12 02:12:39,566 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-12 02:12:39,566 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-12 02:12:39,566 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-12 02:12:39,570 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-12 02:12:39,571 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 25 interpolants. [2023-11-12 02:12:39,571 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=300, Invalid=300, Unknown=0, NotChecked=0, Total=600 [2023-11-12 02:12:39,572 INFO L87 Difference]: Start difference. First operand 75 states and 99 transitions. cyclomatic complexity: 27 Second operand has 25 states, 24 states have (on average 2.3333333333333335) internal successors, (56), 25 states have internal predecessors, (56), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-12 02:12:39,616 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-12 02:12:39,616 INFO L93 Difference]: Finished difference Result 124 states and 148 transitions. [2023-11-12 02:12:39,616 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 124 states and 148 transitions. [2023-11-12 02:12:39,618 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1 [2023-11-12 02:12:39,619 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 124 states to 100 states and 124 transitions. [2023-11-12 02:12:39,619 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 9 [2023-11-12 02:12:39,619 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 9 [2023-11-12 02:12:39,619 INFO L73 IsDeterministic]: Start isDeterministic. Operand 100 states and 124 transitions. [2023-11-12 02:12:39,619 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2023-11-12 02:12:39,619 INFO L218 hiAutomatonCegarLoop]: Abstraction has 100 states and 124 transitions. [2023-11-12 02:12:39,619 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 100 states and 124 transitions. [2023-11-12 02:12:39,623 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 100 to 99. [2023-11-12 02:12:39,623 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 99 states, 99 states have (on average 1.2424242424242424) internal successors, (123), 98 states have internal predecessors, (123), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-12 02:12:39,624 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 99 states to 99 states and 123 transitions. [2023-11-12 02:12:39,624 INFO L240 hiAutomatonCegarLoop]: Abstraction has 99 states and 123 transitions. [2023-11-12 02:12:39,628 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 24 states. [2023-11-12 02:12:39,629 INFO L428 stractBuchiCegarLoop]: Abstraction has 99 states and 123 transitions. [2023-11-12 02:12:39,630 INFO L335 stractBuchiCegarLoop]: ======== Iteration 10 ============ [2023-11-12 02:12:39,630 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 99 states and 123 transitions. [2023-11-12 02:12:39,631 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1 [2023-11-12 02:12:39,631 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-12 02:12:39,631 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-12 02:12:39,634 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [23, 22, 1, 1, 1, 1, 1] [2023-11-12 02:12:39,634 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1] [2023-11-12 02:12:39,636 INFO L748 eck$LassoCheckResult]: Stem: 2097#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(9, 2); 2098#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~post2#1, main_#t~nondet1#1, main_#t~post4#1, main_#t~post5#1, main_#t~nondet3#1, main_~i~0#1, main_~j~0#1;havoc main_~i~0#1;havoc main_~j~0#1; 2101#L26 main_~i~0#1 := 0; 2102#L29-2 havoc main_#t~nondet1#1; 2095#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 2096#L29-2 havoc main_#t~nondet1#1; 2106#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 2149#L29-2 havoc main_#t~nondet1#1; 2148#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 2147#L29-2 havoc main_#t~nondet1#1; 2146#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 2145#L29-2 havoc main_#t~nondet1#1; 2144#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 2143#L29-2 havoc main_#t~nondet1#1; 2142#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 2141#L29-2 havoc main_#t~nondet1#1; 2140#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 2139#L29-2 havoc main_#t~nondet1#1; 2138#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 2137#L29-2 havoc main_#t~nondet1#1; 2136#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 2135#L29-2 havoc main_#t~nondet1#1; 2134#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 2133#L29-2 havoc main_#t~nondet1#1; 2132#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 2131#L29-2 havoc main_#t~nondet1#1; 2130#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 2129#L29-2 havoc main_#t~nondet1#1; 2128#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 2127#L29-2 havoc main_#t~nondet1#1; 2126#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 2125#L29-2 havoc main_#t~nondet1#1; 2124#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 2123#L29-2 havoc main_#t~nondet1#1; 2122#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 2121#L29-2 havoc main_#t~nondet1#1; 2120#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 2119#L29-2 havoc main_#t~nondet1#1; 2118#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 2117#L29-2 havoc main_#t~nondet1#1; 2116#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 2115#L29-2 havoc main_#t~nondet1#1; 2114#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 2113#L29-2 havoc main_#t~nondet1#1; 2112#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 2111#L29-2 havoc main_#t~nondet1#1; 2110#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 2109#L29-2 havoc main_#t~nondet1#1; 2094#L29 assume !(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1; 2090#L29-3 assume main_~i~0#1 >= 100; 2091#L32 [2023-11-12 02:12:39,636 INFO L750 eck$LassoCheckResult]: Loop: 2091#L32 assume true; 2091#L32 [2023-11-12 02:12:39,636 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-12 02:12:39,636 INFO L85 PathProgramCache]: Analyzing trace with hash -439176862, now seen corresponding path program 4 times [2023-11-12 02:12:39,636 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-12 02:12:39,637 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [611293154] [2023-11-12 02:12:39,637 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-12 02:12:39,637 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-12 02:12:39,668 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-12 02:12:40,290 INFO L134 CoverageAnalysis]: Checked inductivity of 506 backedges. 0 proven. 506 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-12 02:12:40,290 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-12 02:12:40,290 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [611293154] [2023-11-12 02:12:40,292 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [611293154] provided 0 perfect and 1 imperfect interpolant sequences [2023-11-12 02:12:40,293 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1241732072] [2023-11-12 02:12:40,293 INFO L93 rtionOrderModulation]: Changing assertion order to TERMS_WITH_SMALL_CONSTANTS_FIRST [2023-11-12 02:12:40,293 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2023-11-12 02:12:40,293 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_13489a2e-8a24-4e25-8b20-2091353b9675/bin/uautomizer-verify-uTZkv6EMXl/z3 [2023-11-12 02:12:40,300 INFO L229 MonitoredProcess]: Starting monitored process 12 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_13489a2e-8a24-4e25-8b20-2091353b9675/bin/uautomizer-verify-uTZkv6EMXl/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2023-11-12 02:12:40,320 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_13489a2e-8a24-4e25-8b20-2091353b9675/bin/uautomizer-verify-uTZkv6EMXl/z3 -smt2 -in SMTLIB2_COMPLIANT=true (12)] Waiting until timeout for monitored process [2023-11-12 02:12:40,372 INFO L228 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2023-11-12 02:12:40,372 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2023-11-12 02:12:40,373 INFO L262 TraceCheckSpWp]: Trace formula consists of 133 conjuncts, 24 conjunts are in the unsatisfiable core [2023-11-12 02:12:40,377 INFO L285 TraceCheckSpWp]: Computing forward predicates... [2023-11-12 02:12:40,500 INFO L134 CoverageAnalysis]: Checked inductivity of 506 backedges. 0 proven. 506 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-12 02:12:40,500 INFO L327 TraceCheckSpWp]: Computing backward predicates... [2023-11-12 02:12:41,484 INFO L134 CoverageAnalysis]: Checked inductivity of 506 backedges. 0 proven. 506 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-12 02:12:41,485 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1241732072] provided 0 perfect and 2 imperfect interpolant sequences [2023-11-12 02:12:41,485 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2023-11-12 02:12:41,485 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [24, 24, 24] total 48 [2023-11-12 02:12:41,485 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1698224131] [2023-11-12 02:12:41,485 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2023-11-12 02:12:41,486 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-12 02:12:41,486 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-12 02:12:41,486 INFO L85 PathProgramCache]: Analyzing trace with hash 93, now seen corresponding path program 9 times [2023-11-12 02:12:41,486 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-12 02:12:41,487 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1547690449] [2023-11-12 02:12:41,487 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-12 02:12:41,487 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-12 02:12:41,489 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-12 02:12:41,489 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-12 02:12:41,490 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-12 02:12:41,490 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-12 02:12:41,493 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-12 02:12:41,494 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 49 interpolants. [2023-11-12 02:12:41,495 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=1176, Invalid=1176, Unknown=0, NotChecked=0, Total=2352 [2023-11-12 02:12:41,496 INFO L87 Difference]: Start difference. First operand 99 states and 123 transitions. cyclomatic complexity: 27 Second operand has 49 states, 48 states have (on average 2.1041666666666665) internal successors, (101), 49 states have internal predecessors, (101), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-12 02:12:42,178 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-12 02:12:42,179 INFO L93 Difference]: Finished difference Result 1898 states and 1971 transitions. [2023-11-12 02:12:42,179 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1898 states and 1971 transitions. [2023-11-12 02:12:42,200 INFO L131 ngComponentsAnalysis]: Automaton has 25 accepting balls. 25 [2023-11-12 02:12:42,215 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1898 states to 1850 states and 1923 transitions. [2023-11-12 02:12:42,216 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 81 [2023-11-12 02:12:42,216 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 81 [2023-11-12 02:12:42,216 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1850 states and 1923 transitions. [2023-11-12 02:12:42,219 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2023-11-12 02:12:42,219 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1850 states and 1923 transitions. [2023-11-12 02:12:42,221 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1850 states and 1923 transitions. [2023-11-12 02:12:42,249 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1850 to 147. [2023-11-12 02:12:42,249 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 147 states, 147 states have (on average 1.3265306122448979) internal successors, (195), 146 states have internal predecessors, (195), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-12 02:12:42,250 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 147 states to 147 states and 195 transitions. [2023-11-12 02:12:42,250 INFO L240 hiAutomatonCegarLoop]: Abstraction has 147 states and 195 transitions. [2023-11-12 02:12:42,251 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 48 states. [2023-11-12 02:12:42,252 INFO L428 stractBuchiCegarLoop]: Abstraction has 147 states and 195 transitions. [2023-11-12 02:12:42,252 INFO L335 stractBuchiCegarLoop]: ======== Iteration 11 ============ [2023-11-12 02:12:42,252 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 147 states and 195 transitions. [2023-11-12 02:12:42,253 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1 [2023-11-12 02:12:42,254 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-12 02:12:42,254 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-12 02:12:42,255 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [23, 22, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-12 02:12:42,256 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1] [2023-11-12 02:12:42,256 INFO L748 eck$LassoCheckResult]: Stem: 4440#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(9, 2); 4441#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~post2#1, main_#t~nondet1#1, main_#t~post4#1, main_#t~post5#1, main_#t~nondet3#1, main_~i~0#1, main_~j~0#1;havoc main_~i~0#1;havoc main_~j~0#1; 4443#L26 main_~i~0#1 := 0; 4444#L29-2 havoc main_#t~nondet1#1; 4448#L29 assume !(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1; 4435#L29-3 assume !(main_~i~0#1 >= 100);main_~j~0#1 := 0; 4436#L35-2 havoc main_#t~nondet3#1; 4442#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 4447#L35-2 havoc main_#t~nondet3#1; 4579#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 4578#L35-2 havoc main_#t~nondet3#1; 4577#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 4576#L35-2 havoc main_#t~nondet3#1; 4575#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 4574#L35-2 havoc main_#t~nondet3#1; 4573#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 4572#L35-2 havoc main_#t~nondet3#1; 4571#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 4570#L35-2 havoc main_#t~nondet3#1; 4569#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 4568#L35-2 havoc main_#t~nondet3#1; 4567#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 4566#L35-2 havoc main_#t~nondet3#1; 4565#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 4564#L35-2 havoc main_#t~nondet3#1; 4563#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 4562#L35-2 havoc main_#t~nondet3#1; 4561#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 4560#L35-2 havoc main_#t~nondet3#1; 4559#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 4558#L35-2 havoc main_#t~nondet3#1; 4557#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 4556#L35-2 havoc main_#t~nondet3#1; 4555#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 4554#L35-2 havoc main_#t~nondet3#1; 4553#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 4552#L35-2 havoc main_#t~nondet3#1; 4551#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 4550#L35-2 havoc main_#t~nondet3#1; 4549#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 4548#L35-2 havoc main_#t~nondet3#1; 4547#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 4546#L35-2 havoc main_#t~nondet3#1; 4545#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 4544#L35-2 havoc main_#t~nondet3#1; 4543#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 4542#L35-2 havoc main_#t~nondet3#1; 4541#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 4540#L35-2 havoc main_#t~nondet3#1; 4539#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 4538#L35-2 havoc main_#t~nondet3#1; 4446#L35 assume !(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1; 4445#L35-3 assume main_~j~0#1 >= 100; 4434#L32 [2023-11-12 02:12:42,256 INFO L750 eck$LassoCheckResult]: Loop: 4434#L32 assume true; 4434#L32 [2023-11-12 02:12:42,257 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-12 02:12:42,257 INFO L85 PathProgramCache]: Analyzing trace with hash -173936093, now seen corresponding path program 4 times [2023-11-12 02:12:42,257 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-12 02:12:42,257 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [401429771] [2023-11-12 02:12:42,258 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-12 02:12:42,258 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-12 02:12:42,284 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-12 02:12:42,944 INFO L134 CoverageAnalysis]: Checked inductivity of 506 backedges. 0 proven. 506 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-12 02:12:42,944 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-12 02:12:42,945 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [401429771] [2023-11-12 02:12:42,945 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [401429771] provided 0 perfect and 1 imperfect interpolant sequences [2023-11-12 02:12:42,945 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [496425621] [2023-11-12 02:12:42,945 INFO L93 rtionOrderModulation]: Changing assertion order to TERMS_WITH_SMALL_CONSTANTS_FIRST [2023-11-12 02:12:42,945 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2023-11-12 02:12:42,946 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_13489a2e-8a24-4e25-8b20-2091353b9675/bin/uautomizer-verify-uTZkv6EMXl/z3 [2023-11-12 02:12:42,950 INFO L229 MonitoredProcess]: Starting monitored process 13 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_13489a2e-8a24-4e25-8b20-2091353b9675/bin/uautomizer-verify-uTZkv6EMXl/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2023-11-12 02:12:42,977 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_13489a2e-8a24-4e25-8b20-2091353b9675/bin/uautomizer-verify-uTZkv6EMXl/z3 -smt2 -in SMTLIB2_COMPLIANT=true (13)] Waiting until timeout for monitored process [2023-11-12 02:12:43,034 INFO L228 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2023-11-12 02:12:43,035 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2023-11-12 02:12:43,037 INFO L262 TraceCheckSpWp]: Trace formula consists of 182 conjuncts, 24 conjunts are in the unsatisfiable core [2023-11-12 02:12:43,040 INFO L285 TraceCheckSpWp]: Computing forward predicates... [2023-11-12 02:12:43,150 INFO L134 CoverageAnalysis]: Checked inductivity of 506 backedges. 0 proven. 506 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-12 02:12:43,150 INFO L327 TraceCheckSpWp]: Computing backward predicates... [2023-11-12 02:12:44,147 INFO L134 CoverageAnalysis]: Checked inductivity of 506 backedges. 0 proven. 506 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-12 02:12:44,148 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [496425621] provided 0 perfect and 2 imperfect interpolant sequences [2023-11-12 02:12:44,148 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2023-11-12 02:12:44,148 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [24, 24, 24] total 48 [2023-11-12 02:12:44,149 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1521165239] [2023-11-12 02:12:44,149 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2023-11-12 02:12:44,149 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-12 02:12:44,150 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-12 02:12:44,150 INFO L85 PathProgramCache]: Analyzing trace with hash 93, now seen corresponding path program 10 times [2023-11-12 02:12:44,150 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-12 02:12:44,150 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [523310760] [2023-11-12 02:12:44,150 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-12 02:12:44,151 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-12 02:12:44,152 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-12 02:12:44,152 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-12 02:12:44,153 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-12 02:12:44,154 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-12 02:12:44,158 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-12 02:12:44,159 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 49 interpolants. [2023-11-12 02:12:44,160 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=1176, Invalid=1176, Unknown=0, NotChecked=0, Total=2352 [2023-11-12 02:12:44,161 INFO L87 Difference]: Start difference. First operand 147 states and 195 transitions. cyclomatic complexity: 51 Second operand has 49 states, 48 states have (on average 2.1666666666666665) internal successors, (104), 49 states have internal predecessors, (104), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-12 02:12:44,266 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-12 02:12:44,267 INFO L93 Difference]: Finished difference Result 244 states and 292 transitions. [2023-11-12 02:12:44,267 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 244 states and 292 transitions. [2023-11-12 02:12:44,269 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1 [2023-11-12 02:12:44,271 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 244 states to 196 states and 244 transitions. [2023-11-12 02:12:44,272 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 9 [2023-11-12 02:12:44,272 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 9 [2023-11-12 02:12:44,272 INFO L73 IsDeterministic]: Start isDeterministic. Operand 196 states and 244 transitions. [2023-11-12 02:12:44,272 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2023-11-12 02:12:44,273 INFO L218 hiAutomatonCegarLoop]: Abstraction has 196 states and 244 transitions. [2023-11-12 02:12:44,273 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 196 states and 244 transitions. [2023-11-12 02:12:44,276 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 196 to 195. [2023-11-12 02:12:44,276 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 195 states, 195 states have (on average 1.2461538461538462) internal successors, (243), 194 states have internal predecessors, (243), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-12 02:12:44,277 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 195 states to 195 states and 243 transitions. [2023-11-12 02:12:44,278 INFO L240 hiAutomatonCegarLoop]: Abstraction has 195 states and 243 transitions. [2023-11-12 02:12:44,278 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 48 states. [2023-11-12 02:12:44,279 INFO L428 stractBuchiCegarLoop]: Abstraction has 195 states and 243 transitions. [2023-11-12 02:12:44,279 INFO L335 stractBuchiCegarLoop]: ======== Iteration 12 ============ [2023-11-12 02:12:44,279 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 195 states and 243 transitions. [2023-11-12 02:12:44,281 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1 [2023-11-12 02:12:44,281 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-12 02:12:44,281 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-12 02:12:44,283 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [47, 46, 1, 1, 1, 1, 1] [2023-11-12 02:12:44,283 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1] [2023-11-12 02:12:44,284 INFO L748 eck$LassoCheckResult]: Stem: 5195#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(9, 2); 5196#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~post2#1, main_#t~nondet1#1, main_#t~post4#1, main_#t~post5#1, main_#t~nondet3#1, main_~i~0#1, main_~j~0#1;havoc main_~i~0#1;havoc main_~j~0#1; 5199#L26 main_~i~0#1 := 0; 5200#L29-2 havoc main_#t~nondet1#1; 5193#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 5194#L29-2 havoc main_#t~nondet1#1; 5202#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 5295#L29-2 havoc main_#t~nondet1#1; 5294#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 5293#L29-2 havoc main_#t~nondet1#1; 5292#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 5291#L29-2 havoc main_#t~nondet1#1; 5290#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 5289#L29-2 havoc main_#t~nondet1#1; 5288#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 5287#L29-2 havoc main_#t~nondet1#1; 5286#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 5285#L29-2 havoc main_#t~nondet1#1; 5284#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 5283#L29-2 havoc main_#t~nondet1#1; 5282#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 5281#L29-2 havoc main_#t~nondet1#1; 5280#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 5279#L29-2 havoc main_#t~nondet1#1; 5278#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 5277#L29-2 havoc main_#t~nondet1#1; 5276#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 5275#L29-2 havoc main_#t~nondet1#1; 5274#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 5273#L29-2 havoc main_#t~nondet1#1; 5272#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 5271#L29-2 havoc main_#t~nondet1#1; 5270#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 5269#L29-2 havoc main_#t~nondet1#1; 5268#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 5267#L29-2 havoc main_#t~nondet1#1; 5266#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 5265#L29-2 havoc main_#t~nondet1#1; 5264#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 5263#L29-2 havoc main_#t~nondet1#1; 5262#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 5261#L29-2 havoc main_#t~nondet1#1; 5260#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 5259#L29-2 havoc main_#t~nondet1#1; 5258#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 5257#L29-2 havoc main_#t~nondet1#1; 5256#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 5255#L29-2 havoc main_#t~nondet1#1; 5254#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 5253#L29-2 havoc main_#t~nondet1#1; 5252#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 5251#L29-2 havoc main_#t~nondet1#1; 5250#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 5249#L29-2 havoc main_#t~nondet1#1; 5248#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 5247#L29-2 havoc main_#t~nondet1#1; 5246#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 5245#L29-2 havoc main_#t~nondet1#1; 5244#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 5243#L29-2 havoc main_#t~nondet1#1; 5242#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 5241#L29-2 havoc main_#t~nondet1#1; 5240#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 5239#L29-2 havoc main_#t~nondet1#1; 5238#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 5237#L29-2 havoc main_#t~nondet1#1; 5236#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 5235#L29-2 havoc main_#t~nondet1#1; 5234#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 5233#L29-2 havoc main_#t~nondet1#1; 5232#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 5231#L29-2 havoc main_#t~nondet1#1; 5230#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 5229#L29-2 havoc main_#t~nondet1#1; 5228#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 5227#L29-2 havoc main_#t~nondet1#1; 5226#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 5225#L29-2 havoc main_#t~nondet1#1; 5224#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 5223#L29-2 havoc main_#t~nondet1#1; 5222#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 5221#L29-2 havoc main_#t~nondet1#1; 5220#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 5219#L29-2 havoc main_#t~nondet1#1; 5218#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 5217#L29-2 havoc main_#t~nondet1#1; 5216#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 5215#L29-2 havoc main_#t~nondet1#1; 5214#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 5213#L29-2 havoc main_#t~nondet1#1; 5212#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 5211#L29-2 havoc main_#t~nondet1#1; 5210#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 5209#L29-2 havoc main_#t~nondet1#1; 5206#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 5205#L29-2 havoc main_#t~nondet1#1; 5192#L29 assume !(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1; 5188#L29-3 assume main_~i~0#1 >= 100; 5189#L32 [2023-11-12 02:12:44,284 INFO L750 eck$LassoCheckResult]: Loop: 5189#L32 assume true; 5189#L32 [2023-11-12 02:12:44,284 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-12 02:12:44,285 INFO L85 PathProgramCache]: Analyzing trace with hash -41810454, now seen corresponding path program 5 times [2023-11-12 02:12:44,285 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-12 02:12:44,285 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1973303395] [2023-11-12 02:12:44,285 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-12 02:12:44,286 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-12 02:12:44,321 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-12 02:12:46,134 INFO L134 CoverageAnalysis]: Checked inductivity of 2162 backedges. 0 proven. 2162 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-12 02:12:46,134 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-12 02:12:46,134 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1973303395] [2023-11-12 02:12:46,135 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1973303395] provided 0 perfect and 1 imperfect interpolant sequences [2023-11-12 02:12:46,135 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [2093867657] [2023-11-12 02:12:46,135 INFO L93 rtionOrderModulation]: Changing assertion order to INSIDE_LOOP_FIRST1 [2023-11-12 02:12:46,135 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2023-11-12 02:12:46,135 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_13489a2e-8a24-4e25-8b20-2091353b9675/bin/uautomizer-verify-uTZkv6EMXl/z3 [2023-11-12 02:12:46,139 INFO L229 MonitoredProcess]: Starting monitored process 14 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_13489a2e-8a24-4e25-8b20-2091353b9675/bin/uautomizer-verify-uTZkv6EMXl/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2023-11-12 02:12:46,168 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_13489a2e-8a24-4e25-8b20-2091353b9675/bin/uautomizer-verify-uTZkv6EMXl/z3 -smt2 -in SMTLIB2_COMPLIANT=true (14)] Waiting until timeout for monitored process [2023-11-12 02:12:46,251 INFO L228 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 47 check-sat command(s) [2023-11-12 02:12:46,251 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2023-11-12 02:12:46,253 INFO L262 TraceCheckSpWp]: Trace formula consists of 253 conjuncts, 48 conjunts are in the unsatisfiable core [2023-11-12 02:12:46,258 INFO L285 TraceCheckSpWp]: Computing forward predicates... [2023-11-12 02:12:46,440 INFO L134 CoverageAnalysis]: Checked inductivity of 2162 backedges. 0 proven. 2162 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-12 02:12:46,440 INFO L327 TraceCheckSpWp]: Computing backward predicates... [2023-11-12 02:12:50,063 INFO L134 CoverageAnalysis]: Checked inductivity of 2162 backedges. 0 proven. 2162 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-12 02:12:50,064 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [2093867657] provided 0 perfect and 2 imperfect interpolant sequences [2023-11-12 02:12:50,064 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2023-11-12 02:12:50,064 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [48, 48, 48] total 96 [2023-11-12 02:12:50,064 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [723490799] [2023-11-12 02:12:50,064 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2023-11-12 02:12:50,065 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-12 02:12:50,066 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-12 02:12:50,066 INFO L85 PathProgramCache]: Analyzing trace with hash 93, now seen corresponding path program 11 times [2023-11-12 02:12:50,066 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-12 02:12:50,066 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [122341311] [2023-11-12 02:12:50,066 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-12 02:12:50,067 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-12 02:12:50,070 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-12 02:12:50,070 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-12 02:12:50,071 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-12 02:12:50,071 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-12 02:12:50,073 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-12 02:12:50,075 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 97 interpolants. [2023-11-12 02:12:50,079 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=4656, Invalid=4656, Unknown=0, NotChecked=0, Total=9312 [2023-11-12 02:12:50,080 INFO L87 Difference]: Start difference. First operand 195 states and 243 transitions. cyclomatic complexity: 51 Second operand has 97 states, 96 states have (on average 2.0520833333333335) internal successors, (197), 97 states have internal predecessors, (197), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-12 02:12:53,086 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-12 02:12:53,086 INFO L93 Difference]: Finished difference Result 7250 states and 7395 transitions. [2023-11-12 02:12:53,086 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 7250 states and 7395 transitions. [2023-11-12 02:12:53,145 INFO L131 ngComponentsAnalysis]: Automaton has 49 accepting balls. 49 [2023-11-12 02:12:53,191 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 7250 states to 7154 states and 7299 transitions. [2023-11-12 02:12:53,191 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 153 [2023-11-12 02:12:53,192 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 153 [2023-11-12 02:12:53,192 INFO L73 IsDeterministic]: Start isDeterministic. Operand 7154 states and 7299 transitions. [2023-11-12 02:12:53,196 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2023-11-12 02:12:53,196 INFO L218 hiAutomatonCegarLoop]: Abstraction has 7154 states and 7299 transitions. [2023-11-12 02:12:53,204 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 7154 states and 7299 transitions. [2023-11-12 02:12:53,233 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 7154 to 291. [2023-11-12 02:12:53,234 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 291 states, 291 states have (on average 1.3298969072164948) internal successors, (387), 290 states have internal predecessors, (387), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-12 02:12:53,235 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 291 states to 291 states and 387 transitions. [2023-11-12 02:12:53,235 INFO L240 hiAutomatonCegarLoop]: Abstraction has 291 states and 387 transitions. [2023-11-12 02:12:53,236 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 96 states. [2023-11-12 02:12:53,237 INFO L428 stractBuchiCegarLoop]: Abstraction has 291 states and 387 transitions. [2023-11-12 02:12:53,237 INFO L335 stractBuchiCegarLoop]: ======== Iteration 13 ============ [2023-11-12 02:12:53,237 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 291 states and 387 transitions. [2023-11-12 02:12:53,239 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1 [2023-11-12 02:12:53,239 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-12 02:12:53,239 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-12 02:12:53,241 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [47, 46, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-12 02:12:53,241 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1] [2023-11-12 02:12:53,241 INFO L748 eck$LassoCheckResult]: Stem: 13319#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(9, 2); 13320#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~post2#1, main_#t~nondet1#1, main_#t~post4#1, main_#t~post5#1, main_#t~nondet3#1, main_~i~0#1, main_~j~0#1;havoc main_~i~0#1;havoc main_~j~0#1; 13325#L26 main_~i~0#1 := 0; 13326#L29-2 havoc main_#t~nondet1#1; 13328#L29 assume !(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1; 13317#L29-3 assume !(main_~i~0#1 >= 100);main_~j~0#1 := 0; 13318#L35-2 havoc main_#t~nondet3#1; 13324#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 13331#L35-2 havoc main_#t~nondet3#1; 13605#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 13604#L35-2 havoc main_#t~nondet3#1; 13603#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 13602#L35-2 havoc main_#t~nondet3#1; 13601#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 13600#L35-2 havoc main_#t~nondet3#1; 13599#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 13598#L35-2 havoc main_#t~nondet3#1; 13597#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 13596#L35-2 havoc main_#t~nondet3#1; 13595#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 13594#L35-2 havoc main_#t~nondet3#1; 13593#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 13592#L35-2 havoc main_#t~nondet3#1; 13591#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 13590#L35-2 havoc main_#t~nondet3#1; 13589#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 13588#L35-2 havoc main_#t~nondet3#1; 13587#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 13586#L35-2 havoc main_#t~nondet3#1; 13585#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 13584#L35-2 havoc main_#t~nondet3#1; 13583#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 13582#L35-2 havoc main_#t~nondet3#1; 13581#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 13580#L35-2 havoc main_#t~nondet3#1; 13579#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 13578#L35-2 havoc main_#t~nondet3#1; 13577#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 13576#L35-2 havoc main_#t~nondet3#1; 13575#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 13574#L35-2 havoc main_#t~nondet3#1; 13573#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 13572#L35-2 havoc main_#t~nondet3#1; 13571#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 13570#L35-2 havoc main_#t~nondet3#1; 13569#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 13568#L35-2 havoc main_#t~nondet3#1; 13567#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 13566#L35-2 havoc main_#t~nondet3#1; 13565#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 13564#L35-2 havoc main_#t~nondet3#1; 13563#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 13562#L35-2 havoc main_#t~nondet3#1; 13561#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 13560#L35-2 havoc main_#t~nondet3#1; 13559#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 13558#L35-2 havoc main_#t~nondet3#1; 13557#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 13556#L35-2 havoc main_#t~nondet3#1; 13555#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 13554#L35-2 havoc main_#t~nondet3#1; 13553#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 13552#L35-2 havoc main_#t~nondet3#1; 13551#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 13550#L35-2 havoc main_#t~nondet3#1; 13549#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 13548#L35-2 havoc main_#t~nondet3#1; 13547#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 13546#L35-2 havoc main_#t~nondet3#1; 13545#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 13544#L35-2 havoc main_#t~nondet3#1; 13543#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 13542#L35-2 havoc main_#t~nondet3#1; 13541#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 13540#L35-2 havoc main_#t~nondet3#1; 13539#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 13538#L35-2 havoc main_#t~nondet3#1; 13537#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 13536#L35-2 havoc main_#t~nondet3#1; 13535#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 13534#L35-2 havoc main_#t~nondet3#1; 13533#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 13532#L35-2 havoc main_#t~nondet3#1; 13531#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 13530#L35-2 havoc main_#t~nondet3#1; 13529#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 13528#L35-2 havoc main_#t~nondet3#1; 13527#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 13526#L35-2 havoc main_#t~nondet3#1; 13525#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 13524#L35-2 havoc main_#t~nondet3#1; 13523#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 13522#L35-2 havoc main_#t~nondet3#1; 13521#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 13520#L35-2 havoc main_#t~nondet3#1; 13519#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 13518#L35-2 havoc main_#t~nondet3#1; 13517#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 13516#L35-2 havoc main_#t~nondet3#1; 13330#L35 assume !(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1; 13327#L35-3 assume main_~j~0#1 >= 100; 13316#L32 [2023-11-12 02:12:53,242 INFO L750 eck$LassoCheckResult]: Loop: 13316#L32 assume true; 13316#L32 [2023-11-12 02:12:53,242 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-12 02:12:53,242 INFO L85 PathProgramCache]: Analyzing trace with hash -174540373, now seen corresponding path program 5 times [2023-11-12 02:12:53,242 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-12 02:12:53,243 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2394691] [2023-11-12 02:12:53,243 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-12 02:12:53,243 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-12 02:12:53,276 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-12 02:12:55,006 INFO L134 CoverageAnalysis]: Checked inductivity of 2162 backedges. 0 proven. 2162 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-12 02:12:55,006 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-12 02:12:55,006 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2394691] [2023-11-12 02:12:55,007 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2394691] provided 0 perfect and 1 imperfect interpolant sequences [2023-11-12 02:12:55,007 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1332767227] [2023-11-12 02:12:55,007 INFO L93 rtionOrderModulation]: Changing assertion order to INSIDE_LOOP_FIRST1 [2023-11-12 02:12:55,007 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2023-11-12 02:12:55,007 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_13489a2e-8a24-4e25-8b20-2091353b9675/bin/uautomizer-verify-uTZkv6EMXl/z3 [2023-11-12 02:12:55,011 INFO L229 MonitoredProcess]: Starting monitored process 15 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_13489a2e-8a24-4e25-8b20-2091353b9675/bin/uautomizer-verify-uTZkv6EMXl/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2023-11-12 02:12:55,013 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_13489a2e-8a24-4e25-8b20-2091353b9675/bin/uautomizer-verify-uTZkv6EMXl/z3 -smt2 -in SMTLIB2_COMPLIANT=true (15)] Waiting until timeout for monitored process [2023-11-12 02:12:55,140 INFO L228 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 47 check-sat command(s) [2023-11-12 02:12:55,141 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2023-11-12 02:12:55,144 INFO L262 TraceCheckSpWp]: Trace formula consists of 350 conjuncts, 48 conjunts are in the unsatisfiable core [2023-11-12 02:12:55,149 INFO L285 TraceCheckSpWp]: Computing forward predicates... [2023-11-12 02:12:55,362 INFO L134 CoverageAnalysis]: Checked inductivity of 2162 backedges. 0 proven. 2162 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-12 02:12:55,362 INFO L327 TraceCheckSpWp]: Computing backward predicates... [2023-11-12 02:12:58,827 INFO L134 CoverageAnalysis]: Checked inductivity of 2162 backedges. 0 proven. 2162 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-12 02:12:58,827 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1332767227] provided 0 perfect and 2 imperfect interpolant sequences [2023-11-12 02:12:58,827 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2023-11-12 02:12:58,827 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [48, 48, 48] total 96 [2023-11-12 02:12:58,827 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1321460921] [2023-11-12 02:12:58,828 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2023-11-12 02:12:58,828 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-12 02:12:58,829 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-12 02:12:58,829 INFO L85 PathProgramCache]: Analyzing trace with hash 93, now seen corresponding path program 12 times [2023-11-12 02:12:58,829 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-12 02:12:58,829 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2119446600] [2023-11-12 02:12:58,829 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-12 02:12:58,830 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-12 02:12:58,831 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-12 02:12:58,831 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-12 02:12:58,832 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-12 02:12:58,832 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-12 02:12:58,836 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-12 02:12:58,838 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 97 interpolants. [2023-11-12 02:12:58,841 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=4656, Invalid=4656, Unknown=0, NotChecked=0, Total=9312 [2023-11-12 02:12:58,841 INFO L87 Difference]: Start difference. First operand 291 states and 387 transitions. cyclomatic complexity: 99 Second operand has 97 states, 96 states have (on average 2.0833333333333335) internal successors, (200), 97 states have internal predecessors, (200), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-12 02:12:59,111 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-12 02:12:59,111 INFO L93 Difference]: Finished difference Result 484 states and 580 transitions. [2023-11-12 02:12:59,111 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 484 states and 580 transitions. [2023-11-12 02:12:59,115 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1 [2023-11-12 02:12:59,118 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 484 states to 388 states and 484 transitions. [2023-11-12 02:12:59,118 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 9 [2023-11-12 02:12:59,118 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 9 [2023-11-12 02:12:59,118 INFO L73 IsDeterministic]: Start isDeterministic. Operand 388 states and 484 transitions. [2023-11-12 02:12:59,119 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2023-11-12 02:12:59,119 INFO L218 hiAutomatonCegarLoop]: Abstraction has 388 states and 484 transitions. [2023-11-12 02:12:59,119 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 388 states and 484 transitions. [2023-11-12 02:12:59,124 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 388 to 387. [2023-11-12 02:12:59,124 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 387 states, 387 states have (on average 1.248062015503876) internal successors, (483), 386 states have internal predecessors, (483), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-12 02:12:59,126 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 387 states to 387 states and 483 transitions. [2023-11-12 02:12:59,126 INFO L240 hiAutomatonCegarLoop]: Abstraction has 387 states and 483 transitions. [2023-11-12 02:12:59,127 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 96 states. [2023-11-12 02:12:59,127 INFO L428 stractBuchiCegarLoop]: Abstraction has 387 states and 483 transitions. [2023-11-12 02:12:59,127 INFO L335 stractBuchiCegarLoop]: ======== Iteration 14 ============ [2023-11-12 02:12:59,128 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 387 states and 483 transitions. [2023-11-12 02:12:59,130 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1 [2023-11-12 02:12:59,130 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-12 02:12:59,130 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-12 02:12:59,133 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [95, 94, 1, 1, 1, 1, 1] [2023-11-12 02:12:59,133 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1] [2023-11-12 02:12:59,133 INFO L748 eck$LassoCheckResult]: Stem: 14797#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(9, 2); 14798#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~post2#1, main_#t~nondet1#1, main_#t~post4#1, main_#t~post5#1, main_#t~nondet3#1, main_~i~0#1, main_~j~0#1;havoc main_~i~0#1;havoc main_~j~0#1; 14801#L26 main_~i~0#1 := 0; 14802#L29-2 havoc main_#t~nondet1#1; 14795#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 14796#L29-2 havoc main_#t~nondet1#1; 14804#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 14993#L29-2 havoc main_#t~nondet1#1; 14992#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 14991#L29-2 havoc main_#t~nondet1#1; 14990#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 14989#L29-2 havoc main_#t~nondet1#1; 14988#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 14987#L29-2 havoc main_#t~nondet1#1; 14986#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 14985#L29-2 havoc main_#t~nondet1#1; 14984#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 14983#L29-2 havoc main_#t~nondet1#1; 14982#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 14981#L29-2 havoc main_#t~nondet1#1; 14980#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 14979#L29-2 havoc main_#t~nondet1#1; 14978#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 14977#L29-2 havoc main_#t~nondet1#1; 14976#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 14975#L29-2 havoc main_#t~nondet1#1; 14974#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 14973#L29-2 havoc main_#t~nondet1#1; 14972#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 14971#L29-2 havoc main_#t~nondet1#1; 14970#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 14969#L29-2 havoc main_#t~nondet1#1; 14968#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 14967#L29-2 havoc main_#t~nondet1#1; 14966#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 14965#L29-2 havoc main_#t~nondet1#1; 14964#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 14963#L29-2 havoc main_#t~nondet1#1; 14962#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 14961#L29-2 havoc main_#t~nondet1#1; 14960#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 14959#L29-2 havoc main_#t~nondet1#1; 14958#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 14957#L29-2 havoc main_#t~nondet1#1; 14956#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 14955#L29-2 havoc main_#t~nondet1#1; 14954#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 14953#L29-2 havoc main_#t~nondet1#1; 14952#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 14951#L29-2 havoc main_#t~nondet1#1; 14950#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 14949#L29-2 havoc main_#t~nondet1#1; 14948#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 14947#L29-2 havoc main_#t~nondet1#1; 14946#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 14945#L29-2 havoc main_#t~nondet1#1; 14944#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 14943#L29-2 havoc main_#t~nondet1#1; 14942#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 14941#L29-2 havoc main_#t~nondet1#1; 14940#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 14939#L29-2 havoc main_#t~nondet1#1; 14938#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 14937#L29-2 havoc main_#t~nondet1#1; 14936#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 14935#L29-2 havoc main_#t~nondet1#1; 14934#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 14933#L29-2 havoc main_#t~nondet1#1; 14932#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 14931#L29-2 havoc main_#t~nondet1#1; 14930#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 14929#L29-2 havoc main_#t~nondet1#1; 14928#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 14927#L29-2 havoc main_#t~nondet1#1; 14926#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 14925#L29-2 havoc main_#t~nondet1#1; 14924#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 14923#L29-2 havoc main_#t~nondet1#1; 14922#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 14921#L29-2 havoc main_#t~nondet1#1; 14920#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 14919#L29-2 havoc main_#t~nondet1#1; 14918#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 14917#L29-2 havoc main_#t~nondet1#1; 14916#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 14915#L29-2 havoc main_#t~nondet1#1; 14914#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 14913#L29-2 havoc main_#t~nondet1#1; 14912#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 14911#L29-2 havoc main_#t~nondet1#1; 14910#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 14909#L29-2 havoc main_#t~nondet1#1; 14908#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 14907#L29-2 havoc main_#t~nondet1#1; 14906#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 14905#L29-2 havoc main_#t~nondet1#1; 14904#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 14903#L29-2 havoc main_#t~nondet1#1; 14902#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 14901#L29-2 havoc main_#t~nondet1#1; 14900#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 14899#L29-2 havoc main_#t~nondet1#1; 14898#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 14897#L29-2 havoc main_#t~nondet1#1; 14896#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 14895#L29-2 havoc main_#t~nondet1#1; 14894#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 14893#L29-2 havoc main_#t~nondet1#1; 14892#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 14891#L29-2 havoc main_#t~nondet1#1; 14890#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 14889#L29-2 havoc main_#t~nondet1#1; 14888#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 14887#L29-2 havoc main_#t~nondet1#1; 14886#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 14885#L29-2 havoc main_#t~nondet1#1; 14884#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 14883#L29-2 havoc main_#t~nondet1#1; 14882#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 14881#L29-2 havoc main_#t~nondet1#1; 14880#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 14879#L29-2 havoc main_#t~nondet1#1; 14878#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 14877#L29-2 havoc main_#t~nondet1#1; 14876#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 14875#L29-2 havoc main_#t~nondet1#1; 14874#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 14873#L29-2 havoc main_#t~nondet1#1; 14872#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 14871#L29-2 havoc main_#t~nondet1#1; 14870#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 14869#L29-2 havoc main_#t~nondet1#1; 14868#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 14867#L29-2 havoc main_#t~nondet1#1; 14866#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 14865#L29-2 havoc main_#t~nondet1#1; 14864#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 14863#L29-2 havoc main_#t~nondet1#1; 14862#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 14861#L29-2 havoc main_#t~nondet1#1; 14860#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 14859#L29-2 havoc main_#t~nondet1#1; 14858#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 14857#L29-2 havoc main_#t~nondet1#1; 14856#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 14855#L29-2 havoc main_#t~nondet1#1; 14854#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 14853#L29-2 havoc main_#t~nondet1#1; 14852#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 14851#L29-2 havoc main_#t~nondet1#1; 14850#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 14849#L29-2 havoc main_#t~nondet1#1; 14848#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 14847#L29-2 havoc main_#t~nondet1#1; 14846#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 14845#L29-2 havoc main_#t~nondet1#1; 14844#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 14843#L29-2 havoc main_#t~nondet1#1; 14842#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 14841#L29-2 havoc main_#t~nondet1#1; 14840#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 14839#L29-2 havoc main_#t~nondet1#1; 14838#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 14837#L29-2 havoc main_#t~nondet1#1; 14836#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 14835#L29-2 havoc main_#t~nondet1#1; 14834#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 14833#L29-2 havoc main_#t~nondet1#1; 14832#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 14831#L29-2 havoc main_#t~nondet1#1; 14830#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 14829#L29-2 havoc main_#t~nondet1#1; 14828#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 14827#L29-2 havoc main_#t~nondet1#1; 14826#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 14825#L29-2 havoc main_#t~nondet1#1; 14824#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 14823#L29-2 havoc main_#t~nondet1#1; 14822#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 14821#L29-2 havoc main_#t~nondet1#1; 14820#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 14819#L29-2 havoc main_#t~nondet1#1; 14818#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 14817#L29-2 havoc main_#t~nondet1#1; 14816#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 14815#L29-2 havoc main_#t~nondet1#1; 14814#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 14813#L29-2 havoc main_#t~nondet1#1; 14812#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 14811#L29-2 havoc main_#t~nondet1#1; 14808#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 14807#L29-2 havoc main_#t~nondet1#1; 14794#L29 assume !(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1; 14790#L29-3 assume main_~i~0#1 >= 100; 14791#L32 [2023-11-12 02:12:59,134 INFO L750 eck$LassoCheckResult]: Loop: 14791#L32 assume true; 14791#L32 [2023-11-12 02:12:59,134 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-12 02:12:59,134 INFO L85 PathProgramCache]: Analyzing trace with hash 1558585082, now seen corresponding path program 6 times [2023-11-12 02:12:59,134 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-12 02:12:59,135 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [280565344] [2023-11-12 02:12:59,135 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-12 02:12:59,135 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-12 02:12:59,187 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-12 02:13:05,532 INFO L134 CoverageAnalysis]: Checked inductivity of 8930 backedges. 0 proven. 8930 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-12 02:13:05,532 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-12 02:13:05,532 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [280565344] [2023-11-12 02:13:05,532 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [280565344] provided 0 perfect and 1 imperfect interpolant sequences [2023-11-12 02:13:05,533 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1216644538] [2023-11-12 02:13:05,533 INFO L93 rtionOrderModulation]: Changing assertion order to MIX_INSIDE_OUTSIDE [2023-11-12 02:13:05,533 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2023-11-12 02:13:05,533 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_13489a2e-8a24-4e25-8b20-2091353b9675/bin/uautomizer-verify-uTZkv6EMXl/z3 [2023-11-12 02:13:05,537 INFO L229 MonitoredProcess]: Starting monitored process 16 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_13489a2e-8a24-4e25-8b20-2091353b9675/bin/uautomizer-verify-uTZkv6EMXl/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2023-11-12 02:13:05,545 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_13489a2e-8a24-4e25-8b20-2091353b9675/bin/uautomizer-verify-uTZkv6EMXl/z3 -smt2 -in SMTLIB2_COMPLIANT=true (16)] Waiting until timeout for monitored process [2023-11-12 02:13:05,730 INFO L228 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued 95 check-sat command(s) [2023-11-12 02:13:05,730 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2023-11-12 02:13:05,734 INFO L262 TraceCheckSpWp]: Trace formula consists of 493 conjuncts, 96 conjunts are in the unsatisfiable core [2023-11-12 02:13:05,742 INFO L285 TraceCheckSpWp]: Computing forward predicates... [2023-11-12 02:13:06,170 INFO L134 CoverageAnalysis]: Checked inductivity of 8930 backedges. 0 proven. 8930 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-12 02:13:06,171 INFO L327 TraceCheckSpWp]: Computing backward predicates... [2023-11-12 02:13:11,234 INFO L134 CoverageAnalysis]: Checked inductivity of 8930 backedges. 0 proven. 8930 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-12 02:13:11,234 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1216644538] provided 0 perfect and 2 imperfect interpolant sequences [2023-11-12 02:13:11,235 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2023-11-12 02:13:11,235 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [96, 96, 96] total 102 [2023-11-12 02:13:11,235 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1104995524] [2023-11-12 02:13:11,235 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2023-11-12 02:13:11,236 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-12 02:13:11,236 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-12 02:13:11,237 INFO L85 PathProgramCache]: Analyzing trace with hash 93, now seen corresponding path program 13 times [2023-11-12 02:13:11,237 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-12 02:13:11,237 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1700013884] [2023-11-12 02:13:11,237 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-12 02:13:11,238 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-12 02:13:11,239 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-12 02:13:11,239 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-12 02:13:11,240 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-12 02:13:11,240 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-12 02:13:11,242 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-12 02:13:11,244 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 103 interpolants. [2023-11-12 02:13:11,247 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5253, Invalid=5253, Unknown=0, NotChecked=0, Total=10506 [2023-11-12 02:13:11,248 INFO L87 Difference]: Start difference. First operand 387 states and 483 transitions. cyclomatic complexity: 99 Second operand has 103 states, 102 states have (on average 2.0588235294117645) internal successors, (210), 103 states have internal predecessors, (210), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-12 02:13:14,144 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-12 02:13:14,144 INFO L93 Difference]: Finished difference Result 10592 states and 10701 transitions. [2023-11-12 02:13:14,144 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 10592 states and 10701 transitions. [2023-11-12 02:13:14,213 INFO L131 ngComponentsAnalysis]: Automaton has 7 accepting balls. 7 [2023-11-12 02:13:14,285 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 10592 states to 10580 states and 10689 transitions. [2023-11-12 02:13:14,285 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 27 [2023-11-12 02:13:14,285 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 27 [2023-11-12 02:13:14,285 INFO L73 IsDeterministic]: Start isDeterministic. Operand 10580 states and 10689 transitions. [2023-11-12 02:13:14,297 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2023-11-12 02:13:14,297 INFO L218 hiAutomatonCegarLoop]: Abstraction has 10580 states and 10689 transitions. [2023-11-12 02:13:14,313 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 10580 states and 10689 transitions. [2023-11-12 02:13:14,373 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 10580 to 399. [2023-11-12 02:13:14,374 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 399 states, 399 states have (on average 1.255639097744361) internal successors, (501), 398 states have internal predecessors, (501), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-12 02:13:14,376 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 399 states to 399 states and 501 transitions. [2023-11-12 02:13:14,376 INFO L240 hiAutomatonCegarLoop]: Abstraction has 399 states and 501 transitions. [2023-11-12 02:13:14,376 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 102 states. [2023-11-12 02:13:14,377 INFO L428 stractBuchiCegarLoop]: Abstraction has 399 states and 501 transitions. [2023-11-12 02:13:14,377 INFO L335 stractBuchiCegarLoop]: ======== Iteration 15 ============ [2023-11-12 02:13:14,377 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 399 states and 501 transitions. [2023-11-12 02:13:14,379 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1 [2023-11-12 02:13:14,379 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-12 02:13:14,379 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-12 02:13:14,382 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [95, 94, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-12 02:13:14,382 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1] [2023-11-12 02:13:14,383 INFO L748 eck$LassoCheckResult]: Stem: 27037#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(9, 2); 27038#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~post2#1, main_#t~nondet1#1, main_#t~post4#1, main_#t~post5#1, main_#t~nondet3#1, main_~i~0#1, main_~j~0#1;havoc main_~i~0#1;havoc main_~j~0#1; 27043#L26 main_~i~0#1 := 0; 27044#L29-2 havoc main_#t~nondet1#1; 27046#L29 assume !(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1; 27035#L29-3 assume !(main_~i~0#1 >= 100);main_~j~0#1 := 0; 27036#L35-2 havoc main_#t~nondet3#1; 27042#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 27049#L35-2 havoc main_#t~nondet3#1; 27431#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 27430#L35-2 havoc main_#t~nondet3#1; 27429#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 27428#L35-2 havoc main_#t~nondet3#1; 27427#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 27426#L35-2 havoc main_#t~nondet3#1; 27425#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 27424#L35-2 havoc main_#t~nondet3#1; 27423#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 27422#L35-2 havoc main_#t~nondet3#1; 27421#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 27420#L35-2 havoc main_#t~nondet3#1; 27419#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 27418#L35-2 havoc main_#t~nondet3#1; 27417#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 27416#L35-2 havoc main_#t~nondet3#1; 27415#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 27414#L35-2 havoc main_#t~nondet3#1; 27413#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 27412#L35-2 havoc main_#t~nondet3#1; 27411#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 27410#L35-2 havoc main_#t~nondet3#1; 27409#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 27408#L35-2 havoc main_#t~nondet3#1; 27407#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 27406#L35-2 havoc main_#t~nondet3#1; 27405#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 27404#L35-2 havoc main_#t~nondet3#1; 27403#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 27402#L35-2 havoc main_#t~nondet3#1; 27401#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 27400#L35-2 havoc main_#t~nondet3#1; 27399#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 27398#L35-2 havoc main_#t~nondet3#1; 27397#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 27396#L35-2 havoc main_#t~nondet3#1; 27395#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 27394#L35-2 havoc main_#t~nondet3#1; 27393#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 27392#L35-2 havoc main_#t~nondet3#1; 27391#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 27390#L35-2 havoc main_#t~nondet3#1; 27389#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 27388#L35-2 havoc main_#t~nondet3#1; 27387#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 27386#L35-2 havoc main_#t~nondet3#1; 27385#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 27384#L35-2 havoc main_#t~nondet3#1; 27383#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 27382#L35-2 havoc main_#t~nondet3#1; 27381#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 27380#L35-2 havoc main_#t~nondet3#1; 27379#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 27378#L35-2 havoc main_#t~nondet3#1; 27377#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 27376#L35-2 havoc main_#t~nondet3#1; 27375#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 27374#L35-2 havoc main_#t~nondet3#1; 27373#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 27372#L35-2 havoc main_#t~nondet3#1; 27371#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 27370#L35-2 havoc main_#t~nondet3#1; 27369#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 27368#L35-2 havoc main_#t~nondet3#1; 27367#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 27366#L35-2 havoc main_#t~nondet3#1; 27365#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 27364#L35-2 havoc main_#t~nondet3#1; 27363#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 27362#L35-2 havoc main_#t~nondet3#1; 27361#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 27360#L35-2 havoc main_#t~nondet3#1; 27359#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 27358#L35-2 havoc main_#t~nondet3#1; 27357#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 27356#L35-2 havoc main_#t~nondet3#1; 27355#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 27354#L35-2 havoc main_#t~nondet3#1; 27353#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 27352#L35-2 havoc main_#t~nondet3#1; 27351#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 27350#L35-2 havoc main_#t~nondet3#1; 27349#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 27348#L35-2 havoc main_#t~nondet3#1; 27347#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 27346#L35-2 havoc main_#t~nondet3#1; 27345#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 27344#L35-2 havoc main_#t~nondet3#1; 27343#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 27342#L35-2 havoc main_#t~nondet3#1; 27341#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 27340#L35-2 havoc main_#t~nondet3#1; 27339#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 27338#L35-2 havoc main_#t~nondet3#1; 27337#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 27336#L35-2 havoc main_#t~nondet3#1; 27335#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 27334#L35-2 havoc main_#t~nondet3#1; 27333#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 27332#L35-2 havoc main_#t~nondet3#1; 27331#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 27330#L35-2 havoc main_#t~nondet3#1; 27329#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 27328#L35-2 havoc main_#t~nondet3#1; 27327#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 27326#L35-2 havoc main_#t~nondet3#1; 27325#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 27324#L35-2 havoc main_#t~nondet3#1; 27323#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 27322#L35-2 havoc main_#t~nondet3#1; 27321#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 27320#L35-2 havoc main_#t~nondet3#1; 27319#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 27318#L35-2 havoc main_#t~nondet3#1; 27317#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 27316#L35-2 havoc main_#t~nondet3#1; 27315#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 27314#L35-2 havoc main_#t~nondet3#1; 27313#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 27312#L35-2 havoc main_#t~nondet3#1; 27311#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 27310#L35-2 havoc main_#t~nondet3#1; 27309#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 27308#L35-2 havoc main_#t~nondet3#1; 27307#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 27306#L35-2 havoc main_#t~nondet3#1; 27305#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 27304#L35-2 havoc main_#t~nondet3#1; 27303#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 27302#L35-2 havoc main_#t~nondet3#1; 27301#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 27300#L35-2 havoc main_#t~nondet3#1; 27299#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 27298#L35-2 havoc main_#t~nondet3#1; 27297#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 27296#L35-2 havoc main_#t~nondet3#1; 27295#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 27294#L35-2 havoc main_#t~nondet3#1; 27293#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 27292#L35-2 havoc main_#t~nondet3#1; 27291#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 27290#L35-2 havoc main_#t~nondet3#1; 27289#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 27288#L35-2 havoc main_#t~nondet3#1; 27287#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 27286#L35-2 havoc main_#t~nondet3#1; 27285#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 27284#L35-2 havoc main_#t~nondet3#1; 27283#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 27282#L35-2 havoc main_#t~nondet3#1; 27281#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 27280#L35-2 havoc main_#t~nondet3#1; 27279#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 27278#L35-2 havoc main_#t~nondet3#1; 27277#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 27276#L35-2 havoc main_#t~nondet3#1; 27275#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 27274#L35-2 havoc main_#t~nondet3#1; 27273#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 27272#L35-2 havoc main_#t~nondet3#1; 27271#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 27270#L35-2 havoc main_#t~nondet3#1; 27269#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 27268#L35-2 havoc main_#t~nondet3#1; 27267#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 27266#L35-2 havoc main_#t~nondet3#1; 27265#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 27264#L35-2 havoc main_#t~nondet3#1; 27263#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 27262#L35-2 havoc main_#t~nondet3#1; 27261#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 27260#L35-2 havoc main_#t~nondet3#1; 27259#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 27258#L35-2 havoc main_#t~nondet3#1; 27257#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 27256#L35-2 havoc main_#t~nondet3#1; 27255#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 27254#L35-2 havoc main_#t~nondet3#1; 27253#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 27252#L35-2 havoc main_#t~nondet3#1; 27251#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 27250#L35-2 havoc main_#t~nondet3#1; 27249#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 27248#L35-2 havoc main_#t~nondet3#1; 27247#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 27246#L35-2 havoc main_#t~nondet3#1; 27048#L35 assume !(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1; 27045#L35-3 assume main_~j~0#1 >= 100; 27034#L32 [2023-11-12 02:13:14,383 INFO L750 eck$LassoCheckResult]: Loop: 27034#L32 assume true; 27034#L32 [2023-11-12 02:13:14,384 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-12 02:13:14,384 INFO L85 PathProgramCache]: Analyzing trace with hash 1679145147, now seen corresponding path program 6 times [2023-11-12 02:13:14,384 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-12 02:13:14,384 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2138468976] [2023-11-12 02:13:14,385 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-12 02:13:14,385 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-12 02:13:14,463 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat