./Ultimate.py --spec ../../sv-benchmarks/c/properties/termination.prp --file ../../sv-benchmarks/c/systemc/token_ring.08.cil-1.c --full-output --architecture 32bit -------------------------------------------------------------------------------- Checking for termination Using default analysis Version cf1a7837 Calling Ultimate with: /usr/lib/jvm/java-11-openjdk-amd64/bin/java -Dosgi.configuration.area=/tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_97b04cac-bb3a-4255-97fa-d23bd21448ea/bin/uautomizer-verify-uTZkv6EMXl/data/config -Xmx15G -Xms4m -jar /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_97b04cac-bb3a-4255-97fa-d23bd21448ea/bin/uautomizer-verify-uTZkv6EMXl/plugins/org.eclipse.equinox.launcher_1.5.800.v20200727-1323.jar -data @noDefault -ultimatedata /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_97b04cac-bb3a-4255-97fa-d23bd21448ea/bin/uautomizer-verify-uTZkv6EMXl/data -tc /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_97b04cac-bb3a-4255-97fa-d23bd21448ea/bin/uautomizer-verify-uTZkv6EMXl/config/AutomizerTermination.xml -i ../../sv-benchmarks/c/systemc/token_ring.08.cil-1.c -s /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_97b04cac-bb3a-4255-97fa-d23bd21448ea/bin/uautomizer-verify-uTZkv6EMXl/config/svcomp-Termination-32bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_97b04cac-bb3a-4255-97fa-d23bd21448ea/bin/uautomizer-verify-uTZkv6EMXl --witnessprinter.witness.filename witness --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(F end) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 32bit --witnessprinter.graph.data.programhash 42e706fd1a5bd201d46dd2f3322f156b6d900789b8c9ace16cba5458f69fdc62 --- Real Ultimate output --- This is Ultimate 0.2.3-dev-cf1a783 [2023-11-12 02:34:09,264 INFO L188 SettingsManager]: Resetting all preferences to default values... [2023-11-12 02:34:09,377 INFO L114 SettingsManager]: Loading settings from /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_97b04cac-bb3a-4255-97fa-d23bd21448ea/bin/uautomizer-verify-uTZkv6EMXl/config/svcomp-Termination-32bit-Automizer_Default.epf [2023-11-12 02:34:09,384 WARN L101 SettingsManager]: Preference file contains the following unknown settings: [2023-11-12 02:34:09,385 WARN L103 SettingsManager]: * de.uni_freiburg.informatik.ultimate.core.Log level for class [2023-11-12 02:34:09,422 INFO L130 SettingsManager]: Preferences different from defaults after loading the file: [2023-11-12 02:34:09,423 INFO L151 SettingsManager]: Preferences of UltimateCore differ from their defaults: [2023-11-12 02:34:09,423 INFO L153 SettingsManager]: * Log level for class=de.uni_freiburg.informatik.ultimate.lib.smtlibutils.quantifier.QuantifierPusher=ERROR; [2023-11-12 02:34:09,425 INFO L151 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2023-11-12 02:34:09,429 INFO L153 SettingsManager]: * Create parallel compositions if possible=false [2023-11-12 02:34:09,430 INFO L153 SettingsManager]: * Use SBE=true [2023-11-12 02:34:09,431 INFO L151 SettingsManager]: Preferences of BuchiAutomizer differ from their defaults: [2023-11-12 02:34:09,431 INFO L153 SettingsManager]: * NCSB implementation=INTSET_LAZY3 [2023-11-12 02:34:09,433 INFO L153 SettingsManager]: * Use old map elimination=false [2023-11-12 02:34:09,433 INFO L153 SettingsManager]: * Use external solver (rank synthesis)=false [2023-11-12 02:34:09,433 INFO L153 SettingsManager]: * Use only trivial implications for array writes=true [2023-11-12 02:34:09,434 INFO L153 SettingsManager]: * Rank analysis=LINEAR_WITH_GUESSES [2023-11-12 02:34:09,435 INFO L151 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2023-11-12 02:34:09,435 INFO L153 SettingsManager]: * Pointer base address is valid at dereference=ASSUME [2023-11-12 02:34:09,435 INFO L153 SettingsManager]: * sizeof long=4 [2023-11-12 02:34:09,436 INFO L153 SettingsManager]: * Overapproximate operations on floating types=true [2023-11-12 02:34:09,436 INFO L153 SettingsManager]: * sizeof POINTER=4 [2023-11-12 02:34:09,437 INFO L153 SettingsManager]: * Check division by zero=IGNORE [2023-11-12 02:34:09,437 INFO L153 SettingsManager]: * Pointer to allocated memory at dereference=ASSUME [2023-11-12 02:34:09,437 INFO L153 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=ASSUME [2023-11-12 02:34:09,438 INFO L153 SettingsManager]: * Check array bounds for arrays that are off heap=ASSUME [2023-11-12 02:34:09,438 INFO L153 SettingsManager]: * Check unreachability of reach_error function=false [2023-11-12 02:34:09,438 INFO L153 SettingsManager]: * sizeof long double=12 [2023-11-12 02:34:09,439 INFO L153 SettingsManager]: * Check if freed pointer was valid=false [2023-11-12 02:34:09,439 INFO L153 SettingsManager]: * Assume nondeterminstic values are in range=false [2023-11-12 02:34:09,440 INFO L153 SettingsManager]: * Use constant arrays=true [2023-11-12 02:34:09,441 INFO L151 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2023-11-12 02:34:09,441 INFO L153 SettingsManager]: * Size of a code block=SequenceOfStatements [2023-11-12 02:34:09,441 INFO L151 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2023-11-12 02:34:09,441 INFO L153 SettingsManager]: * Trace refinement strategy=CAMEL [2023-11-12 02:34:09,442 INFO L151 SettingsManager]: Preferences of IcfgTransformer differ from their defaults: [2023-11-12 02:34:09,442 INFO L153 SettingsManager]: * TransformationType=MODULO_NEIGHBOR WARNING: An illegal reflective access operation has occurred WARNING: Illegal reflective access by com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 (file:/tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_97b04cac-bb3a-4255-97fa-d23bd21448ea/bin/uautomizer-verify-uTZkv6EMXl/plugins/com.sun.xml.bind_2.2.0.v201505121915.jar) to method java.lang.ClassLoader.defineClass(java.lang.String,byte[],int,int) WARNING: Please consider reporting this to the maintainers of com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 WARNING: Use --illegal-access=warn to enable warnings of further illegal reflective access operations WARNING: All illegal access operations will be denied in a future release Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_97b04cac-bb3a-4255-97fa-d23bd21448ea/bin/uautomizer-verify-uTZkv6EMXl Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(F end) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 32bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> 42e706fd1a5bd201d46dd2f3322f156b6d900789b8c9ace16cba5458f69fdc62 [2023-11-12 02:34:09,697 INFO L75 nceAwareModelManager]: Repository-Root is: /tmp [2023-11-12 02:34:09,721 INFO L261 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2023-11-12 02:34:09,725 INFO L217 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2023-11-12 02:34:09,726 INFO L270 PluginConnector]: Initializing CDTParser... [2023-11-12 02:34:09,727 INFO L274 PluginConnector]: CDTParser initialized [2023-11-12 02:34:09,728 INFO L431 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_97b04cac-bb3a-4255-97fa-d23bd21448ea/bin/uautomizer-verify-uTZkv6EMXl/../../sv-benchmarks/c/systemc/token_ring.08.cil-1.c [2023-11-12 02:34:12,663 INFO L533 CDTParser]: Created temporary CDT project at NULL [2023-11-12 02:34:13,031 INFO L384 CDTParser]: Found 1 translation units. [2023-11-12 02:34:13,033 INFO L180 CDTParser]: Scanning /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_97b04cac-bb3a-4255-97fa-d23bd21448ea/sv-benchmarks/c/systemc/token_ring.08.cil-1.c [2023-11-12 02:34:13,052 INFO L427 CDTParser]: About to delete temporary CDT project at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_97b04cac-bb3a-4255-97fa-d23bd21448ea/bin/uautomizer-verify-uTZkv6EMXl/data/aa8af85ae/3379fc620f754825b0d648b3576e38f1/FLAG91a6bc04c [2023-11-12 02:34:13,067 INFO L435 CDTParser]: Successfully deleted /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_97b04cac-bb3a-4255-97fa-d23bd21448ea/bin/uautomizer-verify-uTZkv6EMXl/data/aa8af85ae/3379fc620f754825b0d648b3576e38f1 [2023-11-12 02:34:13,069 INFO L299 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2023-11-12 02:34:13,071 INFO L133 ToolchainWalker]: Walking toolchain with 6 elements. [2023-11-12 02:34:13,073 INFO L112 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2023-11-12 02:34:13,073 INFO L270 PluginConnector]: Initializing CACSL2BoogieTranslator... [2023-11-12 02:34:13,080 INFO L274 PluginConnector]: CACSL2BoogieTranslator initialized [2023-11-12 02:34:13,081 INFO L184 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 12.11 02:34:13" (1/1) ... [2023-11-12 02:34:13,081 INFO L204 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@e40b351 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 12.11 02:34:13, skipping insertion in model container [2023-11-12 02:34:13,082 INFO L184 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 12.11 02:34:13" (1/1) ... [2023-11-12 02:34:13,149 INFO L177 MainTranslator]: Built tables and reachable declarations [2023-11-12 02:34:13,402 INFO L209 PostProcessor]: Analyzing one entry point: main [2023-11-12 02:34:13,417 INFO L202 MainTranslator]: Completed pre-run [2023-11-12 02:34:13,498 INFO L209 PostProcessor]: Analyzing one entry point: main [2023-11-12 02:34:13,520 INFO L206 MainTranslator]: Completed translation [2023-11-12 02:34:13,521 INFO L201 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 12.11 02:34:13 WrapperNode [2023-11-12 02:34:13,521 INFO L131 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2023-11-12 02:34:13,523 INFO L112 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2023-11-12 02:34:13,523 INFO L270 PluginConnector]: Initializing Boogie Procedure Inliner... [2023-11-12 02:34:13,523 INFO L274 PluginConnector]: Boogie Procedure Inliner initialized [2023-11-12 02:34:13,530 INFO L184 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 12.11 02:34:13" (1/1) ... [2023-11-12 02:34:13,544 INFO L184 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 12.11 02:34:13" (1/1) ... [2023-11-12 02:34:13,649 INFO L138 Inliner]: procedures = 44, calls = 56, calls flagged for inlining = 51, calls inlined = 158, statements flattened = 2377 [2023-11-12 02:34:13,650 INFO L131 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2023-11-12 02:34:13,651 INFO L112 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2023-11-12 02:34:13,651 INFO L270 PluginConnector]: Initializing Boogie Preprocessor... [2023-11-12 02:34:13,651 INFO L274 PluginConnector]: Boogie Preprocessor initialized [2023-11-12 02:34:13,663 INFO L184 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 12.11 02:34:13" (1/1) ... [2023-11-12 02:34:13,663 INFO L184 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 12.11 02:34:13" (1/1) ... [2023-11-12 02:34:13,675 INFO L184 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 12.11 02:34:13" (1/1) ... [2023-11-12 02:34:13,676 INFO L184 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 12.11 02:34:13" (1/1) ... [2023-11-12 02:34:13,717 INFO L184 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 12.11 02:34:13" (1/1) ... [2023-11-12 02:34:13,769 INFO L184 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 12.11 02:34:13" (1/1) ... [2023-11-12 02:34:13,775 INFO L184 PluginConnector]: Executing the observer LTLStepAnnotator from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 12.11 02:34:13" (1/1) ... [2023-11-12 02:34:13,793 INFO L184 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 12.11 02:34:13" (1/1) ... [2023-11-12 02:34:13,812 INFO L131 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2023-11-12 02:34:13,813 INFO L112 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2023-11-12 02:34:13,813 INFO L270 PluginConnector]: Initializing RCFGBuilder... [2023-11-12 02:34:13,814 INFO L274 PluginConnector]: RCFGBuilder initialized [2023-11-12 02:34:13,815 INFO L184 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 12.11 02:34:13" (1/1) ... [2023-11-12 02:34:13,822 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2023-11-12 02:34:13,835 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_97b04cac-bb3a-4255-97fa-d23bd21448ea/bin/uautomizer-verify-uTZkv6EMXl/z3 [2023-11-12 02:34:13,849 INFO L229 MonitoredProcess]: Starting monitored process 1 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_97b04cac-bb3a-4255-97fa-d23bd21448ea/bin/uautomizer-verify-uTZkv6EMXl/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2023-11-12 02:34:13,874 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_97b04cac-bb3a-4255-97fa-d23bd21448ea/bin/uautomizer-verify-uTZkv6EMXl/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (1)] Waiting until timeout for monitored process [2023-11-12 02:34:13,896 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocInit [2023-11-12 02:34:13,896 INFO L130 BoogieDeclarations]: Found specification of procedure write~init~int [2023-11-12 02:34:13,896 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2023-11-12 02:34:13,896 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2023-11-12 02:34:14,038 INFO L236 CfgBuilder]: Building ICFG [2023-11-12 02:34:14,041 INFO L262 CfgBuilder]: Building CFG for each procedure with an implementation [2023-11-12 02:34:15,913 INFO L277 CfgBuilder]: Performing block encoding [2023-11-12 02:34:15,940 INFO L297 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2023-11-12 02:34:15,941 INFO L302 CfgBuilder]: Removed 11 assume(true) statements. [2023-11-12 02:34:15,945 INFO L201 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 12.11 02:34:15 BoogieIcfgContainer [2023-11-12 02:34:15,945 INFO L131 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2023-11-12 02:34:15,947 INFO L112 PluginConnector]: ------------------------BuchiAutomizer---------------------------- [2023-11-12 02:34:15,948 INFO L270 PluginConnector]: Initializing BuchiAutomizer... [2023-11-12 02:34:15,952 INFO L274 PluginConnector]: BuchiAutomizer initialized [2023-11-12 02:34:15,952 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2023-11-12 02:34:15,953 INFO L184 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "CDTParser AST 12.11 02:34:13" (1/3) ... [2023-11-12 02:34:15,953 INFO L204 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@46795cf3 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 12.11 02:34:15, skipping insertion in model container [2023-11-12 02:34:15,953 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2023-11-12 02:34:15,954 INFO L184 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 12.11 02:34:13" (2/3) ... [2023-11-12 02:34:15,954 INFO L204 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@46795cf3 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 12.11 02:34:15, skipping insertion in model container [2023-11-12 02:34:15,954 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2023-11-12 02:34:15,954 INFO L184 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 12.11 02:34:15" (3/3) ... [2023-11-12 02:34:15,955 INFO L332 chiAutomizerObserver]: Analyzing ICFG token_ring.08.cil-1.c [2023-11-12 02:34:16,040 INFO L303 stractBuchiCegarLoop]: Interprodecural is true [2023-11-12 02:34:16,040 INFO L304 stractBuchiCegarLoop]: Hoare is false [2023-11-12 02:34:16,040 INFO L305 stractBuchiCegarLoop]: Compute interpolants for ForwardPredicates [2023-11-12 02:34:16,041 INFO L306 stractBuchiCegarLoop]: Backedges is STRAIGHT_LINE [2023-11-12 02:34:16,041 INFO L307 stractBuchiCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2023-11-12 02:34:16,041 INFO L308 stractBuchiCegarLoop]: Difference is false [2023-11-12 02:34:16,041 INFO L309 stractBuchiCegarLoop]: Minimize is MINIMIZE_SEVPA [2023-11-12 02:34:16,041 INFO L313 stractBuchiCegarLoop]: ======== Iteration 0 == of CEGAR loop == BuchiAutomatonCegarLoop ======== [2023-11-12 02:34:16,051 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 1009 states, 1008 states have (on average 1.5089285714285714) internal successors, (1521), 1008 states have internal predecessors, (1521), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-12 02:34:16,122 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 890 [2023-11-12 02:34:16,123 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-12 02:34:16,123 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-12 02:34:16,139 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-12 02:34:16,140 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-12 02:34:16,140 INFO L335 stractBuchiCegarLoop]: ======== Iteration 1 ============ [2023-11-12 02:34:16,143 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 1009 states, 1008 states have (on average 1.5089285714285714) internal successors, (1521), 1008 states have internal predecessors, (1521), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-12 02:34:16,165 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 890 [2023-11-12 02:34:16,166 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-12 02:34:16,166 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-12 02:34:16,173 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-12 02:34:16,174 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-12 02:34:16,185 INFO L748 eck$LassoCheckResult]: Stem: 155#$Ultimate##0true assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~token~0 := 0;~local~0 := 0; 920#L-1true assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~10#1;havoc main_~__retres1~10#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; 743#init_model_returnLabel#1true assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret25#1, start_simulation_#t~ret26#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 916#update_channels_returnLabel#1true assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 867#L597true assume !(1 == ~m_i~0);~m_st~0 := 2; 447#L597-2true assume 1 == ~t1_i~0;~t1_st~0 := 0; 987#L602-1true assume !(1 == ~t2_i~0);~t2_st~0 := 2; 163#L607-1true assume !(1 == ~t3_i~0);~t3_st~0 := 2; 494#L612-1true assume !(1 == ~t4_i~0);~t4_st~0 := 2; 129#L617-1true assume !(1 == ~t5_i~0);~t5_st~0 := 2; 284#L622-1true assume !(1 == ~t6_i~0);~t6_st~0 := 2; 970#L627-1true assume !(1 == ~t7_i~0);~t7_st~0 := 2; 265#L632-1true assume !(1 == ~t8_i~0);~t8_st~0 := 2; 567#L637-1true assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 504#L854true assume !(0 == ~M_E~0); 332#L854-2true assume !(0 == ~T1_E~0); 639#L859-1true assume !(0 == ~T2_E~0); 68#L864-1true assume !(0 == ~T3_E~0); 123#L869-1true assume !(0 == ~T4_E~0); 877#L874-1true assume 0 == ~T5_E~0;~T5_E~0 := 1; 815#L879-1true assume !(0 == ~T6_E~0); 325#L884-1true assume !(0 == ~T7_E~0); 8#L889-1true assume !(0 == ~T8_E~0); 171#L894-1true assume !(0 == ~E_M~0); 981#L899-1true assume !(0 == ~E_1~0); 509#L904-1true assume !(0 == ~E_2~0); 277#L909-1true assume !(0 == ~E_3~0); 438#L914-1true assume 0 == ~E_4~0;~E_4~0 := 1; 463#L919-1true assume !(0 == ~E_5~0); 218#L924-1true assume !(0 == ~E_6~0); 115#L929-1true assume !(0 == ~E_7~0); 834#L934-1true assume !(0 == ~E_8~0); 263#L939-1true assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 16#L418true assume !(1 == ~m_pc~0); 903#L418-2true is_master_triggered_~__retres1~0#1 := 0; 717#L429true is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 642#is_master_triggered_returnLabel#1true activate_threads_#t~ret15#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 626#L1061true assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 532#L1061-2true assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 890#L437true assume 1 == ~t1_pc~0; 974#L438true assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 632#L448true is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 27#is_transmit1_triggered_returnLabel#1true activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 188#L1069true assume !(0 != activate_threads_~tmp___0~0#1); 826#L1069-2true assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 617#L456true assume !(1 == ~t2_pc~0); 436#L456-2true is_transmit2_triggered_~__retres1~2#1 := 0; 882#L467true is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 240#is_transmit2_triggered_returnLabel#1true activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 661#L1077true assume !(0 != activate_threads_~tmp___1~0#1); 358#L1077-2true assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 66#L475true assume 1 == ~t3_pc~0; 298#L476true assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 97#L486true is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 12#is_transmit3_triggered_returnLabel#1true activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 797#L1085true assume !(0 != activate_threads_~tmp___2~0#1); 190#L1085-2true assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 713#L494true assume !(1 == ~t4_pc~0); 214#L494-2true is_transmit4_triggered_~__retres1~4#1 := 0; 417#L505true is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 73#is_transmit4_triggered_returnLabel#1true activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 953#L1093true assume !(0 != activate_threads_~tmp___3~0#1); 460#L1093-2true assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 95#L513true assume 1 == ~t5_pc~0; 584#L514true assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 911#L524true is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 645#is_transmit5_triggered_returnLabel#1true activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 71#L1101true assume !(0 != activate_threads_~tmp___4~0#1); 895#L1101-2true assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 51#L532true assume !(1 == ~t6_pc~0); 407#L532-2true is_transmit6_triggered_~__retres1~6#1 := 0; 303#L543true is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 227#is_transmit6_triggered_returnLabel#1true activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 849#L1109true assume !(0 != activate_threads_~tmp___5~0#1); 175#L1109-2true assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 665#L551true assume 1 == ~t7_pc~0; 675#L552true assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 465#L562true is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 934#is_transmit7_triggered_returnLabel#1true activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 1007#L1117true assume !(0 != activate_threads_~tmp___6~0#1); 945#L1117-2true assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 292#L570true assume 1 == ~t8_pc~0; 379#L571true assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 749#L581true is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 585#is_transmit8_triggered_returnLabel#1true activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 376#L1125true assume !(0 != activate_threads_~tmp___7~0#1); 63#L1125-2true havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 636#L952true assume 1 == ~M_E~0;~M_E~0 := 2; 38#L952-2true assume !(1 == ~T1_E~0); 597#L957-1true assume !(1 == ~T2_E~0); 899#L962-1true assume !(1 == ~T3_E~0); 391#L967-1true assume !(1 == ~T4_E~0); 869#L972-1true assume !(1 == ~T5_E~0); 668#L977-1true assume !(1 == ~T6_E~0); 950#L982-1true assume !(1 == ~T7_E~0); 126#L987-1true assume 1 == ~T8_E~0;~T8_E~0 := 2; 130#L992-1true assume !(1 == ~E_M~0); 356#L997-1true assume !(1 == ~E_1~0); 821#L1002-1true assume !(1 == ~E_2~0); 346#L1007-1true assume !(1 == ~E_3~0); 9#L1012-1true assume !(1 == ~E_4~0); 564#L1017-1true assume !(1 == ~E_5~0); 349#L1022-1true assume !(1 == ~E_6~0); 370#L1027-1true assume 1 == ~E_7~0;~E_7~0 := 2; 823#L1032-1true assume !(1 == ~E_8~0); 487#L1037-1true assume { :end_inline_reset_delta_events } true; 588#L1303-2true [2023-11-12 02:34:16,188 INFO L750 eck$LassoCheckResult]: Loop: 588#L1303-2true assume !false; 627#L1304true start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 982#L829-1true assume !true; 589#eval_returnLabel#1true havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 375#update_channels_returnLabel#2true assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 475#L854-3true assume !(0 == ~M_E~0); 453#L854-5true assume 0 == ~T1_E~0;~T1_E~0 := 1; 965#L859-3true assume 0 == ~T2_E~0;~T2_E~0 := 1; 926#L864-3true assume 0 == ~T3_E~0;~T3_E~0 := 1; 809#L869-3true assume 0 == ~T4_E~0;~T4_E~0 := 1; 304#L874-3true assume 0 == ~T5_E~0;~T5_E~0 := 1; 357#L879-3true assume 0 == ~T6_E~0;~T6_E~0 := 1; 390#L884-3true assume 0 == ~T7_E~0;~T7_E~0 := 1; 342#L889-3true assume !(0 == ~T8_E~0); 110#L894-3true assume 0 == ~E_M~0;~E_M~0 := 1; 499#L899-3true assume 0 == ~E_1~0;~E_1~0 := 1; 128#L904-3true assume 0 == ~E_2~0;~E_2~0 := 1; 323#L909-3true assume 0 == ~E_3~0;~E_3~0 := 1; 100#L914-3true assume 0 == ~E_4~0;~E_4~0 := 1; 121#L919-3true assume 0 == ~E_5~0;~E_5~0 := 1; 730#L924-3true assume 0 == ~E_6~0;~E_6~0 := 1; 537#L929-3true assume !(0 == ~E_7~0); 440#L934-3true assume 0 == ~E_8~0;~E_8~0 := 1; 670#L939-3true assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 569#L418-30true assume !(1 == ~m_pc~0); 384#L418-32true is_master_triggered_~__retres1~0#1 := 0; 581#L429-10true is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 249#is_master_triggered_returnLabel#11true activate_threads_#t~ret15#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 839#L1061-30true assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 146#L1061-32true assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 216#L437-30true assume !(1 == ~t1_pc~0); 679#L437-32true is_transmit1_triggered_~__retres1~1#1 := 0; 374#L448-10true is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 402#is_transmit1_triggered_returnLabel#11true activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 909#L1069-30true assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 883#L1069-32true assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 193#L456-30true assume 1 == ~t2_pc~0; 719#L457-10true assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 527#L467-10true is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 192#is_transmit2_triggered_returnLabel#11true activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 89#L1077-30true assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 285#L1077-32true assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 766#L475-30true assume !(1 == ~t3_pc~0); 30#L475-32true is_transmit3_triggered_~__retres1~3#1 := 0; 452#L486-10true is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 389#is_transmit3_triggered_returnLabel#11true activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 901#L1085-30true assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 206#L1085-32true assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 999#L494-30true assume 1 == ~t4_pc~0; 200#L495-10true assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 3#L505-10true is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 833#is_transmit4_triggered_returnLabel#11true activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 919#L1093-30true assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 698#L1093-32true assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 956#L513-30true assume 1 == ~t5_pc~0; 988#L514-10true assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 340#L524-10true is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 474#is_transmit5_triggered_returnLabel#11true activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 552#L1101-30true assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 796#L1101-32true assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 295#L532-30true assume 1 == ~t6_pc~0; 957#L533-10true assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 65#L543-10true is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 77#is_transmit6_triggered_returnLabel#11true activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 629#L1109-30true assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 105#L1109-32true assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 133#L551-30true assume 1 == ~t7_pc~0; 165#L552-10true assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 643#L562-10true is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 540#is_transmit7_triggered_returnLabel#11true activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 10#L1117-30true assume !(0 != activate_threads_~tmp___6~0#1); 191#L1117-32true assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 758#L570-30true assume 1 == ~t8_pc~0; 634#L571-10true assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 131#L581-10true is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 973#is_transmit8_triggered_returnLabel#11true activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 36#L1125-30true assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 236#L1125-32true havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 261#L952-3true assume 1 == ~M_E~0;~M_E~0 := 2; 958#L952-5true assume 1 == ~T1_E~0;~T1_E~0 := 2; 752#L957-3true assume 1 == ~T2_E~0;~T2_E~0 := 2; 769#L962-3true assume !(1 == ~T3_E~0); 615#L967-3true assume 1 == ~T4_E~0;~T4_E~0 := 2; 800#L972-3true assume 1 == ~T5_E~0;~T5_E~0 := 2; 508#L977-3true assume 1 == ~T6_E~0;~T6_E~0 := 2; 996#L982-3true assume 1 == ~T7_E~0;~T7_E~0 := 2; 977#L987-3true assume 1 == ~T8_E~0;~T8_E~0 := 2; 226#L992-3true assume 1 == ~E_M~0;~E_M~0 := 2; 365#L997-3true assume 1 == ~E_1~0;~E_1~0 := 2; 224#L1002-3true assume !(1 == ~E_2~0); 464#L1007-3true assume 1 == ~E_3~0;~E_3~0 := 2; 117#L1012-3true assume 1 == ~E_4~0;~E_4~0 := 2; 170#L1017-3true assume 1 == ~E_5~0;~E_5~0 := 2; 324#L1022-3true assume 1 == ~E_6~0;~E_6~0 := 2; 347#L1027-3true assume 1 == ~E_7~0;~E_7~0 := 2; 23#L1032-3true assume 1 == ~E_8~0;~E_8~0 := 2; 434#L1037-3true assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 141#L650-1true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 768#L697-1true exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 205#exists_runnable_thread_returnLabel#2true start_simulation_#t~ret25#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret25#1;havoc start_simulation_#t~ret25#1; 830#L1322true assume !(0 == start_simulation_~tmp~3#1); 246#L1322-2true assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret24#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 61#L650-2true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 753#L697-2true exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 25#exists_runnable_thread_returnLabel#3true stop_simulation_#t~ret24#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret24#1;havoc stop_simulation_#t~ret24#1; 17#L1277true assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 510#L1284true stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 388#stop_simulation_returnLabel#1true start_simulation_#t~ret26#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret24#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret26#1;havoc start_simulation_#t~ret26#1; 673#L1335true assume !(0 != start_simulation_~tmp___0~1#1); 588#L1303-2true [2023-11-12 02:34:16,195 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-12 02:34:16,196 INFO L85 PathProgramCache]: Analyzing trace with hash -1103313420, now seen corresponding path program 1 times [2023-11-12 02:34:16,206 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-12 02:34:16,207 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [777595400] [2023-11-12 02:34:16,207 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-12 02:34:16,208 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-12 02:34:16,362 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-12 02:34:16,602 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-12 02:34:16,603 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-12 02:34:16,603 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [777595400] [2023-11-12 02:34:16,604 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [777595400] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-12 02:34:16,604 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-12 02:34:16,605 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-12 02:34:16,607 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1917282030] [2023-11-12 02:34:16,607 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-12 02:34:16,614 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-12 02:34:16,615 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-12 02:34:16,616 INFO L85 PathProgramCache]: Analyzing trace with hash -118307812, now seen corresponding path program 1 times [2023-11-12 02:34:16,616 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-12 02:34:16,616 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [744670630] [2023-11-12 02:34:16,616 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-12 02:34:16,617 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-12 02:34:16,642 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-12 02:34:16,697 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-12 02:34:16,699 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-12 02:34:16,700 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [744670630] [2023-11-12 02:34:16,700 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [744670630] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-12 02:34:16,700 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-12 02:34:16,700 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2023-11-12 02:34:16,700 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1094547263] [2023-11-12 02:34:16,701 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-12 02:34:16,702 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-12 02:34:16,702 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-12 02:34:16,742 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-12 02:34:16,743 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-12 02:34:16,748 INFO L87 Difference]: Start difference. First operand has 1009 states, 1008 states have (on average 1.5089285714285714) internal successors, (1521), 1008 states have internal predecessors, (1521), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand has 3 states, 3 states have (on average 35.333333333333336) internal successors, (106), 3 states have internal predecessors, (106), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-12 02:34:16,886 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-12 02:34:16,886 INFO L93 Difference]: Finished difference Result 1007 states and 1495 transitions. [2023-11-12 02:34:16,888 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1007 states and 1495 transitions. [2023-11-12 02:34:16,906 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 887 [2023-11-12 02:34:16,926 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1007 states to 1002 states and 1490 transitions. [2023-11-12 02:34:16,927 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1002 [2023-11-12 02:34:16,930 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1002 [2023-11-12 02:34:16,931 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1002 states and 1490 transitions. [2023-11-12 02:34:16,944 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-12 02:34:16,944 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1002 states and 1490 transitions. [2023-11-12 02:34:16,966 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1002 states and 1490 transitions. [2023-11-12 02:34:17,037 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1002 to 1002. [2023-11-12 02:34:17,041 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1002 states, 1002 states have (on average 1.4870259481037924) internal successors, (1490), 1001 states have internal predecessors, (1490), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-12 02:34:17,046 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1002 states to 1002 states and 1490 transitions. [2023-11-12 02:34:17,047 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1002 states and 1490 transitions. [2023-11-12 02:34:17,049 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-12 02:34:17,052 INFO L428 stractBuchiCegarLoop]: Abstraction has 1002 states and 1490 transitions. [2023-11-12 02:34:17,053 INFO L335 stractBuchiCegarLoop]: ======== Iteration 2 ============ [2023-11-12 02:34:17,053 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1002 states and 1490 transitions. [2023-11-12 02:34:17,061 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 887 [2023-11-12 02:34:17,062 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-12 02:34:17,062 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-12 02:34:17,066 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-12 02:34:17,066 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-12 02:34:17,067 INFO L748 eck$LassoCheckResult]: Stem: 2347#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~token~0 := 0;~local~0 := 0; 2348#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~10#1;havoc main_~__retres1~10#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; 2972#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret25#1, start_simulation_#t~ret26#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 2973#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 3011#L597 assume 1 == ~m_i~0;~m_st~0 := 0; 2766#L597-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 2767#L602-1 assume !(1 == ~t2_i~0);~t2_st~0 := 2; 2364#L607-1 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 2365#L612-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 2297#L617-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 2298#L622-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 2560#L627-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 2532#L632-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 2533#L637-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 2816#L854 assume !(0 == ~M_E~0); 2623#L854-2 assume !(0 == ~T1_E~0); 2624#L859-1 assume !(0 == ~T2_E~0); 2177#L864-1 assume !(0 == ~T3_E~0); 2178#L869-1 assume !(0 == ~T4_E~0); 2288#L874-1 assume 0 == ~T5_E~0;~T5_E~0 := 1; 2997#L879-1 assume !(0 == ~T6_E~0); 2613#L884-1 assume !(0 == ~T7_E~0); 2040#L889-1 assume !(0 == ~T8_E~0); 2041#L894-1 assume !(0 == ~E_M~0); 2377#L899-1 assume !(0 == ~E_1~0); 2822#L904-1 assume !(0 == ~E_2~0); 2550#L909-1 assume !(0 == ~E_3~0); 2551#L914-1 assume 0 == ~E_4~0;~E_4~0 := 1; 2757#L919-1 assume !(0 == ~E_5~0); 2456#L924-1 assume !(0 == ~E_6~0); 2270#L929-1 assume !(0 == ~E_7~0); 2271#L934-1 assume !(0 == ~E_8~0); 2529#L939-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 2057#L418 assume !(1 == ~m_pc~0); 2032#L418-2 is_master_triggered_~__retres1~0#1 := 0; 2031#L429 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 2926#is_master_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 2912#L1061 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 2845#L1061-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 2846#L437 assume 1 == ~t1_pc~0; 3014#L438 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 2919#L448 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 2080#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 2081#L1069 assume !(0 != activate_threads_~tmp___0~0#1); 2406#L1069-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 2902#L456 assume !(1 == ~t2_pc~0); 2328#L456-2 is_transmit2_triggered_~__retres1~2#1 := 0; 2327#L467 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 2488#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 2489#L1077 assume !(0 != activate_threads_~tmp___1~0#1); 2661#L1077-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 2171#L475 assume 1 == ~t3_pc~0; 2172#L476 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 2235#L486 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 2048#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 2049#L1085 assume !(0 != activate_threads_~tmp___2~0#1); 2409#L1085-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 2410#L494 assume !(1 == ~t4_pc~0); 2450#L494-2 is_transmit4_triggered_~__retres1~4#1 := 0; 2451#L505 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 2187#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 2188#L1093 assume !(0 != activate_threads_~tmp___3~0#1); 2781#L1093-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 2230#L513 assume 1 == ~t5_pc~0; 2231#L514 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 2452#L524 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 2928#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 2184#L1101 assume !(0 != activate_threads_~tmp___4~0#1); 2185#L1101-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 2137#L532 assume !(1 == ~t6_pc~0); 2138#L532-2 is_transmit6_triggered_~__retres1~6#1 := 0; 2289#L543 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 2470#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 2471#L1109 assume !(0 != activate_threads_~tmp___5~0#1); 2381#L1109-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 2382#L551 assume 1 == ~t7_pc~0; 2939#L552 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 2783#L562 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 2784#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 3023#L1117 assume !(0 != activate_threads_~tmp___6~0#1); 3024#L1117-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 2571#L570 assume 1 == ~t8_pc~0; 2572#L571 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 2687#L581 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 2877#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 2683#L1125 assume !(0 != activate_threads_~tmp___7~0#1); 2165#L1125-2 havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 2166#L952 assume 1 == ~M_E~0;~M_E~0 := 2; 2106#L952-2 assume !(1 == ~T1_E~0); 2107#L957-1 assume !(1 == ~T2_E~0); 2883#L962-1 assume !(1 == ~T3_E~0); 2699#L967-1 assume !(1 == ~T4_E~0); 2700#L972-1 assume !(1 == ~T5_E~0); 2942#L977-1 assume !(1 == ~T6_E~0); 2943#L982-1 assume !(1 == ~T7_E~0); 2291#L987-1 assume 1 == ~T8_E~0;~T8_E~0 := 2; 2292#L992-1 assume !(1 == ~E_M~0); 2299#L997-1 assume !(1 == ~E_1~0); 2659#L1002-1 assume !(1 == ~E_2~0); 2644#L1007-1 assume !(1 == ~E_3~0); 2042#L1012-1 assume !(1 == ~E_4~0); 2043#L1017-1 assume !(1 == ~E_5~0); 2647#L1022-1 assume !(1 == ~E_6~0); 2648#L1027-1 assume 1 == ~E_7~0;~E_7~0 := 2; 2673#L1032-1 assume !(1 == ~E_8~0); 2804#L1037-1 assume { :end_inline_reset_delta_events } true; 2805#L1303-2 [2023-11-12 02:34:17,067 INFO L750 eck$LassoCheckResult]: Loop: 2805#L1303-2 assume !false; 2879#L1304 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 2546#L829-1 assume !false; 2842#L708 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 2432#L650 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 2367#L697 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 2510#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 2511#L712 assume !(0 != eval_~tmp~0#1); 2772#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 2681#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 2682#L854-3 assume !(0 == ~M_E~0); 2773#L854-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 2774#L859-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 3022#L864-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 2996#L869-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 2589#L874-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 2590#L879-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 2660#L884-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 2638#L889-3 assume !(0 == ~T8_E~0); 2261#L894-3 assume 0 == ~E_M~0;~E_M~0 := 1; 2262#L899-3 assume 0 == ~E_1~0;~E_1~0 := 1; 2295#L904-3 assume 0 == ~E_2~0;~E_2~0 := 1; 2296#L909-3 assume 0 == ~E_3~0;~E_3~0 := 1; 2240#L914-3 assume 0 == ~E_4~0;~E_4~0 := 1; 2241#L919-3 assume 0 == ~E_5~0;~E_5~0 := 1; 2284#L924-3 assume 0 == ~E_6~0;~E_6~0 := 1; 2848#L929-3 assume !(0 == ~E_7~0); 2759#L934-3 assume 0 == ~E_8~0;~E_8~0 := 1; 2760#L939-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 2867#L418-30 assume 1 == ~m_pc~0; 2124#L419-10 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 2125#L429-10 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 2501#is_master_triggered_returnLabel#11 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 2502#L1061-30 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 2329#L1061-32 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 2330#L437-30 assume 1 == ~t1_pc~0; 2453#L438-10 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 2679#L448-10 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 2680#is_transmit1_triggered_returnLabel#11 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 2717#L1069-30 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 3013#L1069-32 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 2413#L456-30 assume !(1 == ~t2_pc~0); 2414#L456-32 is_transmit2_triggered_~__retres1~2#1 := 0; 2840#L467-10 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 2412#is_transmit2_triggered_returnLabel#11 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 2218#L1077-30 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 2219#L1077-32 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 2561#L475-30 assume 1 == ~t3_pc~0; 2935#L476-10 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 2089#L486-10 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 2697#is_transmit3_triggered_returnLabel#11 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 2698#L1085-30 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 2436#L1085-32 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 2437#L494-30 assume !(1 == ~t4_pc~0); 2245#L494-32 is_transmit4_triggered_~__retres1~4#1 := 0; 2028#L505-10 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 2029#is_transmit4_triggered_returnLabel#11 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 3001#L1093-30 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 2951#L1093-32 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 2952#L513-30 assume 1 == ~t5_pc~0; 3025#L514-10 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 2567#L524-10 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 2636#is_transmit5_triggered_returnLabel#11 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 2793#L1101-30 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 2859#L1101-32 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 2579#L532-30 assume 1 == ~t6_pc~0; 2580#L533-10 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 2169#L543-10 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 2170#is_transmit6_triggered_returnLabel#11 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 2194#L1109-30 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 2250#L1109-32 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 2251#L551-30 assume 1 == ~t7_pc~0; 2304#L552-10 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 2369#L562-10 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 2849#is_transmit7_triggered_returnLabel#11 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 2044#L1117-30 assume !(0 != activate_threads_~tmp___6~0#1); 2045#L1117-32 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 2411#L570-30 assume 1 == ~t8_pc~0; 2920#L571-10 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 2300#L581-10 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 2301#is_transmit8_triggered_returnLabel#11 activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 2102#L1125-30 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 2103#L1125-32 havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 2482#L952-3 assume 1 == ~M_E~0;~M_E~0 := 2; 2526#L952-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 2977#L957-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 2978#L962-3 assume !(1 == ~T3_E~0); 2900#L967-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 2901#L972-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 2820#L977-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 2821#L982-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 3026#L987-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 2468#L992-3 assume 1 == ~E_M~0;~E_M~0 := 2; 2469#L997-3 assume 1 == ~E_1~0;~E_1~0 := 2; 2464#L1002-3 assume !(1 == ~E_2~0); 2465#L1007-3 assume 1 == ~E_3~0;~E_3~0 := 2; 2274#L1012-3 assume 1 == ~E_4~0;~E_4~0 := 2; 2275#L1017-3 assume 1 == ~E_5~0;~E_5~0 := 2; 2376#L1022-3 assume 1 == ~E_6~0;~E_6~0 := 2; 2612#L1027-3 assume 1 == ~E_7~0;~E_7~0 := 2; 2072#L1032-3 assume 1 == ~E_8~0;~E_8~0 := 2; 2073#L1037-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 2318#L650-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 2319#L697-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 2434#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret25#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret25#1;havoc start_simulation_#t~ret25#1; 2435#L1322 assume !(0 == start_simulation_~tmp~3#1); 2496#L1322-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret24#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 2159#L650-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 2160#L697-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 2076#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret24#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret24#1;havoc stop_simulation_#t~ret24#1; 2058#L1277 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 2059#L1284 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 2695#stop_simulation_returnLabel#1 start_simulation_#t~ret26#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret24#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret26#1;havoc start_simulation_#t~ret26#1; 2696#L1335 assume !(0 != start_simulation_~tmp___0~1#1); 2805#L1303-2 [2023-11-12 02:34:17,069 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-12 02:34:17,069 INFO L85 PathProgramCache]: Analyzing trace with hash 763395254, now seen corresponding path program 1 times [2023-11-12 02:34:17,069 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-12 02:34:17,070 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [735258542] [2023-11-12 02:34:17,070 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-12 02:34:17,070 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-12 02:34:17,094 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-12 02:34:17,152 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-12 02:34:17,153 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-12 02:34:17,153 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [735258542] [2023-11-12 02:34:17,153 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [735258542] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-12 02:34:17,153 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-12 02:34:17,153 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-12 02:34:17,154 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1789994238] [2023-11-12 02:34:17,154 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-12 02:34:17,154 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-12 02:34:17,155 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-12 02:34:17,155 INFO L85 PathProgramCache]: Analyzing trace with hash -221898915, now seen corresponding path program 1 times [2023-11-12 02:34:17,155 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-12 02:34:17,156 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [690219261] [2023-11-12 02:34:17,156 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-12 02:34:17,156 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-12 02:34:17,187 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-12 02:34:17,269 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-12 02:34:17,270 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-12 02:34:17,270 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [690219261] [2023-11-12 02:34:17,270 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [690219261] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-12 02:34:17,270 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-12 02:34:17,270 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-12 02:34:17,271 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1178436564] [2023-11-12 02:34:17,271 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-12 02:34:17,271 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-12 02:34:17,272 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-12 02:34:17,272 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-12 02:34:17,272 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-12 02:34:17,273 INFO L87 Difference]: Start difference. First operand 1002 states and 1490 transitions. cyclomatic complexity: 489 Second operand has 3 states, 3 states have (on average 35.333333333333336) internal successors, (106), 3 states have internal predecessors, (106), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-12 02:34:17,306 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-12 02:34:17,306 INFO L93 Difference]: Finished difference Result 1002 states and 1489 transitions. [2023-11-12 02:34:17,306 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1002 states and 1489 transitions. [2023-11-12 02:34:17,315 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 887 [2023-11-12 02:34:17,325 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1002 states to 1002 states and 1489 transitions. [2023-11-12 02:34:17,325 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1002 [2023-11-12 02:34:17,326 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1002 [2023-11-12 02:34:17,327 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1002 states and 1489 transitions. [2023-11-12 02:34:17,330 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-12 02:34:17,330 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1002 states and 1489 transitions. [2023-11-12 02:34:17,333 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1002 states and 1489 transitions. [2023-11-12 02:34:17,349 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1002 to 1002. [2023-11-12 02:34:17,352 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1002 states, 1002 states have (on average 1.4860279441117765) internal successors, (1489), 1001 states have internal predecessors, (1489), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-12 02:34:17,358 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1002 states to 1002 states and 1489 transitions. [2023-11-12 02:34:17,362 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1002 states and 1489 transitions. [2023-11-12 02:34:17,362 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-12 02:34:17,365 INFO L428 stractBuchiCegarLoop]: Abstraction has 1002 states and 1489 transitions. [2023-11-12 02:34:17,365 INFO L335 stractBuchiCegarLoop]: ======== Iteration 3 ============ [2023-11-12 02:34:17,365 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1002 states and 1489 transitions. [2023-11-12 02:34:17,373 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 887 [2023-11-12 02:34:17,374 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-12 02:34:17,374 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-12 02:34:17,378 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-12 02:34:17,383 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-12 02:34:17,385 INFO L748 eck$LassoCheckResult]: Stem: 4358#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~token~0 := 0;~local~0 := 0; 4359#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~10#1;havoc main_~__retres1~10#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; 4983#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret25#1, start_simulation_#t~ret26#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 4984#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 5022#L597 assume 1 == ~m_i~0;~m_st~0 := 0; 4777#L597-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 4778#L602-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 4375#L607-1 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 4376#L612-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 4308#L617-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 4309#L622-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 4571#L627-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 4543#L632-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 4544#L637-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 4827#L854 assume !(0 == ~M_E~0); 4634#L854-2 assume !(0 == ~T1_E~0); 4635#L859-1 assume !(0 == ~T2_E~0); 4188#L864-1 assume !(0 == ~T3_E~0); 4189#L869-1 assume !(0 == ~T4_E~0); 4299#L874-1 assume 0 == ~T5_E~0;~T5_E~0 := 1; 5008#L879-1 assume !(0 == ~T6_E~0); 4624#L884-1 assume !(0 == ~T7_E~0); 4051#L889-1 assume !(0 == ~T8_E~0); 4052#L894-1 assume !(0 == ~E_M~0); 4388#L899-1 assume !(0 == ~E_1~0); 4833#L904-1 assume !(0 == ~E_2~0); 4561#L909-1 assume !(0 == ~E_3~0); 4562#L914-1 assume 0 == ~E_4~0;~E_4~0 := 1; 4768#L919-1 assume !(0 == ~E_5~0); 4467#L924-1 assume !(0 == ~E_6~0); 4281#L929-1 assume !(0 == ~E_7~0); 4282#L934-1 assume !(0 == ~E_8~0); 4540#L939-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 4068#L418 assume !(1 == ~m_pc~0); 4043#L418-2 is_master_triggered_~__retres1~0#1 := 0; 4042#L429 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 4937#is_master_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 4923#L1061 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 4856#L1061-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 4857#L437 assume 1 == ~t1_pc~0; 5025#L438 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 4930#L448 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 4091#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 4092#L1069 assume !(0 != activate_threads_~tmp___0~0#1); 4417#L1069-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 4913#L456 assume !(1 == ~t2_pc~0); 4339#L456-2 is_transmit2_triggered_~__retres1~2#1 := 0; 4338#L467 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 4499#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 4500#L1077 assume !(0 != activate_threads_~tmp___1~0#1); 4672#L1077-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 4182#L475 assume 1 == ~t3_pc~0; 4183#L476 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 4246#L486 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 4059#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 4060#L1085 assume !(0 != activate_threads_~tmp___2~0#1); 4420#L1085-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 4421#L494 assume !(1 == ~t4_pc~0); 4461#L494-2 is_transmit4_triggered_~__retres1~4#1 := 0; 4462#L505 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 4198#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 4199#L1093 assume !(0 != activate_threads_~tmp___3~0#1); 4792#L1093-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 4241#L513 assume 1 == ~t5_pc~0; 4242#L514 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 4463#L524 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 4939#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 4195#L1101 assume !(0 != activate_threads_~tmp___4~0#1); 4196#L1101-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 4148#L532 assume !(1 == ~t6_pc~0); 4149#L532-2 is_transmit6_triggered_~__retres1~6#1 := 0; 4300#L543 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 4481#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 4482#L1109 assume !(0 != activate_threads_~tmp___5~0#1); 4392#L1109-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 4393#L551 assume 1 == ~t7_pc~0; 4950#L552 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 4794#L562 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 4795#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 5034#L1117 assume !(0 != activate_threads_~tmp___6~0#1); 5035#L1117-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 4582#L570 assume 1 == ~t8_pc~0; 4583#L571 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 4698#L581 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 4888#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 4694#L1125 assume !(0 != activate_threads_~tmp___7~0#1); 4176#L1125-2 havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 4177#L952 assume 1 == ~M_E~0;~M_E~0 := 2; 4117#L952-2 assume !(1 == ~T1_E~0); 4118#L957-1 assume !(1 == ~T2_E~0); 4894#L962-1 assume !(1 == ~T3_E~0); 4710#L967-1 assume !(1 == ~T4_E~0); 4711#L972-1 assume !(1 == ~T5_E~0); 4953#L977-1 assume !(1 == ~T6_E~0); 4954#L982-1 assume !(1 == ~T7_E~0); 4302#L987-1 assume 1 == ~T8_E~0;~T8_E~0 := 2; 4303#L992-1 assume !(1 == ~E_M~0); 4310#L997-1 assume !(1 == ~E_1~0); 4670#L1002-1 assume !(1 == ~E_2~0); 4655#L1007-1 assume !(1 == ~E_3~0); 4053#L1012-1 assume !(1 == ~E_4~0); 4054#L1017-1 assume !(1 == ~E_5~0); 4658#L1022-1 assume !(1 == ~E_6~0); 4659#L1027-1 assume 1 == ~E_7~0;~E_7~0 := 2; 4684#L1032-1 assume !(1 == ~E_8~0); 4815#L1037-1 assume { :end_inline_reset_delta_events } true; 4816#L1303-2 [2023-11-12 02:34:17,387 INFO L750 eck$LassoCheckResult]: Loop: 4816#L1303-2 assume !false; 4890#L1304 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 4557#L829-1 assume !false; 4853#L708 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 4443#L650 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 4378#L697 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 4521#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 4522#L712 assume !(0 != eval_~tmp~0#1); 4783#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 4692#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 4693#L854-3 assume !(0 == ~M_E~0); 4784#L854-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 4785#L859-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 5033#L864-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 5007#L869-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 4600#L874-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 4601#L879-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 4671#L884-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 4649#L889-3 assume !(0 == ~T8_E~0); 4272#L894-3 assume 0 == ~E_M~0;~E_M~0 := 1; 4273#L899-3 assume 0 == ~E_1~0;~E_1~0 := 1; 4306#L904-3 assume 0 == ~E_2~0;~E_2~0 := 1; 4307#L909-3 assume 0 == ~E_3~0;~E_3~0 := 1; 4251#L914-3 assume 0 == ~E_4~0;~E_4~0 := 1; 4252#L919-3 assume 0 == ~E_5~0;~E_5~0 := 1; 4295#L924-3 assume 0 == ~E_6~0;~E_6~0 := 1; 4859#L929-3 assume !(0 == ~E_7~0); 4770#L934-3 assume 0 == ~E_8~0;~E_8~0 := 1; 4771#L939-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 4878#L418-30 assume 1 == ~m_pc~0; 4135#L419-10 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 4136#L429-10 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 4512#is_master_triggered_returnLabel#11 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 4513#L1061-30 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 4340#L1061-32 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 4341#L437-30 assume 1 == ~t1_pc~0; 4464#L438-10 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 4690#L448-10 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 4691#is_transmit1_triggered_returnLabel#11 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 4728#L1069-30 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 5024#L1069-32 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 4424#L456-30 assume !(1 == ~t2_pc~0); 4425#L456-32 is_transmit2_triggered_~__retres1~2#1 := 0; 4851#L467-10 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 4423#is_transmit2_triggered_returnLabel#11 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 4229#L1077-30 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 4230#L1077-32 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 4572#L475-30 assume 1 == ~t3_pc~0; 4946#L476-10 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 4100#L486-10 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 4708#is_transmit3_triggered_returnLabel#11 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 4709#L1085-30 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 4447#L1085-32 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 4448#L494-30 assume !(1 == ~t4_pc~0); 4256#L494-32 is_transmit4_triggered_~__retres1~4#1 := 0; 4039#L505-10 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 4040#is_transmit4_triggered_returnLabel#11 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 5012#L1093-30 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 4962#L1093-32 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 4963#L513-30 assume !(1 == ~t5_pc~0); 4577#L513-32 is_transmit5_triggered_~__retres1~5#1 := 0; 4578#L524-10 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 4647#is_transmit5_triggered_returnLabel#11 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 4804#L1101-30 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 4870#L1101-32 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 4590#L532-30 assume !(1 == ~t6_pc~0); 4592#L532-32 is_transmit6_triggered_~__retres1~6#1 := 0; 4180#L543-10 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 4181#is_transmit6_triggered_returnLabel#11 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 4205#L1109-30 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 4261#L1109-32 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 4262#L551-30 assume !(1 == ~t7_pc~0); 4314#L551-32 is_transmit7_triggered_~__retres1~7#1 := 0; 4380#L562-10 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 4860#is_transmit7_triggered_returnLabel#11 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 4055#L1117-30 assume !(0 != activate_threads_~tmp___6~0#1); 4056#L1117-32 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 4422#L570-30 assume 1 == ~t8_pc~0; 4931#L571-10 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 4311#L581-10 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 4312#is_transmit8_triggered_returnLabel#11 activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 4113#L1125-30 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 4114#L1125-32 havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 4493#L952-3 assume 1 == ~M_E~0;~M_E~0 := 2; 4537#L952-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 4988#L957-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 4989#L962-3 assume !(1 == ~T3_E~0); 4911#L967-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 4912#L972-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 4831#L977-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 4832#L982-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 5037#L987-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 4479#L992-3 assume 1 == ~E_M~0;~E_M~0 := 2; 4480#L997-3 assume 1 == ~E_1~0;~E_1~0 := 2; 4475#L1002-3 assume !(1 == ~E_2~0); 4476#L1007-3 assume 1 == ~E_3~0;~E_3~0 := 2; 4285#L1012-3 assume 1 == ~E_4~0;~E_4~0 := 2; 4286#L1017-3 assume 1 == ~E_5~0;~E_5~0 := 2; 4387#L1022-3 assume 1 == ~E_6~0;~E_6~0 := 2; 4623#L1027-3 assume 1 == ~E_7~0;~E_7~0 := 2; 4083#L1032-3 assume 1 == ~E_8~0;~E_8~0 := 2; 4084#L1037-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 4329#L650-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 4330#L697-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 4445#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret25#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret25#1;havoc start_simulation_#t~ret25#1; 4446#L1322 assume !(0 == start_simulation_~tmp~3#1); 4507#L1322-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret24#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 4170#L650-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 4171#L697-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 4087#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret24#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret24#1;havoc stop_simulation_#t~ret24#1; 4069#L1277 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 4070#L1284 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 4706#stop_simulation_returnLabel#1 start_simulation_#t~ret26#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret24#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret26#1;havoc start_simulation_#t~ret26#1; 4707#L1335 assume !(0 != start_simulation_~tmp___0~1#1); 4816#L1303-2 [2023-11-12 02:34:17,387 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-12 02:34:17,388 INFO L85 PathProgramCache]: Analyzing trace with hash -1134101512, now seen corresponding path program 1 times [2023-11-12 02:34:17,388 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-12 02:34:17,388 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2134471510] [2023-11-12 02:34:17,388 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-12 02:34:17,389 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-12 02:34:17,423 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-12 02:34:17,533 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-12 02:34:17,533 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-12 02:34:17,534 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2134471510] [2023-11-12 02:34:17,534 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2134471510] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-12 02:34:17,534 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-12 02:34:17,534 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-12 02:34:17,535 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1690125270] [2023-11-12 02:34:17,535 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-12 02:34:17,535 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-12 02:34:17,536 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-12 02:34:17,536 INFO L85 PathProgramCache]: Analyzing trace with hash 2036706080, now seen corresponding path program 1 times [2023-11-12 02:34:17,536 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-12 02:34:17,536 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [52923035] [2023-11-12 02:34:17,537 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-12 02:34:17,537 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-12 02:34:17,573 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-12 02:34:17,635 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-12 02:34:17,636 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-12 02:34:17,636 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [52923035] [2023-11-12 02:34:17,636 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [52923035] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-12 02:34:17,636 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-12 02:34:17,637 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-12 02:34:17,637 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [776396663] [2023-11-12 02:34:17,637 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-12 02:34:17,637 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-12 02:34:17,638 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-12 02:34:17,638 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-12 02:34:17,638 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-12 02:34:17,639 INFO L87 Difference]: Start difference. First operand 1002 states and 1489 transitions. cyclomatic complexity: 488 Second operand has 3 states, 3 states have (on average 35.333333333333336) internal successors, (106), 3 states have internal predecessors, (106), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-12 02:34:17,669 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-12 02:34:17,669 INFO L93 Difference]: Finished difference Result 1002 states and 1488 transitions. [2023-11-12 02:34:17,670 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1002 states and 1488 transitions. [2023-11-12 02:34:17,679 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 887 [2023-11-12 02:34:17,688 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1002 states to 1002 states and 1488 transitions. [2023-11-12 02:34:17,688 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1002 [2023-11-12 02:34:17,690 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1002 [2023-11-12 02:34:17,690 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1002 states and 1488 transitions. [2023-11-12 02:34:17,692 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-12 02:34:17,692 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1002 states and 1488 transitions. [2023-11-12 02:34:17,694 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1002 states and 1488 transitions. [2023-11-12 02:34:17,711 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1002 to 1002. [2023-11-12 02:34:17,714 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1002 states, 1002 states have (on average 1.4850299401197604) internal successors, (1488), 1001 states have internal predecessors, (1488), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-12 02:34:17,719 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1002 states to 1002 states and 1488 transitions. [2023-11-12 02:34:17,719 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1002 states and 1488 transitions. [2023-11-12 02:34:17,719 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-12 02:34:17,720 INFO L428 stractBuchiCegarLoop]: Abstraction has 1002 states and 1488 transitions. [2023-11-12 02:34:17,720 INFO L335 stractBuchiCegarLoop]: ======== Iteration 4 ============ [2023-11-12 02:34:17,721 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1002 states and 1488 transitions. [2023-11-12 02:34:17,728 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 887 [2023-11-12 02:34:17,728 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-12 02:34:17,728 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-12 02:34:17,731 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-12 02:34:17,731 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-12 02:34:17,731 INFO L748 eck$LassoCheckResult]: Stem: 6369#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~token~0 := 0;~local~0 := 0; 6370#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~10#1;havoc main_~__retres1~10#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; 6994#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret25#1, start_simulation_#t~ret26#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 6995#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 7033#L597 assume 1 == ~m_i~0;~m_st~0 := 0; 6788#L597-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 6789#L602-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 6386#L607-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 6387#L612-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 6319#L617-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 6320#L622-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 6582#L627-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 6554#L632-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 6555#L637-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 6838#L854 assume !(0 == ~M_E~0); 6645#L854-2 assume !(0 == ~T1_E~0); 6646#L859-1 assume !(0 == ~T2_E~0); 6199#L864-1 assume !(0 == ~T3_E~0); 6200#L869-1 assume !(0 == ~T4_E~0); 6310#L874-1 assume 0 == ~T5_E~0;~T5_E~0 := 1; 7019#L879-1 assume !(0 == ~T6_E~0); 6635#L884-1 assume !(0 == ~T7_E~0); 6062#L889-1 assume !(0 == ~T8_E~0); 6063#L894-1 assume !(0 == ~E_M~0); 6399#L899-1 assume !(0 == ~E_1~0); 6844#L904-1 assume !(0 == ~E_2~0); 6572#L909-1 assume !(0 == ~E_3~0); 6573#L914-1 assume 0 == ~E_4~0;~E_4~0 := 1; 6779#L919-1 assume !(0 == ~E_5~0); 6478#L924-1 assume !(0 == ~E_6~0); 6292#L929-1 assume !(0 == ~E_7~0); 6293#L934-1 assume !(0 == ~E_8~0); 6551#L939-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 6079#L418 assume !(1 == ~m_pc~0); 6054#L418-2 is_master_triggered_~__retres1~0#1 := 0; 6053#L429 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 6948#is_master_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 6934#L1061 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 6867#L1061-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 6868#L437 assume 1 == ~t1_pc~0; 7036#L438 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 6941#L448 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 6102#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 6103#L1069 assume !(0 != activate_threads_~tmp___0~0#1); 6428#L1069-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 6924#L456 assume !(1 == ~t2_pc~0); 6350#L456-2 is_transmit2_triggered_~__retres1~2#1 := 0; 6349#L467 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 6510#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 6511#L1077 assume !(0 != activate_threads_~tmp___1~0#1); 6683#L1077-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 6193#L475 assume 1 == ~t3_pc~0; 6194#L476 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 6257#L486 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 6070#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 6071#L1085 assume !(0 != activate_threads_~tmp___2~0#1); 6431#L1085-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 6432#L494 assume !(1 == ~t4_pc~0); 6472#L494-2 is_transmit4_triggered_~__retres1~4#1 := 0; 6473#L505 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 6209#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 6210#L1093 assume !(0 != activate_threads_~tmp___3~0#1); 6803#L1093-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 6252#L513 assume 1 == ~t5_pc~0; 6253#L514 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 6474#L524 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 6950#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 6206#L1101 assume !(0 != activate_threads_~tmp___4~0#1); 6207#L1101-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 6159#L532 assume !(1 == ~t6_pc~0); 6160#L532-2 is_transmit6_triggered_~__retres1~6#1 := 0; 6311#L543 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 6492#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 6493#L1109 assume !(0 != activate_threads_~tmp___5~0#1); 6403#L1109-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 6404#L551 assume 1 == ~t7_pc~0; 6961#L552 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 6805#L562 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 6806#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 7045#L1117 assume !(0 != activate_threads_~tmp___6~0#1); 7046#L1117-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 6593#L570 assume 1 == ~t8_pc~0; 6594#L571 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 6709#L581 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 6899#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 6705#L1125 assume !(0 != activate_threads_~tmp___7~0#1); 6187#L1125-2 havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 6188#L952 assume 1 == ~M_E~0;~M_E~0 := 2; 6128#L952-2 assume !(1 == ~T1_E~0); 6129#L957-1 assume !(1 == ~T2_E~0); 6905#L962-1 assume !(1 == ~T3_E~0); 6721#L967-1 assume !(1 == ~T4_E~0); 6722#L972-1 assume !(1 == ~T5_E~0); 6964#L977-1 assume !(1 == ~T6_E~0); 6965#L982-1 assume !(1 == ~T7_E~0); 6313#L987-1 assume 1 == ~T8_E~0;~T8_E~0 := 2; 6314#L992-1 assume !(1 == ~E_M~0); 6321#L997-1 assume !(1 == ~E_1~0); 6681#L1002-1 assume !(1 == ~E_2~0); 6666#L1007-1 assume !(1 == ~E_3~0); 6064#L1012-1 assume !(1 == ~E_4~0); 6065#L1017-1 assume !(1 == ~E_5~0); 6669#L1022-1 assume !(1 == ~E_6~0); 6670#L1027-1 assume 1 == ~E_7~0;~E_7~0 := 2; 6695#L1032-1 assume !(1 == ~E_8~0); 6826#L1037-1 assume { :end_inline_reset_delta_events } true; 6827#L1303-2 [2023-11-12 02:34:17,732 INFO L750 eck$LassoCheckResult]: Loop: 6827#L1303-2 assume !false; 6901#L1304 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 6568#L829-1 assume !false; 6864#L708 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 6454#L650 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 6389#L697 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 6532#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 6533#L712 assume !(0 != eval_~tmp~0#1); 6794#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 6703#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 6704#L854-3 assume !(0 == ~M_E~0); 6795#L854-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 6796#L859-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 7044#L864-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 7018#L869-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 6611#L874-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 6612#L879-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 6682#L884-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 6660#L889-3 assume !(0 == ~T8_E~0); 6283#L894-3 assume 0 == ~E_M~0;~E_M~0 := 1; 6284#L899-3 assume 0 == ~E_1~0;~E_1~0 := 1; 6317#L904-3 assume 0 == ~E_2~0;~E_2~0 := 1; 6318#L909-3 assume 0 == ~E_3~0;~E_3~0 := 1; 6262#L914-3 assume 0 == ~E_4~0;~E_4~0 := 1; 6263#L919-3 assume 0 == ~E_5~0;~E_5~0 := 1; 6306#L924-3 assume 0 == ~E_6~0;~E_6~0 := 1; 6870#L929-3 assume !(0 == ~E_7~0); 6781#L934-3 assume 0 == ~E_8~0;~E_8~0 := 1; 6782#L939-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 6889#L418-30 assume 1 == ~m_pc~0; 6146#L419-10 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 6147#L429-10 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 6523#is_master_triggered_returnLabel#11 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 6524#L1061-30 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 6351#L1061-32 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 6352#L437-30 assume 1 == ~t1_pc~0; 6475#L438-10 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 6701#L448-10 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 6702#is_transmit1_triggered_returnLabel#11 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 6739#L1069-30 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 7035#L1069-32 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 6435#L456-30 assume !(1 == ~t2_pc~0); 6436#L456-32 is_transmit2_triggered_~__retres1~2#1 := 0; 6862#L467-10 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 6434#is_transmit2_triggered_returnLabel#11 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 6240#L1077-30 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 6241#L1077-32 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 6583#L475-30 assume 1 == ~t3_pc~0; 6957#L476-10 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 6111#L486-10 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 6719#is_transmit3_triggered_returnLabel#11 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 6720#L1085-30 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 6458#L1085-32 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 6459#L494-30 assume 1 == ~t4_pc~0; 6449#L495-10 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 6050#L505-10 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 6051#is_transmit4_triggered_returnLabel#11 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 7023#L1093-30 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 6973#L1093-32 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 6974#L513-30 assume 1 == ~t5_pc~0; 7047#L514-10 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 6589#L524-10 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 6658#is_transmit5_triggered_returnLabel#11 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 6815#L1101-30 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 6881#L1101-32 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 6601#L532-30 assume 1 == ~t6_pc~0; 6602#L533-10 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 6191#L543-10 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 6192#is_transmit6_triggered_returnLabel#11 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 6216#L1109-30 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 6272#L1109-32 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 6273#L551-30 assume !(1 == ~t7_pc~0); 6325#L551-32 is_transmit7_triggered_~__retres1~7#1 := 0; 6391#L562-10 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 6871#is_transmit7_triggered_returnLabel#11 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 6066#L1117-30 assume !(0 != activate_threads_~tmp___6~0#1); 6067#L1117-32 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 6433#L570-30 assume !(1 == ~t8_pc~0); 6787#L570-32 is_transmit8_triggered_~__retres1~8#1 := 0; 6322#L581-10 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 6323#is_transmit8_triggered_returnLabel#11 activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 6124#L1125-30 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 6125#L1125-32 havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 6504#L952-3 assume 1 == ~M_E~0;~M_E~0 := 2; 6548#L952-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 6999#L957-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 7000#L962-3 assume !(1 == ~T3_E~0); 6922#L967-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 6923#L972-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 6842#L977-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 6843#L982-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 7048#L987-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 6490#L992-3 assume 1 == ~E_M~0;~E_M~0 := 2; 6491#L997-3 assume 1 == ~E_1~0;~E_1~0 := 2; 6486#L1002-3 assume !(1 == ~E_2~0); 6487#L1007-3 assume 1 == ~E_3~0;~E_3~0 := 2; 6296#L1012-3 assume 1 == ~E_4~0;~E_4~0 := 2; 6297#L1017-3 assume 1 == ~E_5~0;~E_5~0 := 2; 6398#L1022-3 assume 1 == ~E_6~0;~E_6~0 := 2; 6634#L1027-3 assume 1 == ~E_7~0;~E_7~0 := 2; 6094#L1032-3 assume 1 == ~E_8~0;~E_8~0 := 2; 6095#L1037-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 6340#L650-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 6341#L697-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 6456#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret25#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret25#1;havoc start_simulation_#t~ret25#1; 6457#L1322 assume !(0 == start_simulation_~tmp~3#1); 6518#L1322-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret24#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 6181#L650-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 6182#L697-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 6098#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret24#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret24#1;havoc stop_simulation_#t~ret24#1; 6080#L1277 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 6081#L1284 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 6717#stop_simulation_returnLabel#1 start_simulation_#t~ret26#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret24#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret26#1;havoc start_simulation_#t~ret26#1; 6718#L1335 assume !(0 != start_simulation_~tmp___0~1#1); 6827#L1303-2 [2023-11-12 02:34:17,732 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-12 02:34:17,733 INFO L85 PathProgramCache]: Analyzing trace with hash 2129824886, now seen corresponding path program 1 times [2023-11-12 02:34:17,733 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-12 02:34:17,733 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1055815520] [2023-11-12 02:34:17,733 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-12 02:34:17,733 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-12 02:34:17,761 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-12 02:34:17,825 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-12 02:34:17,825 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-12 02:34:17,825 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1055815520] [2023-11-12 02:34:17,826 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1055815520] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-12 02:34:17,826 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-12 02:34:17,826 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-12 02:34:17,826 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1222094639] [2023-11-12 02:34:17,826 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-12 02:34:17,827 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-12 02:34:17,827 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-12 02:34:17,827 INFO L85 PathProgramCache]: Analyzing trace with hash 1773359198, now seen corresponding path program 1 times [2023-11-12 02:34:17,828 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-12 02:34:17,828 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [751286231] [2023-11-12 02:34:17,828 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-12 02:34:17,828 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-12 02:34:17,862 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-12 02:34:17,936 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-12 02:34:17,936 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-12 02:34:17,937 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [751286231] [2023-11-12 02:34:17,937 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [751286231] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-12 02:34:17,937 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-12 02:34:17,937 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-12 02:34:17,937 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1332001049] [2023-11-12 02:34:17,938 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-12 02:34:17,940 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-12 02:34:17,940 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-12 02:34:17,941 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-12 02:34:17,941 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-12 02:34:17,941 INFO L87 Difference]: Start difference. First operand 1002 states and 1488 transitions. cyclomatic complexity: 487 Second operand has 3 states, 3 states have (on average 35.333333333333336) internal successors, (106), 3 states have internal predecessors, (106), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-12 02:34:17,975 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-12 02:34:17,975 INFO L93 Difference]: Finished difference Result 1002 states and 1487 transitions. [2023-11-12 02:34:17,976 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1002 states and 1487 transitions. [2023-11-12 02:34:17,985 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 887 [2023-11-12 02:34:17,995 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1002 states to 1002 states and 1487 transitions. [2023-11-12 02:34:17,995 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1002 [2023-11-12 02:34:17,996 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1002 [2023-11-12 02:34:17,996 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1002 states and 1487 transitions. [2023-11-12 02:34:17,998 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-12 02:34:17,998 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1002 states and 1487 transitions. [2023-11-12 02:34:18,033 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1002 states and 1487 transitions. [2023-11-12 02:34:18,055 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1002 to 1002. [2023-11-12 02:34:18,058 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1002 states, 1002 states have (on average 1.4840319361277445) internal successors, (1487), 1001 states have internal predecessors, (1487), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-12 02:34:18,064 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1002 states to 1002 states and 1487 transitions. [2023-11-12 02:34:18,064 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1002 states and 1487 transitions. [2023-11-12 02:34:18,064 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-12 02:34:18,067 INFO L428 stractBuchiCegarLoop]: Abstraction has 1002 states and 1487 transitions. [2023-11-12 02:34:18,071 INFO L335 stractBuchiCegarLoop]: ======== Iteration 5 ============ [2023-11-12 02:34:18,072 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1002 states and 1487 transitions. [2023-11-12 02:34:18,080 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 887 [2023-11-12 02:34:18,080 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-12 02:34:18,080 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-12 02:34:18,083 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-12 02:34:18,083 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-12 02:34:18,084 INFO L748 eck$LassoCheckResult]: Stem: 8380#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~token~0 := 0;~local~0 := 0; 8381#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~10#1;havoc main_~__retres1~10#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; 9005#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret25#1, start_simulation_#t~ret26#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 9006#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 9044#L597 assume 1 == ~m_i~0;~m_st~0 := 0; 8799#L597-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 8800#L602-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 8397#L607-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 8398#L612-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 8330#L617-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 8331#L622-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 8593#L627-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 8565#L632-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 8566#L637-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 8849#L854 assume !(0 == ~M_E~0); 8656#L854-2 assume !(0 == ~T1_E~0); 8657#L859-1 assume !(0 == ~T2_E~0); 8210#L864-1 assume !(0 == ~T3_E~0); 8211#L869-1 assume !(0 == ~T4_E~0); 8321#L874-1 assume 0 == ~T5_E~0;~T5_E~0 := 1; 9030#L879-1 assume !(0 == ~T6_E~0); 8646#L884-1 assume !(0 == ~T7_E~0); 8073#L889-1 assume !(0 == ~T8_E~0); 8074#L894-1 assume !(0 == ~E_M~0); 8410#L899-1 assume !(0 == ~E_1~0); 8855#L904-1 assume !(0 == ~E_2~0); 8583#L909-1 assume !(0 == ~E_3~0); 8584#L914-1 assume 0 == ~E_4~0;~E_4~0 := 1; 8790#L919-1 assume !(0 == ~E_5~0); 8489#L924-1 assume !(0 == ~E_6~0); 8303#L929-1 assume !(0 == ~E_7~0); 8304#L934-1 assume !(0 == ~E_8~0); 8562#L939-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 8090#L418 assume !(1 == ~m_pc~0); 8065#L418-2 is_master_triggered_~__retres1~0#1 := 0; 8064#L429 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 8959#is_master_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 8945#L1061 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 8878#L1061-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 8879#L437 assume 1 == ~t1_pc~0; 9047#L438 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 8952#L448 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 8113#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 8114#L1069 assume !(0 != activate_threads_~tmp___0~0#1); 8439#L1069-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 8935#L456 assume !(1 == ~t2_pc~0); 8361#L456-2 is_transmit2_triggered_~__retres1~2#1 := 0; 8360#L467 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 8521#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 8522#L1077 assume !(0 != activate_threads_~tmp___1~0#1); 8694#L1077-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 8204#L475 assume 1 == ~t3_pc~0; 8205#L476 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 8268#L486 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 8081#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 8082#L1085 assume !(0 != activate_threads_~tmp___2~0#1); 8442#L1085-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 8443#L494 assume !(1 == ~t4_pc~0); 8483#L494-2 is_transmit4_triggered_~__retres1~4#1 := 0; 8484#L505 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 8220#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 8221#L1093 assume !(0 != activate_threads_~tmp___3~0#1); 8814#L1093-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 8263#L513 assume 1 == ~t5_pc~0; 8264#L514 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 8485#L524 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 8961#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 8217#L1101 assume !(0 != activate_threads_~tmp___4~0#1); 8218#L1101-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 8170#L532 assume !(1 == ~t6_pc~0); 8171#L532-2 is_transmit6_triggered_~__retres1~6#1 := 0; 8322#L543 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 8503#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 8504#L1109 assume !(0 != activate_threads_~tmp___5~0#1); 8414#L1109-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 8415#L551 assume 1 == ~t7_pc~0; 8972#L552 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 8816#L562 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 8817#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 9056#L1117 assume !(0 != activate_threads_~tmp___6~0#1); 9057#L1117-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 8604#L570 assume 1 == ~t8_pc~0; 8605#L571 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 8720#L581 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 8910#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 8716#L1125 assume !(0 != activate_threads_~tmp___7~0#1); 8198#L1125-2 havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 8199#L952 assume 1 == ~M_E~0;~M_E~0 := 2; 8139#L952-2 assume !(1 == ~T1_E~0); 8140#L957-1 assume !(1 == ~T2_E~0); 8916#L962-1 assume !(1 == ~T3_E~0); 8732#L967-1 assume !(1 == ~T4_E~0); 8733#L972-1 assume !(1 == ~T5_E~0); 8975#L977-1 assume !(1 == ~T6_E~0); 8976#L982-1 assume !(1 == ~T7_E~0); 8324#L987-1 assume 1 == ~T8_E~0;~T8_E~0 := 2; 8325#L992-1 assume !(1 == ~E_M~0); 8332#L997-1 assume !(1 == ~E_1~0); 8692#L1002-1 assume !(1 == ~E_2~0); 8677#L1007-1 assume !(1 == ~E_3~0); 8075#L1012-1 assume !(1 == ~E_4~0); 8076#L1017-1 assume !(1 == ~E_5~0); 8680#L1022-1 assume !(1 == ~E_6~0); 8681#L1027-1 assume 1 == ~E_7~0;~E_7~0 := 2; 8706#L1032-1 assume !(1 == ~E_8~0); 8837#L1037-1 assume { :end_inline_reset_delta_events } true; 8838#L1303-2 [2023-11-12 02:34:18,084 INFO L750 eck$LassoCheckResult]: Loop: 8838#L1303-2 assume !false; 8912#L1304 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 8579#L829-1 assume !false; 8875#L708 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 8465#L650 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 8400#L697 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 8543#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 8544#L712 assume !(0 != eval_~tmp~0#1); 8805#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 8714#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 8715#L854-3 assume !(0 == ~M_E~0); 8806#L854-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 8807#L859-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 9055#L864-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 9029#L869-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 8622#L874-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 8623#L879-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 8693#L884-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 8671#L889-3 assume !(0 == ~T8_E~0); 8294#L894-3 assume 0 == ~E_M~0;~E_M~0 := 1; 8295#L899-3 assume 0 == ~E_1~0;~E_1~0 := 1; 8328#L904-3 assume 0 == ~E_2~0;~E_2~0 := 1; 8329#L909-3 assume 0 == ~E_3~0;~E_3~0 := 1; 8273#L914-3 assume 0 == ~E_4~0;~E_4~0 := 1; 8274#L919-3 assume 0 == ~E_5~0;~E_5~0 := 1; 8317#L924-3 assume 0 == ~E_6~0;~E_6~0 := 1; 8881#L929-3 assume !(0 == ~E_7~0); 8792#L934-3 assume 0 == ~E_8~0;~E_8~0 := 1; 8793#L939-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 8900#L418-30 assume 1 == ~m_pc~0; 8157#L419-10 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 8158#L429-10 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 8534#is_master_triggered_returnLabel#11 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 8535#L1061-30 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 8362#L1061-32 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 8363#L437-30 assume 1 == ~t1_pc~0; 8486#L438-10 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 8712#L448-10 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 8713#is_transmit1_triggered_returnLabel#11 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 8750#L1069-30 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 9046#L1069-32 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 8446#L456-30 assume 1 == ~t2_pc~0; 8448#L457-10 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 8873#L467-10 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 8445#is_transmit2_triggered_returnLabel#11 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 8251#L1077-30 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 8252#L1077-32 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 8594#L475-30 assume 1 == ~t3_pc~0; 8968#L476-10 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 8122#L486-10 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 8730#is_transmit3_triggered_returnLabel#11 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 8731#L1085-30 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 8469#L1085-32 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 8470#L494-30 assume !(1 == ~t4_pc~0); 8278#L494-32 is_transmit4_triggered_~__retres1~4#1 := 0; 8061#L505-10 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 8062#is_transmit4_triggered_returnLabel#11 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 9034#L1093-30 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 8984#L1093-32 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 8985#L513-30 assume 1 == ~t5_pc~0; 9058#L514-10 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 8600#L524-10 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 8669#is_transmit5_triggered_returnLabel#11 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 8826#L1101-30 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 8892#L1101-32 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 8612#L532-30 assume 1 == ~t6_pc~0; 8613#L533-10 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 8202#L543-10 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 8203#is_transmit6_triggered_returnLabel#11 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 8227#L1109-30 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 8283#L1109-32 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 8284#L551-30 assume !(1 == ~t7_pc~0); 8336#L551-32 is_transmit7_triggered_~__retres1~7#1 := 0; 8402#L562-10 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 8882#is_transmit7_triggered_returnLabel#11 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 8077#L1117-30 assume !(0 != activate_threads_~tmp___6~0#1); 8078#L1117-32 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 8444#L570-30 assume 1 == ~t8_pc~0; 8953#L571-10 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 8333#L581-10 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 8334#is_transmit8_triggered_returnLabel#11 activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 8135#L1125-30 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 8136#L1125-32 havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 8515#L952-3 assume 1 == ~M_E~0;~M_E~0 := 2; 8559#L952-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 9010#L957-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 9011#L962-3 assume !(1 == ~T3_E~0); 8933#L967-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 8934#L972-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 8853#L977-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 8854#L982-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 9059#L987-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 8501#L992-3 assume 1 == ~E_M~0;~E_M~0 := 2; 8502#L997-3 assume 1 == ~E_1~0;~E_1~0 := 2; 8497#L1002-3 assume !(1 == ~E_2~0); 8498#L1007-3 assume 1 == ~E_3~0;~E_3~0 := 2; 8307#L1012-3 assume 1 == ~E_4~0;~E_4~0 := 2; 8308#L1017-3 assume 1 == ~E_5~0;~E_5~0 := 2; 8409#L1022-3 assume 1 == ~E_6~0;~E_6~0 := 2; 8645#L1027-3 assume 1 == ~E_7~0;~E_7~0 := 2; 8105#L1032-3 assume 1 == ~E_8~0;~E_8~0 := 2; 8106#L1037-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 8351#L650-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 8352#L697-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 8467#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret25#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret25#1;havoc start_simulation_#t~ret25#1; 8468#L1322 assume !(0 == start_simulation_~tmp~3#1); 8529#L1322-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret24#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 8192#L650-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 8193#L697-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 8109#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret24#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret24#1;havoc stop_simulation_#t~ret24#1; 8091#L1277 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 8092#L1284 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 8728#stop_simulation_returnLabel#1 start_simulation_#t~ret26#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret24#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret26#1;havoc start_simulation_#t~ret26#1; 8729#L1335 assume !(0 != start_simulation_~tmp___0~1#1); 8838#L1303-2 [2023-11-12 02:34:18,087 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-12 02:34:18,087 INFO L85 PathProgramCache]: Analyzing trace with hash -258739144, now seen corresponding path program 1 times [2023-11-12 02:34:18,087 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-12 02:34:18,087 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1304631037] [2023-11-12 02:34:18,088 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-12 02:34:18,088 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-12 02:34:18,108 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-12 02:34:18,157 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-12 02:34:18,157 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-12 02:34:18,158 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1304631037] [2023-11-12 02:34:18,158 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1304631037] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-12 02:34:18,159 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-12 02:34:18,159 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-12 02:34:18,159 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1193368190] [2023-11-12 02:34:18,159 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-12 02:34:18,160 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-12 02:34:18,161 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-12 02:34:18,161 INFO L85 PathProgramCache]: Analyzing trace with hash -455356643, now seen corresponding path program 1 times [2023-11-12 02:34:18,161 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-12 02:34:18,161 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [642420749] [2023-11-12 02:34:18,162 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-12 02:34:18,162 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-12 02:34:18,185 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-12 02:34:18,260 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-12 02:34:18,261 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-12 02:34:18,261 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [642420749] [2023-11-12 02:34:18,261 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [642420749] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-12 02:34:18,261 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-12 02:34:18,262 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-12 02:34:18,262 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [596758275] [2023-11-12 02:34:18,262 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-12 02:34:18,262 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-12 02:34:18,263 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-12 02:34:18,263 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-12 02:34:18,263 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-12 02:34:18,264 INFO L87 Difference]: Start difference. First operand 1002 states and 1487 transitions. cyclomatic complexity: 486 Second operand has 3 states, 3 states have (on average 35.333333333333336) internal successors, (106), 3 states have internal predecessors, (106), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-12 02:34:18,298 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-12 02:34:18,298 INFO L93 Difference]: Finished difference Result 1002 states and 1486 transitions. [2023-11-12 02:34:18,299 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1002 states and 1486 transitions. [2023-11-12 02:34:18,307 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 887 [2023-11-12 02:34:18,316 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1002 states to 1002 states and 1486 transitions. [2023-11-12 02:34:18,317 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1002 [2023-11-12 02:34:18,318 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1002 [2023-11-12 02:34:18,318 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1002 states and 1486 transitions. [2023-11-12 02:34:18,320 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-12 02:34:18,320 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1002 states and 1486 transitions. [2023-11-12 02:34:18,322 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1002 states and 1486 transitions. [2023-11-12 02:34:18,338 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1002 to 1002. [2023-11-12 02:34:18,341 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1002 states, 1002 states have (on average 1.4830339321357286) internal successors, (1486), 1001 states have internal predecessors, (1486), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-12 02:34:18,345 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1002 states to 1002 states and 1486 transitions. [2023-11-12 02:34:18,346 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1002 states and 1486 transitions. [2023-11-12 02:34:18,346 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-12 02:34:18,349 INFO L428 stractBuchiCegarLoop]: Abstraction has 1002 states and 1486 transitions. [2023-11-12 02:34:18,349 INFO L335 stractBuchiCegarLoop]: ======== Iteration 6 ============ [2023-11-12 02:34:18,349 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1002 states and 1486 transitions. [2023-11-12 02:34:18,356 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 887 [2023-11-12 02:34:18,356 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-12 02:34:18,356 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-12 02:34:18,358 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-12 02:34:18,358 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-12 02:34:18,358 INFO L748 eck$LassoCheckResult]: Stem: 10391#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~token~0 := 0;~local~0 := 0; 10392#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~10#1;havoc main_~__retres1~10#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; 11016#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret25#1, start_simulation_#t~ret26#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 11017#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 11055#L597 assume 1 == ~m_i~0;~m_st~0 := 0; 10810#L597-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 10811#L602-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 10408#L607-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 10409#L612-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 10341#L617-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 10342#L622-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 10604#L627-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 10576#L632-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 10577#L637-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 10860#L854 assume !(0 == ~M_E~0); 10667#L854-2 assume !(0 == ~T1_E~0); 10668#L859-1 assume !(0 == ~T2_E~0); 10221#L864-1 assume !(0 == ~T3_E~0); 10222#L869-1 assume !(0 == ~T4_E~0); 10332#L874-1 assume 0 == ~T5_E~0;~T5_E~0 := 1; 11041#L879-1 assume !(0 == ~T6_E~0); 10657#L884-1 assume !(0 == ~T7_E~0); 10084#L889-1 assume !(0 == ~T8_E~0); 10085#L894-1 assume !(0 == ~E_M~0); 10421#L899-1 assume !(0 == ~E_1~0); 10866#L904-1 assume !(0 == ~E_2~0); 10594#L909-1 assume !(0 == ~E_3~0); 10595#L914-1 assume 0 == ~E_4~0;~E_4~0 := 1; 10801#L919-1 assume !(0 == ~E_5~0); 10500#L924-1 assume !(0 == ~E_6~0); 10314#L929-1 assume !(0 == ~E_7~0); 10315#L934-1 assume !(0 == ~E_8~0); 10573#L939-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 10101#L418 assume !(1 == ~m_pc~0); 10076#L418-2 is_master_triggered_~__retres1~0#1 := 0; 10075#L429 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 10970#is_master_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 10956#L1061 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 10889#L1061-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 10890#L437 assume 1 == ~t1_pc~0; 11058#L438 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 10963#L448 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 10124#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 10125#L1069 assume !(0 != activate_threads_~tmp___0~0#1); 10450#L1069-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 10946#L456 assume !(1 == ~t2_pc~0); 10372#L456-2 is_transmit2_triggered_~__retres1~2#1 := 0; 10371#L467 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 10532#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 10533#L1077 assume !(0 != activate_threads_~tmp___1~0#1); 10705#L1077-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 10215#L475 assume 1 == ~t3_pc~0; 10216#L476 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 10279#L486 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 10092#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 10093#L1085 assume !(0 != activate_threads_~tmp___2~0#1); 10453#L1085-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 10454#L494 assume !(1 == ~t4_pc~0); 10494#L494-2 is_transmit4_triggered_~__retres1~4#1 := 0; 10495#L505 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 10231#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 10232#L1093 assume !(0 != activate_threads_~tmp___3~0#1); 10825#L1093-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 10274#L513 assume 1 == ~t5_pc~0; 10275#L514 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 10496#L524 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 10972#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 10228#L1101 assume !(0 != activate_threads_~tmp___4~0#1); 10229#L1101-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 10181#L532 assume !(1 == ~t6_pc~0); 10182#L532-2 is_transmit6_triggered_~__retres1~6#1 := 0; 10333#L543 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 10514#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 10515#L1109 assume !(0 != activate_threads_~tmp___5~0#1); 10425#L1109-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 10426#L551 assume 1 == ~t7_pc~0; 10983#L552 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 10827#L562 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 10828#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 11067#L1117 assume !(0 != activate_threads_~tmp___6~0#1); 11068#L1117-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 10615#L570 assume 1 == ~t8_pc~0; 10616#L571 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 10731#L581 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 10921#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 10727#L1125 assume !(0 != activate_threads_~tmp___7~0#1); 10209#L1125-2 havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 10210#L952 assume 1 == ~M_E~0;~M_E~0 := 2; 10150#L952-2 assume !(1 == ~T1_E~0); 10151#L957-1 assume !(1 == ~T2_E~0); 10927#L962-1 assume !(1 == ~T3_E~0); 10743#L967-1 assume !(1 == ~T4_E~0); 10744#L972-1 assume !(1 == ~T5_E~0); 10986#L977-1 assume !(1 == ~T6_E~0); 10987#L982-1 assume !(1 == ~T7_E~0); 10335#L987-1 assume 1 == ~T8_E~0;~T8_E~0 := 2; 10336#L992-1 assume !(1 == ~E_M~0); 10343#L997-1 assume !(1 == ~E_1~0); 10703#L1002-1 assume !(1 == ~E_2~0); 10688#L1007-1 assume !(1 == ~E_3~0); 10086#L1012-1 assume !(1 == ~E_4~0); 10087#L1017-1 assume !(1 == ~E_5~0); 10691#L1022-1 assume !(1 == ~E_6~0); 10692#L1027-1 assume 1 == ~E_7~0;~E_7~0 := 2; 10717#L1032-1 assume !(1 == ~E_8~0); 10848#L1037-1 assume { :end_inline_reset_delta_events } true; 10849#L1303-2 [2023-11-12 02:34:18,359 INFO L750 eck$LassoCheckResult]: Loop: 10849#L1303-2 assume !false; 10923#L1304 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 10590#L829-1 assume !false; 10886#L708 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 10476#L650 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 10411#L697 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 10554#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 10555#L712 assume !(0 != eval_~tmp~0#1); 10816#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 10725#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 10726#L854-3 assume !(0 == ~M_E~0); 10817#L854-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 10818#L859-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 11066#L864-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 11040#L869-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 10633#L874-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 10634#L879-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 10704#L884-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 10682#L889-3 assume !(0 == ~T8_E~0); 10305#L894-3 assume 0 == ~E_M~0;~E_M~0 := 1; 10306#L899-3 assume 0 == ~E_1~0;~E_1~0 := 1; 10339#L904-3 assume 0 == ~E_2~0;~E_2~0 := 1; 10340#L909-3 assume 0 == ~E_3~0;~E_3~0 := 1; 10284#L914-3 assume 0 == ~E_4~0;~E_4~0 := 1; 10285#L919-3 assume 0 == ~E_5~0;~E_5~0 := 1; 10328#L924-3 assume 0 == ~E_6~0;~E_6~0 := 1; 10892#L929-3 assume !(0 == ~E_7~0); 10803#L934-3 assume 0 == ~E_8~0;~E_8~0 := 1; 10804#L939-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 10911#L418-30 assume 1 == ~m_pc~0; 10168#L419-10 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 10169#L429-10 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 10545#is_master_triggered_returnLabel#11 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 10546#L1061-30 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 10373#L1061-32 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 10374#L437-30 assume 1 == ~t1_pc~0; 10497#L438-10 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 10723#L448-10 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 10724#is_transmit1_triggered_returnLabel#11 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 10761#L1069-30 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 11057#L1069-32 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 10457#L456-30 assume !(1 == ~t2_pc~0); 10458#L456-32 is_transmit2_triggered_~__retres1~2#1 := 0; 10884#L467-10 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 10456#is_transmit2_triggered_returnLabel#11 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 10262#L1077-30 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 10263#L1077-32 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 10605#L475-30 assume 1 == ~t3_pc~0; 10979#L476-10 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 10133#L486-10 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 10741#is_transmit3_triggered_returnLabel#11 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 10742#L1085-30 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 10480#L1085-32 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 10481#L494-30 assume !(1 == ~t4_pc~0); 10289#L494-32 is_transmit4_triggered_~__retres1~4#1 := 0; 10072#L505-10 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 10073#is_transmit4_triggered_returnLabel#11 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 11045#L1093-30 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 10995#L1093-32 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 10996#L513-30 assume !(1 == ~t5_pc~0); 10610#L513-32 is_transmit5_triggered_~__retres1~5#1 := 0; 10611#L524-10 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 10680#is_transmit5_triggered_returnLabel#11 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 10837#L1101-30 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 10903#L1101-32 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 10623#L532-30 assume 1 == ~t6_pc~0; 10624#L533-10 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 10213#L543-10 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 10214#is_transmit6_triggered_returnLabel#11 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 10238#L1109-30 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 10294#L1109-32 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 10295#L551-30 assume !(1 == ~t7_pc~0); 10347#L551-32 is_transmit7_triggered_~__retres1~7#1 := 0; 10413#L562-10 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 10893#is_transmit7_triggered_returnLabel#11 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 10088#L1117-30 assume !(0 != activate_threads_~tmp___6~0#1); 10089#L1117-32 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 10455#L570-30 assume 1 == ~t8_pc~0; 10964#L571-10 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 10344#L581-10 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 10345#is_transmit8_triggered_returnLabel#11 activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 10146#L1125-30 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 10147#L1125-32 havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 10526#L952-3 assume 1 == ~M_E~0;~M_E~0 := 2; 10570#L952-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 11021#L957-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 11022#L962-3 assume !(1 == ~T3_E~0); 10944#L967-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 10945#L972-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 10864#L977-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 10865#L982-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 11070#L987-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 10512#L992-3 assume 1 == ~E_M~0;~E_M~0 := 2; 10513#L997-3 assume 1 == ~E_1~0;~E_1~0 := 2; 10508#L1002-3 assume !(1 == ~E_2~0); 10509#L1007-3 assume 1 == ~E_3~0;~E_3~0 := 2; 10318#L1012-3 assume 1 == ~E_4~0;~E_4~0 := 2; 10319#L1017-3 assume 1 == ~E_5~0;~E_5~0 := 2; 10420#L1022-3 assume 1 == ~E_6~0;~E_6~0 := 2; 10656#L1027-3 assume 1 == ~E_7~0;~E_7~0 := 2; 10116#L1032-3 assume 1 == ~E_8~0;~E_8~0 := 2; 10117#L1037-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 10362#L650-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 10363#L697-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 10478#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret25#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret25#1;havoc start_simulation_#t~ret25#1; 10479#L1322 assume !(0 == start_simulation_~tmp~3#1); 10540#L1322-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret24#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 10203#L650-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 10204#L697-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 10120#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret24#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret24#1;havoc stop_simulation_#t~ret24#1; 10102#L1277 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 10103#L1284 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 10739#stop_simulation_returnLabel#1 start_simulation_#t~ret26#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret24#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret26#1;havoc start_simulation_#t~ret26#1; 10740#L1335 assume !(0 != start_simulation_~tmp___0~1#1); 10849#L1303-2 [2023-11-12 02:34:18,360 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-12 02:34:18,360 INFO L85 PathProgramCache]: Analyzing trace with hash -1859810250, now seen corresponding path program 1 times [2023-11-12 02:34:18,361 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-12 02:34:18,361 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [321940838] [2023-11-12 02:34:18,361 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-12 02:34:18,362 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-12 02:34:18,375 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-12 02:34:18,409 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-12 02:34:18,409 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-12 02:34:18,409 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [321940838] [2023-11-12 02:34:18,410 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [321940838] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-12 02:34:18,410 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-12 02:34:18,410 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-12 02:34:18,411 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1778454818] [2023-11-12 02:34:18,411 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-12 02:34:18,411 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-12 02:34:18,412 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-12 02:34:18,412 INFO L85 PathProgramCache]: Analyzing trace with hash 568502751, now seen corresponding path program 1 times [2023-11-12 02:34:18,413 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-12 02:34:18,417 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [651093450] [2023-11-12 02:34:18,418 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-12 02:34:18,418 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-12 02:34:18,439 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-12 02:34:18,479 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-12 02:34:18,480 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-12 02:34:18,480 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [651093450] [2023-11-12 02:34:18,481 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [651093450] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-12 02:34:18,481 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-12 02:34:18,482 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-12 02:34:18,482 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1784293408] [2023-11-12 02:34:18,482 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-12 02:34:18,483 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-12 02:34:18,483 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-12 02:34:18,483 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-12 02:34:18,484 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-12 02:34:18,484 INFO L87 Difference]: Start difference. First operand 1002 states and 1486 transitions. cyclomatic complexity: 485 Second operand has 3 states, 3 states have (on average 35.333333333333336) internal successors, (106), 3 states have internal predecessors, (106), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-12 02:34:18,545 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-12 02:34:18,545 INFO L93 Difference]: Finished difference Result 1002 states and 1485 transitions. [2023-11-12 02:34:18,545 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1002 states and 1485 transitions. [2023-11-12 02:34:18,553 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 887 [2023-11-12 02:34:18,562 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1002 states to 1002 states and 1485 transitions. [2023-11-12 02:34:18,562 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1002 [2023-11-12 02:34:18,563 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1002 [2023-11-12 02:34:18,563 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1002 states and 1485 transitions. [2023-11-12 02:34:18,565 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-12 02:34:18,565 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1002 states and 1485 transitions. [2023-11-12 02:34:18,567 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1002 states and 1485 transitions. [2023-11-12 02:34:18,583 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1002 to 1002. [2023-11-12 02:34:18,586 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1002 states, 1002 states have (on average 1.4820359281437125) internal successors, (1485), 1001 states have internal predecessors, (1485), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-12 02:34:18,590 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1002 states to 1002 states and 1485 transitions. [2023-11-12 02:34:18,591 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1002 states and 1485 transitions. [2023-11-12 02:34:18,591 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-12 02:34:18,593 INFO L428 stractBuchiCegarLoop]: Abstraction has 1002 states and 1485 transitions. [2023-11-12 02:34:18,593 INFO L335 stractBuchiCegarLoop]: ======== Iteration 7 ============ [2023-11-12 02:34:18,593 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1002 states and 1485 transitions. [2023-11-12 02:34:18,599 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 887 [2023-11-12 02:34:18,600 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-12 02:34:18,600 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-12 02:34:18,602 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-12 02:34:18,602 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-12 02:34:18,602 INFO L748 eck$LassoCheckResult]: Stem: 12402#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~token~0 := 0;~local~0 := 0; 12403#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~10#1;havoc main_~__retres1~10#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; 13027#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret25#1, start_simulation_#t~ret26#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 13028#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 13066#L597 assume 1 == ~m_i~0;~m_st~0 := 0; 12821#L597-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 12822#L602-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 12419#L607-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 12420#L612-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 12352#L617-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 12353#L622-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 12615#L627-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 12587#L632-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 12588#L637-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 12871#L854 assume !(0 == ~M_E~0); 12678#L854-2 assume !(0 == ~T1_E~0); 12679#L859-1 assume !(0 == ~T2_E~0); 12232#L864-1 assume !(0 == ~T3_E~0); 12233#L869-1 assume !(0 == ~T4_E~0); 12343#L874-1 assume 0 == ~T5_E~0;~T5_E~0 := 1; 13052#L879-1 assume !(0 == ~T6_E~0); 12668#L884-1 assume !(0 == ~T7_E~0); 12095#L889-1 assume !(0 == ~T8_E~0); 12096#L894-1 assume !(0 == ~E_M~0); 12432#L899-1 assume !(0 == ~E_1~0); 12877#L904-1 assume !(0 == ~E_2~0); 12605#L909-1 assume !(0 == ~E_3~0); 12606#L914-1 assume 0 == ~E_4~0;~E_4~0 := 1; 12812#L919-1 assume !(0 == ~E_5~0); 12511#L924-1 assume !(0 == ~E_6~0); 12325#L929-1 assume !(0 == ~E_7~0); 12326#L934-1 assume !(0 == ~E_8~0); 12584#L939-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 12112#L418 assume !(1 == ~m_pc~0); 12087#L418-2 is_master_triggered_~__retres1~0#1 := 0; 12086#L429 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 12981#is_master_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 12967#L1061 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 12900#L1061-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 12901#L437 assume 1 == ~t1_pc~0; 13069#L438 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 12974#L448 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 12135#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 12136#L1069 assume !(0 != activate_threads_~tmp___0~0#1); 12461#L1069-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 12957#L456 assume !(1 == ~t2_pc~0); 12383#L456-2 is_transmit2_triggered_~__retres1~2#1 := 0; 12382#L467 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 12543#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 12544#L1077 assume !(0 != activate_threads_~tmp___1~0#1); 12716#L1077-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 12226#L475 assume 1 == ~t3_pc~0; 12227#L476 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 12290#L486 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 12103#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 12104#L1085 assume !(0 != activate_threads_~tmp___2~0#1); 12464#L1085-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 12465#L494 assume !(1 == ~t4_pc~0); 12505#L494-2 is_transmit4_triggered_~__retres1~4#1 := 0; 12506#L505 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 12242#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 12243#L1093 assume !(0 != activate_threads_~tmp___3~0#1); 12836#L1093-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 12285#L513 assume 1 == ~t5_pc~0; 12286#L514 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 12507#L524 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 12983#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 12239#L1101 assume !(0 != activate_threads_~tmp___4~0#1); 12240#L1101-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 12192#L532 assume !(1 == ~t6_pc~0); 12193#L532-2 is_transmit6_triggered_~__retres1~6#1 := 0; 12344#L543 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 12525#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 12526#L1109 assume !(0 != activate_threads_~tmp___5~0#1); 12436#L1109-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 12437#L551 assume 1 == ~t7_pc~0; 12994#L552 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 12838#L562 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 12839#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 13078#L1117 assume !(0 != activate_threads_~tmp___6~0#1); 13079#L1117-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 12626#L570 assume 1 == ~t8_pc~0; 12627#L571 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 12742#L581 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 12932#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 12738#L1125 assume !(0 != activate_threads_~tmp___7~0#1); 12220#L1125-2 havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 12221#L952 assume 1 == ~M_E~0;~M_E~0 := 2; 12161#L952-2 assume !(1 == ~T1_E~0); 12162#L957-1 assume !(1 == ~T2_E~0); 12938#L962-1 assume !(1 == ~T3_E~0); 12754#L967-1 assume !(1 == ~T4_E~0); 12755#L972-1 assume !(1 == ~T5_E~0); 12997#L977-1 assume !(1 == ~T6_E~0); 12998#L982-1 assume !(1 == ~T7_E~0); 12346#L987-1 assume 1 == ~T8_E~0;~T8_E~0 := 2; 12347#L992-1 assume !(1 == ~E_M~0); 12354#L997-1 assume !(1 == ~E_1~0); 12714#L1002-1 assume !(1 == ~E_2~0); 12699#L1007-1 assume !(1 == ~E_3~0); 12097#L1012-1 assume !(1 == ~E_4~0); 12098#L1017-1 assume !(1 == ~E_5~0); 12702#L1022-1 assume !(1 == ~E_6~0); 12703#L1027-1 assume 1 == ~E_7~0;~E_7~0 := 2; 12728#L1032-1 assume !(1 == ~E_8~0); 12859#L1037-1 assume { :end_inline_reset_delta_events } true; 12860#L1303-2 [2023-11-12 02:34:18,603 INFO L750 eck$LassoCheckResult]: Loop: 12860#L1303-2 assume !false; 12934#L1304 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 12601#L829-1 assume !false; 12897#L708 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 12487#L650 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 12422#L697 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 12565#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 12566#L712 assume !(0 != eval_~tmp~0#1); 12827#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 12736#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 12737#L854-3 assume !(0 == ~M_E~0); 12828#L854-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 12829#L859-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 13077#L864-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 13051#L869-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 12644#L874-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 12645#L879-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 12715#L884-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 12693#L889-3 assume !(0 == ~T8_E~0); 12316#L894-3 assume 0 == ~E_M~0;~E_M~0 := 1; 12317#L899-3 assume 0 == ~E_1~0;~E_1~0 := 1; 12350#L904-3 assume 0 == ~E_2~0;~E_2~0 := 1; 12351#L909-3 assume 0 == ~E_3~0;~E_3~0 := 1; 12295#L914-3 assume 0 == ~E_4~0;~E_4~0 := 1; 12296#L919-3 assume 0 == ~E_5~0;~E_5~0 := 1; 12339#L924-3 assume 0 == ~E_6~0;~E_6~0 := 1; 12903#L929-3 assume !(0 == ~E_7~0); 12814#L934-3 assume 0 == ~E_8~0;~E_8~0 := 1; 12815#L939-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 12922#L418-30 assume 1 == ~m_pc~0; 12179#L419-10 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 12180#L429-10 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 12556#is_master_triggered_returnLabel#11 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 12557#L1061-30 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 12384#L1061-32 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 12385#L437-30 assume 1 == ~t1_pc~0; 12508#L438-10 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 12734#L448-10 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 12735#is_transmit1_triggered_returnLabel#11 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 12772#L1069-30 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 13068#L1069-32 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 12468#L456-30 assume !(1 == ~t2_pc~0); 12469#L456-32 is_transmit2_triggered_~__retres1~2#1 := 0; 12895#L467-10 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 12467#is_transmit2_triggered_returnLabel#11 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 12273#L1077-30 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 12274#L1077-32 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 12616#L475-30 assume 1 == ~t3_pc~0; 12990#L476-10 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 12144#L486-10 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 12752#is_transmit3_triggered_returnLabel#11 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 12753#L1085-30 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 12491#L1085-32 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 12492#L494-30 assume 1 == ~t4_pc~0; 12482#L495-10 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 12083#L505-10 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 12084#is_transmit4_triggered_returnLabel#11 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 13056#L1093-30 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 13006#L1093-32 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 13007#L513-30 assume 1 == ~t5_pc~0; 13080#L514-10 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 12622#L524-10 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 12691#is_transmit5_triggered_returnLabel#11 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 12848#L1101-30 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 12914#L1101-32 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 12634#L532-30 assume 1 == ~t6_pc~0; 12635#L533-10 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 12224#L543-10 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 12225#is_transmit6_triggered_returnLabel#11 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 12249#L1109-30 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 12305#L1109-32 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 12306#L551-30 assume !(1 == ~t7_pc~0); 12358#L551-32 is_transmit7_triggered_~__retres1~7#1 := 0; 12424#L562-10 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 12904#is_transmit7_triggered_returnLabel#11 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 12099#L1117-30 assume !(0 != activate_threads_~tmp___6~0#1); 12100#L1117-32 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 12466#L570-30 assume !(1 == ~t8_pc~0); 12820#L570-32 is_transmit8_triggered_~__retres1~8#1 := 0; 12355#L581-10 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 12356#is_transmit8_triggered_returnLabel#11 activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 12157#L1125-30 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 12158#L1125-32 havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 12537#L952-3 assume 1 == ~M_E~0;~M_E~0 := 2; 12581#L952-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 13032#L957-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 13033#L962-3 assume !(1 == ~T3_E~0); 12955#L967-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 12956#L972-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 12875#L977-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 12876#L982-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 13081#L987-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 12523#L992-3 assume 1 == ~E_M~0;~E_M~0 := 2; 12524#L997-3 assume 1 == ~E_1~0;~E_1~0 := 2; 12519#L1002-3 assume !(1 == ~E_2~0); 12520#L1007-3 assume 1 == ~E_3~0;~E_3~0 := 2; 12329#L1012-3 assume 1 == ~E_4~0;~E_4~0 := 2; 12330#L1017-3 assume 1 == ~E_5~0;~E_5~0 := 2; 12431#L1022-3 assume 1 == ~E_6~0;~E_6~0 := 2; 12667#L1027-3 assume 1 == ~E_7~0;~E_7~0 := 2; 12127#L1032-3 assume 1 == ~E_8~0;~E_8~0 := 2; 12128#L1037-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 12373#L650-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 12374#L697-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 12489#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret25#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret25#1;havoc start_simulation_#t~ret25#1; 12490#L1322 assume !(0 == start_simulation_~tmp~3#1); 12551#L1322-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret24#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 12214#L650-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 12215#L697-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 12131#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret24#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret24#1;havoc stop_simulation_#t~ret24#1; 12113#L1277 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 12114#L1284 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 12750#stop_simulation_returnLabel#1 start_simulation_#t~ret26#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret24#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret26#1;havoc start_simulation_#t~ret26#1; 12751#L1335 assume !(0 != start_simulation_~tmp___0~1#1); 12860#L1303-2 [2023-11-12 02:34:18,603 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-12 02:34:18,603 INFO L85 PathProgramCache]: Analyzing trace with hash -803079048, now seen corresponding path program 1 times [2023-11-12 02:34:18,604 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-12 02:34:18,604 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1382342011] [2023-11-12 02:34:18,604 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-12 02:34:18,604 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-12 02:34:18,617 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-12 02:34:18,648 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-12 02:34:18,648 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-12 02:34:18,648 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1382342011] [2023-11-12 02:34:18,648 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1382342011] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-12 02:34:18,649 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-12 02:34:18,649 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-12 02:34:18,649 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2020587179] [2023-11-12 02:34:18,649 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-12 02:34:18,649 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-12 02:34:18,650 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-12 02:34:18,650 INFO L85 PathProgramCache]: Analyzing trace with hash 1773359198, now seen corresponding path program 2 times [2023-11-12 02:34:18,650 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-12 02:34:18,650 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1941787337] [2023-11-12 02:34:18,651 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-12 02:34:18,651 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-12 02:34:18,666 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-12 02:34:18,719 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-12 02:34:18,720 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-12 02:34:18,720 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1941787337] [2023-11-12 02:34:18,720 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1941787337] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-12 02:34:18,720 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-12 02:34:18,720 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-12 02:34:18,721 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1349360119] [2023-11-12 02:34:18,721 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-12 02:34:18,721 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-12 02:34:18,721 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-12 02:34:18,722 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-12 02:34:18,722 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-12 02:34:18,722 INFO L87 Difference]: Start difference. First operand 1002 states and 1485 transitions. cyclomatic complexity: 484 Second operand has 3 states, 3 states have (on average 35.333333333333336) internal successors, (106), 3 states have internal predecessors, (106), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-12 02:34:18,754 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-12 02:34:18,754 INFO L93 Difference]: Finished difference Result 1002 states and 1484 transitions. [2023-11-12 02:34:18,754 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1002 states and 1484 transitions. [2023-11-12 02:34:18,763 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 887 [2023-11-12 02:34:18,772 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1002 states to 1002 states and 1484 transitions. [2023-11-12 02:34:18,772 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1002 [2023-11-12 02:34:18,773 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1002 [2023-11-12 02:34:18,774 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1002 states and 1484 transitions. [2023-11-12 02:34:18,776 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-12 02:34:18,776 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1002 states and 1484 transitions. [2023-11-12 02:34:18,778 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1002 states and 1484 transitions. [2023-11-12 02:34:18,795 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1002 to 1002. [2023-11-12 02:34:18,797 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1002 states, 1002 states have (on average 1.4810379241516967) internal successors, (1484), 1001 states have internal predecessors, (1484), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-12 02:34:18,802 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1002 states to 1002 states and 1484 transitions. [2023-11-12 02:34:18,802 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1002 states and 1484 transitions. [2023-11-12 02:34:18,803 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-12 02:34:18,805 INFO L428 stractBuchiCegarLoop]: Abstraction has 1002 states and 1484 transitions. [2023-11-12 02:34:18,805 INFO L335 stractBuchiCegarLoop]: ======== Iteration 8 ============ [2023-11-12 02:34:18,805 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1002 states and 1484 transitions. [2023-11-12 02:34:18,811 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 887 [2023-11-12 02:34:18,811 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-12 02:34:18,811 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-12 02:34:18,813 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-12 02:34:18,814 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-12 02:34:18,814 INFO L748 eck$LassoCheckResult]: Stem: 14413#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~token~0 := 0;~local~0 := 0; 14414#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~10#1;havoc main_~__retres1~10#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; 15038#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret25#1, start_simulation_#t~ret26#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 15039#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 15077#L597 assume 1 == ~m_i~0;~m_st~0 := 0; 14832#L597-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 14833#L602-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 14430#L607-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 14431#L612-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 14363#L617-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 14364#L622-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 14626#L627-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 14598#L632-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 14599#L637-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 14882#L854 assume !(0 == ~M_E~0); 14689#L854-2 assume !(0 == ~T1_E~0); 14690#L859-1 assume !(0 == ~T2_E~0); 14243#L864-1 assume !(0 == ~T3_E~0); 14244#L869-1 assume !(0 == ~T4_E~0); 14354#L874-1 assume 0 == ~T5_E~0;~T5_E~0 := 1; 15063#L879-1 assume !(0 == ~T6_E~0); 14679#L884-1 assume !(0 == ~T7_E~0); 14106#L889-1 assume !(0 == ~T8_E~0); 14107#L894-1 assume !(0 == ~E_M~0); 14443#L899-1 assume !(0 == ~E_1~0); 14888#L904-1 assume !(0 == ~E_2~0); 14616#L909-1 assume !(0 == ~E_3~0); 14617#L914-1 assume 0 == ~E_4~0;~E_4~0 := 1; 14823#L919-1 assume !(0 == ~E_5~0); 14522#L924-1 assume !(0 == ~E_6~0); 14336#L929-1 assume !(0 == ~E_7~0); 14337#L934-1 assume !(0 == ~E_8~0); 14595#L939-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 14123#L418 assume !(1 == ~m_pc~0); 14098#L418-2 is_master_triggered_~__retres1~0#1 := 0; 14097#L429 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 14992#is_master_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 14978#L1061 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 14911#L1061-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 14912#L437 assume 1 == ~t1_pc~0; 15080#L438 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 14985#L448 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 14146#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 14147#L1069 assume !(0 != activate_threads_~tmp___0~0#1); 14472#L1069-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 14968#L456 assume !(1 == ~t2_pc~0); 14394#L456-2 is_transmit2_triggered_~__retres1~2#1 := 0; 14393#L467 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 14554#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 14555#L1077 assume !(0 != activate_threads_~tmp___1~0#1); 14727#L1077-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 14237#L475 assume 1 == ~t3_pc~0; 14238#L476 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 14301#L486 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 14114#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 14115#L1085 assume !(0 != activate_threads_~tmp___2~0#1); 14475#L1085-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 14476#L494 assume !(1 == ~t4_pc~0); 14516#L494-2 is_transmit4_triggered_~__retres1~4#1 := 0; 14517#L505 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 14253#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 14254#L1093 assume !(0 != activate_threads_~tmp___3~0#1); 14847#L1093-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 14296#L513 assume 1 == ~t5_pc~0; 14297#L514 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 14518#L524 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 14994#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 14250#L1101 assume !(0 != activate_threads_~tmp___4~0#1); 14251#L1101-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 14203#L532 assume !(1 == ~t6_pc~0); 14204#L532-2 is_transmit6_triggered_~__retres1~6#1 := 0; 14355#L543 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 14536#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 14537#L1109 assume !(0 != activate_threads_~tmp___5~0#1); 14447#L1109-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 14448#L551 assume 1 == ~t7_pc~0; 15005#L552 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 14849#L562 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 14850#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 15089#L1117 assume !(0 != activate_threads_~tmp___6~0#1); 15090#L1117-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 14637#L570 assume 1 == ~t8_pc~0; 14638#L571 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 14753#L581 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 14943#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 14749#L1125 assume !(0 != activate_threads_~tmp___7~0#1); 14231#L1125-2 havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 14232#L952 assume 1 == ~M_E~0;~M_E~0 := 2; 14172#L952-2 assume !(1 == ~T1_E~0); 14173#L957-1 assume !(1 == ~T2_E~0); 14949#L962-1 assume !(1 == ~T3_E~0); 14765#L967-1 assume !(1 == ~T4_E~0); 14766#L972-1 assume !(1 == ~T5_E~0); 15008#L977-1 assume !(1 == ~T6_E~0); 15009#L982-1 assume !(1 == ~T7_E~0); 14357#L987-1 assume 1 == ~T8_E~0;~T8_E~0 := 2; 14358#L992-1 assume !(1 == ~E_M~0); 14365#L997-1 assume !(1 == ~E_1~0); 14725#L1002-1 assume !(1 == ~E_2~0); 14710#L1007-1 assume !(1 == ~E_3~0); 14108#L1012-1 assume !(1 == ~E_4~0); 14109#L1017-1 assume !(1 == ~E_5~0); 14713#L1022-1 assume !(1 == ~E_6~0); 14714#L1027-1 assume 1 == ~E_7~0;~E_7~0 := 2; 14739#L1032-1 assume !(1 == ~E_8~0); 14870#L1037-1 assume { :end_inline_reset_delta_events } true; 14871#L1303-2 [2023-11-12 02:34:18,814 INFO L750 eck$LassoCheckResult]: Loop: 14871#L1303-2 assume !false; 14945#L1304 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 14612#L829-1 assume !false; 14908#L708 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 14498#L650 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 14433#L697 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 14576#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 14577#L712 assume !(0 != eval_~tmp~0#1); 14838#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 14747#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 14748#L854-3 assume !(0 == ~M_E~0); 14839#L854-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 14840#L859-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 15088#L864-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 15062#L869-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 14655#L874-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 14656#L879-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 14726#L884-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 14704#L889-3 assume !(0 == ~T8_E~0); 14327#L894-3 assume 0 == ~E_M~0;~E_M~0 := 1; 14328#L899-3 assume 0 == ~E_1~0;~E_1~0 := 1; 14361#L904-3 assume 0 == ~E_2~0;~E_2~0 := 1; 14362#L909-3 assume 0 == ~E_3~0;~E_3~0 := 1; 14306#L914-3 assume 0 == ~E_4~0;~E_4~0 := 1; 14307#L919-3 assume 0 == ~E_5~0;~E_5~0 := 1; 14350#L924-3 assume 0 == ~E_6~0;~E_6~0 := 1; 14914#L929-3 assume !(0 == ~E_7~0); 14825#L934-3 assume 0 == ~E_8~0;~E_8~0 := 1; 14826#L939-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 14933#L418-30 assume !(1 == ~m_pc~0); 14192#L418-32 is_master_triggered_~__retres1~0#1 := 0; 14191#L429-10 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 14567#is_master_triggered_returnLabel#11 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 14568#L1061-30 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 14395#L1061-32 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 14396#L437-30 assume 1 == ~t1_pc~0; 14519#L438-10 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 14745#L448-10 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 14746#is_transmit1_triggered_returnLabel#11 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 14783#L1069-30 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 15079#L1069-32 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 14479#L456-30 assume !(1 == ~t2_pc~0); 14480#L456-32 is_transmit2_triggered_~__retres1~2#1 := 0; 14906#L467-10 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 14478#is_transmit2_triggered_returnLabel#11 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 14284#L1077-30 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 14285#L1077-32 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 14627#L475-30 assume 1 == ~t3_pc~0; 15001#L476-10 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 14155#L486-10 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 14763#is_transmit3_triggered_returnLabel#11 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 14764#L1085-30 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 14502#L1085-32 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 14503#L494-30 assume !(1 == ~t4_pc~0); 14311#L494-32 is_transmit4_triggered_~__retres1~4#1 := 0; 14094#L505-10 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 14095#is_transmit4_triggered_returnLabel#11 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 15067#L1093-30 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 15017#L1093-32 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 15018#L513-30 assume 1 == ~t5_pc~0; 15091#L514-10 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 14633#L524-10 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 14702#is_transmit5_triggered_returnLabel#11 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 14859#L1101-30 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 14925#L1101-32 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 14645#L532-30 assume 1 == ~t6_pc~0; 14646#L533-10 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 14235#L543-10 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 14236#is_transmit6_triggered_returnLabel#11 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 14260#L1109-30 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 14316#L1109-32 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 14317#L551-30 assume !(1 == ~t7_pc~0); 14369#L551-32 is_transmit7_triggered_~__retres1~7#1 := 0; 14435#L562-10 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 14915#is_transmit7_triggered_returnLabel#11 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 14110#L1117-30 assume !(0 != activate_threads_~tmp___6~0#1); 14111#L1117-32 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 14477#L570-30 assume 1 == ~t8_pc~0; 14986#L571-10 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 14366#L581-10 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 14367#is_transmit8_triggered_returnLabel#11 activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 14168#L1125-30 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 14169#L1125-32 havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 14548#L952-3 assume 1 == ~M_E~0;~M_E~0 := 2; 14592#L952-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 15043#L957-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 15044#L962-3 assume !(1 == ~T3_E~0); 14966#L967-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 14967#L972-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 14886#L977-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 14887#L982-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 15092#L987-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 14534#L992-3 assume 1 == ~E_M~0;~E_M~0 := 2; 14535#L997-3 assume 1 == ~E_1~0;~E_1~0 := 2; 14530#L1002-3 assume !(1 == ~E_2~0); 14531#L1007-3 assume 1 == ~E_3~0;~E_3~0 := 2; 14340#L1012-3 assume 1 == ~E_4~0;~E_4~0 := 2; 14341#L1017-3 assume 1 == ~E_5~0;~E_5~0 := 2; 14442#L1022-3 assume 1 == ~E_6~0;~E_6~0 := 2; 14678#L1027-3 assume 1 == ~E_7~0;~E_7~0 := 2; 14138#L1032-3 assume 1 == ~E_8~0;~E_8~0 := 2; 14139#L1037-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 14384#L650-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 14385#L697-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 14500#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret25#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret25#1;havoc start_simulation_#t~ret25#1; 14501#L1322 assume !(0 == start_simulation_~tmp~3#1); 14562#L1322-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret24#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 14225#L650-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 14226#L697-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 14142#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret24#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret24#1;havoc stop_simulation_#t~ret24#1; 14124#L1277 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 14125#L1284 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 14761#stop_simulation_returnLabel#1 start_simulation_#t~ret26#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret24#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret26#1;havoc start_simulation_#t~ret26#1; 14762#L1335 assume !(0 != start_simulation_~tmp___0~1#1); 14871#L1303-2 [2023-11-12 02:34:18,815 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-12 02:34:18,815 INFO L85 PathProgramCache]: Analyzing trace with hash 2140503030, now seen corresponding path program 1 times [2023-11-12 02:34:18,815 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-12 02:34:18,816 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [566217706] [2023-11-12 02:34:18,816 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-12 02:34:18,816 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-12 02:34:18,837 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-12 02:34:18,870 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-12 02:34:18,870 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-12 02:34:18,872 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [566217706] [2023-11-12 02:34:18,872 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [566217706] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-12 02:34:18,872 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-12 02:34:18,873 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-12 02:34:18,878 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1791540482] [2023-11-12 02:34:18,878 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-12 02:34:18,878 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-12 02:34:18,879 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-12 02:34:18,879 INFO L85 PathProgramCache]: Analyzing trace with hash 459444767, now seen corresponding path program 1 times [2023-11-12 02:34:18,879 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-12 02:34:18,882 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1705988103] [2023-11-12 02:34:18,882 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-12 02:34:18,882 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-12 02:34:18,902 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-12 02:34:18,970 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-12 02:34:18,970 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-12 02:34:18,970 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1705988103] [2023-11-12 02:34:18,970 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1705988103] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-12 02:34:18,970 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-12 02:34:18,971 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-12 02:34:18,971 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [615591701] [2023-11-12 02:34:18,971 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-12 02:34:18,971 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-12 02:34:18,972 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-12 02:34:18,972 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-12 02:34:18,972 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-12 02:34:18,972 INFO L87 Difference]: Start difference. First operand 1002 states and 1484 transitions. cyclomatic complexity: 483 Second operand has 3 states, 3 states have (on average 35.333333333333336) internal successors, (106), 3 states have internal predecessors, (106), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-12 02:34:19,006 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-12 02:34:19,006 INFO L93 Difference]: Finished difference Result 1002 states and 1483 transitions. [2023-11-12 02:34:19,006 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1002 states and 1483 transitions. [2023-11-12 02:34:19,014 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 887 [2023-11-12 02:34:19,023 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1002 states to 1002 states and 1483 transitions. [2023-11-12 02:34:19,024 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1002 [2023-11-12 02:34:19,025 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1002 [2023-11-12 02:34:19,025 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1002 states and 1483 transitions. [2023-11-12 02:34:19,027 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-12 02:34:19,027 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1002 states and 1483 transitions. [2023-11-12 02:34:19,029 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1002 states and 1483 transitions. [2023-11-12 02:34:19,045 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1002 to 1002. [2023-11-12 02:34:19,048 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1002 states, 1002 states have (on average 1.4800399201596806) internal successors, (1483), 1001 states have internal predecessors, (1483), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-12 02:34:19,053 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1002 states to 1002 states and 1483 transitions. [2023-11-12 02:34:19,053 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1002 states and 1483 transitions. [2023-11-12 02:34:19,054 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-12 02:34:19,056 INFO L428 stractBuchiCegarLoop]: Abstraction has 1002 states and 1483 transitions. [2023-11-12 02:34:19,056 INFO L335 stractBuchiCegarLoop]: ======== Iteration 9 ============ [2023-11-12 02:34:19,057 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1002 states and 1483 transitions. [2023-11-12 02:34:19,063 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 887 [2023-11-12 02:34:19,063 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-12 02:34:19,063 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-12 02:34:19,065 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-12 02:34:19,065 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-12 02:34:19,065 INFO L748 eck$LassoCheckResult]: Stem: 16424#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~token~0 := 0;~local~0 := 0; 16425#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~10#1;havoc main_~__retres1~10#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; 17049#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret25#1, start_simulation_#t~ret26#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 17050#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 17088#L597 assume 1 == ~m_i~0;~m_st~0 := 0; 16843#L597-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 16844#L602-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 16441#L607-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 16442#L612-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 16374#L617-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 16375#L622-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 16637#L627-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 16609#L632-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 16610#L637-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 16893#L854 assume !(0 == ~M_E~0); 16700#L854-2 assume !(0 == ~T1_E~0); 16701#L859-1 assume !(0 == ~T2_E~0); 16254#L864-1 assume !(0 == ~T3_E~0); 16255#L869-1 assume !(0 == ~T4_E~0); 16365#L874-1 assume 0 == ~T5_E~0;~T5_E~0 := 1; 17074#L879-1 assume !(0 == ~T6_E~0); 16690#L884-1 assume !(0 == ~T7_E~0); 16117#L889-1 assume !(0 == ~T8_E~0); 16118#L894-1 assume !(0 == ~E_M~0); 16454#L899-1 assume !(0 == ~E_1~0); 16899#L904-1 assume !(0 == ~E_2~0); 16627#L909-1 assume !(0 == ~E_3~0); 16628#L914-1 assume 0 == ~E_4~0;~E_4~0 := 1; 16834#L919-1 assume !(0 == ~E_5~0); 16533#L924-1 assume !(0 == ~E_6~0); 16347#L929-1 assume !(0 == ~E_7~0); 16348#L934-1 assume !(0 == ~E_8~0); 16606#L939-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 16134#L418 assume !(1 == ~m_pc~0); 16109#L418-2 is_master_triggered_~__retres1~0#1 := 0; 16108#L429 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 17003#is_master_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 16989#L1061 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 16922#L1061-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 16923#L437 assume 1 == ~t1_pc~0; 17091#L438 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 16996#L448 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 16157#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 16158#L1069 assume !(0 != activate_threads_~tmp___0~0#1); 16483#L1069-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 16979#L456 assume !(1 == ~t2_pc~0); 16405#L456-2 is_transmit2_triggered_~__retres1~2#1 := 0; 16404#L467 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 16565#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 16566#L1077 assume !(0 != activate_threads_~tmp___1~0#1); 16738#L1077-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 16248#L475 assume 1 == ~t3_pc~0; 16249#L476 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 16312#L486 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 16125#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 16126#L1085 assume !(0 != activate_threads_~tmp___2~0#1); 16486#L1085-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 16487#L494 assume !(1 == ~t4_pc~0); 16527#L494-2 is_transmit4_triggered_~__retres1~4#1 := 0; 16528#L505 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 16264#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 16265#L1093 assume !(0 != activate_threads_~tmp___3~0#1); 16858#L1093-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 16307#L513 assume 1 == ~t5_pc~0; 16308#L514 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 16529#L524 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 17005#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 16261#L1101 assume !(0 != activate_threads_~tmp___4~0#1); 16262#L1101-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 16214#L532 assume !(1 == ~t6_pc~0); 16215#L532-2 is_transmit6_triggered_~__retres1~6#1 := 0; 16366#L543 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 16547#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 16548#L1109 assume !(0 != activate_threads_~tmp___5~0#1); 16458#L1109-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 16459#L551 assume 1 == ~t7_pc~0; 17016#L552 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 16860#L562 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 16861#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 17100#L1117 assume !(0 != activate_threads_~tmp___6~0#1); 17101#L1117-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 16648#L570 assume 1 == ~t8_pc~0; 16649#L571 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 16764#L581 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 16954#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 16760#L1125 assume !(0 != activate_threads_~tmp___7~0#1); 16242#L1125-2 havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 16243#L952 assume 1 == ~M_E~0;~M_E~0 := 2; 16183#L952-2 assume !(1 == ~T1_E~0); 16184#L957-1 assume !(1 == ~T2_E~0); 16960#L962-1 assume !(1 == ~T3_E~0); 16776#L967-1 assume !(1 == ~T4_E~0); 16777#L972-1 assume !(1 == ~T5_E~0); 17019#L977-1 assume !(1 == ~T6_E~0); 17020#L982-1 assume !(1 == ~T7_E~0); 16368#L987-1 assume 1 == ~T8_E~0;~T8_E~0 := 2; 16369#L992-1 assume !(1 == ~E_M~0); 16376#L997-1 assume !(1 == ~E_1~0); 16736#L1002-1 assume !(1 == ~E_2~0); 16721#L1007-1 assume !(1 == ~E_3~0); 16119#L1012-1 assume !(1 == ~E_4~0); 16120#L1017-1 assume !(1 == ~E_5~0); 16724#L1022-1 assume !(1 == ~E_6~0); 16725#L1027-1 assume 1 == ~E_7~0;~E_7~0 := 2; 16750#L1032-1 assume !(1 == ~E_8~0); 16881#L1037-1 assume { :end_inline_reset_delta_events } true; 16882#L1303-2 [2023-11-12 02:34:19,066 INFO L750 eck$LassoCheckResult]: Loop: 16882#L1303-2 assume !false; 16956#L1304 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 16623#L829-1 assume !false; 16919#L708 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 16509#L650 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 16444#L697 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 16587#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 16588#L712 assume !(0 != eval_~tmp~0#1); 16849#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 16758#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 16759#L854-3 assume !(0 == ~M_E~0); 16850#L854-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 16851#L859-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 17099#L864-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 17073#L869-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 16666#L874-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 16667#L879-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 16737#L884-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 16715#L889-3 assume !(0 == ~T8_E~0); 16338#L894-3 assume 0 == ~E_M~0;~E_M~0 := 1; 16339#L899-3 assume 0 == ~E_1~0;~E_1~0 := 1; 16372#L904-3 assume 0 == ~E_2~0;~E_2~0 := 1; 16373#L909-3 assume 0 == ~E_3~0;~E_3~0 := 1; 16317#L914-3 assume 0 == ~E_4~0;~E_4~0 := 1; 16318#L919-3 assume 0 == ~E_5~0;~E_5~0 := 1; 16361#L924-3 assume 0 == ~E_6~0;~E_6~0 := 1; 16925#L929-3 assume !(0 == ~E_7~0); 16836#L934-3 assume 0 == ~E_8~0;~E_8~0 := 1; 16837#L939-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 16944#L418-30 assume 1 == ~m_pc~0; 16201#L419-10 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 16202#L429-10 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 16578#is_master_triggered_returnLabel#11 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 16579#L1061-30 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 16406#L1061-32 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 16407#L437-30 assume 1 == ~t1_pc~0; 16530#L438-10 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 16756#L448-10 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 16757#is_transmit1_triggered_returnLabel#11 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 16794#L1069-30 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 17090#L1069-32 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 16490#L456-30 assume !(1 == ~t2_pc~0); 16491#L456-32 is_transmit2_triggered_~__retres1~2#1 := 0; 16917#L467-10 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 16489#is_transmit2_triggered_returnLabel#11 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 16295#L1077-30 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 16296#L1077-32 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 16638#L475-30 assume 1 == ~t3_pc~0; 17012#L476-10 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 16166#L486-10 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 16774#is_transmit3_triggered_returnLabel#11 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 16775#L1085-30 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 16513#L1085-32 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 16514#L494-30 assume !(1 == ~t4_pc~0); 16322#L494-32 is_transmit4_triggered_~__retres1~4#1 := 0; 16105#L505-10 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 16106#is_transmit4_triggered_returnLabel#11 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 17078#L1093-30 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 17028#L1093-32 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 17029#L513-30 assume !(1 == ~t5_pc~0); 16643#L513-32 is_transmit5_triggered_~__retres1~5#1 := 0; 16644#L524-10 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 16713#is_transmit5_triggered_returnLabel#11 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 16870#L1101-30 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 16936#L1101-32 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 16656#L532-30 assume 1 == ~t6_pc~0; 16657#L533-10 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 16246#L543-10 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 16247#is_transmit6_triggered_returnLabel#11 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 16271#L1109-30 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 16327#L1109-32 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 16328#L551-30 assume !(1 == ~t7_pc~0); 16380#L551-32 is_transmit7_triggered_~__retres1~7#1 := 0; 16446#L562-10 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 16926#is_transmit7_triggered_returnLabel#11 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 16121#L1117-30 assume !(0 != activate_threads_~tmp___6~0#1); 16122#L1117-32 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 16488#L570-30 assume 1 == ~t8_pc~0; 16997#L571-10 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 16377#L581-10 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 16378#is_transmit8_triggered_returnLabel#11 activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 16179#L1125-30 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 16180#L1125-32 havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 16559#L952-3 assume 1 == ~M_E~0;~M_E~0 := 2; 16603#L952-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 17054#L957-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 17055#L962-3 assume !(1 == ~T3_E~0); 16977#L967-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 16978#L972-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 16897#L977-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 16898#L982-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 17103#L987-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 16545#L992-3 assume 1 == ~E_M~0;~E_M~0 := 2; 16546#L997-3 assume 1 == ~E_1~0;~E_1~0 := 2; 16541#L1002-3 assume !(1 == ~E_2~0); 16542#L1007-3 assume 1 == ~E_3~0;~E_3~0 := 2; 16351#L1012-3 assume 1 == ~E_4~0;~E_4~0 := 2; 16352#L1017-3 assume 1 == ~E_5~0;~E_5~0 := 2; 16453#L1022-3 assume 1 == ~E_6~0;~E_6~0 := 2; 16689#L1027-3 assume 1 == ~E_7~0;~E_7~0 := 2; 16149#L1032-3 assume 1 == ~E_8~0;~E_8~0 := 2; 16150#L1037-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 16395#L650-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 16396#L697-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 16511#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret25#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret25#1;havoc start_simulation_#t~ret25#1; 16512#L1322 assume !(0 == start_simulation_~tmp~3#1); 16573#L1322-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret24#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 16236#L650-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 16237#L697-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 16153#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret24#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret24#1;havoc stop_simulation_#t~ret24#1; 16135#L1277 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 16136#L1284 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 16772#stop_simulation_returnLabel#1 start_simulation_#t~ret26#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret24#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret26#1;havoc start_simulation_#t~ret26#1; 16773#L1335 assume !(0 != start_simulation_~tmp___0~1#1); 16882#L1303-2 [2023-11-12 02:34:19,066 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-12 02:34:19,067 INFO L85 PathProgramCache]: Analyzing trace with hash -535489352, now seen corresponding path program 1 times [2023-11-12 02:34:19,067 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-12 02:34:19,067 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [135688295] [2023-11-12 02:34:19,067 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-12 02:34:19,067 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-12 02:34:19,094 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-12 02:34:19,171 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-12 02:34:19,171 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-12 02:34:19,171 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [135688295] [2023-11-12 02:34:19,172 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [135688295] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-12 02:34:19,172 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-12 02:34:19,172 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-12 02:34:19,172 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1654609844] [2023-11-12 02:34:19,172 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-12 02:34:19,173 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-12 02:34:19,173 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-12 02:34:19,173 INFO L85 PathProgramCache]: Analyzing trace with hash 568502751, now seen corresponding path program 2 times [2023-11-12 02:34:19,174 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-12 02:34:19,174 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1664636223] [2023-11-12 02:34:19,174 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-12 02:34:19,174 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-12 02:34:19,192 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-12 02:34:19,233 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-12 02:34:19,233 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-12 02:34:19,234 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1664636223] [2023-11-12 02:34:19,234 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1664636223] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-12 02:34:19,234 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-12 02:34:19,234 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-12 02:34:19,234 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [100410223] [2023-11-12 02:34:19,234 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-12 02:34:19,235 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-12 02:34:19,235 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-12 02:34:19,235 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2023-11-12 02:34:19,236 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2023-11-12 02:34:19,236 INFO L87 Difference]: Start difference. First operand 1002 states and 1483 transitions. cyclomatic complexity: 482 Second operand has 4 states, 4 states have (on average 26.5) internal successors, (106), 3 states have internal predecessors, (106), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-12 02:34:19,431 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-12 02:34:19,431 INFO L93 Difference]: Finished difference Result 1824 states and 2689 transitions. [2023-11-12 02:34:19,431 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1824 states and 2689 transitions. [2023-11-12 02:34:19,447 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 1691 [2023-11-12 02:34:19,463 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1824 states to 1824 states and 2689 transitions. [2023-11-12 02:34:19,463 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1824 [2023-11-12 02:34:19,465 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1824 [2023-11-12 02:34:19,466 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1824 states and 2689 transitions. [2023-11-12 02:34:19,469 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-12 02:34:19,469 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1824 states and 2689 transitions. [2023-11-12 02:34:19,472 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1824 states and 2689 transitions. [2023-11-12 02:34:19,511 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1824 to 1824. [2023-11-12 02:34:19,516 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1824 states, 1824 states have (on average 1.4742324561403508) internal successors, (2689), 1823 states have internal predecessors, (2689), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-12 02:34:19,524 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1824 states to 1824 states and 2689 transitions. [2023-11-12 02:34:19,525 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1824 states and 2689 transitions. [2023-11-12 02:34:19,525 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2023-11-12 02:34:19,527 INFO L428 stractBuchiCegarLoop]: Abstraction has 1824 states and 2689 transitions. [2023-11-12 02:34:19,527 INFO L335 stractBuchiCegarLoop]: ======== Iteration 10 ============ [2023-11-12 02:34:19,527 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1824 states and 2689 transitions. [2023-11-12 02:34:19,535 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 1691 [2023-11-12 02:34:19,535 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-12 02:34:19,536 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-12 02:34:19,538 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-12 02:34:19,538 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-12 02:34:19,538 INFO L748 eck$LassoCheckResult]: Stem: 19262#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~token~0 := 0;~local~0 := 0; 19263#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~10#1;havoc main_~__retres1~10#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; 19933#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret25#1, start_simulation_#t~ret26#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 19934#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 19980#L597 assume 1 == ~m_i~0;~m_st~0 := 0; 19692#L597-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 19693#L602-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 19279#L607-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 19280#L612-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 19211#L617-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 19212#L622-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 19481#L627-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 19451#L632-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 19452#L637-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 19747#L854 assume !(0 == ~M_E~0); 19547#L854-2 assume !(0 == ~T1_E~0); 19548#L859-1 assume !(0 == ~T2_E~0); 19090#L864-1 assume !(0 == ~T3_E~0); 19091#L869-1 assume !(0 == ~T4_E~0); 19202#L874-1 assume !(0 == ~T5_E~0); 19965#L879-1 assume !(0 == ~T6_E~0); 19537#L884-1 assume !(0 == ~T7_E~0); 18953#L889-1 assume !(0 == ~T8_E~0); 18954#L894-1 assume !(0 == ~E_M~0); 19292#L899-1 assume !(0 == ~E_1~0); 19753#L904-1 assume !(0 == ~E_2~0); 19470#L909-1 assume !(0 == ~E_3~0); 19471#L914-1 assume 0 == ~E_4~0;~E_4~0 := 1; 19683#L919-1 assume !(0 == ~E_5~0); 19373#L924-1 assume !(0 == ~E_6~0); 19184#L929-1 assume !(0 == ~E_7~0); 19185#L934-1 assume !(0 == ~E_8~0); 19448#L939-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 18970#L418 assume !(1 == ~m_pc~0); 18945#L418-2 is_master_triggered_~__retres1~0#1 := 0; 18944#L429 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 19877#is_master_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 19861#L1061 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 19781#L1061-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 19782#L437 assume 1 == ~t1_pc~0; 19985#L438 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 19869#L448 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 18993#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 18994#L1069 assume !(0 != activate_threads_~tmp___0~0#1); 19322#L1069-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 19851#L456 assume !(1 == ~t2_pc~0); 19243#L456-2 is_transmit2_triggered_~__retres1~2#1 := 0; 19242#L467 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 19407#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 19408#L1077 assume !(0 != activate_threads_~tmp___1~0#1); 19585#L1077-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 19084#L475 assume 1 == ~t3_pc~0; 19085#L476 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 19149#L486 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 18961#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 18962#L1085 assume !(0 != activate_threads_~tmp___2~0#1); 19325#L1085-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 19326#L494 assume !(1 == ~t4_pc~0); 19367#L494-2 is_transmit4_triggered_~__retres1~4#1 := 0; 19368#L505 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 19100#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 19101#L1093 assume !(0 != activate_threads_~tmp___3~0#1); 19708#L1093-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 19143#L513 assume 1 == ~t5_pc~0; 19144#L514 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 19369#L524 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 19879#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 19097#L1101 assume !(0 != activate_threads_~tmp___4~0#1); 19098#L1101-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 19050#L532 assume !(1 == ~t6_pc~0); 19051#L532-2 is_transmit6_triggered_~__retres1~6#1 := 0; 19203#L543 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 19388#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 19389#L1109 assume !(0 != activate_threads_~tmp___5~0#1); 19297#L1109-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 19298#L551 assume 1 == ~t7_pc~0; 19892#L552 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 19710#L562 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 19711#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 19994#L1117 assume !(0 != activate_threads_~tmp___6~0#1); 19995#L1117-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 19492#L570 assume 1 == ~t8_pc~0; 19493#L571 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 19611#L581 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 19819#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 19607#L1125 assume !(0 != activate_threads_~tmp___7~0#1); 19078#L1125-2 havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 19079#L952 assume !(1 == ~M_E~0); 19019#L952-2 assume !(1 == ~T1_E~0); 19020#L957-1 assume !(1 == ~T2_E~0); 20076#L962-1 assume !(1 == ~T3_E~0); 20074#L967-1 assume !(1 == ~T4_E~0); 20073#L972-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 19895#L977-1 assume !(1 == ~T6_E~0); 19896#L982-1 assume !(1 == ~T7_E~0); 19205#L987-1 assume 1 == ~T8_E~0;~T8_E~0 := 2; 19206#L992-1 assume !(1 == ~E_M~0); 19213#L997-1 assume !(1 == ~E_1~0); 19583#L1002-1 assume !(1 == ~E_2~0); 19568#L1007-1 assume !(1 == ~E_3~0); 18955#L1012-1 assume !(1 == ~E_4~0); 18956#L1017-1 assume !(1 == ~E_5~0); 19571#L1022-1 assume !(1 == ~E_6~0); 19572#L1027-1 assume 1 == ~E_7~0;~E_7~0 := 2; 19597#L1032-1 assume !(1 == ~E_8~0); 19734#L1037-1 assume { :end_inline_reset_delta_events } true; 19735#L1303-2 [2023-11-12 02:34:19,539 INFO L750 eck$LassoCheckResult]: Loop: 19735#L1303-2 assume !false; 19862#L1304 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 19466#L829-1 assume !false; 19999#L708 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 20008#L650 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 19897#L697 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 19898#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 20003#L712 assume !(0 != eval_~tmp~0#1); 19823#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 19605#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 19606#L854-3 assume !(0 == ~M_E~0); 20001#L854-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 20585#L859-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 20584#L864-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 20583#L869-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 20582#L874-3 assume !(0 == ~T5_E~0); 20581#L879-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 20580#L884-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 20579#L889-3 assume !(0 == ~T8_E~0); 20578#L894-3 assume 0 == ~E_M~0;~E_M~0 := 1; 20577#L899-3 assume 0 == ~E_1~0;~E_1~0 := 1; 20576#L904-3 assume 0 == ~E_2~0;~E_2~0 := 1; 20575#L909-3 assume 0 == ~E_3~0;~E_3~0 := 1; 20574#L914-3 assume 0 == ~E_4~0;~E_4~0 := 1; 20573#L919-3 assume 0 == ~E_5~0;~E_5~0 := 1; 20572#L924-3 assume 0 == ~E_6~0;~E_6~0 := 1; 20571#L929-3 assume !(0 == ~E_7~0); 20570#L934-3 assume 0 == ~E_8~0;~E_8~0 := 1; 20569#L939-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 20568#L418-30 assume 1 == ~m_pc~0; 20566#L419-10 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 20565#L429-10 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 20564#is_master_triggered_returnLabel#11 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 20563#L1061-30 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 20562#L1061-32 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 20561#L437-30 assume !(1 == ~t1_pc~0); 20560#L437-32 is_transmit1_triggered_~__retres1~1#1 := 0; 20558#L448-10 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 20557#is_transmit1_triggered_returnLabel#11 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 20556#L1069-30 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 20555#L1069-32 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 20554#L456-30 assume !(1 == ~t2_pc~0); 20552#L456-32 is_transmit2_triggered_~__retres1~2#1 := 0; 20551#L467-10 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 20550#is_transmit2_triggered_returnLabel#11 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 20549#L1077-30 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 20548#L1077-32 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 20547#L475-30 assume 1 == ~t3_pc~0; 20545#L476-10 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 20544#L486-10 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 20543#is_transmit3_triggered_returnLabel#11 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 20542#L1085-30 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 20541#L1085-32 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 20540#L494-30 assume !(1 == ~t4_pc~0); 20538#L494-32 is_transmit4_triggered_~__retres1~4#1 := 0; 20537#L505-10 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 20536#is_transmit4_triggered_returnLabel#11 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 20535#L1093-30 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 20534#L1093-32 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 20533#L513-30 assume 1 == ~t5_pc~0; 20531#L514-10 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 20530#L524-10 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 20529#is_transmit5_triggered_returnLabel#11 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 20528#L1101-30 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 20527#L1101-32 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 20526#L532-30 assume !(1 == ~t6_pc~0); 20524#L532-32 is_transmit6_triggered_~__retres1~6#1 := 0; 20523#L543-10 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 20522#is_transmit6_triggered_returnLabel#11 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 20521#L1109-30 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 20520#L1109-32 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 20519#L551-30 assume 1 == ~t7_pc~0; 20517#L552-10 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 20516#L562-10 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 20515#is_transmit7_triggered_returnLabel#11 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 18957#L1117-30 assume !(0 != activate_threads_~tmp___6~0#1); 18958#L1117-32 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 19327#L570-30 assume !(1 == ~t8_pc~0); 19691#L570-32 is_transmit8_triggered_~__retres1~8#1 := 0; 19214#L581-10 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 19215#is_transmit8_triggered_returnLabel#11 activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 19015#L1125-30 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 19016#L1125-32 havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 19401#L952-3 assume 1 == ~M_E~0;~M_E~0 := 2; 19445#L952-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 19938#L957-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 19939#L962-3 assume !(1 == ~T3_E~0); 19848#L967-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 19849#L972-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 19751#L977-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 19752#L982-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 19998#L987-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 19386#L992-3 assume 1 == ~E_M~0;~E_M~0 := 2; 19387#L997-3 assume 1 == ~E_1~0;~E_1~0 := 2; 19382#L1002-3 assume !(1 == ~E_2~0); 19383#L1007-3 assume 1 == ~E_3~0;~E_3~0 := 2; 19188#L1012-3 assume 1 == ~E_4~0;~E_4~0 := 2; 19189#L1017-3 assume 1 == ~E_5~0;~E_5~0 := 2; 19291#L1022-3 assume 1 == ~E_6~0;~E_6~0 := 2; 19536#L1027-3 assume 1 == ~E_7~0;~E_7~0 := 2; 18985#L1032-3 assume 1 == ~E_8~0;~E_8~0 := 2; 18986#L1037-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 19233#L650-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 19234#L697-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 20200#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret25#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret25#1;havoc start_simulation_#t~ret25#1; 20199#L1322 assume !(0 == start_simulation_~tmp~3#1); 19771#L1322-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret24#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 20088#L650-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 19940#L697-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 18989#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret24#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret24#1;havoc stop_simulation_#t~ret24#1; 18971#L1277 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 18972#L1284 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 20060#stop_simulation_returnLabel#1 start_simulation_#t~ret26#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret24#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret26#1;havoc start_simulation_#t~ret26#1; 19900#L1335 assume !(0 != start_simulation_~tmp___0~1#1); 19735#L1303-2 [2023-11-12 02:34:19,539 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-12 02:34:19,539 INFO L85 PathProgramCache]: Analyzing trace with hash -1799592066, now seen corresponding path program 1 times [2023-11-12 02:34:19,539 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-12 02:34:19,540 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [502319000] [2023-11-12 02:34:19,540 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-12 02:34:19,540 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-12 02:34:19,555 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-12 02:34:19,625 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-12 02:34:19,625 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-12 02:34:19,625 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [502319000] [2023-11-12 02:34:19,625 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [502319000] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-12 02:34:19,625 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-12 02:34:19,625 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-12 02:34:19,626 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1796342993] [2023-11-12 02:34:19,626 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-12 02:34:19,627 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-12 02:34:19,628 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-12 02:34:19,628 INFO L85 PathProgramCache]: Analyzing trace with hash -1829389214, now seen corresponding path program 1 times [2023-11-12 02:34:19,628 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-12 02:34:19,628 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1893344020] [2023-11-12 02:34:19,628 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-12 02:34:19,628 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-12 02:34:19,643 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-12 02:34:19,683 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-12 02:34:19,683 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-12 02:34:19,684 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1893344020] [2023-11-12 02:34:19,684 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1893344020] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-12 02:34:19,684 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-12 02:34:19,684 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-12 02:34:19,684 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [266397645] [2023-11-12 02:34:19,684 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-12 02:34:19,685 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-12 02:34:19,685 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-12 02:34:19,685 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2023-11-12 02:34:19,685 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2023-11-12 02:34:19,686 INFO L87 Difference]: Start difference. First operand 1824 states and 2689 transitions. cyclomatic complexity: 867 Second operand has 4 states, 4 states have (on average 26.5) internal successors, (106), 3 states have internal predecessors, (106), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-12 02:34:19,922 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-12 02:34:19,922 INFO L93 Difference]: Finished difference Result 3322 states and 4884 transitions. [2023-11-12 02:34:19,922 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 3322 states and 4884 transitions. [2023-11-12 02:34:19,946 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 3169 [2023-11-12 02:34:19,975 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 3322 states to 3322 states and 4884 transitions. [2023-11-12 02:34:19,975 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 3322 [2023-11-12 02:34:19,980 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 3322 [2023-11-12 02:34:19,980 INFO L73 IsDeterministic]: Start isDeterministic. Operand 3322 states and 4884 transitions. [2023-11-12 02:34:19,986 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-12 02:34:19,986 INFO L218 hiAutomatonCegarLoop]: Abstraction has 3322 states and 4884 transitions. [2023-11-12 02:34:19,991 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3322 states and 4884 transitions. [2023-11-12 02:34:20,052 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3322 to 3320. [2023-11-12 02:34:20,059 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 3320 states, 3320 states have (on average 1.4704819277108434) internal successors, (4882), 3319 states have internal predecessors, (4882), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-12 02:34:20,075 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3320 states to 3320 states and 4882 transitions. [2023-11-12 02:34:20,075 INFO L240 hiAutomatonCegarLoop]: Abstraction has 3320 states and 4882 transitions. [2023-11-12 02:34:20,076 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2023-11-12 02:34:20,077 INFO L428 stractBuchiCegarLoop]: Abstraction has 3320 states and 4882 transitions. [2023-11-12 02:34:20,077 INFO L335 stractBuchiCegarLoop]: ======== Iteration 11 ============ [2023-11-12 02:34:20,077 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 3320 states and 4882 transitions. [2023-11-12 02:34:20,092 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 3169 [2023-11-12 02:34:20,092 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-12 02:34:20,092 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-12 02:34:20,094 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-12 02:34:20,094 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-12 02:34:20,095 INFO L748 eck$LassoCheckResult]: Stem: 24421#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~token~0 := 0;~local~0 := 0; 24422#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~10#1;havoc main_~__retres1~10#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; 25092#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret25#1, start_simulation_#t~ret26#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 25093#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 25141#L597 assume 1 == ~m_i~0;~m_st~0 := 0; 24856#L597-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 24857#L602-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 24438#L607-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 24439#L612-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 24371#L617-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 24372#L622-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 24643#L627-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 24615#L632-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 24616#L637-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 24910#L854 assume !(0 == ~M_E~0); 24709#L854-2 assume !(0 == ~T1_E~0); 24710#L859-1 assume !(0 == ~T2_E~0); 24250#L864-1 assume !(0 == ~T3_E~0); 24251#L869-1 assume !(0 == ~T4_E~0); 24362#L874-1 assume !(0 == ~T5_E~0); 25125#L879-1 assume !(0 == ~T6_E~0); 24699#L884-1 assume !(0 == ~T7_E~0); 24109#L889-1 assume !(0 == ~T8_E~0); 24110#L894-1 assume !(0 == ~E_M~0); 24453#L899-1 assume !(0 == ~E_1~0); 24916#L904-1 assume !(0 == ~E_2~0); 24633#L909-1 assume !(0 == ~E_3~0); 24634#L914-1 assume !(0 == ~E_4~0); 24846#L919-1 assume !(0 == ~E_5~0); 24536#L924-1 assume !(0 == ~E_6~0); 24344#L929-1 assume !(0 == ~E_7~0); 24345#L934-1 assume !(0 == ~E_8~0); 24612#L939-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 24127#L418 assume !(1 == ~m_pc~0); 24101#L418-2 is_master_triggered_~__retres1~0#1 := 0; 24100#L429 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 25035#is_master_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 25020#L1061 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 24940#L1061-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 24941#L437 assume 1 == ~t1_pc~0; 25148#L438 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 25027#L448 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 24150#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 24151#L1069 assume !(0 != activate_threads_~tmp___0~0#1); 24484#L1069-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 25008#L456 assume !(1 == ~t2_pc~0); 24402#L456-2 is_transmit2_triggered_~__retres1~2#1 := 0; 24401#L467 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 24570#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 24571#L1077 assume !(0 != activate_threads_~tmp___1~0#1); 24749#L1077-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 24244#L475 assume 1 == ~t3_pc~0; 24245#L476 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 24309#L486 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 24118#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 24119#L1085 assume !(0 != activate_threads_~tmp___2~0#1); 24487#L1085-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 24488#L494 assume !(1 == ~t4_pc~0); 24530#L494-2 is_transmit4_triggered_~__retres1~4#1 := 0; 24531#L505 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 24260#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 24261#L1093 assume !(0 != activate_threads_~tmp___3~0#1); 24871#L1093-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 24304#L513 assume 1 == ~t5_pc~0; 24305#L514 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 24532#L524 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 25037#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 24257#L1101 assume !(0 != activate_threads_~tmp___4~0#1); 24258#L1101-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 24208#L532 assume !(1 == ~t6_pc~0); 24209#L532-2 is_transmit6_triggered_~__retres1~6#1 := 0; 24363#L543 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 24552#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 24553#L1109 assume !(0 != activate_threads_~tmp___5~0#1); 24459#L1109-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 24460#L551 assume 1 == ~t7_pc~0; 25050#L552 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 24875#L562 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 24876#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 25167#L1117 assume !(0 != activate_threads_~tmp___6~0#1); 25168#L1117-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 24656#L570 assume 1 == ~t8_pc~0; 24657#L571 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 24776#L581 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 24981#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 24772#L1125 assume !(0 != activate_threads_~tmp___7~0#1); 24238#L1125-2 havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 24239#L952 assume !(1 == ~M_E~0); 25031#L952-2 assume !(1 == ~T1_E~0); 24987#L957-1 assume !(1 == ~T2_E~0); 24988#L962-1 assume !(1 == ~T3_E~0); 24788#L967-1 assume !(1 == ~T4_E~0); 24789#L972-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 25615#L977-1 assume !(1 == ~T6_E~0); 25613#L982-1 assume !(1 == ~T7_E~0); 25611#L987-1 assume 1 == ~T8_E~0;~T8_E~0 := 2; 25609#L992-1 assume !(1 == ~E_M~0); 24746#L997-1 assume !(1 == ~E_1~0); 24747#L1002-1 assume !(1 == ~E_2~0); 24730#L1007-1 assume !(1 == ~E_3~0); 24731#L1012-1 assume 1 == ~E_4~0;~E_4~0 := 2; 25277#L1017-1 assume !(1 == ~E_5~0); 25251#L1022-1 assume !(1 == ~E_6~0); 25235#L1027-1 assume 1 == ~E_7~0;~E_7~0 := 2; 25223#L1032-1 assume !(1 == ~E_8~0); 25214#L1037-1 assume { :end_inline_reset_delta_events } true; 25207#L1303-2 [2023-11-12 02:34:20,095 INFO L750 eck$LassoCheckResult]: Loop: 25207#L1303-2 assume !false; 25201#L1304 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 25197#L829-1 assume !false; 25196#L708 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 25191#L650 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 25186#L697 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 25185#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 25183#L712 assume !(0 != eval_~tmp~0#1); 25182#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 25181#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 25180#L854-3 assume !(0 == ~M_E~0); 24863#L854-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 24864#L859-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 25163#L864-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 25122#L869-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 24674#L874-3 assume !(0 == ~T5_E~0); 24675#L879-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 24748#L884-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 24724#L889-3 assume !(0 == ~T8_E~0); 24335#L894-3 assume 0 == ~E_M~0;~E_M~0 := 1; 24336#L899-3 assume 0 == ~E_1~0;~E_1~0 := 1; 24369#L904-3 assume 0 == ~E_2~0;~E_2~0 := 1; 24370#L909-3 assume 0 == ~E_3~0;~E_3~0 := 1; 24314#L914-3 assume !(0 == ~E_4~0); 24315#L919-3 assume 0 == ~E_5~0;~E_5~0 := 1; 24358#L924-3 assume 0 == ~E_6~0;~E_6~0 := 1; 24943#L929-3 assume !(0 == ~E_7~0); 24849#L934-3 assume 0 == ~E_8~0;~E_8~0 := 1; 24850#L939-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 24967#L418-30 assume 1 == ~m_pc~0; 24195#L419-10 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 24196#L429-10 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 24583#is_master_triggered_returnLabel#11 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 24584#L1061-30 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 24403#L1061-32 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 24404#L437-30 assume 1 == ~t1_pc~0; 24533#L438-10 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 24768#L448-10 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 24769#is_transmit1_triggered_returnLabel#11 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 24806#L1069-30 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 25157#L1069-32 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 26466#L456-30 assume !(1 == ~t2_pc~0); 26462#L456-32 is_transmit2_triggered_~__retres1~2#1 := 0; 26460#L467-10 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 26458#is_transmit2_triggered_returnLabel#11 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 26456#L1077-30 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 26454#L1077-32 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 26452#L475-30 assume 1 == ~t3_pc~0; 26448#L476-10 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 26446#L486-10 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 26444#is_transmit3_triggered_returnLabel#11 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 26442#L1085-30 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 26440#L1085-32 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 26438#L494-30 assume !(1 == ~t4_pc~0); 26434#L494-32 is_transmit4_triggered_~__retres1~4#1 := 0; 26432#L505-10 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 26430#is_transmit4_triggered_returnLabel#11 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 26428#L1093-30 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 26426#L1093-32 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 26424#L513-30 assume 1 == ~t5_pc~0; 26420#L514-10 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 26418#L524-10 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 26416#is_transmit5_triggered_returnLabel#11 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 26414#L1101-30 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 26412#L1101-32 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 26410#L532-30 assume !(1 == ~t6_pc~0); 26406#L532-32 is_transmit6_triggered_~__retres1~6#1 := 0; 26404#L543-10 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 26402#is_transmit6_triggered_returnLabel#11 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 26400#L1109-30 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 26398#L1109-32 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 26397#L551-30 assume 1 == ~t7_pc~0; 26392#L552-10 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 26390#L562-10 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 26388#is_transmit7_triggered_returnLabel#11 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 26387#L1117-30 assume !(0 != activate_threads_~tmp___6~0#1); 26386#L1117-32 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 26385#L570-30 assume !(1 == ~t8_pc~0); 26384#L570-32 is_transmit8_triggered_~__retres1~8#1 := 0; 26382#L581-10 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 26381#is_transmit8_triggered_returnLabel#11 activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 26380#L1125-30 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 26379#L1125-32 havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 26378#L952-3 assume 1 == ~M_E~0;~M_E~0 := 2; 24608#L952-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 26377#L957-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 26376#L962-3 assume !(1 == ~T3_E~0); 26374#L967-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 26373#L972-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 25120#L977-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 26369#L982-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 26367#L987-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 26365#L992-3 assume 1 == ~E_M~0;~E_M~0 := 2; 26363#L997-3 assume 1 == ~E_1~0;~E_1~0 := 2; 26361#L1002-3 assume !(1 == ~E_2~0); 24873#L1007-3 assume 1 == ~E_3~0;~E_3~0 := 2; 24874#L1012-3 assume 1 == ~E_4~0;~E_4~0 := 2; 25698#L1017-3 assume 1 == ~E_5~0;~E_5~0 := 2; 25692#L1022-3 assume 1 == ~E_6~0;~E_6~0 := 2; 25686#L1027-3 assume 1 == ~E_7~0;~E_7~0 := 2; 25680#L1032-3 assume 1 == ~E_8~0;~E_8~0 := 2; 25677#L1037-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 25667#L650-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 25654#L697-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 25648#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret25#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret25#1;havoc start_simulation_#t~ret25#1; 25642#L1322 assume !(0 == start_simulation_~tmp~3#1); 24930#L1322-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret24#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 25346#L650-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 25315#L697-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 25281#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret24#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret24#1;havoc stop_simulation_#t~ret24#1; 25253#L1277 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 25236#L1284 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 25224#stop_simulation_returnLabel#1 start_simulation_#t~ret26#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret24#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret26#1;havoc start_simulation_#t~ret26#1; 25215#L1335 assume !(0 != start_simulation_~tmp___0~1#1); 25207#L1303-2 [2023-11-12 02:34:20,096 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-12 02:34:20,096 INFO L85 PathProgramCache]: Analyzing trace with hash -1616610622, now seen corresponding path program 1 times [2023-11-12 02:34:20,096 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-12 02:34:20,096 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1003815492] [2023-11-12 02:34:20,096 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-12 02:34:20,096 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-12 02:34:20,114 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-12 02:34:20,194 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-12 02:34:20,194 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-12 02:34:20,194 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1003815492] [2023-11-12 02:34:20,194 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1003815492] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-12 02:34:20,195 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-12 02:34:20,195 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2023-11-12 02:34:20,195 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [928881417] [2023-11-12 02:34:20,195 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-12 02:34:20,196 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-12 02:34:20,196 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-12 02:34:20,196 INFO L85 PathProgramCache]: Analyzing trace with hash 1462023267, now seen corresponding path program 1 times [2023-11-12 02:34:20,196 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-12 02:34:20,197 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1015552487] [2023-11-12 02:34:20,197 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-12 02:34:20,197 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-12 02:34:20,225 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-12 02:34:20,285 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-12 02:34:20,286 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-12 02:34:20,286 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1015552487] [2023-11-12 02:34:20,286 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1015552487] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-12 02:34:20,286 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-12 02:34:20,286 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-12 02:34:20,286 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1945318079] [2023-11-12 02:34:20,286 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-12 02:34:20,287 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-12 02:34:20,287 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-12 02:34:20,287 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2023-11-12 02:34:20,288 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2023-11-12 02:34:20,288 INFO L87 Difference]: Start difference. First operand 3320 states and 4882 transitions. cyclomatic complexity: 1566 Second operand has 5 states, 5 states have (on average 21.2) internal successors, (106), 5 states have internal predecessors, (106), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-12 02:34:20,702 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-12 02:34:20,702 INFO L93 Difference]: Finished difference Result 8767 states and 12715 transitions. [2023-11-12 02:34:20,703 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 8767 states and 12715 transitions. [2023-11-12 02:34:20,748 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 8444 [2023-11-12 02:34:20,804 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 8767 states to 8767 states and 12715 transitions. [2023-11-12 02:34:20,804 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 8767 [2023-11-12 02:34:20,814 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 8767 [2023-11-12 02:34:20,814 INFO L73 IsDeterministic]: Start isDeterministic. Operand 8767 states and 12715 transitions. [2023-11-12 02:34:20,828 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-12 02:34:20,828 INFO L218 hiAutomatonCegarLoop]: Abstraction has 8767 states and 12715 transitions. [2023-11-12 02:34:20,838 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 8767 states and 12715 transitions. [2023-11-12 02:34:20,922 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 8767 to 3440. [2023-11-12 02:34:20,929 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 3440 states, 3440 states have (on average 1.4540697674418606) internal successors, (5002), 3439 states have internal predecessors, (5002), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-12 02:34:20,940 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3440 states to 3440 states and 5002 transitions. [2023-11-12 02:34:20,940 INFO L240 hiAutomatonCegarLoop]: Abstraction has 3440 states and 5002 transitions. [2023-11-12 02:34:20,940 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2023-11-12 02:34:20,941 INFO L428 stractBuchiCegarLoop]: Abstraction has 3440 states and 5002 transitions. [2023-11-12 02:34:20,941 INFO L335 stractBuchiCegarLoop]: ======== Iteration 12 ============ [2023-11-12 02:34:20,941 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 3440 states and 5002 transitions. [2023-11-12 02:34:20,955 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 3286 [2023-11-12 02:34:20,955 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-12 02:34:20,956 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-12 02:34:20,957 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-12 02:34:20,958 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-12 02:34:20,958 INFO L748 eck$LassoCheckResult]: Stem: 36518#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~token~0 := 0;~local~0 := 0; 36519#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~10#1;havoc main_~__retres1~10#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; 37200#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret25#1, start_simulation_#t~ret26#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 37201#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 37253#L597 assume 1 == ~m_i~0;~m_st~0 := 0; 36951#L597-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 36952#L602-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 36536#L607-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 36537#L612-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 36470#L617-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 36471#L622-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 36733#L627-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 36705#L632-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 36706#L637-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 37007#L854 assume !(0 == ~M_E~0); 36800#L854-2 assume !(0 == ~T1_E~0); 36801#L859-1 assume !(0 == ~T2_E~0); 36347#L864-1 assume !(0 == ~T3_E~0); 36348#L869-1 assume !(0 == ~T4_E~0); 36459#L874-1 assume !(0 == ~T5_E~0); 37236#L879-1 assume !(0 == ~T6_E~0); 36789#L884-1 assume !(0 == ~T7_E~0); 36209#L889-1 assume !(0 == ~T8_E~0); 36210#L894-1 assume !(0 == ~E_M~0); 36550#L899-1 assume !(0 == ~E_1~0); 37013#L904-1 assume !(0 == ~E_2~0); 36724#L909-1 assume !(0 == ~E_3~0); 36725#L914-1 assume !(0 == ~E_4~0); 36942#L919-1 assume !(0 == ~E_5~0); 36627#L924-1 assume !(0 == ~E_6~0); 36445#L929-1 assume !(0 == ~E_7~0); 36446#L934-1 assume !(0 == ~E_8~0); 36702#L939-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 36227#L418 assume !(1 == ~m_pc~0); 36201#L418-2 is_master_triggered_~__retres1~0#1 := 0; 37185#L429 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 37186#is_master_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 37123#L1061 assume !(0 != activate_threads_~tmp~1#1); 37040#L1061-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 37041#L437 assume 1 == ~t1_pc~0; 37259#L438 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 37130#L448 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 36253#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 36254#L1069 assume !(0 != activate_threads_~tmp___0~0#1); 36577#L1069-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 37112#L456 assume !(1 == ~t2_pc~0); 36499#L456-2 is_transmit2_triggered_~__retres1~2#1 := 0; 36498#L467 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 36659#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 36660#L1077 assume !(0 != activate_threads_~tmp___1~0#1); 36840#L1077-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 36341#L475 assume 1 == ~t3_pc~0; 36342#L476 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 36407#L486 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 36218#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 36219#L1085 assume !(0 != activate_threads_~tmp___2~0#1); 36580#L1085-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 36581#L494 assume !(1 == ~t4_pc~0); 36621#L494-2 is_transmit4_triggered_~__retres1~4#1 := 0; 36622#L505 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 36357#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 36358#L1093 assume !(0 != activate_threads_~tmp___3~0#1); 36966#L1093-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 36400#L513 assume 1 == ~t5_pc~0; 36401#L514 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 36624#L524 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 37143#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 36354#L1101 assume !(0 != activate_threads_~tmp___4~0#1); 36355#L1101-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 36307#L532 assume !(1 == ~t6_pc~0); 36308#L532-2 is_transmit6_triggered_~__retres1~6#1 := 0; 36460#L543 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 36641#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 36642#L1109 assume !(0 != activate_threads_~tmp___5~0#1); 36552#L1109-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 36553#L551 assume 1 == ~t7_pc~0; 37157#L552 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 36968#L562 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 36969#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 37279#L1117 assume !(0 != activate_threads_~tmp___6~0#1); 37282#L1117-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 36744#L570 assume 1 == ~t8_pc~0; 36745#L571 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 36866#L581 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 37082#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 36864#L1125 assume !(0 != activate_threads_~tmp___7~0#1); 36339#L1125-2 havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 36340#L952 assume !(1 == ~M_E~0); 36276#L952-2 assume !(1 == ~T1_E~0); 36277#L957-1 assume !(1 == ~T2_E~0); 37261#L962-1 assume !(1 == ~T3_E~0); 37262#L967-1 assume !(1 == ~T4_E~0); 37254#L972-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 37160#L977-1 assume !(1 == ~T6_E~0); 37161#L982-1 assume !(1 == ~T7_E~0); 36462#L987-1 assume 1 == ~T8_E~0;~T8_E~0 := 2; 36463#L992-1 assume !(1 == ~E_M~0); 36472#L997-1 assume !(1 == ~E_1~0); 36838#L1002-1 assume !(1 == ~E_2~0); 37395#L1007-1 assume !(1 == ~E_3~0); 37380#L1012-1 assume 1 == ~E_4~0;~E_4~0 := 2; 37378#L1017-1 assume !(1 == ~E_5~0); 37365#L1022-1 assume !(1 == ~E_6~0); 37352#L1027-1 assume 1 == ~E_7~0;~E_7~0 := 2; 37340#L1032-1 assume !(1 == ~E_8~0); 37331#L1037-1 assume { :end_inline_reset_delta_events } true; 37324#L1303-2 [2023-11-12 02:34:20,959 INFO L750 eck$LassoCheckResult]: Loop: 37324#L1303-2 assume !false; 37318#L1304 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 37314#L829-1 assume !false; 37313#L708 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 37308#L650 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 37303#L697 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 37302#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 37300#L712 assume !(0 != eval_~tmp~0#1); 37299#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 37298#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 37297#L854-3 assume !(0 == ~M_E~0); 36958#L854-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 36959#L859-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 37276#L864-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 37235#L869-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 36762#L874-3 assume !(0 == ~T5_E~0); 36763#L879-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 36839#L884-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 36816#L889-3 assume !(0 == ~T8_E~0); 36431#L894-3 assume 0 == ~E_M~0;~E_M~0 := 1; 36432#L899-3 assume 0 == ~E_1~0;~E_1~0 := 1; 36466#L904-3 assume 0 == ~E_2~0;~E_2~0 := 1; 36467#L909-3 assume 0 == ~E_3~0;~E_3~0 := 1; 36410#L914-3 assume !(0 == ~E_4~0); 36411#L919-3 assume 0 == ~E_5~0;~E_5~0 := 1; 36455#L924-3 assume 0 == ~E_6~0;~E_6~0 := 1; 37043#L929-3 assume !(0 == ~E_7~0); 36944#L934-3 assume 0 == ~E_8~0;~E_8~0 := 1; 36945#L939-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 37162#L418-30 assume 1 == ~m_pc~0; 36298#L419-10 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 36299#L429-10 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 39582#is_master_triggered_returnLabel#11 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 39581#L1061-30 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 36500#L1061-32 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 36501#L437-30 assume 1 == ~t1_pc~0; 36625#L438-10 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 36858#L448-10 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 36859#is_transmit1_triggered_returnLabel#11 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 36900#L1069-30 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 37258#L1069-32 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 36587#L456-30 assume !(1 == ~t2_pc~0); 36588#L456-32 is_transmit2_triggered_~__retres1~2#1 := 0; 37035#L467-10 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 36583#is_transmit2_triggered_returnLabel#11 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 36391#L1077-30 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 36392#L1077-32 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 36734#L475-30 assume 1 == ~t3_pc~0; 39153#L476-10 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 39151#L486-10 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 39149#is_transmit3_triggered_returnLabel#11 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 39147#L1085-30 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 39144#L1085-32 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 39142#L494-30 assume !(1 == ~t4_pc~0); 39139#L494-32 is_transmit4_triggered_~__retres1~4#1 := 0; 38777#L505-10 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 38773#is_transmit4_triggered_returnLabel#11 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 38767#L1093-30 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 38763#L1093-32 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 38750#L513-30 assume 1 == ~t5_pc~0; 38745#L514-10 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 38741#L524-10 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 38736#is_transmit5_triggered_returnLabel#11 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 38730#L1101-30 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 38726#L1101-32 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 38723#L532-30 assume !(1 == ~t6_pc~0); 38710#L532-32 is_transmit6_triggered_~__retres1~6#1 := 0; 38706#L543-10 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 38701#is_transmit6_triggered_returnLabel#11 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 38695#L1109-30 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 38691#L1109-32 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 38687#L551-30 assume 1 == ~t7_pc~0; 38682#L552-10 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 38679#L562-10 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 38675#is_transmit7_triggered_returnLabel#11 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 38573#L1117-30 assume !(0 != activate_threads_~tmp___6~0#1); 38568#L1117-32 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 38564#L570-30 assume 1 == ~t8_pc~0; 38557#L571-10 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 38553#L581-10 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 38549#is_transmit8_triggered_returnLabel#11 activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 38546#L1125-30 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 37505#L1125-32 havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 37504#L952-3 assume 1 == ~M_E~0;~M_E~0 := 2; 36698#L952-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 37503#L957-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 37502#L962-3 assume !(1 == ~T3_E~0); 37501#L967-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 37499#L972-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 37496#L977-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 37495#L982-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 37494#L987-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 37493#L992-3 assume 1 == ~E_M~0;~E_M~0 := 2; 37492#L997-3 assume 1 == ~E_1~0;~E_1~0 := 2; 37491#L1002-3 assume !(1 == ~E_2~0); 37490#L1007-3 assume 1 == ~E_3~0;~E_3~0 := 2; 37489#L1012-3 assume 1 == ~E_4~0;~E_4~0 := 2; 37486#L1017-3 assume 1 == ~E_5~0;~E_5~0 := 2; 37485#L1022-3 assume 1 == ~E_6~0;~E_6~0 := 2; 37484#L1027-3 assume 1 == ~E_7~0;~E_7~0 := 2; 37455#L1032-3 assume 1 == ~E_8~0;~E_8~0 := 2; 37454#L1037-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 37453#L650-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 37443#L697-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 37440#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret25#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret25#1;havoc start_simulation_#t~ret25#1; 37435#L1322 assume !(0 == start_simulation_~tmp~3#1); 37030#L1322-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret24#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 37415#L650-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 37393#L697-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 37379#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret24#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret24#1;havoc stop_simulation_#t~ret24#1; 37366#L1277 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 37353#L1284 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 37341#stop_simulation_returnLabel#1 start_simulation_#t~ret26#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret24#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret26#1;havoc start_simulation_#t~ret26#1; 37332#L1335 assume !(0 != start_simulation_~tmp___0~1#1); 37324#L1303-2 [2023-11-12 02:34:20,959 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-12 02:34:20,959 INFO L85 PathProgramCache]: Analyzing trace with hash -2109236796, now seen corresponding path program 1 times [2023-11-12 02:34:20,960 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-12 02:34:20,960 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1003205676] [2023-11-12 02:34:20,960 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-12 02:34:20,960 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-12 02:34:20,973 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-12 02:34:21,056 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-12 02:34:21,057 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-12 02:34:21,057 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1003205676] [2023-11-12 02:34:21,057 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1003205676] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-12 02:34:21,057 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-12 02:34:21,058 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-12 02:34:21,058 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1076129931] [2023-11-12 02:34:21,058 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-12 02:34:21,058 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-12 02:34:21,059 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-12 02:34:21,059 INFO L85 PathProgramCache]: Analyzing trace with hash 336763298, now seen corresponding path program 1 times [2023-11-12 02:34:21,059 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-12 02:34:21,060 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1344890222] [2023-11-12 02:34:21,060 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-12 02:34:21,060 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-12 02:34:21,077 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-12 02:34:21,122 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-12 02:34:21,123 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-12 02:34:21,123 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1344890222] [2023-11-12 02:34:21,123 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1344890222] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-12 02:34:21,123 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-12 02:34:21,124 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-12 02:34:21,124 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1641553932] [2023-11-12 02:34:21,124 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-12 02:34:21,124 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-12 02:34:21,125 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-12 02:34:21,125 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2023-11-12 02:34:21,125 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2023-11-12 02:34:21,126 INFO L87 Difference]: Start difference. First operand 3440 states and 5002 transitions. cyclomatic complexity: 1566 Second operand has 4 states, 4 states have (on average 26.5) internal successors, (106), 3 states have internal predecessors, (106), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-12 02:34:21,467 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-12 02:34:21,467 INFO L93 Difference]: Finished difference Result 9457 states and 13565 transitions. [2023-11-12 02:34:21,467 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 9457 states and 13565 transitions. [2023-11-12 02:34:21,521 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 9028 [2023-11-12 02:34:21,565 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 9457 states to 9457 states and 13565 transitions. [2023-11-12 02:34:21,565 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 9457 [2023-11-12 02:34:21,576 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 9457 [2023-11-12 02:34:21,577 INFO L73 IsDeterministic]: Start isDeterministic. Operand 9457 states and 13565 transitions. [2023-11-12 02:34:21,592 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-12 02:34:21,592 INFO L218 hiAutomatonCegarLoop]: Abstraction has 9457 states and 13565 transitions. [2023-11-12 02:34:21,604 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 9457 states and 13565 transitions. [2023-11-12 02:34:21,861 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 9457 to 8969. [2023-11-12 02:34:21,878 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 8969 states, 8969 states have (on average 1.4379529490467164) internal successors, (12897), 8968 states have internal predecessors, (12897), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-12 02:34:21,932 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 8969 states to 8969 states and 12897 transitions. [2023-11-12 02:34:21,932 INFO L240 hiAutomatonCegarLoop]: Abstraction has 8969 states and 12897 transitions. [2023-11-12 02:34:21,933 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2023-11-12 02:34:21,934 INFO L428 stractBuchiCegarLoop]: Abstraction has 8969 states and 12897 transitions. [2023-11-12 02:34:21,934 INFO L335 stractBuchiCegarLoop]: ======== Iteration 13 ============ [2023-11-12 02:34:21,934 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 8969 states and 12897 transitions. [2023-11-12 02:34:21,974 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 8800 [2023-11-12 02:34:21,974 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-12 02:34:21,974 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-12 02:34:21,977 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-12 02:34:21,977 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-12 02:34:21,977 INFO L748 eck$LassoCheckResult]: Stem: 49433#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~token~0 := 0;~local~0 := 0; 49434#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~10#1;havoc main_~__retres1~10#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; 50247#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret25#1, start_simulation_#t~ret26#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 50248#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 50351#L597 assume 1 == ~m_i~0;~m_st~0 := 0; 49908#L597-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 49909#L602-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 49450#L607-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 49451#L612-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 49379#L617-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 49380#L622-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 49662#L627-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 49632#L632-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 49633#L637-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 49976#L854 assume !(0 == ~M_E~0); 49737#L854-2 assume !(0 == ~T1_E~0); 49738#L859-1 assume !(0 == ~T2_E~0); 49255#L864-1 assume !(0 == ~T3_E~0); 49256#L869-1 assume !(0 == ~T4_E~0); 49370#L874-1 assume !(0 == ~T5_E~0); 50316#L879-1 assume !(0 == ~T6_E~0); 49728#L884-1 assume !(0 == ~T7_E~0); 49113#L889-1 assume !(0 == ~T8_E~0); 49114#L894-1 assume !(0 == ~E_M~0); 49467#L899-1 assume !(0 == ~E_1~0); 49982#L904-1 assume !(0 == ~E_2~0); 49651#L909-1 assume !(0 == ~E_3~0); 49652#L914-1 assume !(0 == ~E_4~0); 49895#L919-1 assume !(0 == ~E_5~0); 49552#L924-1 assume !(0 == ~E_6~0); 49351#L929-1 assume !(0 == ~E_7~0); 49352#L934-1 assume !(0 == ~E_8~0); 49629#L939-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 49132#L418 assume !(1 == ~m_pc~0); 49133#L418-2 is_master_triggered_~__retres1~0#1 := 0; 50224#L429 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 50143#is_master_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 50121#L1061 assume !(0 != activate_threads_~tmp~1#1); 50009#L1061-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 50010#L437 assume !(1 == ~t1_pc~0); 50295#L437-2 is_transmit1_triggered_~__retres1~1#1 := 0; 50131#L448 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 49157#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 49158#L1069 assume !(0 != activate_threads_~tmp___0~0#1); 49497#L1069-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 50107#L456 assume !(1 == ~t2_pc~0); 49411#L456-2 is_transmit2_triggered_~__retres1~2#1 := 0; 49410#L467 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 49586#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 49587#L1077 assume !(0 != activate_threads_~tmp___1~0#1); 49779#L1077-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 49249#L475 assume 1 == ~t3_pc~0; 49250#L476 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 49316#L486 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 49123#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 49124#L1085 assume !(0 != activate_threads_~tmp___2~0#1); 49500#L1085-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 49501#L494 assume !(1 == ~t4_pc~0); 49546#L494-2 is_transmit4_triggered_~__retres1~4#1 := 0; 49547#L505 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 49265#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 49266#L1093 assume !(0 != activate_threads_~tmp___3~0#1); 49925#L1093-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 49310#L513 assume 1 == ~t5_pc~0; 49311#L514 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 49548#L524 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 50147#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 49262#L1101 assume !(0 != activate_threads_~tmp___4~0#1); 49263#L1101-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 49215#L532 assume !(1 == ~t6_pc~0); 49216#L532-2 is_transmit6_triggered_~__retres1~6#1 := 0; 49371#L543 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 49568#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 49569#L1109 assume !(0 != activate_threads_~tmp___5~0#1); 49473#L1109-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 49474#L551 assume 1 == ~t7_pc~0; 50165#L552 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 49929#L562 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 49930#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 50387#L1117 assume !(0 != activate_threads_~tmp___6~0#1); 50396#L1117-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 49677#L570 assume 1 == ~t8_pc~0; 49678#L571 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 49809#L581 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 50072#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 49804#L1125 assume !(0 != activate_threads_~tmp___7~0#1); 49243#L1125-2 havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 49244#L952 assume !(1 == ~M_E~0); 50135#L952-2 assume !(1 == ~T1_E~0); 56280#L957-1 assume !(1 == ~T2_E~0); 56279#L962-1 assume !(1 == ~T3_E~0); 49826#L967-1 assume !(1 == ~T4_E~0); 49827#L972-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 56189#L977-1 assume !(1 == ~T6_E~0); 56210#L982-1 assume !(1 == ~T7_E~0); 49373#L987-1 assume 1 == ~T8_E~0;~T8_E~0 := 2; 49374#L992-1 assume !(1 == ~E_M~0); 49381#L997-1 assume !(1 == ~E_1~0); 49777#L1002-1 assume !(1 == ~E_2~0); 56133#L1007-1 assume !(1 == ~E_3~0); 56116#L1012-1 assume 1 == ~E_4~0;~E_4~0 := 2; 56098#L1017-1 assume !(1 == ~E_5~0); 56080#L1022-1 assume !(1 == ~E_6~0); 56065#L1027-1 assume 1 == ~E_7~0;~E_7~0 := 2; 56053#L1032-1 assume !(1 == ~E_8~0); 56044#L1037-1 assume { :end_inline_reset_delta_events } true; 56037#L1303-2 [2023-11-12 02:34:21,978 INFO L750 eck$LassoCheckResult]: Loop: 56037#L1303-2 assume !false; 56031#L1304 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 56027#L829-1 assume !false; 56026#L708 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 56021#L650 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 56016#L697 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 56015#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 56013#L712 assume !(0 != eval_~tmp~0#1); 56014#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 56759#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 56757#L854-3 assume !(0 == ~M_E~0); 56755#L854-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 56752#L859-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 56750#L864-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 56748#L869-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 56746#L874-3 assume !(0 == ~T5_E~0); 56744#L879-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 56742#L884-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 56739#L889-3 assume !(0 == ~T8_E~0); 56737#L894-3 assume 0 == ~E_M~0;~E_M~0 := 1; 56735#L899-3 assume 0 == ~E_1~0;~E_1~0 := 1; 56733#L904-3 assume 0 == ~E_2~0;~E_2~0 := 1; 56731#L909-3 assume 0 == ~E_3~0;~E_3~0 := 1; 56729#L914-3 assume !(0 == ~E_4~0); 56726#L919-3 assume 0 == ~E_5~0;~E_5~0 := 1; 56724#L924-3 assume 0 == ~E_6~0;~E_6~0 := 1; 56722#L929-3 assume !(0 == ~E_7~0); 56721#L934-3 assume 0 == ~E_8~0;~E_8~0 := 1; 56720#L939-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 56719#L418-30 assume !(1 == ~m_pc~0); 56718#L418-32 is_master_triggered_~__retres1~0#1 := 0; 56716#L429-10 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 56714#is_master_triggered_returnLabel#11 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 56712#L1061-30 assume !(0 != activate_threads_~tmp~1#1); 56710#L1061-32 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 56708#L437-30 assume !(1 == ~t1_pc~0); 56706#L437-32 is_transmit1_triggered_~__retres1~1#1 := 0; 56704#L448-10 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 56702#is_transmit1_triggered_returnLabel#11 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 56700#L1069-30 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 56698#L1069-32 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 56696#L456-30 assume !(1 == ~t2_pc~0); 56693#L456-32 is_transmit2_triggered_~__retres1~2#1 := 0; 56691#L467-10 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 56688#is_transmit2_triggered_returnLabel#11 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 56686#L1077-30 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 56684#L1077-32 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 56682#L475-30 assume 1 == ~t3_pc~0; 56679#L476-10 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 56677#L486-10 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 56674#is_transmit3_triggered_returnLabel#11 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 56672#L1085-30 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 56670#L1085-32 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 56668#L494-30 assume !(1 == ~t4_pc~0); 56665#L494-32 is_transmit4_triggered_~__retres1~4#1 := 0; 56663#L505-10 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 56660#is_transmit4_triggered_returnLabel#11 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 56658#L1093-30 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 56656#L1093-32 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 56654#L513-30 assume 1 == ~t5_pc~0; 56651#L514-10 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 56649#L524-10 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 56646#is_transmit5_triggered_returnLabel#11 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 56644#L1101-30 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 56642#L1101-32 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 56640#L532-30 assume !(1 == ~t6_pc~0); 56637#L532-32 is_transmit6_triggered_~__retres1~6#1 := 0; 56635#L543-10 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 56632#is_transmit6_triggered_returnLabel#11 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 56630#L1109-30 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 56628#L1109-32 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 56626#L551-30 assume !(1 == ~t7_pc~0); 56624#L551-32 is_transmit7_triggered_~__retres1~7#1 := 0; 56621#L562-10 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 56618#is_transmit7_triggered_returnLabel#11 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 56616#L1117-30 assume !(0 != activate_threads_~tmp___6~0#1); 56614#L1117-32 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 56612#L570-30 assume 1 == ~t8_pc~0; 56609#L571-10 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 56607#L581-10 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 56604#is_transmit8_triggered_returnLabel#11 activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 56602#L1125-30 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 56600#L1125-32 havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 56598#L952-3 assume 1 == ~M_E~0;~M_E~0 := 2; 49625#L952-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 56596#L957-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 56595#L962-3 assume !(1 == ~T3_E~0); 56593#L967-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 56591#L972-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 56587#L977-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 56585#L982-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 56583#L987-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 56581#L992-3 assume 1 == ~E_M~0;~E_M~0 := 2; 56579#L997-3 assume 1 == ~E_1~0;~E_1~0 := 2; 56339#L1002-3 assume !(1 == ~E_2~0); 56334#L1007-3 assume 1 == ~E_3~0;~E_3~0 := 2; 56332#L1012-3 assume 1 == ~E_4~0;~E_4~0 := 2; 56327#L1017-3 assume 1 == ~E_5~0;~E_5~0 := 2; 56325#L1022-3 assume 1 == ~E_6~0;~E_6~0 := 2; 56324#L1027-3 assume 1 == ~E_7~0;~E_7~0 := 2; 56291#L1032-3 assume 1 == ~E_8~0;~E_8~0 := 2; 56241#L1037-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 56201#L650-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 56192#L697-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 56191#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret25#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret25#1;havoc start_simulation_#t~ret25#1; 56190#L1322 assume !(0 == start_simulation_~tmp~3#1); 51559#L1322-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret24#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 56139#L650-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 56118#L697-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 56099#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret24#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret24#1;havoc stop_simulation_#t~ret24#1; 56082#L1277 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 56066#L1284 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 56054#stop_simulation_returnLabel#1 start_simulation_#t~ret26#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret24#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret26#1;havoc start_simulation_#t~ret26#1; 56045#L1335 assume !(0 != start_simulation_~tmp___0~1#1); 56037#L1303-2 [2023-11-12 02:34:21,979 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-12 02:34:21,979 INFO L85 PathProgramCache]: Analyzing trace with hash 28257477, now seen corresponding path program 1 times [2023-11-12 02:34:21,979 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-12 02:34:21,980 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1212029280] [2023-11-12 02:34:21,980 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-12 02:34:21,980 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-12 02:34:21,994 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-12 02:34:22,055 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-12 02:34:22,056 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-12 02:34:22,056 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1212029280] [2023-11-12 02:34:22,056 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1212029280] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-12 02:34:22,056 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-12 02:34:22,057 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-12 02:34:22,057 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1989615247] [2023-11-12 02:34:22,057 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-12 02:34:22,057 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-12 02:34:22,058 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-12 02:34:22,058 INFO L85 PathProgramCache]: Analyzing trace with hash -976758297, now seen corresponding path program 1 times [2023-11-12 02:34:22,058 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-12 02:34:22,058 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [738124424] [2023-11-12 02:34:22,059 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-12 02:34:22,059 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-12 02:34:22,073 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-12 02:34:22,111 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-12 02:34:22,111 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-12 02:34:22,111 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [738124424] [2023-11-12 02:34:22,111 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [738124424] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-12 02:34:22,112 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-12 02:34:22,112 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-12 02:34:22,112 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1780555534] [2023-11-12 02:34:22,112 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-12 02:34:22,112 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-12 02:34:22,113 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-12 02:34:22,113 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2023-11-12 02:34:22,113 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2023-11-12 02:34:22,114 INFO L87 Difference]: Start difference. First operand 8969 states and 12897 transitions. cyclomatic complexity: 3936 Second operand has 4 states, 4 states have (on average 26.5) internal successors, (106), 3 states have internal predecessors, (106), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-12 02:34:22,592 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-12 02:34:22,593 INFO L93 Difference]: Finished difference Result 25532 states and 36298 transitions. [2023-11-12 02:34:22,593 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 25532 states and 36298 transitions. [2023-11-12 02:34:22,727 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 24752 [2023-11-12 02:34:22,935 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 25532 states to 25532 states and 36298 transitions. [2023-11-12 02:34:22,935 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 25532 [2023-11-12 02:34:22,964 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 25532 [2023-11-12 02:34:22,964 INFO L73 IsDeterministic]: Start isDeterministic. Operand 25532 states and 36298 transitions. [2023-11-12 02:34:22,993 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-12 02:34:22,993 INFO L218 hiAutomatonCegarLoop]: Abstraction has 25532 states and 36298 transitions. [2023-11-12 02:34:23,023 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 25532 states and 36298 transitions. [2023-11-12 02:34:23,540 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 25532 to 24702. [2023-11-12 02:34:23,582 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 24702 states, 24702 states have (on average 1.4243381102744717) internal successors, (35184), 24701 states have internal predecessors, (35184), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-12 02:34:23,683 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 24702 states to 24702 states and 35184 transitions. [2023-11-12 02:34:23,683 INFO L240 hiAutomatonCegarLoop]: Abstraction has 24702 states and 35184 transitions. [2023-11-12 02:34:23,684 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2023-11-12 02:34:23,684 INFO L428 stractBuchiCegarLoop]: Abstraction has 24702 states and 35184 transitions. [2023-11-12 02:34:23,685 INFO L335 stractBuchiCegarLoop]: ======== Iteration 14 ============ [2023-11-12 02:34:23,685 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 24702 states and 35184 transitions. [2023-11-12 02:34:23,930 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 24494 [2023-11-12 02:34:23,930 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-12 02:34:23,930 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-12 02:34:23,933 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-12 02:34:23,933 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-12 02:34:23,933 INFO L748 eck$LassoCheckResult]: Stem: 83934#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~token~0 := 0;~local~0 := 0; 83935#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~10#1;havoc main_~__retres1~10#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; 84681#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret25#1, start_simulation_#t~ret26#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 84682#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 84757#L597 assume 1 == ~m_i~0;~m_st~0 := 0; 84384#L597-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 84385#L602-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 83954#L607-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 83955#L612-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 83883#L617-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 83884#L622-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 84155#L627-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 84125#L632-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 84126#L637-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 84449#L854 assume !(0 == ~M_E~0); 84225#L854-2 assume !(0 == ~T1_E~0); 84226#L859-1 assume !(0 == ~T2_E~0); 83760#L864-1 assume !(0 == ~T3_E~0); 83761#L869-1 assume !(0 == ~T4_E~0); 83872#L874-1 assume !(0 == ~T5_E~0); 84730#L879-1 assume !(0 == ~T6_E~0); 84212#L884-1 assume !(0 == ~T7_E~0); 83624#L889-1 assume !(0 == ~T8_E~0); 83625#L894-1 assume !(0 == ~E_M~0); 83966#L899-1 assume !(0 == ~E_1~0); 84456#L904-1 assume !(0 == ~E_2~0); 84147#L909-1 assume !(0 == ~E_3~0); 84148#L914-1 assume !(0 == ~E_4~0); 84373#L919-1 assume !(0 == ~E_5~0); 84044#L924-1 assume !(0 == ~E_6~0); 83858#L929-1 assume !(0 == ~E_7~0); 83859#L934-1 assume !(0 == ~E_8~0); 84124#L939-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 83641#L418 assume !(1 == ~m_pc~0); 83642#L418-2 is_master_triggered_~__retres1~0#1 := 0; 84663#L429 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 84597#is_master_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 84580#L1061 assume !(0 != activate_threads_~tmp~1#1); 84483#L1061-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 84484#L437 assume !(1 == ~t1_pc~0); 84714#L437-2 is_transmit1_triggered_~__retres1~1#1 := 0; 84587#L448 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 83668#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 83669#L1069 assume !(0 != activate_threads_~tmp___0~0#1); 83992#L1069-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 84570#L456 assume !(1 == ~t2_pc~0); 83915#L456-2 is_transmit2_triggered_~__retres1~2#1 := 0; 83914#L467 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 84077#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 84078#L1077 assume !(0 != activate_threads_~tmp___1~0#1); 84259#L1077-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 83755#L475 assume !(1 == ~t3_pc~0); 83756#L475-2 is_transmit3_triggered_~__retres1~3#1 := 0; 83820#L486 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 83632#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 83633#L1085 assume !(0 != activate_threads_~tmp___2~0#1); 83995#L1085-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 83996#L494 assume !(1 == ~t4_pc~0); 84038#L494-2 is_transmit4_triggered_~__retres1~4#1 := 0; 84039#L505 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 83770#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 83771#L1093 assume !(0 != activate_threads_~tmp___3~0#1); 84399#L1093-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 83815#L513 assume 1 == ~t5_pc~0; 83816#L514 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 84043#L524 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 84599#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 83767#L1101 assume !(0 != activate_threads_~tmp___4~0#1); 83768#L1101-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 83723#L532 assume !(1 == ~t6_pc~0); 83724#L532-2 is_transmit6_triggered_~__retres1~6#1 := 0; 83873#L543 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 84059#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 84060#L1109 assume !(0 != activate_threads_~tmp___5~0#1); 83968#L1109-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 83969#L551 assume 1 == ~t7_pc~0; 84617#L552 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 84402#L562 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 84403#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 84787#L1117 assume !(0 != activate_threads_~tmp___6~0#1); 84791#L1117-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 84167#L570 assume 1 == ~t8_pc~0; 84168#L571 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 84289#L581 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 84535#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 84286#L1125 assume !(0 != activate_threads_~tmp___7~0#1); 83753#L1125-2 havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 83754#L952 assume !(1 == ~M_E~0); 84593#L952-2 assume !(1 == ~T1_E~0); 84544#L957-1 assume !(1 == ~T2_E~0); 84545#L962-1 assume !(1 == ~T3_E~0); 84306#L967-1 assume !(1 == ~T4_E~0); 84307#L972-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 87977#L977-1 assume !(1 == ~T6_E~0); 84792#L982-1 assume !(1 == ~T7_E~0); 84793#L987-1 assume 1 == ~T8_E~0;~T8_E~0 := 2; 83885#L992-1 assume !(1 == ~E_M~0); 83886#L997-1 assume !(1 == ~E_1~0); 88026#L1002-1 assume !(1 == ~E_2~0); 88025#L1007-1 assume !(1 == ~E_3~0); 88024#L1012-1 assume 1 == ~E_4~0;~E_4~0 := 2; 83627#L1017-1 assume !(1 == ~E_5~0); 84246#L1022-1 assume !(1 == ~E_6~0); 84247#L1027-1 assume 1 == ~E_7~0;~E_7~0 := 2; 84732#L1032-1 assume !(1 == ~E_8~0); 84733#L1037-1 assume { :end_inline_reset_delta_events } true; 89001#L1303-2 [2023-11-12 02:34:23,934 INFO L750 eck$LassoCheckResult]: Loop: 89001#L1303-2 assume !false; 92314#L1304 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 92310#L829-1 assume !false; 92309#L708 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 91229#L650 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 91224#L697 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 91223#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 91221#L712 assume !(0 != eval_~tmp~0#1); 91222#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 92527#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 92526#L854-3 assume !(0 == ~M_E~0); 92525#L854-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 92524#L859-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 92523#L864-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 92522#L869-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 92521#L874-3 assume !(0 == ~T5_E~0); 92520#L879-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 92519#L884-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 92518#L889-3 assume !(0 == ~T8_E~0); 92517#L894-3 assume 0 == ~E_M~0;~E_M~0 := 1; 92516#L899-3 assume 0 == ~E_1~0;~E_1~0 := 1; 92515#L904-3 assume 0 == ~E_2~0;~E_2~0 := 1; 92514#L909-3 assume 0 == ~E_3~0;~E_3~0 := 1; 92513#L914-3 assume !(0 == ~E_4~0); 92512#L919-3 assume 0 == ~E_5~0;~E_5~0 := 1; 92511#L924-3 assume 0 == ~E_6~0;~E_6~0 := 1; 92510#L929-3 assume !(0 == ~E_7~0); 92509#L934-3 assume 0 == ~E_8~0;~E_8~0 := 1; 92508#L939-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 92507#L418-30 assume !(1 == ~m_pc~0); 92506#L418-32 is_master_triggered_~__retres1~0#1 := 0; 92505#L429-10 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 92504#is_master_triggered_returnLabel#11 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 92503#L1061-30 assume !(0 != activate_threads_~tmp~1#1); 92502#L1061-32 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 92501#L437-30 assume !(1 == ~t1_pc~0); 92500#L437-32 is_transmit1_triggered_~__retres1~1#1 := 0; 92499#L448-10 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 92498#is_transmit1_triggered_returnLabel#11 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 92497#L1069-30 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 92496#L1069-32 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 92495#L456-30 assume !(1 == ~t2_pc~0); 92493#L456-32 is_transmit2_triggered_~__retres1~2#1 := 0; 92492#L467-10 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 92491#is_transmit2_triggered_returnLabel#11 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 92490#L1077-30 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 92489#L1077-32 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 92488#L475-30 assume !(1 == ~t3_pc~0); 92487#L475-32 is_transmit3_triggered_~__retres1~3#1 := 0; 92486#L486-10 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 92485#is_transmit3_triggered_returnLabel#11 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 92484#L1085-30 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 92483#L1085-32 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 92482#L494-30 assume 1 == ~t4_pc~0; 92481#L495-10 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 92479#L505-10 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 92478#is_transmit4_triggered_returnLabel#11 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 92477#L1093-30 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 92476#L1093-32 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 92475#L513-30 assume 1 == ~t5_pc~0; 92473#L514-10 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 92472#L524-10 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 92471#is_transmit5_triggered_returnLabel#11 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 92470#L1101-30 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 92469#L1101-32 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 92468#L532-30 assume 1 == ~t6_pc~0; 92467#L533-10 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 92465#L543-10 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 92464#is_transmit6_triggered_returnLabel#11 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 92463#L1109-30 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 92462#L1109-32 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 92461#L551-30 assume 1 == ~t7_pc~0; 92459#L552-10 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 92458#L562-10 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 92457#is_transmit7_triggered_returnLabel#11 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 92456#L1117-30 assume !(0 != activate_threads_~tmp___6~0#1); 92455#L1117-32 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 92454#L570-30 assume !(1 == ~t8_pc~0); 92453#L570-32 is_transmit8_triggered_~__retres1~8#1 := 0; 92451#L581-10 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 92450#is_transmit8_triggered_returnLabel#11 activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 92449#L1125-30 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 92448#L1125-32 havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 92447#L952-3 assume 1 == ~M_E~0;~M_E~0 := 2; 91724#L952-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 92446#L957-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 92445#L962-3 assume !(1 == ~T3_E~0); 92444#L967-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 92356#L972-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 92355#L977-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 92354#L982-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 92353#L987-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 92352#L992-3 assume 1 == ~E_M~0;~E_M~0 := 2; 92351#L997-3 assume 1 == ~E_1~0;~E_1~0 := 2; 92350#L1002-3 assume !(1 == ~E_2~0); 92349#L1007-3 assume 1 == ~E_3~0;~E_3~0 := 2; 92348#L1012-3 assume 1 == ~E_4~0;~E_4~0 := 2; 91708#L1017-3 assume 1 == ~E_5~0;~E_5~0 := 2; 92347#L1022-3 assume 1 == ~E_6~0;~E_6~0 := 2; 92346#L1027-3 assume 1 == ~E_7~0;~E_7~0 := 2; 92345#L1032-3 assume 1 == ~E_8~0;~E_8~0 := 2; 92344#L1037-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 92343#L650-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 92334#L697-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 92333#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret25#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret25#1;havoc start_simulation_#t~ret25#1; 92332#L1322 assume !(0 == start_simulation_~tmp~3#1); 92330#L1322-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret24#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 92325#L650-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 92320#L697-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 92319#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret24#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret24#1;havoc stop_simulation_#t~ret24#1; 92318#L1277 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 92317#L1284 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 92316#stop_simulation_returnLabel#1 start_simulation_#t~ret26#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret24#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret26#1;havoc start_simulation_#t~ret26#1; 92315#L1335 assume !(0 != start_simulation_~tmp___0~1#1); 89001#L1303-2 [2023-11-12 02:34:23,935 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-12 02:34:23,935 INFO L85 PathProgramCache]: Analyzing trace with hash -1079871162, now seen corresponding path program 1 times [2023-11-12 02:34:23,935 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-12 02:34:23,936 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1859981796] [2023-11-12 02:34:23,936 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-12 02:34:23,936 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-12 02:34:23,953 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-12 02:34:24,003 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-12 02:34:24,004 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-12 02:34:24,004 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1859981796] [2023-11-12 02:34:24,004 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1859981796] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-12 02:34:24,004 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-12 02:34:24,005 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2023-11-12 02:34:24,005 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1142231947] [2023-11-12 02:34:24,005 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-12 02:34:24,005 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-12 02:34:24,006 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-12 02:34:24,006 INFO L85 PathProgramCache]: Analyzing trace with hash -2109269850, now seen corresponding path program 1 times [2023-11-12 02:34:24,006 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-12 02:34:24,007 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [574330121] [2023-11-12 02:34:24,007 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-12 02:34:24,007 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-12 02:34:24,022 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-12 02:34:24,057 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-12 02:34:24,057 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-12 02:34:24,057 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [574330121] [2023-11-12 02:34:24,058 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [574330121] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-12 02:34:24,058 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-12 02:34:24,058 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-12 02:34:24,058 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1152276047] [2023-11-12 02:34:24,058 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-12 02:34:24,059 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-12 02:34:24,059 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-12 02:34:24,059 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-12 02:34:24,060 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-12 02:34:24,060 INFO L87 Difference]: Start difference. First operand 24702 states and 35184 transitions. cyclomatic complexity: 10498 Second operand has 3 states, 3 states have (on average 35.333333333333336) internal successors, (106), 2 states have internal predecessors, (106), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-12 02:34:24,481 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-12 02:34:24,481 INFO L93 Difference]: Finished difference Result 46640 states and 66145 transitions. [2023-11-12 02:34:24,481 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 46640 states and 66145 transitions. [2023-11-12 02:34:24,703 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 46301 [2023-11-12 02:34:25,054 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 46640 states to 46640 states and 66145 transitions. [2023-11-12 02:34:25,054 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 46640 [2023-11-12 02:34:25,110 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 46640 [2023-11-12 02:34:25,110 INFO L73 IsDeterministic]: Start isDeterministic. Operand 46640 states and 66145 transitions. [2023-11-12 02:34:25,166 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-12 02:34:25,167 INFO L218 hiAutomatonCegarLoop]: Abstraction has 46640 states and 66145 transitions. [2023-11-12 02:34:25,217 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 46640 states and 66145 transitions. [2023-11-12 02:34:26,090 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 46640 to 46568. [2023-11-12 02:34:26,151 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 46568 states, 46568 states have (on average 1.4188498539769798) internal successors, (66073), 46567 states have internal predecessors, (66073), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-12 02:34:26,459 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 46568 states to 46568 states and 66073 transitions. [2023-11-12 02:34:26,459 INFO L240 hiAutomatonCegarLoop]: Abstraction has 46568 states and 66073 transitions. [2023-11-12 02:34:26,459 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-12 02:34:26,460 INFO L428 stractBuchiCegarLoop]: Abstraction has 46568 states and 66073 transitions. [2023-11-12 02:34:26,460 INFO L335 stractBuchiCegarLoop]: ======== Iteration 15 ============ [2023-11-12 02:34:26,461 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 46568 states and 66073 transitions. [2023-11-12 02:34:26,609 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 46229 [2023-11-12 02:34:26,609 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-12 02:34:26,610 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-12 02:34:26,612 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-12 02:34:26,612 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-12 02:34:26,612 INFO L748 eck$LassoCheckResult]: Stem: 155284#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~token~0 := 0;~local~0 := 0; 155285#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~10#1;havoc main_~__retres1~10#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; 156011#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret25#1, start_simulation_#t~ret26#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 156012#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 156098#L597 assume 1 == ~m_i~0;~m_st~0 := 0; 155735#L597-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 155736#L602-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 155304#L607-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 155305#L612-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 155231#L617-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 155232#L622-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 155503#L627-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 155473#L632-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 155474#L637-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 155797#L854 assume !(0 == ~M_E~0); 155575#L854-2 assume !(0 == ~T1_E~0); 155576#L859-1 assume !(0 == ~T2_E~0); 155109#L864-1 assume !(0 == ~T3_E~0); 155110#L869-1 assume !(0 == ~T4_E~0); 155220#L874-1 assume !(0 == ~T5_E~0); 156069#L879-1 assume !(0 == ~T6_E~0); 155561#L884-1 assume !(0 == ~T7_E~0); 154972#L889-1 assume !(0 == ~T8_E~0); 154973#L894-1 assume !(0 == ~E_M~0); 155315#L899-1 assume !(0 == ~E_1~0); 155803#L904-1 assume !(0 == ~E_2~0); 155495#L909-1 assume !(0 == ~E_3~0); 155496#L914-1 assume !(0 == ~E_4~0); 155720#L919-1 assume !(0 == ~E_5~0); 155394#L924-1 assume !(0 == ~E_6~0); 155206#L929-1 assume !(0 == ~E_7~0); 155207#L934-1 assume !(0 == ~E_8~0); 155470#L939-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 154990#L418 assume !(1 == ~m_pc~0); 154991#L418-2 is_master_triggered_~__retres1~0#1 := 0; 155990#L429 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 155929#is_master_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 155915#L1061 assume !(0 != activate_threads_~tmp~1#1); 155826#L1061-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 155827#L437 assume !(1 == ~t1_pc~0); 156053#L437-2 is_transmit1_triggered_~__retres1~1#1 := 0; 155922#L448 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 155014#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 155015#L1069 assume !(0 != activate_threads_~tmp___0~0#1); 155341#L1069-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 155908#L456 assume !(1 == ~t2_pc~0); 155264#L456-2 is_transmit2_triggered_~__retres1~2#1 := 0; 155263#L467 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 155427#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 155428#L1077 assume !(0 != activate_threads_~tmp___1~0#1); 155611#L1077-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 155104#L475 assume !(1 == ~t3_pc~0); 155105#L475-2 is_transmit3_triggered_~__retres1~3#1 := 0; 155169#L486 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 154981#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 154982#L1085 assume !(0 != activate_threads_~tmp___2~0#1); 155344#L1085-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 155345#L494 assume !(1 == ~t4_pc~0); 155388#L494-2 is_transmit4_triggered_~__retres1~4#1 := 0; 155389#L505 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 155119#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 155120#L1093 assume !(0 != activate_threads_~tmp___3~0#1); 155751#L1093-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 155165#L513 assume !(1 == ~t5_pc~0); 155166#L513-2 is_transmit5_triggered_~__retres1~5#1 := 0; 155393#L524 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 155932#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 155116#L1101 assume !(0 != activate_threads_~tmp___4~0#1); 155117#L1101-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 155072#L532 assume !(1 == ~t6_pc~0); 155073#L532-2 is_transmit6_triggered_~__retres1~6#1 := 0; 155221#L543 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 155409#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 155410#L1109 assume !(0 != activate_threads_~tmp___5~0#1); 155317#L1109-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 155318#L551 assume 1 == ~t7_pc~0; 155951#L552 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 155753#L562 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 155754#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 156123#L1117 assume !(0 != activate_threads_~tmp___6~0#1); 156129#L1117-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 155514#L570 assume 1 == ~t8_pc~0; 155515#L571 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 155640#L581 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 155870#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 155637#L1125 assume !(0 != activate_threads_~tmp___7~0#1); 155102#L1125-2 havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 155103#L952 assume !(1 == ~M_E~0); 155926#L952-2 assume !(1 == ~T1_E~0); 169115#L957-1 assume !(1 == ~T2_E~0); 169114#L962-1 assume !(1 == ~T3_E~0); 169113#L967-1 assume !(1 == ~T4_E~0); 169111#L972-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 169112#L977-1 assume !(1 == ~T6_E~0); 172269#L982-1 assume !(1 == ~T7_E~0); 172266#L987-1 assume 1 == ~T8_E~0;~T8_E~0 := 2; 155233#L992-1 assume !(1 == ~E_M~0); 155234#L997-1 assume !(1 == ~E_1~0); 156072#L1002-1 assume !(1 == ~E_2~0); 156073#L1007-1 assume !(1 == ~E_3~0); 154974#L1012-1 assume 1 == ~E_4~0;~E_4~0 := 2; 154975#L1017-1 assume !(1 == ~E_5~0); 172233#L1022-1 assume !(1 == ~E_6~0); 172232#L1027-1 assume 1 == ~E_7~0;~E_7~0 := 2; 172231#L1032-1 assume !(1 == ~E_8~0); 155784#L1037-1 assume { :end_inline_reset_delta_events } true; 155785#L1303-2 [2023-11-12 02:34:26,613 INFO L750 eck$LassoCheckResult]: Loop: 155785#L1303-2 assume !false; 174399#L1304 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 176040#L829-1 assume !false; 176038#L708 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 174347#L650 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 174343#L697 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 174324#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 174325#L712 assume !(0 != eval_~tmp~0#1); 175714#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 177806#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 177804#L854-3 assume !(0 == ~M_E~0); 177802#L854-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 177801#L859-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 177800#L864-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 177799#L869-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 177797#L874-3 assume !(0 == ~T5_E~0); 177795#L879-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 177793#L884-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 177791#L889-3 assume !(0 == ~T8_E~0); 177789#L894-3 assume 0 == ~E_M~0;~E_M~0 := 1; 177787#L899-3 assume 0 == ~E_1~0;~E_1~0 := 1; 177785#L904-3 assume 0 == ~E_2~0;~E_2~0 := 1; 177783#L909-3 assume 0 == ~E_3~0;~E_3~0 := 1; 177781#L914-3 assume !(0 == ~E_4~0); 177779#L919-3 assume 0 == ~E_5~0;~E_5~0 := 1; 177777#L924-3 assume 0 == ~E_6~0;~E_6~0 := 1; 177775#L929-3 assume !(0 == ~E_7~0); 177773#L934-3 assume 0 == ~E_8~0;~E_8~0 := 1; 177771#L939-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 177769#L418-30 assume !(1 == ~m_pc~0); 177767#L418-32 is_master_triggered_~__retres1~0#1 := 0; 177765#L429-10 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 177763#is_master_triggered_returnLabel#11 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 177761#L1061-30 assume !(0 != activate_threads_~tmp~1#1); 177759#L1061-32 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 177757#L437-30 assume !(1 == ~t1_pc~0); 177755#L437-32 is_transmit1_triggered_~__retres1~1#1 := 0; 177753#L448-10 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 177751#is_transmit1_triggered_returnLabel#11 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 177749#L1069-30 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 177747#L1069-32 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 177745#L456-30 assume 1 == ~t2_pc~0; 177744#L457-10 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 177741#L467-10 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 177739#is_transmit2_triggered_returnLabel#11 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 177737#L1077-30 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 177735#L1077-32 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 177733#L475-30 assume !(1 == ~t3_pc~0); 177730#L475-32 is_transmit3_triggered_~__retres1~3#1 := 0; 177728#L486-10 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 177726#is_transmit3_triggered_returnLabel#11 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 177724#L1085-30 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 177722#L1085-32 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 177720#L494-30 assume 1 == ~t4_pc~0; 177718#L495-10 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 177714#L505-10 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 177711#is_transmit4_triggered_returnLabel#11 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 177708#L1093-30 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 177705#L1093-32 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 177702#L513-30 assume !(1 == ~t5_pc~0); 177698#L513-32 is_transmit5_triggered_~__retres1~5#1 := 0; 177695#L524-10 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 177692#is_transmit5_triggered_returnLabel#11 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 177689#L1101-30 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 177686#L1101-32 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 177683#L532-30 assume 1 == ~t6_pc~0; 177680#L533-10 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 177676#L543-10 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 177672#is_transmit6_triggered_returnLabel#11 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 177669#L1109-30 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 177667#L1109-32 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 177665#L551-30 assume 1 == ~t7_pc~0; 177640#L552-10 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 177637#L562-10 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 177634#is_transmit7_triggered_returnLabel#11 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 177631#L1117-30 assume !(0 != activate_threads_~tmp___6~0#1); 177628#L1117-32 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 177624#L570-30 assume 1 == ~t8_pc~0; 177620#L571-10 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 177614#L581-10 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 177611#is_transmit8_triggered_returnLabel#11 activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 177608#L1125-30 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 177605#L1125-32 havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 177602#L952-3 assume 1 == ~M_E~0;~M_E~0 := 2; 169328#L952-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 177595#L957-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 177591#L962-3 assume !(1 == ~T3_E~0); 177587#L967-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 177583#L972-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 177578#L977-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 177574#L982-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 177569#L987-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 177565#L992-3 assume 1 == ~E_M~0;~E_M~0 := 2; 177561#L997-3 assume 1 == ~E_1~0;~E_1~0 := 2; 177556#L1002-3 assume !(1 == ~E_2~0); 177551#L1007-3 assume 1 == ~E_3~0;~E_3~0 := 2; 177547#L1012-3 assume 1 == ~E_4~0;~E_4~0 := 2; 172354#L1017-3 assume 1 == ~E_5~0;~E_5~0 := 2; 177538#L1022-3 assume 1 == ~E_6~0;~E_6~0 := 2; 177534#L1027-3 assume 1 == ~E_7~0;~E_7~0 := 2; 177530#L1032-3 assume 1 == ~E_8~0;~E_8~0 := 2; 177528#L1037-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 177468#L650-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 177454#L697-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 177448#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret25#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret25#1;havoc start_simulation_#t~ret25#1; 177443#L1322 assume !(0 == start_simulation_~tmp~3#1); 177440#L1322-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret24#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 177386#L650-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 174547#L697-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 174548#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret24#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret24#1;havoc stop_simulation_#t~ret24#1; 174539#L1277 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 174540#L1284 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 174424#stop_simulation_returnLabel#1 start_simulation_#t~ret26#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret24#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret26#1;havoc start_simulation_#t~ret26#1; 174425#L1335 assume !(0 != start_simulation_~tmp___0~1#1); 155785#L1303-2 [2023-11-12 02:34:26,613 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-12 02:34:26,614 INFO L85 PathProgramCache]: Analyzing trace with hash 818659143, now seen corresponding path program 1 times [2023-11-12 02:34:26,614 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-12 02:34:26,614 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1465280684] [2023-11-12 02:34:26,614 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-12 02:34:26,615 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-12 02:34:26,633 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-12 02:34:26,702 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-12 02:34:26,702 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-12 02:34:26,703 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1465280684] [2023-11-12 02:34:26,703 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1465280684] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-12 02:34:26,703 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-12 02:34:26,703 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-12 02:34:26,703 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [998746354] [2023-11-12 02:34:26,704 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-12 02:34:26,704 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-12 02:34:26,704 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-12 02:34:26,705 INFO L85 PathProgramCache]: Analyzing trace with hash 2115288101, now seen corresponding path program 1 times [2023-11-12 02:34:26,705 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-12 02:34:26,705 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1134490057] [2023-11-12 02:34:26,705 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-12 02:34:26,705 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-12 02:34:26,720 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-12 02:34:26,861 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-12 02:34:26,861 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-12 02:34:26,862 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1134490057] [2023-11-12 02:34:26,862 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1134490057] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-12 02:34:26,862 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-12 02:34:26,862 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-12 02:34:26,862 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [597452210] [2023-11-12 02:34:26,862 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-12 02:34:26,863 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-12 02:34:26,863 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-12 02:34:26,863 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2023-11-12 02:34:26,863 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2023-11-12 02:34:26,863 INFO L87 Difference]: Start difference. First operand 46568 states and 66073 transitions. cyclomatic complexity: 19537 Second operand has 4 states, 4 states have (on average 26.5) internal successors, (106), 3 states have internal predecessors, (106), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-12 02:34:27,811 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-12 02:34:27,811 INFO L93 Difference]: Finished difference Result 129005 states and 181692 transitions. [2023-11-12 02:34:27,811 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 129005 states and 181692 transitions. [2023-11-12 02:34:28,894 INFO L131 ngComponentsAnalysis]: Automaton has 64 accepting balls. 125931 [2023-11-12 02:34:29,555 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 129005 states to 129005 states and 181692 transitions. [2023-11-12 02:34:29,556 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 129005 [2023-11-12 02:34:29,664 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 129005 [2023-11-12 02:34:29,664 INFO L73 IsDeterministic]: Start isDeterministic. Operand 129005 states and 181692 transitions. [2023-11-12 02:34:29,757 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-12 02:34:29,757 INFO L218 hiAutomatonCegarLoop]: Abstraction has 129005 states and 181692 transitions. [2023-11-12 02:34:29,869 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 129005 states and 181692 transitions. [2023-11-12 02:34:31,915 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 129005 to 125493. [2023-11-12 02:34:32,117 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 125493 states, 125493 states have (on average 1.4117440813431825) internal successors, (177164), 125492 states have internal predecessors, (177164), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-12 02:34:32,492 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 125493 states to 125493 states and 177164 transitions. [2023-11-12 02:34:32,492 INFO L240 hiAutomatonCegarLoop]: Abstraction has 125493 states and 177164 transitions. [2023-11-12 02:34:32,493 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2023-11-12 02:34:32,493 INFO L428 stractBuchiCegarLoop]: Abstraction has 125493 states and 177164 transitions. [2023-11-12 02:34:32,493 INFO L335 stractBuchiCegarLoop]: ======== Iteration 16 ============ [2023-11-12 02:34:32,494 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 125493 states and 177164 transitions. [2023-11-12 02:34:33,426 INFO L131 ngComponentsAnalysis]: Automaton has 64 accepting balls. 124851 [2023-11-12 02:34:33,426 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-12 02:34:33,426 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-12 02:34:33,429 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-12 02:34:33,429 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-12 02:34:33,431 INFO L748 eck$LassoCheckResult]: Stem: 330868#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~token~0 := 0;~local~0 := 0; 330869#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~10#1;havoc main_~__retres1~10#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; 331638#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret25#1, start_simulation_#t~ret26#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 331639#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 331725#L597 assume 1 == ~m_i~0;~m_st~0 := 0; 331332#L597-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 331333#L602-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 330892#L607-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 330893#L612-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 330817#L617-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 330818#L622-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 331095#L627-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 331066#L632-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 331067#L637-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 331400#L854 assume !(0 == ~M_E~0); 331172#L854-2 assume !(0 == ~T1_E~0); 331173#L859-1 assume !(0 == ~T2_E~0); 330694#L864-1 assume !(0 == ~T3_E~0); 330695#L869-1 assume !(0 == ~T4_E~0); 330805#L874-1 assume !(0 == ~T5_E~0); 331689#L879-1 assume !(0 == ~T6_E~0); 331158#L884-1 assume !(0 == ~T7_E~0); 330555#L889-1 assume !(0 == ~T8_E~0); 330556#L894-1 assume !(0 == ~E_M~0); 330904#L899-1 assume !(0 == ~E_1~0); 331407#L904-1 assume !(0 == ~E_2~0); 331089#L909-1 assume !(0 == ~E_3~0); 331090#L914-1 assume !(0 == ~E_4~0); 331320#L919-1 assume !(0 == ~E_5~0); 330983#L924-1 assume !(0 == ~E_6~0); 330791#L929-1 assume !(0 == ~E_7~0); 330792#L934-1 assume !(0 == ~E_8~0); 331065#L939-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 330573#L418 assume !(1 == ~m_pc~0); 330574#L418-2 is_master_triggered_~__retres1~0#1 := 0; 331623#L429 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 331555#is_master_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 331539#L1061 assume !(0 != activate_threads_~tmp~1#1); 331437#L1061-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 331438#L437 assume !(1 == ~t1_pc~0); 331674#L437-2 is_transmit1_triggered_~__retres1~1#1 := 0; 331546#L448 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 330599#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 330600#L1069 assume !(0 != activate_threads_~tmp___0~0#1); 330931#L1069-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 331530#L456 assume !(1 == ~t2_pc~0); 330848#L456-2 is_transmit2_triggered_~__retres1~2#1 := 0; 330847#L467 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 331018#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 331019#L1077 assume !(0 != activate_threads_~tmp___1~0#1); 331207#L1077-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 330689#L475 assume !(1 == ~t3_pc~0); 330690#L475-2 is_transmit3_triggered_~__retres1~3#1 := 0; 330754#L486 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 330564#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 330565#L1085 assume !(0 != activate_threads_~tmp___2~0#1); 330934#L1085-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 330935#L494 assume !(1 == ~t4_pc~0); 330978#L494-2 is_transmit4_triggered_~__retres1~4#1 := 0; 330979#L505 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 330704#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 330705#L1093 assume !(0 != activate_threads_~tmp___3~0#1); 331349#L1093-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 330750#L513 assume !(1 == ~t5_pc~0); 330751#L513-2 is_transmit5_triggered_~__retres1~5#1 := 0; 330982#L524 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 331557#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 330701#L1101 assume !(0 != activate_threads_~tmp___4~0#1); 330702#L1101-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 330655#L532 assume !(1 == ~t6_pc~0); 330656#L532-2 is_transmit6_triggered_~__retres1~6#1 := 0; 330806#L543 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 331000#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 331001#L1109 assume !(0 != activate_threads_~tmp___5~0#1); 330906#L1109-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 330907#L551 assume !(1 == ~t7_pc~0); 331408#L551-2 is_transmit7_triggered_~__retres1~7#1 := 0; 331351#L562 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 331352#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 331747#L1117 assume !(0 != activate_threads_~tmp___6~0#1); 331752#L1117-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 331110#L570 assume 1 == ~t8_pc~0; 331111#L571 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 331237#L581 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 331491#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 331234#L1125 assume !(0 != activate_threads_~tmp___7~0#1); 330687#L1125-2 havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 330688#L952 assume !(1 == ~M_E~0); 331551#L952-2 assume !(1 == ~T1_E~0); 331503#L957-1 assume !(1 == ~T2_E~0); 331504#L962-1 assume !(1 == ~T3_E~0); 331253#L967-1 assume !(1 == ~T4_E~0); 331254#L972-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 346306#L977-1 assume !(1 == ~T6_E~0); 331757#L982-1 assume !(1 == ~T7_E~0); 331758#L987-1 assume 1 == ~T8_E~0;~T8_E~0 := 2; 330819#L992-1 assume !(1 == ~E_M~0); 330820#L997-1 assume !(1 == ~E_1~0); 331693#L1002-1 assume !(1 == ~E_2~0); 331694#L1007-1 assume !(1 == ~E_3~0); 330557#L1012-1 assume 1 == ~E_4~0;~E_4~0 := 2; 330558#L1017-1 assume !(1 == ~E_5~0); 331472#L1022-1 assume !(1 == ~E_6~0); 331221#L1027-1 assume 1 == ~E_7~0;~E_7~0 := 2; 331222#L1032-1 assume !(1 == ~E_8~0); 331384#L1037-1 assume { :end_inline_reset_delta_events } true; 331385#L1303-2 [2023-11-12 02:34:33,431 INFO L750 eck$LassoCheckResult]: Loop: 331385#L1303-2 assume !false; 423848#L1304 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 423845#L829-1 assume !false; 348590#L708 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 338658#L650 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 338649#L697 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 338638#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 338639#L712 assume !(0 != eval_~tmp~0#1); 349557#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 349553#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 349551#L854-3 assume !(0 == ~M_E~0); 349548#L854-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 349546#L859-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 349544#L864-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 349542#L869-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 349540#L874-3 assume !(0 == ~T5_E~0); 349538#L879-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 349536#L884-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 349534#L889-3 assume !(0 == ~T8_E~0); 349532#L894-3 assume 0 == ~E_M~0;~E_M~0 := 1; 349530#L899-3 assume 0 == ~E_1~0;~E_1~0 := 1; 349528#L904-3 assume 0 == ~E_2~0;~E_2~0 := 1; 349526#L909-3 assume 0 == ~E_3~0;~E_3~0 := 1; 349523#L914-3 assume !(0 == ~E_4~0); 349521#L919-3 assume 0 == ~E_5~0;~E_5~0 := 1; 349518#L924-3 assume 0 == ~E_6~0;~E_6~0 := 1; 349516#L929-3 assume !(0 == ~E_7~0); 349514#L934-3 assume 0 == ~E_8~0;~E_8~0 := 1; 349513#L939-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 349509#L418-30 assume !(1 == ~m_pc~0); 349507#L418-32 is_master_triggered_~__retres1~0#1 := 0; 349505#L429-10 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 349504#is_master_triggered_returnLabel#11 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 349503#L1061-30 assume !(0 != activate_threads_~tmp~1#1); 349501#L1061-32 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 349451#L437-30 assume !(1 == ~t1_pc~0); 349434#L437-32 is_transmit1_triggered_~__retres1~1#1 := 0; 349428#L448-10 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 349373#is_transmit1_triggered_returnLabel#11 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 349360#L1069-30 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 349356#L1069-32 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 349352#L456-30 assume 1 == ~t2_pc~0; 349345#L457-10 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 349340#L467-10 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 349336#is_transmit2_triggered_returnLabel#11 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 349332#L1077-30 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 349328#L1077-32 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 349324#L475-30 assume !(1 == ~t3_pc~0); 349318#L475-32 is_transmit3_triggered_~__retres1~3#1 := 0; 349314#L486-10 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 349310#is_transmit3_triggered_returnLabel#11 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 349305#L1085-30 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 349300#L1085-32 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 349295#L494-30 assume 1 == ~t4_pc~0; 349289#L495-10 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 349283#L505-10 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 349279#is_transmit4_triggered_returnLabel#11 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 349275#L1093-30 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 349271#L1093-32 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 349267#L513-30 assume !(1 == ~t5_pc~0); 349261#L513-32 is_transmit5_triggered_~__retres1~5#1 := 0; 349256#L524-10 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 349251#is_transmit5_triggered_returnLabel#11 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 349246#L1101-30 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 349241#L1101-32 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 349236#L532-30 assume !(1 == ~t6_pc~0); 349229#L532-32 is_transmit6_triggered_~__retres1~6#1 := 0; 349230#L543-10 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 429412#is_transmit6_triggered_returnLabel#11 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 429408#L1109-30 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 429406#L1109-32 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 429404#L551-30 assume !(1 == ~t7_pc~0); 429402#L551-32 is_transmit7_triggered_~__retres1~7#1 := 0; 429399#L562-10 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 429397#is_transmit7_triggered_returnLabel#11 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 429396#L1117-30 assume !(0 != activate_threads_~tmp___6~0#1); 429392#L1117-32 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 429390#L570-30 assume !(1 == ~t8_pc~0); 429388#L570-32 is_transmit8_triggered_~__retres1~8#1 := 0; 429385#L581-10 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 349147#is_transmit8_triggered_returnLabel#11 activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 349140#L1125-30 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 349141#L1125-32 havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 423978#L952-3 assume 1 == ~M_E~0;~M_E~0 := 2; 421197#L952-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 423977#L957-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 423976#L962-3 assume !(1 == ~T3_E~0); 423974#L967-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 423973#L972-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 423971#L977-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 423970#L982-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 423969#L987-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 423967#L992-3 assume 1 == ~E_M~0;~E_M~0 := 2; 423965#L997-3 assume 1 == ~E_1~0;~E_1~0 := 2; 423963#L1002-3 assume !(1 == ~E_2~0); 423961#L1007-3 assume 1 == ~E_3~0;~E_3~0 := 2; 423933#L1012-3 assume 1 == ~E_4~0;~E_4~0 := 2; 423932#L1017-3 assume 1 == ~E_5~0;~E_5~0 := 2; 423931#L1022-3 assume 1 == ~E_6~0;~E_6~0 := 2; 423930#L1027-3 assume 1 == ~E_7~0;~E_7~0 := 2; 423929#L1032-3 assume 1 == ~E_8~0;~E_8~0 := 2; 423928#L1037-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 423877#L650-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 423868#L697-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 423867#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret25#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret25#1;havoc start_simulation_#t~ret25#1; 423866#L1322 assume !(0 == start_simulation_~tmp~3#1); 423864#L1322-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret24#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 423859#L650-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 423854#L697-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 423853#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret24#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret24#1;havoc stop_simulation_#t~ret24#1; 423852#L1277 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 423851#L1284 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 423850#stop_simulation_returnLabel#1 start_simulation_#t~ret26#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret24#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret26#1;havoc start_simulation_#t~ret26#1; 423849#L1335 assume !(0 != start_simulation_~tmp___0~1#1); 331385#L1303-2 [2023-11-12 02:34:33,432 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-12 02:34:33,432 INFO L85 PathProgramCache]: Analyzing trace with hash -952811832, now seen corresponding path program 1 times [2023-11-12 02:34:33,432 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-12 02:34:33,432 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1756702355] [2023-11-12 02:34:33,432 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-12 02:34:33,433 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-12 02:34:33,450 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-12 02:34:33,510 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-12 02:34:33,511 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-12 02:34:33,511 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1756702355] [2023-11-12 02:34:33,511 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1756702355] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-12 02:34:33,511 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-12 02:34:33,512 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2023-11-12 02:34:33,512 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1896453512] [2023-11-12 02:34:33,512 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-12 02:34:33,512 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-12 02:34:33,513 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-12 02:34:33,513 INFO L85 PathProgramCache]: Analyzing trace with hash -1982652888, now seen corresponding path program 1 times [2023-11-12 02:34:33,513 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-12 02:34:33,514 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1533607535] [2023-11-12 02:34:33,514 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-12 02:34:33,514 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-12 02:34:33,530 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-12 02:34:33,575 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-12 02:34:33,575 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-12 02:34:33,575 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1533607535] [2023-11-12 02:34:33,575 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1533607535] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-12 02:34:33,576 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-12 02:34:33,576 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-12 02:34:33,576 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [55855389] [2023-11-12 02:34:33,576 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-12 02:34:33,577 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-12 02:34:33,577 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-12 02:34:33,577 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-12 02:34:33,578 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-12 02:34:33,578 INFO L87 Difference]: Start difference. First operand 125493 states and 177164 transitions. cyclomatic complexity: 51735 Second operand has 3 states, 3 states have (on average 35.333333333333336) internal successors, (106), 2 states have internal predecessors, (106), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-12 02:34:35,025 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-12 02:34:35,025 INFO L93 Difference]: Finished difference Result 235813 states and 332018 transitions. [2023-11-12 02:34:35,026 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 235813 states and 332018 transitions. [2023-11-12 02:34:36,395 INFO L131 ngComponentsAnalysis]: Automaton has 128 accepting balls. 234244 [2023-11-12 02:34:37,234 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 235813 states to 235813 states and 332018 transitions. [2023-11-12 02:34:37,234 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 235813 [2023-11-12 02:34:37,354 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 235813 [2023-11-12 02:34:37,354 INFO L73 IsDeterministic]: Start isDeterministic. Operand 235813 states and 332018 transitions. [2023-11-12 02:34:37,521 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-12 02:34:37,521 INFO L218 hiAutomatonCegarLoop]: Abstraction has 235813 states and 332018 transitions. [2023-11-12 02:34:37,713 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 235813 states and 332018 transitions. [2023-11-12 02:34:40,252 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 235813 to 235381. [2023-11-12 02:34:40,455 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 235381 states, 235381 states have (on average 1.4087203300181408) internal successors, (331586), 235380 states have internal predecessors, (331586), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-12 02:34:41,958 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 235381 states to 235381 states and 331586 transitions. [2023-11-12 02:34:41,960 INFO L240 hiAutomatonCegarLoop]: Abstraction has 235381 states and 331586 transitions. [2023-11-12 02:34:41,960 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-12 02:34:41,962 INFO L428 stractBuchiCegarLoop]: Abstraction has 235381 states and 331586 transitions. [2023-11-12 02:34:41,975 INFO L335 stractBuchiCegarLoop]: ======== Iteration 17 ============ [2023-11-12 02:34:41,975 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 235381 states and 331586 transitions. [2023-11-12 02:34:42,486 INFO L131 ngComponentsAnalysis]: Automaton has 128 accepting balls. 233812 [2023-11-12 02:34:42,486 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-12 02:34:42,487 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-12 02:34:42,489 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-12 02:34:42,489 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-12 02:34:42,490 INFO L748 eck$LassoCheckResult]: Stem: 692185#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~token~0 := 0;~local~0 := 0; 692186#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~10#1;havoc main_~__retres1~10#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; 692983#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret25#1, start_simulation_#t~ret26#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 692984#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 693073#L597 assume 1 == ~m_i~0;~m_st~0 := 0; 692652#L597-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 692653#L602-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 692207#L607-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 692208#L612-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 692131#L617-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 692132#L622-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 692411#L627-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 692380#L632-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 692381#L637-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 692722#L854 assume !(0 == ~M_E~0); 692485#L854-2 assume !(0 == ~T1_E~0); 692486#L859-1 assume !(0 == ~T2_E~0); 692008#L864-1 assume !(0 == ~T3_E~0); 692009#L869-1 assume !(0 == ~T4_E~0); 692120#L874-1 assume !(0 == ~T5_E~0); 693041#L879-1 assume !(0 == ~T6_E~0); 692470#L884-1 assume !(0 == ~T7_E~0); 691868#L889-1 assume !(0 == ~T8_E~0); 691869#L894-1 assume !(0 == ~E_M~0); 692219#L899-1 assume !(0 == ~E_1~0); 692728#L904-1 assume !(0 == ~E_2~0); 692404#L909-1 assume !(0 == ~E_3~0); 692405#L914-1 assume !(0 == ~E_4~0); 692640#L919-1 assume !(0 == ~E_5~0); 692298#L924-1 assume !(0 == ~E_6~0); 692106#L929-1 assume !(0 == ~E_7~0); 692107#L934-1 assume !(0 == ~E_8~0); 692377#L939-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 691886#L418 assume !(1 == ~m_pc~0); 691887#L418-2 is_master_triggered_~__retres1~0#1 := 0; 692965#L429 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 692892#is_master_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 692877#L1061 assume !(0 != activate_threads_~tmp~1#1); 692762#L1061-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 692763#L437 assume !(1 == ~t1_pc~0); 693023#L437-2 is_transmit1_triggered_~__retres1~1#1 := 0; 692885#L448 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 691913#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 691914#L1069 assume !(0 != activate_threads_~tmp___0~0#1); 692245#L1069-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 692868#L456 assume !(1 == ~t2_pc~0); 692165#L456-2 is_transmit2_triggered_~__retres1~2#1 := 0; 692164#L467 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 692331#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 692332#L1077 assume !(0 != activate_threads_~tmp___1~0#1); 692521#L1077-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 692003#L475 assume !(1 == ~t3_pc~0); 692004#L475-2 is_transmit3_triggered_~__retres1~3#1 := 0; 692069#L486 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 691877#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 691878#L1085 assume !(0 != activate_threads_~tmp___2~0#1); 692248#L1085-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 692249#L494 assume !(1 == ~t4_pc~0); 692293#L494-2 is_transmit4_triggered_~__retres1~4#1 := 0; 692294#L505 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 692018#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 692019#L1093 assume !(0 != activate_threads_~tmp___3~0#1); 692668#L1093-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 692065#L513 assume !(1 == ~t5_pc~0); 692066#L513-2 is_transmit5_triggered_~__retres1~5#1 := 0; 692297#L524 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 692895#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 692015#L1101 assume !(0 != activate_threads_~tmp___4~0#1); 692016#L1101-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 691969#L532 assume !(1 == ~t6_pc~0); 691970#L532-2 is_transmit6_triggered_~__retres1~6#1 := 0; 692121#L543 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 692311#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 692312#L1109 assume !(0 != activate_threads_~tmp___5~0#1); 692221#L1109-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 692222#L551 assume !(1 == ~t7_pc~0); 692731#L551-2 is_transmit7_triggered_~__retres1~7#1 := 0; 692672#L562 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 692673#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 693108#L1117 assume !(0 != activate_threads_~tmp___6~0#1); 693114#L1117-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 692425#L570 assume !(1 == ~t8_pc~0); 692426#L570-2 is_transmit8_triggered_~__retres1~8#1 := 0; 692990#L581 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 692824#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 692552#L1125 assume !(0 != activate_threads_~tmp___7~0#1); 692001#L1125-2 havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 692002#L952 assume !(1 == ~M_E~0); 692889#L952-2 assume !(1 == ~T1_E~0); 692840#L957-1 assume !(1 == ~T2_E~0); 692841#L962-1 assume !(1 == ~T3_E~0); 692571#L967-1 assume !(1 == ~T4_E~0); 692572#L972-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 717352#L977-1 assume !(1 == ~T6_E~0); 693118#L982-1 assume !(1 == ~T7_E~0); 693119#L987-1 assume 1 == ~T8_E~0;~T8_E~0 := 2; 692133#L992-1 assume !(1 == ~E_M~0); 692134#L997-1 assume !(1 == ~E_1~0); 693042#L1002-1 assume !(1 == ~E_2~0); 693043#L1007-1 assume !(1 == ~E_3~0); 717343#L1012-1 assume 1 == ~E_4~0;~E_4~0 := 2; 717342#L1017-1 assume !(1 == ~E_5~0); 717341#L1022-1 assume !(1 == ~E_6~0); 717340#L1027-1 assume 1 == ~E_7~0;~E_7~0 := 2; 717339#L1032-1 assume !(1 == ~E_8~0); 717336#L1037-1 assume { :end_inline_reset_delta_events } true; 717337#L1303-2 [2023-11-12 02:34:42,491 INFO L750 eck$LassoCheckResult]: Loop: 717337#L1303-2 assume !false; 912631#L1304 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 912628#L829-1 assume !false; 912627#L708 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 912613#L650 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 912607#L697 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 912605#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 912602#L712 assume !(0 != eval_~tmp~0#1); 912603#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 912753#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 912752#L854-3 assume !(0 == ~M_E~0); 912751#L854-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 912750#L859-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 912749#L864-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 912748#L869-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 912747#L874-3 assume !(0 == ~T5_E~0); 912746#L879-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 912745#L884-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 912744#L889-3 assume !(0 == ~T8_E~0); 912743#L894-3 assume 0 == ~E_M~0;~E_M~0 := 1; 912742#L899-3 assume 0 == ~E_1~0;~E_1~0 := 1; 912741#L904-3 assume 0 == ~E_2~0;~E_2~0 := 1; 912740#L909-3 assume 0 == ~E_3~0;~E_3~0 := 1; 912739#L914-3 assume !(0 == ~E_4~0); 912738#L919-3 assume 0 == ~E_5~0;~E_5~0 := 1; 912737#L924-3 assume 0 == ~E_6~0;~E_6~0 := 1; 912736#L929-3 assume !(0 == ~E_7~0); 912735#L934-3 assume 0 == ~E_8~0;~E_8~0 := 1; 912734#L939-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 912733#L418-30 assume !(1 == ~m_pc~0); 912732#L418-32 is_master_triggered_~__retres1~0#1 := 0; 912731#L429-10 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 912730#is_master_triggered_returnLabel#11 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 912729#L1061-30 assume !(0 != activate_threads_~tmp~1#1); 912728#L1061-32 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 912727#L437-30 assume !(1 == ~t1_pc~0); 912726#L437-32 is_transmit1_triggered_~__retres1~1#1 := 0; 912725#L448-10 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 912724#is_transmit1_triggered_returnLabel#11 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 912723#L1069-30 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 912722#L1069-32 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 912721#L456-30 assume !(1 == ~t2_pc~0); 912719#L456-32 is_transmit2_triggered_~__retres1~2#1 := 0; 912718#L467-10 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 912717#is_transmit2_triggered_returnLabel#11 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 912716#L1077-30 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 912715#L1077-32 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 912714#L475-30 assume !(1 == ~t3_pc~0); 912713#L475-32 is_transmit3_triggered_~__retres1~3#1 := 0; 912712#L486-10 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 912711#is_transmit3_triggered_returnLabel#11 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 912710#L1085-30 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 912709#L1085-32 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 912708#L494-30 assume 1 == ~t4_pc~0; 912707#L495-10 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 912705#L505-10 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 912704#is_transmit4_triggered_returnLabel#11 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 912703#L1093-30 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 912702#L1093-32 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 912701#L513-30 assume !(1 == ~t5_pc~0); 912700#L513-32 is_transmit5_triggered_~__retres1~5#1 := 0; 912699#L524-10 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 912698#is_transmit5_triggered_returnLabel#11 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 912697#L1101-30 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 912696#L1101-32 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 912695#L532-30 assume !(1 == ~t6_pc~0); 912693#L532-32 is_transmit6_triggered_~__retres1~6#1 := 0; 912692#L543-10 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 912691#is_transmit6_triggered_returnLabel#11 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 912690#L1109-30 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 912689#L1109-32 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 912688#L551-30 assume !(1 == ~t7_pc~0); 912687#L551-32 is_transmit7_triggered_~__retres1~7#1 := 0; 912686#L562-10 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 912685#is_transmit7_triggered_returnLabel#11 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 912684#L1117-30 assume !(0 != activate_threads_~tmp___6~0#1); 912683#L1117-32 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 912682#L570-30 assume !(1 == ~t8_pc~0); 912681#L570-32 is_transmit8_triggered_~__retres1~8#1 := 0; 912680#L581-10 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 912679#is_transmit8_triggered_returnLabel#11 activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 912678#L1125-30 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 912677#L1125-32 havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 912676#L952-3 assume 1 == ~M_E~0;~M_E~0 := 2; 834044#L952-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 912675#L957-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 912674#L962-3 assume !(1 == ~T3_E~0); 912673#L967-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 912672#L972-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 846834#L977-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 912671#L982-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 912670#L987-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 912669#L992-3 assume 1 == ~E_M~0;~E_M~0 := 2; 912668#L997-3 assume 1 == ~E_1~0;~E_1~0 := 2; 912667#L1002-3 assume !(1 == ~E_2~0); 912666#L1007-3 assume 1 == ~E_3~0;~E_3~0 := 2; 912665#L1012-3 assume 1 == ~E_4~0;~E_4~0 := 2; 834024#L1017-3 assume 1 == ~E_5~0;~E_5~0 := 2; 912664#L1022-3 assume 1 == ~E_6~0;~E_6~0 := 2; 912663#L1027-3 assume 1 == ~E_7~0;~E_7~0 := 2; 912662#L1032-3 assume 1 == ~E_8~0;~E_8~0 := 2; 912661#L1037-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 912660#L650-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 912651#L697-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 912650#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret25#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret25#1;havoc start_simulation_#t~ret25#1; 912649#L1322 assume !(0 == start_simulation_~tmp~3#1); 912647#L1322-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret24#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 912642#L650-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 912637#L697-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 912636#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret24#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret24#1;havoc stop_simulation_#t~ret24#1; 912635#L1277 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 912634#L1284 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 912633#stop_simulation_returnLabel#1 start_simulation_#t~ret26#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret24#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret26#1;havoc start_simulation_#t~ret26#1; 912632#L1335 assume !(0 != start_simulation_~tmp___0~1#1); 717337#L1303-2 [2023-11-12 02:34:42,491 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-12 02:34:42,492 INFO L85 PathProgramCache]: Analyzing trace with hash 1284551433, now seen corresponding path program 1 times [2023-11-12 02:34:42,492 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-12 02:34:42,492 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [419770850] [2023-11-12 02:34:42,492 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-12 02:34:42,493 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-12 02:34:42,512 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-12 02:34:42,580 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-12 02:34:42,580 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-12 02:34:42,581 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [419770850] [2023-11-12 02:34:42,581 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [419770850] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-12 02:34:42,581 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-12 02:34:42,581 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-12 02:34:42,581 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1135506876] [2023-11-12 02:34:42,582 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-12 02:34:42,582 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-12 02:34:42,582 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-12 02:34:42,582 INFO L85 PathProgramCache]: Analyzing trace with hash 149335145, now seen corresponding path program 1 times [2023-11-12 02:34:42,583 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-12 02:34:42,583 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [918285212] [2023-11-12 02:34:42,583 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-12 02:34:42,583 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-12 02:34:42,596 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-12 02:34:42,627 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-12 02:34:42,627 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-12 02:34:42,628 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [918285212] [2023-11-12 02:34:42,628 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [918285212] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-12 02:34:42,628 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-12 02:34:42,628 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-12 02:34:42,628 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2137685005] [2023-11-12 02:34:42,628 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-12 02:34:42,629 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-12 02:34:42,629 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-12 02:34:42,629 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2023-11-12 02:34:42,630 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2023-11-12 02:34:42,630 INFO L87 Difference]: Start difference. First operand 235381 states and 331586 transitions. cyclomatic complexity: 96333 Second operand has 4 states, 4 states have (on average 26.5) internal successors, (106), 3 states have internal predecessors, (106), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-12 02:34:44,010 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-12 02:34:44,010 INFO L93 Difference]: Finished difference Result 179848 states and 252738 transitions. [2023-11-12 02:34:44,010 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 179848 states and 252738 transitions. [2023-11-12 02:34:44,740 INFO L131 ngComponentsAnalysis]: Automaton has 96 accepting balls. 178666 [2023-11-12 02:34:46,083 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 179848 states to 179848 states and 252738 transitions. [2023-11-12 02:34:46,083 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 179848 [2023-11-12 02:34:46,227 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 179848 [2023-11-12 02:34:46,236 INFO L73 IsDeterministic]: Start isDeterministic. Operand 179848 states and 252738 transitions. [2023-11-12 02:34:46,320 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-12 02:34:46,320 INFO L218 hiAutomatonCegarLoop]: Abstraction has 179848 states and 252738 transitions. [2023-11-12 02:34:46,419 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 179848 states and 252738 transitions. [2023-11-12 02:34:48,043 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 179848 to 124341. [2023-11-12 02:34:48,109 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 124341 states, 124341 states have (on average 1.4058677346973243) internal successors, (174807), 124340 states have internal predecessors, (174807), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-12 02:34:48,383 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 124341 states to 124341 states and 174807 transitions. [2023-11-12 02:34:48,384 INFO L240 hiAutomatonCegarLoop]: Abstraction has 124341 states and 174807 transitions. [2023-11-12 02:34:48,384 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2023-11-12 02:34:48,385 INFO L428 stractBuchiCegarLoop]: Abstraction has 124341 states and 174807 transitions. [2023-11-12 02:34:48,385 INFO L335 stractBuchiCegarLoop]: ======== Iteration 18 ============ [2023-11-12 02:34:48,385 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 124341 states and 174807 transitions. [2023-11-12 02:34:48,673 INFO L131 ngComponentsAnalysis]: Automaton has 64 accepting balls. 123520 [2023-11-12 02:34:48,673 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-12 02:34:48,673 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-12 02:34:48,675 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-12 02:34:48,676 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-12 02:34:48,676 INFO L748 eck$LassoCheckResult]: Stem: 1107416#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~token~0 := 0;~local~0 := 0; 1107417#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~10#1;havoc main_~__retres1~10#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; 1108180#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret25#1, start_simulation_#t~ret26#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 1108181#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 1108266#L597 assume 1 == ~m_i~0;~m_st~0 := 0; 1107874#L597-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 1107875#L602-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 1107438#L607-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 1107439#L612-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 1107366#L617-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 1107367#L622-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 1107648#L627-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 1107617#L632-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 1107618#L637-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 1107941#L854 assume !(0 == ~M_E~0); 1107718#L854-2 assume !(0 == ~T1_E~0); 1107719#L859-1 assume !(0 == ~T2_E~0); 1107244#L864-1 assume !(0 == ~T3_E~0); 1107245#L869-1 assume !(0 == ~T4_E~0); 1107355#L874-1 assume !(0 == ~T5_E~0); 1108237#L879-1 assume !(0 == ~T6_E~0); 1107705#L884-1 assume !(0 == ~T7_E~0); 1107107#L889-1 assume !(0 == ~T8_E~0); 1107108#L894-1 assume !(0 == ~E_M~0); 1107451#L899-1 assume !(0 == ~E_1~0); 1107947#L904-1 assume !(0 == ~E_2~0); 1107641#L909-1 assume !(0 == ~E_3~0); 1107642#L914-1 assume !(0 == ~E_4~0); 1107862#L919-1 assume !(0 == ~E_5~0); 1107537#L924-1 assume !(0 == ~E_6~0); 1107341#L929-1 assume !(0 == ~E_7~0); 1107342#L934-1 assume !(0 == ~E_8~0); 1107616#L939-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1107124#L418 assume !(1 == ~m_pc~0); 1107125#L418-2 is_master_triggered_~__retres1~0#1 := 0; 1108161#L429 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1108093#is_master_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 1108074#L1061 assume !(0 != activate_threads_~tmp~1#1); 1107975#L1061-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1107976#L437 assume !(1 == ~t1_pc~0); 1108222#L437-2 is_transmit1_triggered_~__retres1~1#1 := 0; 1108083#L448 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1107150#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 1107151#L1069 assume !(0 != activate_threads_~tmp___0~0#1); 1107482#L1069-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1108064#L456 assume !(1 == ~t2_pc~0); 1107397#L456-2 is_transmit2_triggered_~__retres1~2#1 := 0; 1107396#L467 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1107571#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 1107572#L1077 assume !(0 != activate_threads_~tmp___1~0#1); 1107751#L1077-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1107239#L475 assume !(1 == ~t3_pc~0); 1107240#L475-2 is_transmit3_triggered_~__retres1~3#1 := 0; 1107304#L486 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1107115#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1107116#L1085 assume !(0 != activate_threads_~tmp___2~0#1); 1107485#L1085-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1107486#L494 assume !(1 == ~t4_pc~0); 1107532#L494-2 is_transmit4_triggered_~__retres1~4#1 := 0; 1107533#L505 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1107254#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1107255#L1093 assume !(0 != activate_threads_~tmp___3~0#1); 1107890#L1093-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1107300#L513 assume !(1 == ~t5_pc~0); 1107301#L513-2 is_transmit5_triggered_~__retres1~5#1 := 0; 1107536#L524 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1108095#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1107251#L1101 assume !(0 != activate_threads_~tmp___4~0#1); 1107252#L1101-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1107205#L532 assume !(1 == ~t6_pc~0); 1107206#L532-2 is_transmit6_triggered_~__retres1~6#1 := 0; 1107356#L543 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1107552#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1107553#L1109 assume !(0 != activate_threads_~tmp___5~0#1); 1107456#L1109-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1107457#L551 assume !(1 == ~t7_pc~0); 1107948#L551-2 is_transmit7_triggered_~__retres1~7#1 := 0; 1107893#L562 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1107894#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 1108290#L1117 assume !(0 != activate_threads_~tmp___6~0#1); 1108293#L1117-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 1107662#L570 assume !(1 == ~t8_pc~0); 1107663#L570-2 is_transmit8_triggered_~__retres1~8#1 := 0; 1108184#L581 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 1108024#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 1107777#L1125 assume !(0 != activate_threads_~tmp___7~0#1); 1107237#L1125-2 havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1107238#L952 assume !(1 == ~M_E~0); 1107172#L952-2 assume !(1 == ~T1_E~0); 1107173#L957-1 assume !(1 == ~T2_E~0); 1108040#L962-1 assume !(1 == ~T3_E~0); 1107795#L967-1 assume !(1 == ~T4_E~0); 1107796#L972-1 assume !(1 == ~T5_E~0); 1108113#L977-1 assume !(1 == ~T6_E~0); 1108114#L982-1 assume !(1 == ~T7_E~0); 1107358#L987-1 assume 1 == ~T8_E~0;~T8_E~0 := 2; 1107359#L992-1 assume !(1 == ~E_M~0); 1107368#L997-1 assume !(1 == ~E_1~0); 1107749#L1002-1 assume !(1 == ~E_2~0); 1107733#L1007-1 assume !(1 == ~E_3~0); 1107109#L1012-1 assume !(1 == ~E_4~0); 1107110#L1017-1 assume !(1 == ~E_5~0); 1107739#L1022-1 assume !(1 == ~E_6~0); 1107740#L1027-1 assume 1 == ~E_7~0;~E_7~0 := 2; 1107764#L1032-1 assume !(1 == ~E_8~0); 1107925#L1037-1 assume { :end_inline_reset_delta_events } true; 1107926#L1303-2 [2023-11-12 02:34:48,677 INFO L750 eck$LassoCheckResult]: Loop: 1107926#L1303-2 assume !false; 1156841#L1304 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 1156838#L829-1 assume !false; 1156837#L708 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 1149252#L650 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 1149244#L697 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 1149240#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 1149236#L712 assume !(0 != eval_~tmp~0#1); 1126681#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 1126679#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 1126677#L854-3 assume !(0 == ~M_E~0); 1126675#L854-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 1126672#L859-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 1126638#L864-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 1126632#L869-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 1126624#L874-3 assume !(0 == ~T5_E~0); 1126617#L879-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 1126609#L884-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 1126598#L889-3 assume !(0 == ~T8_E~0); 1126599#L894-3 assume 0 == ~E_M~0;~E_M~0 := 1; 1214368#L899-3 assume 0 == ~E_1~0;~E_1~0 := 1; 1214366#L904-3 assume 0 == ~E_2~0;~E_2~0 := 1; 1214364#L909-3 assume 0 == ~E_3~0;~E_3~0 := 1; 1214362#L914-3 assume !(0 == ~E_4~0); 1214360#L919-3 assume 0 == ~E_5~0;~E_5~0 := 1; 1214359#L924-3 assume 0 == ~E_6~0;~E_6~0 := 1; 1214357#L929-3 assume !(0 == ~E_7~0); 1214355#L934-3 assume 0 == ~E_8~0;~E_8~0 := 1; 1214353#L939-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1214351#L418-30 assume !(1 == ~m_pc~0); 1214349#L418-32 is_master_triggered_~__retres1~0#1 := 0; 1214346#L429-10 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1214344#is_master_triggered_returnLabel#11 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 1214342#L1061-30 assume !(0 != activate_threads_~tmp~1#1); 1214340#L1061-32 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1214338#L437-30 assume !(1 == ~t1_pc~0); 1214336#L437-32 is_transmit1_triggered_~__retres1~1#1 := 0; 1214334#L448-10 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1214332#is_transmit1_triggered_returnLabel#11 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 1214330#L1069-30 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 1214328#L1069-32 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1214326#L456-30 assume !(1 == ~t2_pc~0); 1214323#L456-32 is_transmit2_triggered_~__retres1~2#1 := 0; 1214320#L467-10 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1214318#is_transmit2_triggered_returnLabel#11 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 1214316#L1077-30 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 1214314#L1077-32 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1214312#L475-30 assume !(1 == ~t3_pc~0); 1214310#L475-32 is_transmit3_triggered_~__retres1~3#1 := 0; 1214309#L486-10 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1214307#is_transmit3_triggered_returnLabel#11 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1214305#L1085-30 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 1214303#L1085-32 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1214301#L494-30 assume !(1 == ~t4_pc~0); 1214298#L494-32 is_transmit4_triggered_~__retres1~4#1 := 0; 1214296#L505-10 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1214294#is_transmit4_triggered_returnLabel#11 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1214292#L1093-30 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 1214290#L1093-32 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1214288#L513-30 assume !(1 == ~t5_pc~0); 1214286#L513-32 is_transmit5_triggered_~__retres1~5#1 := 0; 1214284#L524-10 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1214282#is_transmit5_triggered_returnLabel#11 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1214280#L1101-30 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 1214278#L1101-32 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1214276#L532-30 assume 1 == ~t6_pc~0; 1214274#L533-10 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 1214271#L543-10 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1214269#is_transmit6_triggered_returnLabel#11 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1214267#L1109-30 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 1214265#L1109-32 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1214263#L551-30 assume !(1 == ~t7_pc~0); 1214261#L551-32 is_transmit7_triggered_~__retres1~7#1 := 0; 1214259#L562-10 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1214257#is_transmit7_triggered_returnLabel#11 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 1214255#L1117-30 assume !(0 != activate_threads_~tmp___6~0#1); 1214253#L1117-32 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 1214251#L570-30 assume !(1 == ~t8_pc~0); 1214249#L570-32 is_transmit8_triggered_~__retres1~8#1 := 0; 1214248#L581-10 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 1214247#is_transmit8_triggered_returnLabel#11 activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 1214237#L1125-30 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 1214236#L1125-32 havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1214235#L952-3 assume !(1 == ~M_E~0); 1170227#L952-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 1167569#L957-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 1167566#L962-3 assume !(1 == ~T3_E~0); 1167564#L967-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 1167562#L972-3 assume !(1 == ~T5_E~0); 1167560#L977-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 1167558#L982-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 1167556#L987-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 1167554#L992-3 assume 1 == ~E_M~0;~E_M~0 := 2; 1167553#L997-3 assume 1 == ~E_1~0;~E_1~0 := 2; 1167543#L1002-3 assume !(1 == ~E_2~0); 1167541#L1007-3 assume 1 == ~E_3~0;~E_3~0 := 2; 1167539#L1012-3 assume 1 == ~E_4~0;~E_4~0 := 2; 1167537#L1017-3 assume 1 == ~E_5~0;~E_5~0 := 2; 1167535#L1022-3 assume 1 == ~E_6~0;~E_6~0 := 2; 1167533#L1027-3 assume 1 == ~E_7~0;~E_7~0 := 2; 1167531#L1032-3 assume 1 == ~E_8~0;~E_8~0 := 2; 1167529#L1037-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 1167509#L650-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 1167499#L697-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 1167497#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret25#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret25#1;havoc start_simulation_#t~ret25#1; 1156384#L1322 assume !(0 == start_simulation_~tmp~3#1); 1156385#L1322-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret24#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 1157423#L650-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 1157417#L697-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 1157415#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret24#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret24#1;havoc stop_simulation_#t~ret24#1; 1157413#L1277 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 1157411#L1284 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 1157410#stop_simulation_returnLabel#1 start_simulation_#t~ret26#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret24#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret26#1;havoc start_simulation_#t~ret26#1; 1157409#L1335 assume !(0 != start_simulation_~tmp___0~1#1); 1107926#L1303-2 [2023-11-12 02:34:48,678 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-12 02:34:48,678 INFO L85 PathProgramCache]: Analyzing trace with hash 330692485, now seen corresponding path program 1 times [2023-11-12 02:34:48,678 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-12 02:34:48,678 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2023797045] [2023-11-12 02:34:48,679 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-12 02:34:48,679 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-12 02:34:48,702 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-12 02:34:48,773 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-12 02:34:48,773 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-12 02:34:48,774 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2023797045] [2023-11-12 02:34:48,774 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2023797045] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-12 02:34:48,774 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-12 02:34:48,774 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-12 02:34:48,774 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [681537288] [2023-11-12 02:34:48,775 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-12 02:34:48,775 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-12 02:34:48,775 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-12 02:34:48,776 INFO L85 PathProgramCache]: Analyzing trace with hash 473303465, now seen corresponding path program 1 times [2023-11-12 02:34:48,776 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-12 02:34:48,776 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2095845578] [2023-11-12 02:34:48,776 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-12 02:34:48,777 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-12 02:34:48,793 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-12 02:34:48,833 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-12 02:34:48,834 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-12 02:34:48,834 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2095845578] [2023-11-12 02:34:48,834 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2095845578] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-12 02:34:48,834 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-12 02:34:48,834 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-12 02:34:48,835 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [471622760] [2023-11-12 02:34:48,835 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-12 02:34:48,835 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-12 02:34:48,836 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-12 02:34:48,836 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2023-11-12 02:34:48,836 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2023-11-12 02:34:48,836 INFO L87 Difference]: Start difference. First operand 124341 states and 174807 transitions. cyclomatic complexity: 50530 Second operand has 4 states, 4 states have (on average 26.5) internal successors, (106), 3 states have internal predecessors, (106), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-12 02:34:50,185 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-12 02:34:50,185 INFO L93 Difference]: Finished difference Result 199317 states and 279980 transitions. [2023-11-12 02:34:50,185 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 199317 states and 279980 transitions. [2023-11-12 02:34:50,885 INFO L131 ngComponentsAnalysis]: Automaton has 96 accepting balls. 198054 [2023-11-12 02:34:51,298 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 199317 states to 199317 states and 279980 transitions. [2023-11-12 02:34:51,298 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 199317 [2023-11-12 02:34:51,380 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 199317 [2023-11-12 02:34:51,380 INFO L73 IsDeterministic]: Start isDeterministic. Operand 199317 states and 279980 transitions. [2023-11-12 02:34:51,446 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-12 02:34:51,446 INFO L218 hiAutomatonCegarLoop]: Abstraction has 199317 states and 279980 transitions. [2023-11-12 02:34:52,335 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 199317 states and 279980 transitions. [2023-11-12 02:34:53,652 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 199317 to 141521. [2023-11-12 02:34:53,738 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 141521 states, 141521 states have (on average 1.4069926018046792) internal successors, (199119), 141520 states have internal predecessors, (199119), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-12 02:34:54,824 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 141521 states to 141521 states and 199119 transitions. [2023-11-12 02:34:54,824 INFO L240 hiAutomatonCegarLoop]: Abstraction has 141521 states and 199119 transitions. [2023-11-12 02:34:54,825 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2023-11-12 02:34:54,825 INFO L428 stractBuchiCegarLoop]: Abstraction has 141521 states and 199119 transitions. [2023-11-12 02:34:54,825 INFO L335 stractBuchiCegarLoop]: ======== Iteration 19 ============ [2023-11-12 02:34:54,825 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 141521 states and 199119 transitions. [2023-11-12 02:34:55,124 INFO L131 ngComponentsAnalysis]: Automaton has 64 accepting balls. 140624 [2023-11-12 02:34:55,124 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-12 02:34:55,124 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-12 02:34:55,126 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-12 02:34:55,126 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-12 02:34:55,126 INFO L748 eck$LassoCheckResult]: Stem: 1431088#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~token~0 := 0;~local~0 := 0; 1431089#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~10#1;havoc main_~__retres1~10#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; 1431861#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret25#1, start_simulation_#t~ret26#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 1431862#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 1431944#L597 assume 1 == ~m_i~0;~m_st~0 := 0; 1431555#L597-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 1431556#L602-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 1431106#L607-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 1431107#L612-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 1431036#L617-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 1431037#L622-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 1431312#L627-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 1431284#L632-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 1431285#L637-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 1431621#L854 assume !(0 == ~M_E~0); 1431381#L854-2 assume !(0 == ~T1_E~0); 1431382#L859-1 assume !(0 == ~T2_E~0); 1430913#L864-1 assume !(0 == ~T3_E~0); 1430914#L869-1 assume !(0 == ~T4_E~0); 1431025#L874-1 assume !(0 == ~T5_E~0); 1431915#L879-1 assume !(0 == ~T6_E~0); 1431372#L884-1 assume !(0 == ~T7_E~0); 1430775#L889-1 assume 0 == ~T8_E~0;~T8_E~0 := 1; 1430776#L894-1 assume !(0 == ~E_M~0); 1432002#L899-1 assume !(0 == ~E_1~0); 1432003#L904-1 assume !(0 == ~E_2~0); 1431301#L909-1 assume !(0 == ~E_3~0); 1431302#L914-1 assume !(0 == ~E_4~0); 1431575#L919-1 assume !(0 == ~E_5~0); 1431576#L924-1 assume !(0 == ~E_6~0); 1431007#L929-1 assume !(0 == ~E_7~0); 1431008#L934-1 assume !(0 == ~E_8~0); 1431280#L939-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1431281#L418 assume !(1 == ~m_pc~0); 1431962#L418-2 is_master_triggered_~__retres1~0#1 := 0; 1431963#L429 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1431777#is_master_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 1431778#L1061 assume !(0 != activate_threads_~tmp~1#1); 1431659#L1061-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1431660#L437 assume !(1 == ~t1_pc~0); 1431896#L437-2 is_transmit1_triggered_~__retres1~1#1 := 0; 1431897#L448 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1430816#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 1430817#L1069 assume !(0 != activate_threads_~tmp___0~0#1); 1431917#L1069-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1431918#L456 assume !(1 == ~t2_pc~0); 1431066#L456-2 is_transmit2_triggered_~__retres1~2#1 := 0; 1431065#L467 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1431240#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 1431241#L1077 assume !(0 != activate_threads_~tmp___1~0#1); 1431421#L1077-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1431422#L475 assume !(1 == ~t3_pc~0); 1431501#L475-2 is_transmit3_triggered_~__retres1~3#1 := 0; 1431502#L486 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1430784#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1430785#L1085 assume !(0 != activate_threads_~tmp___2~0#1); 1431155#L1085-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1431156#L494 assume !(1 == ~t4_pc~0); 1431200#L494-2 is_transmit4_triggered_~__retres1~4#1 := 0; 1431201#L505 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1430923#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1430924#L1093 assume !(0 != activate_threads_~tmp___3~0#1); 1431572#L1093-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1431573#L513 assume !(1 == ~t5_pc~0); 1431202#L513-2 is_transmit5_triggered_~__retres1~5#1 := 0; 1431203#L524 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1431781#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1431782#L1101 assume !(0 != activate_threads_~tmp___4~0#1); 1431956#L1101-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1431957#L532 assume !(1 == ~t6_pc~0); 1431028#L532-2 is_transmit6_triggered_~__retres1~6#1 := 0; 1431027#L543 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1431221#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1431222#L1109 assume !(0 != activate_threads_~tmp___5~0#1); 1431125#L1109-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1431126#L551 assume !(1 == ~t7_pc~0); 1431630#L551-2 is_transmit7_triggered_~__retres1~7#1 := 0; 1431631#L562 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1431978#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 1431979#L1117 assume !(0 != activate_threads_~tmp___6~0#1); 1431985#L1117-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 1431986#L570 assume !(1 == ~t8_pc~0); 1431905#L570-2 is_transmit8_triggered_~__retres1~8#1 := 0; 1431906#L581 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 1431710#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 1431711#L1125 assume !(0 != activate_threads_~tmp___7~0#1); 1430902#L1125-2 havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1430903#L952 assume !(1 == ~M_E~0); 1430841#L952-2 assume !(1 == ~T1_E~0); 1430842#L957-1 assume !(1 == ~T2_E~0); 1431959#L962-1 assume !(1 == ~T3_E~0); 1431960#L967-1 assume !(1 == ~T4_E~0); 1431945#L972-1 assume !(1 == ~T5_E~0); 1431946#L977-1 assume !(1 == ~T6_E~0); 1431988#L982-1 assume !(1 == ~T7_E~0); 1431989#L987-1 assume 1 == ~T8_E~0;~T8_E~0 := 2; 1431031#L992-1 assume !(1 == ~E_M~0); 1431038#L997-1 assume !(1 == ~E_1~0); 1431419#L1002-1 assume !(1 == ~E_2~0); 1431404#L1007-1 assume !(1 == ~E_3~0); 1430778#L1012-1 assume !(1 == ~E_4~0); 1430779#L1017-1 assume !(1 == ~E_5~0); 1431407#L1022-1 assume !(1 == ~E_6~0); 1431408#L1027-1 assume 1 == ~E_7~0;~E_7~0 := 2; 1431435#L1032-1 assume !(1 == ~E_8~0); 1431608#L1037-1 assume { :end_inline_reset_delta_events } true; 1431609#L1303-2 [2023-11-12 02:34:55,127 INFO L750 eck$LassoCheckResult]: Loop: 1431609#L1303-2 assume !false; 1494543#L1304 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 1494538#L829-1 assume !false; 1494536#L708 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 1494524#L650 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 1494518#L697 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 1494515#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 1494512#L712 assume !(0 != eval_~tmp~0#1); 1494510#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 1494508#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 1494506#L854-3 assume !(0 == ~M_E~0); 1494504#L854-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 1494502#L859-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 1494500#L864-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 1494498#L869-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 1494496#L874-3 assume !(0 == ~T5_E~0); 1494494#L879-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 1494492#L884-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 1494488#L889-3 assume !(0 == ~T8_E~0); 1494486#L894-3 assume 0 == ~E_M~0;~E_M~0 := 1; 1494484#L899-3 assume 0 == ~E_1~0;~E_1~0 := 1; 1494482#L904-3 assume 0 == ~E_2~0;~E_2~0 := 1; 1494480#L909-3 assume 0 == ~E_3~0;~E_3~0 := 1; 1494479#L914-3 assume !(0 == ~E_4~0); 1494478#L919-3 assume 0 == ~E_5~0;~E_5~0 := 1; 1494474#L924-3 assume 0 == ~E_6~0;~E_6~0 := 1; 1494472#L929-3 assume !(0 == ~E_7~0); 1494470#L934-3 assume 0 == ~E_8~0;~E_8~0 := 1; 1494469#L939-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1494466#L418-30 assume !(1 == ~m_pc~0); 1494465#L418-32 is_master_triggered_~__retres1~0#1 := 0; 1494461#L429-10 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1494459#is_master_triggered_returnLabel#11 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 1494457#L1061-30 assume !(0 != activate_threads_~tmp~1#1); 1494456#L1061-32 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1494453#L437-30 assume !(1 == ~t1_pc~0); 1494451#L437-32 is_transmit1_triggered_~__retres1~1#1 := 0; 1494449#L448-10 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1494447#is_transmit1_triggered_returnLabel#11 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 1494445#L1069-30 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 1494443#L1069-32 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1494441#L456-30 assume !(1 == ~t2_pc~0); 1494438#L456-32 is_transmit2_triggered_~__retres1~2#1 := 0; 1494436#L467-10 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1494434#is_transmit2_triggered_returnLabel#11 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 1494432#L1077-30 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 1494430#L1077-32 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1494428#L475-30 assume !(1 == ~t3_pc~0); 1494427#L475-32 is_transmit3_triggered_~__retres1~3#1 := 0; 1494426#L486-10 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1494422#is_transmit3_triggered_returnLabel#11 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1494420#L1085-30 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 1494418#L1085-32 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1494417#L494-30 assume 1 == ~t4_pc~0; 1494414#L495-10 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 1494412#L505-10 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1494410#is_transmit4_triggered_returnLabel#11 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1494409#L1093-30 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 1494408#L1093-32 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1494407#L513-30 assume !(1 == ~t5_pc~0); 1494406#L513-32 is_transmit5_triggered_~__retres1~5#1 := 0; 1494405#L524-10 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1494404#is_transmit5_triggered_returnLabel#11 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1494403#L1101-30 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 1494402#L1101-32 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1494401#L532-30 assume !(1 == ~t6_pc~0); 1494398#L532-32 is_transmit6_triggered_~__retres1~6#1 := 0; 1494396#L543-10 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1494394#is_transmit6_triggered_returnLabel#11 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1494392#L1109-30 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 1494390#L1109-32 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1494388#L551-30 assume !(1 == ~t7_pc~0); 1494386#L551-32 is_transmit7_triggered_~__retres1~7#1 := 0; 1494384#L562-10 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1494382#is_transmit7_triggered_returnLabel#11 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 1494380#L1117-30 assume !(0 != activate_threads_~tmp___6~0#1); 1494378#L1117-32 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 1494376#L570-30 assume !(1 == ~t8_pc~0); 1494374#L570-32 is_transmit8_triggered_~__retres1~8#1 := 0; 1494372#L581-10 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 1494370#is_transmit8_triggered_returnLabel#11 activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 1494368#L1125-30 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 1494366#L1125-32 havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1494364#L952-3 assume !(1 == ~M_E~0); 1494362#L952-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 1494360#L957-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 1494358#L962-3 assume !(1 == ~T3_E~0); 1494356#L967-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 1494355#L972-3 assume !(1 == ~T5_E~0); 1494353#L977-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 1494351#L982-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 1494349#L987-3 assume !(1 == ~T8_E~0); 1494346#L992-3 assume 1 == ~E_M~0;~E_M~0 := 2; 1494344#L997-3 assume 1 == ~E_1~0;~E_1~0 := 2; 1494342#L1002-3 assume !(1 == ~E_2~0); 1494340#L1007-3 assume 1 == ~E_3~0;~E_3~0 := 2; 1494338#L1012-3 assume 1 == ~E_4~0;~E_4~0 := 2; 1494336#L1017-3 assume 1 == ~E_5~0;~E_5~0 := 2; 1494334#L1022-3 assume 1 == ~E_6~0;~E_6~0 := 2; 1494332#L1027-3 assume 1 == ~E_7~0;~E_7~0 := 2; 1494330#L1032-3 assume 1 == ~E_8~0;~E_8~0 := 2; 1494329#L1037-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 1494323#L650-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 1494314#L697-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 1494311#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret25#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret25#1;havoc start_simulation_#t~ret25#1; 1473970#L1322 assume !(0 == start_simulation_~tmp~3#1); 1473971#L1322-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret24#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 1494562#L650-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 1494556#L697-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 1494554#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret24#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret24#1;havoc stop_simulation_#t~ret24#1; 1494552#L1277 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 1494550#L1284 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 1494548#stop_simulation_returnLabel#1 start_simulation_#t~ret26#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret24#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret26#1;havoc start_simulation_#t~ret26#1; 1494546#L1335 assume !(0 != start_simulation_~tmp___0~1#1); 1431609#L1303-2 [2023-11-12 02:34:55,127 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-12 02:34:55,128 INFO L85 PathProgramCache]: Analyzing trace with hash -2085143865, now seen corresponding path program 1 times [2023-11-12 02:34:55,128 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-12 02:34:55,128 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [628345351] [2023-11-12 02:34:55,128 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-12 02:34:55,128 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-12 02:34:55,140 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-12 02:34:55,188 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-12 02:34:55,188 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-12 02:34:55,189 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [628345351] [2023-11-12 02:34:55,189 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [628345351] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-12 02:34:55,189 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-12 02:34:55,189 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-12 02:34:55,189 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1525830370] [2023-11-12 02:34:55,189 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-12 02:34:55,190 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-12 02:34:55,191 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-12 02:34:55,191 INFO L85 PathProgramCache]: Analyzing trace with hash -892463701, now seen corresponding path program 1 times [2023-11-12 02:34:55,191 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-12 02:34:55,191 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [585098586] [2023-11-12 02:34:55,192 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-12 02:34:55,192 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-12 02:34:55,205 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-12 02:34:55,236 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-12 02:34:55,237 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-12 02:34:55,237 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [585098586] [2023-11-12 02:34:55,237 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [585098586] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-12 02:34:55,240 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-12 02:34:55,240 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-12 02:34:55,240 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1284036689] [2023-11-12 02:34:55,240 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-12 02:34:55,242 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-12 02:34:55,242 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-12 02:34:55,242 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2023-11-12 02:34:55,242 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2023-11-12 02:34:55,243 INFO L87 Difference]: Start difference. First operand 141521 states and 199119 transitions. cyclomatic complexity: 57662 Second operand has 4 states, 4 states have (on average 26.5) internal successors, (106), 3 states have internal predecessors, (106), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-12 02:34:55,648 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-12 02:34:55,648 INFO L93 Difference]: Finished difference Result 124341 states and 174265 transitions. [2023-11-12 02:34:55,648 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 124341 states and 174265 transitions.