./Ultimate.py --spec ../../sv-benchmarks/c/properties/termination.prp --file ../../sv-benchmarks/c/systemc/token_ring.10.cil-1.c --full-output --architecture 32bit -------------------------------------------------------------------------------- Checking for termination Using default analysis Version cf1a7837 Calling Ultimate with: /usr/lib/jvm/java-11-openjdk-amd64/bin/java -Dosgi.configuration.area=/tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7df9f9d5-724c-4200-8191-796c16c1dec7/bin/uautomizer-verify-uTZkv6EMXl/data/config -Xmx15G -Xms4m -jar /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7df9f9d5-724c-4200-8191-796c16c1dec7/bin/uautomizer-verify-uTZkv6EMXl/plugins/org.eclipse.equinox.launcher_1.5.800.v20200727-1323.jar -data @noDefault -ultimatedata /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7df9f9d5-724c-4200-8191-796c16c1dec7/bin/uautomizer-verify-uTZkv6EMXl/data -tc /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7df9f9d5-724c-4200-8191-796c16c1dec7/bin/uautomizer-verify-uTZkv6EMXl/config/AutomizerTermination.xml -i ../../sv-benchmarks/c/systemc/token_ring.10.cil-1.c -s /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7df9f9d5-724c-4200-8191-796c16c1dec7/bin/uautomizer-verify-uTZkv6EMXl/config/svcomp-Termination-32bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7df9f9d5-724c-4200-8191-796c16c1dec7/bin/uautomizer-verify-uTZkv6EMXl --witnessprinter.witness.filename witness --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(F end) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 32bit --witnessprinter.graph.data.programhash 9102a3dc168a1a089cfcbe45042daf88c4c5eebedf113fc0c98e676c1fbaab5b --- Real Ultimate output --- This is Ultimate 0.2.3-dev-cf1a783 [2023-11-12 02:20:00,252 INFO L188 SettingsManager]: Resetting all preferences to default values... [2023-11-12 02:20:00,373 INFO L114 SettingsManager]: Loading settings from /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7df9f9d5-724c-4200-8191-796c16c1dec7/bin/uautomizer-verify-uTZkv6EMXl/config/svcomp-Termination-32bit-Automizer_Default.epf [2023-11-12 02:20:00,379 WARN L101 SettingsManager]: Preference file contains the following unknown settings: [2023-11-12 02:20:00,380 WARN L103 SettingsManager]: * de.uni_freiburg.informatik.ultimate.core.Log level for class [2023-11-12 02:20:00,405 INFO L130 SettingsManager]: Preferences different from defaults after loading the file: [2023-11-12 02:20:00,406 INFO L151 SettingsManager]: Preferences of UltimateCore differ from their defaults: [2023-11-12 02:20:00,406 INFO L153 SettingsManager]: * Log level for class=de.uni_freiburg.informatik.ultimate.lib.smtlibutils.quantifier.QuantifierPusher=ERROR; [2023-11-12 02:20:00,408 INFO L151 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2023-11-12 02:20:00,413 INFO L153 SettingsManager]: * Create parallel compositions if possible=false [2023-11-12 02:20:00,415 INFO L153 SettingsManager]: * Use SBE=true [2023-11-12 02:20:00,415 INFO L151 SettingsManager]: Preferences of BuchiAutomizer differ from their defaults: [2023-11-12 02:20:00,416 INFO L153 SettingsManager]: * NCSB implementation=INTSET_LAZY3 [2023-11-12 02:20:00,417 INFO L153 SettingsManager]: * Use old map elimination=false [2023-11-12 02:20:00,418 INFO L153 SettingsManager]: * Use external solver (rank synthesis)=false [2023-11-12 02:20:00,418 INFO L153 SettingsManager]: * Use only trivial implications for array writes=true [2023-11-12 02:20:00,419 INFO L153 SettingsManager]: * Rank analysis=LINEAR_WITH_GUESSES [2023-11-12 02:20:00,420 INFO L151 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2023-11-12 02:20:00,421 INFO L153 SettingsManager]: * Pointer base address is valid at dereference=ASSUME [2023-11-12 02:20:00,421 INFO L153 SettingsManager]: * sizeof long=4 [2023-11-12 02:20:00,422 INFO L153 SettingsManager]: * Overapproximate operations on floating types=true [2023-11-12 02:20:00,422 INFO L153 SettingsManager]: * sizeof POINTER=4 [2023-11-12 02:20:00,423 INFO L153 SettingsManager]: * Check division by zero=IGNORE [2023-11-12 02:20:00,423 INFO L153 SettingsManager]: * Pointer to allocated memory at dereference=ASSUME [2023-11-12 02:20:00,424 INFO L153 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=ASSUME [2023-11-12 02:20:00,424 INFO L153 SettingsManager]: * Check array bounds for arrays that are off heap=ASSUME [2023-11-12 02:20:00,425 INFO L153 SettingsManager]: * Check unreachability of reach_error function=false [2023-11-12 02:20:00,425 INFO L153 SettingsManager]: * sizeof long double=12 [2023-11-12 02:20:00,426 INFO L153 SettingsManager]: * Check if freed pointer was valid=false [2023-11-12 02:20:00,426 INFO L153 SettingsManager]: * Assume nondeterminstic values are in range=false [2023-11-12 02:20:00,428 INFO L153 SettingsManager]: * Use constant arrays=true [2023-11-12 02:20:00,428 INFO L151 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2023-11-12 02:20:00,428 INFO L153 SettingsManager]: * Size of a code block=SequenceOfStatements [2023-11-12 02:20:00,429 INFO L151 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2023-11-12 02:20:00,429 INFO L153 SettingsManager]: * Trace refinement strategy=CAMEL [2023-11-12 02:20:00,430 INFO L151 SettingsManager]: Preferences of IcfgTransformer differ from their defaults: [2023-11-12 02:20:00,430 INFO L153 SettingsManager]: * TransformationType=MODULO_NEIGHBOR WARNING: An illegal reflective access operation has occurred WARNING: Illegal reflective access by com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 (file:/tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7df9f9d5-724c-4200-8191-796c16c1dec7/bin/uautomizer-verify-uTZkv6EMXl/plugins/com.sun.xml.bind_2.2.0.v201505121915.jar) to method java.lang.ClassLoader.defineClass(java.lang.String,byte[],int,int) WARNING: Please consider reporting this to the maintainers of com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 WARNING: Use --illegal-access=warn to enable warnings of further illegal reflective access operations WARNING: All illegal access operations will be denied in a future release Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7df9f9d5-724c-4200-8191-796c16c1dec7/bin/uautomizer-verify-uTZkv6EMXl Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(F end) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 32bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> 9102a3dc168a1a089cfcbe45042daf88c4c5eebedf113fc0c98e676c1fbaab5b [2023-11-12 02:20:00,782 INFO L75 nceAwareModelManager]: Repository-Root is: /tmp [2023-11-12 02:20:00,813 INFO L261 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2023-11-12 02:20:00,815 INFO L217 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2023-11-12 02:20:00,817 INFO L270 PluginConnector]: Initializing CDTParser... [2023-11-12 02:20:00,818 INFO L274 PluginConnector]: CDTParser initialized [2023-11-12 02:20:00,819 INFO L431 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7df9f9d5-724c-4200-8191-796c16c1dec7/bin/uautomizer-verify-uTZkv6EMXl/../../sv-benchmarks/c/systemc/token_ring.10.cil-1.c [2023-11-12 02:20:03,977 INFO L533 CDTParser]: Created temporary CDT project at NULL [2023-11-12 02:20:04,297 INFO L384 CDTParser]: Found 1 translation units. [2023-11-12 02:20:04,298 INFO L180 CDTParser]: Scanning /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7df9f9d5-724c-4200-8191-796c16c1dec7/sv-benchmarks/c/systemc/token_ring.10.cil-1.c [2023-11-12 02:20:04,314 INFO L427 CDTParser]: About to delete temporary CDT project at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7df9f9d5-724c-4200-8191-796c16c1dec7/bin/uautomizer-verify-uTZkv6EMXl/data/2a84a0dea/e896bdad429047f6a87cede55c29c00b/FLAG7c289e7cc [2023-11-12 02:20:04,333 INFO L435 CDTParser]: Successfully deleted /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7df9f9d5-724c-4200-8191-796c16c1dec7/bin/uautomizer-verify-uTZkv6EMXl/data/2a84a0dea/e896bdad429047f6a87cede55c29c00b [2023-11-12 02:20:04,339 INFO L299 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2023-11-12 02:20:04,341 INFO L133 ToolchainWalker]: Walking toolchain with 6 elements. [2023-11-12 02:20:04,346 INFO L112 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2023-11-12 02:20:04,347 INFO L270 PluginConnector]: Initializing CACSL2BoogieTranslator... [2023-11-12 02:20:04,353 INFO L274 PluginConnector]: CACSL2BoogieTranslator initialized [2023-11-12 02:20:04,354 INFO L184 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 12.11 02:20:04" (1/1) ... [2023-11-12 02:20:04,355 INFO L204 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@3931b501 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 12.11 02:20:04, skipping insertion in model container [2023-11-12 02:20:04,355 INFO L184 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 12.11 02:20:04" (1/1) ... [2023-11-12 02:20:04,427 INFO L177 MainTranslator]: Built tables and reachable declarations [2023-11-12 02:20:04,799 INFO L209 PostProcessor]: Analyzing one entry point: main [2023-11-12 02:20:04,816 INFO L202 MainTranslator]: Completed pre-run [2023-11-12 02:20:04,900 INFO L209 PostProcessor]: Analyzing one entry point: main [2023-11-12 02:20:04,920 INFO L206 MainTranslator]: Completed translation [2023-11-12 02:20:04,921 INFO L201 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 12.11 02:20:04 WrapperNode [2023-11-12 02:20:04,921 INFO L131 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2023-11-12 02:20:04,922 INFO L112 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2023-11-12 02:20:04,922 INFO L270 PluginConnector]: Initializing Boogie Procedure Inliner... [2023-11-12 02:20:04,923 INFO L274 PluginConnector]: Boogie Procedure Inliner initialized [2023-11-12 02:20:04,930 INFO L184 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 12.11 02:20:04" (1/1) ... [2023-11-12 02:20:04,945 INFO L184 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 12.11 02:20:04" (1/1) ... [2023-11-12 02:20:05,065 INFO L138 Inliner]: procedures = 48, calls = 63, calls flagged for inlining = 58, calls inlined = 212, statements flattened = 3223 [2023-11-12 02:20:05,066 INFO L131 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2023-11-12 02:20:05,067 INFO L112 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2023-11-12 02:20:05,067 INFO L270 PluginConnector]: Initializing Boogie Preprocessor... [2023-11-12 02:20:05,067 INFO L274 PluginConnector]: Boogie Preprocessor initialized [2023-11-12 02:20:05,077 INFO L184 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 12.11 02:20:04" (1/1) ... [2023-11-12 02:20:05,077 INFO L184 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 12.11 02:20:04" (1/1) ... [2023-11-12 02:20:05,094 INFO L184 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 12.11 02:20:04" (1/1) ... [2023-11-12 02:20:05,094 INFO L184 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 12.11 02:20:04" (1/1) ... [2023-11-12 02:20:05,210 INFO L184 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 12.11 02:20:04" (1/1) ... [2023-11-12 02:20:05,245 INFO L184 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 12.11 02:20:04" (1/1) ... [2023-11-12 02:20:05,251 INFO L184 PluginConnector]: Executing the observer LTLStepAnnotator from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 12.11 02:20:04" (1/1) ... [2023-11-12 02:20:05,263 INFO L184 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 12.11 02:20:04" (1/1) ... [2023-11-12 02:20:05,276 INFO L131 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2023-11-12 02:20:05,277 INFO L112 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2023-11-12 02:20:05,277 INFO L270 PluginConnector]: Initializing RCFGBuilder... [2023-11-12 02:20:05,278 INFO L274 PluginConnector]: RCFGBuilder initialized [2023-11-12 02:20:05,279 INFO L184 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 12.11 02:20:04" (1/1) ... [2023-11-12 02:20:05,288 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2023-11-12 02:20:05,301 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7df9f9d5-724c-4200-8191-796c16c1dec7/bin/uautomizer-verify-uTZkv6EMXl/z3 [2023-11-12 02:20:05,320 INFO L229 MonitoredProcess]: Starting monitored process 1 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7df9f9d5-724c-4200-8191-796c16c1dec7/bin/uautomizer-verify-uTZkv6EMXl/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2023-11-12 02:20:05,336 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7df9f9d5-724c-4200-8191-796c16c1dec7/bin/uautomizer-verify-uTZkv6EMXl/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (1)] Waiting until timeout for monitored process [2023-11-12 02:20:05,370 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocInit [2023-11-12 02:20:05,370 INFO L130 BoogieDeclarations]: Found specification of procedure write~init~int [2023-11-12 02:20:05,370 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2023-11-12 02:20:05,371 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2023-11-12 02:20:05,491 INFO L236 CfgBuilder]: Building ICFG [2023-11-12 02:20:05,494 INFO L262 CfgBuilder]: Building CFG for each procedure with an implementation [2023-11-12 02:20:07,392 INFO L277 CfgBuilder]: Performing block encoding [2023-11-12 02:20:07,424 INFO L297 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2023-11-12 02:20:07,424 INFO L302 CfgBuilder]: Removed 13 assume(true) statements. [2023-11-12 02:20:07,428 INFO L201 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 12.11 02:20:07 BoogieIcfgContainer [2023-11-12 02:20:07,429 INFO L131 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2023-11-12 02:20:07,431 INFO L112 PluginConnector]: ------------------------BuchiAutomizer---------------------------- [2023-11-12 02:20:07,431 INFO L270 PluginConnector]: Initializing BuchiAutomizer... [2023-11-12 02:20:07,435 INFO L274 PluginConnector]: BuchiAutomizer initialized [2023-11-12 02:20:07,436 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2023-11-12 02:20:07,436 INFO L184 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "CDTParser AST 12.11 02:20:04" (1/3) ... [2023-11-12 02:20:07,437 INFO L204 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@7dd0f839 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 12.11 02:20:07, skipping insertion in model container [2023-11-12 02:20:07,437 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2023-11-12 02:20:07,438 INFO L184 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 12.11 02:20:04" (2/3) ... [2023-11-12 02:20:07,439 INFO L204 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@7dd0f839 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 12.11 02:20:07, skipping insertion in model container [2023-11-12 02:20:07,440 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2023-11-12 02:20:07,440 INFO L184 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 12.11 02:20:07" (3/3) ... [2023-11-12 02:20:07,441 INFO L332 chiAutomizerObserver]: Analyzing ICFG token_ring.10.cil-1.c [2023-11-12 02:20:07,535 INFO L303 stractBuchiCegarLoop]: Interprodecural is true [2023-11-12 02:20:07,536 INFO L304 stractBuchiCegarLoop]: Hoare is false [2023-11-12 02:20:07,536 INFO L305 stractBuchiCegarLoop]: Compute interpolants for ForwardPredicates [2023-11-12 02:20:07,536 INFO L306 stractBuchiCegarLoop]: Backedges is STRAIGHT_LINE [2023-11-12 02:20:07,536 INFO L307 stractBuchiCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2023-11-12 02:20:07,536 INFO L308 stractBuchiCegarLoop]: Difference is false [2023-11-12 02:20:07,536 INFO L309 stractBuchiCegarLoop]: Minimize is MINIMIZE_SEVPA [2023-11-12 02:20:07,536 INFO L313 stractBuchiCegarLoop]: ======== Iteration 0 == of CEGAR loop == BuchiAutomatonCegarLoop ======== [2023-11-12 02:20:07,550 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 1387 states, 1386 states have (on average 1.5021645021645023) internal successors, (2082), 1386 states have internal predecessors, (2082), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-12 02:20:07,641 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1244 [2023-11-12 02:20:07,641 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-12 02:20:07,642 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-12 02:20:07,660 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-12 02:20:07,661 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-12 02:20:07,661 INFO L335 stractBuchiCegarLoop]: ======== Iteration 1 ============ [2023-11-12 02:20:07,665 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 1387 states, 1386 states have (on average 1.5021645021645023) internal successors, (2082), 1386 states have internal predecessors, (2082), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-12 02:20:07,685 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1244 [2023-11-12 02:20:07,686 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-12 02:20:07,686 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-12 02:20:07,693 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-12 02:20:07,694 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-12 02:20:07,705 INFO L748 eck$LassoCheckResult]: Stem: 205#$Ultimate##0true assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~token~0 := 0;~local~0 := 0; 1274#L-1true assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~12#1;havoc main_~__retres1~12#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1; 1023#init_model_returnLabel#1true assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret30#1, start_simulation_#t~ret31#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 1268#update_channels_returnLabel#1true assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 1171#L731true assume !(1 == ~m_i~0);~m_st~0 := 2; 1034#L731-2true assume 1 == ~t1_i~0;~t1_st~0 := 0; 940#L736-1true assume !(1 == ~t2_i~0);~t2_st~0 := 2; 1010#L741-1true assume !(1 == ~t3_i~0);~t3_st~0 := 2; 1328#L746-1true assume !(1 == ~t4_i~0);~t4_st~0 := 2; 169#L751-1true assume !(1 == ~t5_i~0);~t5_st~0 := 2; 229#L756-1true assume !(1 == ~t6_i~0);~t6_st~0 := 2; 850#L761-1true assume !(1 == ~t7_i~0);~t7_st~0 := 2; 386#L766-1true assume !(1 == ~t8_i~0);~t8_st~0 := 2; 335#L771-1true assume 1 == ~t9_i~0;~t9_st~0 := 0; 170#L776-1true assume !(1 == ~t10_i~0);~t10_st~0 := 2; 10#L781-1true assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 54#L1036true assume !(0 == ~M_E~0); 1043#L1036-2true assume !(0 == ~T1_E~0); 620#L1041-1true assume !(0 == ~T2_E~0); 982#L1046-1true assume 0 == ~T3_E~0;~T3_E~0 := 1; 193#L1051-1true assume !(0 == ~T4_E~0); 759#L1056-1true assume !(0 == ~T5_E~0); 814#L1061-1true assume !(0 == ~T6_E~0); 137#L1066-1true assume !(0 == ~T7_E~0); 1166#L1071-1true assume !(0 == ~T8_E~0); 739#L1076-1true assume !(0 == ~T9_E~0); 83#L1081-1true assume !(0 == ~T10_E~0); 300#L1086-1true assume 0 == ~E_M~0;~E_M~0 := 1; 1183#L1091-1true assume !(0 == ~E_1~0); 1045#L1096-1true assume !(0 == ~E_2~0); 1278#L1101-1true assume !(0 == ~E_3~0); 344#L1106-1true assume !(0 == ~E_4~0); 559#L1111-1true assume !(0 == ~E_5~0); 462#L1116-1true assume !(0 == ~E_6~0); 1105#L1121-1true assume !(0 == ~E_7~0); 338#L1126-1true assume 0 == ~E_8~0;~E_8~0 := 1; 539#L1131-1true assume !(0 == ~E_9~0); 629#L1136-1true assume !(0 == ~E_10~0); 905#L1141-1true assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 799#L514true assume 1 == ~m_pc~0; 749#L515true assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 348#L525true is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 877#is_master_triggered_returnLabel#1true activate_threads_#t~ret18#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1117#L1285true assume !(0 != activate_threads_~tmp~1#1); 1204#L1285-2true assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 145#L533true assume !(1 == ~t1_pc~0); 1059#L533-2true is_transmit1_triggered_~__retres1~1#1 := 0; 506#L544true is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 34#is_transmit1_triggered_returnLabel#1true activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 919#L1293true assume !(0 != activate_threads_~tmp___0~0#1); 653#L1293-2true assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 909#L552true assume 1 == ~t2_pc~0; 269#L553true assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 941#L563true is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 340#is_transmit2_triggered_returnLabel#1true activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 986#L1301true assume !(0 != activate_threads_~tmp___1~0#1); 357#L1301-2true assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 518#L571true assume 1 == ~t3_pc~0; 503#L572true assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 691#L582true is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 9#is_transmit3_triggered_returnLabel#1true activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 660#L1309true assume !(0 != activate_threads_~tmp___2~0#1); 465#L1309-2true assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 48#L590true assume !(1 == ~t4_pc~0); 517#L590-2true is_transmit4_triggered_~__retres1~4#1 := 0; 1300#L601true is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 92#is_transmit4_triggered_returnLabel#1true activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 1129#L1317true assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 676#L1317-2true assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 463#L609true assume 1 == ~t5_pc~0; 1290#L610true assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 1114#L620true is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 881#is_transmit5_triggered_returnLabel#1true activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 1388#L1325true assume !(0 != activate_threads_~tmp___4~0#1); 457#L1325-2true assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1287#L628true assume !(1 == ~t6_pc~0); 540#L628-2true is_transmit6_triggered_~__retres1~6#1 := 0; 1264#L639true is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 324#is_transmit6_triggered_returnLabel#1true activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 1194#L1333true assume !(0 != activate_threads_~tmp___5~0#1); 715#L1333-2true assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 859#L647true assume 1 == ~t7_pc~0; 345#L648true assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 896#L658true is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1294#is_transmit7_triggered_returnLabel#1true activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 346#L1341true assume !(0 != activate_threads_~tmp___6~0#1); 1257#L1341-2true assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 1230#L666true assume !(1 == ~t8_pc~0); 797#L666-2true is_transmit8_triggered_~__retres1~8#1 := 0; 356#L677true is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 800#is_transmit8_triggered_returnLabel#1true activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 482#L1349true assume !(0 != activate_threads_~tmp___7~0#1); 298#L1349-2true assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 1147#L685true assume 1 == ~t9_pc~0; 1310#L686true assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 920#L696true is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 381#is_transmit9_triggered_returnLabel#1true activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 316#L1357true assume !(0 != activate_threads_~tmp___8~0#1); 1017#L1357-2true assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 599#L704true assume !(1 == ~t10_pc~0); 1102#L704-2true is_transmit10_triggered_~__retres1~10#1 := 0; 1052#L715true is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 495#is_transmit10_triggered_returnLabel#1true activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 71#L1365true assume !(0 != activate_threads_~tmp___9~0#1); 197#L1365-2true havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 704#L1154true assume !(1 == ~M_E~0); 1190#L1154-2true assume !(1 == ~T1_E~0); 182#L1159-1true assume !(1 == ~T2_E~0); 1320#L1164-1true assume !(1 == ~T3_E~0); 480#L1169-1true assume !(1 == ~T4_E~0); 382#L1174-1true assume 1 == ~T5_E~0;~T5_E~0 := 2; 253#L1179-1true assume !(1 == ~T6_E~0); 174#L1184-1true assume !(1 == ~T7_E~0); 217#L1189-1true assume !(1 == ~T8_E~0); 289#L1194-1true assume !(1 == ~T9_E~0); 1368#L1199-1true assume !(1 == ~T10_E~0); 263#L1204-1true assume !(1 == ~E_M~0); 1225#L1209-1true assume !(1 == ~E_1~0); 672#L1214-1true assume 1 == ~E_2~0;~E_2~0 := 2; 1318#L1219-1true assume !(1 == ~E_3~0); 1200#L1224-1true assume !(1 == ~E_4~0); 500#L1229-1true assume !(1 == ~E_5~0); 117#L1234-1true assume !(1 == ~E_6~0); 786#L1239-1true assume !(1 == ~E_7~0); 143#L1244-1true assume !(1 == ~E_8~0); 836#L1249-1true assume !(1 == ~E_9~0); 747#L1254-1true assume 1 == ~E_10~0;~E_10~0 := 2; 68#L1259-1true assume { :end_inline_reset_delta_events } true; 1179#L1565-2true [2023-11-12 02:20:07,708 INFO L750 eck$LassoCheckResult]: Loop: 1179#L1565-2true assume !false; 680#L1566true start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 1073#L1011-1true assume false; 811#eval_returnLabel#1true havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 512#update_channels_returnLabel#2true assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 754#L1036-3true assume 0 == ~M_E~0;~M_E~0 := 1; 1080#L1036-5true assume 0 == ~T1_E~0;~T1_E~0 := 1; 1316#L1041-3true assume 0 == ~T2_E~0;~T2_E~0 := 1; 844#L1046-3true assume 0 == ~T3_E~0;~T3_E~0 := 1; 1201#L1051-3true assume !(0 == ~T4_E~0); 755#L1056-3true assume 0 == ~T5_E~0;~T5_E~0 := 1; 191#L1061-3true assume 0 == ~T6_E~0;~T6_E~0 := 1; 192#L1066-3true assume 0 == ~T7_E~0;~T7_E~0 := 1; 1333#L1071-3true assume 0 == ~T8_E~0;~T8_E~0 := 1; 1083#L1076-3true assume 0 == ~T9_E~0;~T9_E~0 := 1; 65#L1081-3true assume 0 == ~T10_E~0;~T10_E~0 := 1; 1247#L1086-3true assume 0 == ~E_M~0;~E_M~0 := 1; 88#L1091-3true assume !(0 == ~E_1~0); 1157#L1096-3true assume 0 == ~E_2~0;~E_2~0 := 1; 1012#L1101-3true assume 0 == ~E_3~0;~E_3~0 := 1; 1079#L1106-3true assume 0 == ~E_4~0;~E_4~0 := 1; 1134#L1111-3true assume 0 == ~E_5~0;~E_5~0 := 1; 998#L1116-3true assume 0 == ~E_6~0;~E_6~0 := 1; 609#L1121-3true assume 0 == ~E_7~0;~E_7~0 := 1; 944#L1126-3true assume 0 == ~E_8~0;~E_8~0 := 1; 870#L1131-3true assume !(0 == ~E_9~0); 1311#L1136-3true assume 0 == ~E_10~0;~E_10~0 := 1; 1284#L1141-3true assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 613#L514-36true assume 1 == ~m_pc~0; 1362#L515-12true assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 283#L525-12true is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1026#is_master_triggered_returnLabel#13true activate_threads_#t~ret18#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 651#L1285-36true assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 221#L1285-38true assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 400#L533-36true assume !(1 == ~t1_pc~0); 751#L533-38true is_transmit1_triggered_~__retres1~1#1 := 0; 969#L544-12true is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1024#is_transmit1_triggered_returnLabel#13true activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 690#L1293-36true assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 516#L1293-38true assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1377#L552-36true assume !(1 == ~t2_pc~0); 1349#L552-38true is_transmit2_triggered_~__retres1~2#1 := 0; 558#L563-12true is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 857#is_transmit2_triggered_returnLabel#13true activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1188#L1301-36true assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 203#L1301-38true assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 847#L571-36true assume !(1 == ~t3_pc~0); 975#L571-38true is_transmit3_triggered_~__retres1~3#1 := 0; 254#L582-12true is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 378#is_transmit3_triggered_returnLabel#13true activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 842#L1309-36true assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 887#L1309-38true assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 238#L590-36true assume 1 == ~t4_pc~0; 705#L591-12true assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 1027#L601-12true is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 525#is_transmit4_triggered_returnLabel#13true activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 1323#L1317-36true assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 807#L1317-38true assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1070#L609-36true assume !(1 == ~t5_pc~0); 1340#L609-38true is_transmit5_triggered_~__retres1~5#1 := 0; 520#L620-12true is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 978#is_transmit5_triggered_returnLabel#13true activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 876#L1325-36true assume !(0 != activate_threads_~tmp___4~0#1); 580#L1325-38true assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 435#L628-36true assume !(1 == ~t6_pc~0); 1144#L628-38true is_transmit6_triggered_~__retres1~6#1 := 0; 1148#L639-12true is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 364#is_transmit6_triggered_returnLabel#13true activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 760#L1333-36true assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 614#L1333-38true assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1111#L647-36true assume !(1 == ~t7_pc~0); 678#L647-38true is_transmit7_triggered_~__retres1~7#1 := 0; 77#L658-12true is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 948#is_transmit7_triggered_returnLabel#13true activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 85#L1341-36true assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 706#L1341-38true assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 779#L666-36true assume 1 == ~t8_pc~0; 181#L667-12true assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 1209#L677-12true is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 604#is_transmit8_triggered_returnLabel#13true activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 1222#L1349-36true assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 268#L1349-38true assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 595#L685-36true assume !(1 == ~t9_pc~0); 132#L685-38true is_transmit9_triggered_~__retres1~9#1 := 0; 888#L696-12true is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 403#is_transmit9_triggered_returnLabel#13true activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 1277#L1357-36true assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 354#L1357-38true assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 363#L704-36true assume !(1 == ~t10_pc~0); 266#L704-38true is_transmit10_triggered_~__retres1~10#1 := 0; 1163#L715-12true is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 305#is_transmit10_triggered_returnLabel#13true activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 732#L1365-36true assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 139#L1365-38true havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1361#L1154-3true assume 1 == ~M_E~0;~M_E~0 := 2; 981#L1154-5true assume 1 == ~T1_E~0;~T1_E~0 := 2; 769#L1159-3true assume 1 == ~T2_E~0;~T2_E~0 := 2; 1335#L1164-3true assume 1 == ~T3_E~0;~T3_E~0 := 2; 1107#L1169-3true assume 1 == ~T4_E~0;~T4_E~0 := 2; 309#L1174-3true assume 1 == ~T5_E~0;~T5_E~0 := 2; 1196#L1179-3true assume !(1 == ~T6_E~0); 923#L1184-3true assume 1 == ~T7_E~0;~T7_E~0 := 2; 78#L1189-3true assume 1 == ~T8_E~0;~T8_E~0 := 2; 929#L1194-3true assume 1 == ~T9_E~0;~T9_E~0 := 2; 274#L1199-3true assume 1 == ~T10_E~0;~T10_E~0 := 2; 1371#L1204-3true assume 1 == ~E_M~0;~E_M~0 := 2; 497#L1209-3true assume 1 == ~E_1~0;~E_1~0 := 2; 17#L1214-3true assume 1 == ~E_2~0;~E_2~0 := 2; 1021#L1219-3true assume !(1 == ~E_3~0); 658#L1224-3true assume 1 == ~E_4~0;~E_4~0 := 2; 1382#L1229-3true assume 1 == ~E_5~0;~E_5~0 := 2; 679#L1234-3true assume 1 == ~E_6~0;~E_6~0 := 2; 144#L1239-3true assume 1 == ~E_7~0;~E_7~0 := 2; 535#L1244-3true assume 1 == ~E_8~0;~E_8~0 := 2; 1086#L1249-3true assume 1 == ~E_9~0;~E_9~0 := 2; 999#L1254-3true assume 1 == ~E_10~0;~E_10~0 := 2; 664#L1259-3true assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 763#L794-1true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 1296#L851-1true exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 297#exists_runnable_thread_returnLabel#2true start_simulation_#t~ret30#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret30#1;havoc start_simulation_#t~ret30#1; 618#L1584true assume !(0 == start_simulation_~tmp~3#1); 643#L1584-2true assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret29#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 150#L794-2true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 943#L851-2true exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 32#exists_runnable_thread_returnLabel#3true stop_simulation_#t~ret29#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret29#1;havoc stop_simulation_#t~ret29#1; 342#L1539true assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 987#L1546true stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 528#stop_simulation_returnLabel#1true start_simulation_#t~ret31#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret29#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret31#1;havoc start_simulation_#t~ret31#1; 1174#L1597true assume !(0 != start_simulation_~tmp___0~1#1); 1179#L1565-2true [2023-11-12 02:20:07,716 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-12 02:20:07,717 INFO L85 PathProgramCache]: Analyzing trace with hash 121410427, now seen corresponding path program 1 times [2023-11-12 02:20:07,726 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-12 02:20:07,732 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1190404592] [2023-11-12 02:20:07,733 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-12 02:20:07,734 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-12 02:20:07,855 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-12 02:20:08,109 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-12 02:20:08,110 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-12 02:20:08,110 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1190404592] [2023-11-12 02:20:08,111 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1190404592] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-12 02:20:08,111 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-12 02:20:08,112 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-12 02:20:08,113 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1507503394] [2023-11-12 02:20:08,114 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-12 02:20:08,119 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-12 02:20:08,120 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-12 02:20:08,120 INFO L85 PathProgramCache]: Analyzing trace with hash 1329563516, now seen corresponding path program 1 times [2023-11-12 02:20:08,120 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-12 02:20:08,121 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1736331574] [2023-11-12 02:20:08,121 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-12 02:20:08,121 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-12 02:20:08,156 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-12 02:20:08,208 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-12 02:20:08,209 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-12 02:20:08,209 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1736331574] [2023-11-12 02:20:08,209 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1736331574] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-12 02:20:08,210 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-12 02:20:08,210 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2023-11-12 02:20:08,210 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [84479915] [2023-11-12 02:20:08,210 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-12 02:20:08,212 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-12 02:20:08,213 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-12 02:20:08,245 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-12 02:20:08,246 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-12 02:20:08,251 INFO L87 Difference]: Start difference. First operand has 1387 states, 1386 states have (on average 1.5021645021645023) internal successors, (2082), 1386 states have internal predecessors, (2082), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand has 3 states, 3 states have (on average 42.666666666666664) internal successors, (128), 3 states have internal predecessors, (128), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-12 02:20:08,376 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-12 02:20:08,377 INFO L93 Difference]: Finished difference Result 1383 states and 2049 transitions. [2023-11-12 02:20:08,378 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1383 states and 2049 transitions. [2023-11-12 02:20:08,396 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1238 [2023-11-12 02:20:08,418 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1383 states to 1377 states and 2043 transitions. [2023-11-12 02:20:08,419 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1377 [2023-11-12 02:20:08,422 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1377 [2023-11-12 02:20:08,423 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1377 states and 2043 transitions. [2023-11-12 02:20:08,437 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-12 02:20:08,437 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1377 states and 2043 transitions. [2023-11-12 02:20:08,463 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1377 states and 2043 transitions. [2023-11-12 02:20:08,529 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1377 to 1377. [2023-11-12 02:20:08,533 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1377 states, 1377 states have (on average 1.4836601307189543) internal successors, (2043), 1376 states have internal predecessors, (2043), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-12 02:20:08,539 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1377 states to 1377 states and 2043 transitions. [2023-11-12 02:20:08,540 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1377 states and 2043 transitions. [2023-11-12 02:20:08,542 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-12 02:20:08,545 INFO L428 stractBuchiCegarLoop]: Abstraction has 1377 states and 2043 transitions. [2023-11-12 02:20:08,545 INFO L335 stractBuchiCegarLoop]: ======== Iteration 2 ============ [2023-11-12 02:20:08,546 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1377 states and 2043 transitions. [2023-11-12 02:20:08,556 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1238 [2023-11-12 02:20:08,556 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-12 02:20:08,556 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-12 02:20:08,560 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-12 02:20:08,560 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-12 02:20:08,561 INFO L748 eck$LassoCheckResult]: Stem: 3197#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~token~0 := 0;~local~0 := 0; 3198#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~12#1;havoc main_~__retres1~12#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1; 4074#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret30#1, start_simulation_#t~ret31#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 4075#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 4137#L731 assume 1 == ~m_i~0;~m_st~0 := 0; 4078#L731-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 4038#L736-1 assume !(1 == ~t2_i~0);~t2_st~0 := 2; 4039#L741-1 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 4067#L746-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 3136#L751-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 3137#L756-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 3242#L761-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 3487#L766-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 3413#L771-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 3138#L776-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 2797#L781-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 2798#L1036 assume !(0 == ~M_E~0); 2895#L1036-2 assume !(0 == ~T1_E~0); 3800#L1041-1 assume !(0 == ~T2_E~0); 3801#L1046-1 assume 0 == ~T3_E~0;~T3_E~0 := 1; 3172#L1051-1 assume !(0 == ~T4_E~0); 3173#L1056-1 assume !(0 == ~T5_E~0); 3929#L1061-1 assume !(0 == ~T6_E~0); 3067#L1066-1 assume !(0 == ~T7_E~0); 3068#L1071-1 assume !(0 == ~T8_E~0); 3911#L1076-1 assume !(0 == ~T9_E~0); 2957#L1081-1 assume !(0 == ~T10_E~0); 2958#L1086-1 assume 0 == ~E_M~0;~E_M~0 := 1; 3358#L1091-1 assume !(0 == ~E_1~0); 4086#L1096-1 assume !(0 == ~E_2~0); 4087#L1101-1 assume !(0 == ~E_3~0); 3426#L1106-1 assume !(0 == ~E_4~0); 3427#L1111-1 assume !(0 == ~E_5~0); 3591#L1116-1 assume !(0 == ~E_6~0); 3592#L1121-1 assume !(0 == ~E_7~0); 3417#L1126-1 assume 0 == ~E_8~0;~E_8~0 := 1; 3418#L1131-1 assume !(0 == ~E_9~0); 3693#L1136-1 assume !(0 == ~E_10~0); 3808#L1141-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 3957#L514 assume 1 == ~m_pc~0; 3922#L515 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 3435#L525 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 3436#is_master_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 4009#L1285 assume !(0 != activate_threads_~tmp~1#1); 4122#L1285-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 3086#L533 assume !(1 == ~t1_pc~0); 3087#L533-2 is_transmit1_triggered_~__retres1~1#1 := 0; 3606#L544 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 2852#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 2853#L1293 assume !(0 != activate_threads_~tmp___0~0#1); 3829#L1293-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 3830#L552 assume 1 == ~t2_pc~0; 3307#L553 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 3308#L563 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 3421#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 3422#L1301 assume !(0 != activate_threads_~tmp___1~0#1); 3453#L1301-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 3454#L571 assume 1 == ~t3_pc~0; 3646#L572 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 3647#L582 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 2795#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 2796#L1309 assume !(0 != activate_threads_~tmp___2~0#1); 3596#L1309-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 2881#L590 assume !(1 == ~t4_pc~0); 2882#L590-2 is_transmit4_triggered_~__retres1~4#1 := 0; 3654#L601 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 2975#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 2976#L1317 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 3857#L1317-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 3593#L609 assume 1 == ~t5_pc~0; 3594#L610 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 4119#L620 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 4011#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 4012#L1325 assume !(0 != activate_threads_~tmp___4~0#1); 3585#L1325-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 3586#L628 assume !(1 == ~t6_pc~0); 3518#L628-2 is_transmit6_triggered_~__retres1~6#1 := 0; 3517#L639 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 3395#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 3396#L1333 assume !(0 != activate_threads_~tmp___5~0#1); 3891#L1333-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 3892#L647 assume 1 == ~t7_pc~0; 3428#L648 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 3429#L658 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 4020#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 3433#L1341 assume !(0 != activate_threads_~tmp___6~0#1); 3434#L1341-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 4148#L666 assume !(1 == ~t8_pc~0); 3219#L666-2 is_transmit8_triggered_~__retres1~8#1 := 0; 3220#L677 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 3447#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 3618#L1349 assume !(0 != activate_threads_~tmp___7~0#1); 3356#L1349-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 3357#L685 assume 1 == ~t9_pc~0; 4127#L686 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 4028#L696 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 3481#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 3385#L1357 assume !(0 != activate_threads_~tmp___8~0#1); 3386#L1357-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 3771#L704 assume !(1 == ~t10_pc~0); 3375#L704-2 is_transmit10_triggered_~__retres1~10#1 := 0; 3374#L715 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 3636#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 2929#L1365 assume !(0 != activate_threads_~tmp___9~0#1); 2930#L1365-2 havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 3181#L1154 assume !(1 == ~M_E~0); 3879#L1154-2 assume !(1 == ~T1_E~0); 3155#L1159-1 assume !(1 == ~T2_E~0); 3156#L1164-1 assume !(1 == ~T3_E~0); 3615#L1169-1 assume !(1 == ~T4_E~0); 3482#L1174-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 3286#L1179-1 assume !(1 == ~T6_E~0); 3140#L1184-1 assume !(1 == ~T7_E~0); 3141#L1189-1 assume !(1 == ~T8_E~0); 3217#L1194-1 assume !(1 == ~T9_E~0); 3344#L1199-1 assume !(1 == ~T10_E~0); 3298#L1204-1 assume !(1 == ~E_M~0); 3299#L1209-1 assume !(1 == ~E_1~0); 3852#L1214-1 assume 1 == ~E_2~0;~E_2~0 := 2; 3853#L1219-1 assume !(1 == ~E_3~0); 4141#L1224-1 assume !(1 == ~E_4~0); 3640#L1229-1 assume !(1 == ~E_5~0); 3024#L1234-1 assume !(1 == ~E_6~0); 3025#L1239-1 assume !(1 == ~E_7~0); 3082#L1244-1 assume !(1 == ~E_8~0); 3083#L1249-1 assume !(1 == ~E_9~0); 3920#L1254-1 assume 1 == ~E_10~0;~E_10~0 := 2; 2924#L1259-1 assume { :end_inline_reset_delta_events } true; 2925#L1565-2 [2023-11-12 02:20:08,562 INFO L750 eck$LassoCheckResult]: Loop: 2925#L1565-2 assume !false; 3858#L1566 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 3624#L1011-1 assume !false; 3587#L862 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 3360#L794 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 3123#L851 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 3460#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 3152#L866 assume !(0 != eval_~tmp~0#1); 3154#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 3657#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 3658#L1036-3 assume 0 == ~M_E~0;~M_E~0 := 1; 3924#L1036-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 4103#L1041-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 3985#L1046-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 3986#L1051-3 assume !(0 == ~T4_E~0); 3925#L1056-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 3169#L1061-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 3170#L1066-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 3171#L1071-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 4105#L1076-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 2916#L1081-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 2917#L1086-3 assume 0 == ~E_M~0;~E_M~0 := 1; 2971#L1091-3 assume !(0 == ~E_1~0); 2972#L1096-3 assume 0 == ~E_2~0;~E_2~0 := 1; 4069#L1101-3 assume 0 == ~E_3~0;~E_3~0 := 1; 4070#L1106-3 assume 0 == ~E_4~0;~E_4~0 := 1; 4102#L1111-3 assume 0 == ~E_5~0;~E_5~0 := 1; 4061#L1116-3 assume 0 == ~E_6~0;~E_6~0 := 1; 3786#L1121-3 assume 0 == ~E_7~0;~E_7~0 := 1; 3787#L1126-3 assume 0 == ~E_8~0;~E_8~0 := 1; 4000#L1131-3 assume !(0 == ~E_9~0); 4001#L1136-3 assume 0 == ~E_10~0;~E_10~0 := 1; 4153#L1141-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 3789#L514-36 assume !(1 == ~m_pc~0); 3498#L514-38 is_master_triggered_~__retres1~0#1 := 0; 3333#L525-12 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 3334#is_master_triggered_returnLabel#13 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 3828#L1285-36 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 3226#L1285-38 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 3227#L533-36 assume 1 == ~t1_pc~0; 3507#L534-12 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 3603#L544-12 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 4051#is_transmit1_triggered_returnLabel#13 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 3866#L1293-36 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 3663#L1293-38 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 3664#L552-36 assume 1 == ~t2_pc~0; 3221#L553-12 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 3222#L563-12 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 3722#is_transmit2_triggered_returnLabel#13 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 3993#L1301-36 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 3193#L1301-38 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 3194#L571-36 assume 1 == ~t3_pc~0; 3581#L572-12 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 3284#L582-12 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 3285#is_transmit3_triggered_returnLabel#13 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 3477#L1309-36 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 3984#L1309-38 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 3253#L590-36 assume 1 == ~t4_pc~0; 3254#L591-12 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 3880#L601-12 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 3673#is_transmit4_triggered_returnLabel#13 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 3674#L1317-36 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 3963#L1317-38 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 3964#L609-36 assume 1 == ~t5_pc~0; 3841#L610-12 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 3666#L620-12 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 3667#is_transmit5_triggered_returnLabel#13 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 4008#L1325-36 assume !(0 != activate_threads_~tmp___4~0#1); 3750#L1325-38 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 3557#L628-36 assume 1 == ~t6_pc~0; 3405#L629-12 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 3406#L639-12 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 3456#is_transmit6_triggered_returnLabel#13 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 3457#L1333-36 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 3791#L1333-38 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 3792#L647-36 assume 1 == ~t7_pc~0; 3715#L648-12 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 2943#L658-12 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 2944#is_transmit7_triggered_returnLabel#13 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 2961#L1341-36 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 2962#L1341-38 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 3881#L666-36 assume 1 == ~t8_pc~0; 3149#L667-12 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 3150#L677-12 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 3779#is_transmit8_triggered_returnLabel#13 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 3780#L1349-36 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 3304#L1349-38 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 3305#L685-36 assume 1 == ~t9_pc~0; 3766#L686-12 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 3056#L696-12 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 3511#is_transmit9_triggered_returnLabel#13 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 3512#L1357-36 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 3444#L1357-38 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 3445#L704-36 assume 1 == ~t10_pc~0; 3043#L705-12 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 3044#L715-12 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 3365#is_transmit10_triggered_returnLabel#13 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 3366#L1365-36 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 3071#L1365-38 havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 3072#L1154-3 assume 1 == ~M_E~0;~M_E~0 := 2; 4055#L1154-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 3938#L1159-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 3939#L1164-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 4116#L1169-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 3371#L1174-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 3372#L1179-3 assume !(1 == ~T6_E~0); 4030#L1184-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 2945#L1189-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 2946#L1194-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 3315#L1199-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 3316#L1204-3 assume 1 == ~E_M~0;~E_M~0 := 2; 3635#L1209-3 assume 1 == ~E_1~0;~E_1~0 := 2; 2813#L1214-3 assume 1 == ~E_2~0;~E_2~0 := 2; 2814#L1219-3 assume !(1 == ~E_3~0); 3835#L1224-3 assume 1 == ~E_4~0;~E_4~0 := 2; 3836#L1229-3 assume 1 == ~E_5~0;~E_5~0 := 2; 3856#L1234-3 assume 1 == ~E_6~0;~E_6~0 := 2; 3084#L1239-3 assume 1 == ~E_7~0;~E_7~0 := 2; 3085#L1244-3 assume 1 == ~E_8~0;~E_8~0 := 2; 3686#L1249-3 assume 1 == ~E_9~0;~E_9~0 := 2; 4062#L1254-3 assume 1 == ~E_10~0;~E_10~0 := 2; 3839#L1259-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 3840#L794-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 2893#L851-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 3353#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret30#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret30#1;havoc start_simulation_#t~ret30#1; 3354#L1584 assume !(0 == start_simulation_~tmp~3#1); 3797#L1584-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret29#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 3098#L794-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 2793#L851-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 2845#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret29#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret29#1;havoc stop_simulation_#t~ret29#1; 2846#L1539 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 3423#L1546 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 3679#stop_simulation_returnLabel#1 start_simulation_#t~ret31#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret29#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret31#1;havoc start_simulation_#t~ret31#1; 3680#L1597 assume !(0 != start_simulation_~tmp___0~1#1); 2925#L1565-2 [2023-11-12 02:20:08,563 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-12 02:20:08,564 INFO L85 PathProgramCache]: Analyzing trace with hash -825627459, now seen corresponding path program 1 times [2023-11-12 02:20:08,564 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-12 02:20:08,564 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [458576341] [2023-11-12 02:20:08,564 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-12 02:20:08,565 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-12 02:20:08,586 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-12 02:20:08,651 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-12 02:20:08,651 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-12 02:20:08,652 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [458576341] [2023-11-12 02:20:08,652 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [458576341] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-12 02:20:08,652 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-12 02:20:08,652 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-12 02:20:08,652 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [141098206] [2023-11-12 02:20:08,653 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-12 02:20:08,653 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-12 02:20:08,654 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-12 02:20:08,654 INFO L85 PathProgramCache]: Analyzing trace with hash 642940402, now seen corresponding path program 1 times [2023-11-12 02:20:08,654 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-12 02:20:08,654 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1040488823] [2023-11-12 02:20:08,654 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-12 02:20:08,655 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-12 02:20:08,698 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-12 02:20:08,848 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-12 02:20:08,848 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-12 02:20:08,849 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1040488823] [2023-11-12 02:20:08,849 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1040488823] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-12 02:20:08,849 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-12 02:20:08,849 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-12 02:20:08,849 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1414161667] [2023-11-12 02:20:08,850 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-12 02:20:08,850 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-12 02:20:08,850 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-12 02:20:08,851 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-12 02:20:08,851 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-12 02:20:08,851 INFO L87 Difference]: Start difference. First operand 1377 states and 2043 transitions. cyclomatic complexity: 667 Second operand has 3 states, 3 states have (on average 42.666666666666664) internal successors, (128), 3 states have internal predecessors, (128), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-12 02:20:08,902 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-12 02:20:08,902 INFO L93 Difference]: Finished difference Result 1377 states and 2042 transitions. [2023-11-12 02:20:08,902 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1377 states and 2042 transitions. [2023-11-12 02:20:08,915 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1238 [2023-11-12 02:20:08,927 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1377 states to 1377 states and 2042 transitions. [2023-11-12 02:20:08,927 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1377 [2023-11-12 02:20:08,930 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1377 [2023-11-12 02:20:08,931 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1377 states and 2042 transitions. [2023-11-12 02:20:08,934 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-12 02:20:08,934 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1377 states and 2042 transitions. [2023-11-12 02:20:08,937 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1377 states and 2042 transitions. [2023-11-12 02:20:08,985 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1377 to 1377. [2023-11-12 02:20:08,990 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1377 states, 1377 states have (on average 1.4829339143064633) internal successors, (2042), 1376 states have internal predecessors, (2042), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-12 02:20:08,998 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1377 states to 1377 states and 2042 transitions. [2023-11-12 02:20:09,001 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1377 states and 2042 transitions. [2023-11-12 02:20:09,003 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-12 02:20:09,005 INFO L428 stractBuchiCegarLoop]: Abstraction has 1377 states and 2042 transitions. [2023-11-12 02:20:09,006 INFO L335 stractBuchiCegarLoop]: ======== Iteration 3 ============ [2023-11-12 02:20:09,006 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1377 states and 2042 transitions. [2023-11-12 02:20:09,017 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1238 [2023-11-12 02:20:09,019 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-12 02:20:09,019 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-12 02:20:09,024 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-12 02:20:09,029 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-12 02:20:09,032 INFO L748 eck$LassoCheckResult]: Stem: 5958#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~token~0 := 0;~local~0 := 0; 5959#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~12#1;havoc main_~__retres1~12#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1; 6835#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret30#1, start_simulation_#t~ret31#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 6836#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 6898#L731 assume 1 == ~m_i~0;~m_st~0 := 0; 6839#L731-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 6799#L736-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 6800#L741-1 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 6828#L746-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 5895#L751-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 5896#L756-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 6003#L761-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 6248#L766-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 6174#L771-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 5897#L776-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 5558#L781-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 5559#L1036 assume !(0 == ~M_E~0); 5656#L1036-2 assume !(0 == ~T1_E~0); 6561#L1041-1 assume !(0 == ~T2_E~0); 6562#L1046-1 assume 0 == ~T3_E~0;~T3_E~0 := 1; 5933#L1051-1 assume !(0 == ~T4_E~0); 5934#L1056-1 assume !(0 == ~T5_E~0); 6690#L1061-1 assume !(0 == ~T6_E~0); 5828#L1066-1 assume !(0 == ~T7_E~0); 5829#L1071-1 assume !(0 == ~T8_E~0); 6672#L1076-1 assume !(0 == ~T9_E~0); 5718#L1081-1 assume !(0 == ~T10_E~0); 5719#L1086-1 assume 0 == ~E_M~0;~E_M~0 := 1; 6119#L1091-1 assume !(0 == ~E_1~0); 6846#L1096-1 assume !(0 == ~E_2~0); 6847#L1101-1 assume !(0 == ~E_3~0); 6187#L1106-1 assume !(0 == ~E_4~0); 6188#L1111-1 assume !(0 == ~E_5~0); 6352#L1116-1 assume !(0 == ~E_6~0); 6353#L1121-1 assume !(0 == ~E_7~0); 6178#L1126-1 assume 0 == ~E_8~0;~E_8~0 := 1; 6179#L1131-1 assume !(0 == ~E_9~0); 6454#L1136-1 assume !(0 == ~E_10~0); 6569#L1141-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 6718#L514 assume 1 == ~m_pc~0; 6683#L515 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 6196#L525 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 6197#is_master_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 6770#L1285 assume !(0 != activate_threads_~tmp~1#1); 6882#L1285-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 5847#L533 assume !(1 == ~t1_pc~0); 5848#L533-2 is_transmit1_triggered_~__retres1~1#1 := 0; 6367#L544 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 5611#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 5612#L1293 assume !(0 != activate_threads_~tmp___0~0#1); 6590#L1293-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 6591#L552 assume 1 == ~t2_pc~0; 6067#L553 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 6068#L563 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 6182#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 6183#L1301 assume !(0 != activate_threads_~tmp___1~0#1); 6209#L1301-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 6210#L571 assume 1 == ~t3_pc~0; 6405#L572 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 6406#L582 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 5556#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 5557#L1309 assume !(0 != activate_threads_~tmp___2~0#1); 6357#L1309-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 5642#L590 assume !(1 == ~t4_pc~0); 5643#L590-2 is_transmit4_triggered_~__retres1~4#1 := 0; 6415#L601 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 5736#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 5737#L1317 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 6617#L1317-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 6354#L609 assume 1 == ~t5_pc~0; 6355#L610 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 6880#L620 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 6772#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 6773#L1325 assume !(0 != activate_threads_~tmp___4~0#1); 6346#L1325-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 6347#L628 assume !(1 == ~t6_pc~0); 6279#L628-2 is_transmit6_triggered_~__retres1~6#1 := 0; 6278#L639 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 6155#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 6156#L1333 assume !(0 != activate_threads_~tmp___5~0#1); 6652#L1333-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 6653#L647 assume 1 == ~t7_pc~0; 6189#L648 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 6190#L658 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 6781#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 6192#L1341 assume !(0 != activate_threads_~tmp___6~0#1); 6193#L1341-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 6909#L666 assume !(1 == ~t8_pc~0); 5980#L666-2 is_transmit8_triggered_~__retres1~8#1 := 0; 5981#L677 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 6208#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 6378#L1349 assume !(0 != activate_threads_~tmp___7~0#1); 6116#L1349-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 6117#L685 assume 1 == ~t9_pc~0; 6888#L686 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 6789#L696 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 6242#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 6146#L1357 assume !(0 != activate_threads_~tmp___8~0#1); 6147#L1357-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 6532#L704 assume !(1 == ~t10_pc~0); 6136#L704-2 is_transmit10_triggered_~__retres1~10#1 := 0; 6135#L715 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 6396#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 5690#L1365 assume !(0 != activate_threads_~tmp___9~0#1); 5691#L1365-2 havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 5942#L1154 assume !(1 == ~M_E~0); 6640#L1154-2 assume !(1 == ~T1_E~0); 5916#L1159-1 assume !(1 == ~T2_E~0); 5917#L1164-1 assume !(1 == ~T3_E~0); 6376#L1169-1 assume !(1 == ~T4_E~0); 6243#L1174-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 6045#L1179-1 assume !(1 == ~T6_E~0); 5901#L1184-1 assume !(1 == ~T7_E~0); 5902#L1189-1 assume !(1 == ~T8_E~0); 5978#L1194-1 assume !(1 == ~T9_E~0); 6103#L1199-1 assume !(1 == ~T10_E~0); 6057#L1204-1 assume !(1 == ~E_M~0); 6058#L1209-1 assume !(1 == ~E_1~0); 6611#L1214-1 assume 1 == ~E_2~0;~E_2~0 := 2; 6612#L1219-1 assume !(1 == ~E_3~0); 6902#L1224-1 assume !(1 == ~E_4~0); 6400#L1229-1 assume !(1 == ~E_5~0); 5785#L1234-1 assume !(1 == ~E_6~0); 5786#L1239-1 assume !(1 == ~E_7~0); 5843#L1244-1 assume !(1 == ~E_8~0); 5844#L1249-1 assume !(1 == ~E_9~0); 6681#L1254-1 assume 1 == ~E_10~0;~E_10~0 := 2; 5685#L1259-1 assume { :end_inline_reset_delta_events } true; 5686#L1565-2 [2023-11-12 02:20:09,033 INFO L750 eck$LassoCheckResult]: Loop: 5686#L1565-2 assume !false; 6619#L1566 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 6384#L1011-1 assume !false; 6348#L862 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 6121#L794 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 5884#L851 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 6221#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 5908#L866 assume !(0 != eval_~tmp~0#1); 5910#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 6417#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 6418#L1036-3 assume 0 == ~M_E~0;~M_E~0 := 1; 6685#L1036-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 6864#L1041-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 6746#L1046-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 6747#L1051-3 assume !(0 == ~T4_E~0); 6686#L1056-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 5930#L1061-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 5931#L1066-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 5932#L1071-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 6866#L1076-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 5677#L1081-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 5678#L1086-3 assume 0 == ~E_M~0;~E_M~0 := 1; 5728#L1091-3 assume !(0 == ~E_1~0); 5729#L1096-3 assume 0 == ~E_2~0;~E_2~0 := 1; 6830#L1101-3 assume 0 == ~E_3~0;~E_3~0 := 1; 6831#L1106-3 assume 0 == ~E_4~0;~E_4~0 := 1; 6863#L1111-3 assume 0 == ~E_5~0;~E_5~0 := 1; 6822#L1116-3 assume 0 == ~E_6~0;~E_6~0 := 1; 6547#L1121-3 assume 0 == ~E_7~0;~E_7~0 := 1; 6548#L1126-3 assume 0 == ~E_8~0;~E_8~0 := 1; 6761#L1131-3 assume !(0 == ~E_9~0); 6762#L1136-3 assume 0 == ~E_10~0;~E_10~0 := 1; 6914#L1141-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 6550#L514-36 assume !(1 == ~m_pc~0); 6259#L514-38 is_master_triggered_~__retres1~0#1 := 0; 6094#L525-12 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 6095#is_master_triggered_returnLabel#13 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 6589#L1285-36 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 5987#L1285-38 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 5988#L533-36 assume 1 == ~t1_pc~0; 6268#L534-12 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 6361#L544-12 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 6812#is_transmit1_triggered_returnLabel#13 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 6627#L1293-36 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 6424#L1293-38 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 6425#L552-36 assume !(1 == ~t2_pc~0); 5984#L552-38 is_transmit2_triggered_~__retres1~2#1 := 0; 5983#L563-12 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 6483#is_transmit2_triggered_returnLabel#13 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 6754#L1301-36 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 5954#L1301-38 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 5955#L571-36 assume 1 == ~t3_pc~0; 6342#L572-12 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 6046#L582-12 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 6047#is_transmit3_triggered_returnLabel#13 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 6238#L1309-36 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 6745#L1309-38 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 6017#L590-36 assume 1 == ~t4_pc~0; 6018#L591-12 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 6641#L601-12 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 6434#is_transmit4_triggered_returnLabel#13 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 6435#L1317-36 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 6724#L1317-38 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 6725#L609-36 assume 1 == ~t5_pc~0; 6602#L610-12 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 6427#L620-12 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 6428#is_transmit5_triggered_returnLabel#13 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 6769#L1325-36 assume !(0 != activate_threads_~tmp___4~0#1); 6511#L1325-38 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 6318#L628-36 assume 1 == ~t6_pc~0; 6166#L629-12 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 6167#L639-12 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 6217#is_transmit6_triggered_returnLabel#13 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 6218#L1333-36 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 6552#L1333-38 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 6553#L647-36 assume 1 == ~t7_pc~0; 6476#L648-12 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 5704#L658-12 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 5705#is_transmit7_triggered_returnLabel#13 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 5722#L1341-36 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 5723#L1341-38 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 6642#L666-36 assume 1 == ~t8_pc~0; 5913#L667-12 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 5914#L677-12 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 6540#is_transmit8_triggered_returnLabel#13 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 6541#L1349-36 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 6065#L1349-38 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 6066#L685-36 assume !(1 == ~t9_pc~0); 5816#L685-38 is_transmit9_triggered_~__retres1~9#1 := 0; 5817#L696-12 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 6272#is_transmit9_triggered_returnLabel#13 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 6273#L1357-36 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 6205#L1357-38 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 6206#L704-36 assume 1 == ~t10_pc~0; 5804#L705-12 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 5805#L715-12 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 6126#is_transmit10_triggered_returnLabel#13 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 6127#L1365-36 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 5832#L1365-38 havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 5833#L1154-3 assume 1 == ~M_E~0;~M_E~0 := 2; 6816#L1154-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 6699#L1159-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 6700#L1164-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 6877#L1169-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 6132#L1174-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 6133#L1179-3 assume !(1 == ~T6_E~0); 6791#L1184-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 5706#L1189-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 5707#L1194-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 6076#L1199-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 6077#L1204-3 assume 1 == ~E_M~0;~E_M~0 := 2; 6397#L1209-3 assume 1 == ~E_1~0;~E_1~0 := 2; 5574#L1214-3 assume 1 == ~E_2~0;~E_2~0 := 2; 5575#L1219-3 assume !(1 == ~E_3~0); 6596#L1224-3 assume 1 == ~E_4~0;~E_4~0 := 2; 6597#L1229-3 assume 1 == ~E_5~0;~E_5~0 := 2; 6618#L1234-3 assume 1 == ~E_6~0;~E_6~0 := 2; 5845#L1239-3 assume 1 == ~E_7~0;~E_7~0 := 2; 5846#L1244-3 assume 1 == ~E_8~0;~E_8~0 := 2; 6451#L1249-3 assume 1 == ~E_9~0;~E_9~0 := 2; 6823#L1254-3 assume 1 == ~E_10~0;~E_10~0 := 2; 6600#L1259-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 6601#L794-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 5654#L851-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 6114#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret30#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret30#1;havoc start_simulation_#t~ret30#1; 6115#L1584 assume !(0 == start_simulation_~tmp~3#1); 6558#L1584-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret29#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 5859#L794-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 5554#L851-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 5606#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret29#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret29#1;havoc stop_simulation_#t~ret29#1; 5607#L1539 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 6185#L1546 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 6440#stop_simulation_returnLabel#1 start_simulation_#t~ret31#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret29#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret31#1;havoc start_simulation_#t~ret31#1; 6441#L1597 assume !(0 != start_simulation_~tmp___0~1#1); 5686#L1565-2 [2023-11-12 02:20:09,034 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-12 02:20:09,034 INFO L85 PathProgramCache]: Analyzing trace with hash 1224781439, now seen corresponding path program 1 times [2023-11-12 02:20:09,035 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-12 02:20:09,035 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1104240076] [2023-11-12 02:20:09,036 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-12 02:20:09,036 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-12 02:20:09,066 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-12 02:20:09,146 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-12 02:20:09,146 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-12 02:20:09,146 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1104240076] [2023-11-12 02:20:09,146 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1104240076] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-12 02:20:09,147 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-12 02:20:09,147 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-12 02:20:09,147 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [595323088] [2023-11-12 02:20:09,147 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-12 02:20:09,148 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-12 02:20:09,148 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-12 02:20:09,148 INFO L85 PathProgramCache]: Analyzing trace with hash 1657784244, now seen corresponding path program 1 times [2023-11-12 02:20:09,149 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-12 02:20:09,149 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1549791195] [2023-11-12 02:20:09,149 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-12 02:20:09,149 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-12 02:20:09,185 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-12 02:20:09,278 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-12 02:20:09,279 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-12 02:20:09,279 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1549791195] [2023-11-12 02:20:09,280 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1549791195] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-12 02:20:09,280 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-12 02:20:09,280 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-12 02:20:09,280 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [608105479] [2023-11-12 02:20:09,280 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-12 02:20:09,282 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-12 02:20:09,282 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-12 02:20:09,283 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-12 02:20:09,283 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-12 02:20:09,284 INFO L87 Difference]: Start difference. First operand 1377 states and 2042 transitions. cyclomatic complexity: 666 Second operand has 3 states, 3 states have (on average 42.666666666666664) internal successors, (128), 3 states have internal predecessors, (128), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-12 02:20:09,325 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-12 02:20:09,325 INFO L93 Difference]: Finished difference Result 1377 states and 2041 transitions. [2023-11-12 02:20:09,326 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1377 states and 2041 transitions. [2023-11-12 02:20:09,337 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1238 [2023-11-12 02:20:09,349 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1377 states to 1377 states and 2041 transitions. [2023-11-12 02:20:09,350 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1377 [2023-11-12 02:20:09,351 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1377 [2023-11-12 02:20:09,352 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1377 states and 2041 transitions. [2023-11-12 02:20:09,354 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-12 02:20:09,354 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1377 states and 2041 transitions. [2023-11-12 02:20:09,357 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1377 states and 2041 transitions. [2023-11-12 02:20:09,378 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1377 to 1377. [2023-11-12 02:20:09,382 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1377 states, 1377 states have (on average 1.4822076978939724) internal successors, (2041), 1376 states have internal predecessors, (2041), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-12 02:20:09,388 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1377 states to 1377 states and 2041 transitions. [2023-11-12 02:20:09,389 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1377 states and 2041 transitions. [2023-11-12 02:20:09,389 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-12 02:20:09,391 INFO L428 stractBuchiCegarLoop]: Abstraction has 1377 states and 2041 transitions. [2023-11-12 02:20:09,392 INFO L335 stractBuchiCegarLoop]: ======== Iteration 4 ============ [2023-11-12 02:20:09,392 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1377 states and 2041 transitions. [2023-11-12 02:20:09,401 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1238 [2023-11-12 02:20:09,402 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-12 02:20:09,402 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-12 02:20:09,406 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-12 02:20:09,406 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-12 02:20:09,407 INFO L748 eck$LassoCheckResult]: Stem: 8719#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~token~0 := 0;~local~0 := 0; 8720#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~12#1;havoc main_~__retres1~12#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1; 9596#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret30#1, start_simulation_#t~ret31#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 9597#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 9659#L731 assume 1 == ~m_i~0;~m_st~0 := 0; 9600#L731-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 9560#L736-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 9561#L741-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 9589#L746-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 8656#L751-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 8657#L756-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 8764#L761-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 9009#L766-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 8935#L771-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 8658#L776-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 8319#L781-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 8320#L1036 assume !(0 == ~M_E~0); 8417#L1036-2 assume !(0 == ~T1_E~0); 9322#L1041-1 assume !(0 == ~T2_E~0); 9323#L1046-1 assume 0 == ~T3_E~0;~T3_E~0 := 1; 8694#L1051-1 assume !(0 == ~T4_E~0); 8695#L1056-1 assume !(0 == ~T5_E~0); 9451#L1061-1 assume !(0 == ~T6_E~0); 8589#L1066-1 assume !(0 == ~T7_E~0); 8590#L1071-1 assume !(0 == ~T8_E~0); 9433#L1076-1 assume !(0 == ~T9_E~0); 8479#L1081-1 assume !(0 == ~T10_E~0); 8480#L1086-1 assume 0 == ~E_M~0;~E_M~0 := 1; 8880#L1091-1 assume !(0 == ~E_1~0); 9607#L1096-1 assume !(0 == ~E_2~0); 9608#L1101-1 assume !(0 == ~E_3~0); 8948#L1106-1 assume !(0 == ~E_4~0); 8949#L1111-1 assume !(0 == ~E_5~0); 9113#L1116-1 assume !(0 == ~E_6~0); 9114#L1121-1 assume !(0 == ~E_7~0); 8939#L1126-1 assume 0 == ~E_8~0;~E_8~0 := 1; 8940#L1131-1 assume !(0 == ~E_9~0); 9215#L1136-1 assume !(0 == ~E_10~0); 9330#L1141-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 9479#L514 assume 1 == ~m_pc~0; 9444#L515 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 8957#L525 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 8958#is_master_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 9531#L1285 assume !(0 != activate_threads_~tmp~1#1); 9643#L1285-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 8608#L533 assume !(1 == ~t1_pc~0); 8609#L533-2 is_transmit1_triggered_~__retres1~1#1 := 0; 9128#L544 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 8372#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 8373#L1293 assume !(0 != activate_threads_~tmp___0~0#1); 9351#L1293-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 9352#L552 assume 1 == ~t2_pc~0; 8828#L553 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 8829#L563 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 8943#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 8944#L1301 assume !(0 != activate_threads_~tmp___1~0#1); 8970#L1301-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 8971#L571 assume 1 == ~t3_pc~0; 9166#L572 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 9167#L582 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 8317#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 8318#L1309 assume !(0 != activate_threads_~tmp___2~0#1); 9118#L1309-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 8403#L590 assume !(1 == ~t4_pc~0); 8404#L590-2 is_transmit4_triggered_~__retres1~4#1 := 0; 9176#L601 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 8497#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 8498#L1317 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 9378#L1317-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 9115#L609 assume 1 == ~t5_pc~0; 9116#L610 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 9641#L620 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 9533#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 9534#L1325 assume !(0 != activate_threads_~tmp___4~0#1); 9107#L1325-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 9108#L628 assume !(1 == ~t6_pc~0); 9040#L628-2 is_transmit6_triggered_~__retres1~6#1 := 0; 9039#L639 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 8916#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 8917#L1333 assume !(0 != activate_threads_~tmp___5~0#1); 9413#L1333-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 9414#L647 assume 1 == ~t7_pc~0; 8950#L648 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 8951#L658 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 9542#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 8953#L1341 assume !(0 != activate_threads_~tmp___6~0#1); 8954#L1341-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 9670#L666 assume !(1 == ~t8_pc~0); 8741#L666-2 is_transmit8_triggered_~__retres1~8#1 := 0; 8742#L677 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 8969#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 9139#L1349 assume !(0 != activate_threads_~tmp___7~0#1); 8877#L1349-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 8878#L685 assume 1 == ~t9_pc~0; 9649#L686 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 9550#L696 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 9003#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 8907#L1357 assume !(0 != activate_threads_~tmp___8~0#1); 8908#L1357-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 9293#L704 assume !(1 == ~t10_pc~0); 8897#L704-2 is_transmit10_triggered_~__retres1~10#1 := 0; 8896#L715 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 9157#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 8451#L1365 assume !(0 != activate_threads_~tmp___9~0#1); 8452#L1365-2 havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 8703#L1154 assume !(1 == ~M_E~0); 9401#L1154-2 assume !(1 == ~T1_E~0); 8677#L1159-1 assume !(1 == ~T2_E~0); 8678#L1164-1 assume !(1 == ~T3_E~0); 9137#L1169-1 assume !(1 == ~T4_E~0); 9004#L1174-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 8806#L1179-1 assume !(1 == ~T6_E~0); 8662#L1184-1 assume !(1 == ~T7_E~0); 8663#L1189-1 assume !(1 == ~T8_E~0); 8739#L1194-1 assume !(1 == ~T9_E~0); 8864#L1199-1 assume !(1 == ~T10_E~0); 8818#L1204-1 assume !(1 == ~E_M~0); 8819#L1209-1 assume !(1 == ~E_1~0); 9372#L1214-1 assume 1 == ~E_2~0;~E_2~0 := 2; 9373#L1219-1 assume !(1 == ~E_3~0); 9663#L1224-1 assume !(1 == ~E_4~0); 9161#L1229-1 assume !(1 == ~E_5~0); 8546#L1234-1 assume !(1 == ~E_6~0); 8547#L1239-1 assume !(1 == ~E_7~0); 8604#L1244-1 assume !(1 == ~E_8~0); 8605#L1249-1 assume !(1 == ~E_9~0); 9442#L1254-1 assume 1 == ~E_10~0;~E_10~0 := 2; 8446#L1259-1 assume { :end_inline_reset_delta_events } true; 8447#L1565-2 [2023-11-12 02:20:09,408 INFO L750 eck$LassoCheckResult]: Loop: 8447#L1565-2 assume !false; 9380#L1566 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 9146#L1011-1 assume !false; 9109#L862 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 8882#L794 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 8645#L851 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 8982#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 8669#L866 assume !(0 != eval_~tmp~0#1); 8671#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 9178#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 9179#L1036-3 assume 0 == ~M_E~0;~M_E~0 := 1; 9446#L1036-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 9625#L1041-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 9507#L1046-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 9508#L1051-3 assume !(0 == ~T4_E~0); 9447#L1056-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 8691#L1061-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 8692#L1066-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 8693#L1071-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 9627#L1076-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 8438#L1081-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 8439#L1086-3 assume 0 == ~E_M~0;~E_M~0 := 1; 8489#L1091-3 assume !(0 == ~E_1~0); 8490#L1096-3 assume 0 == ~E_2~0;~E_2~0 := 1; 9591#L1101-3 assume 0 == ~E_3~0;~E_3~0 := 1; 9592#L1106-3 assume 0 == ~E_4~0;~E_4~0 := 1; 9624#L1111-3 assume 0 == ~E_5~0;~E_5~0 := 1; 9583#L1116-3 assume 0 == ~E_6~0;~E_6~0 := 1; 9308#L1121-3 assume 0 == ~E_7~0;~E_7~0 := 1; 9309#L1126-3 assume 0 == ~E_8~0;~E_8~0 := 1; 9522#L1131-3 assume !(0 == ~E_9~0); 9523#L1136-3 assume 0 == ~E_10~0;~E_10~0 := 1; 9675#L1141-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 9311#L514-36 assume 1 == ~m_pc~0; 9312#L515-12 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 8855#L525-12 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 8856#is_master_triggered_returnLabel#13 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 9350#L1285-36 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 8748#L1285-38 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 8749#L533-36 assume 1 == ~t1_pc~0; 9029#L534-12 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 9122#L544-12 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 9573#is_transmit1_triggered_returnLabel#13 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 9388#L1293-36 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 9185#L1293-38 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 9186#L552-36 assume 1 == ~t2_pc~0; 8743#L553-12 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 8744#L563-12 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 9244#is_transmit2_triggered_returnLabel#13 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 9515#L1301-36 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 8715#L1301-38 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 8716#L571-36 assume !(1 == ~t3_pc~0); 9104#L571-38 is_transmit3_triggered_~__retres1~3#1 := 0; 8807#L582-12 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 8808#is_transmit3_triggered_returnLabel#13 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 8999#L1309-36 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 9506#L1309-38 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 8778#L590-36 assume 1 == ~t4_pc~0; 8779#L591-12 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 9402#L601-12 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 9196#is_transmit4_triggered_returnLabel#13 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 9197#L1317-36 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 9485#L1317-38 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 9486#L609-36 assume 1 == ~t5_pc~0; 9363#L610-12 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 9188#L620-12 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 9189#is_transmit5_triggered_returnLabel#13 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 9530#L1325-36 assume !(0 != activate_threads_~tmp___4~0#1); 9272#L1325-38 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 9079#L628-36 assume !(1 == ~t6_pc~0); 8929#L628-38 is_transmit6_triggered_~__retres1~6#1 := 0; 8928#L639-12 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 8978#is_transmit6_triggered_returnLabel#13 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 8979#L1333-36 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 9313#L1333-38 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 9314#L647-36 assume 1 == ~t7_pc~0; 9237#L648-12 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 8465#L658-12 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 8466#is_transmit7_triggered_returnLabel#13 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 8483#L1341-36 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 8484#L1341-38 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 9403#L666-36 assume 1 == ~t8_pc~0; 8674#L667-12 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 8675#L677-12 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 9301#is_transmit8_triggered_returnLabel#13 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 9302#L1349-36 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 8826#L1349-38 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 8827#L685-36 assume !(1 == ~t9_pc~0); 8577#L685-38 is_transmit9_triggered_~__retres1~9#1 := 0; 8578#L696-12 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 9033#is_transmit9_triggered_returnLabel#13 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 9034#L1357-36 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 8966#L1357-38 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 8967#L704-36 assume 1 == ~t10_pc~0; 8565#L705-12 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 8566#L715-12 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 8887#is_transmit10_triggered_returnLabel#13 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 8888#L1365-36 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 8593#L1365-38 havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 8594#L1154-3 assume 1 == ~M_E~0;~M_E~0 := 2; 9577#L1154-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 9460#L1159-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 9461#L1164-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 9638#L1169-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 8893#L1174-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 8894#L1179-3 assume !(1 == ~T6_E~0); 9552#L1184-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 8467#L1189-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 8468#L1194-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 8837#L1199-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 8838#L1204-3 assume 1 == ~E_M~0;~E_M~0 := 2; 9158#L1209-3 assume 1 == ~E_1~0;~E_1~0 := 2; 8338#L1214-3 assume 1 == ~E_2~0;~E_2~0 := 2; 8339#L1219-3 assume !(1 == ~E_3~0); 9357#L1224-3 assume 1 == ~E_4~0;~E_4~0 := 2; 9358#L1229-3 assume 1 == ~E_5~0;~E_5~0 := 2; 9379#L1234-3 assume 1 == ~E_6~0;~E_6~0 := 2; 8606#L1239-3 assume 1 == ~E_7~0;~E_7~0 := 2; 8607#L1244-3 assume 1 == ~E_8~0;~E_8~0 := 2; 9212#L1249-3 assume 1 == ~E_9~0;~E_9~0 := 2; 9584#L1254-3 assume 1 == ~E_10~0;~E_10~0 := 2; 9361#L1259-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 9362#L794-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 8415#L851-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 8875#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret30#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret30#1;havoc start_simulation_#t~ret30#1; 8876#L1584 assume !(0 == start_simulation_~tmp~3#1); 9319#L1584-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret29#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 8620#L794-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 8315#L851-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 8367#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret29#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret29#1;havoc stop_simulation_#t~ret29#1; 8368#L1539 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 8946#L1546 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 9201#stop_simulation_returnLabel#1 start_simulation_#t~ret31#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret29#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret31#1;havoc start_simulation_#t~ret31#1; 9202#L1597 assume !(0 != start_simulation_~tmp___0~1#1); 8447#L1565-2 [2023-11-12 02:20:09,411 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-12 02:20:09,411 INFO L85 PathProgramCache]: Analyzing trace with hash 736734333, now seen corresponding path program 1 times [2023-11-12 02:20:09,411 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-12 02:20:09,411 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [809241044] [2023-11-12 02:20:09,412 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-12 02:20:09,412 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-12 02:20:09,429 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-12 02:20:09,486 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-12 02:20:09,487 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-12 02:20:09,487 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [809241044] [2023-11-12 02:20:09,488 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [809241044] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-12 02:20:09,488 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-12 02:20:09,488 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-12 02:20:09,489 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [366027402] [2023-11-12 02:20:09,489 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-12 02:20:09,490 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-12 02:20:09,490 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-12 02:20:09,490 INFO L85 PathProgramCache]: Analyzing trace with hash -1243014924, now seen corresponding path program 1 times [2023-11-12 02:20:09,491 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-12 02:20:09,495 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [889393626] [2023-11-12 02:20:09,495 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-12 02:20:09,496 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-12 02:20:09,540 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-12 02:20:09,610 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-12 02:20:09,611 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-12 02:20:09,612 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [889393626] [2023-11-12 02:20:09,612 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [889393626] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-12 02:20:09,612 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-12 02:20:09,612 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-12 02:20:09,612 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1705395767] [2023-11-12 02:20:09,613 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-12 02:20:09,613 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-12 02:20:09,614 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-12 02:20:09,614 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-12 02:20:09,614 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-12 02:20:09,614 INFO L87 Difference]: Start difference. First operand 1377 states and 2041 transitions. cyclomatic complexity: 665 Second operand has 3 states, 3 states have (on average 42.666666666666664) internal successors, (128), 3 states have internal predecessors, (128), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-12 02:20:09,647 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-12 02:20:09,647 INFO L93 Difference]: Finished difference Result 1377 states and 2040 transitions. [2023-11-12 02:20:09,647 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1377 states and 2040 transitions. [2023-11-12 02:20:09,659 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1238 [2023-11-12 02:20:09,671 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1377 states to 1377 states and 2040 transitions. [2023-11-12 02:20:09,671 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1377 [2023-11-12 02:20:09,673 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1377 [2023-11-12 02:20:09,673 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1377 states and 2040 transitions. [2023-11-12 02:20:09,675 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-12 02:20:09,675 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1377 states and 2040 transitions. [2023-11-12 02:20:09,678 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1377 states and 2040 transitions. [2023-11-12 02:20:09,698 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1377 to 1377. [2023-11-12 02:20:09,702 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1377 states, 1377 states have (on average 1.4814814814814814) internal successors, (2040), 1376 states have internal predecessors, (2040), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-12 02:20:09,707 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1377 states to 1377 states and 2040 transitions. [2023-11-12 02:20:09,707 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1377 states and 2040 transitions. [2023-11-12 02:20:09,708 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-12 02:20:09,711 INFO L428 stractBuchiCegarLoop]: Abstraction has 1377 states and 2040 transitions. [2023-11-12 02:20:09,714 INFO L335 stractBuchiCegarLoop]: ======== Iteration 5 ============ [2023-11-12 02:20:09,714 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1377 states and 2040 transitions. [2023-11-12 02:20:09,723 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1238 [2023-11-12 02:20:09,723 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-12 02:20:09,723 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-12 02:20:09,725 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-12 02:20:09,725 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-12 02:20:09,726 INFO L748 eck$LassoCheckResult]: Stem: 11480#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~token~0 := 0;~local~0 := 0; 11481#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~12#1;havoc main_~__retres1~12#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1; 12357#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret30#1, start_simulation_#t~ret31#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 12358#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 12420#L731 assume 1 == ~m_i~0;~m_st~0 := 0; 12361#L731-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 12321#L736-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 12322#L741-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 12350#L746-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 11419#L751-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 11420#L756-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 11525#L761-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 11770#L766-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 11696#L771-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 11421#L776-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 11080#L781-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 11081#L1036 assume !(0 == ~M_E~0); 11178#L1036-2 assume !(0 == ~T1_E~0); 12083#L1041-1 assume !(0 == ~T2_E~0); 12084#L1046-1 assume 0 == ~T3_E~0;~T3_E~0 := 1; 11455#L1051-1 assume !(0 == ~T4_E~0); 11456#L1056-1 assume !(0 == ~T5_E~0); 12212#L1061-1 assume !(0 == ~T6_E~0); 11350#L1066-1 assume !(0 == ~T7_E~0); 11351#L1071-1 assume !(0 == ~T8_E~0); 12194#L1076-1 assume !(0 == ~T9_E~0); 11240#L1081-1 assume !(0 == ~T10_E~0); 11241#L1086-1 assume 0 == ~E_M~0;~E_M~0 := 1; 11641#L1091-1 assume !(0 == ~E_1~0); 12369#L1096-1 assume !(0 == ~E_2~0); 12370#L1101-1 assume !(0 == ~E_3~0); 11709#L1106-1 assume !(0 == ~E_4~0); 11710#L1111-1 assume !(0 == ~E_5~0); 11874#L1116-1 assume !(0 == ~E_6~0); 11875#L1121-1 assume !(0 == ~E_7~0); 11700#L1126-1 assume 0 == ~E_8~0;~E_8~0 := 1; 11701#L1131-1 assume !(0 == ~E_9~0); 11976#L1136-1 assume !(0 == ~E_10~0); 12091#L1141-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 12240#L514 assume 1 == ~m_pc~0; 12205#L515 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 11718#L525 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 11719#is_master_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 12293#L1285 assume !(0 != activate_threads_~tmp~1#1); 12405#L1285-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 11369#L533 assume !(1 == ~t1_pc~0); 11370#L533-2 is_transmit1_triggered_~__retres1~1#1 := 0; 11889#L544 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 11135#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 11136#L1293 assume !(0 != activate_threads_~tmp___0~0#1); 12112#L1293-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 12113#L552 assume 1 == ~t2_pc~0; 11590#L553 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 11591#L563 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 11704#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 11705#L1301 assume !(0 != activate_threads_~tmp___1~0#1); 11736#L1301-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 11737#L571 assume 1 == ~t3_pc~0; 11929#L572 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 11930#L582 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 11078#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 11079#L1309 assume !(0 != activate_threads_~tmp___2~0#1); 11879#L1309-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 11164#L590 assume !(1 == ~t4_pc~0); 11165#L590-2 is_transmit4_triggered_~__retres1~4#1 := 0; 11938#L601 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 11258#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 11259#L1317 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 12140#L1317-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 11876#L609 assume 1 == ~t5_pc~0; 11877#L610 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 12402#L620 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 12294#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 12295#L1325 assume !(0 != activate_threads_~tmp___4~0#1); 11868#L1325-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 11869#L628 assume !(1 == ~t6_pc~0); 11801#L628-2 is_transmit6_triggered_~__retres1~6#1 := 0; 11800#L639 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 11678#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 11679#L1333 assume !(0 != activate_threads_~tmp___5~0#1); 12174#L1333-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 12175#L647 assume 1 == ~t7_pc~0; 11711#L648 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 11712#L658 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 12303#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 11716#L1341 assume !(0 != activate_threads_~tmp___6~0#1); 11717#L1341-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 12431#L666 assume !(1 == ~t8_pc~0); 11502#L666-2 is_transmit8_triggered_~__retres1~8#1 := 0; 11503#L677 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 11730#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 11901#L1349 assume !(0 != activate_threads_~tmp___7~0#1); 11639#L1349-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 11640#L685 assume 1 == ~t9_pc~0; 12410#L686 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 12311#L696 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 11764#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 11668#L1357 assume !(0 != activate_threads_~tmp___8~0#1); 11669#L1357-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 12054#L704 assume !(1 == ~t10_pc~0); 11658#L704-2 is_transmit10_triggered_~__retres1~10#1 := 0; 11657#L715 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 11919#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 11212#L1365 assume !(0 != activate_threads_~tmp___9~0#1); 11213#L1365-2 havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 11464#L1154 assume !(1 == ~M_E~0); 12162#L1154-2 assume !(1 == ~T1_E~0); 11438#L1159-1 assume !(1 == ~T2_E~0); 11439#L1164-1 assume !(1 == ~T3_E~0); 11898#L1169-1 assume !(1 == ~T4_E~0); 11765#L1174-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 11569#L1179-1 assume !(1 == ~T6_E~0); 11423#L1184-1 assume !(1 == ~T7_E~0); 11424#L1189-1 assume !(1 == ~T8_E~0); 11500#L1194-1 assume !(1 == ~T9_E~0); 11627#L1199-1 assume !(1 == ~T10_E~0); 11581#L1204-1 assume !(1 == ~E_M~0); 11582#L1209-1 assume !(1 == ~E_1~0); 12135#L1214-1 assume 1 == ~E_2~0;~E_2~0 := 2; 12136#L1219-1 assume !(1 == ~E_3~0); 12424#L1224-1 assume !(1 == ~E_4~0); 11923#L1229-1 assume !(1 == ~E_5~0); 11307#L1234-1 assume !(1 == ~E_6~0); 11308#L1239-1 assume !(1 == ~E_7~0); 11365#L1244-1 assume !(1 == ~E_8~0); 11366#L1249-1 assume !(1 == ~E_9~0); 12203#L1254-1 assume 1 == ~E_10~0;~E_10~0 := 2; 11207#L1259-1 assume { :end_inline_reset_delta_events } true; 11208#L1565-2 [2023-11-12 02:20:09,726 INFO L750 eck$LassoCheckResult]: Loop: 11208#L1565-2 assume !false; 12141#L1566 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 11907#L1011-1 assume !false; 11870#L862 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 11646#L794 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 11406#L851 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 11743#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 11435#L866 assume !(0 != eval_~tmp~0#1); 11437#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 11940#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 11941#L1036-3 assume 0 == ~M_E~0;~M_E~0 := 1; 12207#L1036-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 12386#L1041-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 12268#L1046-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 12269#L1051-3 assume !(0 == ~T4_E~0); 12208#L1056-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 11452#L1061-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 11453#L1066-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 11454#L1071-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 12388#L1076-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 11199#L1081-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 11200#L1086-3 assume 0 == ~E_M~0;~E_M~0 := 1; 11254#L1091-3 assume !(0 == ~E_1~0); 11255#L1096-3 assume 0 == ~E_2~0;~E_2~0 := 1; 12352#L1101-3 assume 0 == ~E_3~0;~E_3~0 := 1; 12353#L1106-3 assume 0 == ~E_4~0;~E_4~0 := 1; 12385#L1111-3 assume 0 == ~E_5~0;~E_5~0 := 1; 12344#L1116-3 assume 0 == ~E_6~0;~E_6~0 := 1; 12069#L1121-3 assume 0 == ~E_7~0;~E_7~0 := 1; 12070#L1126-3 assume 0 == ~E_8~0;~E_8~0 := 1; 12283#L1131-3 assume !(0 == ~E_9~0); 12284#L1136-3 assume 0 == ~E_10~0;~E_10~0 := 1; 12436#L1141-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 12072#L514-36 assume !(1 == ~m_pc~0); 11781#L514-38 is_master_triggered_~__retres1~0#1 := 0; 11616#L525-12 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 11617#is_master_triggered_returnLabel#13 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 12111#L1285-36 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 11509#L1285-38 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 11510#L533-36 assume 1 == ~t1_pc~0; 11789#L534-12 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 11883#L544-12 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 12334#is_transmit1_triggered_returnLabel#13 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 12149#L1293-36 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 11946#L1293-38 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 11947#L552-36 assume 1 == ~t2_pc~0; 11504#L553-12 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 11505#L563-12 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 12005#is_transmit2_triggered_returnLabel#13 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 12276#L1301-36 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 11476#L1301-38 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 11477#L571-36 assume 1 == ~t3_pc~0; 11864#L572-12 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 11567#L582-12 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 11568#is_transmit3_triggered_returnLabel#13 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 11760#L1309-36 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 12267#L1309-38 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 11539#L590-36 assume 1 == ~t4_pc~0; 11540#L591-12 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 12163#L601-12 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 11956#is_transmit4_triggered_returnLabel#13 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 11957#L1317-36 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 12246#L1317-38 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 12247#L609-36 assume 1 == ~t5_pc~0; 12124#L610-12 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 11949#L620-12 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 11950#is_transmit5_triggered_returnLabel#13 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 12291#L1325-36 assume !(0 != activate_threads_~tmp___4~0#1); 12033#L1325-38 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 11840#L628-36 assume 1 == ~t6_pc~0; 11688#L629-12 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 11689#L639-12 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 11739#is_transmit6_triggered_returnLabel#13 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 11740#L1333-36 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 12074#L1333-38 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 12075#L647-36 assume 1 == ~t7_pc~0; 11998#L648-12 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 11226#L658-12 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 11227#is_transmit7_triggered_returnLabel#13 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 11244#L1341-36 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 11245#L1341-38 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 12164#L666-36 assume 1 == ~t8_pc~0; 11432#L667-12 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 11433#L677-12 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 12062#is_transmit8_triggered_returnLabel#13 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 12063#L1349-36 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 11587#L1349-38 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 11588#L685-36 assume 1 == ~t9_pc~0; 12049#L686-12 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 11339#L696-12 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 11794#is_transmit9_triggered_returnLabel#13 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 11795#L1357-36 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 11727#L1357-38 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 11728#L704-36 assume !(1 == ~t10_pc~0); 11328#L704-38 is_transmit10_triggered_~__retres1~10#1 := 0; 11327#L715-12 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 11648#is_transmit10_triggered_returnLabel#13 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 11649#L1365-36 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 11354#L1365-38 havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 11355#L1154-3 assume 1 == ~M_E~0;~M_E~0 := 2; 12338#L1154-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 12221#L1159-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 12222#L1164-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 12399#L1169-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 11654#L1174-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 11655#L1179-3 assume !(1 == ~T6_E~0); 12313#L1184-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 11228#L1189-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 11229#L1194-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 11598#L1199-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 11599#L1204-3 assume 1 == ~E_M~0;~E_M~0 := 2; 11918#L1209-3 assume 1 == ~E_1~0;~E_1~0 := 2; 11096#L1214-3 assume 1 == ~E_2~0;~E_2~0 := 2; 11097#L1219-3 assume !(1 == ~E_3~0); 12118#L1224-3 assume 1 == ~E_4~0;~E_4~0 := 2; 12119#L1229-3 assume 1 == ~E_5~0;~E_5~0 := 2; 12139#L1234-3 assume 1 == ~E_6~0;~E_6~0 := 2; 11367#L1239-3 assume 1 == ~E_7~0;~E_7~0 := 2; 11368#L1244-3 assume 1 == ~E_8~0;~E_8~0 := 2; 11969#L1249-3 assume 1 == ~E_9~0;~E_9~0 := 2; 12345#L1254-3 assume 1 == ~E_10~0;~E_10~0 := 2; 12122#L1259-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 12123#L794-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 11176#L851-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 11636#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret30#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret30#1;havoc start_simulation_#t~ret30#1; 11637#L1584 assume !(0 == start_simulation_~tmp~3#1); 12080#L1584-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret29#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 11381#L794-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 11076#L851-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 11128#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret29#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret29#1;havoc stop_simulation_#t~ret29#1; 11129#L1539 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 11707#L1546 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 11962#stop_simulation_returnLabel#1 start_simulation_#t~ret31#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret29#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret31#1;havoc start_simulation_#t~ret31#1; 11963#L1597 assume !(0 != start_simulation_~tmp___0~1#1); 11208#L1565-2 [2023-11-12 02:20:09,728 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-12 02:20:09,728 INFO L85 PathProgramCache]: Analyzing trace with hash 1829369535, now seen corresponding path program 1 times [2023-11-12 02:20:09,729 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-12 02:20:09,729 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1725705201] [2023-11-12 02:20:09,729 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-12 02:20:09,729 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-12 02:20:09,750 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-12 02:20:09,792 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-12 02:20:09,792 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-12 02:20:09,792 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1725705201] [2023-11-12 02:20:09,793 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1725705201] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-12 02:20:09,793 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-12 02:20:09,793 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-12 02:20:09,793 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [528594606] [2023-11-12 02:20:09,794 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-12 02:20:09,794 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-12 02:20:09,794 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-12 02:20:09,795 INFO L85 PathProgramCache]: Analyzing trace with hash 157765683, now seen corresponding path program 1 times [2023-11-12 02:20:09,795 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-12 02:20:09,795 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1517087931] [2023-11-12 02:20:09,795 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-12 02:20:09,795 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-12 02:20:09,815 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-12 02:20:09,870 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-12 02:20:09,870 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-12 02:20:09,870 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1517087931] [2023-11-12 02:20:09,871 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1517087931] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-12 02:20:09,871 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-12 02:20:09,871 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-12 02:20:09,871 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [141424041] [2023-11-12 02:20:09,871 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-12 02:20:09,872 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-12 02:20:09,872 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-12 02:20:09,872 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-12 02:20:09,872 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-12 02:20:09,873 INFO L87 Difference]: Start difference. First operand 1377 states and 2040 transitions. cyclomatic complexity: 664 Second operand has 3 states, 3 states have (on average 42.666666666666664) internal successors, (128), 3 states have internal predecessors, (128), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-12 02:20:09,910 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-12 02:20:09,911 INFO L93 Difference]: Finished difference Result 1377 states and 2039 transitions. [2023-11-12 02:20:09,911 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1377 states and 2039 transitions. [2023-11-12 02:20:09,922 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1238 [2023-11-12 02:20:09,933 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1377 states to 1377 states and 2039 transitions. [2023-11-12 02:20:09,933 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1377 [2023-11-12 02:20:09,935 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1377 [2023-11-12 02:20:09,935 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1377 states and 2039 transitions. [2023-11-12 02:20:09,937 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-12 02:20:09,938 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1377 states and 2039 transitions. [2023-11-12 02:20:09,940 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1377 states and 2039 transitions. [2023-11-12 02:20:09,960 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1377 to 1377. [2023-11-12 02:20:09,963 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1377 states, 1377 states have (on average 1.4807552650689906) internal successors, (2039), 1376 states have internal predecessors, (2039), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-12 02:20:09,969 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1377 states to 1377 states and 2039 transitions. [2023-11-12 02:20:09,969 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1377 states and 2039 transitions. [2023-11-12 02:20:09,970 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-12 02:20:09,972 INFO L428 stractBuchiCegarLoop]: Abstraction has 1377 states and 2039 transitions. [2023-11-12 02:20:09,972 INFO L335 stractBuchiCegarLoop]: ======== Iteration 6 ============ [2023-11-12 02:20:09,972 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1377 states and 2039 transitions. [2023-11-12 02:20:09,981 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1238 [2023-11-12 02:20:09,981 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-12 02:20:09,981 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-12 02:20:09,983 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-12 02:20:09,984 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-12 02:20:09,984 INFO L748 eck$LassoCheckResult]: Stem: 14241#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~token~0 := 0;~local~0 := 0; 14242#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~12#1;havoc main_~__retres1~12#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1; 15118#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret30#1, start_simulation_#t~ret31#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 15119#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 15181#L731 assume 1 == ~m_i~0;~m_st~0 := 0; 15122#L731-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 15082#L736-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 15083#L741-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 15111#L746-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 14178#L751-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 14179#L756-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 14286#L761-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 14531#L766-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 14457#L771-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 14180#L776-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 13841#L781-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 13842#L1036 assume !(0 == ~M_E~0); 13939#L1036-2 assume !(0 == ~T1_E~0); 14844#L1041-1 assume !(0 == ~T2_E~0); 14845#L1046-1 assume 0 == ~T3_E~0;~T3_E~0 := 1; 14216#L1051-1 assume !(0 == ~T4_E~0); 14217#L1056-1 assume !(0 == ~T5_E~0); 14973#L1061-1 assume !(0 == ~T6_E~0); 14111#L1066-1 assume !(0 == ~T7_E~0); 14112#L1071-1 assume !(0 == ~T8_E~0); 14955#L1076-1 assume !(0 == ~T9_E~0); 14001#L1081-1 assume !(0 == ~T10_E~0); 14002#L1086-1 assume 0 == ~E_M~0;~E_M~0 := 1; 14402#L1091-1 assume !(0 == ~E_1~0); 15129#L1096-1 assume !(0 == ~E_2~0); 15130#L1101-1 assume !(0 == ~E_3~0); 14470#L1106-1 assume !(0 == ~E_4~0); 14471#L1111-1 assume !(0 == ~E_5~0); 14635#L1116-1 assume !(0 == ~E_6~0); 14636#L1121-1 assume !(0 == ~E_7~0); 14461#L1126-1 assume 0 == ~E_8~0;~E_8~0 := 1; 14462#L1131-1 assume !(0 == ~E_9~0); 14737#L1136-1 assume !(0 == ~E_10~0); 14852#L1141-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 15001#L514 assume 1 == ~m_pc~0; 14966#L515 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 14479#L525 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 14480#is_master_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 15053#L1285 assume !(0 != activate_threads_~tmp~1#1); 15165#L1285-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 14130#L533 assume !(1 == ~t1_pc~0); 14131#L533-2 is_transmit1_triggered_~__retres1~1#1 := 0; 14650#L544 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 13894#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 13895#L1293 assume !(0 != activate_threads_~tmp___0~0#1); 14873#L1293-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 14874#L552 assume 1 == ~t2_pc~0; 14350#L553 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 14351#L563 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 14465#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 14466#L1301 assume !(0 != activate_threads_~tmp___1~0#1); 14492#L1301-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 14493#L571 assume 1 == ~t3_pc~0; 14688#L572 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 14689#L582 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 13839#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 13840#L1309 assume !(0 != activate_threads_~tmp___2~0#1); 14640#L1309-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 13925#L590 assume !(1 == ~t4_pc~0); 13926#L590-2 is_transmit4_triggered_~__retres1~4#1 := 0; 14698#L601 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 14019#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 14020#L1317 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 14900#L1317-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 14637#L609 assume 1 == ~t5_pc~0; 14638#L610 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 15163#L620 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 15055#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 15056#L1325 assume !(0 != activate_threads_~tmp___4~0#1); 14629#L1325-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 14630#L628 assume !(1 == ~t6_pc~0); 14562#L628-2 is_transmit6_triggered_~__retres1~6#1 := 0; 14561#L639 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 14438#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 14439#L1333 assume !(0 != activate_threads_~tmp___5~0#1); 14935#L1333-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 14936#L647 assume 1 == ~t7_pc~0; 14472#L648 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 14473#L658 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 15064#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 14475#L1341 assume !(0 != activate_threads_~tmp___6~0#1); 14476#L1341-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 15192#L666 assume !(1 == ~t8_pc~0); 14263#L666-2 is_transmit8_triggered_~__retres1~8#1 := 0; 14264#L677 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 14491#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 14661#L1349 assume !(0 != activate_threads_~tmp___7~0#1); 14399#L1349-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 14400#L685 assume 1 == ~t9_pc~0; 15171#L686 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 15072#L696 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 14525#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 14429#L1357 assume !(0 != activate_threads_~tmp___8~0#1); 14430#L1357-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 14815#L704 assume !(1 == ~t10_pc~0); 14419#L704-2 is_transmit10_triggered_~__retres1~10#1 := 0; 14418#L715 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 14679#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 13973#L1365 assume !(0 != activate_threads_~tmp___9~0#1); 13974#L1365-2 havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 14225#L1154 assume !(1 == ~M_E~0); 14923#L1154-2 assume !(1 == ~T1_E~0); 14199#L1159-1 assume !(1 == ~T2_E~0); 14200#L1164-1 assume !(1 == ~T3_E~0); 14659#L1169-1 assume !(1 == ~T4_E~0); 14526#L1174-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 14328#L1179-1 assume !(1 == ~T6_E~0); 14184#L1184-1 assume !(1 == ~T7_E~0); 14185#L1189-1 assume !(1 == ~T8_E~0); 14261#L1194-1 assume !(1 == ~T9_E~0); 14386#L1199-1 assume !(1 == ~T10_E~0); 14340#L1204-1 assume !(1 == ~E_M~0); 14341#L1209-1 assume !(1 == ~E_1~0); 14894#L1214-1 assume 1 == ~E_2~0;~E_2~0 := 2; 14895#L1219-1 assume !(1 == ~E_3~0); 15185#L1224-1 assume !(1 == ~E_4~0); 14683#L1229-1 assume !(1 == ~E_5~0); 14068#L1234-1 assume !(1 == ~E_6~0); 14069#L1239-1 assume !(1 == ~E_7~0); 14126#L1244-1 assume !(1 == ~E_8~0); 14127#L1249-1 assume !(1 == ~E_9~0); 14964#L1254-1 assume 1 == ~E_10~0;~E_10~0 := 2; 13968#L1259-1 assume { :end_inline_reset_delta_events } true; 13969#L1565-2 [2023-11-12 02:20:09,985 INFO L750 eck$LassoCheckResult]: Loop: 13969#L1565-2 assume !false; 14902#L1566 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 14667#L1011-1 assume !false; 14631#L862 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 14404#L794 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 14167#L851 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 14504#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 14191#L866 assume !(0 != eval_~tmp~0#1); 14193#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 14700#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 14701#L1036-3 assume 0 == ~M_E~0;~M_E~0 := 1; 14968#L1036-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 15147#L1041-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 15029#L1046-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 15030#L1051-3 assume !(0 == ~T4_E~0); 14969#L1056-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 14213#L1061-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 14214#L1066-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 14215#L1071-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 15149#L1076-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 13960#L1081-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 13961#L1086-3 assume 0 == ~E_M~0;~E_M~0 := 1; 14011#L1091-3 assume !(0 == ~E_1~0); 14012#L1096-3 assume 0 == ~E_2~0;~E_2~0 := 1; 15113#L1101-3 assume 0 == ~E_3~0;~E_3~0 := 1; 15114#L1106-3 assume 0 == ~E_4~0;~E_4~0 := 1; 15146#L1111-3 assume 0 == ~E_5~0;~E_5~0 := 1; 15105#L1116-3 assume 0 == ~E_6~0;~E_6~0 := 1; 14830#L1121-3 assume 0 == ~E_7~0;~E_7~0 := 1; 14831#L1126-3 assume 0 == ~E_8~0;~E_8~0 := 1; 15044#L1131-3 assume !(0 == ~E_9~0); 15045#L1136-3 assume 0 == ~E_10~0;~E_10~0 := 1; 15197#L1141-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 14833#L514-36 assume 1 == ~m_pc~0; 14834#L515-12 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 14377#L525-12 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 14378#is_master_triggered_returnLabel#13 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 14872#L1285-36 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 14270#L1285-38 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 14271#L533-36 assume 1 == ~t1_pc~0; 14551#L534-12 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 14644#L544-12 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 15095#is_transmit1_triggered_returnLabel#13 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 14910#L1293-36 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 14707#L1293-38 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 14708#L552-36 assume 1 == ~t2_pc~0; 14265#L553-12 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 14266#L563-12 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 14766#is_transmit2_triggered_returnLabel#13 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 15037#L1301-36 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 14237#L1301-38 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 14238#L571-36 assume 1 == ~t3_pc~0; 14625#L572-12 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 14329#L582-12 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 14330#is_transmit3_triggered_returnLabel#13 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 14521#L1309-36 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 15028#L1309-38 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 14300#L590-36 assume 1 == ~t4_pc~0; 14301#L591-12 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 14924#L601-12 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 14717#is_transmit4_triggered_returnLabel#13 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 14718#L1317-36 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 15007#L1317-38 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 15008#L609-36 assume 1 == ~t5_pc~0; 14885#L610-12 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 14710#L620-12 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 14711#is_transmit5_triggered_returnLabel#13 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 15052#L1325-36 assume !(0 != activate_threads_~tmp___4~0#1); 14794#L1325-38 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 14601#L628-36 assume 1 == ~t6_pc~0; 14449#L629-12 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 14450#L639-12 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 14500#is_transmit6_triggered_returnLabel#13 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 14501#L1333-36 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 14835#L1333-38 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 14836#L647-36 assume 1 == ~t7_pc~0; 14759#L648-12 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 13987#L658-12 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 13988#is_transmit7_triggered_returnLabel#13 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 14005#L1341-36 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 14006#L1341-38 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 14925#L666-36 assume 1 == ~t8_pc~0; 14196#L667-12 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 14197#L677-12 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 14823#is_transmit8_triggered_returnLabel#13 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 14824#L1349-36 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 14348#L1349-38 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 14349#L685-36 assume !(1 == ~t9_pc~0); 14099#L685-38 is_transmit9_triggered_~__retres1~9#1 := 0; 14100#L696-12 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 14555#is_transmit9_triggered_returnLabel#13 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 14556#L1357-36 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 14488#L1357-38 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 14489#L704-36 assume 1 == ~t10_pc~0; 14087#L705-12 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 14088#L715-12 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 14409#is_transmit10_triggered_returnLabel#13 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 14410#L1365-36 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 14115#L1365-38 havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 14116#L1154-3 assume 1 == ~M_E~0;~M_E~0 := 2; 15099#L1154-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 14982#L1159-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 14983#L1164-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 15160#L1169-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 14415#L1174-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 14416#L1179-3 assume !(1 == ~T6_E~0); 15074#L1184-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 13989#L1189-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 13990#L1194-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 14359#L1199-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 14360#L1204-3 assume 1 == ~E_M~0;~E_M~0 := 2; 14680#L1209-3 assume 1 == ~E_1~0;~E_1~0 := 2; 13857#L1214-3 assume 1 == ~E_2~0;~E_2~0 := 2; 13858#L1219-3 assume !(1 == ~E_3~0); 14879#L1224-3 assume 1 == ~E_4~0;~E_4~0 := 2; 14880#L1229-3 assume 1 == ~E_5~0;~E_5~0 := 2; 14901#L1234-3 assume 1 == ~E_6~0;~E_6~0 := 2; 14128#L1239-3 assume 1 == ~E_7~0;~E_7~0 := 2; 14129#L1244-3 assume 1 == ~E_8~0;~E_8~0 := 2; 14734#L1249-3 assume 1 == ~E_9~0;~E_9~0 := 2; 15106#L1254-3 assume 1 == ~E_10~0;~E_10~0 := 2; 14883#L1259-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 14884#L794-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 13937#L851-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 14397#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret30#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret30#1;havoc start_simulation_#t~ret30#1; 14398#L1584 assume !(0 == start_simulation_~tmp~3#1); 14841#L1584-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret29#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 14142#L794-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 13837#L851-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 13889#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret29#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret29#1;havoc stop_simulation_#t~ret29#1; 13890#L1539 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 14468#L1546 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 14723#stop_simulation_returnLabel#1 start_simulation_#t~ret31#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret29#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret31#1;havoc start_simulation_#t~ret31#1; 14724#L1597 assume !(0 != start_simulation_~tmp___0~1#1); 13969#L1565-2 [2023-11-12 02:20:09,986 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-12 02:20:09,986 INFO L85 PathProgramCache]: Analyzing trace with hash -1183425475, now seen corresponding path program 1 times [2023-11-12 02:20:09,986 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-12 02:20:09,986 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [743213964] [2023-11-12 02:20:09,986 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-12 02:20:09,987 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-12 02:20:10,006 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-12 02:20:10,054 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-12 02:20:10,055 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-12 02:20:10,055 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [743213964] [2023-11-12 02:20:10,055 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [743213964] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-12 02:20:10,055 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-12 02:20:10,056 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-12 02:20:10,056 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1702416030] [2023-11-12 02:20:10,056 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-12 02:20:10,056 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-12 02:20:10,057 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-12 02:20:10,057 INFO L85 PathProgramCache]: Analyzing trace with hash -220510030, now seen corresponding path program 1 times [2023-11-12 02:20:10,062 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-12 02:20:10,062 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [552541503] [2023-11-12 02:20:10,062 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-12 02:20:10,063 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-12 02:20:10,083 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-12 02:20:10,142 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-12 02:20:10,142 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-12 02:20:10,142 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [552541503] [2023-11-12 02:20:10,143 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [552541503] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-12 02:20:10,143 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-12 02:20:10,143 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-12 02:20:10,143 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1276730463] [2023-11-12 02:20:10,143 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-12 02:20:10,144 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-12 02:20:10,144 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-12 02:20:10,145 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-12 02:20:10,145 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-12 02:20:10,145 INFO L87 Difference]: Start difference. First operand 1377 states and 2039 transitions. cyclomatic complexity: 663 Second operand has 3 states, 3 states have (on average 42.666666666666664) internal successors, (128), 3 states have internal predecessors, (128), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-12 02:20:10,182 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-12 02:20:10,182 INFO L93 Difference]: Finished difference Result 1377 states and 2038 transitions. [2023-11-12 02:20:10,182 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1377 states and 2038 transitions. [2023-11-12 02:20:10,193 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1238 [2023-11-12 02:20:10,205 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1377 states to 1377 states and 2038 transitions. [2023-11-12 02:20:10,205 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1377 [2023-11-12 02:20:10,207 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1377 [2023-11-12 02:20:10,207 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1377 states and 2038 transitions. [2023-11-12 02:20:10,210 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-12 02:20:10,210 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1377 states and 2038 transitions. [2023-11-12 02:20:10,213 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1377 states and 2038 transitions. [2023-11-12 02:20:10,233 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1377 to 1377. [2023-11-12 02:20:10,237 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1377 states, 1377 states have (on average 1.4800290486564995) internal successors, (2038), 1376 states have internal predecessors, (2038), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-12 02:20:10,243 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1377 states to 1377 states and 2038 transitions. [2023-11-12 02:20:10,243 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1377 states and 2038 transitions. [2023-11-12 02:20:10,244 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-12 02:20:10,246 INFO L428 stractBuchiCegarLoop]: Abstraction has 1377 states and 2038 transitions. [2023-11-12 02:20:10,246 INFO L335 stractBuchiCegarLoop]: ======== Iteration 7 ============ [2023-11-12 02:20:10,246 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1377 states and 2038 transitions. [2023-11-12 02:20:10,256 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1238 [2023-11-12 02:20:10,256 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-12 02:20:10,256 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-12 02:20:10,259 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-12 02:20:10,259 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-12 02:20:10,259 INFO L748 eck$LassoCheckResult]: Stem: 17002#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~token~0 := 0;~local~0 := 0; 17003#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~12#1;havoc main_~__retres1~12#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1; 17879#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret30#1, start_simulation_#t~ret31#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 17880#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 17942#L731 assume 1 == ~m_i~0;~m_st~0 := 0; 17883#L731-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 17843#L736-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 17844#L741-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 17872#L746-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 16939#L751-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 16940#L756-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 17047#L761-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 17292#L766-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 17218#L771-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 16941#L776-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 16602#L781-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 16603#L1036 assume !(0 == ~M_E~0); 16700#L1036-2 assume !(0 == ~T1_E~0); 17605#L1041-1 assume !(0 == ~T2_E~0); 17606#L1046-1 assume 0 == ~T3_E~0;~T3_E~0 := 1; 16977#L1051-1 assume !(0 == ~T4_E~0); 16978#L1056-1 assume !(0 == ~T5_E~0); 17734#L1061-1 assume !(0 == ~T6_E~0); 16872#L1066-1 assume !(0 == ~T7_E~0); 16873#L1071-1 assume !(0 == ~T8_E~0); 17716#L1076-1 assume !(0 == ~T9_E~0); 16762#L1081-1 assume !(0 == ~T10_E~0); 16763#L1086-1 assume 0 == ~E_M~0;~E_M~0 := 1; 17163#L1091-1 assume !(0 == ~E_1~0); 17890#L1096-1 assume !(0 == ~E_2~0); 17891#L1101-1 assume !(0 == ~E_3~0); 17231#L1106-1 assume !(0 == ~E_4~0); 17232#L1111-1 assume !(0 == ~E_5~0); 17396#L1116-1 assume !(0 == ~E_6~0); 17397#L1121-1 assume !(0 == ~E_7~0); 17222#L1126-1 assume 0 == ~E_8~0;~E_8~0 := 1; 17223#L1131-1 assume !(0 == ~E_9~0); 17498#L1136-1 assume !(0 == ~E_10~0); 17613#L1141-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 17762#L514 assume 1 == ~m_pc~0; 17727#L515 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 17240#L525 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 17241#is_master_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 17814#L1285 assume !(0 != activate_threads_~tmp~1#1); 17926#L1285-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 16891#L533 assume !(1 == ~t1_pc~0); 16892#L533-2 is_transmit1_triggered_~__retres1~1#1 := 0; 17411#L544 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 16655#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 16656#L1293 assume !(0 != activate_threads_~tmp___0~0#1); 17634#L1293-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 17635#L552 assume 1 == ~t2_pc~0; 17111#L553 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 17112#L563 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 17226#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 17227#L1301 assume !(0 != activate_threads_~tmp___1~0#1); 17253#L1301-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 17254#L571 assume 1 == ~t3_pc~0; 17449#L572 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 17450#L582 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 16600#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 16601#L1309 assume !(0 != activate_threads_~tmp___2~0#1); 17401#L1309-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 16686#L590 assume !(1 == ~t4_pc~0); 16687#L590-2 is_transmit4_triggered_~__retres1~4#1 := 0; 17459#L601 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 16780#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 16781#L1317 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 17662#L1317-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 17398#L609 assume 1 == ~t5_pc~0; 17399#L610 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 17924#L620 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 17816#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 17817#L1325 assume !(0 != activate_threads_~tmp___4~0#1); 17390#L1325-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 17391#L628 assume !(1 == ~t6_pc~0); 17323#L628-2 is_transmit6_triggered_~__retres1~6#1 := 0; 17322#L639 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 17199#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 17200#L1333 assume !(0 != activate_threads_~tmp___5~0#1); 17696#L1333-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 17697#L647 assume 1 == ~t7_pc~0; 17233#L648 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 17234#L658 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 17825#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 17236#L1341 assume !(0 != activate_threads_~tmp___6~0#1); 17237#L1341-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 17953#L666 assume !(1 == ~t8_pc~0); 17024#L666-2 is_transmit8_triggered_~__retres1~8#1 := 0; 17025#L677 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 17252#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 17422#L1349 assume !(0 != activate_threads_~tmp___7~0#1); 17160#L1349-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 17161#L685 assume 1 == ~t9_pc~0; 17932#L686 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 17833#L696 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 17286#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 17190#L1357 assume !(0 != activate_threads_~tmp___8~0#1); 17191#L1357-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 17576#L704 assume !(1 == ~t10_pc~0); 17180#L704-2 is_transmit10_triggered_~__retres1~10#1 := 0; 17179#L715 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 17441#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 16734#L1365 assume !(0 != activate_threads_~tmp___9~0#1); 16735#L1365-2 havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 16986#L1154 assume !(1 == ~M_E~0); 17684#L1154-2 assume !(1 == ~T1_E~0); 16960#L1159-1 assume !(1 == ~T2_E~0); 16961#L1164-1 assume !(1 == ~T3_E~0); 17420#L1169-1 assume !(1 == ~T4_E~0); 17287#L1174-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 17089#L1179-1 assume !(1 == ~T6_E~0); 16945#L1184-1 assume !(1 == ~T7_E~0); 16946#L1189-1 assume !(1 == ~T8_E~0); 17022#L1194-1 assume !(1 == ~T9_E~0); 17147#L1199-1 assume !(1 == ~T10_E~0); 17101#L1204-1 assume !(1 == ~E_M~0); 17102#L1209-1 assume !(1 == ~E_1~0); 17655#L1214-1 assume 1 == ~E_2~0;~E_2~0 := 2; 17656#L1219-1 assume !(1 == ~E_3~0); 17946#L1224-1 assume !(1 == ~E_4~0); 17444#L1229-1 assume !(1 == ~E_5~0); 16829#L1234-1 assume !(1 == ~E_6~0); 16830#L1239-1 assume !(1 == ~E_7~0); 16887#L1244-1 assume !(1 == ~E_8~0); 16888#L1249-1 assume !(1 == ~E_9~0); 17725#L1254-1 assume 1 == ~E_10~0;~E_10~0 := 2; 16729#L1259-1 assume { :end_inline_reset_delta_events } true; 16730#L1565-2 [2023-11-12 02:20:10,260 INFO L750 eck$LassoCheckResult]: Loop: 16730#L1565-2 assume !false; 17663#L1566 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 17429#L1011-1 assume !false; 17392#L862 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 17165#L794 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 16928#L851 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 17265#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 16952#L866 assume !(0 != eval_~tmp~0#1); 16954#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 17461#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 17462#L1036-3 assume 0 == ~M_E~0;~M_E~0 := 1; 17729#L1036-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 17908#L1041-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 17790#L1046-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 17791#L1051-3 assume !(0 == ~T4_E~0); 17730#L1056-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 16974#L1061-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 16975#L1066-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 16976#L1071-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 17910#L1076-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 16721#L1081-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 16722#L1086-3 assume 0 == ~E_M~0;~E_M~0 := 1; 16772#L1091-3 assume !(0 == ~E_1~0); 16773#L1096-3 assume 0 == ~E_2~0;~E_2~0 := 1; 17874#L1101-3 assume 0 == ~E_3~0;~E_3~0 := 1; 17875#L1106-3 assume 0 == ~E_4~0;~E_4~0 := 1; 17907#L1111-3 assume 0 == ~E_5~0;~E_5~0 := 1; 17866#L1116-3 assume 0 == ~E_6~0;~E_6~0 := 1; 17591#L1121-3 assume 0 == ~E_7~0;~E_7~0 := 1; 17592#L1126-3 assume 0 == ~E_8~0;~E_8~0 := 1; 17805#L1131-3 assume !(0 == ~E_9~0); 17806#L1136-3 assume 0 == ~E_10~0;~E_10~0 := 1; 17958#L1141-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 17594#L514-36 assume !(1 == ~m_pc~0); 17303#L514-38 is_master_triggered_~__retres1~0#1 := 0; 17138#L525-12 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 17139#is_master_triggered_returnLabel#13 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 17633#L1285-36 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 17031#L1285-38 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 17032#L533-36 assume 1 == ~t1_pc~0; 17312#L534-12 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 17405#L544-12 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 17856#is_transmit1_triggered_returnLabel#13 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 17671#L1293-36 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 17468#L1293-38 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 17469#L552-36 assume 1 == ~t2_pc~0; 17026#L553-12 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 17027#L563-12 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 17527#is_transmit2_triggered_returnLabel#13 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 17798#L1301-36 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 16998#L1301-38 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 16999#L571-36 assume 1 == ~t3_pc~0; 17386#L572-12 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 17090#L582-12 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 17091#is_transmit3_triggered_returnLabel#13 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 17282#L1309-36 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 17789#L1309-38 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 17061#L590-36 assume 1 == ~t4_pc~0; 17062#L591-12 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 17685#L601-12 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 17479#is_transmit4_triggered_returnLabel#13 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 17480#L1317-36 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 17768#L1317-38 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 17769#L609-36 assume 1 == ~t5_pc~0; 17646#L610-12 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 17471#L620-12 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 17472#is_transmit5_triggered_returnLabel#13 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 17813#L1325-36 assume !(0 != activate_threads_~tmp___4~0#1); 17555#L1325-38 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 17362#L628-36 assume 1 == ~t6_pc~0; 17210#L629-12 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 17211#L639-12 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 17261#is_transmit6_triggered_returnLabel#13 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 17262#L1333-36 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 17596#L1333-38 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 17597#L647-36 assume 1 == ~t7_pc~0; 17520#L648-12 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 16750#L658-12 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 16751#is_transmit7_triggered_returnLabel#13 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 16766#L1341-36 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 16767#L1341-38 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 17686#L666-36 assume 1 == ~t8_pc~0; 16957#L667-12 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 16958#L677-12 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 17584#is_transmit8_triggered_returnLabel#13 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 17585#L1349-36 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 17109#L1349-38 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 17110#L685-36 assume 1 == ~t9_pc~0; 17570#L686-12 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 16859#L696-12 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 17314#is_transmit9_triggered_returnLabel#13 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 17315#L1357-36 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 17249#L1357-38 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 17250#L704-36 assume 1 == ~t10_pc~0; 16848#L705-12 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 16849#L715-12 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 17170#is_transmit10_triggered_returnLabel#13 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 17171#L1365-36 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 16874#L1365-38 havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 16875#L1154-3 assume 1 == ~M_E~0;~M_E~0 := 2; 17860#L1154-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 17743#L1159-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 17744#L1164-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 17921#L1169-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 17176#L1174-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 17177#L1179-3 assume !(1 == ~T6_E~0); 17835#L1184-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 16748#L1189-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 16749#L1194-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 17120#L1199-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 17121#L1204-3 assume 1 == ~E_M~0;~E_M~0 := 2; 17440#L1209-3 assume 1 == ~E_1~0;~E_1~0 := 2; 16618#L1214-3 assume 1 == ~E_2~0;~E_2~0 := 2; 16619#L1219-3 assume !(1 == ~E_3~0); 17640#L1224-3 assume 1 == ~E_4~0;~E_4~0 := 2; 17641#L1229-3 assume 1 == ~E_5~0;~E_5~0 := 2; 17661#L1234-3 assume 1 == ~E_6~0;~E_6~0 := 2; 16889#L1239-3 assume 1 == ~E_7~0;~E_7~0 := 2; 16890#L1244-3 assume 1 == ~E_8~0;~E_8~0 := 2; 17491#L1249-3 assume 1 == ~E_9~0;~E_9~0 := 2; 17867#L1254-3 assume 1 == ~E_10~0;~E_10~0 := 2; 17644#L1259-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 17645#L794-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 16698#L851-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 17158#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret30#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret30#1;havoc start_simulation_#t~ret30#1; 17159#L1584 assume !(0 == start_simulation_~tmp~3#1); 17602#L1584-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret29#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 16903#L794-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 16598#L851-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 16650#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret29#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret29#1;havoc stop_simulation_#t~ret29#1; 16651#L1539 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 17228#L1546 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 17484#stop_simulation_returnLabel#1 start_simulation_#t~ret31#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret29#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret31#1;havoc start_simulation_#t~ret31#1; 17485#L1597 assume !(0 != start_simulation_~tmp___0~1#1); 16730#L1565-2 [2023-11-12 02:20:10,261 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-12 02:20:10,261 INFO L85 PathProgramCache]: Analyzing trace with hash 659050239, now seen corresponding path program 1 times [2023-11-12 02:20:10,261 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-12 02:20:10,261 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2081320760] [2023-11-12 02:20:10,261 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-12 02:20:10,262 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-12 02:20:10,275 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-12 02:20:10,309 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-12 02:20:10,309 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-12 02:20:10,309 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2081320760] [2023-11-12 02:20:10,310 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2081320760] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-12 02:20:10,310 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-12 02:20:10,310 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-12 02:20:10,310 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1310088493] [2023-11-12 02:20:10,310 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-12 02:20:10,311 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-12 02:20:10,311 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-12 02:20:10,311 INFO L85 PathProgramCache]: Analyzing trace with hash 642940402, now seen corresponding path program 2 times [2023-11-12 02:20:10,311 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-12 02:20:10,312 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [24122558] [2023-11-12 02:20:10,312 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-12 02:20:10,312 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-12 02:20:10,330 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-12 02:20:10,398 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-12 02:20:10,398 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-12 02:20:10,398 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [24122558] [2023-11-12 02:20:10,398 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [24122558] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-12 02:20:10,399 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-12 02:20:10,399 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-12 02:20:10,399 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [688136545] [2023-11-12 02:20:10,399 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-12 02:20:10,399 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-12 02:20:10,400 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-12 02:20:10,400 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-12 02:20:10,400 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-12 02:20:10,401 INFO L87 Difference]: Start difference. First operand 1377 states and 2038 transitions. cyclomatic complexity: 662 Second operand has 3 states, 3 states have (on average 42.666666666666664) internal successors, (128), 3 states have internal predecessors, (128), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-12 02:20:10,437 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-12 02:20:10,437 INFO L93 Difference]: Finished difference Result 1377 states and 2037 transitions. [2023-11-12 02:20:10,437 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1377 states and 2037 transitions. [2023-11-12 02:20:10,446 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1238 [2023-11-12 02:20:10,457 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1377 states to 1377 states and 2037 transitions. [2023-11-12 02:20:10,458 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1377 [2023-11-12 02:20:10,459 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1377 [2023-11-12 02:20:10,460 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1377 states and 2037 transitions. [2023-11-12 02:20:10,462 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-12 02:20:10,463 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1377 states and 2037 transitions. [2023-11-12 02:20:10,466 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1377 states and 2037 transitions. [2023-11-12 02:20:10,489 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1377 to 1377. [2023-11-12 02:20:10,493 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1377 states, 1377 states have (on average 1.4793028322440087) internal successors, (2037), 1376 states have internal predecessors, (2037), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-12 02:20:10,499 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1377 states to 1377 states and 2037 transitions. [2023-11-12 02:20:10,499 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1377 states and 2037 transitions. [2023-11-12 02:20:10,500 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-12 02:20:10,502 INFO L428 stractBuchiCegarLoop]: Abstraction has 1377 states and 2037 transitions. [2023-11-12 02:20:10,502 INFO L335 stractBuchiCegarLoop]: ======== Iteration 8 ============ [2023-11-12 02:20:10,502 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1377 states and 2037 transitions. [2023-11-12 02:20:10,509 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1238 [2023-11-12 02:20:10,509 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-12 02:20:10,509 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-12 02:20:10,511 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-12 02:20:10,512 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-12 02:20:10,512 INFO L748 eck$LassoCheckResult]: Stem: 19763#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~token~0 := 0;~local~0 := 0; 19764#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~12#1;havoc main_~__retres1~12#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1; 20640#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret30#1, start_simulation_#t~ret31#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 20641#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 20703#L731 assume 1 == ~m_i~0;~m_st~0 := 0; 20644#L731-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 20604#L736-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 20605#L741-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 20633#L746-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 19702#L751-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 19703#L756-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 19808#L761-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 20053#L766-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 19979#L771-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 19704#L776-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 19363#L781-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 19364#L1036 assume !(0 == ~M_E~0); 19461#L1036-2 assume !(0 == ~T1_E~0); 20366#L1041-1 assume !(0 == ~T2_E~0); 20367#L1046-1 assume 0 == ~T3_E~0;~T3_E~0 := 1; 19738#L1051-1 assume !(0 == ~T4_E~0); 19739#L1056-1 assume !(0 == ~T5_E~0); 20495#L1061-1 assume !(0 == ~T6_E~0); 19633#L1066-1 assume !(0 == ~T7_E~0); 19634#L1071-1 assume !(0 == ~T8_E~0); 20477#L1076-1 assume !(0 == ~T9_E~0); 19523#L1081-1 assume !(0 == ~T10_E~0); 19524#L1086-1 assume 0 == ~E_M~0;~E_M~0 := 1; 19924#L1091-1 assume !(0 == ~E_1~0); 20652#L1096-1 assume !(0 == ~E_2~0); 20653#L1101-1 assume !(0 == ~E_3~0); 19992#L1106-1 assume !(0 == ~E_4~0); 19993#L1111-1 assume !(0 == ~E_5~0); 20157#L1116-1 assume !(0 == ~E_6~0); 20158#L1121-1 assume !(0 == ~E_7~0); 19983#L1126-1 assume 0 == ~E_8~0;~E_8~0 := 1; 19984#L1131-1 assume !(0 == ~E_9~0); 20259#L1136-1 assume !(0 == ~E_10~0); 20374#L1141-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 20523#L514 assume 1 == ~m_pc~0; 20488#L515 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 20001#L525 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 20002#is_master_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 20576#L1285 assume !(0 != activate_threads_~tmp~1#1); 20688#L1285-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 19655#L533 assume !(1 == ~t1_pc~0); 19656#L533-2 is_transmit1_triggered_~__retres1~1#1 := 0; 20172#L544 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 19418#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 19419#L1293 assume !(0 != activate_threads_~tmp___0~0#1); 20395#L1293-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 20396#L552 assume 1 == ~t2_pc~0; 19873#L553 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 19874#L563 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 19987#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 19988#L1301 assume !(0 != activate_threads_~tmp___1~0#1); 20019#L1301-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 20020#L571 assume 1 == ~t3_pc~0; 20212#L572 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 20213#L582 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 19361#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 19362#L1309 assume !(0 != activate_threads_~tmp___2~0#1); 20162#L1309-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 19447#L590 assume !(1 == ~t4_pc~0); 19448#L590-2 is_transmit4_triggered_~__retres1~4#1 := 0; 20221#L601 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 19541#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 19542#L1317 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 20423#L1317-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 20159#L609 assume 1 == ~t5_pc~0; 20160#L610 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 20685#L620 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 20577#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 20578#L1325 assume !(0 != activate_threads_~tmp___4~0#1); 20151#L1325-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 20152#L628 assume !(1 == ~t6_pc~0); 20084#L628-2 is_transmit6_triggered_~__retres1~6#1 := 0; 20083#L639 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 19963#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 19964#L1333 assume !(0 != activate_threads_~tmp___5~0#1); 20457#L1333-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 20458#L647 assume 1 == ~t7_pc~0; 19994#L648 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 19995#L658 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 20586#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 19999#L1341 assume !(0 != activate_threads_~tmp___6~0#1); 20000#L1341-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 20714#L666 assume !(1 == ~t8_pc~0); 19785#L666-2 is_transmit8_triggered_~__retres1~8#1 := 0; 19786#L677 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 20013#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 20184#L1349 assume !(0 != activate_threads_~tmp___7~0#1); 19922#L1349-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 19923#L685 assume 1 == ~t9_pc~0; 20693#L686 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 20594#L696 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 20047#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 19951#L1357 assume !(0 != activate_threads_~tmp___8~0#1); 19952#L1357-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 20337#L704 assume !(1 == ~t10_pc~0); 19941#L704-2 is_transmit10_triggered_~__retres1~10#1 := 0; 19940#L715 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 20202#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 19495#L1365 assume !(0 != activate_threads_~tmp___9~0#1); 19496#L1365-2 havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 19747#L1154 assume !(1 == ~M_E~0); 20445#L1154-2 assume !(1 == ~T1_E~0); 19721#L1159-1 assume !(1 == ~T2_E~0); 19722#L1164-1 assume !(1 == ~T3_E~0); 20181#L1169-1 assume !(1 == ~T4_E~0); 20048#L1174-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 19852#L1179-1 assume !(1 == ~T6_E~0); 19706#L1184-1 assume !(1 == ~T7_E~0); 19707#L1189-1 assume !(1 == ~T8_E~0); 19783#L1194-1 assume !(1 == ~T9_E~0); 19910#L1199-1 assume !(1 == ~T10_E~0); 19864#L1204-1 assume !(1 == ~E_M~0); 19865#L1209-1 assume !(1 == ~E_1~0); 20418#L1214-1 assume 1 == ~E_2~0;~E_2~0 := 2; 20419#L1219-1 assume !(1 == ~E_3~0); 20707#L1224-1 assume !(1 == ~E_4~0); 20206#L1229-1 assume !(1 == ~E_5~0); 19590#L1234-1 assume !(1 == ~E_6~0); 19591#L1239-1 assume !(1 == ~E_7~0); 19648#L1244-1 assume !(1 == ~E_8~0); 19649#L1249-1 assume !(1 == ~E_9~0); 20486#L1254-1 assume 1 == ~E_10~0;~E_10~0 := 2; 19490#L1259-1 assume { :end_inline_reset_delta_events } true; 19491#L1565-2 [2023-11-12 02:20:10,513 INFO L750 eck$LassoCheckResult]: Loop: 19491#L1565-2 assume !false; 20424#L1566 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 20190#L1011-1 assume !false; 20153#L862 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 19929#L794 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 19689#L851 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 20026#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 19718#L866 assume !(0 != eval_~tmp~0#1); 19720#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 20223#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 20224#L1036-3 assume 0 == ~M_E~0;~M_E~0 := 1; 20490#L1036-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 20670#L1041-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 20551#L1046-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 20552#L1051-3 assume !(0 == ~T4_E~0); 20491#L1056-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 19735#L1061-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 19736#L1066-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 19737#L1071-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 20671#L1076-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 19482#L1081-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 19483#L1086-3 assume 0 == ~E_M~0;~E_M~0 := 1; 19537#L1091-3 assume !(0 == ~E_1~0); 19538#L1096-3 assume 0 == ~E_2~0;~E_2~0 := 1; 20635#L1101-3 assume 0 == ~E_3~0;~E_3~0 := 1; 20636#L1106-3 assume 0 == ~E_4~0;~E_4~0 := 1; 20668#L1111-3 assume 0 == ~E_5~0;~E_5~0 := 1; 20627#L1116-3 assume 0 == ~E_6~0;~E_6~0 := 1; 20352#L1121-3 assume 0 == ~E_7~0;~E_7~0 := 1; 20353#L1126-3 assume 0 == ~E_8~0;~E_8~0 := 1; 20566#L1131-3 assume !(0 == ~E_9~0); 20567#L1136-3 assume 0 == ~E_10~0;~E_10~0 := 1; 20719#L1141-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 20354#L514-36 assume 1 == ~m_pc~0; 20355#L515-12 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 19899#L525-12 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 19900#is_master_triggered_returnLabel#13 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 20394#L1285-36 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 19792#L1285-38 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 19793#L533-36 assume 1 == ~t1_pc~0; 20072#L534-12 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 20166#L544-12 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 20617#is_transmit1_triggered_returnLabel#13 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 20432#L1293-36 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 20229#L1293-38 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 20230#L552-36 assume 1 == ~t2_pc~0; 19787#L553-12 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 19788#L563-12 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 20288#is_transmit2_triggered_returnLabel#13 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 20559#L1301-36 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 19759#L1301-38 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 19760#L571-36 assume 1 == ~t3_pc~0; 20147#L572-12 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 19850#L582-12 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 19851#is_transmit3_triggered_returnLabel#13 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 20043#L1309-36 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 20550#L1309-38 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 19822#L590-36 assume !(1 == ~t4_pc~0); 19824#L590-38 is_transmit4_triggered_~__retres1~4#1 := 0; 20446#L601-12 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 20239#is_transmit4_triggered_returnLabel#13 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 20240#L1317-36 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 20529#L1317-38 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 20530#L609-36 assume 1 == ~t5_pc~0; 20407#L610-12 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 20232#L620-12 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 20233#is_transmit5_triggered_returnLabel#13 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 20574#L1325-36 assume !(0 != activate_threads_~tmp___4~0#1); 20316#L1325-38 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 20123#L628-36 assume 1 == ~t6_pc~0; 19971#L629-12 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 19972#L639-12 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 20022#is_transmit6_triggered_returnLabel#13 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 20023#L1333-36 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 20357#L1333-38 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 20358#L647-36 assume 1 == ~t7_pc~0; 20281#L648-12 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 19509#L658-12 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 19510#is_transmit7_triggered_returnLabel#13 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 19527#L1341-36 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 19528#L1341-38 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 20447#L666-36 assume 1 == ~t8_pc~0; 19715#L667-12 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 19716#L677-12 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 20345#is_transmit8_triggered_returnLabel#13 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 20346#L1349-36 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 19870#L1349-38 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 19871#L685-36 assume !(1 == ~t9_pc~0); 19621#L685-38 is_transmit9_triggered_~__retres1~9#1 := 0; 19622#L696-12 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 20077#is_transmit9_triggered_returnLabel#13 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 20078#L1357-36 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 20010#L1357-38 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 20011#L704-36 assume 1 == ~t10_pc~0; 19609#L705-12 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 19610#L715-12 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 19931#is_transmit10_triggered_returnLabel#13 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 19932#L1365-36 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 19637#L1365-38 havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 19638#L1154-3 assume 1 == ~M_E~0;~M_E~0 := 2; 20621#L1154-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 20504#L1159-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 20505#L1164-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 20682#L1169-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 19937#L1174-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 19938#L1179-3 assume !(1 == ~T6_E~0); 20596#L1184-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 19511#L1189-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 19512#L1194-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 19881#L1199-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 19882#L1204-3 assume 1 == ~E_M~0;~E_M~0 := 2; 20201#L1209-3 assume 1 == ~E_1~0;~E_1~0 := 2; 19379#L1214-3 assume 1 == ~E_2~0;~E_2~0 := 2; 19380#L1219-3 assume !(1 == ~E_3~0); 20401#L1224-3 assume 1 == ~E_4~0;~E_4~0 := 2; 20402#L1229-3 assume 1 == ~E_5~0;~E_5~0 := 2; 20422#L1234-3 assume 1 == ~E_6~0;~E_6~0 := 2; 19650#L1239-3 assume 1 == ~E_7~0;~E_7~0 := 2; 19651#L1244-3 assume 1 == ~E_8~0;~E_8~0 := 2; 20252#L1249-3 assume 1 == ~E_9~0;~E_9~0 := 2; 20628#L1254-3 assume 1 == ~E_10~0;~E_10~0 := 2; 20405#L1259-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 20406#L794-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 19459#L851-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 19919#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret30#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret30#1;havoc start_simulation_#t~ret30#1; 19920#L1584 assume !(0 == start_simulation_~tmp~3#1); 20363#L1584-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret29#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 19664#L794-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 19359#L851-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 19411#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret29#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret29#1;havoc stop_simulation_#t~ret29#1; 19412#L1539 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 19990#L1546 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 20245#stop_simulation_returnLabel#1 start_simulation_#t~ret31#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret29#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret31#1;havoc start_simulation_#t~ret31#1; 20246#L1597 assume !(0 != start_simulation_~tmp___0~1#1); 19491#L1565-2 [2023-11-12 02:20:10,513 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-12 02:20:10,514 INFO L85 PathProgramCache]: Analyzing trace with hash -1913914371, now seen corresponding path program 1 times [2023-11-12 02:20:10,514 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-12 02:20:10,514 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [160493656] [2023-11-12 02:20:10,514 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-12 02:20:10,514 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-12 02:20:10,530 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-12 02:20:10,588 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-12 02:20:10,589 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-12 02:20:10,590 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [160493656] [2023-11-12 02:20:10,590 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [160493656] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-12 02:20:10,590 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-12 02:20:10,591 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-12 02:20:10,591 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [557302107] [2023-11-12 02:20:10,591 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-12 02:20:10,591 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-12 02:20:10,595 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-12 02:20:10,596 INFO L85 PathProgramCache]: Analyzing trace with hash -2062823821, now seen corresponding path program 1 times [2023-11-12 02:20:10,596 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-12 02:20:10,598 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [128569602] [2023-11-12 02:20:10,598 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-12 02:20:10,599 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-12 02:20:10,615 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-12 02:20:10,661 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-12 02:20:10,662 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-12 02:20:10,662 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [128569602] [2023-11-12 02:20:10,664 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [128569602] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-12 02:20:10,664 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-12 02:20:10,665 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-12 02:20:10,665 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1153150524] [2023-11-12 02:20:10,665 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-12 02:20:10,665 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-12 02:20:10,666 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-12 02:20:10,666 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-12 02:20:10,666 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-12 02:20:10,667 INFO L87 Difference]: Start difference. First operand 1377 states and 2037 transitions. cyclomatic complexity: 661 Second operand has 3 states, 3 states have (on average 42.666666666666664) internal successors, (128), 3 states have internal predecessors, (128), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-12 02:20:10,700 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-12 02:20:10,700 INFO L93 Difference]: Finished difference Result 1377 states and 2036 transitions. [2023-11-12 02:20:10,700 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1377 states and 2036 transitions. [2023-11-12 02:20:10,709 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1238 [2023-11-12 02:20:10,721 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1377 states to 1377 states and 2036 transitions. [2023-11-12 02:20:10,721 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1377 [2023-11-12 02:20:10,723 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1377 [2023-11-12 02:20:10,723 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1377 states and 2036 transitions. [2023-11-12 02:20:10,725 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-12 02:20:10,725 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1377 states and 2036 transitions. [2023-11-12 02:20:10,728 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1377 states and 2036 transitions. [2023-11-12 02:20:10,748 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1377 to 1377. [2023-11-12 02:20:10,751 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1377 states, 1377 states have (on average 1.478576615831518) internal successors, (2036), 1376 states have internal predecessors, (2036), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-12 02:20:10,757 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1377 states to 1377 states and 2036 transitions. [2023-11-12 02:20:10,757 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1377 states and 2036 transitions. [2023-11-12 02:20:10,757 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-12 02:20:10,760 INFO L428 stractBuchiCegarLoop]: Abstraction has 1377 states and 2036 transitions. [2023-11-12 02:20:10,760 INFO L335 stractBuchiCegarLoop]: ======== Iteration 9 ============ [2023-11-12 02:20:10,760 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1377 states and 2036 transitions. [2023-11-12 02:20:10,766 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1238 [2023-11-12 02:20:10,766 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-12 02:20:10,767 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-12 02:20:10,769 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-12 02:20:10,769 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-12 02:20:10,769 INFO L748 eck$LassoCheckResult]: Stem: 22524#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~token~0 := 0;~local~0 := 0; 22525#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~12#1;havoc main_~__retres1~12#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1; 23401#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret30#1, start_simulation_#t~ret31#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 23402#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 23464#L731 assume 1 == ~m_i~0;~m_st~0 := 0; 23405#L731-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 23365#L736-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 23366#L741-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 23394#L746-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 22461#L751-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 22462#L756-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 22569#L761-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 22814#L766-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 22740#L771-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 22463#L776-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 22124#L781-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 22125#L1036 assume !(0 == ~M_E~0); 22222#L1036-2 assume !(0 == ~T1_E~0); 23127#L1041-1 assume !(0 == ~T2_E~0); 23128#L1046-1 assume 0 == ~T3_E~0;~T3_E~0 := 1; 22499#L1051-1 assume !(0 == ~T4_E~0); 22500#L1056-1 assume !(0 == ~T5_E~0); 23256#L1061-1 assume !(0 == ~T6_E~0); 22394#L1066-1 assume !(0 == ~T7_E~0); 22395#L1071-1 assume !(0 == ~T8_E~0); 23238#L1076-1 assume !(0 == ~T9_E~0); 22284#L1081-1 assume !(0 == ~T10_E~0); 22285#L1086-1 assume 0 == ~E_M~0;~E_M~0 := 1; 22685#L1091-1 assume !(0 == ~E_1~0); 23412#L1096-1 assume !(0 == ~E_2~0); 23413#L1101-1 assume !(0 == ~E_3~0); 22753#L1106-1 assume !(0 == ~E_4~0); 22754#L1111-1 assume !(0 == ~E_5~0); 22918#L1116-1 assume !(0 == ~E_6~0); 22919#L1121-1 assume !(0 == ~E_7~0); 22744#L1126-1 assume 0 == ~E_8~0;~E_8~0 := 1; 22745#L1131-1 assume !(0 == ~E_9~0); 23020#L1136-1 assume !(0 == ~E_10~0); 23135#L1141-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 23284#L514 assume 1 == ~m_pc~0; 23249#L515 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 22762#L525 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 22763#is_master_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 23336#L1285 assume !(0 != activate_threads_~tmp~1#1); 23448#L1285-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 22413#L533 assume !(1 == ~t1_pc~0); 22414#L533-2 is_transmit1_triggered_~__retres1~1#1 := 0; 22933#L544 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 22177#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 22178#L1293 assume !(0 != activate_threads_~tmp___0~0#1); 23156#L1293-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 23157#L552 assume 1 == ~t2_pc~0; 22633#L553 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 22634#L563 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 22748#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 22749#L1301 assume !(0 != activate_threads_~tmp___1~0#1); 22775#L1301-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 22776#L571 assume 1 == ~t3_pc~0; 22971#L572 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 22972#L582 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 22122#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 22123#L1309 assume !(0 != activate_threads_~tmp___2~0#1); 22923#L1309-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 22208#L590 assume !(1 == ~t4_pc~0); 22209#L590-2 is_transmit4_triggered_~__retres1~4#1 := 0; 22981#L601 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 22302#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 22303#L1317 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 23183#L1317-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 22920#L609 assume 1 == ~t5_pc~0; 22921#L610 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 23446#L620 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 23338#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 23339#L1325 assume !(0 != activate_threads_~tmp___4~0#1); 22912#L1325-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 22913#L628 assume !(1 == ~t6_pc~0); 22845#L628-2 is_transmit6_triggered_~__retres1~6#1 := 0; 22844#L639 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 22721#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 22722#L1333 assume !(0 != activate_threads_~tmp___5~0#1); 23218#L1333-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 23219#L647 assume 1 == ~t7_pc~0; 22755#L648 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 22756#L658 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 23347#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 22758#L1341 assume !(0 != activate_threads_~tmp___6~0#1); 22759#L1341-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 23475#L666 assume !(1 == ~t8_pc~0); 22546#L666-2 is_transmit8_triggered_~__retres1~8#1 := 0; 22547#L677 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 22774#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 22944#L1349 assume !(0 != activate_threads_~tmp___7~0#1); 22682#L1349-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 22683#L685 assume 1 == ~t9_pc~0; 23454#L686 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 23355#L696 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 22808#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 22712#L1357 assume !(0 != activate_threads_~tmp___8~0#1); 22713#L1357-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 23098#L704 assume !(1 == ~t10_pc~0); 22702#L704-2 is_transmit10_triggered_~__retres1~10#1 := 0; 22701#L715 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 22962#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 22256#L1365 assume !(0 != activate_threads_~tmp___9~0#1); 22257#L1365-2 havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 22508#L1154 assume !(1 == ~M_E~0); 23206#L1154-2 assume !(1 == ~T1_E~0); 22482#L1159-1 assume !(1 == ~T2_E~0); 22483#L1164-1 assume !(1 == ~T3_E~0); 22942#L1169-1 assume !(1 == ~T4_E~0); 22809#L1174-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 22611#L1179-1 assume !(1 == ~T6_E~0); 22467#L1184-1 assume !(1 == ~T7_E~0); 22468#L1189-1 assume !(1 == ~T8_E~0); 22544#L1194-1 assume !(1 == ~T9_E~0); 22669#L1199-1 assume !(1 == ~T10_E~0); 22623#L1204-1 assume !(1 == ~E_M~0); 22624#L1209-1 assume !(1 == ~E_1~0); 23177#L1214-1 assume 1 == ~E_2~0;~E_2~0 := 2; 23178#L1219-1 assume !(1 == ~E_3~0); 23468#L1224-1 assume !(1 == ~E_4~0); 22966#L1229-1 assume !(1 == ~E_5~0); 22351#L1234-1 assume !(1 == ~E_6~0); 22352#L1239-1 assume !(1 == ~E_7~0); 22409#L1244-1 assume !(1 == ~E_8~0); 22410#L1249-1 assume !(1 == ~E_9~0); 23247#L1254-1 assume 1 == ~E_10~0;~E_10~0 := 2; 22251#L1259-1 assume { :end_inline_reset_delta_events } true; 22252#L1565-2 [2023-11-12 02:20:10,770 INFO L750 eck$LassoCheckResult]: Loop: 22252#L1565-2 assume !false; 23185#L1566 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 22950#L1011-1 assume !false; 22914#L862 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 22687#L794 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 22450#L851 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 22787#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 22474#L866 assume !(0 != eval_~tmp~0#1); 22476#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 22983#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 22984#L1036-3 assume 0 == ~M_E~0;~M_E~0 := 1; 23251#L1036-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 23430#L1041-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 23312#L1046-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 23313#L1051-3 assume !(0 == ~T4_E~0); 23252#L1056-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 22496#L1061-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 22497#L1066-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 22498#L1071-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 23432#L1076-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 22243#L1081-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 22244#L1086-3 assume 0 == ~E_M~0;~E_M~0 := 1; 22294#L1091-3 assume !(0 == ~E_1~0); 22295#L1096-3 assume 0 == ~E_2~0;~E_2~0 := 1; 23396#L1101-3 assume 0 == ~E_3~0;~E_3~0 := 1; 23397#L1106-3 assume 0 == ~E_4~0;~E_4~0 := 1; 23429#L1111-3 assume 0 == ~E_5~0;~E_5~0 := 1; 23388#L1116-3 assume 0 == ~E_6~0;~E_6~0 := 1; 23113#L1121-3 assume 0 == ~E_7~0;~E_7~0 := 1; 23114#L1126-3 assume 0 == ~E_8~0;~E_8~0 := 1; 23327#L1131-3 assume !(0 == ~E_9~0); 23328#L1136-3 assume 0 == ~E_10~0;~E_10~0 := 1; 23480#L1141-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 23116#L514-36 assume !(1 == ~m_pc~0); 22825#L514-38 is_master_triggered_~__retres1~0#1 := 0; 22660#L525-12 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 22661#is_master_triggered_returnLabel#13 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 23155#L1285-36 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 22553#L1285-38 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 22554#L533-36 assume 1 == ~t1_pc~0; 22834#L534-12 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 22927#L544-12 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 23378#is_transmit1_triggered_returnLabel#13 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 23193#L1293-36 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 22990#L1293-38 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 22991#L552-36 assume 1 == ~t2_pc~0; 22548#L553-12 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 22549#L563-12 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 23049#is_transmit2_triggered_returnLabel#13 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 23320#L1301-36 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 22520#L1301-38 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 22521#L571-36 assume 1 == ~t3_pc~0; 22908#L572-12 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 22612#L582-12 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 22613#is_transmit3_triggered_returnLabel#13 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 22804#L1309-36 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 23311#L1309-38 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 22583#L590-36 assume 1 == ~t4_pc~0; 22584#L591-12 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 23207#L601-12 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 23000#is_transmit4_triggered_returnLabel#13 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 23001#L1317-36 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 23290#L1317-38 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 23291#L609-36 assume 1 == ~t5_pc~0; 23168#L610-12 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 22993#L620-12 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 22994#is_transmit5_triggered_returnLabel#13 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 23335#L1325-36 assume !(0 != activate_threads_~tmp___4~0#1); 23077#L1325-38 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 22884#L628-36 assume 1 == ~t6_pc~0; 22732#L629-12 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 22733#L639-12 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 22783#is_transmit6_triggered_returnLabel#13 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 22784#L1333-36 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 23118#L1333-38 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 23119#L647-36 assume 1 == ~t7_pc~0; 23042#L648-12 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 22270#L658-12 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 22271#is_transmit7_triggered_returnLabel#13 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 22288#L1341-36 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 22289#L1341-38 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 23208#L666-36 assume !(1 == ~t8_pc~0); 22481#L666-38 is_transmit8_triggered_~__retres1~8#1 := 0; 22480#L677-12 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 23106#is_transmit8_triggered_returnLabel#13 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 23107#L1349-36 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 22631#L1349-38 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 22632#L685-36 assume 1 == ~t9_pc~0; 23093#L686-12 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 22383#L696-12 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 22838#is_transmit9_triggered_returnLabel#13 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 22839#L1357-36 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 22771#L1357-38 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 22772#L704-36 assume 1 == ~t10_pc~0; 22370#L705-12 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 22371#L715-12 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 22692#is_transmit10_triggered_returnLabel#13 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 22693#L1365-36 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 22398#L1365-38 havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 22399#L1154-3 assume 1 == ~M_E~0;~M_E~0 := 2; 23382#L1154-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 23265#L1159-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 23266#L1164-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 23443#L1169-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 22698#L1174-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 22699#L1179-3 assume !(1 == ~T6_E~0); 23357#L1184-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 22272#L1189-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 22273#L1194-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 22642#L1199-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 22643#L1204-3 assume 1 == ~E_M~0;~E_M~0 := 2; 22963#L1209-3 assume 1 == ~E_1~0;~E_1~0 := 2; 22140#L1214-3 assume 1 == ~E_2~0;~E_2~0 := 2; 22141#L1219-3 assume !(1 == ~E_3~0); 23162#L1224-3 assume 1 == ~E_4~0;~E_4~0 := 2; 23163#L1229-3 assume 1 == ~E_5~0;~E_5~0 := 2; 23184#L1234-3 assume 1 == ~E_6~0;~E_6~0 := 2; 22411#L1239-3 assume 1 == ~E_7~0;~E_7~0 := 2; 22412#L1244-3 assume 1 == ~E_8~0;~E_8~0 := 2; 23017#L1249-3 assume 1 == ~E_9~0;~E_9~0 := 2; 23389#L1254-3 assume 1 == ~E_10~0;~E_10~0 := 2; 23166#L1259-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 23167#L794-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 22220#L851-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 22680#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret30#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret30#1;havoc start_simulation_#t~ret30#1; 22681#L1584 assume !(0 == start_simulation_~tmp~3#1); 23124#L1584-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret29#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 22425#L794-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 22120#L851-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 22172#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret29#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret29#1;havoc stop_simulation_#t~ret29#1; 22173#L1539 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 22751#L1546 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 23006#stop_simulation_returnLabel#1 start_simulation_#t~ret31#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret29#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret31#1;havoc start_simulation_#t~ret31#1; 23007#L1597 assume !(0 != start_simulation_~tmp___0~1#1); 22252#L1565-2 [2023-11-12 02:20:10,771 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-12 02:20:10,771 INFO L85 PathProgramCache]: Analyzing trace with hash -1581271233, now seen corresponding path program 1 times [2023-11-12 02:20:10,771 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-12 02:20:10,771 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1685023067] [2023-11-12 02:20:10,771 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-12 02:20:10,772 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-12 02:20:10,785 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-12 02:20:10,821 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-12 02:20:10,822 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-12 02:20:10,822 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1685023067] [2023-11-12 02:20:10,822 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1685023067] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-12 02:20:10,822 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-12 02:20:10,822 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-12 02:20:10,823 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [596663236] [2023-11-12 02:20:10,823 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-12 02:20:10,823 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-12 02:20:10,824 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-12 02:20:10,824 INFO L85 PathProgramCache]: Analyzing trace with hash 369161907, now seen corresponding path program 1 times [2023-11-12 02:20:10,824 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-12 02:20:10,824 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1661706064] [2023-11-12 02:20:10,825 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-12 02:20:10,825 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-12 02:20:10,842 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-12 02:20:10,889 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-12 02:20:10,889 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-12 02:20:10,889 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1661706064] [2023-11-12 02:20:10,889 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1661706064] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-12 02:20:10,890 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-12 02:20:10,890 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-12 02:20:10,890 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1741190941] [2023-11-12 02:20:10,890 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-12 02:20:10,891 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-12 02:20:10,891 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-12 02:20:10,891 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-12 02:20:10,891 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-12 02:20:10,892 INFO L87 Difference]: Start difference. First operand 1377 states and 2036 transitions. cyclomatic complexity: 660 Second operand has 3 states, 3 states have (on average 42.666666666666664) internal successors, (128), 3 states have internal predecessors, (128), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-12 02:20:10,928 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-12 02:20:10,929 INFO L93 Difference]: Finished difference Result 1377 states and 2035 transitions. [2023-11-12 02:20:10,929 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1377 states and 2035 transitions. [2023-11-12 02:20:10,938 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1238 [2023-11-12 02:20:10,950 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1377 states to 1377 states and 2035 transitions. [2023-11-12 02:20:10,950 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1377 [2023-11-12 02:20:10,952 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1377 [2023-11-12 02:20:10,952 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1377 states and 2035 transitions. [2023-11-12 02:20:10,955 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-12 02:20:10,955 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1377 states and 2035 transitions. [2023-11-12 02:20:10,958 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1377 states and 2035 transitions. [2023-11-12 02:20:10,977 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1377 to 1377. [2023-11-12 02:20:10,981 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1377 states, 1377 states have (on average 1.4778503994190269) internal successors, (2035), 1376 states have internal predecessors, (2035), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-12 02:20:10,986 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1377 states to 1377 states and 2035 transitions. [2023-11-12 02:20:10,987 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1377 states and 2035 transitions. [2023-11-12 02:20:10,987 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-12 02:20:10,989 INFO L428 stractBuchiCegarLoop]: Abstraction has 1377 states and 2035 transitions. [2023-11-12 02:20:10,989 INFO L335 stractBuchiCegarLoop]: ======== Iteration 10 ============ [2023-11-12 02:20:10,989 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1377 states and 2035 transitions. [2023-11-12 02:20:10,995 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1238 [2023-11-12 02:20:10,995 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-12 02:20:10,995 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-12 02:20:10,998 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-12 02:20:10,998 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-12 02:20:10,998 INFO L748 eck$LassoCheckResult]: Stem: 25285#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~token~0 := 0;~local~0 := 0; 25286#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~12#1;havoc main_~__retres1~12#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1; 26162#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret30#1, start_simulation_#t~ret31#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 26163#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 26225#L731 assume 1 == ~m_i~0;~m_st~0 := 0; 26166#L731-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 26126#L736-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 26127#L741-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 26155#L746-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 25222#L751-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 25223#L756-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 25330#L761-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 25575#L766-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 25501#L771-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 25224#L776-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 24885#L781-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 24886#L1036 assume !(0 == ~M_E~0); 24983#L1036-2 assume !(0 == ~T1_E~0); 25888#L1041-1 assume !(0 == ~T2_E~0); 25889#L1046-1 assume 0 == ~T3_E~0;~T3_E~0 := 1; 25260#L1051-1 assume !(0 == ~T4_E~0); 25261#L1056-1 assume !(0 == ~T5_E~0); 26017#L1061-1 assume !(0 == ~T6_E~0); 25155#L1066-1 assume !(0 == ~T7_E~0); 25156#L1071-1 assume !(0 == ~T8_E~0); 25999#L1076-1 assume !(0 == ~T9_E~0); 25045#L1081-1 assume !(0 == ~T10_E~0); 25046#L1086-1 assume 0 == ~E_M~0;~E_M~0 := 1; 25446#L1091-1 assume !(0 == ~E_1~0); 26173#L1096-1 assume !(0 == ~E_2~0); 26174#L1101-1 assume !(0 == ~E_3~0); 25514#L1106-1 assume !(0 == ~E_4~0); 25515#L1111-1 assume !(0 == ~E_5~0); 25679#L1116-1 assume !(0 == ~E_6~0); 25680#L1121-1 assume !(0 == ~E_7~0); 25505#L1126-1 assume 0 == ~E_8~0;~E_8~0 := 1; 25506#L1131-1 assume !(0 == ~E_9~0); 25781#L1136-1 assume !(0 == ~E_10~0); 25896#L1141-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 26045#L514 assume 1 == ~m_pc~0; 26010#L515 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 25523#L525 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 25524#is_master_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 26097#L1285 assume !(0 != activate_threads_~tmp~1#1); 26209#L1285-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 25174#L533 assume !(1 == ~t1_pc~0); 25175#L533-2 is_transmit1_triggered_~__retres1~1#1 := 0; 25694#L544 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 24938#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 24939#L1293 assume !(0 != activate_threads_~tmp___0~0#1); 25917#L1293-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 25918#L552 assume 1 == ~t2_pc~0; 25394#L553 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 25395#L563 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 25509#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 25510#L1301 assume !(0 != activate_threads_~tmp___1~0#1); 25539#L1301-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 25540#L571 assume 1 == ~t3_pc~0; 25732#L572 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 25733#L582 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 24883#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 24884#L1309 assume !(0 != activate_threads_~tmp___2~0#1); 25684#L1309-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 24969#L590 assume !(1 == ~t4_pc~0); 24970#L590-2 is_transmit4_triggered_~__retres1~4#1 := 0; 25742#L601 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 25063#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 25064#L1317 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 25945#L1317-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 25681#L609 assume 1 == ~t5_pc~0; 25682#L610 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 26207#L620 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 26099#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 26100#L1325 assume !(0 != activate_threads_~tmp___4~0#1); 25673#L1325-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 25674#L628 assume !(1 == ~t6_pc~0); 25606#L628-2 is_transmit6_triggered_~__retres1~6#1 := 0; 25605#L639 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 25482#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 25483#L1333 assume !(0 != activate_threads_~tmp___5~0#1); 25979#L1333-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 25980#L647 assume 1 == ~t7_pc~0; 25516#L648 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 25517#L658 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 26108#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 25519#L1341 assume !(0 != activate_threads_~tmp___6~0#1); 25520#L1341-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 26236#L666 assume !(1 == ~t8_pc~0); 25307#L666-2 is_transmit8_triggered_~__retres1~8#1 := 0; 25308#L677 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 25535#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 25705#L1349 assume !(0 != activate_threads_~tmp___7~0#1); 25443#L1349-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 25444#L685 assume 1 == ~t9_pc~0; 26215#L686 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 26116#L696 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 25569#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 25473#L1357 assume !(0 != activate_threads_~tmp___8~0#1); 25474#L1357-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 25859#L704 assume !(1 == ~t10_pc~0); 25463#L704-2 is_transmit10_triggered_~__retres1~10#1 := 0; 25462#L715 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 25724#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 25017#L1365 assume !(0 != activate_threads_~tmp___9~0#1); 25018#L1365-2 havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 25269#L1154 assume !(1 == ~M_E~0); 25967#L1154-2 assume !(1 == ~T1_E~0); 25243#L1159-1 assume !(1 == ~T2_E~0); 25244#L1164-1 assume !(1 == ~T3_E~0); 25703#L1169-1 assume !(1 == ~T4_E~0); 25570#L1174-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 25372#L1179-1 assume !(1 == ~T6_E~0); 25228#L1184-1 assume !(1 == ~T7_E~0); 25229#L1189-1 assume !(1 == ~T8_E~0); 25305#L1194-1 assume !(1 == ~T9_E~0); 25430#L1199-1 assume !(1 == ~T10_E~0); 25384#L1204-1 assume !(1 == ~E_M~0); 25385#L1209-1 assume !(1 == ~E_1~0); 25940#L1214-1 assume 1 == ~E_2~0;~E_2~0 := 2; 25941#L1219-1 assume !(1 == ~E_3~0); 26229#L1224-1 assume !(1 == ~E_4~0); 25727#L1229-1 assume !(1 == ~E_5~0); 25112#L1234-1 assume !(1 == ~E_6~0); 25113#L1239-1 assume !(1 == ~E_7~0); 25170#L1244-1 assume !(1 == ~E_8~0); 25171#L1249-1 assume !(1 == ~E_9~0); 26008#L1254-1 assume 1 == ~E_10~0;~E_10~0 := 2; 25012#L1259-1 assume { :end_inline_reset_delta_events } true; 25013#L1565-2 [2023-11-12 02:20:10,999 INFO L750 eck$LassoCheckResult]: Loop: 25013#L1565-2 assume !false; 25946#L1566 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 25712#L1011-1 assume !false; 25675#L862 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 25448#L794 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 25211#L851 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 25548#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 25238#L866 assume !(0 != eval_~tmp~0#1); 25240#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 25744#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 25745#L1036-3 assume 0 == ~M_E~0;~M_E~0 := 1; 26012#L1036-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 26191#L1041-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 26073#L1046-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 26074#L1051-3 assume !(0 == ~T4_E~0); 26013#L1056-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 25257#L1061-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 25258#L1066-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 25259#L1071-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 26193#L1076-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 25004#L1081-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 25005#L1086-3 assume 0 == ~E_M~0;~E_M~0 := 1; 25055#L1091-3 assume !(0 == ~E_1~0); 25056#L1096-3 assume 0 == ~E_2~0;~E_2~0 := 1; 26157#L1101-3 assume 0 == ~E_3~0;~E_3~0 := 1; 26158#L1106-3 assume 0 == ~E_4~0;~E_4~0 := 1; 26190#L1111-3 assume 0 == ~E_5~0;~E_5~0 := 1; 26149#L1116-3 assume 0 == ~E_6~0;~E_6~0 := 1; 25874#L1121-3 assume 0 == ~E_7~0;~E_7~0 := 1; 25875#L1126-3 assume 0 == ~E_8~0;~E_8~0 := 1; 26088#L1131-3 assume !(0 == ~E_9~0); 26089#L1136-3 assume 0 == ~E_10~0;~E_10~0 := 1; 26241#L1141-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 25877#L514-36 assume !(1 == ~m_pc~0); 25586#L514-38 is_master_triggered_~__retres1~0#1 := 0; 25421#L525-12 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 25422#is_master_triggered_returnLabel#13 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 25916#L1285-36 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 25314#L1285-38 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 25315#L533-36 assume 1 == ~t1_pc~0; 25595#L534-12 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 25688#L544-12 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 26139#is_transmit1_triggered_returnLabel#13 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 25954#L1293-36 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 25751#L1293-38 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 25752#L552-36 assume 1 == ~t2_pc~0; 25309#L553-12 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 25310#L563-12 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 25810#is_transmit2_triggered_returnLabel#13 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 26081#L1301-36 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 25281#L1301-38 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 25282#L571-36 assume 1 == ~t3_pc~0; 25669#L572-12 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 25373#L582-12 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 25374#is_transmit3_triggered_returnLabel#13 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 25565#L1309-36 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 26072#L1309-38 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 25346#L590-36 assume 1 == ~t4_pc~0; 25347#L591-12 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 25968#L601-12 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 25762#is_transmit4_triggered_returnLabel#13 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 25763#L1317-36 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 26051#L1317-38 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 26052#L609-36 assume 1 == ~t5_pc~0; 25929#L610-12 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 25754#L620-12 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 25755#is_transmit5_triggered_returnLabel#13 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 26096#L1325-36 assume !(0 != activate_threads_~tmp___4~0#1); 25838#L1325-38 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 25645#L628-36 assume 1 == ~t6_pc~0; 25493#L629-12 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 25494#L639-12 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 25544#is_transmit6_triggered_returnLabel#13 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 25545#L1333-36 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 25879#L1333-38 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 25880#L647-36 assume 1 == ~t7_pc~0; 25803#L648-12 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 25031#L658-12 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 25032#is_transmit7_triggered_returnLabel#13 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 25049#L1341-36 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 25050#L1341-38 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 25969#L666-36 assume 1 == ~t8_pc~0; 25235#L667-12 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 25236#L677-12 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 25867#is_transmit8_triggered_returnLabel#13 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 25868#L1349-36 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 25392#L1349-38 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 25393#L685-36 assume !(1 == ~t9_pc~0); 25141#L685-38 is_transmit9_triggered_~__retres1~9#1 := 0; 25142#L696-12 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 25598#is_transmit9_triggered_returnLabel#13 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 25599#L1357-36 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 25532#L1357-38 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 25533#L704-36 assume 1 == ~t10_pc~0; 25131#L705-12 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 25132#L715-12 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 25453#is_transmit10_triggered_returnLabel#13 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 25454#L1365-36 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 25157#L1365-38 havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 25158#L1154-3 assume 1 == ~M_E~0;~M_E~0 := 2; 26143#L1154-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 26026#L1159-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 26027#L1164-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 26204#L1169-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 25459#L1174-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 25460#L1179-3 assume !(1 == ~T6_E~0); 26118#L1184-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 25033#L1189-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 25034#L1194-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 25403#L1199-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 25404#L1204-3 assume 1 == ~E_M~0;~E_M~0 := 2; 25723#L1209-3 assume 1 == ~E_1~0;~E_1~0 := 2; 24901#L1214-3 assume 1 == ~E_2~0;~E_2~0 := 2; 24902#L1219-3 assume !(1 == ~E_3~0); 25923#L1224-3 assume 1 == ~E_4~0;~E_4~0 := 2; 25924#L1229-3 assume 1 == ~E_5~0;~E_5~0 := 2; 25944#L1234-3 assume 1 == ~E_6~0;~E_6~0 := 2; 25172#L1239-3 assume 1 == ~E_7~0;~E_7~0 := 2; 25173#L1244-3 assume 1 == ~E_8~0;~E_8~0 := 2; 25774#L1249-3 assume 1 == ~E_9~0;~E_9~0 := 2; 26150#L1254-3 assume 1 == ~E_10~0;~E_10~0 := 2; 25927#L1259-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 25928#L794-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 24981#L851-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 25441#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret30#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret30#1;havoc start_simulation_#t~ret30#1; 25442#L1584 assume !(0 == start_simulation_~tmp~3#1); 25885#L1584-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret29#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 25186#L794-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 24881#L851-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 24933#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret29#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret29#1;havoc stop_simulation_#t~ret29#1; 24934#L1539 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 25511#L1546 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 25767#stop_simulation_returnLabel#1 start_simulation_#t~ret31#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret29#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret31#1;havoc start_simulation_#t~ret31#1; 25768#L1597 assume !(0 != start_simulation_~tmp___0~1#1); 25013#L1565-2 [2023-11-12 02:20:11,000 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-12 02:20:11,000 INFO L85 PathProgramCache]: Analyzing trace with hash 711809793, now seen corresponding path program 1 times [2023-11-12 02:20:11,000 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-12 02:20:11,000 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1019977220] [2023-11-12 02:20:11,000 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-12 02:20:11,001 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-12 02:20:11,022 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-12 02:20:11,124 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-12 02:20:11,124 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-12 02:20:11,125 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1019977220] [2023-11-12 02:20:11,125 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1019977220] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-12 02:20:11,125 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-12 02:20:11,125 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-12 02:20:11,125 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [703337656] [2023-11-12 02:20:11,125 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-12 02:20:11,127 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-12 02:20:11,127 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-12 02:20:11,127 INFO L85 PathProgramCache]: Analyzing trace with hash -1250501773, now seen corresponding path program 1 times [2023-11-12 02:20:11,127 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-12 02:20:11,127 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [974317554] [2023-11-12 02:20:11,128 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-12 02:20:11,128 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-12 02:20:11,145 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-12 02:20:11,190 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-12 02:20:11,190 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-12 02:20:11,191 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [974317554] [2023-11-12 02:20:11,191 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [974317554] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-12 02:20:11,191 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-12 02:20:11,191 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-12 02:20:11,191 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2027038640] [2023-11-12 02:20:11,191 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-12 02:20:11,192 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-12 02:20:11,192 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-12 02:20:11,192 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2023-11-12 02:20:11,192 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2023-11-12 02:20:11,193 INFO L87 Difference]: Start difference. First operand 1377 states and 2035 transitions. cyclomatic complexity: 659 Second operand has 4 states, 4 states have (on average 32.0) internal successors, (128), 3 states have internal predecessors, (128), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-12 02:20:11,388 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-12 02:20:11,389 INFO L93 Difference]: Finished difference Result 2536 states and 3734 transitions. [2023-11-12 02:20:11,389 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2536 states and 3734 transitions. [2023-11-12 02:20:11,405 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 2375 [2023-11-12 02:20:11,426 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2536 states to 2536 states and 3734 transitions. [2023-11-12 02:20:11,426 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2536 [2023-11-12 02:20:11,429 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2536 [2023-11-12 02:20:11,429 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2536 states and 3734 transitions. [2023-11-12 02:20:11,433 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-12 02:20:11,434 INFO L218 hiAutomatonCegarLoop]: Abstraction has 2536 states and 3734 transitions. [2023-11-12 02:20:11,438 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2536 states and 3734 transitions. [2023-11-12 02:20:11,479 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2536 to 2536. [2023-11-12 02:20:11,484 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2536 states, 2536 states have (on average 1.472397476340694) internal successors, (3734), 2535 states have internal predecessors, (3734), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-12 02:20:11,501 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2536 states to 2536 states and 3734 transitions. [2023-11-12 02:20:11,501 INFO L240 hiAutomatonCegarLoop]: Abstraction has 2536 states and 3734 transitions. [2023-11-12 02:20:11,502 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2023-11-12 02:20:11,502 INFO L428 stractBuchiCegarLoop]: Abstraction has 2536 states and 3734 transitions. [2023-11-12 02:20:11,502 INFO L335 stractBuchiCegarLoop]: ======== Iteration 11 ============ [2023-11-12 02:20:11,503 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2536 states and 3734 transitions. [2023-11-12 02:20:11,514 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 2375 [2023-11-12 02:20:11,514 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-12 02:20:11,514 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-12 02:20:11,516 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-12 02:20:11,517 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-12 02:20:11,517 INFO L748 eck$LassoCheckResult]: Stem: 29208#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~token~0 := 0;~local~0 := 0; 29209#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~12#1;havoc main_~__retres1~12#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1; 30090#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret30#1, start_simulation_#t~ret31#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 30091#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 30162#L731 assume 1 == ~m_i~0;~m_st~0 := 0; 30094#L731-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 30054#L736-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 30055#L741-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 30083#L746-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 29145#L751-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 29146#L756-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 29253#L761-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 29499#L766-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 29424#L771-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 29147#L776-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 28808#L781-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 28809#L1036 assume !(0 == ~M_E~0); 28906#L1036-2 assume !(0 == ~T1_E~0); 29813#L1041-1 assume !(0 == ~T2_E~0); 29814#L1046-1 assume !(0 == ~T3_E~0); 29183#L1051-1 assume !(0 == ~T4_E~0); 29184#L1056-1 assume !(0 == ~T5_E~0); 29944#L1061-1 assume !(0 == ~T6_E~0); 29078#L1066-1 assume !(0 == ~T7_E~0); 29079#L1071-1 assume !(0 == ~T8_E~0); 29926#L1076-1 assume !(0 == ~T9_E~0); 28968#L1081-1 assume !(0 == ~T10_E~0); 28969#L1086-1 assume 0 == ~E_M~0;~E_M~0 := 1; 29369#L1091-1 assume !(0 == ~E_1~0); 30101#L1096-1 assume !(0 == ~E_2~0); 30102#L1101-1 assume !(0 == ~E_3~0); 29437#L1106-1 assume !(0 == ~E_4~0); 29438#L1111-1 assume !(0 == ~E_5~0); 29604#L1116-1 assume !(0 == ~E_6~0); 29605#L1121-1 assume !(0 == ~E_7~0); 29428#L1126-1 assume 0 == ~E_8~0;~E_8~0 := 1; 29429#L1131-1 assume !(0 == ~E_9~0); 29706#L1136-1 assume !(0 == ~E_10~0); 29821#L1141-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 29972#L514 assume 1 == ~m_pc~0; 29937#L515 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 29446#L525 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 29447#is_master_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 30024#L1285 assume !(0 != activate_threads_~tmp~1#1); 30141#L1285-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 29097#L533 assume !(1 == ~t1_pc~0); 29098#L533-2 is_transmit1_triggered_~__retres1~1#1 := 0; 29619#L544 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 28861#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 28862#L1293 assume !(0 != activate_threads_~tmp___0~0#1); 29842#L1293-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 29843#L552 assume 1 == ~t2_pc~0; 29317#L553 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 29318#L563 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 29432#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 29433#L1301 assume !(0 != activate_threads_~tmp___1~0#1); 29459#L1301-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 29460#L571 assume 1 == ~t3_pc~0; 29657#L572 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 29658#L582 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 28806#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 28807#L1309 assume !(0 != activate_threads_~tmp___2~0#1); 29609#L1309-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 28892#L590 assume !(1 == ~t4_pc~0); 28893#L590-2 is_transmit4_triggered_~__retres1~4#1 := 0; 29667#L601 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 28986#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 28987#L1317 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 29869#L1317-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 29606#L609 assume 1 == ~t5_pc~0; 29607#L610 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 30139#L620 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 30026#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 30027#L1325 assume !(0 != activate_threads_~tmp___4~0#1); 29598#L1325-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 29599#L628 assume !(1 == ~t6_pc~0); 29531#L628-2 is_transmit6_triggered_~__retres1~6#1 := 0; 29530#L639 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 29405#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 29406#L1333 assume !(0 != activate_threads_~tmp___5~0#1); 29906#L1333-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 29907#L647 assume 1 == ~t7_pc~0; 29439#L648 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 29440#L658 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 30036#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 29442#L1341 assume !(0 != activate_threads_~tmp___6~0#1); 29443#L1341-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 30176#L666 assume !(1 == ~t8_pc~0); 29230#L666-2 is_transmit8_triggered_~__retres1~8#1 := 0; 29231#L677 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 29458#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 29630#L1349 assume !(0 != activate_threads_~tmp___7~0#1); 29366#L1349-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 29367#L685 assume 1 == ~t9_pc~0; 30150#L686 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 30044#L696 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 29493#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 29396#L1357 assume !(0 != activate_threads_~tmp___8~0#1); 29397#L1357-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 29784#L704 assume !(1 == ~t10_pc~0); 29386#L704-2 is_transmit10_triggered_~__retres1~10#1 := 0; 29385#L715 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 29648#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 28940#L1365 assume !(0 != activate_threads_~tmp___9~0#1); 28941#L1365-2 havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 29192#L1154 assume 1 == ~M_E~0;~M_E~0 := 2; 29893#L1154-2 assume !(1 == ~T1_E~0); 31020#L1159-1 assume !(1 == ~T2_E~0); 31018#L1164-1 assume !(1 == ~T3_E~0); 30184#L1169-1 assume !(1 == ~T4_E~0); 31015#L1174-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 31013#L1179-1 assume !(1 == ~T6_E~0); 31010#L1184-1 assume !(1 == ~T7_E~0); 31008#L1189-1 assume !(1 == ~T8_E~0); 31006#L1194-1 assume !(1 == ~T9_E~0); 31004#L1199-1 assume !(1 == ~T10_E~0); 30276#L1204-1 assume !(1 == ~E_M~0); 30264#L1209-1 assume !(1 == ~E_1~0); 30262#L1214-1 assume 1 == ~E_2~0;~E_2~0 := 2; 30260#L1219-1 assume !(1 == ~E_3~0); 30258#L1224-1 assume !(1 == ~E_4~0); 30256#L1229-1 assume !(1 == ~E_5~0); 30253#L1234-1 assume !(1 == ~E_6~0); 30251#L1239-1 assume !(1 == ~E_7~0); 30249#L1244-1 assume !(1 == ~E_8~0); 30248#L1249-1 assume !(1 == ~E_9~0); 30231#L1254-1 assume 1 == ~E_10~0;~E_10~0 := 2; 30222#L1259-1 assume { :end_inline_reset_delta_events } true; 30215#L1565-2 [2023-11-12 02:20:11,517 INFO L750 eck$LassoCheckResult]: Loop: 30215#L1565-2 assume !false; 30211#L1566 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 30207#L1011-1 assume !false; 30206#L862 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 30205#L794 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 30194#L851 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 30193#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 30191#L866 assume !(0 != eval_~tmp~0#1); 30190#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 30189#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 30188#L1036-3 assume 0 == ~M_E~0;~M_E~0 := 1; 30120#L1036-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 30121#L1041-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 30000#L1046-3 assume !(0 == ~T3_E~0); 30001#L1051-3 assume !(0 == ~T4_E~0); 29940#L1056-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 29180#L1061-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 29181#L1066-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 29182#L1071-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 30123#L1076-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 28927#L1081-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 28928#L1086-3 assume 0 == ~E_M~0;~E_M~0 := 1; 28978#L1091-3 assume !(0 == ~E_1~0); 28979#L1096-3 assume 0 == ~E_2~0;~E_2~0 := 1; 31000#L1101-3 assume 0 == ~E_3~0;~E_3~0 := 1; 30998#L1106-3 assume 0 == ~E_4~0;~E_4~0 := 1; 30996#L1111-3 assume 0 == ~E_5~0;~E_5~0 := 1; 30994#L1116-3 assume 0 == ~E_6~0;~E_6~0 := 1; 30992#L1121-3 assume 0 == ~E_7~0;~E_7~0 := 1; 30989#L1126-3 assume 0 == ~E_8~0;~E_8~0 := 1; 30987#L1131-3 assume !(0 == ~E_9~0); 30985#L1136-3 assume 0 == ~E_10~0;~E_10~0 := 1; 30983#L1141-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 30981#L514-36 assume !(1 == ~m_pc~0); 30978#L514-38 is_master_triggered_~__retres1~0#1 := 0; 30975#L525-12 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 30973#is_master_triggered_returnLabel#13 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 30971#L1285-36 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 30969#L1285-38 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 30967#L533-36 assume 1 == ~t1_pc~0; 30964#L534-12 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 30961#L544-12 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 30959#is_transmit1_triggered_returnLabel#13 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 30957#L1293-36 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 30955#L1293-38 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 30953#L552-36 assume !(1 == ~t2_pc~0); 30950#L552-38 is_transmit2_triggered_~__retres1~2#1 := 0; 30947#L563-12 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 30945#is_transmit2_triggered_returnLabel#13 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 30943#L1301-36 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 30941#L1301-38 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 30939#L571-36 assume 1 == ~t3_pc~0; 30936#L572-12 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 30933#L582-12 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 30931#is_transmit3_triggered_returnLabel#13 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 30929#L1309-36 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 30927#L1309-38 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 30925#L590-36 assume !(1 == ~t4_pc~0); 30922#L590-38 is_transmit4_triggered_~__retres1~4#1 := 0; 30919#L601-12 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 30917#is_transmit4_triggered_returnLabel#13 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 30915#L1317-36 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 30914#L1317-38 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 30913#L609-36 assume !(1 == ~t5_pc~0); 30912#L609-38 is_transmit5_triggered_~__retres1~5#1 := 0; 30910#L620-12 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 30909#is_transmit5_triggered_returnLabel#13 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 30908#L1325-36 assume !(0 != activate_threads_~tmp___4~0#1); 30907#L1325-38 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 30906#L628-36 assume 1 == ~t6_pc~0; 30904#L629-12 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 30903#L639-12 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 30902#is_transmit6_triggered_returnLabel#13 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 30901#L1333-36 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 30900#L1333-38 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 30899#L647-36 assume 1 == ~t7_pc~0; 30897#L648-12 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 30896#L658-12 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 30895#is_transmit7_triggered_returnLabel#13 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 30894#L1341-36 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 30893#L1341-38 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 30892#L666-36 assume 1 == ~t8_pc~0; 30889#L667-12 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 30887#L677-12 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 30885#is_transmit8_triggered_returnLabel#13 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 30883#L1349-36 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 30880#L1349-38 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 30878#L685-36 assume !(1 == ~t9_pc~0); 30875#L685-38 is_transmit9_triggered_~__retres1~9#1 := 0; 30873#L696-12 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 30871#is_transmit9_triggered_returnLabel#13 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 30869#L1357-36 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 30866#L1357-38 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 30864#L704-36 assume 1 == ~t10_pc~0; 30861#L705-12 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 30859#L715-12 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 30857#is_transmit10_triggered_returnLabel#13 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 30855#L1365-36 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 30852#L1365-38 havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 30850#L1154-3 assume 1 == ~M_E~0;~M_E~0 := 2; 30187#L1154-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 30847#L1159-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 30845#L1164-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 30185#L1169-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 30841#L1174-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 30839#L1179-3 assume !(1 == ~T6_E~0); 30837#L1184-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 30835#L1189-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 30833#L1194-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 30831#L1199-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 30828#L1204-3 assume 1 == ~E_M~0;~E_M~0 := 2; 30827#L1209-3 assume 1 == ~E_1~0;~E_1~0 := 2; 30826#L1214-3 assume 1 == ~E_2~0;~E_2~0 := 2; 30825#L1219-3 assume !(1 == ~E_3~0); 30824#L1224-3 assume 1 == ~E_4~0;~E_4~0 := 2; 30823#L1229-3 assume 1 == ~E_5~0;~E_5~0 := 2; 30822#L1234-3 assume 1 == ~E_6~0;~E_6~0 := 2; 30821#L1239-3 assume 1 == ~E_7~0;~E_7~0 := 2; 30820#L1244-3 assume 1 == ~E_8~0;~E_8~0 := 2; 30819#L1249-3 assume 1 == ~E_9~0;~E_9~0 := 2; 30818#L1254-3 assume 1 == ~E_10~0;~E_10~0 := 2; 30817#L1259-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 30719#L794-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 30717#L851-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 30715#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret30#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret30#1;havoc start_simulation_#t~ret30#1; 30671#L1584 assume !(0 == start_simulation_~tmp~3#1); 30181#L1584-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret29#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 30274#L794-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 30263#L851-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 30261#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret29#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret29#1;havoc stop_simulation_#t~ret29#1; 30259#L1539 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 30257#L1546 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 30232#stop_simulation_returnLabel#1 start_simulation_#t~ret31#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret29#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret31#1;havoc start_simulation_#t~ret31#1; 30223#L1597 assume !(0 != start_simulation_~tmp___0~1#1); 30215#L1565-2 [2023-11-12 02:20:11,518 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-12 02:20:11,518 INFO L85 PathProgramCache]: Analyzing trace with hash 1478663553, now seen corresponding path program 1 times [2023-11-12 02:20:11,518 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-12 02:20:11,518 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1721308287] [2023-11-12 02:20:11,519 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-12 02:20:11,519 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-12 02:20:11,533 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-12 02:20:11,599 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-12 02:20:11,599 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-12 02:20:11,600 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1721308287] [2023-11-12 02:20:11,600 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1721308287] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-12 02:20:11,600 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-12 02:20:11,600 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-12 02:20:11,600 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [184623635] [2023-11-12 02:20:11,600 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-12 02:20:11,601 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-12 02:20:11,601 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-12 02:20:11,601 INFO L85 PathProgramCache]: Analyzing trace with hash -1651803656, now seen corresponding path program 1 times [2023-11-12 02:20:11,601 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-12 02:20:11,602 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2100496455] [2023-11-12 02:20:11,602 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-12 02:20:11,602 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-12 02:20:11,629 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-12 02:20:11,713 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-12 02:20:11,713 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-12 02:20:11,713 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2100496455] [2023-11-12 02:20:11,713 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2100496455] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-12 02:20:11,714 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-12 02:20:11,714 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-12 02:20:11,714 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [306431665] [2023-11-12 02:20:11,714 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-12 02:20:11,715 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-12 02:20:11,715 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-12 02:20:11,716 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2023-11-12 02:20:11,716 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2023-11-12 02:20:11,716 INFO L87 Difference]: Start difference. First operand 2536 states and 3734 transitions. cyclomatic complexity: 1200 Second operand has 4 states, 4 states have (on average 32.0) internal successors, (128), 3 states have internal predecessors, (128), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-12 02:20:12,006 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-12 02:20:12,007 INFO L93 Difference]: Finished difference Result 4684 states and 6883 transitions. [2023-11-12 02:20:12,007 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 4684 states and 6883 transitions. [2023-11-12 02:20:12,039 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 4491 [2023-11-12 02:20:12,081 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 4684 states to 4684 states and 6883 transitions. [2023-11-12 02:20:12,082 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 4684 [2023-11-12 02:20:12,087 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 4684 [2023-11-12 02:20:12,088 INFO L73 IsDeterministic]: Start isDeterministic. Operand 4684 states and 6883 transitions. [2023-11-12 02:20:12,095 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-12 02:20:12,096 INFO L218 hiAutomatonCegarLoop]: Abstraction has 4684 states and 6883 transitions. [2023-11-12 02:20:12,103 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 4684 states and 6883 transitions. [2023-11-12 02:20:12,199 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 4684 to 4682. [2023-11-12 02:20:12,209 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 4682 states, 4682 states have (on average 1.4696710807347289) internal successors, (6881), 4681 states have internal predecessors, (6881), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-12 02:20:12,225 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 4682 states to 4682 states and 6881 transitions. [2023-11-12 02:20:12,225 INFO L240 hiAutomatonCegarLoop]: Abstraction has 4682 states and 6881 transitions. [2023-11-12 02:20:12,225 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2023-11-12 02:20:12,226 INFO L428 stractBuchiCegarLoop]: Abstraction has 4682 states and 6881 transitions. [2023-11-12 02:20:12,226 INFO L335 stractBuchiCegarLoop]: ======== Iteration 12 ============ [2023-11-12 02:20:12,226 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 4682 states and 6881 transitions. [2023-11-12 02:20:12,249 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 4491 [2023-11-12 02:20:12,249 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-12 02:20:12,249 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-12 02:20:12,251 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-12 02:20:12,252 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-12 02:20:12,252 INFO L748 eck$LassoCheckResult]: Stem: 36439#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~token~0 := 0;~local~0 := 0; 36440#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~12#1;havoc main_~__retres1~12#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1; 37389#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret30#1, start_simulation_#t~ret31#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 37390#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 37463#L731 assume 1 == ~m_i~0;~m_st~0 := 0; 37393#L731-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 37341#L736-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 37342#L741-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 37381#L746-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 36377#L751-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 36378#L756-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 36485#L761-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 36742#L766-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 36664#L771-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 36379#L776-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 36038#L781-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 36039#L1036 assume !(0 == ~M_E~0); 36136#L1036-2 assume !(0 == ~T1_E~0); 37070#L1041-1 assume !(0 == ~T2_E~0); 37071#L1046-1 assume !(0 == ~T3_E~0); 36414#L1051-1 assume !(0 == ~T4_E~0); 36415#L1056-1 assume !(0 == ~T5_E~0); 37209#L1061-1 assume !(0 == ~T6_E~0); 36308#L1066-1 assume !(0 == ~T7_E~0); 36309#L1071-1 assume !(0 == ~T8_E~0); 37190#L1076-1 assume !(0 == ~T9_E~0); 36198#L1081-1 assume !(0 == ~T10_E~0); 36199#L1086-1 assume !(0 == ~E_M~0); 36608#L1091-1 assume !(0 == ~E_1~0); 37401#L1096-1 assume !(0 == ~E_2~0); 37402#L1101-1 assume !(0 == ~E_3~0); 36677#L1106-1 assume !(0 == ~E_4~0); 36678#L1111-1 assume !(0 == ~E_5~0); 36854#L1116-1 assume !(0 == ~E_6~0); 36855#L1121-1 assume !(0 == ~E_7~0); 36668#L1126-1 assume 0 == ~E_8~0;~E_8~0 := 1; 36669#L1131-1 assume !(0 == ~E_9~0); 36960#L1136-1 assume !(0 == ~E_10~0); 37078#L1141-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 37245#L514 assume 1 == ~m_pc~0; 37201#L515 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 36686#L525 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 36687#is_master_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 37305#L1285 assume !(0 != activate_threads_~tmp~1#1); 37447#L1285-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 36330#L533 assume !(1 == ~t1_pc~0); 36331#L533-2 is_transmit1_triggered_~__retres1~1#1 := 0; 36869#L544 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 36093#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 36094#L1293 assume !(0 != activate_threads_~tmp___0~0#1); 37099#L1293-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 37100#L552 assume 1 == ~t2_pc~0; 36556#L553 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 36557#L563 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 36672#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 36673#L1301 assume !(0 != activate_threads_~tmp___1~0#1); 36706#L1301-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 36707#L571 assume 1 == ~t3_pc~0; 36913#L572 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 36914#L582 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 36036#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 36037#L1309 assume !(0 != activate_threads_~tmp___2~0#1); 36859#L1309-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 36122#L590 assume !(1 == ~t4_pc~0); 36123#L590-2 is_transmit4_triggered_~__retres1~4#1 := 0; 36922#L601 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 36216#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 36217#L1317 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 37131#L1317-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 36856#L609 assume 1 == ~t5_pc~0; 36857#L610 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 37442#L620 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 37306#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 37307#L1325 assume !(0 != activate_threads_~tmp___4~0#1); 36848#L1325-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 36849#L628 assume !(1 == ~t6_pc~0); 36776#L628-2 is_transmit6_triggered_~__retres1~6#1 := 0; 36775#L639 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 36648#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 36649#L1333 assume !(0 != activate_threads_~tmp___5~0#1); 37168#L1333-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 37169#L647 assume 1 == ~t7_pc~0; 36679#L648 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 36680#L658 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 37315#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 36684#L1341 assume !(0 != activate_threads_~tmp___6~0#1); 36685#L1341-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 37484#L666 assume !(1 == ~t8_pc~0); 36462#L666-2 is_transmit8_triggered_~__retres1~8#1 := 0; 36463#L677 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 36698#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 36883#L1349 assume !(0 != activate_threads_~tmp___7~0#1); 36606#L1349-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 36607#L685 assume 1 == ~t9_pc~0; 37450#L686 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 37330#L696 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 36735#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 36635#L1357 assume !(0 != activate_threads_~tmp___8~0#1); 36636#L1357-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 37040#L704 assume !(1 == ~t10_pc~0); 36625#L704-2 is_transmit10_triggered_~__retres1~10#1 := 0; 36624#L715 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 36903#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 36170#L1365 assume !(0 != activate_threads_~tmp___9~0#1); 36171#L1365-2 havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 36423#L1154 assume 1 == ~M_E~0;~M_E~0 := 2; 37154#L1154-2 assume !(1 == ~T1_E~0); 37470#L1159-1 assume !(1 == ~T2_E~0); 37496#L1164-1 assume !(1 == ~T3_E~0); 36879#L1169-1 assume !(1 == ~T4_E~0); 36880#L1174-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 36532#L1179-1 assume !(1 == ~T6_E~0); 36533#L1184-1 assume !(1 == ~T7_E~0); 36459#L1189-1 assume !(1 == ~T8_E~0); 36460#L1194-1 assume !(1 == ~T9_E~0); 37507#L1199-1 assume !(1 == ~T10_E~0); 37508#L1204-1 assume !(1 == ~E_M~0); 37580#L1209-1 assume !(1 == ~E_1~0); 37577#L1214-1 assume 1 == ~E_2~0;~E_2~0 := 2; 37575#L1219-1 assume !(1 == ~E_3~0); 37573#L1224-1 assume !(1 == ~E_4~0); 37571#L1229-1 assume !(1 == ~E_5~0); 37569#L1234-1 assume !(1 == ~E_6~0); 37565#L1239-1 assume !(1 == ~E_7~0); 37563#L1244-1 assume !(1 == ~E_8~0); 37561#L1249-1 assume !(1 == ~E_9~0); 37558#L1254-1 assume 1 == ~E_10~0;~E_10~0 := 2; 37548#L1259-1 assume { :end_inline_reset_delta_events } true; 37541#L1565-2 [2023-11-12 02:20:12,253 INFO L750 eck$LassoCheckResult]: Loop: 37541#L1565-2 assume !false; 37535#L1566 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 37531#L1011-1 assume !false; 37530#L862 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 37529#L794 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 37518#L851 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 37517#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 37515#L866 assume !(0 != eval_~tmp~0#1); 37514#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 37513#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 37512#L1036-3 assume 0 == ~M_E~0;~M_E~0 := 1; 37425#L1036-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 37426#L1041-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 37495#L1046-3 assume !(0 == ~T3_E~0); 39886#L1051-3 assume !(0 == ~T4_E~0); 37204#L1056-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 36411#L1061-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 36412#L1066-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 36413#L1071-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 37427#L1076-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 36157#L1081-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 36158#L1086-3 assume !(0 == ~E_M~0); 36212#L1091-3 assume !(0 == ~E_1~0); 36213#L1096-3 assume 0 == ~E_2~0;~E_2~0 := 1; 37383#L1101-3 assume 0 == ~E_3~0;~E_3~0 := 1; 37384#L1106-3 assume 0 == ~E_4~0;~E_4~0 := 1; 37423#L1111-3 assume 0 == ~E_5~0;~E_5~0 := 1; 37373#L1116-3 assume 0 == ~E_6~0;~E_6~0 := 1; 37055#L1121-3 assume 0 == ~E_7~0;~E_7~0 := 1; 37056#L1126-3 assume 0 == ~E_8~0;~E_8~0 := 1; 37294#L1131-3 assume !(0 == ~E_9~0); 37295#L1136-3 assume 0 == ~E_10~0;~E_10~0 := 1; 37492#L1141-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 37057#L514-36 assume 1 == ~m_pc~0; 37058#L515-12 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 36582#L525-12 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 36583#is_master_triggered_returnLabel#13 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 37098#L1285-36 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 36469#L1285-38 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 36470#L533-36 assume 1 == ~t1_pc~0; 36762#L534-12 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 36863#L544-12 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 37357#is_transmit1_triggered_returnLabel#13 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 37141#L1293-36 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 36930#L1293-38 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 36931#L552-36 assume 1 == ~t2_pc~0; 36464#L553-12 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 36465#L563-12 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 36989#is_transmit2_triggered_returnLabel#13 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 37286#L1301-36 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 36435#L1301-38 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 36436#L571-36 assume 1 == ~t3_pc~0; 36844#L572-12 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 36530#L582-12 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 36531#is_transmit3_triggered_returnLabel#13 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 36731#L1309-36 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 37277#L1309-38 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 36499#L590-36 assume 1 == ~t4_pc~0; 36500#L591-12 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 37156#L601-12 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 36940#is_transmit4_triggered_returnLabel#13 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 36941#L1317-36 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 37251#L1317-38 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 37252#L609-36 assume !(1 == ~t5_pc~0); 37418#L609-38 is_transmit5_triggered_~__retres1~5#1 := 0; 39832#L620-12 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 39831#is_transmit5_triggered_returnLabel#13 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 39830#L1325-36 assume !(0 != activate_threads_~tmp___4~0#1); 39829#L1325-38 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 39828#L628-36 assume 1 == ~t6_pc~0; 36656#L629-12 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 36657#L639-12 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 36709#is_transmit6_triggered_returnLabel#13 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 36710#L1333-36 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 37060#L1333-38 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 37061#L647-36 assume 1 == ~t7_pc~0; 36982#L648-12 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 36184#L658-12 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 36185#is_transmit7_triggered_returnLabel#13 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 36202#L1341-36 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 36203#L1341-38 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 37157#L666-36 assume 1 == ~t8_pc~0; 36391#L667-12 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 36392#L677-12 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 37048#is_transmit8_triggered_returnLabel#13 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 37049#L1349-36 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 36553#L1349-38 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 36554#L685-36 assume !(1 == ~t9_pc~0); 36296#L685-38 is_transmit9_triggered_~__retres1~9#1 := 0; 36297#L696-12 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 36769#is_transmit9_triggered_returnLabel#13 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 36770#L1357-36 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 38589#L1357-38 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 38586#L704-36 assume 1 == ~t10_pc~0; 38579#L705-12 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 38570#L715-12 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 36615#is_transmit10_triggered_returnLabel#13 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 36616#L1365-36 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 38562#L1365-38 havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 38557#L1154-3 assume 1 == ~M_E~0;~M_E~0 := 2; 37361#L1154-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 37362#L1159-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 38548#L1164-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 38544#L1169-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 38540#L1174-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 38534#L1179-3 assume !(1 == ~T6_E~0); 38530#L1184-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 38526#L1189-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 38522#L1194-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 36564#L1199-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 36565#L1204-3 assume 1 == ~E_M~0;~E_M~0 := 2; 38506#L1209-3 assume 1 == ~E_1~0;~E_1~0 := 2; 38503#L1214-3 assume 1 == ~E_2~0;~E_2~0 := 2; 38500#L1219-3 assume !(1 == ~E_3~0); 38497#L1224-3 assume 1 == ~E_4~0;~E_4~0 := 2; 38494#L1229-3 assume 1 == ~E_5~0;~E_5~0 := 2; 38491#L1234-3 assume 1 == ~E_6~0;~E_6~0 := 2; 38485#L1239-3 assume 1 == ~E_7~0;~E_7~0 := 2; 38480#L1244-3 assume 1 == ~E_8~0;~E_8~0 := 2; 38476#L1249-3 assume 1 == ~E_9~0;~E_9~0 := 2; 38472#L1254-3 assume 1 == ~E_10~0;~E_10~0 := 2; 38468#L1259-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 38065#L794-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 38052#L851-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 38041#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret30#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret30#1;havoc start_simulation_#t~ret30#1; 38029#L1584 assume !(0 == start_simulation_~tmp~3#1); 37491#L1584-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret29#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 37619#L794-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 37607#L851-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 37605#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret29#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret29#1;havoc stop_simulation_#t~ret29#1; 37603#L1539 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 37599#L1546 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 37596#stop_simulation_returnLabel#1 start_simulation_#t~ret31#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret29#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret31#1;havoc start_simulation_#t~ret31#1; 37549#L1597 assume !(0 != start_simulation_~tmp___0~1#1); 37541#L1565-2 [2023-11-12 02:20:12,253 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-12 02:20:12,254 INFO L85 PathProgramCache]: Analyzing trace with hash 171521155, now seen corresponding path program 1 times [2023-11-12 02:20:12,254 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-12 02:20:12,256 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1462014372] [2023-11-12 02:20:12,256 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-12 02:20:12,256 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-12 02:20:12,272 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-12 02:20:12,345 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-12 02:20:12,345 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-12 02:20:12,345 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1462014372] [2023-11-12 02:20:12,346 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1462014372] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-12 02:20:12,346 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-12 02:20:12,346 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-12 02:20:12,347 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2101580545] [2023-11-12 02:20:12,348 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-12 02:20:12,348 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-12 02:20:12,348 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-12 02:20:12,349 INFO L85 PathProgramCache]: Analyzing trace with hash 39360823, now seen corresponding path program 1 times [2023-11-12 02:20:12,349 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-12 02:20:12,349 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [10661451] [2023-11-12 02:20:12,349 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-12 02:20:12,349 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-12 02:20:12,392 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-12 02:20:12,442 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-12 02:20:12,442 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-12 02:20:12,442 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [10661451] [2023-11-12 02:20:12,442 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [10661451] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-12 02:20:12,443 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-12 02:20:12,443 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-12 02:20:12,443 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [485036343] [2023-11-12 02:20:12,443 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-12 02:20:12,444 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-12 02:20:12,444 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-12 02:20:12,444 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2023-11-12 02:20:12,444 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2023-11-12 02:20:12,454 INFO L87 Difference]: Start difference. First operand 4682 states and 6881 transitions. cyclomatic complexity: 2203 Second operand has 4 states, 4 states have (on average 32.0) internal successors, (128), 3 states have internal predecessors, (128), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-12 02:20:12,697 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-12 02:20:12,697 INFO L93 Difference]: Finished difference Result 8780 states and 12872 transitions. [2023-11-12 02:20:12,698 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 8780 states and 12872 transitions. [2023-11-12 02:20:12,749 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 8565 [2023-11-12 02:20:12,796 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 8780 states to 8780 states and 12872 transitions. [2023-11-12 02:20:12,796 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 8780 [2023-11-12 02:20:12,807 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 8780 [2023-11-12 02:20:12,807 INFO L73 IsDeterministic]: Start isDeterministic. Operand 8780 states and 12872 transitions. [2023-11-12 02:20:12,821 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-12 02:20:12,822 INFO L218 hiAutomatonCegarLoop]: Abstraction has 8780 states and 12872 transitions. [2023-11-12 02:20:12,833 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 8780 states and 12872 transitions. [2023-11-12 02:20:12,977 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 8780 to 8776. [2023-11-12 02:20:12,992 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 8776 states, 8776 states have (on average 1.466271649954421) internal successors, (12868), 8775 states have internal predecessors, (12868), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-12 02:20:13,091 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 8776 states to 8776 states and 12868 transitions. [2023-11-12 02:20:13,091 INFO L240 hiAutomatonCegarLoop]: Abstraction has 8776 states and 12868 transitions. [2023-11-12 02:20:13,091 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2023-11-12 02:20:13,092 INFO L428 stractBuchiCegarLoop]: Abstraction has 8776 states and 12868 transitions. [2023-11-12 02:20:13,092 INFO L335 stractBuchiCegarLoop]: ======== Iteration 13 ============ [2023-11-12 02:20:13,092 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 8776 states and 12868 transitions. [2023-11-12 02:20:13,144 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 8565 [2023-11-12 02:20:13,144 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-12 02:20:13,144 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-12 02:20:13,147 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-12 02:20:13,147 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-12 02:20:13,147 INFO L748 eck$LassoCheckResult]: Stem: 49914#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~token~0 := 0;~local~0 := 0; 49915#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~12#1;havoc main_~__retres1~12#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1; 50857#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret30#1, start_simulation_#t~ret31#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 50858#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 50935#L731 assume 1 == ~m_i~0;~m_st~0 := 0; 50861#L731-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 50816#L736-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 50817#L741-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 50848#L746-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 49849#L751-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 49850#L756-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 49960#L761-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 50216#L766-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 50137#L771-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 49851#L776-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 49510#L781-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 49511#L1036 assume !(0 == ~M_E~0); 49608#L1036-2 assume !(0 == ~T1_E~0); 50544#L1041-1 assume !(0 == ~T2_E~0); 50545#L1046-1 assume !(0 == ~T3_E~0); 49889#L1051-1 assume !(0 == ~T4_E~0); 49890#L1056-1 assume !(0 == ~T5_E~0); 50691#L1061-1 assume !(0 == ~T6_E~0); 49780#L1066-1 assume !(0 == ~T7_E~0); 49781#L1071-1 assume !(0 == ~T8_E~0); 50673#L1076-1 assume !(0 == ~T9_E~0); 49670#L1081-1 assume !(0 == ~T10_E~0); 49671#L1086-1 assume !(0 == ~E_M~0); 50080#L1091-1 assume !(0 == ~E_1~0); 50869#L1096-1 assume !(0 == ~E_2~0); 50870#L1101-1 assume !(0 == ~E_3~0); 50150#L1106-1 assume !(0 == ~E_4~0); 50151#L1111-1 assume !(0 == ~E_5~0); 50327#L1116-1 assume !(0 == ~E_6~0); 50328#L1121-1 assume !(0 == ~E_7~0); 50141#L1126-1 assume !(0 == ~E_8~0); 50142#L1131-1 assume !(0 == ~E_9~0); 50436#L1136-1 assume !(0 == ~E_10~0); 50553#L1141-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 50724#L514 assume 1 == ~m_pc~0; 50684#L515 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 50159#L525 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 50160#is_master_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 50780#L1285 assume !(0 != activate_threads_~tmp~1#1); 50911#L1285-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 49800#L533 assume !(1 == ~t1_pc~0); 49801#L533-2 is_transmit1_triggered_~__retres1~1#1 := 0; 50342#L544 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 49563#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 49564#L1293 assume !(0 != activate_threads_~tmp___0~0#1); 50576#L1293-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 50577#L552 assume 1 == ~t2_pc~0; 50026#L553 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 50027#L563 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 50145#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 50146#L1301 assume !(0 != activate_threads_~tmp___1~0#1); 50172#L1301-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 50173#L571 assume 1 == ~t3_pc~0; 50386#L572 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 50387#L582 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 49508#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 49509#L1309 assume !(0 != activate_threads_~tmp___2~0#1); 50332#L1309-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 49594#L590 assume !(1 == ~t4_pc~0); 49595#L590-2 is_transmit4_triggered_~__retres1~4#1 := 0; 50396#L601 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 49688#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 49689#L1317 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 50608#L1317-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 50329#L609 assume 1 == ~t5_pc~0; 50330#L610 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 50909#L620 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 50784#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 50785#L1325 assume !(0 != activate_threads_~tmp___4~0#1); 50321#L1325-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 50322#L628 assume !(1 == ~t6_pc~0); 50252#L628-2 is_transmit6_triggered_~__retres1~6#1 := 0; 50251#L639 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 50118#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 50119#L1333 assume !(0 != activate_threads_~tmp___5~0#1); 50650#L1333-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 50651#L647 assume 1 == ~t7_pc~0; 50152#L648 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 50153#L658 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 50794#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 50155#L1341 assume !(0 != activate_threads_~tmp___6~0#1); 50156#L1341-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 50952#L666 assume !(1 == ~t8_pc~0); 49937#L666-2 is_transmit8_triggered_~__retres1~8#1 := 0; 49938#L677 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 50171#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 50355#L1349 assume !(0 != activate_threads_~tmp___7~0#1); 50077#L1349-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 50078#L685 assume 1 == ~t9_pc~0; 50920#L686 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 50804#L696 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 50209#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 50107#L1357 assume !(0 != activate_threads_~tmp___8~0#1); 50108#L1357-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 50515#L704 assume !(1 == ~t10_pc~0); 50097#L704-2 is_transmit10_triggered_~__retres1~10#1 := 0; 50096#L715 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 50376#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 49642#L1365 assume !(0 != activate_threads_~tmp___9~0#1); 49643#L1365-2 havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 49898#L1154 assume 1 == ~M_E~0;~M_E~0 := 2; 50637#L1154-2 assume !(1 == ~T1_E~0); 50938#L1159-1 assume !(1 == ~T2_E~0); 50967#L1164-1 assume !(1 == ~T3_E~0); 50352#L1169-1 assume !(1 == ~T4_E~0); 50353#L1174-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 50002#L1179-1 assume !(1 == ~T6_E~0); 50003#L1184-1 assume !(1 == ~T7_E~0); 49934#L1189-1 assume !(1 == ~T8_E~0); 49935#L1194-1 assume !(1 == ~T9_E~0); 50981#L1199-1 assume !(1 == ~T10_E~0); 50982#L1204-1 assume !(1 == ~E_M~0); 51061#L1209-1 assume !(1 == ~E_1~0); 51057#L1214-1 assume 1 == ~E_2~0;~E_2~0 := 2; 51054#L1219-1 assume !(1 == ~E_3~0); 51051#L1224-1 assume !(1 == ~E_4~0); 51048#L1229-1 assume !(1 == ~E_5~0); 51045#L1234-1 assume !(1 == ~E_6~0); 51041#L1239-1 assume !(1 == ~E_7~0); 51038#L1244-1 assume !(1 == ~E_8~0); 51034#L1249-1 assume !(1 == ~E_9~0); 51031#L1254-1 assume 1 == ~E_10~0;~E_10~0 := 2; 51022#L1259-1 assume { :end_inline_reset_delta_events } true; 51015#L1565-2 [2023-11-12 02:20:13,148 INFO L750 eck$LassoCheckResult]: Loop: 51015#L1565-2 assume !false; 51009#L1566 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 51005#L1011-1 assume !false; 51004#L862 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 51003#L794 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 50992#L851 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 50991#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 50989#L866 assume !(0 != eval_~tmp~0#1); 50988#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 50987#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 50985#L1036-3 assume 0 == ~M_E~0;~M_E~0 := 1; 50986#L1036-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 53502#L1041-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 53500#L1046-3 assume !(0 == ~T3_E~0); 53498#L1051-3 assume !(0 == ~T4_E~0); 53496#L1056-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 53494#L1061-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 53491#L1066-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 53489#L1071-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 53487#L1076-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 53485#L1081-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 53483#L1086-3 assume !(0 == ~E_M~0); 53481#L1091-3 assume !(0 == ~E_1~0); 53478#L1096-3 assume 0 == ~E_2~0;~E_2~0 := 1; 53476#L1101-3 assume 0 == ~E_3~0;~E_3~0 := 1; 53474#L1106-3 assume 0 == ~E_4~0;~E_4~0 := 1; 53472#L1111-3 assume 0 == ~E_5~0;~E_5~0 := 1; 53470#L1116-3 assume 0 == ~E_6~0;~E_6~0 := 1; 53468#L1121-3 assume 0 == ~E_7~0;~E_7~0 := 1; 53465#L1126-3 assume !(0 == ~E_8~0); 53463#L1131-3 assume !(0 == ~E_9~0); 53461#L1136-3 assume 0 == ~E_10~0;~E_10~0 := 1; 53459#L1141-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 53158#L514-36 assume !(1 == ~m_pc~0); 53154#L514-38 is_master_triggered_~__retres1~0#1 := 0; 53152#L525-12 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 53150#is_master_triggered_returnLabel#13 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 53148#L1285-36 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 53146#L1285-38 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 53143#L533-36 assume 1 == ~t1_pc~0; 53139#L534-12 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 53136#L544-12 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 53134#is_transmit1_triggered_returnLabel#13 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 53132#L1293-36 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 53130#L1293-38 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 53128#L552-36 assume !(1 == ~t2_pc~0); 53125#L552-38 is_transmit2_triggered_~__retres1~2#1 := 0; 53124#L563-12 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 53121#is_transmit2_triggered_returnLabel#13 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 53119#L1301-36 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 53117#L1301-38 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 53115#L571-36 assume 1 == ~t3_pc~0; 53112#L572-12 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 53110#L582-12 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 53107#is_transmit3_triggered_returnLabel#13 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 53105#L1309-36 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 53103#L1309-38 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 53101#L590-36 assume !(1 == ~t4_pc~0); 53098#L590-38 is_transmit4_triggered_~__retres1~4#1 := 0; 53096#L601-12 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 53095#is_transmit4_triggered_returnLabel#13 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 53093#L1317-36 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 53090#L1317-38 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 53089#L609-36 assume 1 == ~t5_pc~0; 53086#L610-12 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 53084#L620-12 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 53082#is_transmit5_triggered_returnLabel#13 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 52624#L1325-36 assume !(0 != activate_threads_~tmp___4~0#1); 52620#L1325-38 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 52618#L628-36 assume 1 == ~t6_pc~0; 52615#L629-12 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 52614#L639-12 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 52613#is_transmit6_triggered_returnLabel#13 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 52610#L1333-36 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 52608#L1333-38 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 52606#L647-36 assume 1 == ~t7_pc~0; 52604#L648-12 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 52197#L658-12 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 52194#is_transmit7_triggered_returnLabel#13 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 52192#L1341-36 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 52190#L1341-38 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 52188#L666-36 assume 1 == ~t8_pc~0; 52185#L667-12 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 52183#L677-12 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 52180#is_transmit8_triggered_returnLabel#13 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 52178#L1349-36 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 52176#L1349-38 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 52174#L685-36 assume !(1 == ~t9_pc~0); 52168#L685-38 is_transmit9_triggered_~__retres1~9#1 := 0; 52166#L696-12 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 52164#is_transmit9_triggered_returnLabel#13 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 52162#L1357-36 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 52160#L1357-38 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 52158#L704-36 assume 1 == ~t10_pc~0; 52154#L705-12 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 52152#L715-12 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 52150#is_transmit10_triggered_returnLabel#13 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 52148#L1365-36 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 52146#L1365-38 havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 52144#L1154-3 assume 1 == ~M_E~0;~M_E~0 := 2; 50978#L1154-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 52141#L1159-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 52140#L1164-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 50971#L1169-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 52085#L1174-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 52079#L1179-3 assume !(1 == ~T6_E~0); 52069#L1184-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 52063#L1189-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 52057#L1194-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 52051#L1199-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 52045#L1204-3 assume 1 == ~E_M~0;~E_M~0 := 2; 52038#L1209-3 assume 1 == ~E_1~0;~E_1~0 := 2; 51436#L1214-3 assume 1 == ~E_2~0;~E_2~0 := 2; 51434#L1219-3 assume !(1 == ~E_3~0); 51177#L1224-3 assume 1 == ~E_4~0;~E_4~0 := 2; 51175#L1229-3 assume 1 == ~E_5~0;~E_5~0 := 2; 51166#L1234-3 assume 1 == ~E_6~0;~E_6~0 := 2; 51160#L1239-3 assume 1 == ~E_7~0;~E_7~0 := 2; 51155#L1244-3 assume 1 == ~E_8~0;~E_8~0 := 2; 51149#L1249-3 assume 1 == ~E_9~0;~E_9~0 := 2; 51145#L1254-3 assume 1 == ~E_10~0;~E_10~0 := 2; 51137#L1259-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 51121#L794-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 51118#L851-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 51115#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret30#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret30#1;havoc start_simulation_#t~ret30#1; 51112#L1584 assume !(0 == start_simulation_~tmp~3#1); 50962#L1584-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret29#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 51107#L794-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 51096#L851-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 51093#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret29#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret29#1;havoc stop_simulation_#t~ret29#1; 51091#L1539 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 51089#L1546 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 51087#stop_simulation_returnLabel#1 start_simulation_#t~ret31#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret29#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret31#1;havoc start_simulation_#t~ret31#1; 51023#L1597 assume !(0 != start_simulation_~tmp___0~1#1); 51015#L1565-2 [2023-11-12 02:20:13,148 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-12 02:20:13,149 INFO L85 PathProgramCache]: Analyzing trace with hash -711987835, now seen corresponding path program 1 times [2023-11-12 02:20:13,149 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-12 02:20:13,149 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [897518966] [2023-11-12 02:20:13,149 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-12 02:20:13,149 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-12 02:20:13,176 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-12 02:20:13,237 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-12 02:20:13,237 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-12 02:20:13,238 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [897518966] [2023-11-12 02:20:13,238 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [897518966] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-12 02:20:13,238 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-12 02:20:13,238 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2023-11-12 02:20:13,238 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [485783373] [2023-11-12 02:20:13,239 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-12 02:20:13,239 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-12 02:20:13,239 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-12 02:20:13,240 INFO L85 PathProgramCache]: Analyzing trace with hash -2145863301, now seen corresponding path program 1 times [2023-11-12 02:20:13,240 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-12 02:20:13,240 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [702166128] [2023-11-12 02:20:13,240 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-12 02:20:13,240 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-12 02:20:13,257 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-12 02:20:13,300 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-12 02:20:13,300 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-12 02:20:13,300 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [702166128] [2023-11-12 02:20:13,301 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [702166128] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-12 02:20:13,301 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-12 02:20:13,301 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-12 02:20:13,301 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1132962126] [2023-11-12 02:20:13,301 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-12 02:20:13,302 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-12 02:20:13,302 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-12 02:20:13,302 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-12 02:20:13,303 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-12 02:20:13,303 INFO L87 Difference]: Start difference. First operand 8776 states and 12868 transitions. cyclomatic complexity: 4100 Second operand has 3 states, 3 states have (on average 42.666666666666664) internal successors, (128), 2 states have internal predecessors, (128), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-12 02:20:13,546 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-12 02:20:13,546 INFO L93 Difference]: Finished difference Result 17187 states and 25003 transitions. [2023-11-12 02:20:13,546 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 17187 states and 25003 transitions. [2023-11-12 02:20:13,629 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 16969 [2023-11-12 02:20:13,693 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 17187 states to 17187 states and 25003 transitions. [2023-11-12 02:20:13,693 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 17187 [2023-11-12 02:20:13,711 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 17187 [2023-11-12 02:20:13,711 INFO L73 IsDeterministic]: Start isDeterministic. Operand 17187 states and 25003 transitions. [2023-11-12 02:20:13,732 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-12 02:20:13,733 INFO L218 hiAutomatonCegarLoop]: Abstraction has 17187 states and 25003 transitions. [2023-11-12 02:20:13,755 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 17187 states and 25003 transitions. [2023-11-12 02:20:14,132 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 17187 to 16579. [2023-11-12 02:20:14,160 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 16579 states, 16579 states have (on average 1.4564810905362204) internal successors, (24147), 16578 states have internal predecessors, (24147), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-12 02:20:14,223 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 16579 states to 16579 states and 24147 transitions. [2023-11-12 02:20:14,224 INFO L240 hiAutomatonCegarLoop]: Abstraction has 16579 states and 24147 transitions. [2023-11-12 02:20:14,224 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-12 02:20:14,225 INFO L428 stractBuchiCegarLoop]: Abstraction has 16579 states and 24147 transitions. [2023-11-12 02:20:14,226 INFO L335 stractBuchiCegarLoop]: ======== Iteration 14 ============ [2023-11-12 02:20:14,226 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 16579 states and 24147 transitions. [2023-11-12 02:20:14,296 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 16361 [2023-11-12 02:20:14,296 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-12 02:20:14,296 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-12 02:20:14,299 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-12 02:20:14,299 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-12 02:20:14,300 INFO L748 eck$LassoCheckResult]: Stem: 75894#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~token~0 := 0;~local~0 := 0; 75895#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~12#1;havoc main_~__retres1~12#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1; 76917#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret30#1, start_simulation_#t~ret31#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 76918#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 77024#L731 assume 1 == ~m_i~0;~m_st~0 := 0; 76924#L731-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 76860#L736-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 76861#L741-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 76909#L746-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 75824#L751-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 75825#L756-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 75941#L761-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 76200#L766-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 76124#L771-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 75826#L776-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 75480#L781-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 75481#L1036 assume !(0 == ~M_E~0); 75578#L1036-2 assume !(0 == ~T1_E~0); 76542#L1041-1 assume !(0 == ~T2_E~0); 76543#L1046-1 assume !(0 == ~T3_E~0); 75868#L1051-1 assume !(0 == ~T4_E~0); 75869#L1056-1 assume !(0 == ~T5_E~0); 76696#L1061-1 assume !(0 == ~T6_E~0); 75752#L1066-1 assume !(0 == ~T7_E~0); 75753#L1071-1 assume !(0 == ~T8_E~0); 76679#L1076-1 assume !(0 == ~T9_E~0); 75639#L1081-1 assume !(0 == ~T10_E~0); 75640#L1086-1 assume !(0 == ~E_M~0); 76066#L1091-1 assume !(0 == ~E_1~0); 76933#L1096-1 assume !(0 == ~E_2~0); 76934#L1101-1 assume !(0 == ~E_3~0); 76137#L1106-1 assume !(0 == ~E_4~0); 76138#L1111-1 assume !(0 == ~E_5~0); 76311#L1116-1 assume !(0 == ~E_6~0); 76312#L1121-1 assume !(0 == ~E_7~0); 76128#L1126-1 assume !(0 == ~E_8~0); 76129#L1131-1 assume !(0 == ~E_9~0); 76420#L1136-1 assume !(0 == ~E_10~0); 76555#L1141-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 76740#L514 assume !(1 == ~m_pc~0); 76741#L514-2 is_master_triggered_~__retres1~0#1 := 0; 76146#L525 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 76147#is_master_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 76819#L1285 assume !(0 != activate_threads_~tmp~1#1); 76993#L1285-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 75775#L533 assume !(1 == ~t1_pc~0); 75776#L533-2 is_transmit1_triggered_~__retres1~1#1 := 0; 76327#L544 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 75535#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 75536#L1293 assume !(0 != activate_threads_~tmp___0~0#1); 76583#L1293-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 76584#L552 assume 1 == ~t2_pc~0; 76011#L553 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 76012#L563 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 76132#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 76133#L1301 assume !(0 != activate_threads_~tmp___1~0#1); 76166#L1301-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 76167#L571 assume 1 == ~t3_pc~0; 76370#L572 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 76371#L582 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 75478#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 75479#L1309 assume !(0 != activate_threads_~tmp___2~0#1); 76317#L1309-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 75564#L590 assume !(1 == ~t4_pc~0); 75565#L590-2 is_transmit4_triggered_~__retres1~4#1 := 0; 76380#L601 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 75657#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 75658#L1317 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 76616#L1317-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 76313#L609 assume 1 == ~t5_pc~0; 76314#L610 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 76986#L620 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 76820#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 76821#L1325 assume !(0 != activate_threads_~tmp___4~0#1); 76305#L1325-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 76306#L628 assume !(1 == ~t6_pc~0); 76234#L628-2 is_transmit6_triggered_~__retres1~6#1 := 0; 76233#L639 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 76107#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 76108#L1333 assume !(0 != activate_threads_~tmp___5~0#1); 76658#L1333-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 76659#L647 assume 1 == ~t7_pc~0; 76139#L648 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 76140#L658 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 76830#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 76144#L1341 assume !(0 != activate_threads_~tmp___6~0#1); 76145#L1341-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 77056#L666 assume !(1 == ~t8_pc~0); 75917#L666-2 is_transmit8_triggered_~__retres1~8#1 := 0; 75918#L677 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 76159#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 76340#L1349 assume !(0 != activate_threads_~tmp___7~0#1); 76063#L1349-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 76064#L685 assume 1 == ~t9_pc~0; 77004#L686 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 76841#L696 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 76194#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 76092#L1357 assume !(0 != activate_threads_~tmp___8~0#1); 76093#L1357-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 76510#L704 assume !(1 == ~t10_pc~0); 76082#L704-2 is_transmit10_triggered_~__retres1~10#1 := 0; 76081#L715 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 76360#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 75611#L1365 assume !(0 != activate_threads_~tmp___9~0#1); 75612#L1365-2 havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 75876#L1154 assume 1 == ~M_E~0;~M_E~0 := 2; 76645#L1154-2 assume !(1 == ~T1_E~0); 75845#L1159-1 assume !(1 == ~T2_E~0); 75846#L1164-1 assume !(1 == ~T3_E~0); 76337#L1169-1 assume !(1 == ~T4_E~0); 76195#L1174-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 75990#L1179-1 assume !(1 == ~T6_E~0); 75830#L1184-1 assume !(1 == ~T7_E~0); 75831#L1189-1 assume !(1 == ~T8_E~0); 75915#L1194-1 assume !(1 == ~T9_E~0); 76050#L1199-1 assume !(1 == ~T10_E~0); 76002#L1204-1 assume !(1 == ~E_M~0); 76003#L1209-1 assume !(1 == ~E_1~0); 77051#L1214-1 assume 1 == ~E_2~0;~E_2~0 := 2; 78117#L1219-1 assume !(1 == ~E_3~0); 78087#L1224-1 assume !(1 == ~E_4~0); 78052#L1229-1 assume !(1 == ~E_5~0); 78050#L1234-1 assume !(1 == ~E_6~0); 78029#L1239-1 assume !(1 == ~E_7~0); 78013#L1244-1 assume !(1 == ~E_8~0); 77998#L1249-1 assume !(1 == ~E_9~0); 77986#L1254-1 assume 1 == ~E_10~0;~E_10~0 := 2; 77977#L1259-1 assume { :end_inline_reset_delta_events } true; 77970#L1565-2 [2023-11-12 02:20:14,300 INFO L750 eck$LassoCheckResult]: Loop: 77970#L1565-2 assume !false; 77964#L1566 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 77960#L1011-1 assume !false; 77959#L862 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 77958#L794 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 77947#L851 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 77946#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 77944#L866 assume !(0 != eval_~tmp~0#1); 77943#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 77942#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 77939#L1036-3 assume 0 == ~M_E~0;~M_E~0 := 1; 77940#L1036-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 80858#L1041-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 80165#L1046-3 assume !(0 == ~T3_E~0); 80163#L1051-3 assume !(0 == ~T4_E~0); 80160#L1056-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 80158#L1061-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 80156#L1066-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 80154#L1071-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 80152#L1076-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 80150#L1081-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 80147#L1086-3 assume !(0 == ~E_M~0); 77913#L1091-3 assume !(0 == ~E_1~0); 77912#L1096-3 assume 0 == ~E_2~0;~E_2~0 := 1; 77836#L1101-3 assume 0 == ~E_3~0;~E_3~0 := 1; 77808#L1106-3 assume 0 == ~E_4~0;~E_4~0 := 1; 77806#L1111-3 assume 0 == ~E_5~0;~E_5~0 := 1; 77803#L1116-3 assume 0 == ~E_6~0;~E_6~0 := 1; 77801#L1121-3 assume 0 == ~E_7~0;~E_7~0 := 1; 77799#L1126-3 assume !(0 == ~E_8~0); 77798#L1131-3 assume !(0 == ~E_9~0); 77744#L1136-3 assume 0 == ~E_10~0;~E_10~0 := 1; 77743#L1141-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 76530#L514-36 assume !(1 == ~m_pc~0); 76531#L514-38 is_master_triggered_~__retres1~0#1 := 0; 79640#L525-12 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 79638#is_master_triggered_returnLabel#13 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 79636#L1285-36 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 79633#L1285-38 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 79631#L533-36 assume !(1 == ~t1_pc~0); 79629#L533-38 is_transmit1_triggered_~__retres1~1#1 := 0; 79626#L544-12 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 79624#is_transmit1_triggered_returnLabel#13 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 79623#L1293-36 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 79622#L1293-38 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 79621#L552-36 assume !(1 == ~t2_pc~0); 79619#L552-38 is_transmit2_triggered_~__retres1~2#1 := 0; 79617#L563-12 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 79615#is_transmit2_triggered_returnLabel#13 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 79613#L1301-36 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 79611#L1301-38 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 79609#L571-36 assume !(1 == ~t3_pc~0); 79607#L571-38 is_transmit3_triggered_~__retres1~3#1 := 0; 79604#L582-12 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 79602#is_transmit3_triggered_returnLabel#13 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 79600#L1309-36 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 79598#L1309-38 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 79596#L590-36 assume !(1 == ~t4_pc~0); 79593#L590-38 is_transmit4_triggered_~__retres1~4#1 := 0; 79589#L601-12 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 79587#is_transmit4_triggered_returnLabel#13 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 79361#L1317-36 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 79132#L1317-38 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 79131#L609-36 assume !(1 == ~t5_pc~0); 78969#L609-38 is_transmit5_triggered_~__retres1~5#1 := 0; 78966#L620-12 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 78964#is_transmit5_triggered_returnLabel#13 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 78962#L1325-36 assume !(0 != activate_threads_~tmp___4~0#1); 78960#L1325-38 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 78958#L628-36 assume 1 == ~t6_pc~0; 78955#L629-12 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 78953#L639-12 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 78951#is_transmit6_triggered_returnLabel#13 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 78928#L1333-36 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 78865#L1333-38 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 78697#L647-36 assume !(1 == ~t7_pc~0); 78695#L647-38 is_transmit7_triggered_~__retres1~7#1 := 0; 78692#L658-12 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 78691#is_transmit7_triggered_returnLabel#13 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 78689#L1341-36 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 78687#L1341-38 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 78685#L666-36 assume 1 == ~t8_pc~0; 78679#L667-12 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 78677#L677-12 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 78675#is_transmit8_triggered_returnLabel#13 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 78673#L1349-36 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 78671#L1349-38 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 78669#L685-36 assume 1 == ~t9_pc~0; 78559#L686-12 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 78556#L696-12 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 78554#is_transmit9_triggered_returnLabel#13 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 78552#L1357-36 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 78550#L1357-38 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 78465#L704-36 assume !(1 == ~t10_pc~0); 78463#L704-38 is_transmit10_triggered_~__retres1~10#1 := 0; 78460#L715-12 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 78458#is_transmit10_triggered_returnLabel#13 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 78428#L1365-36 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 78419#L1365-38 havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 78410#L1154-3 assume 1 == ~M_E~0;~M_E~0 := 2; 78401#L1154-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 78392#L1159-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 78383#L1164-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 78369#L1169-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 78364#L1174-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 78359#L1179-3 assume !(1 == ~T6_E~0); 78354#L1184-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 78349#L1189-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 78344#L1194-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 78338#L1199-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 78333#L1204-3 assume 1 == ~E_M~0;~E_M~0 := 2; 78326#L1209-3 assume 1 == ~E_1~0;~E_1~0 := 2; 78323#L1214-3 assume 1 == ~E_2~0;~E_2~0 := 2; 78320#L1219-3 assume !(1 == ~E_3~0); 78317#L1224-3 assume 1 == ~E_4~0;~E_4~0 := 2; 78313#L1229-3 assume 1 == ~E_5~0;~E_5~0 := 2; 78310#L1234-3 assume 1 == ~E_6~0;~E_6~0 := 2; 78307#L1239-3 assume 1 == ~E_7~0;~E_7~0 := 2; 78304#L1244-3 assume 1 == ~E_8~0;~E_8~0 := 2; 78300#L1249-3 assume 1 == ~E_9~0;~E_9~0 := 2; 78298#L1254-3 assume 1 == ~E_10~0;~E_10~0 := 2; 78295#L1259-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 78283#L794-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 78281#L851-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 78280#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret30#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret30#1;havoc start_simulation_#t~ret30#1; 78112#L1584 assume !(0 == start_simulation_~tmp~3#1); 77937#L1584-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret29#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 78062#L794-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 78051#L851-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 78030#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret29#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret29#1;havoc stop_simulation_#t~ret29#1; 78014#L1539 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 77999#L1546 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 77987#stop_simulation_returnLabel#1 start_simulation_#t~ret31#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret29#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret31#1;havoc start_simulation_#t~ret31#1; 77978#L1597 assume !(0 != start_simulation_~tmp___0~1#1); 77970#L1565-2 [2023-11-12 02:20:14,301 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-12 02:20:14,301 INFO L85 PathProgramCache]: Analyzing trace with hash -2098669114, now seen corresponding path program 1 times [2023-11-12 02:20:14,301 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-12 02:20:14,301 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [697287621] [2023-11-12 02:20:14,302 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-12 02:20:14,303 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-12 02:20:14,322 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-12 02:20:14,521 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-12 02:20:14,521 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-12 02:20:14,522 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [697287621] [2023-11-12 02:20:14,522 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [697287621] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-12 02:20:14,522 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-12 02:20:14,522 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-12 02:20:14,522 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1735547519] [2023-11-12 02:20:14,522 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-12 02:20:14,524 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-12 02:20:14,525 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-12 02:20:14,525 INFO L85 PathProgramCache]: Analyzing trace with hash -956504769, now seen corresponding path program 1 times [2023-11-12 02:20:14,525 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-12 02:20:14,525 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1797109902] [2023-11-12 02:20:14,525 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-12 02:20:14,526 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-12 02:20:14,545 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-12 02:20:14,590 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-12 02:20:14,590 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-12 02:20:14,591 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1797109902] [2023-11-12 02:20:14,591 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1797109902] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-12 02:20:14,591 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-12 02:20:14,591 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-12 02:20:14,592 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [833494543] [2023-11-12 02:20:14,592 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-12 02:20:14,592 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-12 02:20:14,592 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-12 02:20:14,593 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2023-11-12 02:20:14,593 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2023-11-12 02:20:14,593 INFO L87 Difference]: Start difference. First operand 16579 states and 24147 transitions. cyclomatic complexity: 7584 Second operand has 4 states, 4 states have (on average 32.0) internal successors, (128), 3 states have internal predecessors, (128), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-12 02:20:15,082 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-12 02:20:15,082 INFO L93 Difference]: Finished difference Result 40212 states and 58080 transitions. [2023-11-12 02:20:15,083 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 40212 states and 58080 transitions. [2023-11-12 02:20:15,336 INFO L131 ngComponentsAnalysis]: Automaton has 24 accepting balls. 39323 [2023-11-12 02:20:15,473 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 40212 states to 40212 states and 58080 transitions. [2023-11-12 02:20:15,473 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 40212 [2023-11-12 02:20:15,515 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 40212 [2023-11-12 02:20:15,515 INFO L73 IsDeterministic]: Start isDeterministic. Operand 40212 states and 58080 transitions. [2023-11-12 02:20:15,724 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-12 02:20:15,724 INFO L218 hiAutomatonCegarLoop]: Abstraction has 40212 states and 58080 transitions. [2023-11-12 02:20:15,763 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 40212 states and 58080 transitions. [2023-11-12 02:20:16,264 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 40212 to 31489. [2023-11-12 02:20:16,315 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 31489 states, 31489 states have (on average 1.4496808409285782) internal successors, (45649), 31488 states have internal predecessors, (45649), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-12 02:20:16,430 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 31489 states to 31489 states and 45649 transitions. [2023-11-12 02:20:16,430 INFO L240 hiAutomatonCegarLoop]: Abstraction has 31489 states and 45649 transitions. [2023-11-12 02:20:16,431 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2023-11-12 02:20:16,432 INFO L428 stractBuchiCegarLoop]: Abstraction has 31489 states and 45649 transitions. [2023-11-12 02:20:16,432 INFO L335 stractBuchiCegarLoop]: ======== Iteration 15 ============ [2023-11-12 02:20:16,432 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 31489 states and 45649 transitions. [2023-11-12 02:20:16,670 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 31264 [2023-11-12 02:20:16,671 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-12 02:20:16,671 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-12 02:20:16,680 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-12 02:20:16,680 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-12 02:20:16,681 INFO L748 eck$LassoCheckResult]: Stem: 132679#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~token~0 := 0;~local~0 := 0; 132680#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~12#1;havoc main_~__retres1~12#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1; 133693#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret30#1, start_simulation_#t~ret31#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 133694#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 133789#L731 assume 1 == ~m_i~0;~m_st~0 := 0; 133699#L731-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 133641#L736-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 133642#L741-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 133685#L746-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 132615#L751-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 132616#L756-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 132726#L761-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 132984#L766-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 132906#L771-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 132617#L776-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 132281#L781-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 132282#L1036 assume !(0 == ~M_E~0); 132378#L1036-2 assume !(0 == ~T1_E~0); 133322#L1041-1 assume !(0 == ~T2_E~0); 133323#L1046-1 assume !(0 == ~T3_E~0); 132654#L1051-1 assume !(0 == ~T4_E~0); 132655#L1056-1 assume !(0 == ~T5_E~0); 133482#L1061-1 assume !(0 == ~T6_E~0); 132549#L1066-1 assume !(0 == ~T7_E~0); 132550#L1071-1 assume !(0 == ~T8_E~0); 133462#L1076-1 assume !(0 == ~T9_E~0); 132439#L1081-1 assume !(0 == ~T10_E~0); 132440#L1086-1 assume !(0 == ~E_M~0); 132847#L1091-1 assume !(0 == ~E_1~0); 133711#L1096-1 assume !(0 == ~E_2~0); 133712#L1101-1 assume !(0 == ~E_3~0); 132919#L1106-1 assume !(0 == ~E_4~0); 132920#L1111-1 assume !(0 == ~E_5~0); 133097#L1116-1 assume !(0 == ~E_6~0); 133098#L1121-1 assume !(0 == ~E_7~0); 132910#L1126-1 assume !(0 == ~E_8~0); 132911#L1131-1 assume !(0 == ~E_9~0); 133208#L1136-1 assume !(0 == ~E_10~0); 133332#L1141-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 133527#L514 assume !(1 == ~m_pc~0); 133528#L514-2 is_master_triggered_~__retres1~0#1 := 0; 132928#L525 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 132929#is_master_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 133604#L1285 assume !(0 != activate_threads_~tmp~1#1); 133761#L1285-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 132568#L533 assume !(1 == ~t1_pc~0); 132569#L533-2 is_transmit1_triggered_~__retres1~1#1 := 0; 133113#L544 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 132333#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 132334#L1293 assume !(0 != activate_threads_~tmp___0~0#1); 133358#L1293-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 133359#L552 assume !(1 == ~t2_pc~0); 133055#L552-2 is_transmit2_triggered_~__retres1~2#1 := 0; 133056#L563 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 132914#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 132915#L1301 assume !(0 != activate_threads_~tmp___1~0#1); 132941#L1301-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 132942#L571 assume 1 == ~t3_pc~0; 133156#L572 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 133157#L582 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 132279#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 132280#L1309 assume !(0 != activate_threads_~tmp___2~0#1); 133102#L1309-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 132364#L590 assume !(1 == ~t4_pc~0); 132365#L590-2 is_transmit4_triggered_~__retres1~4#1 := 0; 133167#L601 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 132457#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 132458#L1317 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 133393#L1317-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 133099#L609 assume 1 == ~t5_pc~0; 133100#L610 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 133759#L620 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 133606#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 133607#L1325 assume !(0 != activate_threads_~tmp___4~0#1); 133090#L1325-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 133091#L628 assume !(1 == ~t6_pc~0); 133016#L628-2 is_transmit6_triggered_~__retres1~6#1 := 0; 133015#L639 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 132884#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 132885#L1333 assume !(0 != activate_threads_~tmp___5~0#1); 133439#L1333-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 133440#L647 assume 1 == ~t7_pc~0; 132921#L648 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 132922#L658 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 133616#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 132924#L1341 assume !(0 != activate_threads_~tmp___6~0#1); 132925#L1341-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 133825#L666 assume !(1 == ~t8_pc~0); 132704#L666-2 is_transmit8_triggered_~__retres1~8#1 := 0; 132705#L677 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 132940#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 133126#L1349 assume !(0 != activate_threads_~tmp___7~0#1); 132844#L1349-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 132845#L685 assume 1 == ~t9_pc~0; 133776#L686 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 133628#L696 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 132976#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 132874#L1357 assume !(0 != activate_threads_~tmp___8~0#1); 132875#L1357-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 133293#L704 assume !(1 == ~t10_pc~0); 132865#L704-2 is_transmit10_triggered_~__retres1~10#1 := 0; 132864#L715 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 133147#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 132411#L1365 assume !(0 != activate_threads_~tmp___9~0#1); 132412#L1365-2 havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 132663#L1154 assume 1 == ~M_E~0;~M_E~0 := 2; 133423#L1154-2 assume !(1 == ~T1_E~0); 133798#L1159-1 assume !(1 == ~T2_E~0); 133856#L1164-1 assume !(1 == ~T3_E~0); 133857#L1169-1 assume !(1 == ~T4_E~0); 132977#L1174-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 132978#L1179-1 assume !(1 == ~T6_E~0); 132621#L1184-1 assume !(1 == ~T7_E~0); 132622#L1189-1 assume !(1 == ~T8_E~0); 132829#L1194-1 assume !(1 == ~T9_E~0); 132830#L1199-1 assume !(1 == ~T10_E~0); 132783#L1204-1 assume !(1 == ~E_M~0); 132784#L1209-1 assume !(1 == ~E_1~0); 133385#L1214-1 assume 1 == ~E_2~0;~E_2~0 := 2; 133386#L1219-1 assume !(1 == ~E_3~0); 133801#L1224-1 assume !(1 == ~E_4~0); 133802#L1229-1 assume !(1 == ~E_5~0); 132506#L1234-1 assume !(1 == ~E_6~0); 132507#L1239-1 assume !(1 == ~E_7~0); 132564#L1244-1 assume !(1 == ~E_8~0); 132565#L1249-1 assume !(1 == ~E_9~0); 146139#L1254-1 assume 1 == ~E_10~0;~E_10~0 := 2; 146137#L1259-1 assume { :end_inline_reset_delta_events } true; 146136#L1565-2 [2023-11-12 02:20:16,681 INFO L750 eck$LassoCheckResult]: Loop: 146136#L1565-2 assume !false; 146132#L1566 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 146120#L1011-1 assume !false; 146108#L862 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 145984#L794 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 145964#L851 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 145959#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 145952#L866 assume !(0 != eval_~tmp~0#1); 145953#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 149564#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 149562#L1036-3 assume 0 == ~M_E~0;~M_E~0 := 1; 149559#L1036-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 149557#L1041-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 149555#L1046-3 assume !(0 == ~T3_E~0); 149553#L1051-3 assume !(0 == ~T4_E~0); 149551#L1056-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 149549#L1061-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 149546#L1066-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 149544#L1071-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 149542#L1076-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 149540#L1081-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 149538#L1086-3 assume !(0 == ~E_M~0); 149536#L1091-3 assume !(0 == ~E_1~0); 149533#L1096-3 assume 0 == ~E_2~0;~E_2~0 := 1; 149531#L1101-3 assume 0 == ~E_3~0;~E_3~0 := 1; 149529#L1106-3 assume 0 == ~E_4~0;~E_4~0 := 1; 149527#L1111-3 assume 0 == ~E_5~0;~E_5~0 := 1; 149525#L1116-3 assume 0 == ~E_6~0;~E_6~0 := 1; 149523#L1121-3 assume 0 == ~E_7~0;~E_7~0 := 1; 149520#L1126-3 assume !(0 == ~E_8~0); 149518#L1131-3 assume !(0 == ~E_9~0); 149516#L1136-3 assume 0 == ~E_10~0;~E_10~0 := 1; 149514#L1141-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 149512#L514-36 assume !(1 == ~m_pc~0); 149510#L514-38 is_master_triggered_~__retres1~0#1 := 0; 149507#L525-12 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 149505#is_master_triggered_returnLabel#13 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 149503#L1285-36 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 149501#L1285-38 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 149499#L533-36 assume 1 == ~t1_pc~0; 149496#L534-12 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 149493#L544-12 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 149491#is_transmit1_triggered_returnLabel#13 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 149489#L1293-36 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 149487#L1293-38 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 133878#L552-36 assume !(1 == ~t2_pc~0); 133879#L552-38 is_transmit2_triggered_~__retres1~2#1 := 0; 148359#L563-12 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 148353#is_transmit2_triggered_returnLabel#13 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 147839#L1301-36 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 147823#L1301-38 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 147822#L571-36 assume 1 == ~t3_pc~0; 147820#L572-12 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 147819#L582-12 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 147818#is_transmit3_triggered_returnLabel#13 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 147817#L1309-36 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 147816#L1309-38 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 147815#L590-36 assume 1 == ~t4_pc~0; 147814#L591-12 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 147812#L601-12 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 147811#is_transmit4_triggered_returnLabel#13 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 147810#L1317-36 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 147809#L1317-38 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 147808#L609-36 assume 1 == ~t5_pc~0; 147806#L610-12 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 147805#L620-12 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 147804#is_transmit5_triggered_returnLabel#13 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 147803#L1325-36 assume !(0 != activate_threads_~tmp___4~0#1); 147802#L1325-38 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 147801#L628-36 assume 1 == ~t6_pc~0; 147799#L629-12 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 147798#L639-12 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 147797#is_transmit6_triggered_returnLabel#13 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 147796#L1333-36 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 147795#L1333-38 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 147794#L647-36 assume 1 == ~t7_pc~0; 147792#L648-12 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 147791#L658-12 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 147790#is_transmit7_triggered_returnLabel#13 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 147789#L1341-36 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 147788#L1341-38 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 147787#L666-36 assume !(1 == ~t8_pc~0); 147786#L666-38 is_transmit8_triggered_~__retres1~8#1 := 0; 147784#L677-12 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 147783#is_transmit8_triggered_returnLabel#13 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 147781#L1349-36 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 147779#L1349-38 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 147777#L685-36 assume !(1 == ~t9_pc~0); 147774#L685-38 is_transmit9_triggered_~__retres1~9#1 := 0; 147772#L696-12 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 147770#is_transmit9_triggered_returnLabel#13 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 147768#L1357-36 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 147765#L1357-38 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 147763#L704-36 assume 1 == ~t10_pc~0; 147760#L705-12 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 147758#L715-12 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 147756#is_transmit10_triggered_returnLabel#13 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 147754#L1365-36 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 147753#L1365-38 havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 147751#L1154-3 assume 1 == ~M_E~0;~M_E~0 := 2; 133868#L1154-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 147748#L1159-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 147746#L1164-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 146610#L1169-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 147742#L1174-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 147740#L1179-3 assume !(1 == ~T6_E~0); 147738#L1184-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 147736#L1189-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 147734#L1194-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 147732#L1199-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 147729#L1204-3 assume 1 == ~E_M~0;~E_M~0 := 2; 133872#L1209-3 assume 1 == ~E_1~0;~E_1~0 := 2; 147726#L1214-3 assume 1 == ~E_2~0;~E_2~0 := 2; 147724#L1219-3 assume !(1 == ~E_3~0); 147722#L1224-3 assume 1 == ~E_4~0;~E_4~0 := 2; 147720#L1229-3 assume 1 == ~E_5~0;~E_5~0 := 2; 147717#L1234-3 assume 1 == ~E_6~0;~E_6~0 := 2; 147715#L1239-3 assume 1 == ~E_7~0;~E_7~0 := 2; 147713#L1244-3 assume 1 == ~E_8~0;~E_8~0 := 2; 143050#L1249-3 assume 1 == ~E_9~0;~E_9~0 := 2; 147710#L1254-3 assume 1 == ~E_10~0;~E_10~0 := 2; 147708#L1259-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 147681#L794-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 147680#L851-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 147679#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret30#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret30#1;havoc start_simulation_#t~ret30#1; 147134#L1584 assume !(0 == start_simulation_~tmp~3#1); 147132#L1584-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret29#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 147124#L794-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 147113#L851-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 147096#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret29#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret29#1;havoc stop_simulation_#t~ret29#1; 147088#L1539 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 146249#L1546 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 146142#stop_simulation_returnLabel#1 start_simulation_#t~ret31#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret29#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret31#1;havoc start_simulation_#t~ret31#1; 146138#L1597 assume !(0 != start_simulation_~tmp___0~1#1); 146136#L1565-2 [2023-11-12 02:20:16,681 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-12 02:20:16,682 INFO L85 PathProgramCache]: Analyzing trace with hash 353984391, now seen corresponding path program 1 times [2023-11-12 02:20:16,682 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-12 02:20:16,682 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1076536097] [2023-11-12 02:20:16,682 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-12 02:20:16,682 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-12 02:20:16,697 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-12 02:20:16,761 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-12 02:20:16,762 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-12 02:20:16,762 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1076536097] [2023-11-12 02:20:16,762 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1076536097] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-12 02:20:16,762 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-12 02:20:16,762 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-12 02:20:16,762 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1477158648] [2023-11-12 02:20:16,763 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-12 02:20:16,763 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-12 02:20:16,763 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-12 02:20:16,763 INFO L85 PathProgramCache]: Analyzing trace with hash -577328005, now seen corresponding path program 1 times [2023-11-12 02:20:16,764 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-12 02:20:16,764 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [23323904] [2023-11-12 02:20:16,764 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-12 02:20:16,764 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-12 02:20:16,779 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-12 02:20:16,822 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-12 02:20:16,822 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-12 02:20:16,822 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [23323904] [2023-11-12 02:20:16,822 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [23323904] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-12 02:20:16,822 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-12 02:20:16,823 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-12 02:20:16,823 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1487568331] [2023-11-12 02:20:16,823 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-12 02:20:16,823 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-12 02:20:16,823 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-12 02:20:16,824 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2023-11-12 02:20:16,824 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2023-11-12 02:20:16,824 INFO L87 Difference]: Start difference. First operand 31489 states and 45649 transitions. cyclomatic complexity: 14176 Second operand has 4 states, 4 states have (on average 32.0) internal successors, (128), 3 states have internal predecessors, (128), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-12 02:20:17,613 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-12 02:20:17,622 INFO L93 Difference]: Finished difference Result 76393 states and 109901 transitions. [2023-11-12 02:20:17,623 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 76393 states and 109901 transitions. [2023-11-12 02:20:18,077 INFO L131 ngComponentsAnalysis]: Automaton has 24 accepting balls. 74833 [2023-11-12 02:20:18,390 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 76393 states to 76393 states and 109901 transitions. [2023-11-12 02:20:18,390 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 76393 [2023-11-12 02:20:18,440 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 76393 [2023-11-12 02:20:18,441 INFO L73 IsDeterministic]: Start isDeterministic. Operand 76393 states and 109901 transitions. [2023-11-12 02:20:18,509 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-12 02:20:18,509 INFO L218 hiAutomatonCegarLoop]: Abstraction has 76393 states and 109901 transitions. [2023-11-12 02:20:18,691 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 76393 states and 109901 transitions. [2023-11-12 02:20:19,364 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 76393 to 59884. [2023-11-12 02:20:19,428 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 59884 states, 59884 states have (on average 1.4437579320018703) internal successors, (86458), 59883 states have internal predecessors, (86458), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-12 02:20:19,775 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 59884 states to 59884 states and 86458 transitions. [2023-11-12 02:20:19,776 INFO L240 hiAutomatonCegarLoop]: Abstraction has 59884 states and 86458 transitions. [2023-11-12 02:20:19,777 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2023-11-12 02:20:19,777 INFO L428 stractBuchiCegarLoop]: Abstraction has 59884 states and 86458 transitions. [2023-11-12 02:20:19,777 INFO L335 stractBuchiCegarLoop]: ======== Iteration 16 ============ [2023-11-12 02:20:19,778 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 59884 states and 86458 transitions. [2023-11-12 02:20:20,114 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 59644 [2023-11-12 02:20:20,115 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-12 02:20:20,115 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-12 02:20:20,119 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-12 02:20:20,119 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-12 02:20:20,120 INFO L748 eck$LassoCheckResult]: Stem: 240577#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~token~0 := 0;~local~0 := 0; 240578#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~12#1;havoc main_~__retres1~12#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1; 241566#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret30#1, start_simulation_#t~ret31#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 241567#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 241649#L731 assume 1 == ~m_i~0;~m_st~0 := 0; 241569#L731-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 241517#L736-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 241518#L741-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 241556#L746-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 240509#L751-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 240510#L756-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 240624#L761-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 240880#L766-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 240798#L771-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 240511#L776-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 240173#L781-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 240174#L1036 assume !(0 == ~M_E~0); 240270#L1036-2 assume !(0 == ~T1_E~0); 241223#L1041-1 assume !(0 == ~T2_E~0); 241224#L1046-1 assume !(0 == ~T3_E~0); 240552#L1051-1 assume !(0 == ~T4_E~0); 240553#L1056-1 assume !(0 == ~T5_E~0); 241371#L1061-1 assume !(0 == ~T6_E~0); 240442#L1066-1 assume !(0 == ~T7_E~0); 240443#L1071-1 assume !(0 == ~T8_E~0); 241352#L1076-1 assume !(0 == ~T9_E~0); 240333#L1081-1 assume !(0 == ~T10_E~0); 240334#L1086-1 assume !(0 == ~E_M~0); 240742#L1091-1 assume !(0 == ~E_1~0); 241580#L1096-1 assume !(0 == ~E_2~0); 241581#L1101-1 assume !(0 == ~E_3~0); 240811#L1106-1 assume !(0 == ~E_4~0); 240812#L1111-1 assume !(0 == ~E_5~0); 241001#L1116-1 assume !(0 == ~E_6~0); 241002#L1121-1 assume !(0 == ~E_7~0); 240802#L1126-1 assume !(0 == ~E_8~0); 240803#L1131-1 assume !(0 == ~E_9~0); 241110#L1136-1 assume !(0 == ~E_10~0); 241231#L1141-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 241406#L514 assume !(1 == ~m_pc~0); 241407#L514-2 is_master_triggered_~__retres1~0#1 := 0; 240820#L525 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 240821#is_master_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 241482#L1285 assume !(0 != activate_threads_~tmp~1#1); 241625#L1285-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 240462#L533 assume !(1 == ~t1_pc~0); 240463#L533-2 is_transmit1_triggered_~__retres1~1#1 := 0; 241016#L544 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 240225#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 240226#L1293 assume !(0 != activate_threads_~tmp___0~0#1); 241256#L1293-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 241257#L552 assume !(1 == ~t2_pc~0); 240958#L552-2 is_transmit2_triggered_~__retres1~2#1 := 0; 240959#L563 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 240806#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 240807#L1301 assume !(0 != activate_threads_~tmp___1~0#1); 240834#L1301-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 240835#L571 assume !(1 == ~t3_pc~0); 241077#L571-2 is_transmit3_triggered_~__retres1~3#1 := 0; 241162#L582 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 240171#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 240172#L1309 assume !(0 != activate_threads_~tmp___2~0#1); 241006#L1309-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 240256#L590 assume !(1 == ~t4_pc~0); 240257#L590-2 is_transmit4_triggered_~__retres1~4#1 := 0; 241066#L601 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 240351#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 240352#L1317 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 241286#L1317-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 241003#L609 assume 1 == ~t5_pc~0; 241004#L610 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 241623#L620 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 241484#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 241485#L1325 assume !(0 != activate_threads_~tmp___4~0#1); 240994#L1325-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 240995#L628 assume !(1 == ~t6_pc~0); 240918#L628-2 is_transmit6_triggered_~__retres1~6#1 := 0; 240917#L639 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 240779#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 240780#L1333 assume !(0 != activate_threads_~tmp___5~0#1); 241328#L1333-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 241329#L647 assume 1 == ~t7_pc~0; 240813#L648 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 240814#L658 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 241494#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 240816#L1341 assume !(0 != activate_threads_~tmp___6~0#1); 240817#L1341-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 241675#L666 assume !(1 == ~t8_pc~0); 240601#L666-2 is_transmit8_triggered_~__retres1~8#1 := 0; 240602#L677 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 240833#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 241029#L1349 assume !(0 != activate_threads_~tmp___7~0#1); 240739#L1349-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 240740#L685 assume 1 == ~t9_pc~0; 241635#L686 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 241504#L696 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 240872#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 240769#L1357 assume !(0 != activate_threads_~tmp___8~0#1); 240770#L1357-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 241193#L704 assume !(1 == ~t10_pc~0); 240759#L704-2 is_transmit10_triggered_~__retres1~10#1 := 0; 240758#L715 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 241049#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 240305#L1365 assume !(0 != activate_threads_~tmp___9~0#1); 240306#L1365-2 havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 240561#L1154 assume 1 == ~M_E~0;~M_E~0 := 2; 241312#L1154-2 assume !(1 == ~T1_E~0); 241657#L1159-1 assume !(1 == ~T2_E~0); 241705#L1164-1 assume !(1 == ~T3_E~0); 241026#L1169-1 assume !(1 == ~T4_E~0); 241027#L1174-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 240665#L1179-1 assume !(1 == ~T6_E~0); 240666#L1184-1 assume !(1 == ~T7_E~0); 240598#L1189-1 assume !(1 == ~T8_E~0); 240599#L1194-1 assume !(1 == ~T9_E~0); 241719#L1199-1 assume !(1 == ~T10_E~0); 241720#L1204-1 assume !(1 == ~E_M~0); 262276#L1209-1 assume !(1 == ~E_1~0); 262275#L1214-1 assume 1 == ~E_2~0;~E_2~0 := 2; 262274#L1219-1 assume !(1 == ~E_3~0); 262273#L1224-1 assume !(1 == ~E_4~0); 262272#L1229-1 assume !(1 == ~E_5~0); 262271#L1234-1 assume !(1 == ~E_6~0); 262270#L1239-1 assume !(1 == ~E_7~0); 262269#L1244-1 assume !(1 == ~E_8~0); 262267#L1249-1 assume !(1 == ~E_9~0); 262266#L1254-1 assume 1 == ~E_10~0;~E_10~0 := 2; 262264#L1259-1 assume { :end_inline_reset_delta_events } true; 262262#L1565-2 [2023-11-12 02:20:20,120 INFO L750 eck$LassoCheckResult]: Loop: 262262#L1565-2 assume !false; 262260#L1566 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 262254#L1011-1 assume !false; 262252#L862 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 262250#L794 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 262238#L851 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 262236#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 262233#L866 assume !(0 != eval_~tmp~0#1); 262234#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 270347#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 270346#L1036-3 assume 0 == ~M_E~0;~M_E~0 := 1; 270322#L1036-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 270320#L1041-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 270318#L1046-3 assume !(0 == ~T3_E~0); 270316#L1051-3 assume !(0 == ~T4_E~0); 270314#L1056-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 270312#L1061-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 270309#L1066-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 270307#L1071-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 270305#L1076-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 270303#L1081-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 270301#L1086-3 assume !(0 == ~E_M~0); 270299#L1091-3 assume !(0 == ~E_1~0); 270296#L1096-3 assume 0 == ~E_2~0;~E_2~0 := 1; 270294#L1101-3 assume 0 == ~E_3~0;~E_3~0 := 1; 270292#L1106-3 assume 0 == ~E_4~0;~E_4~0 := 1; 270290#L1111-3 assume 0 == ~E_5~0;~E_5~0 := 1; 270288#L1116-3 assume 0 == ~E_6~0;~E_6~0 := 1; 270286#L1121-3 assume 0 == ~E_7~0;~E_7~0 := 1; 270274#L1126-3 assume !(0 == ~E_8~0); 270271#L1131-3 assume !(0 == ~E_9~0); 270245#L1136-3 assume 0 == ~E_10~0;~E_10~0 := 1; 270241#L1141-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 270237#L514-36 assume !(1 == ~m_pc~0); 270233#L514-38 is_master_triggered_~__retres1~0#1 := 0; 270227#L525-12 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 270223#is_master_triggered_returnLabel#13 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 270218#L1285-36 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 270214#L1285-38 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 270210#L533-36 assume 1 == ~t1_pc~0; 270205#L534-12 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 270199#L544-12 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 270195#is_transmit1_triggered_returnLabel#13 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 270187#L1293-36 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 270181#L1293-38 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 270175#L552-36 assume !(1 == ~t2_pc~0); 259953#L552-38 is_transmit2_triggered_~__retres1~2#1 := 0; 270162#L563-12 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 270156#is_transmit2_triggered_returnLabel#13 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 270149#L1301-36 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 270143#L1301-38 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 270136#L571-36 assume !(1 == ~t3_pc~0); 250352#L571-38 is_transmit3_triggered_~__retres1~3#1 := 0; 270122#L582-12 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 270116#is_transmit3_triggered_returnLabel#13 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 270109#L1309-36 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 270103#L1309-38 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 270090#L590-36 assume 1 == ~t4_pc~0; 270084#L591-12 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 270055#L601-12 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 270050#is_transmit4_triggered_returnLabel#13 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 241707#L1317-36 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 241418#L1317-38 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 241419#L609-36 assume 1 == ~t5_pc~0; 241271#L610-12 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 241080#L620-12 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 241081#is_transmit5_triggered_returnLabel#13 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 241481#L1325-36 assume !(0 != activate_threads_~tmp___4~0#1); 241171#L1325-38 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 240961#L628-36 assume 1 == ~t6_pc~0; 240790#L629-12 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 240791#L639-12 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 240845#is_transmit6_triggered_returnLabel#13 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 240846#L1333-36 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 241213#L1333-38 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 241214#L647-36 assume !(1 == ~t7_pc~0); 241134#L647-38 is_transmit7_triggered_~__retres1~7#1 := 0; 240319#L658-12 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 240320#is_transmit7_triggered_returnLabel#13 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 240337#L1341-36 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 240338#L1341-38 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 269829#L666-36 assume !(1 == ~t8_pc~0); 269824#L666-38 is_transmit8_triggered_~__retres1~8#1 := 0; 269818#L677-12 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 269813#is_transmit8_triggered_returnLabel#13 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 269796#L1349-36 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 269792#L1349-38 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 269787#L685-36 assume !(1 == ~t9_pc~0); 269781#L685-38 is_transmit9_triggered_~__retres1~9#1 := 0; 269776#L696-12 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 269770#is_transmit9_triggered_returnLabel#13 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 269762#L1357-36 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 269757#L1357-38 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 269751#L704-36 assume 1 == ~t10_pc~0; 269744#L705-12 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 269738#L715-12 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 269734#is_transmit10_triggered_returnLabel#13 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 241341#L1365-36 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 240446#L1365-38 havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 240447#L1154-3 assume 1 == ~M_E~0;~M_E~0 := 2; 241542#L1154-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 241380#L1159-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 241381#L1164-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 241620#L1169-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 240755#L1174-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 240756#L1179-3 assume !(1 == ~T6_E~0); 241506#L1184-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 240321#L1189-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 240322#L1194-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 240695#L1199-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 240696#L1204-3 assume 1 == ~E_M~0;~E_M~0 := 2; 241050#L1209-3 assume 1 == ~E_1~0;~E_1~0 := 2; 240189#L1214-3 assume 1 == ~E_2~0;~E_2~0 := 2; 240190#L1219-3 assume !(1 == ~E_3~0); 241264#L1224-3 assume 1 == ~E_4~0;~E_4~0 := 2; 241265#L1229-3 assume 1 == ~E_5~0;~E_5~0 := 2; 241287#L1234-3 assume 1 == ~E_6~0;~E_6~0 := 2; 240460#L1239-3 assume 1 == ~E_7~0;~E_7~0 := 2; 240461#L1244-3 assume 1 == ~E_8~0;~E_8~0 := 2; 241107#L1249-3 assume 1 == ~E_9~0;~E_9~0 := 2; 241551#L1254-3 assume 1 == ~E_10~0;~E_10~0 := 2; 241269#L1259-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 241270#L794-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 240268#L851-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 240737#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret30#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret30#1;havoc start_simulation_#t~ret30#1; 240738#L1584 assume !(0 == start_simulation_~tmp~3#1); 268912#L1584-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret29#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 268896#L794-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 266354#L851-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 266350#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret29#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret29#1;havoc stop_simulation_#t~ret29#1; 266348#L1539 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 266346#L1546 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 266343#stop_simulation_returnLabel#1 start_simulation_#t~ret31#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret29#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret31#1;havoc start_simulation_#t~ret31#1; 262265#L1597 assume !(0 != start_simulation_~tmp___0~1#1); 262262#L1565-2 [2023-11-12 02:20:20,121 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-12 02:20:20,121 INFO L85 PathProgramCache]: Analyzing trace with hash -1601336824, now seen corresponding path program 1 times [2023-11-12 02:20:20,121 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-12 02:20:20,122 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1111742596] [2023-11-12 02:20:20,122 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-12 02:20:20,122 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-12 02:20:20,146 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-12 02:20:20,225 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-12 02:20:20,225 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-12 02:20:20,225 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1111742596] [2023-11-12 02:20:20,226 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1111742596] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-12 02:20:20,226 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-12 02:20:20,226 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2023-11-12 02:20:20,226 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1496555721] [2023-11-12 02:20:20,227 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-12 02:20:20,227 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-12 02:20:20,227 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-12 02:20:20,228 INFO L85 PathProgramCache]: Analyzing trace with hash 1286160765, now seen corresponding path program 1 times [2023-11-12 02:20:20,228 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-12 02:20:20,228 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1319725239] [2023-11-12 02:20:20,228 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-12 02:20:20,229 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-12 02:20:20,248 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-12 02:20:20,294 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-12 02:20:20,295 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-12 02:20:20,295 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1319725239] [2023-11-12 02:20:20,295 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1319725239] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-12 02:20:20,295 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-12 02:20:20,295 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-12 02:20:20,296 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1690210651] [2023-11-12 02:20:20,296 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-12 02:20:20,296 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-12 02:20:20,297 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-12 02:20:20,297 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2023-11-12 02:20:20,297 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2023-11-12 02:20:20,297 INFO L87 Difference]: Start difference. First operand 59884 states and 86458 transitions. cyclomatic complexity: 26590 Second operand has 5 states, 5 states have (on average 25.6) internal successors, (128), 5 states have internal predecessors, (128), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-12 02:20:21,290 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-12 02:20:21,290 INFO L93 Difference]: Finished difference Result 144384 states and 206761 transitions. [2023-11-12 02:20:21,290 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 144384 states and 206761 transitions. [2023-11-12 02:20:22,139 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 143928 [2023-11-12 02:20:22,949 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 144384 states to 144384 states and 206761 transitions. [2023-11-12 02:20:22,949 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 144384 [2023-11-12 02:20:23,014 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 144384 [2023-11-12 02:20:23,014 INFO L73 IsDeterministic]: Start isDeterministic. Operand 144384 states and 206761 transitions. [2023-11-12 02:20:23,157 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-12 02:20:23,158 INFO L218 hiAutomatonCegarLoop]: Abstraction has 144384 states and 206761 transitions. [2023-11-12 02:20:23,233 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 144384 states and 206761 transitions. [2023-11-12 02:20:24,090 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 144384 to 61735. [2023-11-12 02:20:24,143 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 61735 states, 61735 states have (on average 1.4304527415566535) internal successors, (88309), 61734 states have internal predecessors, (88309), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-12 02:20:24,284 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 61735 states to 61735 states and 88309 transitions. [2023-11-12 02:20:24,286 INFO L240 hiAutomatonCegarLoop]: Abstraction has 61735 states and 88309 transitions. [2023-11-12 02:20:24,286 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2023-11-12 02:20:24,288 INFO L428 stractBuchiCegarLoop]: Abstraction has 61735 states and 88309 transitions. [2023-11-12 02:20:24,288 INFO L335 stractBuchiCegarLoop]: ======== Iteration 17 ============ [2023-11-12 02:20:24,289 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 61735 states and 88309 transitions. [2023-11-12 02:20:24,457 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 61492 [2023-11-12 02:20:24,457 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-12 02:20:24,458 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-12 02:20:24,461 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-12 02:20:24,461 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-12 02:20:24,461 INFO L748 eck$LassoCheckResult]: Stem: 444866#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~token~0 := 0;~local~0 := 0; 444867#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~12#1;havoc main_~__retres1~12#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1; 445915#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret30#1, start_simulation_#t~ret31#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 445916#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 446020#L731 assume 1 == ~m_i~0;~m_st~0 := 0; 445921#L731-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 445841#L736-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 445842#L741-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 445906#L746-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 444794#L751-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 444795#L756-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 444914#L761-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 445171#L766-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 445090#L771-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 444793#L776-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 444454#L781-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 444455#L1036 assume !(0 == ~M_E~0); 444551#L1036-2 assume !(0 == ~T1_E~0); 445517#L1041-1 assume !(0 == ~T2_E~0); 445518#L1046-1 assume !(0 == ~T3_E~0); 444838#L1051-1 assume !(0 == ~T4_E~0); 444839#L1056-1 assume !(0 == ~T5_E~0); 445675#L1061-1 assume !(0 == ~T6_E~0); 444724#L1066-1 assume !(0 == ~T7_E~0); 444725#L1071-1 assume !(0 == ~T8_E~0); 445655#L1076-1 assume !(0 == ~T9_E~0); 444614#L1081-1 assume !(0 == ~T10_E~0); 444615#L1086-1 assume !(0 == ~E_M~0); 445034#L1091-1 assume !(0 == ~E_1~0); 445931#L1096-1 assume !(0 == ~E_2~0); 445932#L1101-1 assume !(0 == ~E_3~0); 445104#L1106-1 assume !(0 == ~E_4~0); 445105#L1111-1 assume !(0 == ~E_5~0); 445286#L1116-1 assume !(0 == ~E_6~0); 445287#L1121-1 assume !(0 == ~E_7~0); 445094#L1126-1 assume !(0 == ~E_8~0); 445095#L1131-1 assume !(0 == ~E_9~0); 445399#L1136-1 assume !(0 == ~E_10~0); 445525#L1141-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 445718#L514 assume !(1 == ~m_pc~0); 445719#L514-2 is_master_triggered_~__retres1~0#1 := 0; 445113#L525 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 445114#is_master_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 445802#L1285 assume !(0 != activate_threads_~tmp~1#1); 445988#L1285-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 444744#L533 assume !(1 == ~t1_pc~0); 444745#L533-2 is_transmit1_triggered_~__retres1~1#1 := 0; 445304#L544 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 444506#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 444507#L1293 assume !(0 != activate_threads_~tmp___0~0#1); 445555#L1293-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 445556#L552 assume !(1 == ~t2_pc~0); 445244#L552-2 is_transmit2_triggered_~__retres1~2#1 := 0; 445245#L563 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 445098#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 445099#L1301 assume !(0 != activate_threads_~tmp___1~0#1); 445127#L1301-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 445128#L571 assume !(1 == ~t3_pc~0); 445366#L571-2 is_transmit3_triggered_~__retres1~3#1 := 0; 445454#L582 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 444452#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 444453#L1309 assume !(0 != activate_threads_~tmp___2~0#1); 445291#L1309-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 444537#L590 assume !(1 == ~t4_pc~0); 444538#L590-2 is_transmit4_triggered_~__retres1~4#1 := 0; 445365#L601 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 446088#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 445993#L1317 assume !(0 != activate_threads_~tmp___3~0#1); 445584#L1317-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 445288#L609 assume 1 == ~t5_pc~0; 445289#L610 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 445986#L620 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 445805#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 445806#L1325 assume !(0 != activate_threads_~tmp___4~0#1); 445279#L1325-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 445280#L628 assume !(1 == ~t6_pc~0); 445205#L628-2 is_transmit6_triggered_~__retres1~6#1 := 0; 445204#L639 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 445070#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 445071#L1333 assume !(0 != activate_threads_~tmp___5~0#1); 445627#L1333-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 445628#L647 assume 1 == ~t7_pc~0; 445106#L648 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 445107#L658 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 445819#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 445109#L1341 assume !(0 != activate_threads_~tmp___6~0#1); 445110#L1341-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 446045#L666 assume !(1 == ~t8_pc~0); 444891#L666-2 is_transmit8_triggered_~__retres1~8#1 := 0; 444892#L677 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 445126#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 445316#L1349 assume !(0 != activate_threads_~tmp___7~0#1); 445029#L1349-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 445030#L685 assume 1 == ~t9_pc~0; 446002#L686 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 445829#L696 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 445165#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 445060#L1357 assume !(0 != activate_threads_~tmp___8~0#1); 445061#L1357-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 445485#L704 assume !(1 == ~t10_pc~0); 445051#L704-2 is_transmit10_triggered_~__retres1~10#1 := 0; 445050#L715 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 445336#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 444586#L1365 assume !(0 != activate_threads_~tmp___9~0#1); 444587#L1365-2 havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 444848#L1154 assume 1 == ~M_E~0;~M_E~0 := 2; 445611#L1154-2 assume !(1 == ~T1_E~0); 446029#L1159-1 assume !(1 == ~T2_E~0); 446092#L1164-1 assume !(1 == ~T3_E~0); 445314#L1169-1 assume !(1 == ~T4_E~0); 445166#L1174-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 444956#L1179-1 assume !(1 == ~T6_E~0); 444803#L1184-1 assume !(1 == ~T7_E~0); 444804#L1189-1 assume !(1 == ~T8_E~0); 444889#L1194-1 assume !(1 == ~T9_E~0); 445014#L1199-1 assume !(1 == ~T10_E~0); 444968#L1204-1 assume !(1 == ~E_M~0); 444969#L1209-1 assume !(1 == ~E_1~0); 467379#L1214-1 assume 1 == ~E_2~0;~E_2~0 := 2; 467378#L1219-1 assume !(1 == ~E_3~0); 467377#L1224-1 assume !(1 == ~E_4~0); 467376#L1229-1 assume !(1 == ~E_5~0); 467375#L1234-1 assume !(1 == ~E_6~0); 467374#L1239-1 assume !(1 == ~E_7~0); 467373#L1244-1 assume !(1 == ~E_8~0); 467370#L1249-1 assume !(1 == ~E_9~0); 467369#L1254-1 assume 1 == ~E_10~0;~E_10~0 := 2; 466446#L1259-1 assume { :end_inline_reset_delta_events } true; 466444#L1565-2 [2023-11-12 02:20:24,462 INFO L750 eck$LassoCheckResult]: Loop: 466444#L1565-2 assume !false; 466442#L1566 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 466438#L1011-1 assume !false; 466418#L862 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 466416#L794 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 466404#L851 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 466400#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 466397#L866 assume !(0 != eval_~tmp~0#1); 466398#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 475506#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 475504#L1036-3 assume 0 == ~M_E~0;~M_E~0 := 1; 475502#L1036-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 475500#L1041-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 475497#L1046-3 assume !(0 == ~T3_E~0); 475493#L1051-3 assume !(0 == ~T4_E~0); 475489#L1056-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 475484#L1061-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 475480#L1066-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 475476#L1071-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 475472#L1076-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 475467#L1081-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 475462#L1086-3 assume !(0 == ~E_M~0); 475448#L1091-3 assume !(0 == ~E_1~0); 475446#L1096-3 assume 0 == ~E_2~0;~E_2~0 := 1; 475445#L1101-3 assume 0 == ~E_3~0;~E_3~0 := 1; 475443#L1106-3 assume 0 == ~E_4~0;~E_4~0 := 1; 475441#L1111-3 assume 0 == ~E_5~0;~E_5~0 := 1; 475438#L1116-3 assume 0 == ~E_6~0;~E_6~0 := 1; 475434#L1121-3 assume 0 == ~E_7~0;~E_7~0 := 1; 475429#L1126-3 assume !(0 == ~E_8~0); 475424#L1131-3 assume !(0 == ~E_9~0); 475419#L1136-3 assume 0 == ~E_10~0;~E_10~0 := 1; 475412#L1141-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 475406#L514-36 assume !(1 == ~m_pc~0); 475399#L514-38 is_master_triggered_~__retres1~0#1 := 0; 475393#L525-12 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 475385#is_master_triggered_returnLabel#13 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 475379#L1285-36 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 475373#L1285-38 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 475366#L533-36 assume !(1 == ~t1_pc~0); 475360#L533-38 is_transmit1_triggered_~__retres1~1#1 := 0; 475353#L544-12 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 475344#is_transmit1_triggered_returnLabel#13 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 475338#L1293-36 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 475333#L1293-38 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 475032#L552-36 assume !(1 == ~t2_pc~0); 457109#L552-38 is_transmit2_triggered_~__retres1~2#1 := 0; 475030#L563-12 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 475027#is_transmit2_triggered_returnLabel#13 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 474973#L1301-36 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 474952#L1301-38 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 468053#L571-36 assume !(1 == ~t3_pc~0); 468052#L571-38 is_transmit3_triggered_~__retres1~3#1 := 0; 468051#L582-12 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 468050#is_transmit3_triggered_returnLabel#13 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 468049#L1309-36 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 468048#L1309-38 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 468047#L590-36 assume !(1 == ~t4_pc~0); 468046#L590-38 is_transmit4_triggered_~__retres1~4#1 := 0; 468044#L601-12 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 468042#is_transmit4_triggered_returnLabel#13 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 468040#L1317-36 assume !(0 != activate_threads_~tmp___3~0#1); 468037#L1317-38 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 468035#L609-36 assume !(1 == ~t5_pc~0); 468032#L609-38 is_transmit5_triggered_~__retres1~5#1 := 0; 468029#L620-12 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 468027#is_transmit5_triggered_returnLabel#13 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 468025#L1325-36 assume !(0 != activate_threads_~tmp___4~0#1); 468023#L1325-38 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 468021#L628-36 assume !(1 == ~t6_pc~0); 468018#L628-38 is_transmit6_triggered_~__retres1~6#1 := 0; 468015#L639-12 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 468013#is_transmit6_triggered_returnLabel#13 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 468011#L1333-36 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 468009#L1333-38 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 468007#L647-36 assume !(1 == ~t7_pc~0); 468004#L647-38 is_transmit7_triggered_~__retres1~7#1 := 0; 468001#L658-12 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 467999#is_transmit7_triggered_returnLabel#13 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 467812#L1341-36 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 467806#L1341-38 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 467799#L666-36 assume !(1 == ~t8_pc~0); 467792#L666-38 is_transmit8_triggered_~__retres1~8#1 := 0; 467786#L677-12 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 467748#is_transmit8_triggered_returnLabel#13 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 467722#L1349-36 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 467716#L1349-38 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 467709#L685-36 assume 1 == ~t9_pc~0; 467701#L686-12 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 467680#L696-12 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 467367#is_transmit9_triggered_returnLabel#13 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 467360#L1357-36 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 467353#L1357-38 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 467073#L704-36 assume !(1 == ~t10_pc~0); 467070#L704-38 is_transmit10_triggered_~__retres1~10#1 := 0; 467067#L715-12 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 467065#is_transmit10_triggered_returnLabel#13 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 467058#L1365-36 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 466708#L1365-38 havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 466706#L1154-3 assume 1 == ~M_E~0;~M_E~0 := 2; 446111#L1154-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 466703#L1159-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 466701#L1164-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 466697#L1169-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 466695#L1174-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 466693#L1179-3 assume !(1 == ~T6_E~0); 466691#L1184-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 466689#L1189-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 466687#L1194-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 466685#L1199-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 466683#L1204-3 assume 1 == ~E_M~0;~E_M~0 := 2; 454406#L1209-3 assume 1 == ~E_1~0;~E_1~0 := 2; 466680#L1214-3 assume 1 == ~E_2~0;~E_2~0 := 2; 466678#L1219-3 assume !(1 == ~E_3~0); 466676#L1224-3 assume 1 == ~E_4~0;~E_4~0 := 2; 466674#L1229-3 assume 1 == ~E_5~0;~E_5~0 := 2; 466672#L1234-3 assume 1 == ~E_6~0;~E_6~0 := 2; 466670#L1239-3 assume 1 == ~E_7~0;~E_7~0 := 2; 466668#L1244-3 assume 1 == ~E_8~0;~E_8~0 := 2; 466664#L1249-3 assume 1 == ~E_9~0;~E_9~0 := 2; 466662#L1254-3 assume 1 == ~E_10~0;~E_10~0 := 2; 466661#L1259-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 466649#L794-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 466648#L851-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 466644#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret30#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret30#1;havoc start_simulation_#t~ret30#1; 466642#L1584 assume !(0 == start_simulation_~tmp~3#1); 466639#L1584-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret29#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 466497#L794-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 466468#L851-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 466460#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret29#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret29#1;havoc stop_simulation_#t~ret29#1; 466453#L1539 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 466451#L1546 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 466449#stop_simulation_returnLabel#1 start_simulation_#t~ret31#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret29#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret31#1;havoc start_simulation_#t~ret31#1; 466447#L1597 assume !(0 != start_simulation_~tmp___0~1#1); 466444#L1565-2 [2023-11-12 02:20:24,463 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-12 02:20:24,463 INFO L85 PathProgramCache]: Analyzing trace with hash 360237834, now seen corresponding path program 1 times [2023-11-12 02:20:24,463 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-12 02:20:24,463 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [140773613] [2023-11-12 02:20:24,464 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-12 02:20:24,464 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-12 02:20:24,482 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-12 02:20:24,887 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-12 02:20:24,888 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-12 02:20:24,888 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [140773613] [2023-11-12 02:20:24,888 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [140773613] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-12 02:20:24,888 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-12 02:20:24,889 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2023-11-12 02:20:24,889 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1783158897] [2023-11-12 02:20:24,889 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-12 02:20:24,889 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-12 02:20:24,890 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-12 02:20:24,904 INFO L85 PathProgramCache]: Analyzing trace with hash 1531284291, now seen corresponding path program 1 times [2023-11-12 02:20:24,904 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-12 02:20:24,904 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [494256866] [2023-11-12 02:20:24,905 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-12 02:20:24,905 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-12 02:20:24,929 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-12 02:20:24,988 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-12 02:20:24,989 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-12 02:20:24,989 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [494256866] [2023-11-12 02:20:24,989 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [494256866] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-12 02:20:24,989 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-12 02:20:24,990 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-12 02:20:24,990 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1924883183] [2023-11-12 02:20:24,990 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-12 02:20:24,991 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-12 02:20:24,991 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-12 02:20:24,991 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-12 02:20:24,991 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-12 02:20:24,992 INFO L87 Difference]: Start difference. First operand 61735 states and 88309 transitions. cyclomatic complexity: 26590 Second operand has 3 states, 3 states have (on average 42.666666666666664) internal successors, (128), 2 states have internal predecessors, (128), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-12 02:20:25,578 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-12 02:20:25,578 INFO L93 Difference]: Finished difference Result 117490 states and 167414 transitions. [2023-11-12 02:20:25,578 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 117490 states and 167414 transitions. [2023-11-12 02:20:26,103 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 117088 [2023-11-12 02:20:26,437 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 117490 states to 117490 states and 167414 transitions. [2023-11-12 02:20:26,438 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 117490 [2023-11-12 02:20:26,517 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 117490 [2023-11-12 02:20:26,518 INFO L73 IsDeterministic]: Start isDeterministic. Operand 117490 states and 167414 transitions. [2023-11-12 02:20:27,110 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-12 02:20:27,136 INFO L218 hiAutomatonCegarLoop]: Abstraction has 117490 states and 167414 transitions. [2023-11-12 02:20:27,318 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 117490 states and 167414 transitions. [2023-11-12 02:20:28,629 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 117490 to 117362. [2023-11-12 02:20:28,725 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 117362 states, 117362 states have (on average 1.4253847071454133) internal successors, (167286), 117361 states have internal predecessors, (167286), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-12 02:20:29,081 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 117362 states to 117362 states and 167286 transitions. [2023-11-12 02:20:29,081 INFO L240 hiAutomatonCegarLoop]: Abstraction has 117362 states and 167286 transitions. [2023-11-12 02:20:29,082 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-12 02:20:29,082 INFO L428 stractBuchiCegarLoop]: Abstraction has 117362 states and 167286 transitions. [2023-11-12 02:20:29,082 INFO L335 stractBuchiCegarLoop]: ======== Iteration 18 ============ [2023-11-12 02:20:29,082 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 117362 states and 167286 transitions. [2023-11-12 02:20:29,394 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 116960 [2023-11-12 02:20:29,394 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-12 02:20:29,394 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-12 02:20:29,397 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-12 02:20:29,397 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-12 02:20:29,398 INFO L748 eck$LassoCheckResult]: Stem: 624099#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~token~0 := 0;~local~0 := 0; 624100#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~12#1;havoc main_~__retres1~12#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1; 625193#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret30#1, start_simulation_#t~ret31#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 625194#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 625302#L731 assume 1 == ~m_i~0;~m_st~0 := 0; 625198#L731-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 625125#L736-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 625126#L741-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 625182#L746-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 624026#L751-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 624027#L756-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 624144#L761-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 624407#L766-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 624325#L771-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 624028#L776-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 623686#L781-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 623687#L1036 assume !(0 == ~M_E~0); 623782#L1036-2 assume !(0 == ~T1_E~0); 624759#L1041-1 assume !(0 == ~T2_E~0); 624760#L1046-1 assume !(0 == ~T3_E~0); 624073#L1051-1 assume !(0 == ~T4_E~0); 624074#L1056-1 assume !(0 == ~T5_E~0); 624930#L1061-1 assume !(0 == ~T6_E~0); 623955#L1066-1 assume !(0 == ~T7_E~0); 623956#L1071-1 assume !(0 == ~T8_E~0); 624909#L1076-1 assume !(0 == ~T9_E~0); 623845#L1081-1 assume !(0 == ~T10_E~0); 623846#L1086-1 assume !(0 == ~E_M~0); 624270#L1091-1 assume !(0 == ~E_1~0); 625212#L1096-1 assume !(0 == ~E_2~0); 625213#L1101-1 assume !(0 == ~E_3~0); 624339#L1106-1 assume !(0 == ~E_4~0); 624340#L1111-1 assume !(0 == ~E_5~0); 624521#L1116-1 assume !(0 == ~E_6~0); 624522#L1121-1 assume !(0 == ~E_7~0); 624329#L1126-1 assume !(0 == ~E_8~0); 624330#L1131-1 assume !(0 == ~E_9~0); 624635#L1136-1 assume !(0 == ~E_10~0); 624770#L1141-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 624975#L514 assume !(1 == ~m_pc~0); 624976#L514-2 is_master_triggered_~__retres1~0#1 := 0; 624348#L525 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 624349#is_master_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 625073#L1285 assume !(0 != activate_threads_~tmp~1#1); 625270#L1285-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 623977#L533 assume !(1 == ~t1_pc~0); 623978#L533-2 is_transmit1_triggered_~__retres1~1#1 := 0; 624539#L544 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 623740#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 623741#L1293 assume !(0 != activate_threads_~tmp___0~0#1); 624799#L1293-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 624800#L552 assume !(1 == ~t2_pc~0); 624481#L552-2 is_transmit2_triggered_~__retres1~2#1 := 0; 624482#L563 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 624333#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 624334#L1301 assume !(0 != activate_threads_~tmp___1~0#1); 624372#L1301-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 624373#L571 assume !(1 == ~t3_pc~0); 624605#L571-2 is_transmit3_triggered_~__retres1~3#1 := 0; 624694#L582 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 623684#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 623685#L1309 assume !(0 != activate_threads_~tmp___2~0#1); 624526#L1309-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 623768#L590 assume !(1 == ~t4_pc~0); 623769#L590-2 is_transmit4_triggered_~__retres1~4#1 := 0; 624603#L601 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 625431#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 625273#L1317 assume !(0 != activate_threads_~tmp___3~0#1); 624836#L1317-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 624523#L609 assume !(1 == ~t5_pc~0); 624524#L609-2 is_transmit5_triggered_~__retres1~5#1 := 0; 625264#L620 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 625074#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 625075#L1325 assume !(0 != activate_threads_~tmp___4~0#1); 624515#L1325-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 624516#L628 assume !(1 == ~t6_pc~0); 624439#L628-2 is_transmit6_triggered_~__retres1~6#1 := 0; 624438#L639 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 624309#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 624310#L1333 assume !(0 != activate_threads_~tmp___5~0#1); 624882#L1333-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 624883#L647 assume 1 == ~t7_pc~0; 624341#L648 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 624342#L658 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 625089#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 624346#L1341 assume !(0 != activate_threads_~tmp___6~0#1); 624347#L1341-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 625335#L666 assume !(1 == ~t8_pc~0); 624122#L666-2 is_transmit8_triggered_~__retres1~8#1 := 0; 624123#L677 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 624361#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 624553#L1349 assume !(0 != activate_threads_~tmp___7~0#1); 624266#L1349-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 624267#L685 assume 1 == ~t9_pc~0; 625280#L686 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 625105#L696 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 624401#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 624295#L1357 assume !(0 != activate_threads_~tmp___8~0#1); 624296#L1357-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 624726#L704 assume !(1 == ~t10_pc~0); 624286#L704-2 is_transmit10_triggered_~__retres1~10#1 := 0; 624285#L715 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 624576#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 623817#L1365 assume !(0 != activate_threads_~tmp___9~0#1); 623818#L1365-2 havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 624081#L1154 assume 1 == ~M_E~0;~M_E~0 := 2; 624868#L1154-2 assume !(1 == ~T1_E~0); 624050#L1159-1 assume !(1 == ~T2_E~0); 624051#L1164-1 assume !(1 == ~T3_E~0); 629439#L1169-1 assume !(1 == ~T4_E~0); 629033#L1174-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 629031#L1179-1 assume !(1 == ~T6_E~0); 629029#L1184-1 assume !(1 == ~T7_E~0); 629028#L1189-1 assume !(1 == ~T8_E~0); 629026#L1194-1 assume !(1 == ~T9_E~0); 629024#L1199-1 assume !(1 == ~T10_E~0); 628529#L1204-1 assume !(1 == ~E_M~0); 628526#L1209-1 assume !(1 == ~E_1~0); 628524#L1214-1 assume 1 == ~E_2~0;~E_2~0 := 2; 628522#L1219-1 assume !(1 == ~E_3~0); 628139#L1224-1 assume !(1 == ~E_4~0); 628137#L1229-1 assume !(1 == ~E_5~0); 628135#L1234-1 assume !(1 == ~E_6~0); 627888#L1239-1 assume !(1 == ~E_7~0); 627886#L1244-1 assume !(1 == ~E_8~0); 627882#L1249-1 assume !(1 == ~E_9~0); 627694#L1254-1 assume 1 == ~E_10~0;~E_10~0 := 2; 627558#L1259-1 assume { :end_inline_reset_delta_events } true; 627556#L1565-2 [2023-11-12 02:20:29,398 INFO L750 eck$LassoCheckResult]: Loop: 627556#L1565-2 assume !false; 627553#L1566 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 627400#L1011-1 assume !false; 627397#L862 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 627395#L794 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 627383#L851 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 627381#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 627378#L866 assume !(0 != eval_~tmp~0#1); 627379#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 652395#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 652396#L1036-3 assume 0 == ~M_E~0;~M_E~0 := 1; 652391#L1036-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 652392#L1041-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 652387#L1046-3 assume !(0 == ~T3_E~0); 652388#L1051-3 assume !(0 == ~T4_E~0); 652383#L1056-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 652384#L1061-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 652379#L1066-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 652380#L1071-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 652375#L1076-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 652376#L1081-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 652371#L1086-3 assume !(0 == ~E_M~0); 652372#L1091-3 assume !(0 == ~E_1~0); 652367#L1096-3 assume 0 == ~E_2~0;~E_2~0 := 1; 652368#L1101-3 assume 0 == ~E_3~0;~E_3~0 := 1; 652363#L1106-3 assume 0 == ~E_4~0;~E_4~0 := 1; 652364#L1111-3 assume 0 == ~E_5~0;~E_5~0 := 1; 652359#L1116-3 assume 0 == ~E_6~0;~E_6~0 := 1; 652360#L1121-3 assume 0 == ~E_7~0;~E_7~0 := 1; 652355#L1126-3 assume !(0 == ~E_8~0); 652356#L1131-3 assume !(0 == ~E_9~0); 652351#L1136-3 assume 0 == ~E_10~0;~E_10~0 := 1; 652352#L1141-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 652347#L514-36 assume !(1 == ~m_pc~0); 652348#L514-38 is_master_triggered_~__retres1~0#1 := 0; 652330#L525-12 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 652331#is_master_triggered_returnLabel#13 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 651832#L1285-36 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 651833#L1285-38 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 651824#L533-36 assume 1 == ~t1_pc~0; 651825#L534-12 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 651817#L544-12 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 651818#is_transmit1_triggered_returnLabel#13 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 651798#L1293-36 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 651799#L1293-38 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 631970#L552-36 assume !(1 == ~t2_pc~0); 631968#L552-38 is_transmit2_triggered_~__retres1~2#1 := 0; 629621#L563-12 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 629155#is_transmit2_triggered_returnLabel#13 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 629153#L1301-36 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 629151#L1301-38 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 629149#L571-36 assume !(1 == ~t3_pc~0); 628206#L571-38 is_transmit3_triggered_~__retres1~3#1 := 0; 629146#L582-12 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 629144#is_transmit3_triggered_returnLabel#13 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 629142#L1309-36 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 629140#L1309-38 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 629138#L590-36 assume !(1 == ~t4_pc~0); 629134#L590-38 is_transmit4_triggered_~__retres1~4#1 := 0; 629132#L601-12 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 629130#is_transmit4_triggered_returnLabel#13 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 629128#L1317-36 assume !(0 != activate_threads_~tmp___3~0#1); 629125#L1317-38 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 629124#L609-36 assume !(1 == ~t5_pc~0); 629122#L609-38 is_transmit5_triggered_~__retres1~5#1 := 0; 629120#L620-12 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 629118#is_transmit5_triggered_returnLabel#13 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 629116#L1325-36 assume !(0 != activate_threads_~tmp___4~0#1); 629114#L1325-38 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 629112#L628-36 assume 1 == ~t6_pc~0; 629109#L629-12 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 629107#L639-12 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 629105#is_transmit6_triggered_returnLabel#13 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 629103#L1333-36 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 629101#L1333-38 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 629099#L647-36 assume !(1 == ~t7_pc~0); 629095#L647-38 is_transmit7_triggered_~__retres1~7#1 := 0; 629091#L658-12 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 629089#is_transmit7_triggered_returnLabel#13 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 629087#L1341-36 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 629085#L1341-38 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 629083#L666-36 assume !(1 == ~t8_pc~0); 629081#L666-38 is_transmit8_triggered_~__retres1~8#1 := 0; 629077#L677-12 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 629075#is_transmit8_triggered_returnLabel#13 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 629073#L1349-36 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 629071#L1349-38 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 629069#L685-36 assume 1 == ~t9_pc~0; 629064#L686-12 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 629061#L696-12 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 629059#is_transmit9_triggered_returnLabel#13 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 629057#L1357-36 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 629055#L1357-38 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 629053#L704-36 assume !(1 == ~t10_pc~0); 629051#L704-38 is_transmit10_triggered_~__retres1~10#1 := 0; 629048#L715-12 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 629046#is_transmit10_triggered_returnLabel#13 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 629044#L1365-36 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 629042#L1365-38 havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 629040#L1154-3 assume 1 == ~M_E~0;~M_E~0 := 2; 628233#L1154-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 629037#L1159-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 628594#L1164-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 628590#L1169-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 628588#L1174-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 628586#L1179-3 assume !(1 == ~T6_E~0); 628584#L1184-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 628582#L1189-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 628579#L1194-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 628577#L1199-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 628575#L1204-3 assume 1 == ~E_M~0;~E_M~0 := 2; 628571#L1209-3 assume 1 == ~E_1~0;~E_1~0 := 2; 628155#L1214-3 assume 1 == ~E_2~0;~E_2~0 := 2; 628152#L1219-3 assume !(1 == ~E_3~0); 628150#L1224-3 assume 1 == ~E_4~0;~E_4~0 := 2; 628148#L1229-3 assume 1 == ~E_5~0;~E_5~0 := 2; 628146#L1234-3 assume 1 == ~E_6~0;~E_6~0 := 2; 628144#L1239-3 assume 1 == ~E_7~0;~E_7~0 := 2; 628142#L1244-3 assume 1 == ~E_8~0;~E_8~0 := 2; 628138#L1249-3 assume 1 == ~E_9~0;~E_9~0 := 2; 628136#L1254-3 assume 1 == ~E_10~0;~E_10~0 := 2; 628134#L1259-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 628034#L794-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 628032#L851-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 628030#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret30#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret30#1;havoc start_simulation_#t~ret30#1; 628028#L1584 assume !(0 == start_simulation_~tmp~3#1); 628025#L1584-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret29#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 627767#L794-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 627754#L851-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 627752#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret29#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret29#1;havoc stop_simulation_#t~ret29#1; 627750#L1539 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 627749#L1546 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 627746#stop_simulation_returnLabel#1 start_simulation_#t~ret31#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret29#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret31#1;havoc start_simulation_#t~ret31#1; 627559#L1597 assume !(0 != start_simulation_~tmp___0~1#1); 627556#L1565-2 [2023-11-12 02:20:29,399 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-12 02:20:29,399 INFO L85 PathProgramCache]: Analyzing trace with hash -671092981, now seen corresponding path program 1 times [2023-11-12 02:20:29,399 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-12 02:20:29,400 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [669822673] [2023-11-12 02:20:29,400 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-12 02:20:29,400 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-12 02:20:29,416 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-12 02:20:29,476 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-12 02:20:29,477 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-12 02:20:29,477 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [669822673] [2023-11-12 02:20:29,477 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [669822673] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-12 02:20:29,477 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-12 02:20:29,477 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-12 02:20:29,478 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [873389106] [2023-11-12 02:20:29,478 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-12 02:20:29,478 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-12 02:20:29,478 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-12 02:20:29,479 INFO L85 PathProgramCache]: Analyzing trace with hash 1280717953, now seen corresponding path program 1 times [2023-11-12 02:20:29,479 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-12 02:20:29,479 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [773204286] [2023-11-12 02:20:29,479 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-12 02:20:29,479 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-12 02:20:29,494 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-12 02:20:29,527 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-12 02:20:29,527 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-12 02:20:29,527 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [773204286] [2023-11-12 02:20:29,528 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [773204286] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-12 02:20:29,528 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-12 02:20:29,528 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-12 02:20:29,528 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [760292407] [2023-11-12 02:20:29,528 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-12 02:20:29,529 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-12 02:20:29,529 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-12 02:20:29,529 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2023-11-12 02:20:29,529 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2023-11-12 02:20:29,530 INFO L87 Difference]: Start difference. First operand 117362 states and 167286 transitions. cyclomatic complexity: 49956 Second operand has 4 states, 4 states have (on average 32.0) internal successors, (128), 3 states have internal predecessors, (128), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-12 02:20:31,217 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-12 02:20:31,217 INFO L93 Difference]: Finished difference Result 287061 states and 406079 transitions. [2023-11-12 02:20:31,217 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 287061 states and 406079 transitions. [2023-11-12 02:20:33,328 INFO L131 ngComponentsAnalysis]: Automaton has 48 accepting balls. 280996 [2023-11-12 02:20:34,137 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 287061 states to 287061 states and 406079 transitions. [2023-11-12 02:20:34,138 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 287061 [2023-11-12 02:20:34,332 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 287061 [2023-11-12 02:20:34,333 INFO L73 IsDeterministic]: Start isDeterministic. Operand 287061 states and 406079 transitions. [2023-11-12 02:20:35,198 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-12 02:20:35,198 INFO L218 hiAutomatonCegarLoop]: Abstraction has 287061 states and 406079 transitions. [2023-11-12 02:20:35,321 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 287061 states and 406079 transitions. [2023-11-12 02:20:37,262 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 287061 to 227905. [2023-11-12 02:20:37,403 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 227905 states, 227905 states have (on average 1.4191307781751168) internal successors, (323427), 227904 states have internal predecessors, (323427), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-12 02:20:38,753 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 227905 states to 227905 states and 323427 transitions. [2023-11-12 02:20:38,754 INFO L240 hiAutomatonCegarLoop]: Abstraction has 227905 states and 323427 transitions. [2023-11-12 02:20:38,754 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2023-11-12 02:20:38,755 INFO L428 stractBuchiCegarLoop]: Abstraction has 227905 states and 323427 transitions. [2023-11-12 02:20:38,755 INFO L335 stractBuchiCegarLoop]: ======== Iteration 19 ============ [2023-11-12 02:20:38,755 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 227905 states and 323427 transitions. [2023-11-12 02:20:39,296 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 227312 [2023-11-12 02:20:39,296 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-12 02:20:39,296 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-12 02:20:39,300 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-12 02:20:39,300 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-12 02:20:39,301 INFO L748 eck$LassoCheckResult]: Stem: 1028524#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~token~0 := 0;~local~0 := 0; 1028525#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~12#1;havoc main_~__retres1~12#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1; 1029571#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret30#1, start_simulation_#t~ret31#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 1029572#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 1029687#L731 assume 1 == ~m_i~0;~m_st~0 := 0; 1029575#L731-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 1029506#L736-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 1029507#L741-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 1029559#L746-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 1028452#L751-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 1028453#L756-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 1028570#L761-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 1028828#L766-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 1028748#L771-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 1028454#L776-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 1028119#L781-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 1028120#L1036 assume !(0 == ~M_E~0); 1028215#L1036-2 assume !(0 == ~T1_E~0); 1029191#L1041-1 assume !(0 == ~T2_E~0); 1029192#L1046-1 assume !(0 == ~T3_E~0); 1028496#L1051-1 assume !(0 == ~T4_E~0); 1028497#L1056-1 assume !(0 == ~T5_E~0); 1029349#L1061-1 assume !(0 == ~T6_E~0); 1028386#L1066-1 assume !(0 == ~T7_E~0); 1028387#L1071-1 assume !(0 == ~T8_E~0); 1029329#L1076-1 assume !(0 == ~T9_E~0); 1028278#L1081-1 assume !(0 == ~T10_E~0); 1028279#L1086-1 assume !(0 == ~E_M~0); 1028689#L1091-1 assume !(0 == ~E_1~0); 1029585#L1096-1 assume !(0 == ~E_2~0); 1029586#L1101-1 assume !(0 == ~E_3~0); 1028763#L1106-1 assume !(0 == ~E_4~0); 1028764#L1111-1 assume !(0 == ~E_5~0); 1028949#L1116-1 assume !(0 == ~E_6~0); 1028950#L1121-1 assume !(0 == ~E_7~0); 1028752#L1126-1 assume !(0 == ~E_8~0); 1028753#L1131-1 assume !(0 == ~E_9~0); 1029067#L1136-1 assume !(0 == ~E_10~0); 1029201#L1141-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1029385#L514 assume !(1 == ~m_pc~0); 1029386#L514-2 is_master_triggered_~__retres1~0#1 := 0; 1028769#L525 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1028770#is_master_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1029462#L1285 assume !(0 != activate_threads_~tmp~1#1); 1029649#L1285-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1028405#L533 assume !(1 == ~t1_pc~0); 1028406#L533-2 is_transmit1_triggered_~__retres1~1#1 := 0; 1028966#L544 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1028171#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1028172#L1293 assume !(0 != activate_threads_~tmp___0~0#1); 1029226#L1293-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1029227#L552 assume !(1 == ~t2_pc~0); 1028902#L552-2 is_transmit2_triggered_~__retres1~2#1 := 0; 1028903#L563 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1028756#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1028757#L1301 assume !(0 != activate_threads_~tmp___1~0#1); 1028782#L1301-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1028783#L571 assume !(1 == ~t3_pc~0); 1029032#L571-2 is_transmit3_triggered_~__retres1~3#1 := 0; 1029123#L582 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1028117#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1028118#L1309 assume !(0 != activate_threads_~tmp___2~0#1); 1028954#L1309-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1028201#L590 assume !(1 == ~t4_pc~0); 1028202#L590-2 is_transmit4_triggered_~__retres1~4#1 := 0; 1029031#L601 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1029792#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 1029660#L1317 assume !(0 != activate_threads_~tmp___3~0#1); 1029256#L1317-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1028951#L609 assume !(1 == ~t5_pc~0); 1028952#L609-2 is_transmit5_triggered_~__retres1~5#1 := 0; 1029646#L620 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1029464#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 1029465#L1325 assume !(0 != activate_threads_~tmp___4~0#1); 1028942#L1325-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1028943#L628 assume !(1 == ~t6_pc~0); 1028862#L628-2 is_transmit6_triggered_~__retres1~6#1 := 0; 1028861#L639 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1028729#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 1028730#L1333 assume !(0 != activate_threads_~tmp___5~0#1); 1029303#L1333-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1029304#L647 assume !(1 == ~t7_pc~0); 1029445#L647-2 is_transmit7_triggered_~__retres1~7#1 := 0; 1029479#L658 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1029480#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 1028765#L1341 assume !(0 != activate_threads_~tmp___6~0#1); 1028766#L1341-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 1029715#L666 assume !(1 == ~t8_pc~0); 1028547#L666-2 is_transmit8_triggered_~__retres1~8#1 := 0; 1028548#L677 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 1028781#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 1028980#L1349 assume !(0 != activate_threads_~tmp___7~0#1); 1028686#L1349-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 1028687#L685 assume 1 == ~t9_pc~0; 1029668#L686 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 1029491#L696 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 1028820#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 1028717#L1357 assume !(0 != activate_threads_~tmp___8~0#1); 1028718#L1357-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 1029160#L704 assume !(1 == ~t10_pc~0); 1028708#L704-2 is_transmit10_triggered_~__retres1~10#1 := 0; 1028707#L715 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 1029000#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 1028251#L1365 assume !(0 != activate_threads_~tmp___9~0#1); 1028252#L1365-2 havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1028506#L1154 assume 1 == ~M_E~0;~M_E~0 := 2; 1029287#L1154-2 assume !(1 == ~T1_E~0); 1029694#L1159-1 assume !(1 == ~T2_E~0); 1029754#L1164-1 assume !(1 == ~T3_E~0); 1029755#L1169-1 assume !(1 == ~T4_E~0); 1028821#L1174-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 1028822#L1179-1 assume !(1 == ~T6_E~0); 1028460#L1184-1 assume !(1 == ~T7_E~0); 1028461#L1189-1 assume !(1 == ~T8_E~0); 1028672#L1194-1 assume !(1 == ~T9_E~0); 1028673#L1199-1 assume !(1 == ~T10_E~0); 1028626#L1204-1 assume !(1 == ~E_M~0); 1028627#L1209-1 assume !(1 == ~E_1~0); 1029250#L1214-1 assume 1 == ~E_2~0;~E_2~0 := 2; 1029251#L1219-1 assume !(1 == ~E_3~0); 1029700#L1224-1 assume !(1 == ~E_4~0); 1029007#L1229-1 assume !(1 == ~E_5~0); 1028345#L1234-1 assume !(1 == ~E_6~0); 1028346#L1239-1 assume !(1 == ~E_7~0); 1028401#L1244-1 assume !(1 == ~E_8~0); 1028402#L1249-1 assume !(1 == ~E_9~0); 1029424#L1254-1 assume 1 == ~E_10~0;~E_10~0 := 2; 1028245#L1259-1 assume { :end_inline_reset_delta_events } true; 1028246#L1565-2 [2023-11-12 02:20:39,301 INFO L750 eck$LassoCheckResult]: Loop: 1028246#L1565-2 assume !false; 1124236#L1566 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 1124231#L1011-1 assume !false; 1124229#L862 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 1124227#L794 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 1124206#L851 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 1124198#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 1123944#L866 assume !(0 != eval_~tmp~0#1); 1123945#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 1136988#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 1136987#L1036-3 assume 0 == ~M_E~0;~M_E~0 := 1; 1136986#L1036-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 1136985#L1041-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 1136984#L1046-3 assume !(0 == ~T3_E~0); 1136983#L1051-3 assume !(0 == ~T4_E~0); 1136982#L1056-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 1136981#L1061-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 1136980#L1066-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 1136979#L1071-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 1136978#L1076-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 1136977#L1081-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 1136976#L1086-3 assume !(0 == ~E_M~0); 1136975#L1091-3 assume !(0 == ~E_1~0); 1136974#L1096-3 assume 0 == ~E_2~0;~E_2~0 := 1; 1136973#L1101-3 assume 0 == ~E_3~0;~E_3~0 := 1; 1136972#L1106-3 assume 0 == ~E_4~0;~E_4~0 := 1; 1136971#L1111-3 assume 0 == ~E_5~0;~E_5~0 := 1; 1136970#L1116-3 assume 0 == ~E_6~0;~E_6~0 := 1; 1136969#L1121-3 assume 0 == ~E_7~0;~E_7~0 := 1; 1136968#L1126-3 assume !(0 == ~E_8~0); 1136967#L1131-3 assume !(0 == ~E_9~0); 1136966#L1136-3 assume 0 == ~E_10~0;~E_10~0 := 1; 1136965#L1141-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1136964#L514-36 assume !(1 == ~m_pc~0); 1136963#L514-38 is_master_triggered_~__retres1~0#1 := 0; 1136962#L525-12 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1136961#is_master_triggered_returnLabel#13 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1136959#L1285-36 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 1136957#L1285-38 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1136955#L533-36 assume !(1 == ~t1_pc~0); 1136953#L533-38 is_transmit1_triggered_~__retres1~1#1 := 0; 1136950#L544-12 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1136948#is_transmit1_triggered_returnLabel#13 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1136946#L1293-36 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 1136943#L1293-38 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1136941#L552-36 assume !(1 == ~t2_pc~0); 1122436#L552-38 is_transmit2_triggered_~__retres1~2#1 := 0; 1136938#L563-12 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1136936#is_transmit2_triggered_returnLabel#13 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1136934#L1301-36 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 1136931#L1301-38 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1124561#L571-36 assume !(1 == ~t3_pc~0); 1124560#L571-38 is_transmit3_triggered_~__retres1~3#1 := 0; 1124558#L582-12 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1124556#is_transmit3_triggered_returnLabel#13 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1124554#L1309-36 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 1124552#L1309-38 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1124550#L590-36 assume !(1 == ~t4_pc~0); 1124545#L590-38 is_transmit4_triggered_~__retres1~4#1 := 0; 1124543#L601-12 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1124541#is_transmit4_triggered_returnLabel#13 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 1124539#L1317-36 assume !(0 != activate_threads_~tmp___3~0#1); 1124536#L1317-38 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1124534#L609-36 assume !(1 == ~t5_pc~0); 1124531#L609-38 is_transmit5_triggered_~__retres1~5#1 := 0; 1124529#L620-12 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1124527#is_transmit5_triggered_returnLabel#13 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 1124525#L1325-36 assume !(0 != activate_threads_~tmp___4~0#1); 1124523#L1325-38 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1124521#L628-36 assume 1 == ~t6_pc~0; 1124517#L629-12 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 1124515#L639-12 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1124513#is_transmit6_triggered_returnLabel#13 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 1124511#L1333-36 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 1124509#L1333-38 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1124507#L647-36 assume !(1 == ~t7_pc~0); 1079013#L647-38 is_transmit7_triggered_~__retres1~7#1 := 0; 1124504#L658-12 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1124502#is_transmit7_triggered_returnLabel#13 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 1124500#L1341-36 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 1124498#L1341-38 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 1124496#L666-36 assume 1 == ~t8_pc~0; 1124493#L667-12 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 1124491#L677-12 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 1124489#is_transmit8_triggered_returnLabel#13 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 1124487#L1349-36 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 1124485#L1349-38 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 1124483#L685-36 assume 1 == ~t9_pc~0; 1124481#L686-12 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 1124478#L696-12 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 1124476#is_transmit9_triggered_returnLabel#13 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 1124474#L1357-36 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 1124472#L1357-38 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 1124470#L704-36 assume 1 == ~t10_pc~0; 1124467#L705-12 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 1124465#L715-12 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 1124463#is_transmit10_triggered_returnLabel#13 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 1124462#L1365-36 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 1124461#L1365-38 havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1124460#L1154-3 assume 1 == ~M_E~0;~M_E~0 := 2; 1093826#L1154-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 1124457#L1159-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 1124455#L1164-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 1112895#L1169-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 1124452#L1174-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 1124450#L1179-3 assume !(1 == ~T6_E~0); 1124448#L1184-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 1124445#L1189-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 1124443#L1194-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 1124441#L1199-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 1124439#L1204-3 assume 1 == ~E_M~0;~E_M~0 := 2; 1096820#L1209-3 assume 1 == ~E_1~0;~E_1~0 := 2; 1124436#L1214-3 assume 1 == ~E_2~0;~E_2~0 := 2; 1124435#L1219-3 assume !(1 == ~E_3~0); 1124433#L1224-3 assume 1 == ~E_4~0;~E_4~0 := 2; 1124431#L1229-3 assume 1 == ~E_5~0;~E_5~0 := 2; 1124429#L1234-3 assume 1 == ~E_6~0;~E_6~0 := 2; 1124427#L1239-3 assume 1 == ~E_7~0;~E_7~0 := 2; 1124425#L1244-3 assume 1 == ~E_8~0;~E_8~0 := 2; 1109632#L1249-3 assume 1 == ~E_9~0;~E_9~0 := 2; 1124423#L1254-3 assume 1 == ~E_10~0;~E_10~0 := 2; 1124421#L1259-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 1124389#L794-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 1124387#L851-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 1124385#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret30#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret30#1;havoc start_simulation_#t~ret30#1; 1124383#L1584 assume !(0 == start_simulation_~tmp~3#1); 1124380#L1584-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret29#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 1124262#L794-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 1124251#L851-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 1124248#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret29#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret29#1;havoc stop_simulation_#t~ret29#1; 1124246#L1539 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 1124244#L1546 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 1124242#stop_simulation_returnLabel#1 start_simulation_#t~ret31#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret29#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret31#1;havoc start_simulation_#t~ret31#1; 1124240#L1597 assume !(0 != start_simulation_~tmp___0~1#1); 1028246#L1565-2 [2023-11-12 02:20:39,302 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-12 02:20:39,302 INFO L85 PathProgramCache]: Analyzing trace with hash 1730432140, now seen corresponding path program 1 times [2023-11-12 02:20:39,303 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-12 02:20:39,303 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1519546393] [2023-11-12 02:20:39,303 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-12 02:20:39,303 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-12 02:20:39,320 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-12 02:20:39,384 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-12 02:20:39,384 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-12 02:20:39,384 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1519546393] [2023-11-12 02:20:39,385 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1519546393] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-12 02:20:39,385 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-12 02:20:39,385 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-12 02:20:39,385 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [485766839] [2023-11-12 02:20:39,385 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-12 02:20:39,386 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-12 02:20:39,387 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-12 02:20:39,387 INFO L85 PathProgramCache]: Analyzing trace with hash 1912594688, now seen corresponding path program 1 times [2023-11-12 02:20:39,387 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-12 02:20:39,387 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1877310422] [2023-11-12 02:20:39,388 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-12 02:20:39,388 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-12 02:20:39,402 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-12 02:20:39,442 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-12 02:20:39,442 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-12 02:20:39,442 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1877310422] [2023-11-12 02:20:39,442 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1877310422] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-12 02:20:39,445 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-12 02:20:39,445 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-12 02:20:39,445 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [316964189] [2023-11-12 02:20:39,446 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-12 02:20:39,447 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-12 02:20:39,447 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-12 02:20:39,447 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2023-11-12 02:20:39,448 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2023-11-12 02:20:39,448 INFO L87 Difference]: Start difference. First operand 227905 states and 323427 transitions. cyclomatic complexity: 95554 Second operand has 4 states, 4 states have (on average 32.0) internal successors, (128), 3 states have internal predecessors, (128), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-12 02:20:42,073 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-12 02:20:42,073 INFO L93 Difference]: Finished difference Result 542656 states and 765248 transitions. [2023-11-12 02:20:42,073 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 542656 states and 765248 transitions. [2023-11-12 02:20:45,992 INFO L131 ngComponentsAnalysis]: Automaton has 48 accepting balls. 530800 [2023-11-12 02:20:47,077 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 542656 states to 542656 states and 765248 transitions. [2023-11-12 02:20:47,078 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 542656 [2023-11-12 02:20:47,297 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 542656 [2023-11-12 02:20:47,298 INFO L73 IsDeterministic]: Start isDeterministic. Operand 542656 states and 765248 transitions. [2023-11-12 02:20:48,161 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-12 02:20:48,161 INFO L218 hiAutomatonCegarLoop]: Abstraction has 542656 states and 765248 transitions. [2023-11-12 02:20:48,407 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 542656 states and 765248 transitions.