./Ultimate.py --spec ../../sv-benchmarks/c/properties/termination.prp --file ../../sv-benchmarks/c/systemc/token_ring.14.cil.c --full-output --architecture 32bit -------------------------------------------------------------------------------- Checking for termination Using default analysis Version cf1a7837 Calling Ultimate with: /usr/lib/jvm/java-1.11.0-openjdk-amd64/bin/java -Dosgi.configuration.area=/tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_c1952168-68ee-40ba-b0ab-0972acb3d83f/bin/uautomizer-verify-uTZkv6EMXl/data/config -Xmx15G -Xms4m -jar /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_c1952168-68ee-40ba-b0ab-0972acb3d83f/bin/uautomizer-verify-uTZkv6EMXl/plugins/org.eclipse.equinox.launcher_1.5.800.v20200727-1323.jar -data @noDefault -ultimatedata /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_c1952168-68ee-40ba-b0ab-0972acb3d83f/bin/uautomizer-verify-uTZkv6EMXl/data -tc /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_c1952168-68ee-40ba-b0ab-0972acb3d83f/bin/uautomizer-verify-uTZkv6EMXl/config/AutomizerTermination.xml -i ../../sv-benchmarks/c/systemc/token_ring.14.cil.c -s /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_c1952168-68ee-40ba-b0ab-0972acb3d83f/bin/uautomizer-verify-uTZkv6EMXl/config/svcomp-Termination-32bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_c1952168-68ee-40ba-b0ab-0972acb3d83f/bin/uautomizer-verify-uTZkv6EMXl --witnessprinter.witness.filename witness --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(F end) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 32bit --witnessprinter.graph.data.programhash 78a96934dff25285973ef889167a345947d7e73ab8a2ec405d96bd61e690530f --- Real Ultimate output --- This is Ultimate 0.2.3-dev-cf1a783 [2023-11-12 02:03:48,074 INFO L188 SettingsManager]: Resetting all preferences to default values... [2023-11-12 02:03:48,186 INFO L114 SettingsManager]: Loading settings from /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_c1952168-68ee-40ba-b0ab-0972acb3d83f/bin/uautomizer-verify-uTZkv6EMXl/config/svcomp-Termination-32bit-Automizer_Default.epf [2023-11-12 02:03:48,193 WARN L101 SettingsManager]: Preference file contains the following unknown settings: [2023-11-12 02:03:48,194 WARN L103 SettingsManager]: * de.uni_freiburg.informatik.ultimate.core.Log level for class [2023-11-12 02:03:48,236 INFO L130 SettingsManager]: Preferences different from defaults after loading the file: [2023-11-12 02:03:48,237 INFO L151 SettingsManager]: Preferences of UltimateCore differ from their defaults: [2023-11-12 02:03:48,237 INFO L153 SettingsManager]: * Log level for class=de.uni_freiburg.informatik.ultimate.lib.smtlibutils.quantifier.QuantifierPusher=ERROR; [2023-11-12 02:03:48,238 INFO L151 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2023-11-12 02:03:48,244 INFO L153 SettingsManager]: * Create parallel compositions if possible=false [2023-11-12 02:03:48,245 INFO L153 SettingsManager]: * Use SBE=true [2023-11-12 02:03:48,245 INFO L151 SettingsManager]: Preferences of BuchiAutomizer differ from their defaults: [2023-11-12 02:03:48,246 INFO L153 SettingsManager]: * NCSB implementation=INTSET_LAZY3 [2023-11-12 02:03:48,247 INFO L153 SettingsManager]: * Use old map elimination=false [2023-11-12 02:03:48,248 INFO L153 SettingsManager]: * Use external solver (rank synthesis)=false [2023-11-12 02:03:48,248 INFO L153 SettingsManager]: * Use only trivial implications for array writes=true [2023-11-12 02:03:48,249 INFO L153 SettingsManager]: * Rank analysis=LINEAR_WITH_GUESSES [2023-11-12 02:03:48,250 INFO L151 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2023-11-12 02:03:48,250 INFO L153 SettingsManager]: * Pointer base address is valid at dereference=ASSUME [2023-11-12 02:03:48,251 INFO L153 SettingsManager]: * sizeof long=4 [2023-11-12 02:03:48,251 INFO L153 SettingsManager]: * Overapproximate operations on floating types=true [2023-11-12 02:03:48,252 INFO L153 SettingsManager]: * sizeof POINTER=4 [2023-11-12 02:03:48,252 INFO L153 SettingsManager]: * Check division by zero=IGNORE [2023-11-12 02:03:48,253 INFO L153 SettingsManager]: * Pointer to allocated memory at dereference=ASSUME [2023-11-12 02:03:48,253 INFO L153 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=ASSUME [2023-11-12 02:03:48,254 INFO L153 SettingsManager]: * Check array bounds for arrays that are off heap=ASSUME [2023-11-12 02:03:48,264 INFO L153 SettingsManager]: * Check unreachability of reach_error function=false [2023-11-12 02:03:48,265 INFO L153 SettingsManager]: * sizeof long double=12 [2023-11-12 02:03:48,265 INFO L153 SettingsManager]: * Check if freed pointer was valid=false [2023-11-12 02:03:48,266 INFO L153 SettingsManager]: * Assume nondeterminstic values are in range=false [2023-11-12 02:03:48,267 INFO L153 SettingsManager]: * Use constant arrays=true [2023-11-12 02:03:48,267 INFO L151 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2023-11-12 02:03:48,268 INFO L153 SettingsManager]: * Size of a code block=SequenceOfStatements [2023-11-12 02:03:48,268 INFO L151 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2023-11-12 02:03:48,268 INFO L153 SettingsManager]: * Trace refinement strategy=CAMEL [2023-11-12 02:03:48,269 INFO L151 SettingsManager]: Preferences of IcfgTransformer differ from their defaults: [2023-11-12 02:03:48,269 INFO L153 SettingsManager]: * TransformationType=MODULO_NEIGHBOR WARNING: An illegal reflective access operation has occurred WARNING: Illegal reflective access by com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 (file:/tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_c1952168-68ee-40ba-b0ab-0972acb3d83f/bin/uautomizer-verify-uTZkv6EMXl/plugins/com.sun.xml.bind_2.2.0.v201505121915.jar) to method java.lang.ClassLoader.defineClass(java.lang.String,byte[],int,int) WARNING: Please consider reporting this to the maintainers of com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 WARNING: Use --illegal-access=warn to enable warnings of further illegal reflective access operations WARNING: All illegal access operations will be denied in a future release Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_c1952168-68ee-40ba-b0ab-0972acb3d83f/bin/uautomizer-verify-uTZkv6EMXl Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(F end) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 32bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> 78a96934dff25285973ef889167a345947d7e73ab8a2ec405d96bd61e690530f [2023-11-12 02:03:48,604 INFO L75 nceAwareModelManager]: Repository-Root is: /tmp [2023-11-12 02:03:48,663 INFO L261 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2023-11-12 02:03:48,666 INFO L217 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2023-11-12 02:03:48,667 INFO L270 PluginConnector]: Initializing CDTParser... [2023-11-12 02:03:48,668 INFO L274 PluginConnector]: CDTParser initialized [2023-11-12 02:03:48,669 INFO L431 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_c1952168-68ee-40ba-b0ab-0972acb3d83f/bin/uautomizer-verify-uTZkv6EMXl/../../sv-benchmarks/c/systemc/token_ring.14.cil.c [2023-11-12 02:03:51,619 INFO L533 CDTParser]: Created temporary CDT project at NULL [2023-11-12 02:03:51,970 INFO L384 CDTParser]: Found 1 translation units. [2023-11-12 02:03:51,971 INFO L180 CDTParser]: Scanning /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_c1952168-68ee-40ba-b0ab-0972acb3d83f/sv-benchmarks/c/systemc/token_ring.14.cil.c [2023-11-12 02:03:51,991 INFO L427 CDTParser]: About to delete temporary CDT project at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_c1952168-68ee-40ba-b0ab-0972acb3d83f/bin/uautomizer-verify-uTZkv6EMXl/data/46d3d06af/0ca7f93672474f4d967ea9c0614b8c67/FLAG044de49a0 [2023-11-12 02:03:52,009 INFO L435 CDTParser]: Successfully deleted /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_c1952168-68ee-40ba-b0ab-0972acb3d83f/bin/uautomizer-verify-uTZkv6EMXl/data/46d3d06af/0ca7f93672474f4d967ea9c0614b8c67 [2023-11-12 02:03:52,014 INFO L299 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2023-11-12 02:03:52,016 INFO L133 ToolchainWalker]: Walking toolchain with 6 elements. [2023-11-12 02:03:52,020 INFO L112 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2023-11-12 02:03:52,021 INFO L270 PluginConnector]: Initializing CACSL2BoogieTranslator... [2023-11-12 02:03:52,026 INFO L274 PluginConnector]: CACSL2BoogieTranslator initialized [2023-11-12 02:03:52,027 INFO L184 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 12.11 02:03:52" (1/1) ... [2023-11-12 02:03:52,028 INFO L204 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@52f5b41c and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 12.11 02:03:52, skipping insertion in model container [2023-11-12 02:03:52,029 INFO L184 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 12.11 02:03:52" (1/1) ... [2023-11-12 02:03:52,109 INFO L177 MainTranslator]: Built tables and reachable declarations [2023-11-12 02:03:52,437 INFO L209 PostProcessor]: Analyzing one entry point: main [2023-11-12 02:03:52,465 INFO L202 MainTranslator]: Completed pre-run [2023-11-12 02:03:52,546 INFO L209 PostProcessor]: Analyzing one entry point: main [2023-11-12 02:03:52,570 INFO L206 MainTranslator]: Completed translation [2023-11-12 02:03:52,571 INFO L201 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 12.11 02:03:52 WrapperNode [2023-11-12 02:03:52,571 INFO L131 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2023-11-12 02:03:52,572 INFO L112 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2023-11-12 02:03:52,572 INFO L270 PluginConnector]: Initializing Boogie Procedure Inliner... [2023-11-12 02:03:52,572 INFO L274 PluginConnector]: Boogie Procedure Inliner initialized [2023-11-12 02:03:52,584 INFO L184 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 12.11 02:03:52" (1/1) ... [2023-11-12 02:03:52,604 INFO L184 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 12.11 02:03:52" (1/1) ... [2023-11-12 02:03:52,744 INFO L138 Inliner]: procedures = 52, calls = 69, calls flagged for inlining = 64, calls inlined = 272, statements flattened = 4173 [2023-11-12 02:03:52,745 INFO L131 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2023-11-12 02:03:52,746 INFO L112 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2023-11-12 02:03:52,746 INFO L270 PluginConnector]: Initializing Boogie Preprocessor... [2023-11-12 02:03:52,746 INFO L274 PluginConnector]: Boogie Preprocessor initialized [2023-11-12 02:03:52,756 INFO L184 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 12.11 02:03:52" (1/1) ... [2023-11-12 02:03:52,756 INFO L184 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 12.11 02:03:52" (1/1) ... [2023-11-12 02:03:52,774 INFO L184 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 12.11 02:03:52" (1/1) ... [2023-11-12 02:03:52,774 INFO L184 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 12.11 02:03:52" (1/1) ... [2023-11-12 02:03:52,841 INFO L184 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 12.11 02:03:52" (1/1) ... [2023-11-12 02:03:52,882 INFO L184 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 12.11 02:03:52" (1/1) ... [2023-11-12 02:03:52,888 INFO L184 PluginConnector]: Executing the observer LTLStepAnnotator from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 12.11 02:03:52" (1/1) ... [2023-11-12 02:03:52,902 INFO L184 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 12.11 02:03:52" (1/1) ... [2023-11-12 02:03:52,914 INFO L131 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2023-11-12 02:03:52,915 INFO L112 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2023-11-12 02:03:52,915 INFO L270 PluginConnector]: Initializing RCFGBuilder... [2023-11-12 02:03:52,915 INFO L274 PluginConnector]: RCFGBuilder initialized [2023-11-12 02:03:52,916 INFO L184 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 12.11 02:03:52" (1/1) ... [2023-11-12 02:03:52,922 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2023-11-12 02:03:52,933 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_c1952168-68ee-40ba-b0ab-0972acb3d83f/bin/uautomizer-verify-uTZkv6EMXl/z3 [2023-11-12 02:03:52,946 INFO L229 MonitoredProcess]: Starting monitored process 1 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_c1952168-68ee-40ba-b0ab-0972acb3d83f/bin/uautomizer-verify-uTZkv6EMXl/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2023-11-12 02:03:52,964 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_c1952168-68ee-40ba-b0ab-0972acb3d83f/bin/uautomizer-verify-uTZkv6EMXl/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (1)] Waiting until timeout for monitored process [2023-11-12 02:03:52,988 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocInit [2023-11-12 02:03:52,988 INFO L130 BoogieDeclarations]: Found specification of procedure write~init~int [2023-11-12 02:03:52,989 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2023-11-12 02:03:52,989 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2023-11-12 02:03:53,118 INFO L236 CfgBuilder]: Building ICFG [2023-11-12 02:03:53,120 INFO L262 CfgBuilder]: Building CFG for each procedure with an implementation [2023-11-12 02:03:55,866 INFO L277 CfgBuilder]: Performing block encoding [2023-11-12 02:03:55,897 INFO L297 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2023-11-12 02:03:55,898 INFO L302 CfgBuilder]: Removed 15 assume(true) statements. [2023-11-12 02:03:55,902 INFO L201 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 12.11 02:03:55 BoogieIcfgContainer [2023-11-12 02:03:55,902 INFO L131 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2023-11-12 02:03:55,904 INFO L112 PluginConnector]: ------------------------BuchiAutomizer---------------------------- [2023-11-12 02:03:55,904 INFO L270 PluginConnector]: Initializing BuchiAutomizer... [2023-11-12 02:03:55,908 INFO L274 PluginConnector]: BuchiAutomizer initialized [2023-11-12 02:03:55,908 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2023-11-12 02:03:55,908 INFO L184 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "CDTParser AST 12.11 02:03:52" (1/3) ... [2023-11-12 02:03:55,909 INFO L204 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@e4560a0 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 12.11 02:03:55, skipping insertion in model container [2023-11-12 02:03:55,910 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2023-11-12 02:03:55,910 INFO L184 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 12.11 02:03:52" (2/3) ... [2023-11-12 02:03:55,910 INFO L204 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@e4560a0 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 12.11 02:03:55, skipping insertion in model container [2023-11-12 02:03:55,910 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2023-11-12 02:03:55,910 INFO L184 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 12.11 02:03:55" (3/3) ... [2023-11-12 02:03:55,912 INFO L332 chiAutomizerObserver]: Analyzing ICFG token_ring.14.cil.c [2023-11-12 02:03:56,009 INFO L303 stractBuchiCegarLoop]: Interprodecural is true [2023-11-12 02:03:56,010 INFO L304 stractBuchiCegarLoop]: Hoare is false [2023-11-12 02:03:56,010 INFO L305 stractBuchiCegarLoop]: Compute interpolants for ForwardPredicates [2023-11-12 02:03:56,010 INFO L306 stractBuchiCegarLoop]: Backedges is STRAIGHT_LINE [2023-11-12 02:03:56,010 INFO L307 stractBuchiCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2023-11-12 02:03:56,010 INFO L308 stractBuchiCegarLoop]: Difference is false [2023-11-12 02:03:56,010 INFO L309 stractBuchiCegarLoop]: Minimize is MINIMIZE_SEVPA [2023-11-12 02:03:56,011 INFO L313 stractBuchiCegarLoop]: ======== Iteration 0 == of CEGAR loop == BuchiAutomatonCegarLoop ======== [2023-11-12 02:03:56,023 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 1811 states, 1810 states have (on average 1.4950276243093923) internal successors, (2706), 1810 states have internal predecessors, (2706), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-12 02:03:56,114 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1644 [2023-11-12 02:03:56,114 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-12 02:03:56,114 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-12 02:03:56,131 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-12 02:03:56,131 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-12 02:03:56,132 INFO L335 stractBuchiCegarLoop]: ======== Iteration 1 ============ [2023-11-12 02:03:56,136 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 1811 states, 1810 states have (on average 1.4950276243093923) internal successors, (2706), 1810 states have internal predecessors, (2706), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-12 02:03:56,200 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1644 [2023-11-12 02:03:56,200 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-12 02:03:56,201 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-12 02:03:56,207 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-12 02:03:56,207 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-12 02:03:56,234 INFO L748 eck$LassoCheckResult]: Stem: 135#$Ultimate##0true assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(20, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~token~0 := 0;~local~0 := 0; 1716#L-1true assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~14#1;havoc main_~__retres1~14#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1; 657#init_model_returnLabel#1true assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret34#1, start_simulation_#t~ret35#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 1711#update_channels_returnLabel#1true assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 1369#L848true assume !(1 == ~m_i~0);~m_st~0 := 2; 1480#L848-2true assume 1 == ~t1_i~0;~t1_st~0 := 0; 436#L853-1true assume !(1 == ~t2_i~0);~t2_st~0 := 2; 308#L858-1true assume !(1 == ~t3_i~0);~t3_st~0 := 2; 2#L863-1true assume !(1 == ~t4_i~0);~t4_st~0 := 2; 753#L868-1true assume !(1 == ~t5_i~0);~t5_st~0 := 2; 842#L873-1true assume !(1 == ~t6_i~0);~t6_st~0 := 2; 1612#L878-1true assume !(1 == ~t7_i~0);~t7_st~0 := 2; 1578#L883-1true assume !(1 == ~t8_i~0);~t8_st~0 := 2; 1663#L888-1true assume 1 == ~t9_i~0;~t9_st~0 := 0; 387#L893-1true assume !(1 == ~t10_i~0);~t10_st~0 := 2; 776#L898-1true assume !(1 == ~t11_i~0);~t11_st~0 := 2; 1788#L903-1true assume !(1 == ~t12_i~0);~t12_st~0 := 2; 703#L908-1true assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 411#L1201true assume !(0 == ~M_E~0); 1189#L1201-2true assume 0 == ~T1_E~0;~T1_E~0 := 1; 1609#L1206-1true assume !(0 == ~T2_E~0); 1161#L1211-1true assume !(0 == ~T3_E~0); 1311#L1216-1true assume !(0 == ~T4_E~0); 296#L1221-1true assume !(0 == ~T5_E~0); 1253#L1226-1true assume !(0 == ~T6_E~0); 99#L1231-1true assume !(0 == ~T7_E~0); 1392#L1236-1true assume !(0 == ~T8_E~0); 1234#L1241-1true assume 0 == ~T9_E~0;~T9_E~0 := 1; 321#L1246-1true assume !(0 == ~T10_E~0); 409#L1251-1true assume !(0 == ~T11_E~0); 876#L1256-1true assume !(0 == ~T12_E~0); 6#L1261-1true assume !(0 == ~E_M~0); 1582#L1266-1true assume !(0 == ~E_1~0); 1521#L1271-1true assume !(0 == ~E_2~0); 830#L1276-1true assume !(0 == ~E_3~0); 1516#L1281-1true assume 0 == ~E_4~0;~E_4~0 := 1; 788#L1286-1true assume !(0 == ~E_5~0); 237#L1291-1true assume !(0 == ~E_6~0); 1607#L1296-1true assume !(0 == ~E_7~0); 614#L1301-1true assume !(0 == ~E_8~0); 1104#L1306-1true assume !(0 == ~E_9~0); 1078#L1311-1true assume !(0 == ~E_10~0); 212#L1316-1true assume !(0 == ~E_11~0); 1465#L1321-1true assume 0 == ~E_12~0;~E_12~0 := 1; 628#L1326-1true assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 745#L593true assume 1 == ~m_pc~0; 862#L594true assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 1479#L604true is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 545#is_master_triggered_returnLabel#1true activate_threads_#t~ret20#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 796#L1492true assume !(0 != activate_threads_~tmp~1#1); 1236#L1492-2true assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1127#L612true assume !(1 == ~t1_pc~0); 1671#L612-2true is_transmit1_triggered_~__retres1~1#1 := 0; 1547#L623true is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 925#is_transmit1_triggered_returnLabel#1true activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 149#L1500true assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 443#L1500-2true assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 395#L631true assume 1 == ~t2_pc~0; 353#L632true assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 41#L642true is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 219#is_transmit2_triggered_returnLabel#1true activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 523#L1508true assume !(0 != activate_threads_~tmp___1~0#1); 1317#L1508-2true assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 188#L650true assume !(1 == ~t3_pc~0); 962#L650-2true is_transmit3_triggered_~__retres1~3#1 := 0; 1226#L661true is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 903#is_transmit3_triggered_returnLabel#1true activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 22#L1516true assume !(0 != activate_threads_~tmp___2~0#1); 972#L1516-2true assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 772#L669true assume 1 == ~t4_pc~0; 1279#L670true assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 1797#L680true is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 60#is_transmit4_triggered_returnLabel#1true activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 115#L1524true assume !(0 != activate_threads_~tmp___3~0#1); 244#L1524-2true assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 988#L688true assume !(1 == ~t5_pc~0); 125#L688-2true is_transmit5_triggered_~__retres1~5#1 := 0; 1478#L699true is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1453#is_transmit5_triggered_returnLabel#1true activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 671#L1532true assume !(0 != activate_threads_~tmp___4~0#1); 782#L1532-2true assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1301#L707true assume 1 == ~t6_pc~0; 1349#L708true assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 502#L718true is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 213#is_transmit6_triggered_returnLabel#1true activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 1375#L1540true assume !(0 != activate_threads_~tmp___5~0#1); 732#L1540-2true assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 410#L726true assume 1 == ~t7_pc~0; 346#L727true assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 915#L737true is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1734#is_transmit7_triggered_returnLabel#1true activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 1312#L1548true assume !(0 != activate_threads_~tmp___6~0#1); 56#L1548-2true assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 293#L745true assume !(1 == ~t8_pc~0); 1114#L745-2true is_transmit8_triggered_~__retres1~8#1 := 0; 1201#L756true is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 1396#is_transmit8_triggered_returnLabel#1true activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 550#L1556true assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 1025#L1556-2true assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 1802#L764true assume 1 == ~t9_pc~0; 407#L765true assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 799#L775true is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 255#is_transmit9_triggered_returnLabel#1true activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 1439#L1564true assume !(0 != activate_threads_~tmp___8~0#1); 68#L1564-2true assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 1394#L783true assume !(1 == ~t10_pc~0); 93#L783-2true is_transmit10_triggered_~__retres1~10#1 := 0; 191#L794true is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 1217#is_transmit10_triggered_returnLabel#1true activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 382#L1572true assume !(0 != activate_threads_~tmp___9~0#1); 1177#L1572-2true assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 1282#L802true assume 1 == ~t11_pc~0; 1148#L803true assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 39#L813true is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 1310#is_transmit11_triggered_returnLabel#1true activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 297#L1580true assume !(0 != activate_threads_~tmp___10~0#1); 365#L1580-2true assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 533#L821true assume !(1 == ~t12_pc~0); 605#L821-2true is_transmit12_triggered_~__retres1~12#1 := 0; 1339#L832true is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 43#is_transmit12_triggered_returnLabel#1true activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 1252#L1588true assume !(0 != activate_threads_~tmp___11~0#1); 1257#L1588-2true havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 805#L1339true assume !(1 == ~M_E~0); 1462#L1339-2true assume !(1 == ~T1_E~0); 1322#L1344-1true assume 1 == ~T2_E~0;~T2_E~0 := 2; 1736#L1349-1true assume !(1 == ~T3_E~0); 624#L1354-1true assume !(1 == ~T4_E~0); 995#L1359-1true assume !(1 == ~T5_E~0); 1557#L1364-1true assume !(1 == ~T6_E~0); 272#L1369-1true assume !(1 == ~T7_E~0); 965#L1374-1true assume !(1 == ~T8_E~0); 626#L1379-1true assume !(1 == ~T9_E~0); 700#L1384-1true assume 1 == ~T10_E~0;~T10_E~0 := 2; 1776#L1389-1true assume !(1 == ~T11_E~0); 1241#L1394-1true assume !(1 == ~T12_E~0); 1638#L1399-1true assume !(1 == ~E_M~0); 1442#L1404-1true assume !(1 == ~E_1~0); 324#L1409-1true assume !(1 == ~E_2~0); 1410#L1414-1true assume !(1 == ~E_3~0); 863#L1419-1true assume !(1 == ~E_4~0); 120#L1424-1true assume 1 == ~E_5~0;~E_5~0 := 2; 632#L1429-1true assume !(1 == ~E_6~0); 1269#L1434-1true assume !(1 == ~E_7~0); 1614#L1439-1true assume !(1 == ~E_8~0); 142#L1444-1true assume !(1 == ~E_9~0); 818#L1449-1true assume !(1 == ~E_10~0); 357#L1454-1true assume !(1 == ~E_11~0); 1309#L1459-1true assume !(1 == ~E_12~0); 730#L1464-1true assume { :end_inline_reset_delta_events } true; 492#L1810-2true [2023-11-12 02:03:56,238 INFO L750 eck$LassoCheckResult]: Loop: 492#L1810-2true assume !false; 1346#L1811true start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 877#L1176-1true assume false; 496#eval_returnLabel#1true havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 325#update_channels_returnLabel#2true assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 1058#L1201-3true assume 0 == ~M_E~0;~M_E~0 := 1; 822#L1201-5true assume 0 == ~T1_E~0;~T1_E~0 := 1; 1611#L1206-3true assume 0 == ~T2_E~0;~T2_E~0 := 1; 728#L1211-3true assume 0 == ~T3_E~0;~T3_E~0 := 1; 186#L1216-3true assume !(0 == ~T4_E~0); 470#L1221-3true assume 0 == ~T5_E~0;~T5_E~0 := 1; 1023#L1226-3true assume 0 == ~T6_E~0;~T6_E~0 := 1; 230#L1231-3true assume 0 == ~T7_E~0;~T7_E~0 := 1; 373#L1236-3true assume 0 == ~T8_E~0;~T8_E~0 := 1; 1786#L1241-3true assume 0 == ~T9_E~0;~T9_E~0 := 1; 1345#L1246-3true assume 0 == ~T10_E~0;~T10_E~0 := 1; 1152#L1251-3true assume 0 == ~T11_E~0;~T11_E~0 := 1; 807#L1256-3true assume !(0 == ~T12_E~0); 196#L1261-3true assume 0 == ~E_M~0;~E_M~0 := 1; 517#L1266-3true assume 0 == ~E_1~0;~E_1~0 := 1; 226#L1271-3true assume 0 == ~E_2~0;~E_2~0 := 1; 490#L1276-3true assume 0 == ~E_3~0;~E_3~0 := 1; 456#L1281-3true assume 0 == ~E_4~0;~E_4~0 := 1; 1211#L1286-3true assume 0 == ~E_5~0;~E_5~0 := 1; 860#L1291-3true assume 0 == ~E_6~0;~E_6~0 := 1; 1624#L1296-3true assume !(0 == ~E_7~0); 1548#L1301-3true assume 0 == ~E_8~0;~E_8~0 := 1; 1429#L1306-3true assume 0 == ~E_9~0;~E_9~0 := 1; 528#L1311-3true assume 0 == ~E_10~0;~E_10~0 := 1; 154#L1316-3true assume 0 == ~E_11~0;~E_11~0 := 1; 197#L1321-3true assume 0 == ~E_12~0;~E_12~0 := 1; 604#L1326-3true assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1221#L593-42true assume !(1 == ~m_pc~0); 734#L593-44true is_master_triggered_~__retres1~0#1 := 0; 1771#L604-14true is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 388#is_master_triggered_returnLabel#15true activate_threads_#t~ret20#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1733#L1492-42true assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 102#L1492-44true assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 690#L612-42true assume !(1 == ~t1_pc~0); 1099#L612-44true is_transmit1_triggered_~__retres1~1#1 := 0; 1595#L623-14true is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1625#is_transmit1_triggered_returnLabel#15true activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 148#L1500-42true assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 1767#L1500-44true assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 577#L631-42true assume 1 == ~t2_pc~0; 34#L632-14true assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 566#L642-14true is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 570#is_transmit2_triggered_returnLabel#15true activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 489#L1508-42true assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 1645#L1508-44true assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 239#L650-42true assume !(1 == ~t3_pc~0); 130#L650-44true is_transmit3_triggered_~__retres1~3#1 := 0; 1729#L661-14true is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 890#is_transmit3_triggered_returnLabel#15true activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 352#L1516-42true assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 1379#L1516-44true assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1278#L669-42true assume !(1 == ~t4_pc~0); 18#L669-44true is_transmit4_triggered_~__retres1~4#1 := 0; 1000#L680-14true is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 974#is_transmit4_triggered_returnLabel#15true activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 872#L1524-42true assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 781#L1524-44true assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 859#L688-42true assume !(1 == ~t5_pc~0); 1106#L688-44true is_transmit5_triggered_~__retres1~5#1 := 0; 1358#L699-14true is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 617#is_transmit5_triggered_returnLabel#15true activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 114#L1532-42true assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 1436#L1532-44true assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 31#L707-42true assume 1 == ~t6_pc~0; 1447#L708-14true assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 1705#L718-14true is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 193#is_transmit6_triggered_returnLabel#15true activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 1300#L1540-42true assume !(0 != activate_threads_~tmp___5~0#1); 756#L1540-44true assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1033#L726-42true assume !(1 == ~t7_pc~0); 1801#L726-44true is_transmit7_triggered_~__retres1~7#1 := 0; 1075#L737-14true is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 634#is_transmit7_triggered_returnLabel#15true activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 531#L1548-42true assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 608#L1548-44true assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 1197#L745-42true assume 1 == ~t8_pc~0; 638#L746-14true assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 1433#L756-14true is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 773#is_transmit8_triggered_returnLabel#15true activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 26#L1556-42true assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 428#L1556-44true assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 514#L764-42true assume !(1 == ~t9_pc~0); 1297#L764-44true is_transmit9_triggered_~__retres1~9#1 := 0; 794#L775-14true is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 1651#is_transmit9_triggered_returnLabel#15true activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 161#L1564-42true assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 192#L1564-44true assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 243#L783-42true assume 1 == ~t10_pc~0; 7#L784-14true assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 316#L794-14true is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 768#is_transmit10_triggered_returnLabel#15true activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 1550#L1572-42true assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 1528#L1572-44true assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 959#L802-42true assume 1 == ~t11_pc~0; 276#L803-14true assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 71#L813-14true is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 1366#is_transmit11_triggered_returnLabel#15true activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 46#L1580-42true assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 1565#L1580-44true assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 803#L821-42true assume 1 == ~t12_pc~0; 1703#L822-14true assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 1010#L832-14true is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 602#is_transmit12_triggered_returnLabel#15true activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 1165#L1588-42true assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 557#L1588-44true havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 549#L1339-3true assume 1 == ~M_E~0;~M_E~0 := 2; 673#L1339-5true assume 1 == ~T1_E~0;~T1_E~0 := 2; 810#L1344-3true assume 1 == ~T2_E~0;~T2_E~0 := 2; 771#L1349-3true assume 1 == ~T3_E~0;~T3_E~0 := 2; 344#L1354-3true assume 1 == ~T4_E~0;~T4_E~0 := 2; 778#L1359-3true assume !(1 == ~T5_E~0); 1620#L1364-3true assume 1 == ~T6_E~0;~T6_E~0 := 2; 1512#L1369-3true assume 1 == ~T7_E~0;~T7_E~0 := 2; 1267#L1374-3true assume 1 == ~T8_E~0;~T8_E~0 := 2; 241#L1379-3true assume 1 == ~T9_E~0;~T9_E~0 := 2; 1156#L1384-3true assume 1 == ~T10_E~0;~T10_E~0 := 2; 343#L1389-3true assume 1 == ~T11_E~0;~T11_E~0 := 2; 482#L1394-3true assume 1 == ~T12_E~0;~T12_E~0 := 2; 1719#L1399-3true assume !(1 == ~E_M~0); 1288#L1404-3true assume 1 == ~E_1~0;~E_1~0 := 2; 1233#L1409-3true assume 1 == ~E_2~0;~E_2~0 := 2; 1344#L1414-3true assume 1 == ~E_3~0;~E_3~0 := 2; 1363#L1419-3true assume 1 == ~E_4~0;~E_4~0 := 2; 963#L1424-3true assume 1 == ~E_5~0;~E_5~0 := 2; 171#L1429-3true assume 1 == ~E_6~0;~E_6~0 := 2; 777#L1434-3true assume 1 == ~E_7~0;~E_7~0 := 2; 930#L1439-3true assume !(1 == ~E_8~0); 136#L1444-3true assume 1 == ~E_9~0;~E_9~0 := 2; 201#L1449-3true assume 1 == ~E_10~0;~E_10~0 := 2; 1428#L1454-3true assume 1 == ~E_11~0;~E_11~0 := 2; 774#L1459-3true assume 1 == ~E_12~0;~E_12~0 := 2; 1785#L1464-3true assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 503#L921-1true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 1740#L988-1true exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 189#exists_runnable_thread_returnLabel#2true start_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; 1464#L1829true assume !(0 == start_simulation_~tmp~3#1); 82#L1829-2true assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 1040#L921-2true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 552#L988-2true exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 36#exists_runnable_thread_returnLabel#3true stop_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret33#1;havoc stop_simulation_#t~ret33#1; 789#L1784true assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 1559#L1791true stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 1239#stop_simulation_returnLabel#1true start_simulation_#t~ret35#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 218#L1842true assume !(0 != start_simulation_~tmp___0~1#1); 492#L1810-2true [2023-11-12 02:03:56,245 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-12 02:03:56,246 INFO L85 PathProgramCache]: Analyzing trace with hash -1818030166, now seen corresponding path program 1 times [2023-11-12 02:03:56,267 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-12 02:03:56,268 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2095986906] [2023-11-12 02:03:56,268 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-12 02:03:56,269 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-12 02:03:56,487 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-12 02:03:56,706 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-12 02:03:56,706 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-12 02:03:56,707 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2095986906] [2023-11-12 02:03:56,707 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2095986906] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-12 02:03:56,707 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-12 02:03:56,708 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-12 02:03:56,709 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1660489360] [2023-11-12 02:03:56,710 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-12 02:03:56,714 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-12 02:03:56,715 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-12 02:03:56,715 INFO L85 PathProgramCache]: Analyzing trace with hash 1251295423, now seen corresponding path program 1 times [2023-11-12 02:03:56,716 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-12 02:03:56,716 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [106843211] [2023-11-12 02:03:56,716 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-12 02:03:56,716 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-12 02:03:56,737 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-12 02:03:56,832 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-12 02:03:56,832 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-12 02:03:56,833 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [106843211] [2023-11-12 02:03:56,833 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [106843211] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-12 02:03:56,833 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-12 02:03:56,833 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2023-11-12 02:03:56,834 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1648471817] [2023-11-12 02:03:56,834 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-12 02:03:56,835 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-12 02:03:56,836 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-12 02:03:56,877 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 2 interpolants. [2023-11-12 02:03:56,877 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=1, Invalid=1, Unknown=0, NotChecked=0, Total=2 [2023-11-12 02:03:56,881 INFO L87 Difference]: Start difference. First operand has 1811 states, 1810 states have (on average 1.4950276243093923) internal successors, (2706), 1810 states have internal predecessors, (2706), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand has 2 states, 2 states have (on average 74.5) internal successors, (149), 2 states have internal predecessors, (149), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-12 02:03:56,964 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-12 02:03:56,964 INFO L93 Difference]: Finished difference Result 1807 states and 2670 transitions. [2023-11-12 02:03:56,966 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1807 states and 2670 transitions. [2023-11-12 02:03:56,985 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1638 [2023-11-12 02:03:57,005 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1807 states to 1801 states and 2664 transitions. [2023-11-12 02:03:57,007 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1801 [2023-11-12 02:03:57,009 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1801 [2023-11-12 02:03:57,010 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1801 states and 2664 transitions. [2023-11-12 02:03:57,018 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-12 02:03:57,018 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1801 states and 2664 transitions. [2023-11-12 02:03:57,040 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1801 states and 2664 transitions. [2023-11-12 02:03:57,118 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1801 to 1801. [2023-11-12 02:03:57,125 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1801 states, 1801 states have (on average 1.4791782343142699) internal successors, (2664), 1800 states have internal predecessors, (2664), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-12 02:03:57,133 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1801 states to 1801 states and 2664 transitions. [2023-11-12 02:03:57,135 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1801 states and 2664 transitions. [2023-11-12 02:03:57,136 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 2 states. [2023-11-12 02:03:57,141 INFO L428 stractBuchiCegarLoop]: Abstraction has 1801 states and 2664 transitions. [2023-11-12 02:03:57,142 INFO L335 stractBuchiCegarLoop]: ======== Iteration 2 ============ [2023-11-12 02:03:57,142 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1801 states and 2664 transitions. [2023-11-12 02:03:57,155 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1638 [2023-11-12 02:03:57,156 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-12 02:03:57,156 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-12 02:03:57,164 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-12 02:03:57,164 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-12 02:03:57,166 INFO L748 eck$LassoCheckResult]: Stem: 3915#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(20, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~token~0 := 0;~local~0 := 0; 3916#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~14#1;havoc main_~__retres1~14#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1; 4760#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret34#1, start_simulation_#t~ret35#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 4761#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 5347#L848 assume !(1 == ~m_i~0);~m_st~0 := 2; 5348#L848-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 4441#L853-1 assume !(1 == ~t2_i~0);~t2_st~0 := 2; 4230#L858-1 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 3627#L863-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 3628#L868-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 4872#L873-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 4971#L878-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 5409#L883-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 5410#L888-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 4366#L893-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 4367#L898-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 4898#L903-1 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 4823#L908-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 4403#L1201 assume !(0 == ~M_E~0); 4404#L1201-2 assume 0 == ~T1_E~0;~T1_E~0 := 1; 5256#L1206-1 assume !(0 == ~T2_E~0); 5239#L1211-1 assume !(0 == ~T3_E~0); 5240#L1216-1 assume !(0 == ~T4_E~0); 4211#L1221-1 assume !(0 == ~T5_E~0); 4212#L1226-1 assume !(0 == ~T6_E~0); 3841#L1231-1 assume !(0 == ~T7_E~0); 3842#L1236-1 assume !(0 == ~T8_E~0); 5280#L1241-1 assume 0 == ~T9_E~0;~T9_E~0 := 1; 4251#L1246-1 assume !(0 == ~T10_E~0); 4252#L1251-1 assume !(0 == ~T11_E~0); 4401#L1256-1 assume !(0 == ~T12_E~0); 3636#L1261-1 assume !(0 == ~E_M~0); 3637#L1266-1 assume !(0 == ~E_1~0); 5394#L1271-1 assume !(0 == ~E_2~0); 4955#L1276-1 assume !(0 == ~E_3~0); 4956#L1281-1 assume 0 == ~E_4~0;~E_4~0 := 1; 4910#L1286-1 assume !(0 == ~E_5~0); 4107#L1291-1 assume !(0 == ~E_6~0); 4108#L1296-1 assume !(0 == ~E_7~0); 4696#L1301-1 assume !(0 == ~E_8~0); 4697#L1306-1 assume !(0 == ~E_9~0); 5175#L1311-1 assume !(0 == ~E_10~0); 4058#L1316-1 assume !(0 == ~E_11~0); 4059#L1321-1 assume 0 == ~E_12~0;~E_12~0 := 1; 4715#L1326-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 4716#L593 assume 1 == ~m_pc~0; 4865#L594 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 3940#L604 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 4604#is_master_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 4605#L1492 assume !(0 != activate_threads_~tmp~1#1); 4920#L1492-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 5208#L612 assume !(1 == ~t1_pc~0); 5209#L612-2 is_transmit1_triggered_~__retres1~1#1 := 0; 5343#L623 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 5053#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 3943#L1500 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 3944#L1500-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 4382#L631 assume 1 == ~t2_pc~0; 4309#L632 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 3717#L642 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 3718#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 4072#L1508 assume !(0 != activate_threads_~tmp___1~0#1); 4568#L1508-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 4019#L650 assume !(1 == ~t3_pc~0); 4020#L650-2 is_transmit3_triggered_~__retres1~3#1 := 0; 4738#L661 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 5032#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 3674#L1516 assume !(0 != activate_threads_~tmp___2~0#1); 3675#L1516-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 4891#L669 assume 1 == ~t4_pc~0; 4892#L670 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 5247#L680 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 3757#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 3758#L1524 assume !(0 != activate_threads_~tmp___3~0#1); 3878#L1524-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 4117#L688 assume !(1 == ~t5_pc~0); 3897#L688-2 is_transmit5_triggered_~__retres1~5#1 := 0; 3898#L699 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 5375#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 4780#L1532 assume !(0 != activate_threads_~tmp___4~0#1); 4781#L1532-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 4905#L707 assume 1 == ~t6_pc~0; 5314#L708 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 4537#L718 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 4060#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 4061#L1540 assume !(0 != activate_threads_~tmp___5~0#1); 4851#L1540-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 4402#L726 assume 1 == ~t7_pc~0; 4297#L727 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 3984#L737 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 5044#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 5318#L1548 assume !(0 != activate_threads_~tmp___6~0#1); 3747#L1548-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 3748#L745 assume !(1 == ~t8_pc~0); 4204#L745-2 is_transmit8_triggered_~__retres1~8#1 := 0; 4224#L756 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 5262#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 4613#L1556 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 4614#L1556-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 5132#L764 assume 1 == ~t9_pc~0; 4400#L765 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 4234#L775 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 4133#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 4134#L1564 assume !(0 != activate_threads_~tmp___8~0#1); 3773#L1564-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 3774#L783 assume !(1 == ~t10_pc~0); 3828#L783-2 is_transmit10_triggered_~__retres1~10#1 := 0; 3829#L794 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 4026#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 4356#L1572 assume !(0 != activate_threads_~tmp___9~0#1); 4357#L1572-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 5249#L802 assume 1 == ~t11_pc~0; 5231#L803 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 3714#L813 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 3715#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 4213#L1580 assume !(0 != activate_threads_~tmp___10~0#1); 4214#L1580-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 4331#L821 assume !(1 == ~t12_pc~0); 4582#L821-2 is_transmit12_triggered_~__retres1~12#1 := 0; 4688#L832 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 3721#is_transmit12_triggered_returnLabel#1 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 3722#L1588 assume !(0 != activate_threads_~tmp___11~0#1); 5291#L1588-2 havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 4928#L1339 assume !(1 == ~M_E~0); 4929#L1339-2 assume !(1 == ~T1_E~0); 5321#L1344-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 5322#L1349-1 assume !(1 == ~T3_E~0); 4708#L1354-1 assume !(1 == ~T4_E~0); 4709#L1359-1 assume !(1 == ~T5_E~0); 5108#L1364-1 assume !(1 == ~T6_E~0); 4165#L1369-1 assume !(1 == ~T7_E~0); 4166#L1374-1 assume !(1 == ~T8_E~0); 4711#L1379-1 assume !(1 == ~T9_E~0); 4712#L1384-1 assume 1 == ~T10_E~0;~T10_E~0 := 2; 4820#L1389-1 assume !(1 == ~T11_E~0); 5285#L1394-1 assume !(1 == ~T12_E~0); 5286#L1399-1 assume !(1 == ~E_M~0); 5367#L1404-1 assume !(1 == ~E_1~0); 4258#L1409-1 assume !(1 == ~E_2~0); 4259#L1414-1 assume !(1 == ~E_3~0); 4991#L1419-1 assume !(1 == ~E_4~0); 3887#L1424-1 assume 1 == ~E_5~0;~E_5~0 := 2; 3888#L1429-1 assume !(1 == ~E_6~0); 4723#L1434-1 assume !(1 == ~E_7~0); 5303#L1439-1 assume !(1 == ~E_8~0); 3929#L1444-1 assume !(1 == ~E_9~0); 3930#L1449-1 assume !(1 == ~E_10~0); 4315#L1454-1 assume !(1 == ~E_11~0); 4316#L1459-1 assume !(1 == ~E_12~0); 4850#L1464-1 assume { :end_inline_reset_delta_events } true; 4071#L1810-2 [2023-11-12 02:03:57,169 INFO L750 eck$LassoCheckResult]: Loop: 4071#L1810-2 assume !false; 4521#L1811 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 4619#L1176-1 assume !false; 5001#L999 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 4565#L921 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 3755#L988 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 5055#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 5226#L1003 assume !(0 != eval_~tmp~0#1); 4528#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 4260#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 4261#L1201-3 assume 0 == ~M_E~0;~M_E~0 := 1; 4945#L1201-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 4946#L1206-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 4848#L1211-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 4014#L1216-3 assume !(0 == ~T4_E~0); 4015#L1221-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 4493#L1226-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 4093#L1231-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 4094#L1236-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 4345#L1241-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 5334#L1246-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 5234#L1251-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 4933#L1256-3 assume !(0 == ~T12_E~0); 4034#L1261-3 assume 0 == ~E_M~0;~E_M~0 := 1; 4035#L1266-3 assume 0 == ~E_1~0;~E_1~0 := 1; 4085#L1271-3 assume 0 == ~E_2~0;~E_2~0 := 1; 4086#L1276-3 assume 0 == ~E_3~0;~E_3~0 := 1; 4469#L1281-3 assume 0 == ~E_4~0;~E_4~0 := 1; 4470#L1286-3 assume 0 == ~E_5~0;~E_5~0 := 1; 4988#L1291-3 assume 0 == ~E_6~0;~E_6~0 := 1; 4989#L1296-3 assume !(0 == ~E_7~0); 5406#L1301-3 assume 0 == ~E_8~0;~E_8~0 := 1; 5364#L1306-3 assume 0 == ~E_9~0;~E_9~0 := 1; 4573#L1311-3 assume 0 == ~E_10~0;~E_10~0 := 1; 3954#L1316-3 assume 0 == ~E_11~0;~E_11~0 := 1; 3955#L1321-3 assume 0 == ~E_12~0;~E_12~0 := 1; 4036#L1326-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 4687#L593-42 assume 1 == ~m_pc~0; 5074#L594-14 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 4853#L604-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 4368#is_master_triggered_returnLabel#15 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 4369#L1492-42 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 3848#L1492-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 3849#L612-42 assume !(1 == ~t1_pc~0); 4807#L612-44 is_transmit1_triggered_~__retres1~1#1 := 0; 5188#L623-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 5415#is_transmit1_triggered_returnLabel#15 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 3941#L1500-42 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 3942#L1500-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 4650#L631-42 assume 1 == ~t2_pc~0; 3701#L632-14 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 3702#L642-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 4635#is_transmit2_triggered_returnLabel#15 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 4519#L1508-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 4520#L1508-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 4112#L650-42 assume 1 == ~t3_pc~0; 3666#L651-14 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 3667#L661-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 5021#is_transmit3_triggered_returnLabel#15 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 4307#L1516-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 4308#L1516-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 5305#L669-42 assume !(1 == ~t4_pc~0); 3664#L669-44 is_transmit4_triggered_~__retres1~4#1 := 0; 3665#L680-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 5090#is_transmit4_triggered_returnLabel#15 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 4999#L1524-42 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 4903#L1524-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 4904#L688-42 assume 1 == ~t5_pc~0; 4986#L689-14 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 5191#L699-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 4699#is_transmit5_triggered_returnLabel#15 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 3876#L1532-42 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 3877#L1532-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 3694#L707-42 assume 1 == ~t6_pc~0; 3696#L708-14 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 5370#L718-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 4028#is_transmit6_triggered_returnLabel#15 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 4029#L1540-42 assume !(0 != activate_threads_~tmp___5~0#1); 4874#L1540-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 4875#L726-42 assume 1 == ~t7_pc~0; 5141#L727-14 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 5172#L737-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 4726#is_transmit7_triggered_returnLabel#15 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 4577#L1548-42 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 4578#L1548-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 4691#L745-42 assume 1 == ~t8_pc~0; 4729#L746-14 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 4731#L756-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 4894#is_transmit8_triggered_returnLabel#15 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 3682#L1556-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 3683#L1556-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 4428#L764-42 assume 1 == ~t9_pc~0; 4556#L765-14 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 4917#L775-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 4918#is_transmit9_triggered_returnLabel#15 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 3966#L1564-42 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 3967#L1564-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 4027#L783-42 assume 1 == ~t10_pc~0; 3638#L784-14 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 3639#L794-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 4243#is_transmit10_triggered_returnLabel#15 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 4886#L1572-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 5397#L1572-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 5080#L802-42 assume 1 == ~t11_pc~0; 4174#L803-14 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 3780#L813-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 3781#is_transmit11_triggered_returnLabel#15 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 3727#L1580-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 3728#L1580-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 4925#L821-42 assume !(1 == ~t12_pc~0); 4283#L821-44 is_transmit12_triggered_~__retres1~12#1 := 0; 4284#L832-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 4684#is_transmit12_triggered_returnLabel#15 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 4685#L1588-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 4621#L1588-44 havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 4611#L1339-3 assume 1 == ~M_E~0;~M_E~0 := 2; 4612#L1339-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 4784#L1344-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 4890#L1349-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 4293#L1354-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 4294#L1359-3 assume !(1 == ~T5_E~0); 4900#L1364-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 5391#L1369-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 5301#L1374-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 4114#L1379-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 4115#L1384-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 4291#L1389-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 4292#L1394-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 4507#L1399-3 assume !(1 == ~E_M~0); 5310#L1404-3 assume 1 == ~E_1~0;~E_1~0 := 2; 5278#L1409-3 assume 1 == ~E_2~0;~E_2~0 := 2; 5279#L1414-3 assume 1 == ~E_3~0;~E_3~0 := 2; 5333#L1419-3 assume 1 == ~E_4~0;~E_4~0 := 2; 5083#L1424-3 assume 1 == ~E_5~0;~E_5~0 := 2; 3988#L1429-3 assume 1 == ~E_6~0;~E_6~0 := 2; 3989#L1434-3 assume 1 == ~E_7~0;~E_7~0 := 2; 4899#L1439-3 assume !(1 == ~E_8~0); 3917#L1444-3 assume 1 == ~E_9~0;~E_9~0 := 2; 3918#L1449-3 assume 1 == ~E_10~0;~E_10~0 := 2; 4039#L1454-3 assume 1 == ~E_11~0;~E_11~0 := 2; 4895#L1459-3 assume 1 == ~E_12~0;~E_12~0 := 2; 4896#L1464-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 4538#L921-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 3820#L988-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 4022#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; 4023#L1829 assume !(0 == start_simulation_~tmp~3#1); 3802#L1829-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 3803#L921-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 4617#L988-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 3707#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret33#1;havoc stop_simulation_#t~ret33#1; 3708#L1784 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 4911#L1791 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 5284#stop_simulation_returnLabel#1 start_simulation_#t~ret35#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 4070#L1842 assume !(0 != start_simulation_~tmp___0~1#1); 4071#L1810-2 [2023-11-12 02:03:57,174 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-12 02:03:57,175 INFO L85 PathProgramCache]: Analyzing trace with hash -1818030166, now seen corresponding path program 2 times [2023-11-12 02:03:57,175 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-12 02:03:57,176 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1949449080] [2023-11-12 02:03:57,176 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-12 02:03:57,176 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-12 02:03:57,212 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-12 02:03:57,321 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-12 02:03:57,322 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-12 02:03:57,322 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1949449080] [2023-11-12 02:03:57,322 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1949449080] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-12 02:03:57,323 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-12 02:03:57,323 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-12 02:03:57,323 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1095202600] [2023-11-12 02:03:57,323 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-12 02:03:57,324 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-12 02:03:57,325 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-12 02:03:57,325 INFO L85 PathProgramCache]: Analyzing trace with hash 1042690776, now seen corresponding path program 1 times [2023-11-12 02:03:57,325 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-12 02:03:57,326 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1194872305] [2023-11-12 02:03:57,326 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-12 02:03:57,326 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-12 02:03:57,364 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-12 02:03:57,491 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-12 02:03:57,495 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-12 02:03:57,495 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1194872305] [2023-11-12 02:03:57,495 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1194872305] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-12 02:03:57,496 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-12 02:03:57,496 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-12 02:03:57,496 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1961383318] [2023-11-12 02:03:57,496 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-12 02:03:57,497 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-12 02:03:57,500 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-12 02:03:57,501 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-12 02:03:57,501 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-12 02:03:57,501 INFO L87 Difference]: Start difference. First operand 1801 states and 2664 transitions. cyclomatic complexity: 864 Second operand has 3 states, 3 states have (on average 50.0) internal successors, (150), 3 states have internal predecessors, (150), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-12 02:03:57,564 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-12 02:03:57,564 INFO L93 Difference]: Finished difference Result 1801 states and 2663 transitions. [2023-11-12 02:03:57,565 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1801 states and 2663 transitions. [2023-11-12 02:03:57,579 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1638 [2023-11-12 02:03:57,595 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1801 states to 1801 states and 2663 transitions. [2023-11-12 02:03:57,596 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1801 [2023-11-12 02:03:57,598 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1801 [2023-11-12 02:03:57,599 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1801 states and 2663 transitions. [2023-11-12 02:03:57,602 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-12 02:03:57,602 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1801 states and 2663 transitions. [2023-11-12 02:03:57,605 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1801 states and 2663 transitions. [2023-11-12 02:03:57,627 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1801 to 1801. [2023-11-12 02:03:57,631 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1801 states, 1801 states have (on average 1.478622987229317) internal successors, (2663), 1800 states have internal predecessors, (2663), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-12 02:03:57,639 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1801 states to 1801 states and 2663 transitions. [2023-11-12 02:03:57,642 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1801 states and 2663 transitions. [2023-11-12 02:03:57,642 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-12 02:03:57,643 INFO L428 stractBuchiCegarLoop]: Abstraction has 1801 states and 2663 transitions. [2023-11-12 02:03:57,643 INFO L335 stractBuchiCegarLoop]: ======== Iteration 3 ============ [2023-11-12 02:03:57,643 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1801 states and 2663 transitions. [2023-11-12 02:03:57,694 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1638 [2023-11-12 02:03:57,694 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-12 02:03:57,694 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-12 02:03:57,698 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-12 02:03:57,698 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-12 02:03:57,698 INFO L748 eck$LassoCheckResult]: Stem: 7524#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(20, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~token~0 := 0;~local~0 := 0; 7525#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~14#1;havoc main_~__retres1~14#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1; 8369#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret34#1, start_simulation_#t~ret35#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 8370#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 8956#L848 assume 1 == ~m_i~0;~m_st~0 := 0; 8957#L848-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 8050#L853-1 assume !(1 == ~t2_i~0);~t2_st~0 := 2; 7839#L858-1 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 7236#L863-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 7237#L868-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 8481#L873-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 8580#L878-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 9018#L883-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 9019#L888-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 7975#L893-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 7976#L898-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 8507#L903-1 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 8432#L908-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 8012#L1201 assume !(0 == ~M_E~0); 8013#L1201-2 assume 0 == ~T1_E~0;~T1_E~0 := 1; 8865#L1206-1 assume !(0 == ~T2_E~0); 8848#L1211-1 assume !(0 == ~T3_E~0); 8849#L1216-1 assume !(0 == ~T4_E~0); 7820#L1221-1 assume !(0 == ~T5_E~0); 7821#L1226-1 assume !(0 == ~T6_E~0); 7450#L1231-1 assume !(0 == ~T7_E~0); 7451#L1236-1 assume !(0 == ~T8_E~0); 8889#L1241-1 assume 0 == ~T9_E~0;~T9_E~0 := 1; 7860#L1246-1 assume !(0 == ~T10_E~0); 7861#L1251-1 assume !(0 == ~T11_E~0); 8010#L1256-1 assume !(0 == ~T12_E~0); 7245#L1261-1 assume !(0 == ~E_M~0); 7246#L1266-1 assume !(0 == ~E_1~0); 9003#L1271-1 assume !(0 == ~E_2~0); 8564#L1276-1 assume !(0 == ~E_3~0); 8565#L1281-1 assume 0 == ~E_4~0;~E_4~0 := 1; 8519#L1286-1 assume !(0 == ~E_5~0); 7716#L1291-1 assume !(0 == ~E_6~0); 7717#L1296-1 assume !(0 == ~E_7~0); 8305#L1301-1 assume !(0 == ~E_8~0); 8306#L1306-1 assume !(0 == ~E_9~0); 8784#L1311-1 assume !(0 == ~E_10~0); 7667#L1316-1 assume !(0 == ~E_11~0); 7668#L1321-1 assume 0 == ~E_12~0;~E_12~0 := 1; 8324#L1326-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 8325#L593 assume 1 == ~m_pc~0; 8474#L594 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 7549#L604 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 8213#is_master_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 8214#L1492 assume !(0 != activate_threads_~tmp~1#1); 8529#L1492-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 8817#L612 assume !(1 == ~t1_pc~0); 8818#L612-2 is_transmit1_triggered_~__retres1~1#1 := 0; 8952#L623 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 8662#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 7552#L1500 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 7553#L1500-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 7991#L631 assume 1 == ~t2_pc~0; 7918#L632 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 7326#L642 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 7327#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 7681#L1508 assume !(0 != activate_threads_~tmp___1~0#1); 8177#L1508-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 7628#L650 assume !(1 == ~t3_pc~0); 7629#L650-2 is_transmit3_triggered_~__retres1~3#1 := 0; 8347#L661 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 8641#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 7283#L1516 assume !(0 != activate_threads_~tmp___2~0#1); 7284#L1516-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 8500#L669 assume 1 == ~t4_pc~0; 8501#L670 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 8856#L680 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 7366#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 7367#L1524 assume !(0 != activate_threads_~tmp___3~0#1); 7487#L1524-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 7726#L688 assume !(1 == ~t5_pc~0); 7506#L688-2 is_transmit5_triggered_~__retres1~5#1 := 0; 7507#L699 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 8984#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 8389#L1532 assume !(0 != activate_threads_~tmp___4~0#1); 8390#L1532-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 8514#L707 assume 1 == ~t6_pc~0; 8923#L708 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 8146#L718 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 7669#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 7670#L1540 assume !(0 != activate_threads_~tmp___5~0#1); 8460#L1540-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 8011#L726 assume 1 == ~t7_pc~0; 7906#L727 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 7593#L737 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 8653#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 8927#L1548 assume !(0 != activate_threads_~tmp___6~0#1); 7356#L1548-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 7357#L745 assume !(1 == ~t8_pc~0); 7813#L745-2 is_transmit8_triggered_~__retres1~8#1 := 0; 7833#L756 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 8871#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 8222#L1556 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 8223#L1556-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 8741#L764 assume 1 == ~t9_pc~0; 8009#L765 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 7843#L775 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 7742#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 7743#L1564 assume !(0 != activate_threads_~tmp___8~0#1); 7382#L1564-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 7383#L783 assume !(1 == ~t10_pc~0); 7437#L783-2 is_transmit10_triggered_~__retres1~10#1 := 0; 7438#L794 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 7635#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 7965#L1572 assume !(0 != activate_threads_~tmp___9~0#1); 7966#L1572-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 8858#L802 assume 1 == ~t11_pc~0; 8840#L803 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 7323#L813 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 7324#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 7822#L1580 assume !(0 != activate_threads_~tmp___10~0#1); 7823#L1580-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 7940#L821 assume !(1 == ~t12_pc~0); 8191#L821-2 is_transmit12_triggered_~__retres1~12#1 := 0; 8297#L832 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 7330#is_transmit12_triggered_returnLabel#1 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 7331#L1588 assume !(0 != activate_threads_~tmp___11~0#1); 8900#L1588-2 havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 8537#L1339 assume !(1 == ~M_E~0); 8538#L1339-2 assume !(1 == ~T1_E~0); 8930#L1344-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 8931#L1349-1 assume !(1 == ~T3_E~0); 8317#L1354-1 assume !(1 == ~T4_E~0); 8318#L1359-1 assume !(1 == ~T5_E~0); 8717#L1364-1 assume !(1 == ~T6_E~0); 7774#L1369-1 assume !(1 == ~T7_E~0); 7775#L1374-1 assume !(1 == ~T8_E~0); 8320#L1379-1 assume !(1 == ~T9_E~0); 8321#L1384-1 assume 1 == ~T10_E~0;~T10_E~0 := 2; 8429#L1389-1 assume !(1 == ~T11_E~0); 8894#L1394-1 assume !(1 == ~T12_E~0); 8895#L1399-1 assume !(1 == ~E_M~0); 8976#L1404-1 assume !(1 == ~E_1~0); 7867#L1409-1 assume !(1 == ~E_2~0); 7868#L1414-1 assume !(1 == ~E_3~0); 8600#L1419-1 assume !(1 == ~E_4~0); 7496#L1424-1 assume 1 == ~E_5~0;~E_5~0 := 2; 7497#L1429-1 assume !(1 == ~E_6~0); 8332#L1434-1 assume !(1 == ~E_7~0); 8912#L1439-1 assume !(1 == ~E_8~0); 7538#L1444-1 assume !(1 == ~E_9~0); 7539#L1449-1 assume !(1 == ~E_10~0); 7924#L1454-1 assume !(1 == ~E_11~0); 7925#L1459-1 assume !(1 == ~E_12~0); 8459#L1464-1 assume { :end_inline_reset_delta_events } true; 7680#L1810-2 [2023-11-12 02:03:57,699 INFO L750 eck$LassoCheckResult]: Loop: 7680#L1810-2 assume !false; 8130#L1811 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 8228#L1176-1 assume !false; 8610#L999 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 8174#L921 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 7364#L988 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 8664#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 8835#L1003 assume !(0 != eval_~tmp~0#1); 8137#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 7869#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 7870#L1201-3 assume 0 == ~M_E~0;~M_E~0 := 1; 8554#L1201-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 8555#L1206-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 8457#L1211-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 7623#L1216-3 assume !(0 == ~T4_E~0); 7624#L1221-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 8102#L1226-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 7702#L1231-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 7703#L1236-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 7954#L1241-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 8943#L1246-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 8843#L1251-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 8542#L1256-3 assume !(0 == ~T12_E~0); 7643#L1261-3 assume 0 == ~E_M~0;~E_M~0 := 1; 7644#L1266-3 assume 0 == ~E_1~0;~E_1~0 := 1; 7694#L1271-3 assume 0 == ~E_2~0;~E_2~0 := 1; 7695#L1276-3 assume 0 == ~E_3~0;~E_3~0 := 1; 8078#L1281-3 assume 0 == ~E_4~0;~E_4~0 := 1; 8079#L1286-3 assume 0 == ~E_5~0;~E_5~0 := 1; 8597#L1291-3 assume 0 == ~E_6~0;~E_6~0 := 1; 8598#L1296-3 assume !(0 == ~E_7~0); 9015#L1301-3 assume 0 == ~E_8~0;~E_8~0 := 1; 8973#L1306-3 assume 0 == ~E_9~0;~E_9~0 := 1; 8182#L1311-3 assume 0 == ~E_10~0;~E_10~0 := 1; 7563#L1316-3 assume 0 == ~E_11~0;~E_11~0 := 1; 7564#L1321-3 assume 0 == ~E_12~0;~E_12~0 := 1; 7645#L1326-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 8296#L593-42 assume 1 == ~m_pc~0; 8683#L594-14 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 8462#L604-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 7977#is_master_triggered_returnLabel#15 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 7978#L1492-42 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 7457#L1492-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 7458#L612-42 assume !(1 == ~t1_pc~0); 8416#L612-44 is_transmit1_triggered_~__retres1~1#1 := 0; 8797#L623-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 9024#is_transmit1_triggered_returnLabel#15 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 7550#L1500-42 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 7551#L1500-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 8259#L631-42 assume !(1 == ~t2_pc~0); 7312#L631-44 is_transmit2_triggered_~__retres1~2#1 := 0; 7311#L642-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 8244#is_transmit2_triggered_returnLabel#15 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 8128#L1508-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 8129#L1508-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 7721#L650-42 assume 1 == ~t3_pc~0; 7275#L651-14 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 7276#L661-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 8630#is_transmit3_triggered_returnLabel#15 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 7916#L1516-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 7917#L1516-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 8914#L669-42 assume 1 == ~t4_pc~0; 8196#L670-14 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 7274#L680-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 8699#is_transmit4_triggered_returnLabel#15 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 8608#L1524-42 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 8512#L1524-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 8513#L688-42 assume 1 == ~t5_pc~0; 8595#L689-14 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 8800#L699-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 8308#is_transmit5_triggered_returnLabel#15 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 7485#L1532-42 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 7486#L1532-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 7303#L707-42 assume !(1 == ~t6_pc~0); 7304#L707-44 is_transmit6_triggered_~__retres1~6#1 := 0; 8979#L718-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 7637#is_transmit6_triggered_returnLabel#15 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 7638#L1540-42 assume !(0 != activate_threads_~tmp___5~0#1); 8483#L1540-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 8484#L726-42 assume 1 == ~t7_pc~0; 8750#L727-14 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 8781#L737-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 8335#is_transmit7_triggered_returnLabel#15 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 8186#L1548-42 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 8187#L1548-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 8300#L745-42 assume 1 == ~t8_pc~0; 8338#L746-14 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 8340#L756-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 8503#is_transmit8_triggered_returnLabel#15 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 7291#L1556-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 7292#L1556-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 8037#L764-42 assume 1 == ~t9_pc~0; 8165#L765-14 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 8526#L775-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 8527#is_transmit9_triggered_returnLabel#15 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 7575#L1564-42 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 7576#L1564-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 7636#L783-42 assume !(1 == ~t10_pc~0); 7249#L783-44 is_transmit10_triggered_~__retres1~10#1 := 0; 7248#L794-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 7852#is_transmit10_triggered_returnLabel#15 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 8495#L1572-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 9006#L1572-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 8689#L802-42 assume 1 == ~t11_pc~0; 7783#L803-14 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 7389#L813-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 7390#is_transmit11_triggered_returnLabel#15 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 7336#L1580-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 7337#L1580-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 8534#L821-42 assume !(1 == ~t12_pc~0); 7892#L821-44 is_transmit12_triggered_~__retres1~12#1 := 0; 7893#L832-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 8293#is_transmit12_triggered_returnLabel#15 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 8294#L1588-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 8230#L1588-44 havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 8220#L1339-3 assume 1 == ~M_E~0;~M_E~0 := 2; 8221#L1339-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 8393#L1344-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 8499#L1349-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 7902#L1354-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 7903#L1359-3 assume !(1 == ~T5_E~0); 8509#L1364-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 9000#L1369-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 8910#L1374-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 7723#L1379-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 7724#L1384-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 7900#L1389-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 7901#L1394-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 8116#L1399-3 assume !(1 == ~E_M~0); 8919#L1404-3 assume 1 == ~E_1~0;~E_1~0 := 2; 8887#L1409-3 assume 1 == ~E_2~0;~E_2~0 := 2; 8888#L1414-3 assume 1 == ~E_3~0;~E_3~0 := 2; 8942#L1419-3 assume 1 == ~E_4~0;~E_4~0 := 2; 8692#L1424-3 assume 1 == ~E_5~0;~E_5~0 := 2; 7597#L1429-3 assume 1 == ~E_6~0;~E_6~0 := 2; 7598#L1434-3 assume 1 == ~E_7~0;~E_7~0 := 2; 8508#L1439-3 assume !(1 == ~E_8~0); 7526#L1444-3 assume 1 == ~E_9~0;~E_9~0 := 2; 7527#L1449-3 assume 1 == ~E_10~0;~E_10~0 := 2; 7648#L1454-3 assume 1 == ~E_11~0;~E_11~0 := 2; 8504#L1459-3 assume 1 == ~E_12~0;~E_12~0 := 2; 8505#L1464-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 8147#L921-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 7429#L988-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 7631#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; 7632#L1829 assume !(0 == start_simulation_~tmp~3#1); 7411#L1829-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 7412#L921-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 8226#L988-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 7316#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret33#1;havoc stop_simulation_#t~ret33#1; 7317#L1784 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 8520#L1791 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 8893#stop_simulation_returnLabel#1 start_simulation_#t~ret35#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 7679#L1842 assume !(0 != start_simulation_~tmp___0~1#1); 7680#L1810-2 [2023-11-12 02:03:57,699 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-12 02:03:57,699 INFO L85 PathProgramCache]: Analyzing trace with hash -494851220, now seen corresponding path program 1 times [2023-11-12 02:03:57,700 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-12 02:03:57,710 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1964391264] [2023-11-12 02:03:57,711 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-12 02:03:57,711 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-12 02:03:57,742 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-12 02:03:57,845 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-12 02:03:57,845 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-12 02:03:57,845 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1964391264] [2023-11-12 02:03:57,846 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1964391264] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-12 02:03:57,846 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-12 02:03:57,846 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-12 02:03:57,846 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1176539408] [2023-11-12 02:03:57,847 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-12 02:03:57,847 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-12 02:03:57,848 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-12 02:03:57,848 INFO L85 PathProgramCache]: Analyzing trace with hash 1913226970, now seen corresponding path program 1 times [2023-11-12 02:03:57,848 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-12 02:03:57,848 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [274189105] [2023-11-12 02:03:57,849 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-12 02:03:57,849 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-12 02:03:57,885 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-12 02:03:57,975 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-12 02:03:57,975 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-12 02:03:57,976 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [274189105] [2023-11-12 02:03:57,976 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [274189105] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-12 02:03:57,976 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-12 02:03:57,977 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-12 02:03:57,977 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [790911250] [2023-11-12 02:03:57,977 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-12 02:03:57,978 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-12 02:03:57,978 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-12 02:03:57,978 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-12 02:03:57,978 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-12 02:03:57,979 INFO L87 Difference]: Start difference. First operand 1801 states and 2663 transitions. cyclomatic complexity: 863 Second operand has 3 states, 3 states have (on average 50.0) internal successors, (150), 3 states have internal predecessors, (150), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-12 02:03:58,031 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-12 02:03:58,032 INFO L93 Difference]: Finished difference Result 1801 states and 2662 transitions. [2023-11-12 02:03:58,032 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1801 states and 2662 transitions. [2023-11-12 02:03:58,047 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1638 [2023-11-12 02:03:58,062 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1801 states to 1801 states and 2662 transitions. [2023-11-12 02:03:58,063 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1801 [2023-11-12 02:03:58,065 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1801 [2023-11-12 02:03:58,065 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1801 states and 2662 transitions. [2023-11-12 02:03:58,068 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-12 02:03:58,068 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1801 states and 2662 transitions. [2023-11-12 02:03:58,072 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1801 states and 2662 transitions. [2023-11-12 02:03:58,096 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1801 to 1801. [2023-11-12 02:03:58,100 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1801 states, 1801 states have (on average 1.4780677401443643) internal successors, (2662), 1800 states have internal predecessors, (2662), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-12 02:03:58,108 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1801 states to 1801 states and 2662 transitions. [2023-11-12 02:03:58,109 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1801 states and 2662 transitions. [2023-11-12 02:03:58,109 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-12 02:03:58,111 INFO L428 stractBuchiCegarLoop]: Abstraction has 1801 states and 2662 transitions. [2023-11-12 02:03:58,112 INFO L335 stractBuchiCegarLoop]: ======== Iteration 4 ============ [2023-11-12 02:03:58,112 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1801 states and 2662 transitions. [2023-11-12 02:03:58,122 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1638 [2023-11-12 02:03:58,123 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-12 02:03:58,123 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-12 02:03:58,126 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-12 02:03:58,127 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-12 02:03:58,127 INFO L748 eck$LassoCheckResult]: Stem: 11133#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(20, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~token~0 := 0;~local~0 := 0; 11134#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~14#1;havoc main_~__retres1~14#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1; 11978#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret34#1, start_simulation_#t~ret35#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 11979#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 12565#L848 assume 1 == ~m_i~0;~m_st~0 := 0; 12566#L848-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 11659#L853-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 11448#L858-1 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 10845#L863-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 10846#L868-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 12090#L873-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 12189#L878-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 12627#L883-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 12628#L888-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 11584#L893-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 11585#L898-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 12116#L903-1 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 12041#L908-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 11621#L1201 assume !(0 == ~M_E~0); 11622#L1201-2 assume 0 == ~T1_E~0;~T1_E~0 := 1; 12474#L1206-1 assume !(0 == ~T2_E~0); 12457#L1211-1 assume !(0 == ~T3_E~0); 12458#L1216-1 assume !(0 == ~T4_E~0); 11429#L1221-1 assume !(0 == ~T5_E~0); 11430#L1226-1 assume !(0 == ~T6_E~0); 11059#L1231-1 assume !(0 == ~T7_E~0); 11060#L1236-1 assume !(0 == ~T8_E~0); 12498#L1241-1 assume 0 == ~T9_E~0;~T9_E~0 := 1; 11469#L1246-1 assume !(0 == ~T10_E~0); 11470#L1251-1 assume !(0 == ~T11_E~0); 11619#L1256-1 assume !(0 == ~T12_E~0); 10854#L1261-1 assume !(0 == ~E_M~0); 10855#L1266-1 assume !(0 == ~E_1~0); 12612#L1271-1 assume !(0 == ~E_2~0); 12173#L1276-1 assume !(0 == ~E_3~0); 12174#L1281-1 assume 0 == ~E_4~0;~E_4~0 := 1; 12128#L1286-1 assume !(0 == ~E_5~0); 11325#L1291-1 assume !(0 == ~E_6~0); 11326#L1296-1 assume !(0 == ~E_7~0); 11914#L1301-1 assume !(0 == ~E_8~0); 11915#L1306-1 assume !(0 == ~E_9~0); 12393#L1311-1 assume !(0 == ~E_10~0); 11276#L1316-1 assume !(0 == ~E_11~0); 11277#L1321-1 assume 0 == ~E_12~0;~E_12~0 := 1; 11933#L1326-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 11934#L593 assume 1 == ~m_pc~0; 12083#L594 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 11158#L604 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 11822#is_master_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 11823#L1492 assume !(0 != activate_threads_~tmp~1#1); 12138#L1492-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 12426#L612 assume !(1 == ~t1_pc~0); 12427#L612-2 is_transmit1_triggered_~__retres1~1#1 := 0; 12561#L623 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 12271#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 11161#L1500 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 11162#L1500-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 11600#L631 assume 1 == ~t2_pc~0; 11527#L632 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 10935#L642 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 10936#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 11290#L1508 assume !(0 != activate_threads_~tmp___1~0#1); 11786#L1508-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 11237#L650 assume !(1 == ~t3_pc~0); 11238#L650-2 is_transmit3_triggered_~__retres1~3#1 := 0; 11956#L661 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 12250#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 10892#L1516 assume !(0 != activate_threads_~tmp___2~0#1); 10893#L1516-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 12109#L669 assume 1 == ~t4_pc~0; 12110#L670 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 12465#L680 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 10975#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 10976#L1524 assume !(0 != activate_threads_~tmp___3~0#1); 11096#L1524-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 11335#L688 assume !(1 == ~t5_pc~0); 11115#L688-2 is_transmit5_triggered_~__retres1~5#1 := 0; 11116#L699 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 12593#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 11998#L1532 assume !(0 != activate_threads_~tmp___4~0#1); 11999#L1532-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 12123#L707 assume 1 == ~t6_pc~0; 12532#L708 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 11755#L718 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 11278#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 11279#L1540 assume !(0 != activate_threads_~tmp___5~0#1); 12069#L1540-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 11620#L726 assume 1 == ~t7_pc~0; 11515#L727 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 11202#L737 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 12262#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 12536#L1548 assume !(0 != activate_threads_~tmp___6~0#1); 10965#L1548-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 10966#L745 assume !(1 == ~t8_pc~0); 11422#L745-2 is_transmit8_triggered_~__retres1~8#1 := 0; 11442#L756 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 12480#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 11831#L1556 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 11832#L1556-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 12350#L764 assume 1 == ~t9_pc~0; 11618#L765 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 11452#L775 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 11351#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 11352#L1564 assume !(0 != activate_threads_~tmp___8~0#1); 10991#L1564-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 10992#L783 assume !(1 == ~t10_pc~0); 11046#L783-2 is_transmit10_triggered_~__retres1~10#1 := 0; 11047#L794 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 11244#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 11574#L1572 assume !(0 != activate_threads_~tmp___9~0#1); 11575#L1572-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 12467#L802 assume 1 == ~t11_pc~0; 12449#L803 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 10932#L813 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 10933#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 11431#L1580 assume !(0 != activate_threads_~tmp___10~0#1); 11432#L1580-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 11549#L821 assume !(1 == ~t12_pc~0); 11800#L821-2 is_transmit12_triggered_~__retres1~12#1 := 0; 11906#L832 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 10939#is_transmit12_triggered_returnLabel#1 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 10940#L1588 assume !(0 != activate_threads_~tmp___11~0#1); 12509#L1588-2 havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 12146#L1339 assume !(1 == ~M_E~0); 12147#L1339-2 assume !(1 == ~T1_E~0); 12539#L1344-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 12540#L1349-1 assume !(1 == ~T3_E~0); 11926#L1354-1 assume !(1 == ~T4_E~0); 11927#L1359-1 assume !(1 == ~T5_E~0); 12326#L1364-1 assume !(1 == ~T6_E~0); 11383#L1369-1 assume !(1 == ~T7_E~0); 11384#L1374-1 assume !(1 == ~T8_E~0); 11929#L1379-1 assume !(1 == ~T9_E~0); 11930#L1384-1 assume 1 == ~T10_E~0;~T10_E~0 := 2; 12038#L1389-1 assume !(1 == ~T11_E~0); 12503#L1394-1 assume !(1 == ~T12_E~0); 12504#L1399-1 assume !(1 == ~E_M~0); 12585#L1404-1 assume !(1 == ~E_1~0); 11476#L1409-1 assume !(1 == ~E_2~0); 11477#L1414-1 assume !(1 == ~E_3~0); 12209#L1419-1 assume !(1 == ~E_4~0); 11105#L1424-1 assume 1 == ~E_5~0;~E_5~0 := 2; 11106#L1429-1 assume !(1 == ~E_6~0); 11941#L1434-1 assume !(1 == ~E_7~0); 12521#L1439-1 assume !(1 == ~E_8~0); 11147#L1444-1 assume !(1 == ~E_9~0); 11148#L1449-1 assume !(1 == ~E_10~0); 11533#L1454-1 assume !(1 == ~E_11~0); 11534#L1459-1 assume !(1 == ~E_12~0); 12068#L1464-1 assume { :end_inline_reset_delta_events } true; 11289#L1810-2 [2023-11-12 02:03:58,129 INFO L750 eck$LassoCheckResult]: Loop: 11289#L1810-2 assume !false; 11739#L1811 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 11837#L1176-1 assume !false; 12219#L999 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 11783#L921 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 10973#L988 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 12273#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 12444#L1003 assume !(0 != eval_~tmp~0#1); 11746#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 11478#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 11479#L1201-3 assume 0 == ~M_E~0;~M_E~0 := 1; 12163#L1201-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 12164#L1206-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 12066#L1211-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 11232#L1216-3 assume !(0 == ~T4_E~0); 11233#L1221-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 11711#L1226-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 11311#L1231-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 11312#L1236-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 11563#L1241-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 12552#L1246-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 12452#L1251-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 12151#L1256-3 assume !(0 == ~T12_E~0); 11252#L1261-3 assume 0 == ~E_M~0;~E_M~0 := 1; 11253#L1266-3 assume 0 == ~E_1~0;~E_1~0 := 1; 11303#L1271-3 assume 0 == ~E_2~0;~E_2~0 := 1; 11304#L1276-3 assume 0 == ~E_3~0;~E_3~0 := 1; 11687#L1281-3 assume 0 == ~E_4~0;~E_4~0 := 1; 11688#L1286-3 assume 0 == ~E_5~0;~E_5~0 := 1; 12206#L1291-3 assume 0 == ~E_6~0;~E_6~0 := 1; 12207#L1296-3 assume !(0 == ~E_7~0); 12624#L1301-3 assume 0 == ~E_8~0;~E_8~0 := 1; 12582#L1306-3 assume 0 == ~E_9~0;~E_9~0 := 1; 11791#L1311-3 assume 0 == ~E_10~0;~E_10~0 := 1; 11172#L1316-3 assume 0 == ~E_11~0;~E_11~0 := 1; 11173#L1321-3 assume 0 == ~E_12~0;~E_12~0 := 1; 11254#L1326-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 11905#L593-42 assume 1 == ~m_pc~0; 12292#L594-14 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 12071#L604-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 11586#is_master_triggered_returnLabel#15 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 11587#L1492-42 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 11066#L1492-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 11067#L612-42 assume !(1 == ~t1_pc~0); 12025#L612-44 is_transmit1_triggered_~__retres1~1#1 := 0; 12406#L623-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 12633#is_transmit1_triggered_returnLabel#15 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 11159#L1500-42 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 11160#L1500-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 11868#L631-42 assume 1 == ~t2_pc~0; 10919#L632-14 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 10920#L642-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 11853#is_transmit2_triggered_returnLabel#15 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 11737#L1508-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 11738#L1508-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 11330#L650-42 assume 1 == ~t3_pc~0; 10884#L651-14 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 10885#L661-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 12239#is_transmit3_triggered_returnLabel#15 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 11525#L1516-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 11526#L1516-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 12523#L669-42 assume !(1 == ~t4_pc~0); 10882#L669-44 is_transmit4_triggered_~__retres1~4#1 := 0; 10883#L680-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 12308#is_transmit4_triggered_returnLabel#15 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 12217#L1524-42 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 12121#L1524-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 12122#L688-42 assume 1 == ~t5_pc~0; 12204#L689-14 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 12409#L699-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 11917#is_transmit5_triggered_returnLabel#15 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 11094#L1532-42 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 11095#L1532-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 10912#L707-42 assume !(1 == ~t6_pc~0); 10913#L707-44 is_transmit6_triggered_~__retres1~6#1 := 0; 12588#L718-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 11246#is_transmit6_triggered_returnLabel#15 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 11247#L1540-42 assume !(0 != activate_threads_~tmp___5~0#1); 12092#L1540-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 12093#L726-42 assume 1 == ~t7_pc~0; 12359#L727-14 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 12390#L737-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 11944#is_transmit7_triggered_returnLabel#15 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 11795#L1548-42 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 11796#L1548-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 11909#L745-42 assume 1 == ~t8_pc~0; 11947#L746-14 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 11949#L756-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 12112#is_transmit8_triggered_returnLabel#15 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 10900#L1556-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 10901#L1556-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 11646#L764-42 assume 1 == ~t9_pc~0; 11774#L765-14 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 12135#L775-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 12136#is_transmit9_triggered_returnLabel#15 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 11184#L1564-42 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 11185#L1564-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 11245#L783-42 assume 1 == ~t10_pc~0; 10856#L784-14 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 10857#L794-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 11461#is_transmit10_triggered_returnLabel#15 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 12104#L1572-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 12615#L1572-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 12298#L802-42 assume 1 == ~t11_pc~0; 11392#L803-14 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 10998#L813-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 10999#is_transmit11_triggered_returnLabel#15 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 10945#L1580-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 10946#L1580-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 12143#L821-42 assume 1 == ~t12_pc~0; 12144#L822-14 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 11502#L832-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 11902#is_transmit12_triggered_returnLabel#15 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 11903#L1588-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 11839#L1588-44 havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 11829#L1339-3 assume 1 == ~M_E~0;~M_E~0 := 2; 11830#L1339-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 12002#L1344-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 12108#L1349-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 11511#L1354-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 11512#L1359-3 assume !(1 == ~T5_E~0); 12118#L1364-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 12609#L1369-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 12519#L1374-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 11332#L1379-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 11333#L1384-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 11509#L1389-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 11510#L1394-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 11725#L1399-3 assume !(1 == ~E_M~0); 12528#L1404-3 assume 1 == ~E_1~0;~E_1~0 := 2; 12496#L1409-3 assume 1 == ~E_2~0;~E_2~0 := 2; 12497#L1414-3 assume 1 == ~E_3~0;~E_3~0 := 2; 12551#L1419-3 assume 1 == ~E_4~0;~E_4~0 := 2; 12301#L1424-3 assume 1 == ~E_5~0;~E_5~0 := 2; 11206#L1429-3 assume 1 == ~E_6~0;~E_6~0 := 2; 11207#L1434-3 assume 1 == ~E_7~0;~E_7~0 := 2; 12117#L1439-3 assume !(1 == ~E_8~0); 11135#L1444-3 assume 1 == ~E_9~0;~E_9~0 := 2; 11136#L1449-3 assume 1 == ~E_10~0;~E_10~0 := 2; 11257#L1454-3 assume 1 == ~E_11~0;~E_11~0 := 2; 12113#L1459-3 assume 1 == ~E_12~0;~E_12~0 := 2; 12114#L1464-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 11756#L921-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 11038#L988-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 11240#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; 11241#L1829 assume !(0 == start_simulation_~tmp~3#1); 11020#L1829-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 11021#L921-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 11835#L988-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 10925#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret33#1;havoc stop_simulation_#t~ret33#1; 10926#L1784 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 12129#L1791 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 12502#stop_simulation_returnLabel#1 start_simulation_#t~ret35#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 11288#L1842 assume !(0 != start_simulation_~tmp___0~1#1); 11289#L1810-2 [2023-11-12 02:03:58,130 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-12 02:03:58,131 INFO L85 PathProgramCache]: Analyzing trace with hash -833138770, now seen corresponding path program 1 times [2023-11-12 02:03:58,131 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-12 02:03:58,131 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [290076010] [2023-11-12 02:03:58,132 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-12 02:03:58,132 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-12 02:03:58,168 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-12 02:03:58,228 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-12 02:03:58,229 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-12 02:03:58,230 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [290076010] [2023-11-12 02:03:58,230 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [290076010] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-12 02:03:58,230 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-12 02:03:58,231 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-12 02:03:58,231 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1854775319] [2023-11-12 02:03:58,231 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-12 02:03:58,232 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-12 02:03:58,232 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-12 02:03:58,232 INFO L85 PathProgramCache]: Analyzing trace with hash -918804904, now seen corresponding path program 1 times [2023-11-12 02:03:58,233 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-12 02:03:58,238 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1311484230] [2023-11-12 02:03:58,238 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-12 02:03:58,238 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-12 02:03:58,262 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-12 02:03:58,341 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-12 02:03:58,341 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-12 02:03:58,341 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1311484230] [2023-11-12 02:03:58,341 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1311484230] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-12 02:03:58,342 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-12 02:03:58,342 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-12 02:03:58,342 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1806681766] [2023-11-12 02:03:58,342 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-12 02:03:58,343 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-12 02:03:58,343 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-12 02:03:58,343 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-12 02:03:58,343 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-12 02:03:58,344 INFO L87 Difference]: Start difference. First operand 1801 states and 2662 transitions. cyclomatic complexity: 862 Second operand has 3 states, 3 states have (on average 50.0) internal successors, (150), 3 states have internal predecessors, (150), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-12 02:03:58,398 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-12 02:03:58,398 INFO L93 Difference]: Finished difference Result 1801 states and 2661 transitions. [2023-11-12 02:03:58,399 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1801 states and 2661 transitions. [2023-11-12 02:03:58,414 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1638 [2023-11-12 02:03:58,430 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1801 states to 1801 states and 2661 transitions. [2023-11-12 02:03:58,431 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1801 [2023-11-12 02:03:58,433 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1801 [2023-11-12 02:03:58,433 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1801 states and 2661 transitions. [2023-11-12 02:03:58,436 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-12 02:03:58,436 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1801 states and 2661 transitions. [2023-11-12 02:03:58,440 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1801 states and 2661 transitions. [2023-11-12 02:03:58,465 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1801 to 1801. [2023-11-12 02:03:58,469 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1801 states, 1801 states have (on average 1.4775124930594115) internal successors, (2661), 1800 states have internal predecessors, (2661), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-12 02:03:58,477 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1801 states to 1801 states and 2661 transitions. [2023-11-12 02:03:58,477 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1801 states and 2661 transitions. [2023-11-12 02:03:58,478 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-12 02:03:58,479 INFO L428 stractBuchiCegarLoop]: Abstraction has 1801 states and 2661 transitions. [2023-11-12 02:03:58,479 INFO L335 stractBuchiCegarLoop]: ======== Iteration 5 ============ [2023-11-12 02:03:58,479 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1801 states and 2661 transitions. [2023-11-12 02:03:58,490 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1638 [2023-11-12 02:03:58,490 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-12 02:03:58,491 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-12 02:03:58,493 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-12 02:03:58,494 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-12 02:03:58,494 INFO L748 eck$LassoCheckResult]: Stem: 14742#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(20, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~token~0 := 0;~local~0 := 0; 14743#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~14#1;havoc main_~__retres1~14#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1; 15587#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret34#1, start_simulation_#t~ret35#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 15588#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 16174#L848 assume 1 == ~m_i~0;~m_st~0 := 0; 16175#L848-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 15268#L853-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 15057#L858-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 14454#L863-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 14455#L868-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 15699#L873-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 15798#L878-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 16236#L883-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 16237#L888-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 15193#L893-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 15194#L898-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 15725#L903-1 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 15650#L908-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 15230#L1201 assume !(0 == ~M_E~0); 15231#L1201-2 assume 0 == ~T1_E~0;~T1_E~0 := 1; 16083#L1206-1 assume !(0 == ~T2_E~0); 16066#L1211-1 assume !(0 == ~T3_E~0); 16067#L1216-1 assume !(0 == ~T4_E~0); 15038#L1221-1 assume !(0 == ~T5_E~0); 15039#L1226-1 assume !(0 == ~T6_E~0); 14668#L1231-1 assume !(0 == ~T7_E~0); 14669#L1236-1 assume !(0 == ~T8_E~0); 16107#L1241-1 assume 0 == ~T9_E~0;~T9_E~0 := 1; 15078#L1246-1 assume !(0 == ~T10_E~0); 15079#L1251-1 assume !(0 == ~T11_E~0); 15228#L1256-1 assume !(0 == ~T12_E~0); 14463#L1261-1 assume !(0 == ~E_M~0); 14464#L1266-1 assume !(0 == ~E_1~0); 16221#L1271-1 assume !(0 == ~E_2~0); 15782#L1276-1 assume !(0 == ~E_3~0); 15783#L1281-1 assume 0 == ~E_4~0;~E_4~0 := 1; 15737#L1286-1 assume !(0 == ~E_5~0); 14934#L1291-1 assume !(0 == ~E_6~0); 14935#L1296-1 assume !(0 == ~E_7~0); 15523#L1301-1 assume !(0 == ~E_8~0); 15524#L1306-1 assume !(0 == ~E_9~0); 16002#L1311-1 assume !(0 == ~E_10~0); 14885#L1316-1 assume !(0 == ~E_11~0); 14886#L1321-1 assume 0 == ~E_12~0;~E_12~0 := 1; 15542#L1326-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 15543#L593 assume 1 == ~m_pc~0; 15692#L594 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 14767#L604 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 15431#is_master_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 15432#L1492 assume !(0 != activate_threads_~tmp~1#1); 15747#L1492-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 16035#L612 assume !(1 == ~t1_pc~0); 16036#L612-2 is_transmit1_triggered_~__retres1~1#1 := 0; 16170#L623 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 15880#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 14770#L1500 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 14771#L1500-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 15209#L631 assume 1 == ~t2_pc~0; 15136#L632 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 14544#L642 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 14545#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 14899#L1508 assume !(0 != activate_threads_~tmp___1~0#1); 15395#L1508-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 14846#L650 assume !(1 == ~t3_pc~0); 14847#L650-2 is_transmit3_triggered_~__retres1~3#1 := 0; 15565#L661 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 15859#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 14501#L1516 assume !(0 != activate_threads_~tmp___2~0#1); 14502#L1516-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 15718#L669 assume 1 == ~t4_pc~0; 15719#L670 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 16074#L680 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 14584#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 14585#L1524 assume !(0 != activate_threads_~tmp___3~0#1); 14705#L1524-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 14944#L688 assume !(1 == ~t5_pc~0); 14724#L688-2 is_transmit5_triggered_~__retres1~5#1 := 0; 14725#L699 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 16202#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 15607#L1532 assume !(0 != activate_threads_~tmp___4~0#1); 15608#L1532-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 15732#L707 assume 1 == ~t6_pc~0; 16141#L708 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 15364#L718 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 14887#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 14888#L1540 assume !(0 != activate_threads_~tmp___5~0#1); 15678#L1540-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 15229#L726 assume 1 == ~t7_pc~0; 15124#L727 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 14811#L737 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 15871#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 16145#L1548 assume !(0 != activate_threads_~tmp___6~0#1); 14574#L1548-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 14575#L745 assume !(1 == ~t8_pc~0); 15031#L745-2 is_transmit8_triggered_~__retres1~8#1 := 0; 15051#L756 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 16089#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 15440#L1556 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 15441#L1556-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 15959#L764 assume 1 == ~t9_pc~0; 15227#L765 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 15061#L775 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 14960#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 14961#L1564 assume !(0 != activate_threads_~tmp___8~0#1); 14600#L1564-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 14601#L783 assume !(1 == ~t10_pc~0); 14655#L783-2 is_transmit10_triggered_~__retres1~10#1 := 0; 14656#L794 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 14853#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 15183#L1572 assume !(0 != activate_threads_~tmp___9~0#1); 15184#L1572-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 16076#L802 assume 1 == ~t11_pc~0; 16058#L803 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 14541#L813 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 14542#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 15040#L1580 assume !(0 != activate_threads_~tmp___10~0#1); 15041#L1580-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 15158#L821 assume !(1 == ~t12_pc~0); 15409#L821-2 is_transmit12_triggered_~__retres1~12#1 := 0; 15515#L832 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 14548#is_transmit12_triggered_returnLabel#1 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 14549#L1588 assume !(0 != activate_threads_~tmp___11~0#1); 16118#L1588-2 havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 15755#L1339 assume !(1 == ~M_E~0); 15756#L1339-2 assume !(1 == ~T1_E~0); 16148#L1344-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 16149#L1349-1 assume !(1 == ~T3_E~0); 15535#L1354-1 assume !(1 == ~T4_E~0); 15536#L1359-1 assume !(1 == ~T5_E~0); 15935#L1364-1 assume !(1 == ~T6_E~0); 14992#L1369-1 assume !(1 == ~T7_E~0); 14993#L1374-1 assume !(1 == ~T8_E~0); 15538#L1379-1 assume !(1 == ~T9_E~0); 15539#L1384-1 assume 1 == ~T10_E~0;~T10_E~0 := 2; 15647#L1389-1 assume !(1 == ~T11_E~0); 16112#L1394-1 assume !(1 == ~T12_E~0); 16113#L1399-1 assume !(1 == ~E_M~0); 16194#L1404-1 assume !(1 == ~E_1~0); 15085#L1409-1 assume !(1 == ~E_2~0); 15086#L1414-1 assume !(1 == ~E_3~0); 15818#L1419-1 assume !(1 == ~E_4~0); 14714#L1424-1 assume 1 == ~E_5~0;~E_5~0 := 2; 14715#L1429-1 assume !(1 == ~E_6~0); 15550#L1434-1 assume !(1 == ~E_7~0); 16130#L1439-1 assume !(1 == ~E_8~0); 14756#L1444-1 assume !(1 == ~E_9~0); 14757#L1449-1 assume !(1 == ~E_10~0); 15142#L1454-1 assume !(1 == ~E_11~0); 15143#L1459-1 assume !(1 == ~E_12~0); 15677#L1464-1 assume { :end_inline_reset_delta_events } true; 14898#L1810-2 [2023-11-12 02:03:58,495 INFO L750 eck$LassoCheckResult]: Loop: 14898#L1810-2 assume !false; 15348#L1811 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 15446#L1176-1 assume !false; 15828#L999 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 15392#L921 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 14582#L988 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 15882#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 16053#L1003 assume !(0 != eval_~tmp~0#1); 15355#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 15087#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 15088#L1201-3 assume 0 == ~M_E~0;~M_E~0 := 1; 15772#L1201-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 15773#L1206-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 15675#L1211-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 14841#L1216-3 assume !(0 == ~T4_E~0); 14842#L1221-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 15320#L1226-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 14920#L1231-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 14921#L1236-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 15172#L1241-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 16161#L1246-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 16061#L1251-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 15760#L1256-3 assume !(0 == ~T12_E~0); 14861#L1261-3 assume 0 == ~E_M~0;~E_M~0 := 1; 14862#L1266-3 assume 0 == ~E_1~0;~E_1~0 := 1; 14912#L1271-3 assume 0 == ~E_2~0;~E_2~0 := 1; 14913#L1276-3 assume 0 == ~E_3~0;~E_3~0 := 1; 15296#L1281-3 assume 0 == ~E_4~0;~E_4~0 := 1; 15297#L1286-3 assume 0 == ~E_5~0;~E_5~0 := 1; 15815#L1291-3 assume 0 == ~E_6~0;~E_6~0 := 1; 15816#L1296-3 assume !(0 == ~E_7~0); 16233#L1301-3 assume 0 == ~E_8~0;~E_8~0 := 1; 16191#L1306-3 assume 0 == ~E_9~0;~E_9~0 := 1; 15400#L1311-3 assume 0 == ~E_10~0;~E_10~0 := 1; 14781#L1316-3 assume 0 == ~E_11~0;~E_11~0 := 1; 14782#L1321-3 assume 0 == ~E_12~0;~E_12~0 := 1; 14863#L1326-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 15514#L593-42 assume 1 == ~m_pc~0; 15901#L594-14 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 15680#L604-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 15195#is_master_triggered_returnLabel#15 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 15196#L1492-42 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 14675#L1492-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 14676#L612-42 assume !(1 == ~t1_pc~0); 15634#L612-44 is_transmit1_triggered_~__retres1~1#1 := 0; 16015#L623-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 16242#is_transmit1_triggered_returnLabel#15 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 14768#L1500-42 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 14769#L1500-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 15477#L631-42 assume 1 == ~t2_pc~0; 14528#L632-14 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 14529#L642-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 15462#is_transmit2_triggered_returnLabel#15 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 15346#L1508-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 15347#L1508-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 14939#L650-42 assume 1 == ~t3_pc~0; 14493#L651-14 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 14494#L661-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 15848#is_transmit3_triggered_returnLabel#15 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 15134#L1516-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 15135#L1516-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 16132#L669-42 assume 1 == ~t4_pc~0; 15414#L670-14 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 14492#L680-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 15917#is_transmit4_triggered_returnLabel#15 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 15826#L1524-42 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 15730#L1524-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 15731#L688-42 assume 1 == ~t5_pc~0; 15813#L689-14 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 16018#L699-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 15526#is_transmit5_triggered_returnLabel#15 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 14703#L1532-42 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 14704#L1532-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 14521#L707-42 assume !(1 == ~t6_pc~0); 14522#L707-44 is_transmit6_triggered_~__retres1~6#1 := 0; 16197#L718-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 14855#is_transmit6_triggered_returnLabel#15 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 14856#L1540-42 assume !(0 != activate_threads_~tmp___5~0#1); 15701#L1540-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 15702#L726-42 assume 1 == ~t7_pc~0; 15968#L727-14 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 15999#L737-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 15553#is_transmit7_triggered_returnLabel#15 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 15404#L1548-42 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 15405#L1548-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 15518#L745-42 assume 1 == ~t8_pc~0; 15556#L746-14 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 15558#L756-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 15721#is_transmit8_triggered_returnLabel#15 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 14509#L1556-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 14510#L1556-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 15255#L764-42 assume 1 == ~t9_pc~0; 15383#L765-14 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 15744#L775-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 15745#is_transmit9_triggered_returnLabel#15 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 14793#L1564-42 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 14794#L1564-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 14854#L783-42 assume 1 == ~t10_pc~0; 14465#L784-14 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 14466#L794-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 15070#is_transmit10_triggered_returnLabel#15 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 15713#L1572-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 16224#L1572-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 15907#L802-42 assume 1 == ~t11_pc~0; 15001#L803-14 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 14607#L813-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 14608#is_transmit11_triggered_returnLabel#15 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 14554#L1580-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 14555#L1580-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 15752#L821-42 assume !(1 == ~t12_pc~0); 15110#L821-44 is_transmit12_triggered_~__retres1~12#1 := 0; 15111#L832-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 15511#is_transmit12_triggered_returnLabel#15 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 15512#L1588-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 15448#L1588-44 havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 15438#L1339-3 assume 1 == ~M_E~0;~M_E~0 := 2; 15439#L1339-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 15611#L1344-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 15717#L1349-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 15120#L1354-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 15121#L1359-3 assume !(1 == ~T5_E~0); 15727#L1364-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 16218#L1369-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 16128#L1374-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 14941#L1379-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 14942#L1384-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 15118#L1389-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 15119#L1394-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 15334#L1399-3 assume !(1 == ~E_M~0); 16137#L1404-3 assume 1 == ~E_1~0;~E_1~0 := 2; 16105#L1409-3 assume 1 == ~E_2~0;~E_2~0 := 2; 16106#L1414-3 assume 1 == ~E_3~0;~E_3~0 := 2; 16160#L1419-3 assume 1 == ~E_4~0;~E_4~0 := 2; 15910#L1424-3 assume 1 == ~E_5~0;~E_5~0 := 2; 14815#L1429-3 assume 1 == ~E_6~0;~E_6~0 := 2; 14816#L1434-3 assume 1 == ~E_7~0;~E_7~0 := 2; 15726#L1439-3 assume !(1 == ~E_8~0); 14744#L1444-3 assume 1 == ~E_9~0;~E_9~0 := 2; 14745#L1449-3 assume 1 == ~E_10~0;~E_10~0 := 2; 14866#L1454-3 assume 1 == ~E_11~0;~E_11~0 := 2; 15722#L1459-3 assume 1 == ~E_12~0;~E_12~0 := 2; 15723#L1464-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 15365#L921-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 14647#L988-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 14849#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; 14850#L1829 assume !(0 == start_simulation_~tmp~3#1); 14629#L1829-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 14630#L921-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 15444#L988-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 14534#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret33#1;havoc stop_simulation_#t~ret33#1; 14535#L1784 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 15738#L1791 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 16111#stop_simulation_returnLabel#1 start_simulation_#t~ret35#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 14897#L1842 assume !(0 != start_simulation_~tmp___0~1#1); 14898#L1810-2 [2023-11-12 02:03:58,495 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-12 02:03:58,496 INFO L85 PathProgramCache]: Analyzing trace with hash -1259693268, now seen corresponding path program 1 times [2023-11-12 02:03:58,496 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-12 02:03:58,496 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1334503179] [2023-11-12 02:03:58,496 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-12 02:03:58,497 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-12 02:03:58,513 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-12 02:03:58,599 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-12 02:03:58,599 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-12 02:03:58,599 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1334503179] [2023-11-12 02:03:58,599 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1334503179] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-12 02:03:58,600 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-12 02:03:58,600 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-12 02:03:58,600 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1377067510] [2023-11-12 02:03:58,600 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-12 02:03:58,601 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-12 02:03:58,601 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-12 02:03:58,601 INFO L85 PathProgramCache]: Analyzing trace with hash 1385499736, now seen corresponding path program 1 times [2023-11-12 02:03:58,602 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-12 02:03:58,602 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [116845771] [2023-11-12 02:03:58,602 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-12 02:03:58,602 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-12 02:03:58,622 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-12 02:03:58,686 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-12 02:03:58,687 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-12 02:03:58,687 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [116845771] [2023-11-12 02:03:58,687 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [116845771] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-12 02:03:58,687 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-12 02:03:58,688 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-12 02:03:58,688 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [483313747] [2023-11-12 02:03:58,688 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-12 02:03:58,688 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-12 02:03:58,689 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-12 02:03:58,689 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-12 02:03:58,689 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-12 02:03:58,690 INFO L87 Difference]: Start difference. First operand 1801 states and 2661 transitions. cyclomatic complexity: 861 Second operand has 3 states, 3 states have (on average 50.0) internal successors, (150), 3 states have internal predecessors, (150), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-12 02:03:58,744 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-12 02:03:58,744 INFO L93 Difference]: Finished difference Result 1801 states and 2660 transitions. [2023-11-12 02:03:58,744 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1801 states and 2660 transitions. [2023-11-12 02:03:58,759 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1638 [2023-11-12 02:03:58,774 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1801 states to 1801 states and 2660 transitions. [2023-11-12 02:03:58,775 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1801 [2023-11-12 02:03:58,777 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1801 [2023-11-12 02:03:58,777 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1801 states and 2660 transitions. [2023-11-12 02:03:58,780 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-12 02:03:58,781 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1801 states and 2660 transitions. [2023-11-12 02:03:58,784 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1801 states and 2660 transitions. [2023-11-12 02:03:58,809 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1801 to 1801. [2023-11-12 02:03:58,813 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1801 states, 1801 states have (on average 1.4769572459744587) internal successors, (2660), 1800 states have internal predecessors, (2660), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-12 02:03:58,821 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1801 states to 1801 states and 2660 transitions. [2023-11-12 02:03:58,821 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1801 states and 2660 transitions. [2023-11-12 02:03:58,821 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-12 02:03:58,822 INFO L428 stractBuchiCegarLoop]: Abstraction has 1801 states and 2660 transitions. [2023-11-12 02:03:58,822 INFO L335 stractBuchiCegarLoop]: ======== Iteration 6 ============ [2023-11-12 02:03:58,823 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1801 states and 2660 transitions. [2023-11-12 02:03:58,831 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1638 [2023-11-12 02:03:58,831 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-12 02:03:58,831 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-12 02:03:58,834 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-12 02:03:58,834 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-12 02:03:58,835 INFO L748 eck$LassoCheckResult]: Stem: 18351#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(20, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~token~0 := 0;~local~0 := 0; 18352#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~14#1;havoc main_~__retres1~14#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1; 19197#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret34#1, start_simulation_#t~ret35#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 19198#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 19783#L848 assume 1 == ~m_i~0;~m_st~0 := 0; 19784#L848-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 18878#L853-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 18666#L858-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 18063#L863-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 18064#L868-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 19308#L873-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 19408#L878-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 19845#L883-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 19846#L888-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 18802#L893-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 18803#L898-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 19334#L903-1 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 19259#L908-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 18839#L1201 assume !(0 == ~M_E~0); 18840#L1201-2 assume 0 == ~T1_E~0;~T1_E~0 := 1; 19692#L1206-1 assume !(0 == ~T2_E~0); 19675#L1211-1 assume !(0 == ~T3_E~0); 19676#L1216-1 assume !(0 == ~T4_E~0); 18650#L1221-1 assume !(0 == ~T5_E~0); 18651#L1226-1 assume !(0 == ~T6_E~0); 18277#L1231-1 assume !(0 == ~T7_E~0); 18278#L1236-1 assume !(0 == ~T8_E~0); 19716#L1241-1 assume 0 == ~T9_E~0;~T9_E~0 := 1; 18690#L1246-1 assume !(0 == ~T10_E~0); 18691#L1251-1 assume !(0 == ~T11_E~0); 18837#L1256-1 assume !(0 == ~T12_E~0); 18072#L1261-1 assume !(0 == ~E_M~0); 18073#L1266-1 assume !(0 == ~E_1~0); 19830#L1271-1 assume !(0 == ~E_2~0); 19391#L1276-1 assume !(0 == ~E_3~0); 19392#L1281-1 assume 0 == ~E_4~0;~E_4~0 := 1; 19346#L1286-1 assume !(0 == ~E_5~0); 18543#L1291-1 assume !(0 == ~E_6~0); 18544#L1296-1 assume !(0 == ~E_7~0); 19132#L1301-1 assume !(0 == ~E_8~0); 19133#L1306-1 assume !(0 == ~E_9~0); 19611#L1311-1 assume !(0 == ~E_10~0); 18494#L1316-1 assume !(0 == ~E_11~0); 18495#L1321-1 assume 0 == ~E_12~0;~E_12~0 := 1; 19151#L1326-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 19152#L593 assume 1 == ~m_pc~0; 19301#L594 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 18376#L604 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 19040#is_master_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 19041#L1492 assume !(0 != activate_threads_~tmp~1#1); 19356#L1492-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 19644#L612 assume !(1 == ~t1_pc~0); 19645#L612-2 is_transmit1_triggered_~__retres1~1#1 := 0; 19779#L623 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 19490#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 18379#L1500 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 18380#L1500-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 18818#L631 assume 1 == ~t2_pc~0; 18745#L632 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 18153#L642 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 18154#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 18508#L1508 assume !(0 != activate_threads_~tmp___1~0#1); 19004#L1508-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 18457#L650 assume !(1 == ~t3_pc~0); 18458#L650-2 is_transmit3_triggered_~__retres1~3#1 := 0; 19174#L661 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 19468#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 18110#L1516 assume !(0 != activate_threads_~tmp___2~0#1); 18111#L1516-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 19327#L669 assume 1 == ~t4_pc~0; 19328#L670 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 19684#L680 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 18197#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 18198#L1524 assume !(0 != activate_threads_~tmp___3~0#1); 18314#L1524-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 18553#L688 assume !(1 == ~t5_pc~0); 18333#L688-2 is_transmit5_triggered_~__retres1~5#1 := 0; 18334#L699 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 19811#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 19218#L1532 assume !(0 != activate_threads_~tmp___4~0#1); 19219#L1532-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 19344#L707 assume 1 == ~t6_pc~0; 19750#L708 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 18973#L718 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 18496#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 18497#L1540 assume !(0 != activate_threads_~tmp___5~0#1); 19289#L1540-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 18838#L726 assume 1 == ~t7_pc~0; 18735#L727 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 18420#L737 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 19481#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 19755#L1548 assume !(0 != activate_threads_~tmp___6~0#1); 18183#L1548-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 18184#L745 assume !(1 == ~t8_pc~0); 18640#L745-2 is_transmit8_triggered_~__retres1~8#1 := 0; 18660#L756 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 19698#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 19049#L1556 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 19050#L1556-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 19568#L764 assume 1 == ~t9_pc~0; 18836#L765 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 18670#L775 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 18569#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 18570#L1564 assume !(0 != activate_threads_~tmp___8~0#1); 18209#L1564-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 18210#L783 assume !(1 == ~t10_pc~0); 18264#L783-2 is_transmit10_triggered_~__retres1~10#1 := 0; 18265#L794 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 18462#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 18797#L1572 assume !(0 != activate_threads_~tmp___9~0#1); 18798#L1572-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 19685#L802 assume 1 == ~t11_pc~0; 19667#L803 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 18150#L813 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 18151#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 18647#L1580 assume !(0 != activate_threads_~tmp___10~0#1); 18648#L1580-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 18767#L821 assume !(1 == ~t12_pc~0); 19018#L821-2 is_transmit12_triggered_~__retres1~12#1 := 0; 19124#L832 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 18157#is_transmit12_triggered_returnLabel#1 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 18158#L1588 assume !(0 != activate_threads_~tmp___11~0#1); 19727#L1588-2 havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 19364#L1339 assume !(1 == ~M_E~0); 19365#L1339-2 assume !(1 == ~T1_E~0); 19757#L1344-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 19758#L1349-1 assume !(1 == ~T3_E~0); 19144#L1354-1 assume !(1 == ~T4_E~0); 19145#L1359-1 assume !(1 == ~T5_E~0); 19544#L1364-1 assume !(1 == ~T6_E~0); 18601#L1369-1 assume !(1 == ~T7_E~0); 18602#L1374-1 assume !(1 == ~T8_E~0); 19147#L1379-1 assume !(1 == ~T9_E~0); 19148#L1384-1 assume 1 == ~T10_E~0;~T10_E~0 := 2; 19256#L1389-1 assume !(1 == ~T11_E~0); 19721#L1394-1 assume !(1 == ~T12_E~0); 19722#L1399-1 assume !(1 == ~E_M~0); 19803#L1404-1 assume !(1 == ~E_1~0); 18694#L1409-1 assume !(1 == ~E_2~0); 18695#L1414-1 assume !(1 == ~E_3~0); 19427#L1419-1 assume !(1 == ~E_4~0); 18323#L1424-1 assume 1 == ~E_5~0;~E_5~0 := 2; 18324#L1429-1 assume !(1 == ~E_6~0); 19159#L1434-1 assume !(1 == ~E_7~0); 19739#L1439-1 assume !(1 == ~E_8~0); 18365#L1444-1 assume !(1 == ~E_9~0); 18366#L1449-1 assume !(1 == ~E_10~0); 18751#L1454-1 assume !(1 == ~E_11~0); 18752#L1459-1 assume !(1 == ~E_12~0); 19286#L1464-1 assume { :end_inline_reset_delta_events } true; 18507#L1810-2 [2023-11-12 02:03:58,836 INFO L750 eck$LassoCheckResult]: Loop: 18507#L1810-2 assume !false; 18957#L1811 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 19055#L1176-1 assume !false; 19437#L999 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 19001#L921 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 18191#L988 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 19491#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 19662#L1003 assume !(0 != eval_~tmp~0#1); 18964#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 18696#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 18697#L1201-3 assume 0 == ~M_E~0;~M_E~0 := 1; 19381#L1201-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 19382#L1206-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 19284#L1211-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 18450#L1216-3 assume !(0 == ~T4_E~0); 18451#L1221-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 18929#L1226-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 18529#L1231-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 18530#L1236-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 18781#L1241-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 19770#L1246-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 19670#L1251-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 19369#L1256-3 assume !(0 == ~T12_E~0); 18470#L1261-3 assume 0 == ~E_M~0;~E_M~0 := 1; 18471#L1266-3 assume 0 == ~E_1~0;~E_1~0 := 1; 18521#L1271-3 assume 0 == ~E_2~0;~E_2~0 := 1; 18522#L1276-3 assume 0 == ~E_3~0;~E_3~0 := 1; 18905#L1281-3 assume 0 == ~E_4~0;~E_4~0 := 1; 18906#L1286-3 assume 0 == ~E_5~0;~E_5~0 := 1; 19424#L1291-3 assume 0 == ~E_6~0;~E_6~0 := 1; 19425#L1296-3 assume !(0 == ~E_7~0); 19842#L1301-3 assume 0 == ~E_8~0;~E_8~0 := 1; 19800#L1306-3 assume 0 == ~E_9~0;~E_9~0 := 1; 19009#L1311-3 assume 0 == ~E_10~0;~E_10~0 := 1; 18390#L1316-3 assume 0 == ~E_11~0;~E_11~0 := 1; 18391#L1321-3 assume 0 == ~E_12~0;~E_12~0 := 1; 18472#L1326-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 19123#L593-42 assume 1 == ~m_pc~0; 19510#L594-14 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 19288#L604-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 18804#is_master_triggered_returnLabel#15 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 18805#L1492-42 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 18284#L1492-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 18285#L612-42 assume !(1 == ~t1_pc~0); 19243#L612-44 is_transmit1_triggered_~__retres1~1#1 := 0; 19624#L623-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 19851#is_transmit1_triggered_returnLabel#15 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 18377#L1500-42 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 18378#L1500-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 19086#L631-42 assume 1 == ~t2_pc~0; 18137#L632-14 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 18138#L642-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 19071#is_transmit2_triggered_returnLabel#15 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 18955#L1508-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 18956#L1508-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 18548#L650-42 assume 1 == ~t3_pc~0; 18102#L651-14 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 18103#L661-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 19457#is_transmit3_triggered_returnLabel#15 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 18743#L1516-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 18744#L1516-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 19741#L669-42 assume !(1 == ~t4_pc~0); 18100#L669-44 is_transmit4_triggered_~__retres1~4#1 := 0; 18101#L680-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 19526#is_transmit4_triggered_returnLabel#15 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 19435#L1524-42 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 19339#L1524-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 19340#L688-42 assume 1 == ~t5_pc~0; 19422#L689-14 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 19627#L699-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 19135#is_transmit5_triggered_returnLabel#15 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 18312#L1532-42 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 18313#L1532-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 18130#L707-42 assume !(1 == ~t6_pc~0); 18131#L707-44 is_transmit6_triggered_~__retres1~6#1 := 0; 19806#L718-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 18464#is_transmit6_triggered_returnLabel#15 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 18465#L1540-42 assume !(0 != activate_threads_~tmp___5~0#1); 19310#L1540-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 19311#L726-42 assume 1 == ~t7_pc~0; 19577#L727-14 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 19608#L737-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 19162#is_transmit7_triggered_returnLabel#15 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 19013#L1548-42 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 19014#L1548-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 19127#L745-42 assume 1 == ~t8_pc~0; 19165#L746-14 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 19167#L756-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 19330#is_transmit8_triggered_returnLabel#15 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 18118#L1556-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 18119#L1556-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 18864#L764-42 assume 1 == ~t9_pc~0; 18992#L765-14 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 19353#L775-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 19354#is_transmit9_triggered_returnLabel#15 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 18402#L1564-42 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 18403#L1564-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 18463#L783-42 assume 1 == ~t10_pc~0; 18074#L784-14 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 18075#L794-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 18679#is_transmit10_triggered_returnLabel#15 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 19322#L1572-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 19833#L1572-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 19516#L802-42 assume 1 == ~t11_pc~0; 18610#L803-14 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 18216#L813-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 18217#is_transmit11_triggered_returnLabel#15 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 18163#L1580-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 18164#L1580-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 19361#L821-42 assume 1 == ~t12_pc~0; 19362#L822-14 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 18720#L832-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 19120#is_transmit12_triggered_returnLabel#15 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 19121#L1588-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 19057#L1588-44 havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 19047#L1339-3 assume 1 == ~M_E~0;~M_E~0 := 2; 19048#L1339-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 19220#L1344-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 19326#L1349-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 18729#L1354-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 18730#L1359-3 assume !(1 == ~T5_E~0); 19336#L1364-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 19827#L1369-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 19737#L1374-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 18550#L1379-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 18551#L1384-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 18727#L1389-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 18728#L1394-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 18943#L1399-3 assume !(1 == ~E_M~0); 19746#L1404-3 assume 1 == ~E_1~0;~E_1~0 := 2; 19714#L1409-3 assume 1 == ~E_2~0;~E_2~0 := 2; 19715#L1414-3 assume 1 == ~E_3~0;~E_3~0 := 2; 19769#L1419-3 assume 1 == ~E_4~0;~E_4~0 := 2; 19519#L1424-3 assume 1 == ~E_5~0;~E_5~0 := 2; 18424#L1429-3 assume 1 == ~E_6~0;~E_6~0 := 2; 18425#L1434-3 assume 1 == ~E_7~0;~E_7~0 := 2; 19335#L1439-3 assume !(1 == ~E_8~0); 18353#L1444-3 assume 1 == ~E_9~0;~E_9~0 := 2; 18354#L1449-3 assume 1 == ~E_10~0;~E_10~0 := 2; 18475#L1454-3 assume 1 == ~E_11~0;~E_11~0 := 2; 19331#L1459-3 assume 1 == ~E_12~0;~E_12~0 := 2; 19332#L1464-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 18974#L921-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 18256#L988-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 18455#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; 18456#L1829 assume !(0 == start_simulation_~tmp~3#1); 18238#L1829-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 18239#L921-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 19053#L988-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 18143#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret33#1;havoc stop_simulation_#t~ret33#1; 18144#L1784 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 19347#L1791 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 19720#stop_simulation_returnLabel#1 start_simulation_#t~ret35#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 18506#L1842 assume !(0 != start_simulation_~tmp___0~1#1); 18507#L1810-2 [2023-11-12 02:03:58,837 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-12 02:03:58,837 INFO L85 PathProgramCache]: Analyzing trace with hash -719263762, now seen corresponding path program 1 times [2023-11-12 02:03:58,837 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-12 02:03:58,837 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1431964007] [2023-11-12 02:03:58,838 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-12 02:03:58,838 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-12 02:03:58,858 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-12 02:03:58,906 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-12 02:03:58,907 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-12 02:03:58,907 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1431964007] [2023-11-12 02:03:58,907 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1431964007] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-12 02:03:58,907 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-12 02:03:58,908 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-12 02:03:58,908 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [595475607] [2023-11-12 02:03:58,908 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-12 02:03:58,908 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-12 02:03:58,909 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-12 02:03:58,909 INFO L85 PathProgramCache]: Analyzing trace with hash -918804904, now seen corresponding path program 2 times [2023-11-12 02:03:58,914 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-12 02:03:58,914 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [909214080] [2023-11-12 02:03:58,915 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-12 02:03:58,915 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-12 02:03:58,939 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-12 02:03:59,008 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-12 02:03:59,009 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-12 02:03:59,009 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [909214080] [2023-11-12 02:03:59,009 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [909214080] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-12 02:03:59,009 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-12 02:03:59,009 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-12 02:03:59,010 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2095110298] [2023-11-12 02:03:59,010 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-12 02:03:59,011 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-12 02:03:59,011 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-12 02:03:59,011 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-12 02:03:59,011 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-12 02:03:59,012 INFO L87 Difference]: Start difference. First operand 1801 states and 2660 transitions. cyclomatic complexity: 860 Second operand has 3 states, 3 states have (on average 50.0) internal successors, (150), 3 states have internal predecessors, (150), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-12 02:03:59,064 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-12 02:03:59,065 INFO L93 Difference]: Finished difference Result 1801 states and 2659 transitions. [2023-11-12 02:03:59,065 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1801 states and 2659 transitions. [2023-11-12 02:03:59,078 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1638 [2023-11-12 02:03:59,093 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1801 states to 1801 states and 2659 transitions. [2023-11-12 02:03:59,093 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1801 [2023-11-12 02:03:59,095 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1801 [2023-11-12 02:03:59,096 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1801 states and 2659 transitions. [2023-11-12 02:03:59,099 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-12 02:03:59,099 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1801 states and 2659 transitions. [2023-11-12 02:03:59,103 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1801 states and 2659 transitions. [2023-11-12 02:03:59,129 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1801 to 1801. [2023-11-12 02:03:59,134 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1801 states, 1801 states have (on average 1.4764019988895059) internal successors, (2659), 1800 states have internal predecessors, (2659), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-12 02:03:59,142 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1801 states to 1801 states and 2659 transitions. [2023-11-12 02:03:59,142 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1801 states and 2659 transitions. [2023-11-12 02:03:59,143 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-12 02:03:59,145 INFO L428 stractBuchiCegarLoop]: Abstraction has 1801 states and 2659 transitions. [2023-11-12 02:03:59,145 INFO L335 stractBuchiCegarLoop]: ======== Iteration 7 ============ [2023-11-12 02:03:59,145 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1801 states and 2659 transitions. [2023-11-12 02:03:59,154 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1638 [2023-11-12 02:03:59,154 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-12 02:03:59,156 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-12 02:03:59,159 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-12 02:03:59,159 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-12 02:03:59,159 INFO L748 eck$LassoCheckResult]: Stem: 21960#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(20, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~token~0 := 0;~local~0 := 0; 21961#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~14#1;havoc main_~__retres1~14#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1; 22805#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret34#1, start_simulation_#t~ret35#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 22806#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 23392#L848 assume 1 == ~m_i~0;~m_st~0 := 0; 23393#L848-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 22487#L853-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 22275#L858-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 21672#L863-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 21673#L868-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 22917#L873-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 23017#L878-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 23454#L883-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 23455#L888-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 22411#L893-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 22412#L898-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 22943#L903-1 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 22868#L908-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 22448#L1201 assume !(0 == ~M_E~0); 22449#L1201-2 assume 0 == ~T1_E~0;~T1_E~0 := 1; 23301#L1206-1 assume !(0 == ~T2_E~0); 23284#L1211-1 assume !(0 == ~T3_E~0); 23285#L1216-1 assume !(0 == ~T4_E~0); 22257#L1221-1 assume !(0 == ~T5_E~0); 22258#L1226-1 assume !(0 == ~T6_E~0); 21886#L1231-1 assume !(0 == ~T7_E~0); 21887#L1236-1 assume !(0 == ~T8_E~0); 23325#L1241-1 assume 0 == ~T9_E~0;~T9_E~0 := 1; 22299#L1246-1 assume !(0 == ~T10_E~0); 22300#L1251-1 assume !(0 == ~T11_E~0); 22446#L1256-1 assume !(0 == ~T12_E~0); 21681#L1261-1 assume !(0 == ~E_M~0); 21682#L1266-1 assume !(0 == ~E_1~0); 23439#L1271-1 assume !(0 == ~E_2~0); 23000#L1276-1 assume !(0 == ~E_3~0); 23001#L1281-1 assume 0 == ~E_4~0;~E_4~0 := 1; 22955#L1286-1 assume !(0 == ~E_5~0); 22152#L1291-1 assume !(0 == ~E_6~0); 22153#L1296-1 assume !(0 == ~E_7~0); 22741#L1301-1 assume !(0 == ~E_8~0); 22742#L1306-1 assume !(0 == ~E_9~0); 23220#L1311-1 assume !(0 == ~E_10~0); 22103#L1316-1 assume !(0 == ~E_11~0); 22104#L1321-1 assume 0 == ~E_12~0;~E_12~0 := 1; 22760#L1326-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 22761#L593 assume 1 == ~m_pc~0; 22910#L594 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 21985#L604 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 22649#is_master_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 22650#L1492 assume !(0 != activate_threads_~tmp~1#1); 22965#L1492-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 23253#L612 assume !(1 == ~t1_pc~0); 23254#L612-2 is_transmit1_triggered_~__retres1~1#1 := 0; 23388#L623 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 23098#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 21988#L1500 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 21989#L1500-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 22427#L631 assume 1 == ~t2_pc~0; 22354#L632 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 21762#L642 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 21763#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 22117#L1508 assume !(0 != activate_threads_~tmp___1~0#1); 22613#L1508-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 22066#L650 assume !(1 == ~t3_pc~0); 22067#L650-2 is_transmit3_triggered_~__retres1~3#1 := 0; 22783#L661 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 23077#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 21719#L1516 assume !(0 != activate_threads_~tmp___2~0#1); 21720#L1516-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 22936#L669 assume 1 == ~t4_pc~0; 22937#L670 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 23293#L680 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 21806#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 21807#L1524 assume !(0 != activate_threads_~tmp___3~0#1); 21923#L1524-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 22162#L688 assume !(1 == ~t5_pc~0); 21942#L688-2 is_transmit5_triggered_~__retres1~5#1 := 0; 21943#L699 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 23420#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 22825#L1532 assume !(0 != activate_threads_~tmp___4~0#1); 22826#L1532-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 22953#L707 assume 1 == ~t6_pc~0; 23359#L708 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 22582#L718 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 22105#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 22106#L1540 assume !(0 != activate_threads_~tmp___5~0#1); 22898#L1540-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 22447#L726 assume 1 == ~t7_pc~0; 22344#L727 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 22029#L737 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 23090#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 23363#L1548 assume !(0 != activate_threads_~tmp___6~0#1); 21792#L1548-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 21793#L745 assume !(1 == ~t8_pc~0); 22249#L745-2 is_transmit8_triggered_~__retres1~8#1 := 0; 22269#L756 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 23307#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 22658#L1556 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 22659#L1556-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 23177#L764 assume 1 == ~t9_pc~0; 22445#L765 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 22279#L775 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 22178#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 22179#L1564 assume !(0 != activate_threads_~tmp___8~0#1); 21818#L1564-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 21819#L783 assume !(1 == ~t10_pc~0); 21873#L783-2 is_transmit10_triggered_~__retres1~10#1 := 0; 21874#L794 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 22071#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 22406#L1572 assume !(0 != activate_threads_~tmp___9~0#1); 22407#L1572-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 23294#L802 assume 1 == ~t11_pc~0; 23276#L803 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 21759#L813 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 21760#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 22259#L1580 assume !(0 != activate_threads_~tmp___10~0#1); 22260#L1580-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 22376#L821 assume !(1 == ~t12_pc~0); 22627#L821-2 is_transmit12_triggered_~__retres1~12#1 := 0; 22733#L832 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 21768#is_transmit12_triggered_returnLabel#1 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 21769#L1588 assume !(0 != activate_threads_~tmp___11~0#1); 23336#L1588-2 havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 22973#L1339 assume !(1 == ~M_E~0); 22974#L1339-2 assume !(1 == ~T1_E~0); 23366#L1344-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 23367#L1349-1 assume !(1 == ~T3_E~0); 22754#L1354-1 assume !(1 == ~T4_E~0); 22755#L1359-1 assume !(1 == ~T5_E~0); 23155#L1364-1 assume !(1 == ~T6_E~0); 22210#L1369-1 assume !(1 == ~T7_E~0); 22211#L1374-1 assume !(1 == ~T8_E~0); 22756#L1379-1 assume !(1 == ~T9_E~0); 22757#L1384-1 assume 1 == ~T10_E~0;~T10_E~0 := 2; 22865#L1389-1 assume !(1 == ~T11_E~0); 23330#L1394-1 assume !(1 == ~T12_E~0); 23331#L1399-1 assume !(1 == ~E_M~0); 23412#L1404-1 assume !(1 == ~E_1~0); 22303#L1409-1 assume !(1 == ~E_2~0); 22304#L1414-1 assume !(1 == ~E_3~0); 23036#L1419-1 assume !(1 == ~E_4~0); 21932#L1424-1 assume 1 == ~E_5~0;~E_5~0 := 2; 21933#L1429-1 assume !(1 == ~E_6~0); 22768#L1434-1 assume !(1 == ~E_7~0); 23348#L1439-1 assume !(1 == ~E_8~0); 21974#L1444-1 assume !(1 == ~E_9~0); 21975#L1449-1 assume !(1 == ~E_10~0); 22362#L1454-1 assume !(1 == ~E_11~0); 22363#L1459-1 assume !(1 == ~E_12~0); 22895#L1464-1 assume { :end_inline_reset_delta_events } true; 22116#L1810-2 [2023-11-12 02:03:59,160 INFO L750 eck$LassoCheckResult]: Loop: 22116#L1810-2 assume !false; 22566#L1811 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 22664#L1176-1 assume !false; 23046#L999 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 22612#L921 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 21800#L988 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 23100#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 23273#L1003 assume !(0 != eval_~tmp~0#1); 22573#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 22305#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 22306#L1201-3 assume 0 == ~M_E~0;~M_E~0 := 1; 22990#L1201-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 22991#L1206-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 22893#L1211-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 22059#L1216-3 assume !(0 == ~T4_E~0); 22060#L1221-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 22538#L1226-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 22140#L1231-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 22141#L1236-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 22391#L1241-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 23379#L1246-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 23279#L1251-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 22978#L1256-3 assume !(0 == ~T12_E~0); 22079#L1261-3 assume 0 == ~E_M~0;~E_M~0 := 1; 22080#L1266-3 assume 0 == ~E_1~0;~E_1~0 := 1; 22130#L1271-3 assume 0 == ~E_2~0;~E_2~0 := 1; 22131#L1276-3 assume 0 == ~E_3~0;~E_3~0 := 1; 22514#L1281-3 assume 0 == ~E_4~0;~E_4~0 := 1; 22515#L1286-3 assume 0 == ~E_5~0;~E_5~0 := 1; 23034#L1291-3 assume 0 == ~E_6~0;~E_6~0 := 1; 23035#L1296-3 assume !(0 == ~E_7~0); 23451#L1301-3 assume 0 == ~E_8~0;~E_8~0 := 1; 23409#L1306-3 assume 0 == ~E_9~0;~E_9~0 := 1; 22618#L1311-3 assume 0 == ~E_10~0;~E_10~0 := 1; 21999#L1316-3 assume 0 == ~E_11~0;~E_11~0 := 1; 22000#L1321-3 assume 0 == ~E_12~0;~E_12~0 := 1; 22081#L1326-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 22732#L593-42 assume !(1 == ~m_pc~0); 22896#L593-44 is_master_triggered_~__retres1~0#1 := 0; 22897#L604-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 22413#is_master_triggered_returnLabel#15 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 22414#L1492-42 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 21890#L1492-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 21891#L612-42 assume !(1 == ~t1_pc~0); 22850#L612-44 is_transmit1_triggered_~__retres1~1#1 := 0; 23232#L623-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 23460#is_transmit1_triggered_returnLabel#15 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 21986#L1500-42 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 21987#L1500-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 22694#L631-42 assume 1 == ~t2_pc~0; 21746#L632-14 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 21747#L642-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 22680#is_transmit2_triggered_returnLabel#15 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 22564#L1508-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 22565#L1508-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 22157#L650-42 assume !(1 == ~t3_pc~0); 21713#L650-44 is_transmit3_triggered_~__retres1~3#1 := 0; 21712#L661-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 23066#is_transmit3_triggered_returnLabel#15 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 22352#L1516-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 22353#L1516-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 23350#L669-42 assume 1 == ~t4_pc~0; 22632#L670-14 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 21708#L680-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 23135#is_transmit4_triggered_returnLabel#15 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 23044#L1524-42 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 22948#L1524-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 22949#L688-42 assume 1 == ~t5_pc~0; 23031#L689-14 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 23236#L699-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 22744#is_transmit5_triggered_returnLabel#15 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 21918#L1532-42 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 21919#L1532-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 21739#L707-42 assume !(1 == ~t6_pc~0); 21740#L707-44 is_transmit6_triggered_~__retres1~6#1 := 0; 23415#L718-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 22073#is_transmit6_triggered_returnLabel#15 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 22074#L1540-42 assume !(0 != activate_threads_~tmp___5~0#1); 22919#L1540-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 22920#L726-42 assume 1 == ~t7_pc~0; 23186#L727-14 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 23217#L737-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 22771#is_transmit7_triggered_returnLabel#15 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 22622#L1548-42 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 22623#L1548-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 22736#L745-42 assume 1 == ~t8_pc~0; 22773#L746-14 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 22775#L756-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 22939#is_transmit8_triggered_returnLabel#15 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 21727#L1556-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 21728#L1556-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 22471#L764-42 assume 1 == ~t9_pc~0; 22601#L765-14 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 22962#L775-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 22963#is_transmit9_triggered_returnLabel#15 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 22011#L1564-42 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 22012#L1564-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 22072#L783-42 assume 1 == ~t10_pc~0; 21683#L784-14 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 21684#L794-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 22288#is_transmit10_triggered_returnLabel#15 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 22931#L1572-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 23442#L1572-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 23125#L802-42 assume 1 == ~t11_pc~0; 22219#L803-14 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 21825#L813-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 21826#is_transmit11_triggered_returnLabel#15 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 21772#L1580-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 21773#L1580-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 22970#L821-42 assume !(1 == ~t12_pc~0); 22328#L821-44 is_transmit12_triggered_~__retres1~12#1 := 0; 22329#L832-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 22729#is_transmit12_triggered_returnLabel#15 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 22730#L1588-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 22666#L1588-44 havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 22656#L1339-3 assume 1 == ~M_E~0;~M_E~0 := 2; 22657#L1339-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 22829#L1344-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 22935#L1349-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 22338#L1354-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 22339#L1359-3 assume !(1 == ~T5_E~0); 22945#L1364-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 23436#L1369-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 23346#L1374-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 22158#L1379-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 22159#L1384-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 22336#L1389-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 22337#L1394-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 22552#L1399-3 assume !(1 == ~E_M~0); 23355#L1404-3 assume 1 == ~E_1~0;~E_1~0 := 2; 23323#L1409-3 assume 1 == ~E_2~0;~E_2~0 := 2; 23324#L1414-3 assume 1 == ~E_3~0;~E_3~0 := 2; 23378#L1419-3 assume 1 == ~E_4~0;~E_4~0 := 2; 23128#L1424-3 assume 1 == ~E_5~0;~E_5~0 := 2; 22033#L1429-3 assume 1 == ~E_6~0;~E_6~0 := 2; 22034#L1434-3 assume 1 == ~E_7~0;~E_7~0 := 2; 22944#L1439-3 assume !(1 == ~E_8~0); 21962#L1444-3 assume 1 == ~E_9~0;~E_9~0 := 2; 21963#L1449-3 assume 1 == ~E_10~0;~E_10~0 := 2; 22084#L1454-3 assume 1 == ~E_11~0;~E_11~0 := 2; 22940#L1459-3 assume 1 == ~E_12~0;~E_12~0 := 2; 22941#L1464-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 22583#L921-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 21865#L988-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 22064#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; 22065#L1829 assume !(0 == start_simulation_~tmp~3#1); 21847#L1829-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 21848#L921-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 22662#L988-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 21752#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret33#1;havoc stop_simulation_#t~ret33#1; 21753#L1784 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 22956#L1791 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 23329#stop_simulation_returnLabel#1 start_simulation_#t~ret35#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 22115#L1842 assume !(0 != start_simulation_~tmp___0~1#1); 22116#L1810-2 [2023-11-12 02:03:59,161 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-12 02:03:59,161 INFO L85 PathProgramCache]: Analyzing trace with hash -563283220, now seen corresponding path program 1 times [2023-11-12 02:03:59,161 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-12 02:03:59,162 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1724652412] [2023-11-12 02:03:59,162 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-12 02:03:59,163 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-12 02:03:59,182 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-12 02:03:59,229 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-12 02:03:59,230 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-12 02:03:59,230 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1724652412] [2023-11-12 02:03:59,231 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1724652412] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-12 02:03:59,231 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-12 02:03:59,231 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-12 02:03:59,231 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1704726505] [2023-11-12 02:03:59,232 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-12 02:03:59,232 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-12 02:03:59,232 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-12 02:03:59,233 INFO L85 PathProgramCache]: Analyzing trace with hash -1307554790, now seen corresponding path program 1 times [2023-11-12 02:03:59,233 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-12 02:03:59,233 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [169895000] [2023-11-12 02:03:59,233 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-12 02:03:59,234 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-12 02:03:59,281 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-12 02:03:59,353 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-12 02:03:59,353 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-12 02:03:59,354 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [169895000] [2023-11-12 02:03:59,354 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [169895000] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-12 02:03:59,354 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-12 02:03:59,354 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-12 02:03:59,355 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [389182775] [2023-11-12 02:03:59,355 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-12 02:03:59,355 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-12 02:03:59,356 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-12 02:03:59,356 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-12 02:03:59,356 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-12 02:03:59,356 INFO L87 Difference]: Start difference. First operand 1801 states and 2659 transitions. cyclomatic complexity: 859 Second operand has 3 states, 3 states have (on average 50.0) internal successors, (150), 3 states have internal predecessors, (150), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-12 02:03:59,416 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-12 02:03:59,416 INFO L93 Difference]: Finished difference Result 1801 states and 2658 transitions. [2023-11-12 02:03:59,417 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1801 states and 2658 transitions. [2023-11-12 02:03:59,432 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1638 [2023-11-12 02:03:59,448 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1801 states to 1801 states and 2658 transitions. [2023-11-12 02:03:59,449 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1801 [2023-11-12 02:03:59,453 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1801 [2023-11-12 02:03:59,453 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1801 states and 2658 transitions. [2023-11-12 02:03:59,457 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-12 02:03:59,457 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1801 states and 2658 transitions. [2023-11-12 02:03:59,462 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1801 states and 2658 transitions. [2023-11-12 02:03:59,502 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1801 to 1801. [2023-11-12 02:03:59,506 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1801 states, 1801 states have (on average 1.475846751804553) internal successors, (2658), 1800 states have internal predecessors, (2658), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-12 02:03:59,515 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1801 states to 1801 states and 2658 transitions. [2023-11-12 02:03:59,515 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1801 states and 2658 transitions. [2023-11-12 02:03:59,516 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-12 02:03:59,518 INFO L428 stractBuchiCegarLoop]: Abstraction has 1801 states and 2658 transitions. [2023-11-12 02:03:59,518 INFO L335 stractBuchiCegarLoop]: ======== Iteration 8 ============ [2023-11-12 02:03:59,518 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1801 states and 2658 transitions. [2023-11-12 02:03:59,528 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1638 [2023-11-12 02:03:59,528 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-12 02:03:59,528 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-12 02:03:59,531 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-12 02:03:59,532 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-12 02:03:59,532 INFO L748 eck$LassoCheckResult]: Stem: 25569#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(20, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~token~0 := 0;~local~0 := 0; 25570#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~14#1;havoc main_~__retres1~14#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1; 26414#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret34#1, start_simulation_#t~ret35#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 26415#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 27001#L848 assume 1 == ~m_i~0;~m_st~0 := 0; 27002#L848-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 26096#L853-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 25884#L858-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 25281#L863-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 25282#L868-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 26526#L873-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 26626#L878-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 27063#L883-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 27064#L888-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 26020#L893-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 26021#L898-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 26552#L903-1 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 26477#L908-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 26057#L1201 assume !(0 == ~M_E~0); 26058#L1201-2 assume 0 == ~T1_E~0;~T1_E~0 := 1; 26910#L1206-1 assume !(0 == ~T2_E~0); 26893#L1211-1 assume !(0 == ~T3_E~0); 26894#L1216-1 assume !(0 == ~T4_E~0); 25866#L1221-1 assume !(0 == ~T5_E~0); 25867#L1226-1 assume !(0 == ~T6_E~0); 25495#L1231-1 assume !(0 == ~T7_E~0); 25496#L1236-1 assume !(0 == ~T8_E~0); 26934#L1241-1 assume 0 == ~T9_E~0;~T9_E~0 := 1; 25905#L1246-1 assume !(0 == ~T10_E~0); 25906#L1251-1 assume !(0 == ~T11_E~0); 26055#L1256-1 assume !(0 == ~T12_E~0); 25290#L1261-1 assume !(0 == ~E_M~0); 25291#L1266-1 assume !(0 == ~E_1~0); 27048#L1271-1 assume !(0 == ~E_2~0); 26609#L1276-1 assume !(0 == ~E_3~0); 26610#L1281-1 assume 0 == ~E_4~0;~E_4~0 := 1; 26564#L1286-1 assume !(0 == ~E_5~0); 25761#L1291-1 assume !(0 == ~E_6~0); 25762#L1296-1 assume !(0 == ~E_7~0); 26350#L1301-1 assume !(0 == ~E_8~0); 26351#L1306-1 assume !(0 == ~E_9~0); 26829#L1311-1 assume !(0 == ~E_10~0); 25712#L1316-1 assume !(0 == ~E_11~0); 25713#L1321-1 assume 0 == ~E_12~0;~E_12~0 := 1; 26369#L1326-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 26370#L593 assume 1 == ~m_pc~0; 26519#L594 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 25594#L604 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 26258#is_master_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 26259#L1492 assume !(0 != activate_threads_~tmp~1#1); 26574#L1492-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 26862#L612 assume !(1 == ~t1_pc~0); 26863#L612-2 is_transmit1_triggered_~__retres1~1#1 := 0; 26997#L623 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 26707#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 25597#L1500 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 25598#L1500-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 26036#L631 assume 1 == ~t2_pc~0; 25963#L632 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 25371#L642 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 25372#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 25726#L1508 assume !(0 != activate_threads_~tmp___1~0#1); 26222#L1508-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 25675#L650 assume !(1 == ~t3_pc~0); 25676#L650-2 is_transmit3_triggered_~__retres1~3#1 := 0; 26392#L661 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 26686#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 25328#L1516 assume !(0 != activate_threads_~tmp___2~0#1); 25329#L1516-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 26545#L669 assume 1 == ~t4_pc~0; 26546#L670 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 26902#L680 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 25415#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 25416#L1524 assume !(0 != activate_threads_~tmp___3~0#1); 25532#L1524-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 25771#L688 assume !(1 == ~t5_pc~0); 25551#L688-2 is_transmit5_triggered_~__retres1~5#1 := 0; 25552#L699 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 27029#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 26434#L1532 assume !(0 != activate_threads_~tmp___4~0#1); 26435#L1532-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 26562#L707 assume 1 == ~t6_pc~0; 26968#L708 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 26191#L718 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 25714#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 25715#L1540 assume !(0 != activate_threads_~tmp___5~0#1); 26505#L1540-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 26056#L726 assume 1 == ~t7_pc~0; 25953#L727 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 25638#L737 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 26699#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 26972#L1548 assume !(0 != activate_threads_~tmp___6~0#1); 25401#L1548-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 25402#L745 assume !(1 == ~t8_pc~0); 25858#L745-2 is_transmit8_triggered_~__retres1~8#1 := 0; 25878#L756 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 26916#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 26267#L1556 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 26268#L1556-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 26786#L764 assume 1 == ~t9_pc~0; 26054#L765 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 25888#L775 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 25787#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 25788#L1564 assume !(0 != activate_threads_~tmp___8~0#1); 25427#L1564-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 25428#L783 assume !(1 == ~t10_pc~0); 25482#L783-2 is_transmit10_triggered_~__retres1~10#1 := 0; 25483#L794 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 25680#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 26015#L1572 assume !(0 != activate_threads_~tmp___9~0#1); 26016#L1572-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 26903#L802 assume 1 == ~t11_pc~0; 26885#L803 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 25368#L813 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 25369#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 25868#L1580 assume !(0 != activate_threads_~tmp___10~0#1); 25869#L1580-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 25985#L821 assume !(1 == ~t12_pc~0); 26236#L821-2 is_transmit12_triggered_~__retres1~12#1 := 0; 26342#L832 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 25377#is_transmit12_triggered_returnLabel#1 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 25378#L1588 assume !(0 != activate_threads_~tmp___11~0#1); 26945#L1588-2 havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 26582#L1339 assume !(1 == ~M_E~0); 26583#L1339-2 assume !(1 == ~T1_E~0); 26975#L1344-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 26976#L1349-1 assume !(1 == ~T3_E~0); 26363#L1354-1 assume !(1 == ~T4_E~0); 26364#L1359-1 assume !(1 == ~T5_E~0); 26762#L1364-1 assume !(1 == ~T6_E~0); 25819#L1369-1 assume !(1 == ~T7_E~0); 25820#L1374-1 assume !(1 == ~T8_E~0); 26365#L1379-1 assume !(1 == ~T9_E~0); 26366#L1384-1 assume 1 == ~T10_E~0;~T10_E~0 := 2; 26474#L1389-1 assume !(1 == ~T11_E~0); 26939#L1394-1 assume !(1 == ~T12_E~0); 26940#L1399-1 assume !(1 == ~E_M~0); 27021#L1404-1 assume !(1 == ~E_1~0); 25912#L1409-1 assume !(1 == ~E_2~0); 25913#L1414-1 assume !(1 == ~E_3~0); 26645#L1419-1 assume !(1 == ~E_4~0); 25541#L1424-1 assume 1 == ~E_5~0;~E_5~0 := 2; 25542#L1429-1 assume !(1 == ~E_6~0); 26377#L1434-1 assume !(1 == ~E_7~0); 26957#L1439-1 assume !(1 == ~E_8~0); 25583#L1444-1 assume !(1 == ~E_9~0); 25584#L1449-1 assume !(1 == ~E_10~0); 25971#L1454-1 assume !(1 == ~E_11~0); 25972#L1459-1 assume !(1 == ~E_12~0); 26504#L1464-1 assume { :end_inline_reset_delta_events } true; 25725#L1810-2 [2023-11-12 02:03:59,533 INFO L750 eck$LassoCheckResult]: Loop: 25725#L1810-2 assume !false; 26175#L1811 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 26273#L1176-1 assume !false; 26655#L999 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 26220#L921 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 25409#L988 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 26709#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 26882#L1003 assume !(0 != eval_~tmp~0#1); 26182#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 25914#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 25915#L1201-3 assume 0 == ~M_E~0;~M_E~0 := 1; 26599#L1201-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 26600#L1206-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 26502#L1211-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 25668#L1216-3 assume !(0 == ~T4_E~0); 25669#L1221-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 26147#L1226-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 25747#L1231-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 25748#L1236-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 26000#L1241-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 26988#L1246-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 26888#L1251-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 26587#L1256-3 assume !(0 == ~T12_E~0); 25688#L1261-3 assume 0 == ~E_M~0;~E_M~0 := 1; 25689#L1266-3 assume 0 == ~E_1~0;~E_1~0 := 1; 25739#L1271-3 assume 0 == ~E_2~0;~E_2~0 := 1; 25740#L1276-3 assume 0 == ~E_3~0;~E_3~0 := 1; 26123#L1281-3 assume 0 == ~E_4~0;~E_4~0 := 1; 26124#L1286-3 assume 0 == ~E_5~0;~E_5~0 := 1; 26643#L1291-3 assume 0 == ~E_6~0;~E_6~0 := 1; 26644#L1296-3 assume !(0 == ~E_7~0); 27060#L1301-3 assume 0 == ~E_8~0;~E_8~0 := 1; 27018#L1306-3 assume 0 == ~E_9~0;~E_9~0 := 1; 26227#L1311-3 assume 0 == ~E_10~0;~E_10~0 := 1; 25608#L1316-3 assume 0 == ~E_11~0;~E_11~0 := 1; 25609#L1321-3 assume 0 == ~E_12~0;~E_12~0 := 1; 25690#L1326-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 26341#L593-42 assume 1 == ~m_pc~0; 26729#L594-14 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 26507#L604-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 26024#is_master_triggered_returnLabel#15 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 26025#L1492-42 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 25505#L1492-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 25506#L612-42 assume !(1 == ~t1_pc~0); 26461#L612-44 is_transmit1_triggered_~__retres1~1#1 := 0; 26843#L623-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 27069#is_transmit1_triggered_returnLabel#15 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 25595#L1500-42 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 25596#L1500-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 26304#L631-42 assume !(1 == ~t2_pc~0); 25360#L631-44 is_transmit2_triggered_~__retres1~2#1 := 0; 25359#L642-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 26289#is_transmit2_triggered_returnLabel#15 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 26173#L1508-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 26174#L1508-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 25766#L650-42 assume 1 == ~t3_pc~0; 25323#L651-14 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 25324#L661-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 26675#is_transmit3_triggered_returnLabel#15 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 25961#L1516-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 25962#L1516-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 26959#L669-42 assume 1 == ~t4_pc~0; 26244#L670-14 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 25319#L680-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 26744#is_transmit4_triggered_returnLabel#15 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 26653#L1524-42 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 26557#L1524-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 26558#L688-42 assume 1 == ~t5_pc~0; 26640#L689-14 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 26845#L699-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 26352#is_transmit5_triggered_returnLabel#15 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 25527#L1532-42 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 25528#L1532-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 25341#L707-42 assume !(1 == ~t6_pc~0); 25342#L707-44 is_transmit6_triggered_~__retres1~6#1 := 0; 27024#L718-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 25682#is_transmit6_triggered_returnLabel#15 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 25683#L1540-42 assume !(0 != activate_threads_~tmp___5~0#1); 26528#L1540-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 26529#L726-42 assume 1 == ~t7_pc~0; 26792#L727-14 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 26826#L737-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 26380#is_transmit7_triggered_returnLabel#15 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 26231#L1548-42 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 26232#L1548-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 26345#L745-42 assume 1 == ~t8_pc~0; 26382#L746-14 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 26384#L756-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 26548#is_transmit8_triggered_returnLabel#15 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 25336#L1556-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 25337#L1556-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 26080#L764-42 assume 1 == ~t9_pc~0; 26210#L765-14 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 26571#L775-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 26572#is_transmit9_triggered_returnLabel#15 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 25620#L1564-42 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 25621#L1564-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 25681#L783-42 assume 1 == ~t10_pc~0; 25292#L784-14 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 25293#L794-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 25895#is_transmit10_triggered_returnLabel#15 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 26540#L1572-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 27051#L1572-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 26734#L802-42 assume 1 == ~t11_pc~0; 25828#L803-14 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 25434#L813-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 25435#is_transmit11_triggered_returnLabel#15 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 25381#L1580-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 25382#L1580-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 26579#L821-42 assume !(1 == ~t12_pc~0); 25937#L821-44 is_transmit12_triggered_~__retres1~12#1 := 0; 25938#L832-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 26338#is_transmit12_triggered_returnLabel#15 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 26339#L1588-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 26275#L1588-44 havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 26262#L1339-3 assume 1 == ~M_E~0;~M_E~0 := 2; 26263#L1339-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 26438#L1344-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 26544#L1349-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 25947#L1354-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 25948#L1359-3 assume !(1 == ~T5_E~0); 26554#L1364-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 27045#L1369-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 26955#L1374-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 25767#L1379-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 25768#L1384-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 25945#L1389-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 25946#L1394-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 26161#L1399-3 assume !(1 == ~E_M~0); 26964#L1404-3 assume 1 == ~E_1~0;~E_1~0 := 2; 26932#L1409-3 assume 1 == ~E_2~0;~E_2~0 := 2; 26933#L1414-3 assume 1 == ~E_3~0;~E_3~0 := 2; 26987#L1419-3 assume 1 == ~E_4~0;~E_4~0 := 2; 26737#L1424-3 assume 1 == ~E_5~0;~E_5~0 := 2; 25642#L1429-3 assume 1 == ~E_6~0;~E_6~0 := 2; 25643#L1434-3 assume 1 == ~E_7~0;~E_7~0 := 2; 26553#L1439-3 assume !(1 == ~E_8~0); 25571#L1444-3 assume 1 == ~E_9~0;~E_9~0 := 2; 25572#L1449-3 assume 1 == ~E_10~0;~E_10~0 := 2; 25693#L1454-3 assume 1 == ~E_11~0;~E_11~0 := 2; 26549#L1459-3 assume 1 == ~E_12~0;~E_12~0 := 2; 26550#L1464-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 26192#L921-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 25474#L988-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 25673#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; 25674#L1829 assume !(0 == start_simulation_~tmp~3#1); 25456#L1829-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 25457#L921-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 26271#L988-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 25361#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret33#1;havoc stop_simulation_#t~ret33#1; 25362#L1784 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 26565#L1791 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 26938#stop_simulation_returnLabel#1 start_simulation_#t~ret35#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 25724#L1842 assume !(0 != start_simulation_~tmp___0~1#1); 25725#L1810-2 [2023-11-12 02:03:59,534 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-12 02:03:59,534 INFO L85 PathProgramCache]: Analyzing trace with hash -973893586, now seen corresponding path program 1 times [2023-11-12 02:03:59,535 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-12 02:03:59,535 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [159611919] [2023-11-12 02:03:59,535 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-12 02:03:59,535 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-12 02:03:59,557 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-12 02:03:59,615 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-12 02:03:59,615 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-12 02:03:59,617 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [159611919] [2023-11-12 02:03:59,617 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [159611919] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-12 02:03:59,617 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-12 02:03:59,618 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-12 02:03:59,618 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [111307230] [2023-11-12 02:03:59,618 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-12 02:03:59,619 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-12 02:03:59,619 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-12 02:03:59,619 INFO L85 PathProgramCache]: Analyzing trace with hash 1672959641, now seen corresponding path program 1 times [2023-11-12 02:03:59,620 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-12 02:03:59,622 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2138546593] [2023-11-12 02:03:59,622 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-12 02:03:59,622 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-12 02:03:59,647 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-12 02:03:59,721 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-12 02:03:59,722 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-12 02:03:59,722 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2138546593] [2023-11-12 02:03:59,724 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2138546593] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-12 02:03:59,724 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-12 02:03:59,724 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-12 02:03:59,725 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1068591145] [2023-11-12 02:03:59,725 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-12 02:03:59,725 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-12 02:03:59,725 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-12 02:03:59,726 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-12 02:03:59,726 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-12 02:03:59,726 INFO L87 Difference]: Start difference. First operand 1801 states and 2658 transitions. cyclomatic complexity: 858 Second operand has 3 states, 3 states have (on average 50.0) internal successors, (150), 3 states have internal predecessors, (150), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-12 02:03:59,777 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-12 02:03:59,777 INFO L93 Difference]: Finished difference Result 1801 states and 2657 transitions. [2023-11-12 02:03:59,777 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1801 states and 2657 transitions. [2023-11-12 02:03:59,789 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1638 [2023-11-12 02:03:59,804 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1801 states to 1801 states and 2657 transitions. [2023-11-12 02:03:59,804 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1801 [2023-11-12 02:03:59,806 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1801 [2023-11-12 02:03:59,807 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1801 states and 2657 transitions. [2023-11-12 02:03:59,809 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-12 02:03:59,810 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1801 states and 2657 transitions. [2023-11-12 02:03:59,813 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1801 states and 2657 transitions. [2023-11-12 02:03:59,838 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1801 to 1801. [2023-11-12 02:03:59,842 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1801 states, 1801 states have (on average 1.4752915047196002) internal successors, (2657), 1800 states have internal predecessors, (2657), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-12 02:03:59,856 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1801 states to 1801 states and 2657 transitions. [2023-11-12 02:03:59,857 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1801 states and 2657 transitions. [2023-11-12 02:03:59,857 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-12 02:03:59,860 INFO L428 stractBuchiCegarLoop]: Abstraction has 1801 states and 2657 transitions. [2023-11-12 02:03:59,860 INFO L335 stractBuchiCegarLoop]: ======== Iteration 9 ============ [2023-11-12 02:03:59,861 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1801 states and 2657 transitions. [2023-11-12 02:03:59,869 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1638 [2023-11-12 02:03:59,869 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-12 02:03:59,869 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-12 02:03:59,872 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-12 02:03:59,872 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-12 02:03:59,872 INFO L748 eck$LassoCheckResult]: Stem: 29178#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(20, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~token~0 := 0;~local~0 := 0; 29179#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~14#1;havoc main_~__retres1~14#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1; 30023#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret34#1, start_simulation_#t~ret35#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 30024#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 30610#L848 assume 1 == ~m_i~0;~m_st~0 := 0; 30611#L848-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 29704#L853-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 29493#L858-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 28890#L863-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 28891#L868-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 30135#L873-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 30234#L878-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 30672#L883-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 30673#L888-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 29629#L893-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 29630#L898-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 30161#L903-1 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 30086#L908-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 29666#L1201 assume !(0 == ~M_E~0); 29667#L1201-2 assume 0 == ~T1_E~0;~T1_E~0 := 1; 30519#L1206-1 assume !(0 == ~T2_E~0); 30502#L1211-1 assume !(0 == ~T3_E~0); 30503#L1216-1 assume !(0 == ~T4_E~0); 29474#L1221-1 assume !(0 == ~T5_E~0); 29475#L1226-1 assume !(0 == ~T6_E~0); 29104#L1231-1 assume !(0 == ~T7_E~0); 29105#L1236-1 assume !(0 == ~T8_E~0); 30543#L1241-1 assume 0 == ~T9_E~0;~T9_E~0 := 1; 29514#L1246-1 assume !(0 == ~T10_E~0); 29515#L1251-1 assume !(0 == ~T11_E~0); 29664#L1256-1 assume !(0 == ~T12_E~0); 28899#L1261-1 assume !(0 == ~E_M~0); 28900#L1266-1 assume !(0 == ~E_1~0); 30657#L1271-1 assume !(0 == ~E_2~0); 30218#L1276-1 assume !(0 == ~E_3~0); 30219#L1281-1 assume 0 == ~E_4~0;~E_4~0 := 1; 30173#L1286-1 assume !(0 == ~E_5~0); 29370#L1291-1 assume !(0 == ~E_6~0); 29371#L1296-1 assume !(0 == ~E_7~0); 29959#L1301-1 assume !(0 == ~E_8~0); 29960#L1306-1 assume !(0 == ~E_9~0); 30438#L1311-1 assume !(0 == ~E_10~0); 29321#L1316-1 assume !(0 == ~E_11~0); 29322#L1321-1 assume 0 == ~E_12~0;~E_12~0 := 1; 29978#L1326-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 29979#L593 assume 1 == ~m_pc~0; 30128#L594 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 29203#L604 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 29867#is_master_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 29868#L1492 assume !(0 != activate_threads_~tmp~1#1); 30183#L1492-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 30471#L612 assume !(1 == ~t1_pc~0); 30472#L612-2 is_transmit1_triggered_~__retres1~1#1 := 0; 30606#L623 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 30316#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 29206#L1500 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 29207#L1500-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 29645#L631 assume 1 == ~t2_pc~0; 29572#L632 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 28980#L642 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 28981#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 29335#L1508 assume !(0 != activate_threads_~tmp___1~0#1); 29831#L1508-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 29284#L650 assume !(1 == ~t3_pc~0); 29285#L650-2 is_transmit3_triggered_~__retres1~3#1 := 0; 30001#L661 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 30295#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 28937#L1516 assume !(0 != activate_threads_~tmp___2~0#1); 28938#L1516-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 30154#L669 assume 1 == ~t4_pc~0; 30155#L670 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 30510#L680 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 29022#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 29023#L1524 assume !(0 != activate_threads_~tmp___3~0#1); 29141#L1524-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 29380#L688 assume !(1 == ~t5_pc~0); 29160#L688-2 is_transmit5_triggered_~__retres1~5#1 := 0; 29161#L699 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 30638#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 30043#L1532 assume !(0 != activate_threads_~tmp___4~0#1); 30044#L1532-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 30168#L707 assume 1 == ~t6_pc~0; 30577#L708 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 29800#L718 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 29323#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 29324#L1540 assume !(0 != activate_threads_~tmp___5~0#1); 30114#L1540-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 29665#L726 assume 1 == ~t7_pc~0; 29560#L727 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 29247#L737 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 30307#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 30581#L1548 assume !(0 != activate_threads_~tmp___6~0#1); 29010#L1548-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 29011#L745 assume !(1 == ~t8_pc~0); 29467#L745-2 is_transmit8_triggered_~__retres1~8#1 := 0; 29487#L756 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 30525#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 29876#L1556 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 29877#L1556-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 30395#L764 assume 1 == ~t9_pc~0; 29663#L765 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 29497#L775 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 29396#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 29397#L1564 assume !(0 != activate_threads_~tmp___8~0#1); 29036#L1564-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 29037#L783 assume !(1 == ~t10_pc~0); 29091#L783-2 is_transmit10_triggered_~__retres1~10#1 := 0; 29092#L794 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 29289#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 29619#L1572 assume !(0 != activate_threads_~tmp___9~0#1); 29620#L1572-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 30512#L802 assume 1 == ~t11_pc~0; 30494#L803 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 28977#L813 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 28978#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 29476#L1580 assume !(0 != activate_threads_~tmp___10~0#1); 29477#L1580-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 29594#L821 assume !(1 == ~t12_pc~0); 29845#L821-2 is_transmit12_triggered_~__retres1~12#1 := 0; 29951#L832 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 28986#is_transmit12_triggered_returnLabel#1 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 28987#L1588 assume !(0 != activate_threads_~tmp___11~0#1); 30554#L1588-2 havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 30191#L1339 assume !(1 == ~M_E~0); 30192#L1339-2 assume !(1 == ~T1_E~0); 30584#L1344-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 30585#L1349-1 assume !(1 == ~T3_E~0); 29971#L1354-1 assume !(1 == ~T4_E~0); 29972#L1359-1 assume !(1 == ~T5_E~0); 30371#L1364-1 assume !(1 == ~T6_E~0); 29428#L1369-1 assume !(1 == ~T7_E~0); 29429#L1374-1 assume !(1 == ~T8_E~0); 29974#L1379-1 assume !(1 == ~T9_E~0); 29975#L1384-1 assume 1 == ~T10_E~0;~T10_E~0 := 2; 30083#L1389-1 assume !(1 == ~T11_E~0); 30548#L1394-1 assume !(1 == ~T12_E~0); 30549#L1399-1 assume !(1 == ~E_M~0); 30630#L1404-1 assume !(1 == ~E_1~0); 29521#L1409-1 assume !(1 == ~E_2~0); 29522#L1414-1 assume !(1 == ~E_3~0); 30254#L1419-1 assume !(1 == ~E_4~0); 29150#L1424-1 assume 1 == ~E_5~0;~E_5~0 := 2; 29151#L1429-1 assume !(1 == ~E_6~0); 29986#L1434-1 assume !(1 == ~E_7~0); 30566#L1439-1 assume !(1 == ~E_8~0); 29192#L1444-1 assume !(1 == ~E_9~0); 29193#L1449-1 assume !(1 == ~E_10~0); 29578#L1454-1 assume !(1 == ~E_11~0); 29579#L1459-1 assume !(1 == ~E_12~0); 30113#L1464-1 assume { :end_inline_reset_delta_events } true; 29334#L1810-2 [2023-11-12 02:03:59,873 INFO L750 eck$LassoCheckResult]: Loop: 29334#L1810-2 assume !false; 29784#L1811 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 29882#L1176-1 assume !false; 30264#L999 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 29828#L921 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 29018#L988 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 30318#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 30489#L1003 assume !(0 != eval_~tmp~0#1); 29791#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 29523#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 29524#L1201-3 assume 0 == ~M_E~0;~M_E~0 := 1; 30208#L1201-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 30209#L1206-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 30111#L1211-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 29277#L1216-3 assume !(0 == ~T4_E~0); 29278#L1221-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 29756#L1226-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 29356#L1231-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 29357#L1236-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 29609#L1241-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 30597#L1246-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 30497#L1251-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 30196#L1256-3 assume !(0 == ~T12_E~0); 29297#L1261-3 assume 0 == ~E_M~0;~E_M~0 := 1; 29298#L1266-3 assume 0 == ~E_1~0;~E_1~0 := 1; 29348#L1271-3 assume 0 == ~E_2~0;~E_2~0 := 1; 29349#L1276-3 assume 0 == ~E_3~0;~E_3~0 := 1; 29732#L1281-3 assume 0 == ~E_4~0;~E_4~0 := 1; 29733#L1286-3 assume 0 == ~E_5~0;~E_5~0 := 1; 30252#L1291-3 assume 0 == ~E_6~0;~E_6~0 := 1; 30253#L1296-3 assume !(0 == ~E_7~0); 30669#L1301-3 assume 0 == ~E_8~0;~E_8~0 := 1; 30627#L1306-3 assume 0 == ~E_9~0;~E_9~0 := 1; 29836#L1311-3 assume 0 == ~E_10~0;~E_10~0 := 1; 29217#L1316-3 assume 0 == ~E_11~0;~E_11~0 := 1; 29218#L1321-3 assume 0 == ~E_12~0;~E_12~0 := 1; 29299#L1326-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 29950#L593-42 assume 1 == ~m_pc~0; 30338#L594-14 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 30116#L604-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 29631#is_master_triggered_returnLabel#15 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 29632#L1492-42 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 29111#L1492-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 29112#L612-42 assume !(1 == ~t1_pc~0); 30070#L612-44 is_transmit1_triggered_~__retres1~1#1 := 0; 30451#L623-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 30678#is_transmit1_triggered_returnLabel#15 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 29204#L1500-42 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 29205#L1500-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 29913#L631-42 assume 1 == ~t2_pc~0; 28967#L632-14 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 28968#L642-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 29898#is_transmit2_triggered_returnLabel#15 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 29782#L1508-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 29783#L1508-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 29375#L650-42 assume 1 == ~t3_pc~0; 28932#L651-14 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 28933#L661-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 30284#is_transmit3_triggered_returnLabel#15 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 29570#L1516-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 29571#L1516-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 30568#L669-42 assume 1 == ~t4_pc~0; 29853#L670-14 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 28928#L680-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 30353#is_transmit4_triggered_returnLabel#15 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 30262#L1524-42 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 30166#L1524-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 30167#L688-42 assume 1 == ~t5_pc~0; 30249#L689-14 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 30454#L699-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 29962#is_transmit5_triggered_returnLabel#15 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 29139#L1532-42 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 29140#L1532-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 28957#L707-42 assume !(1 == ~t6_pc~0); 28958#L707-44 is_transmit6_triggered_~__retres1~6#1 := 0; 30635#L718-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 29291#is_transmit6_triggered_returnLabel#15 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 29292#L1540-42 assume !(0 != activate_threads_~tmp___5~0#1); 30137#L1540-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 30138#L726-42 assume 1 == ~t7_pc~0; 30404#L727-14 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 30435#L737-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 29989#is_transmit7_triggered_returnLabel#15 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 29840#L1548-42 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 29841#L1548-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 29954#L745-42 assume 1 == ~t8_pc~0; 29995#L746-14 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 29997#L756-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 30157#is_transmit8_triggered_returnLabel#15 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 28945#L1556-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 28946#L1556-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 29691#L764-42 assume 1 == ~t9_pc~0; 29819#L765-14 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 30180#L775-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 30181#is_transmit9_triggered_returnLabel#15 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 29229#L1564-42 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 29230#L1564-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 29290#L783-42 assume 1 == ~t10_pc~0; 28901#L784-14 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 28902#L794-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 29504#is_transmit10_triggered_returnLabel#15 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 30149#L1572-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 30660#L1572-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 30343#L802-42 assume 1 == ~t11_pc~0; 29437#L803-14 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 29043#L813-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 29044#is_transmit11_triggered_returnLabel#15 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 28990#L1580-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 28991#L1580-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 30188#L821-42 assume !(1 == ~t12_pc~0); 29546#L821-44 is_transmit12_triggered_~__retres1~12#1 := 0; 29547#L832-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 29947#is_transmit12_triggered_returnLabel#15 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 29948#L1588-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 29884#L1588-44 havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 29871#L1339-3 assume 1 == ~M_E~0;~M_E~0 := 2; 29872#L1339-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 30047#L1344-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 30153#L1349-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 29556#L1354-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 29557#L1359-3 assume !(1 == ~T5_E~0); 30163#L1364-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 30654#L1369-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 30564#L1374-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 29376#L1379-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 29377#L1384-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 29554#L1389-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 29555#L1394-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 29770#L1399-3 assume !(1 == ~E_M~0); 30573#L1404-3 assume 1 == ~E_1~0;~E_1~0 := 2; 30541#L1409-3 assume 1 == ~E_2~0;~E_2~0 := 2; 30542#L1414-3 assume 1 == ~E_3~0;~E_3~0 := 2; 30596#L1419-3 assume 1 == ~E_4~0;~E_4~0 := 2; 30346#L1424-3 assume 1 == ~E_5~0;~E_5~0 := 2; 29251#L1429-3 assume 1 == ~E_6~0;~E_6~0 := 2; 29252#L1434-3 assume 1 == ~E_7~0;~E_7~0 := 2; 30162#L1439-3 assume !(1 == ~E_8~0); 29180#L1444-3 assume 1 == ~E_9~0;~E_9~0 := 2; 29181#L1449-3 assume 1 == ~E_10~0;~E_10~0 := 2; 29302#L1454-3 assume 1 == ~E_11~0;~E_11~0 := 2; 30158#L1459-3 assume 1 == ~E_12~0;~E_12~0 := 2; 30159#L1464-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 29801#L921-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 29083#L988-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 29282#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; 29283#L1829 assume !(0 == start_simulation_~tmp~3#1); 29065#L1829-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 29066#L921-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 29880#L988-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 28970#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret33#1;havoc stop_simulation_#t~ret33#1; 28971#L1784 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 30174#L1791 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 30547#stop_simulation_returnLabel#1 start_simulation_#t~ret35#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 29333#L1842 assume !(0 != start_simulation_~tmp___0~1#1); 29334#L1810-2 [2023-11-12 02:03:59,874 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-12 02:03:59,874 INFO L85 PathProgramCache]: Analyzing trace with hash 813976236, now seen corresponding path program 1 times [2023-11-12 02:03:59,874 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-12 02:03:59,874 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2061914861] [2023-11-12 02:03:59,875 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-12 02:03:59,875 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-12 02:03:59,891 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-12 02:03:59,936 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-12 02:03:59,937 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-12 02:03:59,937 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2061914861] [2023-11-12 02:03:59,937 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2061914861] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-12 02:03:59,937 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-12 02:03:59,938 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-12 02:03:59,938 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1436683980] [2023-11-12 02:03:59,938 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-12 02:03:59,938 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-12 02:03:59,939 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-12 02:03:59,939 INFO L85 PathProgramCache]: Analyzing trace with hash 1385499736, now seen corresponding path program 2 times [2023-11-12 02:03:59,939 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-12 02:03:59,939 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [122528212] [2023-11-12 02:03:59,940 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-12 02:03:59,940 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-12 02:03:59,966 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-12 02:04:00,026 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-12 02:04:00,027 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-12 02:04:00,027 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [122528212] [2023-11-12 02:04:00,027 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [122528212] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-12 02:04:00,028 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-12 02:04:00,028 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-12 02:04:00,028 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [796690666] [2023-11-12 02:04:00,028 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-12 02:04:00,029 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-12 02:04:00,029 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-12 02:04:00,029 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-12 02:04:00,029 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-12 02:04:00,030 INFO L87 Difference]: Start difference. First operand 1801 states and 2657 transitions. cyclomatic complexity: 857 Second operand has 3 states, 3 states have (on average 50.0) internal successors, (150), 3 states have internal predecessors, (150), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-12 02:04:00,078 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-12 02:04:00,079 INFO L93 Difference]: Finished difference Result 1801 states and 2656 transitions. [2023-11-12 02:04:00,079 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1801 states and 2656 transitions. [2023-11-12 02:04:00,090 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1638 [2023-11-12 02:04:00,104 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1801 states to 1801 states and 2656 transitions. [2023-11-12 02:04:00,104 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1801 [2023-11-12 02:04:00,106 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1801 [2023-11-12 02:04:00,107 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1801 states and 2656 transitions. [2023-11-12 02:04:00,149 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-12 02:04:00,149 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1801 states and 2656 transitions. [2023-11-12 02:04:00,153 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1801 states and 2656 transitions. [2023-11-12 02:04:00,179 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1801 to 1801. [2023-11-12 02:04:00,183 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1801 states, 1801 states have (on average 1.4747362576346474) internal successors, (2656), 1800 states have internal predecessors, (2656), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-12 02:04:00,190 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1801 states to 1801 states and 2656 transitions. [2023-11-12 02:04:00,190 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1801 states and 2656 transitions. [2023-11-12 02:04:00,191 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-12 02:04:00,191 INFO L428 stractBuchiCegarLoop]: Abstraction has 1801 states and 2656 transitions. [2023-11-12 02:04:00,191 INFO L335 stractBuchiCegarLoop]: ======== Iteration 10 ============ [2023-11-12 02:04:00,191 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1801 states and 2656 transitions. [2023-11-12 02:04:00,200 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1638 [2023-11-12 02:04:00,200 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-12 02:04:00,200 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-12 02:04:00,203 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-12 02:04:00,203 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-12 02:04:00,204 INFO L748 eck$LassoCheckResult]: Stem: 32787#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(20, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~token~0 := 0;~local~0 := 0; 32788#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~14#1;havoc main_~__retres1~14#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1; 33632#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret34#1, start_simulation_#t~ret35#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 33633#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 34219#L848 assume 1 == ~m_i~0;~m_st~0 := 0; 34220#L848-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 33313#L853-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 33102#L858-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 32499#L863-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 32500#L868-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 33744#L873-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 33843#L878-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 34281#L883-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 34282#L888-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 33238#L893-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 33239#L898-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 33770#L903-1 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 33695#L908-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 33275#L1201 assume !(0 == ~M_E~0); 33276#L1201-2 assume 0 == ~T1_E~0;~T1_E~0 := 1; 34128#L1206-1 assume !(0 == ~T2_E~0); 34111#L1211-1 assume !(0 == ~T3_E~0); 34112#L1216-1 assume !(0 == ~T4_E~0); 33083#L1221-1 assume !(0 == ~T5_E~0); 33084#L1226-1 assume !(0 == ~T6_E~0); 32713#L1231-1 assume !(0 == ~T7_E~0); 32714#L1236-1 assume !(0 == ~T8_E~0); 34152#L1241-1 assume 0 == ~T9_E~0;~T9_E~0 := 1; 33123#L1246-1 assume !(0 == ~T10_E~0); 33124#L1251-1 assume !(0 == ~T11_E~0); 33273#L1256-1 assume !(0 == ~T12_E~0); 32508#L1261-1 assume !(0 == ~E_M~0); 32509#L1266-1 assume !(0 == ~E_1~0); 34266#L1271-1 assume !(0 == ~E_2~0); 33827#L1276-1 assume !(0 == ~E_3~0); 33828#L1281-1 assume 0 == ~E_4~0;~E_4~0 := 1; 33782#L1286-1 assume !(0 == ~E_5~0); 32979#L1291-1 assume !(0 == ~E_6~0); 32980#L1296-1 assume !(0 == ~E_7~0); 33568#L1301-1 assume !(0 == ~E_8~0); 33569#L1306-1 assume !(0 == ~E_9~0); 34047#L1311-1 assume !(0 == ~E_10~0); 32930#L1316-1 assume !(0 == ~E_11~0); 32931#L1321-1 assume 0 == ~E_12~0;~E_12~0 := 1; 33587#L1326-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 33588#L593 assume 1 == ~m_pc~0; 33737#L594 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 32812#L604 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 33476#is_master_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 33477#L1492 assume !(0 != activate_threads_~tmp~1#1); 33792#L1492-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 34080#L612 assume !(1 == ~t1_pc~0); 34081#L612-2 is_transmit1_triggered_~__retres1~1#1 := 0; 34215#L623 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 33925#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 32815#L1500 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 32816#L1500-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 33254#L631 assume 1 == ~t2_pc~0; 33181#L632 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 32589#L642 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 32590#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 32944#L1508 assume !(0 != activate_threads_~tmp___1~0#1); 33440#L1508-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 32891#L650 assume !(1 == ~t3_pc~0); 32892#L650-2 is_transmit3_triggered_~__retres1~3#1 := 0; 33610#L661 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 33904#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 32546#L1516 assume !(0 != activate_threads_~tmp___2~0#1); 32547#L1516-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 33763#L669 assume 1 == ~t4_pc~0; 33764#L670 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 34119#L680 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 32629#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 32630#L1524 assume !(0 != activate_threads_~tmp___3~0#1); 32750#L1524-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 32989#L688 assume !(1 == ~t5_pc~0); 32769#L688-2 is_transmit5_triggered_~__retres1~5#1 := 0; 32770#L699 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 34247#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 33652#L1532 assume !(0 != activate_threads_~tmp___4~0#1); 33653#L1532-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 33777#L707 assume 1 == ~t6_pc~0; 34186#L708 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 33409#L718 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 32932#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 32933#L1540 assume !(0 != activate_threads_~tmp___5~0#1); 33723#L1540-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 33274#L726 assume 1 == ~t7_pc~0; 33169#L727 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 32856#L737 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 33916#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 34190#L1548 assume !(0 != activate_threads_~tmp___6~0#1); 32619#L1548-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 32620#L745 assume !(1 == ~t8_pc~0); 33076#L745-2 is_transmit8_triggered_~__retres1~8#1 := 0; 33096#L756 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 34134#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 33485#L1556 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 33486#L1556-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 34004#L764 assume 1 == ~t9_pc~0; 33272#L765 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 33106#L775 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 33005#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 33006#L1564 assume !(0 != activate_threads_~tmp___8~0#1); 32645#L1564-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 32646#L783 assume !(1 == ~t10_pc~0); 32700#L783-2 is_transmit10_triggered_~__retres1~10#1 := 0; 32701#L794 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 32898#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 33228#L1572 assume !(0 != activate_threads_~tmp___9~0#1); 33229#L1572-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 34121#L802 assume 1 == ~t11_pc~0; 34103#L803 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 32586#L813 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 32587#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 33085#L1580 assume !(0 != activate_threads_~tmp___10~0#1); 33086#L1580-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 33203#L821 assume !(1 == ~t12_pc~0); 33454#L821-2 is_transmit12_triggered_~__retres1~12#1 := 0; 33560#L832 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 32593#is_transmit12_triggered_returnLabel#1 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 32594#L1588 assume !(0 != activate_threads_~tmp___11~0#1); 34163#L1588-2 havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 33800#L1339 assume !(1 == ~M_E~0); 33801#L1339-2 assume !(1 == ~T1_E~0); 34193#L1344-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 34194#L1349-1 assume !(1 == ~T3_E~0); 33580#L1354-1 assume !(1 == ~T4_E~0); 33581#L1359-1 assume !(1 == ~T5_E~0); 33980#L1364-1 assume !(1 == ~T6_E~0); 33037#L1369-1 assume !(1 == ~T7_E~0); 33038#L1374-1 assume !(1 == ~T8_E~0); 33583#L1379-1 assume !(1 == ~T9_E~0); 33584#L1384-1 assume 1 == ~T10_E~0;~T10_E~0 := 2; 33692#L1389-1 assume !(1 == ~T11_E~0); 34157#L1394-1 assume !(1 == ~T12_E~0); 34158#L1399-1 assume !(1 == ~E_M~0); 34239#L1404-1 assume !(1 == ~E_1~0); 33130#L1409-1 assume !(1 == ~E_2~0); 33131#L1414-1 assume !(1 == ~E_3~0); 33863#L1419-1 assume !(1 == ~E_4~0); 32759#L1424-1 assume 1 == ~E_5~0;~E_5~0 := 2; 32760#L1429-1 assume !(1 == ~E_6~0); 33595#L1434-1 assume !(1 == ~E_7~0); 34175#L1439-1 assume !(1 == ~E_8~0); 32801#L1444-1 assume !(1 == ~E_9~0); 32802#L1449-1 assume !(1 == ~E_10~0); 33187#L1454-1 assume !(1 == ~E_11~0); 33188#L1459-1 assume !(1 == ~E_12~0); 33722#L1464-1 assume { :end_inline_reset_delta_events } true; 32943#L1810-2 [2023-11-12 02:04:00,204 INFO L750 eck$LassoCheckResult]: Loop: 32943#L1810-2 assume !false; 33393#L1811 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 33491#L1176-1 assume !false; 33873#L999 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 33437#L921 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 32627#L988 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 33927#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 34098#L1003 assume !(0 != eval_~tmp~0#1); 33400#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 33132#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 33133#L1201-3 assume 0 == ~M_E~0;~M_E~0 := 1; 33817#L1201-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 33818#L1206-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 33720#L1211-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 32886#L1216-3 assume !(0 == ~T4_E~0); 32887#L1221-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 33365#L1226-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 32965#L1231-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 32966#L1236-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 33217#L1241-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 34206#L1246-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 34106#L1251-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 33805#L1256-3 assume !(0 == ~T12_E~0); 32906#L1261-3 assume 0 == ~E_M~0;~E_M~0 := 1; 32907#L1266-3 assume 0 == ~E_1~0;~E_1~0 := 1; 32957#L1271-3 assume 0 == ~E_2~0;~E_2~0 := 1; 32958#L1276-3 assume 0 == ~E_3~0;~E_3~0 := 1; 33341#L1281-3 assume 0 == ~E_4~0;~E_4~0 := 1; 33342#L1286-3 assume 0 == ~E_5~0;~E_5~0 := 1; 33860#L1291-3 assume 0 == ~E_6~0;~E_6~0 := 1; 33861#L1296-3 assume !(0 == ~E_7~0); 34278#L1301-3 assume 0 == ~E_8~0;~E_8~0 := 1; 34236#L1306-3 assume 0 == ~E_9~0;~E_9~0 := 1; 33445#L1311-3 assume 0 == ~E_10~0;~E_10~0 := 1; 32826#L1316-3 assume 0 == ~E_11~0;~E_11~0 := 1; 32827#L1321-3 assume 0 == ~E_12~0;~E_12~0 := 1; 32908#L1326-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 33559#L593-42 assume 1 == ~m_pc~0; 33946#L594-14 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 33725#L604-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 33240#is_master_triggered_returnLabel#15 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 33241#L1492-42 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 32720#L1492-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 32721#L612-42 assume 1 == ~t1_pc~0; 33680#L613-14 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 34060#L623-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 34287#is_transmit1_triggered_returnLabel#15 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 32813#L1500-42 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 32814#L1500-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 33522#L631-42 assume 1 == ~t2_pc~0; 32573#L632-14 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 32574#L642-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 33507#is_transmit2_triggered_returnLabel#15 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 33391#L1508-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 33392#L1508-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 32984#L650-42 assume 1 == ~t3_pc~0; 32538#L651-14 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 32539#L661-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 33893#is_transmit3_triggered_returnLabel#15 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 33179#L1516-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 33180#L1516-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 34177#L669-42 assume 1 == ~t4_pc~0; 33459#L670-14 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 32537#L680-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 33962#is_transmit4_triggered_returnLabel#15 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 33871#L1524-42 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 33775#L1524-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 33776#L688-42 assume 1 == ~t5_pc~0; 33858#L689-14 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 34063#L699-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 33571#is_transmit5_triggered_returnLabel#15 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 32748#L1532-42 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 32749#L1532-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 32566#L707-42 assume !(1 == ~t6_pc~0); 32567#L707-44 is_transmit6_triggered_~__retres1~6#1 := 0; 34242#L718-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 32900#is_transmit6_triggered_returnLabel#15 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 32901#L1540-42 assume !(0 != activate_threads_~tmp___5~0#1); 33746#L1540-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 33747#L726-42 assume 1 == ~t7_pc~0; 34013#L727-14 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 34044#L737-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 33598#is_transmit7_triggered_returnLabel#15 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 33449#L1548-42 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 33450#L1548-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 33563#L745-42 assume 1 == ~t8_pc~0; 33601#L746-14 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 33603#L756-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 33766#is_transmit8_triggered_returnLabel#15 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 32554#L1556-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 32555#L1556-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 33300#L764-42 assume 1 == ~t9_pc~0; 33428#L765-14 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 33789#L775-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 33790#is_transmit9_triggered_returnLabel#15 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 32838#L1564-42 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 32839#L1564-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 32899#L783-42 assume !(1 == ~t10_pc~0); 32512#L783-44 is_transmit10_triggered_~__retres1~10#1 := 0; 32511#L794-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 33115#is_transmit10_triggered_returnLabel#15 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 33758#L1572-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 34269#L1572-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 33952#L802-42 assume 1 == ~t11_pc~0; 33046#L803-14 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 32652#L813-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 32653#is_transmit11_triggered_returnLabel#15 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 32599#L1580-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 32600#L1580-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 33797#L821-42 assume !(1 == ~t12_pc~0); 33155#L821-44 is_transmit12_triggered_~__retres1~12#1 := 0; 33156#L832-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 33556#is_transmit12_triggered_returnLabel#15 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 33557#L1588-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 33493#L1588-44 havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 33483#L1339-3 assume 1 == ~M_E~0;~M_E~0 := 2; 33484#L1339-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 33656#L1344-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 33762#L1349-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 33165#L1354-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 33166#L1359-3 assume !(1 == ~T5_E~0); 33772#L1364-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 34263#L1369-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 34173#L1374-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 32986#L1379-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 32987#L1384-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 33163#L1389-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 33164#L1394-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 33379#L1399-3 assume !(1 == ~E_M~0); 34182#L1404-3 assume 1 == ~E_1~0;~E_1~0 := 2; 34150#L1409-3 assume 1 == ~E_2~0;~E_2~0 := 2; 34151#L1414-3 assume 1 == ~E_3~0;~E_3~0 := 2; 34205#L1419-3 assume 1 == ~E_4~0;~E_4~0 := 2; 33955#L1424-3 assume 1 == ~E_5~0;~E_5~0 := 2; 32860#L1429-3 assume 1 == ~E_6~0;~E_6~0 := 2; 32861#L1434-3 assume 1 == ~E_7~0;~E_7~0 := 2; 33771#L1439-3 assume !(1 == ~E_8~0); 32789#L1444-3 assume 1 == ~E_9~0;~E_9~0 := 2; 32790#L1449-3 assume 1 == ~E_10~0;~E_10~0 := 2; 32911#L1454-3 assume 1 == ~E_11~0;~E_11~0 := 2; 33767#L1459-3 assume 1 == ~E_12~0;~E_12~0 := 2; 33768#L1464-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 33410#L921-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 32692#L988-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 32894#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; 32895#L1829 assume !(0 == start_simulation_~tmp~3#1); 32674#L1829-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 32675#L921-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 33489#L988-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 32579#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret33#1;havoc stop_simulation_#t~ret33#1; 32580#L1784 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 33783#L1791 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 34156#stop_simulation_returnLabel#1 start_simulation_#t~ret35#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 32942#L1842 assume !(0 != start_simulation_~tmp___0~1#1); 32943#L1810-2 [2023-11-12 02:04:00,205 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-12 02:04:00,205 INFO L85 PathProgramCache]: Analyzing trace with hash -1345107858, now seen corresponding path program 1 times [2023-11-12 02:04:00,206 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-12 02:04:00,206 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1178293836] [2023-11-12 02:04:00,206 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-12 02:04:00,206 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-12 02:04:00,224 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-12 02:04:00,270 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-12 02:04:00,271 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-12 02:04:00,271 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1178293836] [2023-11-12 02:04:00,271 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1178293836] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-12 02:04:00,271 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-12 02:04:00,272 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-12 02:04:00,272 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [336802558] [2023-11-12 02:04:00,272 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-12 02:04:00,272 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-12 02:04:00,273 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-12 02:04:00,273 INFO L85 PathProgramCache]: Analyzing trace with hash 900687640, now seen corresponding path program 1 times [2023-11-12 02:04:00,273 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-12 02:04:00,273 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [446445541] [2023-11-12 02:04:00,274 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-12 02:04:00,274 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-12 02:04:00,293 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-12 02:04:00,354 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-12 02:04:00,355 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-12 02:04:00,355 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [446445541] [2023-11-12 02:04:00,355 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [446445541] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-12 02:04:00,355 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-12 02:04:00,356 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-12 02:04:00,356 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1170167617] [2023-11-12 02:04:00,356 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-12 02:04:00,356 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-12 02:04:00,357 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-12 02:04:00,357 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-12 02:04:00,357 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-12 02:04:00,358 INFO L87 Difference]: Start difference. First operand 1801 states and 2656 transitions. cyclomatic complexity: 856 Second operand has 3 states, 3 states have (on average 50.0) internal successors, (150), 3 states have internal predecessors, (150), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-12 02:04:00,405 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-12 02:04:00,405 INFO L93 Difference]: Finished difference Result 1801 states and 2655 transitions. [2023-11-12 02:04:00,405 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1801 states and 2655 transitions. [2023-11-12 02:04:00,416 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1638 [2023-11-12 02:04:00,429 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1801 states to 1801 states and 2655 transitions. [2023-11-12 02:04:00,430 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1801 [2023-11-12 02:04:00,432 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1801 [2023-11-12 02:04:00,432 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1801 states and 2655 transitions. [2023-11-12 02:04:00,435 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-12 02:04:00,435 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1801 states and 2655 transitions. [2023-11-12 02:04:00,439 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1801 states and 2655 transitions. [2023-11-12 02:04:00,463 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1801 to 1801. [2023-11-12 02:04:00,467 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1801 states, 1801 states have (on average 1.4741810105496946) internal successors, (2655), 1800 states have internal predecessors, (2655), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-12 02:04:00,474 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1801 states to 1801 states and 2655 transitions. [2023-11-12 02:04:00,474 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1801 states and 2655 transitions. [2023-11-12 02:04:00,474 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-12 02:04:00,475 INFO L428 stractBuchiCegarLoop]: Abstraction has 1801 states and 2655 transitions. [2023-11-12 02:04:00,475 INFO L335 stractBuchiCegarLoop]: ======== Iteration 11 ============ [2023-11-12 02:04:00,475 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1801 states and 2655 transitions. [2023-11-12 02:04:00,483 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1638 [2023-11-12 02:04:00,483 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-12 02:04:00,484 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-12 02:04:00,486 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-12 02:04:00,487 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-12 02:04:00,487 INFO L748 eck$LassoCheckResult]: Stem: 36396#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(20, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~token~0 := 0;~local~0 := 0; 36397#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~14#1;havoc main_~__retres1~14#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1; 37241#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret34#1, start_simulation_#t~ret35#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 37242#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 37828#L848 assume 1 == ~m_i~0;~m_st~0 := 0; 37829#L848-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 36922#L853-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 36711#L858-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 36108#L863-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 36109#L868-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 37353#L873-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 37452#L878-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 37890#L883-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 37891#L888-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 36847#L893-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 36848#L898-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 37379#L903-1 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 37304#L908-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 36884#L1201 assume !(0 == ~M_E~0); 36885#L1201-2 assume 0 == ~T1_E~0;~T1_E~0 := 1; 37737#L1206-1 assume !(0 == ~T2_E~0); 37720#L1211-1 assume !(0 == ~T3_E~0); 37721#L1216-1 assume !(0 == ~T4_E~0); 36692#L1221-1 assume !(0 == ~T5_E~0); 36693#L1226-1 assume !(0 == ~T6_E~0); 36322#L1231-1 assume !(0 == ~T7_E~0); 36323#L1236-1 assume !(0 == ~T8_E~0); 37761#L1241-1 assume 0 == ~T9_E~0;~T9_E~0 := 1; 36732#L1246-1 assume !(0 == ~T10_E~0); 36733#L1251-1 assume !(0 == ~T11_E~0); 36882#L1256-1 assume !(0 == ~T12_E~0); 36117#L1261-1 assume !(0 == ~E_M~0); 36118#L1266-1 assume !(0 == ~E_1~0); 37875#L1271-1 assume !(0 == ~E_2~0); 37436#L1276-1 assume !(0 == ~E_3~0); 37437#L1281-1 assume 0 == ~E_4~0;~E_4~0 := 1; 37391#L1286-1 assume !(0 == ~E_5~0); 36588#L1291-1 assume !(0 == ~E_6~0); 36589#L1296-1 assume !(0 == ~E_7~0); 37177#L1301-1 assume !(0 == ~E_8~0); 37178#L1306-1 assume !(0 == ~E_9~0); 37656#L1311-1 assume !(0 == ~E_10~0); 36539#L1316-1 assume !(0 == ~E_11~0); 36540#L1321-1 assume 0 == ~E_12~0;~E_12~0 := 1; 37196#L1326-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 37197#L593 assume 1 == ~m_pc~0; 37346#L594 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 36421#L604 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 37085#is_master_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 37086#L1492 assume !(0 != activate_threads_~tmp~1#1); 37401#L1492-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 37689#L612 assume !(1 == ~t1_pc~0); 37690#L612-2 is_transmit1_triggered_~__retres1~1#1 := 0; 37824#L623 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 37534#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 36424#L1500 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 36425#L1500-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 36863#L631 assume 1 == ~t2_pc~0; 36790#L632 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 36198#L642 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 36199#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 36553#L1508 assume !(0 != activate_threads_~tmp___1~0#1); 37049#L1508-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 36500#L650 assume !(1 == ~t3_pc~0); 36501#L650-2 is_transmit3_triggered_~__retres1~3#1 := 0; 37219#L661 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 37513#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 36155#L1516 assume !(0 != activate_threads_~tmp___2~0#1); 36156#L1516-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 37372#L669 assume 1 == ~t4_pc~0; 37373#L670 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 37728#L680 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 36238#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 36239#L1524 assume !(0 != activate_threads_~tmp___3~0#1); 36359#L1524-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 36598#L688 assume !(1 == ~t5_pc~0); 36378#L688-2 is_transmit5_triggered_~__retres1~5#1 := 0; 36379#L699 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 37856#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 37261#L1532 assume !(0 != activate_threads_~tmp___4~0#1); 37262#L1532-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 37386#L707 assume 1 == ~t6_pc~0; 37795#L708 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 37018#L718 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 36541#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 36542#L1540 assume !(0 != activate_threads_~tmp___5~0#1); 37332#L1540-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 36883#L726 assume 1 == ~t7_pc~0; 36778#L727 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 36465#L737 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 37525#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 37799#L1548 assume !(0 != activate_threads_~tmp___6~0#1); 36228#L1548-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 36229#L745 assume !(1 == ~t8_pc~0); 36685#L745-2 is_transmit8_triggered_~__retres1~8#1 := 0; 36705#L756 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 37743#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 37094#L1556 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 37095#L1556-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 37613#L764 assume 1 == ~t9_pc~0; 36881#L765 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 36715#L775 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 36614#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 36615#L1564 assume !(0 != activate_threads_~tmp___8~0#1); 36254#L1564-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 36255#L783 assume !(1 == ~t10_pc~0); 36309#L783-2 is_transmit10_triggered_~__retres1~10#1 := 0; 36310#L794 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 36507#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 36837#L1572 assume !(0 != activate_threads_~tmp___9~0#1); 36838#L1572-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 37730#L802 assume 1 == ~t11_pc~0; 37712#L803 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 36195#L813 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 36196#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 36694#L1580 assume !(0 != activate_threads_~tmp___10~0#1); 36695#L1580-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 36812#L821 assume !(1 == ~t12_pc~0); 37063#L821-2 is_transmit12_triggered_~__retres1~12#1 := 0; 37169#L832 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 36202#is_transmit12_triggered_returnLabel#1 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 36203#L1588 assume !(0 != activate_threads_~tmp___11~0#1); 37772#L1588-2 havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 37409#L1339 assume !(1 == ~M_E~0); 37410#L1339-2 assume !(1 == ~T1_E~0); 37802#L1344-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 37803#L1349-1 assume !(1 == ~T3_E~0); 37189#L1354-1 assume !(1 == ~T4_E~0); 37190#L1359-1 assume !(1 == ~T5_E~0); 37589#L1364-1 assume !(1 == ~T6_E~0); 36646#L1369-1 assume !(1 == ~T7_E~0); 36647#L1374-1 assume !(1 == ~T8_E~0); 37192#L1379-1 assume !(1 == ~T9_E~0); 37193#L1384-1 assume 1 == ~T10_E~0;~T10_E~0 := 2; 37301#L1389-1 assume !(1 == ~T11_E~0); 37766#L1394-1 assume !(1 == ~T12_E~0); 37767#L1399-1 assume !(1 == ~E_M~0); 37848#L1404-1 assume !(1 == ~E_1~0); 36739#L1409-1 assume !(1 == ~E_2~0); 36740#L1414-1 assume !(1 == ~E_3~0); 37472#L1419-1 assume !(1 == ~E_4~0); 36368#L1424-1 assume 1 == ~E_5~0;~E_5~0 := 2; 36369#L1429-1 assume !(1 == ~E_6~0); 37204#L1434-1 assume !(1 == ~E_7~0); 37784#L1439-1 assume !(1 == ~E_8~0); 36410#L1444-1 assume !(1 == ~E_9~0); 36411#L1449-1 assume !(1 == ~E_10~0); 36796#L1454-1 assume !(1 == ~E_11~0); 36797#L1459-1 assume !(1 == ~E_12~0); 37331#L1464-1 assume { :end_inline_reset_delta_events } true; 36552#L1810-2 [2023-11-12 02:04:00,488 INFO L750 eck$LassoCheckResult]: Loop: 36552#L1810-2 assume !false; 37002#L1811 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 37100#L1176-1 assume !false; 37482#L999 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 37046#L921 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 36236#L988 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 37536#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 37707#L1003 assume !(0 != eval_~tmp~0#1); 37009#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 36741#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 36742#L1201-3 assume 0 == ~M_E~0;~M_E~0 := 1; 37426#L1201-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 37427#L1206-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 37329#L1211-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 36495#L1216-3 assume !(0 == ~T4_E~0); 36496#L1221-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 36974#L1226-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 36574#L1231-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 36575#L1236-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 36826#L1241-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 37815#L1246-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 37715#L1251-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 37414#L1256-3 assume !(0 == ~T12_E~0); 36515#L1261-3 assume 0 == ~E_M~0;~E_M~0 := 1; 36516#L1266-3 assume 0 == ~E_1~0;~E_1~0 := 1; 36566#L1271-3 assume 0 == ~E_2~0;~E_2~0 := 1; 36567#L1276-3 assume 0 == ~E_3~0;~E_3~0 := 1; 36950#L1281-3 assume 0 == ~E_4~0;~E_4~0 := 1; 36951#L1286-3 assume 0 == ~E_5~0;~E_5~0 := 1; 37469#L1291-3 assume 0 == ~E_6~0;~E_6~0 := 1; 37470#L1296-3 assume !(0 == ~E_7~0); 37887#L1301-3 assume 0 == ~E_8~0;~E_8~0 := 1; 37845#L1306-3 assume 0 == ~E_9~0;~E_9~0 := 1; 37054#L1311-3 assume 0 == ~E_10~0;~E_10~0 := 1; 36435#L1316-3 assume 0 == ~E_11~0;~E_11~0 := 1; 36436#L1321-3 assume 0 == ~E_12~0;~E_12~0 := 1; 36517#L1326-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 37168#L593-42 assume 1 == ~m_pc~0; 37555#L594-14 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 37334#L604-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 36849#is_master_triggered_returnLabel#15 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 36850#L1492-42 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 36329#L1492-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 36330#L612-42 assume !(1 == ~t1_pc~0); 37288#L612-44 is_transmit1_triggered_~__retres1~1#1 := 0; 37669#L623-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 37896#is_transmit1_triggered_returnLabel#15 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 36422#L1500-42 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 36423#L1500-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 37131#L631-42 assume 1 == ~t2_pc~0; 36182#L632-14 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 36183#L642-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 37116#is_transmit2_triggered_returnLabel#15 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 37000#L1508-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 37001#L1508-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 36593#L650-42 assume 1 == ~t3_pc~0; 36147#L651-14 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 36148#L661-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 37502#is_transmit3_triggered_returnLabel#15 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 36788#L1516-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 36789#L1516-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 37786#L669-42 assume !(1 == ~t4_pc~0); 36145#L669-44 is_transmit4_triggered_~__retres1~4#1 := 0; 36146#L680-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 37571#is_transmit4_triggered_returnLabel#15 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 37480#L1524-42 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 37384#L1524-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 37385#L688-42 assume 1 == ~t5_pc~0; 37467#L689-14 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 37672#L699-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 37180#is_transmit5_triggered_returnLabel#15 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 36357#L1532-42 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 36358#L1532-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 36175#L707-42 assume !(1 == ~t6_pc~0); 36176#L707-44 is_transmit6_triggered_~__retres1~6#1 := 0; 37851#L718-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 36509#is_transmit6_triggered_returnLabel#15 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 36510#L1540-42 assume !(0 != activate_threads_~tmp___5~0#1); 37355#L1540-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 37356#L726-42 assume 1 == ~t7_pc~0; 37622#L727-14 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 37653#L737-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 37207#is_transmit7_triggered_returnLabel#15 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 37058#L1548-42 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 37059#L1548-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 37172#L745-42 assume 1 == ~t8_pc~0; 37210#L746-14 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 37212#L756-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 37375#is_transmit8_triggered_returnLabel#15 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 36163#L1556-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 36164#L1556-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 36909#L764-42 assume 1 == ~t9_pc~0; 37037#L765-14 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 37398#L775-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 37399#is_transmit9_triggered_returnLabel#15 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 36447#L1564-42 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 36448#L1564-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 36508#L783-42 assume 1 == ~t10_pc~0; 36119#L784-14 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 36120#L794-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 36724#is_transmit10_triggered_returnLabel#15 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 37367#L1572-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 37878#L1572-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 37561#L802-42 assume !(1 == ~t11_pc~0); 36656#L802-44 is_transmit11_triggered_~__retres1~11#1 := 0; 36261#L813-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 36262#is_transmit11_triggered_returnLabel#15 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 36208#L1580-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 36209#L1580-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 37406#L821-42 assume !(1 == ~t12_pc~0); 36764#L821-44 is_transmit12_triggered_~__retres1~12#1 := 0; 36765#L832-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 37165#is_transmit12_triggered_returnLabel#15 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 37166#L1588-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 37102#L1588-44 havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 37092#L1339-3 assume 1 == ~M_E~0;~M_E~0 := 2; 37093#L1339-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 37265#L1344-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 37371#L1349-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 36774#L1354-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 36775#L1359-3 assume !(1 == ~T5_E~0); 37381#L1364-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 37872#L1369-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 37782#L1374-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 36595#L1379-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 36596#L1384-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 36772#L1389-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 36773#L1394-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 36988#L1399-3 assume !(1 == ~E_M~0); 37791#L1404-3 assume 1 == ~E_1~0;~E_1~0 := 2; 37759#L1409-3 assume 1 == ~E_2~0;~E_2~0 := 2; 37760#L1414-3 assume 1 == ~E_3~0;~E_3~0 := 2; 37814#L1419-3 assume 1 == ~E_4~0;~E_4~0 := 2; 37564#L1424-3 assume 1 == ~E_5~0;~E_5~0 := 2; 36469#L1429-3 assume 1 == ~E_6~0;~E_6~0 := 2; 36470#L1434-3 assume 1 == ~E_7~0;~E_7~0 := 2; 37380#L1439-3 assume !(1 == ~E_8~0); 36398#L1444-3 assume 1 == ~E_9~0;~E_9~0 := 2; 36399#L1449-3 assume 1 == ~E_10~0;~E_10~0 := 2; 36520#L1454-3 assume 1 == ~E_11~0;~E_11~0 := 2; 37376#L1459-3 assume 1 == ~E_12~0;~E_12~0 := 2; 37377#L1464-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 37019#L921-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 36301#L988-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 36503#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; 36504#L1829 assume !(0 == start_simulation_~tmp~3#1); 36283#L1829-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 36284#L921-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 37098#L988-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 36188#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret33#1;havoc stop_simulation_#t~ret33#1; 36189#L1784 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 37392#L1791 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 37765#stop_simulation_returnLabel#1 start_simulation_#t~ret35#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 36551#L1842 assume !(0 != start_simulation_~tmp___0~1#1); 36552#L1810-2 [2023-11-12 02:04:00,489 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-12 02:04:00,489 INFO L85 PathProgramCache]: Analyzing trace with hash -1762996560, now seen corresponding path program 1 times [2023-11-12 02:04:00,489 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-12 02:04:00,489 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2019518048] [2023-11-12 02:04:00,489 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-12 02:04:00,490 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-12 02:04:00,507 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-12 02:04:00,550 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-12 02:04:00,550 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-12 02:04:00,551 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2019518048] [2023-11-12 02:04:00,551 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2019518048] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-12 02:04:00,551 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-12 02:04:00,551 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-12 02:04:00,551 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [429802681] [2023-11-12 02:04:00,551 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-12 02:04:00,552 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-12 02:04:00,552 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-12 02:04:00,552 INFO L85 PathProgramCache]: Analyzing trace with hash 401843482, now seen corresponding path program 1 times [2023-11-12 02:04:00,553 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-12 02:04:00,553 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [621120677] [2023-11-12 02:04:00,553 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-12 02:04:00,553 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-12 02:04:00,572 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-12 02:04:00,630 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-12 02:04:00,630 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-12 02:04:00,631 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [621120677] [2023-11-12 02:04:00,631 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [621120677] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-12 02:04:00,631 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-12 02:04:00,631 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-12 02:04:00,631 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1344164026] [2023-11-12 02:04:00,632 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-12 02:04:00,632 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-12 02:04:00,632 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-12 02:04:00,633 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-12 02:04:00,633 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-12 02:04:00,633 INFO L87 Difference]: Start difference. First operand 1801 states and 2655 transitions. cyclomatic complexity: 855 Second operand has 3 states, 3 states have (on average 50.0) internal successors, (150), 3 states have internal predecessors, (150), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-12 02:04:00,682 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-12 02:04:00,682 INFO L93 Difference]: Finished difference Result 1801 states and 2654 transitions. [2023-11-12 02:04:00,682 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1801 states and 2654 transitions. [2023-11-12 02:04:00,693 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1638 [2023-11-12 02:04:00,707 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1801 states to 1801 states and 2654 transitions. [2023-11-12 02:04:00,707 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1801 [2023-11-12 02:04:00,709 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1801 [2023-11-12 02:04:00,709 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1801 states and 2654 transitions. [2023-11-12 02:04:00,712 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-12 02:04:00,713 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1801 states and 2654 transitions. [2023-11-12 02:04:00,716 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1801 states and 2654 transitions. [2023-11-12 02:04:00,742 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1801 to 1801. [2023-11-12 02:04:00,746 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1801 states, 1801 states have (on average 1.4736257634647418) internal successors, (2654), 1800 states have internal predecessors, (2654), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-12 02:04:00,752 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1801 states to 1801 states and 2654 transitions. [2023-11-12 02:04:00,752 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1801 states and 2654 transitions. [2023-11-12 02:04:00,753 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-12 02:04:00,753 INFO L428 stractBuchiCegarLoop]: Abstraction has 1801 states and 2654 transitions. [2023-11-12 02:04:00,754 INFO L335 stractBuchiCegarLoop]: ======== Iteration 12 ============ [2023-11-12 02:04:00,754 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1801 states and 2654 transitions. [2023-11-12 02:04:00,762 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1638 [2023-11-12 02:04:00,762 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-12 02:04:00,762 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-12 02:04:00,765 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-12 02:04:00,765 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-12 02:04:00,766 INFO L748 eck$LassoCheckResult]: Stem: 40005#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(20, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~token~0 := 0;~local~0 := 0; 40006#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~14#1;havoc main_~__retres1~14#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1; 40850#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret34#1, start_simulation_#t~ret35#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 40851#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 41437#L848 assume 1 == ~m_i~0;~m_st~0 := 0; 41438#L848-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 40531#L853-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 40320#L858-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 39717#L863-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 39718#L868-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 40962#L873-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 41061#L878-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 41499#L883-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 41500#L888-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 40456#L893-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 40457#L898-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 40988#L903-1 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 40913#L908-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 40493#L1201 assume !(0 == ~M_E~0); 40494#L1201-2 assume 0 == ~T1_E~0;~T1_E~0 := 1; 41346#L1206-1 assume !(0 == ~T2_E~0); 41329#L1211-1 assume !(0 == ~T3_E~0); 41330#L1216-1 assume !(0 == ~T4_E~0); 40301#L1221-1 assume !(0 == ~T5_E~0); 40302#L1226-1 assume !(0 == ~T6_E~0); 39931#L1231-1 assume !(0 == ~T7_E~0); 39932#L1236-1 assume !(0 == ~T8_E~0); 41370#L1241-1 assume 0 == ~T9_E~0;~T9_E~0 := 1; 40341#L1246-1 assume !(0 == ~T10_E~0); 40342#L1251-1 assume !(0 == ~T11_E~0); 40491#L1256-1 assume !(0 == ~T12_E~0); 39726#L1261-1 assume !(0 == ~E_M~0); 39727#L1266-1 assume !(0 == ~E_1~0); 41484#L1271-1 assume !(0 == ~E_2~0); 41045#L1276-1 assume !(0 == ~E_3~0); 41046#L1281-1 assume 0 == ~E_4~0;~E_4~0 := 1; 41000#L1286-1 assume !(0 == ~E_5~0); 40197#L1291-1 assume !(0 == ~E_6~0); 40198#L1296-1 assume !(0 == ~E_7~0); 40786#L1301-1 assume !(0 == ~E_8~0); 40787#L1306-1 assume !(0 == ~E_9~0); 41265#L1311-1 assume !(0 == ~E_10~0); 40148#L1316-1 assume !(0 == ~E_11~0); 40149#L1321-1 assume 0 == ~E_12~0;~E_12~0 := 1; 40805#L1326-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 40806#L593 assume 1 == ~m_pc~0; 40955#L594 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 40030#L604 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 40694#is_master_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 40695#L1492 assume !(0 != activate_threads_~tmp~1#1); 41010#L1492-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 41298#L612 assume !(1 == ~t1_pc~0); 41299#L612-2 is_transmit1_triggered_~__retres1~1#1 := 0; 41433#L623 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 41143#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 40033#L1500 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 40034#L1500-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 40472#L631 assume 1 == ~t2_pc~0; 40399#L632 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 39807#L642 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 39808#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 40162#L1508 assume !(0 != activate_threads_~tmp___1~0#1); 40658#L1508-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 40109#L650 assume !(1 == ~t3_pc~0); 40110#L650-2 is_transmit3_triggered_~__retres1~3#1 := 0; 40828#L661 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 41122#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 39764#L1516 assume !(0 != activate_threads_~tmp___2~0#1); 39765#L1516-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 40981#L669 assume 1 == ~t4_pc~0; 40982#L670 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 41337#L680 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 39847#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 39848#L1524 assume !(0 != activate_threads_~tmp___3~0#1); 39968#L1524-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 40207#L688 assume !(1 == ~t5_pc~0); 39987#L688-2 is_transmit5_triggered_~__retres1~5#1 := 0; 39988#L699 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 41465#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 40870#L1532 assume !(0 != activate_threads_~tmp___4~0#1); 40871#L1532-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 40995#L707 assume 1 == ~t6_pc~0; 41404#L708 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 40627#L718 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 40150#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 40151#L1540 assume !(0 != activate_threads_~tmp___5~0#1); 40941#L1540-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 40492#L726 assume 1 == ~t7_pc~0; 40387#L727 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 40074#L737 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 41134#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 41408#L1548 assume !(0 != activate_threads_~tmp___6~0#1); 39837#L1548-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 39838#L745 assume !(1 == ~t8_pc~0); 40294#L745-2 is_transmit8_triggered_~__retres1~8#1 := 0; 40314#L756 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 41352#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 40703#L1556 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 40704#L1556-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 41222#L764 assume 1 == ~t9_pc~0; 40490#L765 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 40324#L775 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 40223#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 40224#L1564 assume !(0 != activate_threads_~tmp___8~0#1); 39863#L1564-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 39864#L783 assume !(1 == ~t10_pc~0); 39918#L783-2 is_transmit10_triggered_~__retres1~10#1 := 0; 39919#L794 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 40116#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 40446#L1572 assume !(0 != activate_threads_~tmp___9~0#1); 40447#L1572-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 41339#L802 assume 1 == ~t11_pc~0; 41321#L803 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 39804#L813 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 39805#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 40303#L1580 assume !(0 != activate_threads_~tmp___10~0#1); 40304#L1580-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 40421#L821 assume !(1 == ~t12_pc~0); 40672#L821-2 is_transmit12_triggered_~__retres1~12#1 := 0; 40778#L832 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 39811#is_transmit12_triggered_returnLabel#1 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 39812#L1588 assume !(0 != activate_threads_~tmp___11~0#1); 41381#L1588-2 havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 41018#L1339 assume !(1 == ~M_E~0); 41019#L1339-2 assume !(1 == ~T1_E~0); 41411#L1344-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 41412#L1349-1 assume !(1 == ~T3_E~0); 40798#L1354-1 assume !(1 == ~T4_E~0); 40799#L1359-1 assume !(1 == ~T5_E~0); 41198#L1364-1 assume !(1 == ~T6_E~0); 40255#L1369-1 assume !(1 == ~T7_E~0); 40256#L1374-1 assume !(1 == ~T8_E~0); 40801#L1379-1 assume !(1 == ~T9_E~0); 40802#L1384-1 assume 1 == ~T10_E~0;~T10_E~0 := 2; 40910#L1389-1 assume !(1 == ~T11_E~0); 41375#L1394-1 assume !(1 == ~T12_E~0); 41376#L1399-1 assume !(1 == ~E_M~0); 41457#L1404-1 assume !(1 == ~E_1~0); 40348#L1409-1 assume !(1 == ~E_2~0); 40349#L1414-1 assume !(1 == ~E_3~0); 41081#L1419-1 assume !(1 == ~E_4~0); 39977#L1424-1 assume 1 == ~E_5~0;~E_5~0 := 2; 39978#L1429-1 assume !(1 == ~E_6~0); 40813#L1434-1 assume !(1 == ~E_7~0); 41393#L1439-1 assume !(1 == ~E_8~0); 40019#L1444-1 assume !(1 == ~E_9~0); 40020#L1449-1 assume !(1 == ~E_10~0); 40405#L1454-1 assume !(1 == ~E_11~0); 40406#L1459-1 assume !(1 == ~E_12~0); 40940#L1464-1 assume { :end_inline_reset_delta_events } true; 40161#L1810-2 [2023-11-12 02:04:00,767 INFO L750 eck$LassoCheckResult]: Loop: 40161#L1810-2 assume !false; 40611#L1811 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 40709#L1176-1 assume !false; 41091#L999 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 40655#L921 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 39845#L988 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 41145#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 41316#L1003 assume !(0 != eval_~tmp~0#1); 40618#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 40350#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 40351#L1201-3 assume 0 == ~M_E~0;~M_E~0 := 1; 41035#L1201-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 41036#L1206-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 40938#L1211-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 40104#L1216-3 assume !(0 == ~T4_E~0); 40105#L1221-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 40583#L1226-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 40183#L1231-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 40184#L1236-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 40435#L1241-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 41424#L1246-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 41324#L1251-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 41023#L1256-3 assume !(0 == ~T12_E~0); 40124#L1261-3 assume 0 == ~E_M~0;~E_M~0 := 1; 40125#L1266-3 assume 0 == ~E_1~0;~E_1~0 := 1; 40175#L1271-3 assume 0 == ~E_2~0;~E_2~0 := 1; 40176#L1276-3 assume 0 == ~E_3~0;~E_3~0 := 1; 40559#L1281-3 assume 0 == ~E_4~0;~E_4~0 := 1; 40560#L1286-3 assume 0 == ~E_5~0;~E_5~0 := 1; 41078#L1291-3 assume 0 == ~E_6~0;~E_6~0 := 1; 41079#L1296-3 assume !(0 == ~E_7~0); 41496#L1301-3 assume 0 == ~E_8~0;~E_8~0 := 1; 41454#L1306-3 assume 0 == ~E_9~0;~E_9~0 := 1; 40663#L1311-3 assume 0 == ~E_10~0;~E_10~0 := 1; 40044#L1316-3 assume 0 == ~E_11~0;~E_11~0 := 1; 40045#L1321-3 assume 0 == ~E_12~0;~E_12~0 := 1; 40126#L1326-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 40777#L593-42 assume 1 == ~m_pc~0; 41164#L594-14 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 40943#L604-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 40458#is_master_triggered_returnLabel#15 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 40459#L1492-42 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 39938#L1492-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 39939#L612-42 assume !(1 == ~t1_pc~0); 40897#L612-44 is_transmit1_triggered_~__retres1~1#1 := 0; 41278#L623-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 41505#is_transmit1_triggered_returnLabel#15 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 40031#L1500-42 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 40032#L1500-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 40740#L631-42 assume !(1 == ~t2_pc~0); 39793#L631-44 is_transmit2_triggered_~__retres1~2#1 := 0; 39792#L642-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 40725#is_transmit2_triggered_returnLabel#15 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 40609#L1508-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 40610#L1508-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 40202#L650-42 assume 1 == ~t3_pc~0; 39756#L651-14 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 39757#L661-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 41111#is_transmit3_triggered_returnLabel#15 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 40397#L1516-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 40398#L1516-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 41395#L669-42 assume 1 == ~t4_pc~0; 40677#L670-14 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 39755#L680-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 41180#is_transmit4_triggered_returnLabel#15 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 41089#L1524-42 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 40993#L1524-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 40994#L688-42 assume 1 == ~t5_pc~0; 41076#L689-14 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 41281#L699-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 40789#is_transmit5_triggered_returnLabel#15 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 39966#L1532-42 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 39967#L1532-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 39784#L707-42 assume !(1 == ~t6_pc~0); 39785#L707-44 is_transmit6_triggered_~__retres1~6#1 := 0; 41460#L718-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 40118#is_transmit6_triggered_returnLabel#15 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 40119#L1540-42 assume !(0 != activate_threads_~tmp___5~0#1); 40964#L1540-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 40965#L726-42 assume !(1 == ~t7_pc~0); 41232#L726-44 is_transmit7_triggered_~__retres1~7#1 := 0; 41262#L737-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 40816#is_transmit7_triggered_returnLabel#15 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 40667#L1548-42 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 40668#L1548-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 40781#L745-42 assume 1 == ~t8_pc~0; 40819#L746-14 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 40821#L756-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 40984#is_transmit8_triggered_returnLabel#15 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 39772#L1556-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 39773#L1556-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 40518#L764-42 assume 1 == ~t9_pc~0; 40646#L765-14 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 41007#L775-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 41008#is_transmit9_triggered_returnLabel#15 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 40056#L1564-42 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 40057#L1564-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 40117#L783-42 assume 1 == ~t10_pc~0; 39728#L784-14 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 39729#L794-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 40333#is_transmit10_triggered_returnLabel#15 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 40976#L1572-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 41487#L1572-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 41170#L802-42 assume 1 == ~t11_pc~0; 40264#L803-14 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 39870#L813-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 39871#is_transmit11_triggered_returnLabel#15 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 39817#L1580-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 39818#L1580-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 41015#L821-42 assume !(1 == ~t12_pc~0); 40373#L821-44 is_transmit12_triggered_~__retres1~12#1 := 0; 40374#L832-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 40774#is_transmit12_triggered_returnLabel#15 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 40775#L1588-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 40711#L1588-44 havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 40701#L1339-3 assume 1 == ~M_E~0;~M_E~0 := 2; 40702#L1339-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 40874#L1344-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 40980#L1349-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 40383#L1354-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 40384#L1359-3 assume !(1 == ~T5_E~0); 40990#L1364-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 41481#L1369-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 41391#L1374-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 40204#L1379-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 40205#L1384-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 40381#L1389-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 40382#L1394-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 40597#L1399-3 assume !(1 == ~E_M~0); 41400#L1404-3 assume 1 == ~E_1~0;~E_1~0 := 2; 41368#L1409-3 assume 1 == ~E_2~0;~E_2~0 := 2; 41369#L1414-3 assume 1 == ~E_3~0;~E_3~0 := 2; 41423#L1419-3 assume 1 == ~E_4~0;~E_4~0 := 2; 41173#L1424-3 assume 1 == ~E_5~0;~E_5~0 := 2; 40078#L1429-3 assume 1 == ~E_6~0;~E_6~0 := 2; 40079#L1434-3 assume 1 == ~E_7~0;~E_7~0 := 2; 40989#L1439-3 assume !(1 == ~E_8~0); 40007#L1444-3 assume 1 == ~E_9~0;~E_9~0 := 2; 40008#L1449-3 assume 1 == ~E_10~0;~E_10~0 := 2; 40129#L1454-3 assume 1 == ~E_11~0;~E_11~0 := 2; 40985#L1459-3 assume 1 == ~E_12~0;~E_12~0 := 2; 40986#L1464-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 40628#L921-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 39910#L988-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 40112#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; 40113#L1829 assume !(0 == start_simulation_~tmp~3#1); 39892#L1829-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 39893#L921-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 40707#L988-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 39797#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret33#1;havoc stop_simulation_#t~ret33#1; 39798#L1784 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 41001#L1791 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 41374#stop_simulation_returnLabel#1 start_simulation_#t~ret35#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 40160#L1842 assume !(0 != start_simulation_~tmp___0~1#1); 40161#L1810-2 [2023-11-12 02:04:00,767 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-12 02:04:00,768 INFO L85 PathProgramCache]: Analyzing trace with hash 1133017134, now seen corresponding path program 1 times [2023-11-12 02:04:00,768 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-12 02:04:00,768 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2051558824] [2023-11-12 02:04:00,768 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-12 02:04:00,769 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-12 02:04:00,785 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-12 02:04:00,828 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-12 02:04:00,828 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-12 02:04:00,828 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2051558824] [2023-11-12 02:04:00,829 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2051558824] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-12 02:04:00,829 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-12 02:04:00,829 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-12 02:04:00,829 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1724217492] [2023-11-12 02:04:00,829 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-12 02:04:00,830 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-12 02:04:00,830 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-12 02:04:00,830 INFO L85 PathProgramCache]: Analyzing trace with hash 1814059162, now seen corresponding path program 1 times [2023-11-12 02:04:00,831 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-12 02:04:00,831 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [261079371] [2023-11-12 02:04:00,831 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-12 02:04:00,831 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-12 02:04:00,849 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-12 02:04:00,940 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-12 02:04:00,940 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-12 02:04:00,940 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [261079371] [2023-11-12 02:04:00,941 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [261079371] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-12 02:04:00,941 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-12 02:04:00,941 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-12 02:04:00,941 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2044567335] [2023-11-12 02:04:00,941 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-12 02:04:00,942 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-12 02:04:00,942 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-12 02:04:00,942 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-12 02:04:00,942 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-12 02:04:00,943 INFO L87 Difference]: Start difference. First operand 1801 states and 2654 transitions. cyclomatic complexity: 854 Second operand has 3 states, 3 states have (on average 50.0) internal successors, (150), 3 states have internal predecessors, (150), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-12 02:04:00,989 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-12 02:04:00,989 INFO L93 Difference]: Finished difference Result 1801 states and 2653 transitions. [2023-11-12 02:04:00,989 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1801 states and 2653 transitions. [2023-11-12 02:04:01,001 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1638 [2023-11-12 02:04:01,012 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1801 states to 1801 states and 2653 transitions. [2023-11-12 02:04:01,012 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1801 [2023-11-12 02:04:01,015 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1801 [2023-11-12 02:04:01,015 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1801 states and 2653 transitions. [2023-11-12 02:04:01,018 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-12 02:04:01,018 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1801 states and 2653 transitions. [2023-11-12 02:04:01,022 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1801 states and 2653 transitions. [2023-11-12 02:04:01,048 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1801 to 1801. [2023-11-12 02:04:01,051 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1801 states, 1801 states have (on average 1.473070516379789) internal successors, (2653), 1800 states have internal predecessors, (2653), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-12 02:04:01,058 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1801 states to 1801 states and 2653 transitions. [2023-11-12 02:04:01,058 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1801 states and 2653 transitions. [2023-11-12 02:04:01,059 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-12 02:04:01,059 INFO L428 stractBuchiCegarLoop]: Abstraction has 1801 states and 2653 transitions. [2023-11-12 02:04:01,059 INFO L335 stractBuchiCegarLoop]: ======== Iteration 13 ============ [2023-11-12 02:04:01,060 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1801 states and 2653 transitions. [2023-11-12 02:04:01,068 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1638 [2023-11-12 02:04:01,068 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-12 02:04:01,068 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-12 02:04:01,071 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-12 02:04:01,071 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-12 02:04:01,072 INFO L748 eck$LassoCheckResult]: Stem: 43614#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(20, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~token~0 := 0;~local~0 := 0; 43615#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~14#1;havoc main_~__retres1~14#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1; 44459#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret34#1, start_simulation_#t~ret35#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 44460#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 45046#L848 assume 1 == ~m_i~0;~m_st~0 := 0; 45047#L848-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 44140#L853-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 43929#L858-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 43326#L863-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 43327#L868-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 44571#L873-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 44670#L878-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 45108#L883-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 45109#L888-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 44065#L893-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 44066#L898-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 44597#L903-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 44522#L908-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 44102#L1201 assume !(0 == ~M_E~0); 44103#L1201-2 assume 0 == ~T1_E~0;~T1_E~0 := 1; 44955#L1206-1 assume !(0 == ~T2_E~0); 44938#L1211-1 assume !(0 == ~T3_E~0); 44939#L1216-1 assume !(0 == ~T4_E~0); 43910#L1221-1 assume !(0 == ~T5_E~0); 43911#L1226-1 assume !(0 == ~T6_E~0); 43540#L1231-1 assume !(0 == ~T7_E~0); 43541#L1236-1 assume !(0 == ~T8_E~0); 44979#L1241-1 assume 0 == ~T9_E~0;~T9_E~0 := 1; 43950#L1246-1 assume !(0 == ~T10_E~0); 43951#L1251-1 assume !(0 == ~T11_E~0); 44100#L1256-1 assume !(0 == ~T12_E~0); 43335#L1261-1 assume !(0 == ~E_M~0); 43336#L1266-1 assume !(0 == ~E_1~0); 45093#L1271-1 assume !(0 == ~E_2~0); 44654#L1276-1 assume !(0 == ~E_3~0); 44655#L1281-1 assume 0 == ~E_4~0;~E_4~0 := 1; 44609#L1286-1 assume !(0 == ~E_5~0); 43806#L1291-1 assume !(0 == ~E_6~0); 43807#L1296-1 assume !(0 == ~E_7~0); 44395#L1301-1 assume !(0 == ~E_8~0); 44396#L1306-1 assume !(0 == ~E_9~0); 44874#L1311-1 assume !(0 == ~E_10~0); 43757#L1316-1 assume !(0 == ~E_11~0); 43758#L1321-1 assume 0 == ~E_12~0;~E_12~0 := 1; 44414#L1326-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 44415#L593 assume 1 == ~m_pc~0; 44564#L594 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 43639#L604 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 44303#is_master_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 44304#L1492 assume !(0 != activate_threads_~tmp~1#1); 44619#L1492-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 44907#L612 assume !(1 == ~t1_pc~0); 44908#L612-2 is_transmit1_triggered_~__retres1~1#1 := 0; 45042#L623 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 44752#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 43642#L1500 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 43643#L1500-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 44081#L631 assume 1 == ~t2_pc~0; 44008#L632 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 43416#L642 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 43417#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 43771#L1508 assume !(0 != activate_threads_~tmp___1~0#1); 44267#L1508-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 43718#L650 assume !(1 == ~t3_pc~0); 43719#L650-2 is_transmit3_triggered_~__retres1~3#1 := 0; 44437#L661 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 44731#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 43373#L1516 assume !(0 != activate_threads_~tmp___2~0#1); 43374#L1516-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 44590#L669 assume 1 == ~t4_pc~0; 44591#L670 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 44946#L680 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 43456#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 43457#L1524 assume !(0 != activate_threads_~tmp___3~0#1); 43577#L1524-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 43816#L688 assume !(1 == ~t5_pc~0); 43596#L688-2 is_transmit5_triggered_~__retres1~5#1 := 0; 43597#L699 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 45074#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 44479#L1532 assume !(0 != activate_threads_~tmp___4~0#1); 44480#L1532-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 44604#L707 assume 1 == ~t6_pc~0; 45013#L708 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 44236#L718 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 43759#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 43760#L1540 assume !(0 != activate_threads_~tmp___5~0#1); 44550#L1540-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 44101#L726 assume 1 == ~t7_pc~0; 43996#L727 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 43683#L737 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 44743#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 45017#L1548 assume !(0 != activate_threads_~tmp___6~0#1); 43446#L1548-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 43447#L745 assume !(1 == ~t8_pc~0); 43903#L745-2 is_transmit8_triggered_~__retres1~8#1 := 0; 43923#L756 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 44961#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 44312#L1556 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 44313#L1556-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 44831#L764 assume 1 == ~t9_pc~0; 44099#L765 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 43933#L775 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 43832#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 43833#L1564 assume !(0 != activate_threads_~tmp___8~0#1); 43472#L1564-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 43473#L783 assume !(1 == ~t10_pc~0); 43527#L783-2 is_transmit10_triggered_~__retres1~10#1 := 0; 43528#L794 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 43725#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 44055#L1572 assume !(0 != activate_threads_~tmp___9~0#1); 44056#L1572-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 44948#L802 assume 1 == ~t11_pc~0; 44930#L803 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 43413#L813 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 43414#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 43912#L1580 assume !(0 != activate_threads_~tmp___10~0#1); 43913#L1580-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 44030#L821 assume !(1 == ~t12_pc~0); 44281#L821-2 is_transmit12_triggered_~__retres1~12#1 := 0; 44387#L832 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 43420#is_transmit12_triggered_returnLabel#1 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 43421#L1588 assume !(0 != activate_threads_~tmp___11~0#1); 44990#L1588-2 havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 44627#L1339 assume !(1 == ~M_E~0); 44628#L1339-2 assume !(1 == ~T1_E~0); 45020#L1344-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 45021#L1349-1 assume !(1 == ~T3_E~0); 44407#L1354-1 assume !(1 == ~T4_E~0); 44408#L1359-1 assume !(1 == ~T5_E~0); 44807#L1364-1 assume !(1 == ~T6_E~0); 43864#L1369-1 assume !(1 == ~T7_E~0); 43865#L1374-1 assume !(1 == ~T8_E~0); 44410#L1379-1 assume !(1 == ~T9_E~0); 44411#L1384-1 assume 1 == ~T10_E~0;~T10_E~0 := 2; 44519#L1389-1 assume !(1 == ~T11_E~0); 44984#L1394-1 assume !(1 == ~T12_E~0); 44985#L1399-1 assume !(1 == ~E_M~0); 45066#L1404-1 assume !(1 == ~E_1~0); 43957#L1409-1 assume !(1 == ~E_2~0); 43958#L1414-1 assume !(1 == ~E_3~0); 44690#L1419-1 assume !(1 == ~E_4~0); 43586#L1424-1 assume 1 == ~E_5~0;~E_5~0 := 2; 43587#L1429-1 assume !(1 == ~E_6~0); 44422#L1434-1 assume !(1 == ~E_7~0); 45002#L1439-1 assume !(1 == ~E_8~0); 43628#L1444-1 assume !(1 == ~E_9~0); 43629#L1449-1 assume !(1 == ~E_10~0); 44014#L1454-1 assume !(1 == ~E_11~0); 44015#L1459-1 assume !(1 == ~E_12~0); 44549#L1464-1 assume { :end_inline_reset_delta_events } true; 43770#L1810-2 [2023-11-12 02:04:01,073 INFO L750 eck$LassoCheckResult]: Loop: 43770#L1810-2 assume !false; 44220#L1811 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 44318#L1176-1 assume !false; 44700#L999 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 44264#L921 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 43454#L988 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 44754#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 44925#L1003 assume !(0 != eval_~tmp~0#1); 44227#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 43959#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 43960#L1201-3 assume 0 == ~M_E~0;~M_E~0 := 1; 44644#L1201-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 44645#L1206-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 44547#L1211-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 43713#L1216-3 assume !(0 == ~T4_E~0); 43714#L1221-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 44192#L1226-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 43792#L1231-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 43793#L1236-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 44044#L1241-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 45033#L1246-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 44933#L1251-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 44632#L1256-3 assume !(0 == ~T12_E~0); 43733#L1261-3 assume 0 == ~E_M~0;~E_M~0 := 1; 43734#L1266-3 assume 0 == ~E_1~0;~E_1~0 := 1; 43784#L1271-3 assume 0 == ~E_2~0;~E_2~0 := 1; 43785#L1276-3 assume 0 == ~E_3~0;~E_3~0 := 1; 44168#L1281-3 assume 0 == ~E_4~0;~E_4~0 := 1; 44169#L1286-3 assume 0 == ~E_5~0;~E_5~0 := 1; 44687#L1291-3 assume 0 == ~E_6~0;~E_6~0 := 1; 44688#L1296-3 assume !(0 == ~E_7~0); 45105#L1301-3 assume 0 == ~E_8~0;~E_8~0 := 1; 45063#L1306-3 assume 0 == ~E_9~0;~E_9~0 := 1; 44272#L1311-3 assume 0 == ~E_10~0;~E_10~0 := 1; 43653#L1316-3 assume 0 == ~E_11~0;~E_11~0 := 1; 43654#L1321-3 assume 0 == ~E_12~0;~E_12~0 := 1; 43735#L1326-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 44386#L593-42 assume 1 == ~m_pc~0; 44773#L594-14 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 44552#L604-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 44067#is_master_triggered_returnLabel#15 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 44068#L1492-42 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 43547#L1492-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 43548#L612-42 assume !(1 == ~t1_pc~0); 44506#L612-44 is_transmit1_triggered_~__retres1~1#1 := 0; 44887#L623-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 45114#is_transmit1_triggered_returnLabel#15 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 43640#L1500-42 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 43641#L1500-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 44349#L631-42 assume 1 == ~t2_pc~0; 43400#L632-14 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 43401#L642-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 44334#is_transmit2_triggered_returnLabel#15 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 44218#L1508-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 44219#L1508-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 43811#L650-42 assume 1 == ~t3_pc~0; 43365#L651-14 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 43366#L661-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 44720#is_transmit3_triggered_returnLabel#15 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 44006#L1516-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 44007#L1516-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 45004#L669-42 assume !(1 == ~t4_pc~0); 43363#L669-44 is_transmit4_triggered_~__retres1~4#1 := 0; 43364#L680-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 44789#is_transmit4_triggered_returnLabel#15 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 44698#L1524-42 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 44602#L1524-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 44603#L688-42 assume 1 == ~t5_pc~0; 44685#L689-14 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 44890#L699-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 44398#is_transmit5_triggered_returnLabel#15 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 43575#L1532-42 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 43576#L1532-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 43393#L707-42 assume !(1 == ~t6_pc~0); 43394#L707-44 is_transmit6_triggered_~__retres1~6#1 := 0; 45069#L718-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 43727#is_transmit6_triggered_returnLabel#15 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 43728#L1540-42 assume !(0 != activate_threads_~tmp___5~0#1); 44573#L1540-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 44574#L726-42 assume 1 == ~t7_pc~0; 44840#L727-14 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 44871#L737-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 44425#is_transmit7_triggered_returnLabel#15 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 44276#L1548-42 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 44277#L1548-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 44390#L745-42 assume 1 == ~t8_pc~0; 44428#L746-14 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 44430#L756-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 44593#is_transmit8_triggered_returnLabel#15 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 43381#L1556-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 43382#L1556-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 44127#L764-42 assume !(1 == ~t9_pc~0); 44256#L764-44 is_transmit9_triggered_~__retres1~9#1 := 0; 44616#L775-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 44617#is_transmit9_triggered_returnLabel#15 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 43665#L1564-42 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 43666#L1564-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 43726#L783-42 assume 1 == ~t10_pc~0; 43337#L784-14 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 43338#L794-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 43942#is_transmit10_triggered_returnLabel#15 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 44585#L1572-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 45096#L1572-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 44779#L802-42 assume 1 == ~t11_pc~0; 43873#L803-14 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 43479#L813-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 43480#is_transmit11_triggered_returnLabel#15 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 43426#L1580-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 43427#L1580-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 44624#L821-42 assume 1 == ~t12_pc~0; 44625#L822-14 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 43983#L832-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 44383#is_transmit12_triggered_returnLabel#15 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 44384#L1588-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 44320#L1588-44 havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 44310#L1339-3 assume 1 == ~M_E~0;~M_E~0 := 2; 44311#L1339-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 44483#L1344-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 44589#L1349-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 43992#L1354-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 43993#L1359-3 assume !(1 == ~T5_E~0); 44599#L1364-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 45090#L1369-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 45000#L1374-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 43813#L1379-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 43814#L1384-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 43990#L1389-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 43991#L1394-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 44206#L1399-3 assume !(1 == ~E_M~0); 45009#L1404-3 assume 1 == ~E_1~0;~E_1~0 := 2; 44977#L1409-3 assume 1 == ~E_2~0;~E_2~0 := 2; 44978#L1414-3 assume 1 == ~E_3~0;~E_3~0 := 2; 45032#L1419-3 assume 1 == ~E_4~0;~E_4~0 := 2; 44782#L1424-3 assume 1 == ~E_5~0;~E_5~0 := 2; 43687#L1429-3 assume 1 == ~E_6~0;~E_6~0 := 2; 43688#L1434-3 assume 1 == ~E_7~0;~E_7~0 := 2; 44598#L1439-3 assume !(1 == ~E_8~0); 43616#L1444-3 assume 1 == ~E_9~0;~E_9~0 := 2; 43617#L1449-3 assume 1 == ~E_10~0;~E_10~0 := 2; 43738#L1454-3 assume 1 == ~E_11~0;~E_11~0 := 2; 44594#L1459-3 assume 1 == ~E_12~0;~E_12~0 := 2; 44595#L1464-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 44237#L921-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 43519#L988-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 43721#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; 43722#L1829 assume !(0 == start_simulation_~tmp~3#1); 43501#L1829-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 43502#L921-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 44316#L988-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 43406#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret33#1;havoc stop_simulation_#t~ret33#1; 43407#L1784 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 44610#L1791 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 44983#stop_simulation_returnLabel#1 start_simulation_#t~ret35#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 43769#L1842 assume !(0 != start_simulation_~tmp___0~1#1); 43770#L1810-2 [2023-11-12 02:04:01,073 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-12 02:04:01,074 INFO L85 PathProgramCache]: Analyzing trace with hash -1544509712, now seen corresponding path program 1 times [2023-11-12 02:04:01,074 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-12 02:04:01,074 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1352786722] [2023-11-12 02:04:01,074 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-12 02:04:01,074 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-12 02:04:01,093 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-12 02:04:01,155 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-12 02:04:01,155 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-12 02:04:01,155 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1352786722] [2023-11-12 02:04:01,156 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1352786722] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-12 02:04:01,156 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-12 02:04:01,156 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2023-11-12 02:04:01,156 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [648623045] [2023-11-12 02:04:01,156 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-12 02:04:01,157 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-12 02:04:01,157 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-12 02:04:01,157 INFO L85 PathProgramCache]: Analyzing trace with hash -341876263, now seen corresponding path program 1 times [2023-11-12 02:04:01,158 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-12 02:04:01,158 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1435850489] [2023-11-12 02:04:01,158 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-12 02:04:01,158 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-12 02:04:01,176 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-12 02:04:01,235 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-12 02:04:01,235 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-12 02:04:01,235 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1435850489] [2023-11-12 02:04:01,236 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1435850489] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-12 02:04:01,236 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-12 02:04:01,236 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-12 02:04:01,236 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2097648497] [2023-11-12 02:04:01,236 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-12 02:04:01,237 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-12 02:04:01,237 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-12 02:04:01,237 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-12 02:04:01,238 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-12 02:04:01,238 INFO L87 Difference]: Start difference. First operand 1801 states and 2653 transitions. cyclomatic complexity: 853 Second operand has 3 states, 3 states have (on average 50.0) internal successors, (150), 2 states have internal predecessors, (150), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-12 02:04:01,301 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-12 02:04:01,301 INFO L93 Difference]: Finished difference Result 1801 states and 2648 transitions. [2023-11-12 02:04:01,301 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1801 states and 2648 transitions. [2023-11-12 02:04:01,312 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1638 [2023-11-12 02:04:01,323 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1801 states to 1801 states and 2648 transitions. [2023-11-12 02:04:01,323 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1801 [2023-11-12 02:04:01,325 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1801 [2023-11-12 02:04:01,325 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1801 states and 2648 transitions. [2023-11-12 02:04:01,328 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-12 02:04:01,328 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1801 states and 2648 transitions. [2023-11-12 02:04:01,332 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1801 states and 2648 transitions. [2023-11-12 02:04:01,356 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1801 to 1801. [2023-11-12 02:04:01,359 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1801 states, 1801 states have (on average 1.470294280955025) internal successors, (2648), 1800 states have internal predecessors, (2648), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-12 02:04:01,365 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1801 states to 1801 states and 2648 transitions. [2023-11-12 02:04:01,366 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1801 states and 2648 transitions. [2023-11-12 02:04:01,366 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-12 02:04:01,367 INFO L428 stractBuchiCegarLoop]: Abstraction has 1801 states and 2648 transitions. [2023-11-12 02:04:01,367 INFO L335 stractBuchiCegarLoop]: ======== Iteration 14 ============ [2023-11-12 02:04:01,367 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1801 states and 2648 transitions. [2023-11-12 02:04:01,375 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1638 [2023-11-12 02:04:01,376 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-12 02:04:01,376 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-12 02:04:01,378 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-12 02:04:01,379 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-12 02:04:01,379 INFO L748 eck$LassoCheckResult]: Stem: 47223#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(20, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~token~0 := 0;~local~0 := 0; 47224#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~14#1;havoc main_~__retres1~14#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1; 48068#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret34#1, start_simulation_#t~ret35#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 48069#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 48655#L848 assume 1 == ~m_i~0;~m_st~0 := 0; 48656#L848-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 47749#L853-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 47538#L858-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 46935#L863-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 46936#L868-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 48180#L873-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 48279#L878-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 48717#L883-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 48718#L888-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 47674#L893-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 47675#L898-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 48206#L903-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 48131#L908-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 47711#L1201 assume !(0 == ~M_E~0); 47712#L1201-2 assume !(0 == ~T1_E~0); 48564#L1206-1 assume !(0 == ~T2_E~0); 48547#L1211-1 assume !(0 == ~T3_E~0); 48548#L1216-1 assume !(0 == ~T4_E~0); 47519#L1221-1 assume !(0 == ~T5_E~0); 47520#L1226-1 assume !(0 == ~T6_E~0); 47149#L1231-1 assume !(0 == ~T7_E~0); 47150#L1236-1 assume !(0 == ~T8_E~0); 48588#L1241-1 assume 0 == ~T9_E~0;~T9_E~0 := 1; 47559#L1246-1 assume !(0 == ~T10_E~0); 47560#L1251-1 assume !(0 == ~T11_E~0); 47709#L1256-1 assume !(0 == ~T12_E~0); 46944#L1261-1 assume !(0 == ~E_M~0); 46945#L1266-1 assume !(0 == ~E_1~0); 48702#L1271-1 assume !(0 == ~E_2~0); 48263#L1276-1 assume !(0 == ~E_3~0); 48264#L1281-1 assume 0 == ~E_4~0;~E_4~0 := 1; 48218#L1286-1 assume !(0 == ~E_5~0); 47415#L1291-1 assume !(0 == ~E_6~0); 47416#L1296-1 assume !(0 == ~E_7~0); 48004#L1301-1 assume !(0 == ~E_8~0); 48005#L1306-1 assume !(0 == ~E_9~0); 48483#L1311-1 assume !(0 == ~E_10~0); 47366#L1316-1 assume !(0 == ~E_11~0); 47367#L1321-1 assume 0 == ~E_12~0;~E_12~0 := 1; 48023#L1326-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 48024#L593 assume 1 == ~m_pc~0; 48173#L594 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 47248#L604 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 47912#is_master_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 47913#L1492 assume !(0 != activate_threads_~tmp~1#1); 48228#L1492-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 48516#L612 assume !(1 == ~t1_pc~0); 48517#L612-2 is_transmit1_triggered_~__retres1~1#1 := 0; 48651#L623 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 48361#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 47251#L1500 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 47252#L1500-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 47690#L631 assume 1 == ~t2_pc~0; 47617#L632 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 47025#L642 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 47026#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 47380#L1508 assume !(0 != activate_threads_~tmp___1~0#1); 47876#L1508-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 47327#L650 assume !(1 == ~t3_pc~0); 47328#L650-2 is_transmit3_triggered_~__retres1~3#1 := 0; 48046#L661 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 48340#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 46982#L1516 assume !(0 != activate_threads_~tmp___2~0#1); 46983#L1516-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 48199#L669 assume 1 == ~t4_pc~0; 48200#L670 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 48555#L680 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 47065#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 47066#L1524 assume !(0 != activate_threads_~tmp___3~0#1); 47186#L1524-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 47425#L688 assume !(1 == ~t5_pc~0); 47205#L688-2 is_transmit5_triggered_~__retres1~5#1 := 0; 47206#L699 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 48683#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 48088#L1532 assume !(0 != activate_threads_~tmp___4~0#1); 48089#L1532-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 48213#L707 assume 1 == ~t6_pc~0; 48622#L708 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 47845#L718 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 47368#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 47369#L1540 assume !(0 != activate_threads_~tmp___5~0#1); 48159#L1540-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 47710#L726 assume 1 == ~t7_pc~0; 47605#L727 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 47292#L737 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 48352#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 48626#L1548 assume !(0 != activate_threads_~tmp___6~0#1); 47055#L1548-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 47056#L745 assume !(1 == ~t8_pc~0); 47512#L745-2 is_transmit8_triggered_~__retres1~8#1 := 0; 47532#L756 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 48570#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 47921#L1556 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 47922#L1556-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 48440#L764 assume 1 == ~t9_pc~0; 47708#L765 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 47542#L775 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 47441#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 47442#L1564 assume !(0 != activate_threads_~tmp___8~0#1); 47081#L1564-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 47082#L783 assume !(1 == ~t10_pc~0); 47136#L783-2 is_transmit10_triggered_~__retres1~10#1 := 0; 47137#L794 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 47334#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 47664#L1572 assume !(0 != activate_threads_~tmp___9~0#1); 47665#L1572-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 48557#L802 assume 1 == ~t11_pc~0; 48539#L803 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 47022#L813 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 47023#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 47521#L1580 assume !(0 != activate_threads_~tmp___10~0#1); 47522#L1580-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 47639#L821 assume !(1 == ~t12_pc~0); 47890#L821-2 is_transmit12_triggered_~__retres1~12#1 := 0; 47996#L832 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 47029#is_transmit12_triggered_returnLabel#1 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 47030#L1588 assume !(0 != activate_threads_~tmp___11~0#1); 48599#L1588-2 havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 48236#L1339 assume !(1 == ~M_E~0); 48237#L1339-2 assume !(1 == ~T1_E~0); 48629#L1344-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 48630#L1349-1 assume !(1 == ~T3_E~0); 48016#L1354-1 assume !(1 == ~T4_E~0); 48017#L1359-1 assume !(1 == ~T5_E~0); 48416#L1364-1 assume !(1 == ~T6_E~0); 47473#L1369-1 assume !(1 == ~T7_E~0); 47474#L1374-1 assume !(1 == ~T8_E~0); 48019#L1379-1 assume !(1 == ~T9_E~0); 48020#L1384-1 assume 1 == ~T10_E~0;~T10_E~0 := 2; 48128#L1389-1 assume !(1 == ~T11_E~0); 48593#L1394-1 assume !(1 == ~T12_E~0); 48594#L1399-1 assume !(1 == ~E_M~0); 48675#L1404-1 assume !(1 == ~E_1~0); 47566#L1409-1 assume !(1 == ~E_2~0); 47567#L1414-1 assume !(1 == ~E_3~0); 48299#L1419-1 assume !(1 == ~E_4~0); 47195#L1424-1 assume 1 == ~E_5~0;~E_5~0 := 2; 47196#L1429-1 assume !(1 == ~E_6~0); 48031#L1434-1 assume !(1 == ~E_7~0); 48611#L1439-1 assume !(1 == ~E_8~0); 47237#L1444-1 assume !(1 == ~E_9~0); 47238#L1449-1 assume !(1 == ~E_10~0); 47623#L1454-1 assume !(1 == ~E_11~0); 47624#L1459-1 assume !(1 == ~E_12~0); 48158#L1464-1 assume { :end_inline_reset_delta_events } true; 47379#L1810-2 [2023-11-12 02:04:01,380 INFO L750 eck$LassoCheckResult]: Loop: 47379#L1810-2 assume !false; 47829#L1811 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 47927#L1176-1 assume !false; 48309#L999 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 47873#L921 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 47063#L988 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 48363#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 48534#L1003 assume !(0 != eval_~tmp~0#1); 47836#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 47568#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 47569#L1201-3 assume 0 == ~M_E~0;~M_E~0 := 1; 48253#L1201-5 assume !(0 == ~T1_E~0); 48254#L1206-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 48156#L1211-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 47322#L1216-3 assume !(0 == ~T4_E~0); 47323#L1221-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 47801#L1226-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 47401#L1231-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 47402#L1236-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 47653#L1241-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 48642#L1246-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 48542#L1251-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 48241#L1256-3 assume !(0 == ~T12_E~0); 47342#L1261-3 assume 0 == ~E_M~0;~E_M~0 := 1; 47343#L1266-3 assume 0 == ~E_1~0;~E_1~0 := 1; 47393#L1271-3 assume 0 == ~E_2~0;~E_2~0 := 1; 47394#L1276-3 assume 0 == ~E_3~0;~E_3~0 := 1; 47777#L1281-3 assume 0 == ~E_4~0;~E_4~0 := 1; 47778#L1286-3 assume 0 == ~E_5~0;~E_5~0 := 1; 48296#L1291-3 assume 0 == ~E_6~0;~E_6~0 := 1; 48297#L1296-3 assume !(0 == ~E_7~0); 48714#L1301-3 assume 0 == ~E_8~0;~E_8~0 := 1; 48672#L1306-3 assume 0 == ~E_9~0;~E_9~0 := 1; 47881#L1311-3 assume 0 == ~E_10~0;~E_10~0 := 1; 47262#L1316-3 assume 0 == ~E_11~0;~E_11~0 := 1; 47263#L1321-3 assume 0 == ~E_12~0;~E_12~0 := 1; 47344#L1326-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 47995#L593-42 assume !(1 == ~m_pc~0); 48160#L593-44 is_master_triggered_~__retres1~0#1 := 0; 48161#L604-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 47676#is_master_triggered_returnLabel#15 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 47677#L1492-42 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 47156#L1492-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 47157#L612-42 assume !(1 == ~t1_pc~0); 48115#L612-44 is_transmit1_triggered_~__retres1~1#1 := 0; 48496#L623-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 48723#is_transmit1_triggered_returnLabel#15 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 47249#L1500-42 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 47250#L1500-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 47958#L631-42 assume 1 == ~t2_pc~0; 47009#L632-14 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 47010#L642-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 47943#is_transmit2_triggered_returnLabel#15 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 47827#L1508-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 47828#L1508-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 47420#L650-42 assume !(1 == ~t3_pc~0); 46976#L650-44 is_transmit3_triggered_~__retres1~3#1 := 0; 46975#L661-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 48329#is_transmit3_triggered_returnLabel#15 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 47615#L1516-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 47616#L1516-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 48613#L669-42 assume 1 == ~t4_pc~0; 47895#L670-14 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 46973#L680-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 48398#is_transmit4_triggered_returnLabel#15 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 48307#L1524-42 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 48211#L1524-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 48212#L688-42 assume 1 == ~t5_pc~0; 48294#L689-14 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 48499#L699-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 48007#is_transmit5_triggered_returnLabel#15 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 47184#L1532-42 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 47185#L1532-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 47002#L707-42 assume !(1 == ~t6_pc~0); 47003#L707-44 is_transmit6_triggered_~__retres1~6#1 := 0; 48678#L718-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 47336#is_transmit6_triggered_returnLabel#15 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 47337#L1540-42 assume !(0 != activate_threads_~tmp___5~0#1); 48182#L1540-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 48183#L726-42 assume 1 == ~t7_pc~0; 48449#L727-14 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 48480#L737-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 48034#is_transmit7_triggered_returnLabel#15 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 47885#L1548-42 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 47886#L1548-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 47999#L745-42 assume 1 == ~t8_pc~0; 48037#L746-14 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 48039#L756-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 48202#is_transmit8_triggered_returnLabel#15 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 46990#L1556-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 46991#L1556-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 47736#L764-42 assume 1 == ~t9_pc~0; 47864#L765-14 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 48225#L775-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 48226#is_transmit9_triggered_returnLabel#15 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 47274#L1564-42 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 47275#L1564-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 47335#L783-42 assume 1 == ~t10_pc~0; 46946#L784-14 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 46947#L794-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 47551#is_transmit10_triggered_returnLabel#15 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 48194#L1572-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 48705#L1572-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 48388#L802-42 assume 1 == ~t11_pc~0; 47482#L803-14 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 47088#L813-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 47089#is_transmit11_triggered_returnLabel#15 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 47035#L1580-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 47036#L1580-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 48233#L821-42 assume !(1 == ~t12_pc~0); 47591#L821-44 is_transmit12_triggered_~__retres1~12#1 := 0; 47592#L832-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 47992#is_transmit12_triggered_returnLabel#15 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 47993#L1588-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 47929#L1588-44 havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 47919#L1339-3 assume 1 == ~M_E~0;~M_E~0 := 2; 47920#L1339-5 assume !(1 == ~T1_E~0); 48092#L1344-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 48198#L1349-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 47601#L1354-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 47602#L1359-3 assume !(1 == ~T5_E~0); 48208#L1364-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 48699#L1369-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 48609#L1374-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 47422#L1379-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 47423#L1384-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 47599#L1389-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 47600#L1394-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 47815#L1399-3 assume !(1 == ~E_M~0); 48618#L1404-3 assume 1 == ~E_1~0;~E_1~0 := 2; 48586#L1409-3 assume 1 == ~E_2~0;~E_2~0 := 2; 48587#L1414-3 assume 1 == ~E_3~0;~E_3~0 := 2; 48641#L1419-3 assume 1 == ~E_4~0;~E_4~0 := 2; 48391#L1424-3 assume 1 == ~E_5~0;~E_5~0 := 2; 47296#L1429-3 assume 1 == ~E_6~0;~E_6~0 := 2; 47297#L1434-3 assume 1 == ~E_7~0;~E_7~0 := 2; 48207#L1439-3 assume !(1 == ~E_8~0); 47225#L1444-3 assume 1 == ~E_9~0;~E_9~0 := 2; 47226#L1449-3 assume 1 == ~E_10~0;~E_10~0 := 2; 47347#L1454-3 assume 1 == ~E_11~0;~E_11~0 := 2; 48203#L1459-3 assume 1 == ~E_12~0;~E_12~0 := 2; 48204#L1464-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 47846#L921-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 47128#L988-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 47330#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; 47331#L1829 assume !(0 == start_simulation_~tmp~3#1); 47110#L1829-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 47111#L921-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 47925#L988-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 47015#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret33#1;havoc stop_simulation_#t~ret33#1; 47016#L1784 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 48219#L1791 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 48592#stop_simulation_returnLabel#1 start_simulation_#t~ret35#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 47378#L1842 assume !(0 != start_simulation_~tmp___0~1#1); 47379#L1810-2 [2023-11-12 02:04:01,381 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-12 02:04:01,381 INFO L85 PathProgramCache]: Analyzing trace with hash -2089382286, now seen corresponding path program 1 times [2023-11-12 02:04:01,381 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-12 02:04:01,381 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [696064001] [2023-11-12 02:04:01,382 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-12 02:04:01,382 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-12 02:04:01,401 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-12 02:04:01,491 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-12 02:04:01,491 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-12 02:04:01,492 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [696064001] [2023-11-12 02:04:01,492 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [696064001] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-12 02:04:01,492 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-12 02:04:01,492 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-12 02:04:01,492 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1145790159] [2023-11-12 02:04:01,493 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-12 02:04:01,493 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-12 02:04:01,493 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-12 02:04:01,494 INFO L85 PathProgramCache]: Analyzing trace with hash -1910359590, now seen corresponding path program 1 times [2023-11-12 02:04:01,494 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-12 02:04:01,494 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1102749698] [2023-11-12 02:04:01,494 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-12 02:04:01,494 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-12 02:04:01,512 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-12 02:04:01,570 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-12 02:04:01,571 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-12 02:04:01,571 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1102749698] [2023-11-12 02:04:01,571 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1102749698] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-12 02:04:01,571 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-12 02:04:01,571 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-12 02:04:01,572 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [15861250] [2023-11-12 02:04:01,572 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-12 02:04:01,572 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-12 02:04:01,573 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-12 02:04:01,573 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2023-11-12 02:04:01,573 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2023-11-12 02:04:01,574 INFO L87 Difference]: Start difference. First operand 1801 states and 2648 transitions. cyclomatic complexity: 848 Second operand has 4 states, 4 states have (on average 37.5) internal successors, (150), 3 states have internal predecessors, (150), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-12 02:04:01,770 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-12 02:04:01,770 INFO L93 Difference]: Finished difference Result 3463 states and 5084 transitions. [2023-11-12 02:04:01,770 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 3463 states and 5084 transitions. [2023-11-12 02:04:01,822 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 3276 [2023-11-12 02:04:01,842 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 3463 states to 3463 states and 5084 transitions. [2023-11-12 02:04:01,842 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 3463 [2023-11-12 02:04:01,846 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 3463 [2023-11-12 02:04:01,846 INFO L73 IsDeterministic]: Start isDeterministic. Operand 3463 states and 5084 transitions. [2023-11-12 02:04:01,851 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-12 02:04:01,851 INFO L218 hiAutomatonCegarLoop]: Abstraction has 3463 states and 5084 transitions. [2023-11-12 02:04:01,857 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3463 states and 5084 transitions. [2023-11-12 02:04:01,906 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3463 to 3463. [2023-11-12 02:04:01,912 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 3463 states, 3463 states have (on average 1.4680912503609587) internal successors, (5084), 3462 states have internal predecessors, (5084), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-12 02:04:01,924 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3463 states to 3463 states and 5084 transitions. [2023-11-12 02:04:01,924 INFO L240 hiAutomatonCegarLoop]: Abstraction has 3463 states and 5084 transitions. [2023-11-12 02:04:01,925 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2023-11-12 02:04:01,925 INFO L428 stractBuchiCegarLoop]: Abstraction has 3463 states and 5084 transitions. [2023-11-12 02:04:01,925 INFO L335 stractBuchiCegarLoop]: ======== Iteration 15 ============ [2023-11-12 02:04:01,926 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 3463 states and 5084 transitions. [2023-11-12 02:04:01,942 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 3276 [2023-11-12 02:04:01,942 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-12 02:04:01,942 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-12 02:04:01,945 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-12 02:04:01,945 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-12 02:04:01,946 INFO L748 eck$LassoCheckResult]: Stem: 52497#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(20, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~token~0 := 0;~local~0 := 0; 52498#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~14#1;havoc main_~__retres1~14#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1; 53347#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret34#1, start_simulation_#t~ret35#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 53348#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 53943#L848 assume 1 == ~m_i~0;~m_st~0 := 0; 53944#L848-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 53025#L853-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 52813#L858-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 52209#L863-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 52210#L868-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 53460#L873-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 53561#L878-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 54015#L883-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 54016#L888-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 52949#L893-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 52950#L898-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 53486#L903-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 53409#L908-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 52986#L1201 assume !(0 == ~M_E~0); 52987#L1201-2 assume !(0 == ~T1_E~0); 53847#L1206-1 assume !(0 == ~T2_E~0); 53830#L1211-1 assume !(0 == ~T3_E~0); 53831#L1216-1 assume !(0 == ~T4_E~0); 52795#L1221-1 assume !(0 == ~T5_E~0); 52796#L1226-1 assume !(0 == ~T6_E~0); 52423#L1231-1 assume !(0 == ~T7_E~0); 52424#L1236-1 assume !(0 == ~T8_E~0); 53873#L1241-1 assume !(0 == ~T9_E~0); 52837#L1246-1 assume !(0 == ~T10_E~0); 52838#L1251-1 assume !(0 == ~T11_E~0); 52984#L1256-1 assume !(0 == ~T12_E~0); 52218#L1261-1 assume !(0 == ~E_M~0); 52219#L1266-1 assume !(0 == ~E_1~0); 53997#L1271-1 assume !(0 == ~E_2~0); 53544#L1276-1 assume !(0 == ~E_3~0); 53545#L1281-1 assume 0 == ~E_4~0;~E_4~0 := 1; 53498#L1286-1 assume !(0 == ~E_5~0); 52689#L1291-1 assume !(0 == ~E_6~0); 52690#L1296-1 assume !(0 == ~E_7~0); 53281#L1301-1 assume !(0 == ~E_8~0); 53282#L1306-1 assume !(0 == ~E_9~0); 53765#L1311-1 assume !(0 == ~E_10~0); 52640#L1316-1 assume !(0 == ~E_11~0); 52641#L1321-1 assume 0 == ~E_12~0;~E_12~0 := 1; 53301#L1326-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 53302#L593 assume 1 == ~m_pc~0; 53452#L594 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 52522#L604 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 53188#is_master_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 53189#L1492 assume !(0 != activate_threads_~tmp~1#1); 53508#L1492-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 53798#L612 assume !(1 == ~t1_pc~0); 53799#L612-2 is_transmit1_triggered_~__retres1~1#1 := 0; 53939#L623 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 53642#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 52525#L1500 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 52526#L1500-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 52965#L631 assume 1 == ~t2_pc~0; 52892#L632 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 52299#L642 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 52300#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 52654#L1508 assume !(0 != activate_threads_~tmp___1~0#1); 53152#L1508-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 52603#L650 assume !(1 == ~t3_pc~0); 52604#L650-2 is_transmit3_triggered_~__retres1~3#1 := 0; 53324#L661 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 53621#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 52256#L1516 assume !(0 != activate_threads_~tmp___2~0#1); 52257#L1516-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 53479#L669 assume 1 == ~t4_pc~0; 53480#L670 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 53839#L680 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 52343#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 52344#L1524 assume !(0 != activate_threads_~tmp___3~0#1); 52460#L1524-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 52700#L688 assume !(1 == ~t5_pc~0); 52479#L688-2 is_transmit5_triggered_~__retres1~5#1 := 0; 52480#L699 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 53975#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 53368#L1532 assume !(0 != activate_threads_~tmp___4~0#1); 53369#L1532-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 53496#L707 assume 1 == ~t6_pc~0; 53908#L708 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 53121#L718 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 52642#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 52643#L1540 assume !(0 != activate_threads_~tmp___5~0#1); 53440#L1540-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 52985#L726 assume 1 == ~t7_pc~0; 52882#L727 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 52566#L737 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 53634#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 53914#L1548 assume !(0 != activate_threads_~tmp___6~0#1); 52329#L1548-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 52330#L745 assume !(1 == ~t8_pc~0); 52787#L745-2 is_transmit8_triggered_~__retres1~8#1 := 0; 52807#L756 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 53853#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 53197#L1556 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 53198#L1556-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 53721#L764 assume 1 == ~t9_pc~0; 52983#L765 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 52817#L775 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 52716#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 52717#L1564 assume !(0 != activate_threads_~tmp___8~0#1); 52355#L1564-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 52356#L783 assume !(1 == ~t10_pc~0); 52410#L783-2 is_transmit10_triggered_~__retres1~10#1 := 0; 52411#L794 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 52608#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 52944#L1572 assume !(0 != activate_threads_~tmp___9~0#1); 52945#L1572-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 53840#L802 assume 1 == ~t11_pc~0; 53822#L803 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 52296#L813 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 52297#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 52797#L1580 assume !(0 != activate_threads_~tmp___10~0#1); 52798#L1580-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 52914#L821 assume !(1 == ~t12_pc~0); 53166#L821-2 is_transmit12_triggered_~__retres1~12#1 := 0; 53272#L832 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 52305#is_transmit12_triggered_returnLabel#1 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 52306#L1588 assume !(0 != activate_threads_~tmp___11~0#1); 53885#L1588-2 havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 53516#L1339 assume !(1 == ~M_E~0); 53517#L1339-2 assume !(1 == ~T1_E~0); 53916#L1344-1 assume !(1 == ~T2_E~0); 53917#L1349-1 assume !(1 == ~T3_E~0); 53294#L1354-1 assume !(1 == ~T4_E~0); 53295#L1359-1 assume !(1 == ~T5_E~0); 53699#L1364-1 assume !(1 == ~T6_E~0); 52748#L1369-1 assume !(1 == ~T7_E~0); 52749#L1374-1 assume !(1 == ~T8_E~0); 53298#L1379-1 assume 1 == ~T9_E~0;~T9_E~0 := 2; 53299#L1384-1 assume 1 == ~T10_E~0;~T10_E~0 := 2; 54132#L1389-1 assume !(1 == ~T11_E~0); 54131#L1394-1 assume !(1 == ~T12_E~0); 54130#L1399-1 assume !(1 == ~E_M~0); 54129#L1404-1 assume !(1 == ~E_1~0); 54127#L1409-1 assume !(1 == ~E_2~0); 54125#L1414-1 assume !(1 == ~E_3~0); 54123#L1419-1 assume !(1 == ~E_4~0); 54121#L1424-1 assume 1 == ~E_5~0;~E_5~0 := 2; 54118#L1429-1 assume !(1 == ~E_6~0); 54116#L1434-1 assume !(1 == ~E_7~0); 54114#L1439-1 assume !(1 == ~E_8~0); 54112#L1444-1 assume !(1 == ~E_9~0); 54110#L1449-1 assume !(1 == ~E_10~0); 54092#L1454-1 assume !(1 == ~E_11~0); 54084#L1459-1 assume !(1 == ~E_12~0); 53437#L1464-1 assume { :end_inline_reset_delta_events } true; 52653#L1810-2 [2023-11-12 02:04:01,947 INFO L750 eck$LassoCheckResult]: Loop: 52653#L1810-2 assume !false; 53105#L1811 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 53203#L1176-1 assume !false; 53590#L999 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 53151#L921 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 52337#L988 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 53644#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 53819#L1003 assume !(0 != eval_~tmp~0#1); 53112#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 52843#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 52844#L1201-3 assume 0 == ~M_E~0;~M_E~0 := 1; 53534#L1201-5 assume !(0 == ~T1_E~0); 53535#L1206-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 54042#L1211-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 55102#L1216-3 assume !(0 == ~T4_E~0); 55101#L1221-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 55100#L1226-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 55099#L1231-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 55098#L1236-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 55096#L1241-3 assume !(0 == ~T9_E~0); 55093#L1246-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 55091#L1251-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 55089#L1256-3 assume !(0 == ~T12_E~0); 55087#L1261-3 assume 0 == ~E_M~0;~E_M~0 := 1; 55085#L1266-3 assume 0 == ~E_1~0;~E_1~0 := 1; 55083#L1271-3 assume 0 == ~E_2~0;~E_2~0 := 1; 55080#L1276-3 assume 0 == ~E_3~0;~E_3~0 := 1; 55078#L1281-3 assume 0 == ~E_4~0;~E_4~0 := 1; 55076#L1286-3 assume 0 == ~E_5~0;~E_5~0 := 1; 55074#L1291-3 assume 0 == ~E_6~0;~E_6~0 := 1; 55072#L1296-3 assume !(0 == ~E_7~0); 55070#L1301-3 assume 0 == ~E_8~0;~E_8~0 := 1; 55067#L1306-3 assume 0 == ~E_9~0;~E_9~0 := 1; 55065#L1311-3 assume 0 == ~E_10~0;~E_10~0 := 1; 55063#L1316-3 assume 0 == ~E_11~0;~E_11~0 := 1; 55061#L1321-3 assume 0 == ~E_12~0;~E_12~0 := 1; 55059#L1326-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 55057#L593-42 assume 1 == ~m_pc~0; 55053#L594-14 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 55051#L604-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 55049#is_master_triggered_returnLabel#15 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 55047#L1492-42 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 55045#L1492-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 55043#L612-42 assume 1 == ~t1_pc~0; 55040#L613-14 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 55037#L623-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 55035#is_transmit1_triggered_returnLabel#15 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 55033#L1500-42 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 55031#L1500-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 55029#L631-42 assume 1 == ~t2_pc~0; 55025#L632-14 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 55023#L642-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 55021#is_transmit2_triggered_returnLabel#15 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 55019#L1508-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 55017#L1508-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 55015#L650-42 assume !(1 == ~t3_pc~0); 55011#L650-44 is_transmit3_triggered_~__retres1~3#1 := 0; 55009#L661-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 55007#is_transmit3_triggered_returnLabel#15 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 55005#L1516-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 55003#L1516-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 55001#L669-42 assume 1 == ~t4_pc~0; 54997#L670-14 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 54995#L680-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 54993#is_transmit4_triggered_returnLabel#15 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 54991#L1524-42 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 54989#L1524-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 54987#L688-42 assume !(1 == ~t5_pc~0); 54983#L688-44 is_transmit5_triggered_~__retres1~5#1 := 0; 54981#L699-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 54979#is_transmit5_triggered_returnLabel#15 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 54977#L1532-42 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 54975#L1532-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 54973#L707-42 assume 1 == ~t6_pc~0; 54969#L708-14 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 54967#L718-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 54965#is_transmit6_triggered_returnLabel#15 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 54963#L1540-42 assume !(0 != activate_threads_~tmp___5~0#1); 54961#L1540-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 54959#L726-42 assume 1 == ~t7_pc~0; 54955#L727-14 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 54953#L737-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 54951#is_transmit7_triggered_returnLabel#15 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 54949#L1548-42 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 54947#L1548-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 54945#L745-42 assume !(1 == ~t8_pc~0); 54941#L745-44 is_transmit8_triggered_~__retres1~8#1 := 0; 54939#L756-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 54937#is_transmit8_triggered_returnLabel#15 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 54935#L1556-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 54933#L1556-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 54931#L764-42 assume !(1 == ~t9_pc~0); 54928#L764-44 is_transmit9_triggered_~__retres1~9#1 := 0; 54925#L775-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 54923#is_transmit9_triggered_returnLabel#15 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 54921#L1564-42 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 54919#L1564-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 54915#L783-42 assume !(1 == ~t10_pc~0); 54912#L783-44 is_transmit10_triggered_~__retres1~10#1 := 0; 54910#L794-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 54909#is_transmit10_triggered_returnLabel#15 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 54908#L1572-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 54905#L1572-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 54904#L802-42 assume 1 == ~t11_pc~0; 54902#L803-14 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 54901#L813-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 54900#is_transmit11_triggered_returnLabel#15 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 54899#L1580-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 54898#L1580-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 54897#L821-42 assume 1 == ~t12_pc~0; 54896#L822-14 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 54894#L832-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 54893#is_transmit12_triggered_returnLabel#15 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 54892#L1588-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 54891#L1588-44 havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 54890#L1339-3 assume 1 == ~M_E~0;~M_E~0 := 2; 54889#L1339-5 assume !(1 == ~T1_E~0); 54888#L1344-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 53525#L1349-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 54887#L1354-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 54886#L1359-3 assume !(1 == ~T5_E~0); 54885#L1364-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 54884#L1369-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 54883#L1374-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 54882#L1379-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 52696#L1384-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 54881#L1389-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 54880#L1394-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 54879#L1399-3 assume !(1 == ~E_M~0); 54878#L1404-3 assume 1 == ~E_1~0;~E_1~0 := 2; 54877#L1409-3 assume 1 == ~E_2~0;~E_2~0 := 2; 54876#L1414-3 assume 1 == ~E_3~0;~E_3~0 := 2; 54875#L1419-3 assume 1 == ~E_4~0;~E_4~0 := 2; 54874#L1424-3 assume 1 == ~E_5~0;~E_5~0 := 2; 54873#L1429-3 assume 1 == ~E_6~0;~E_6~0 := 2; 54872#L1434-3 assume 1 == ~E_7~0;~E_7~0 := 2; 54871#L1439-3 assume !(1 == ~E_8~0); 54870#L1444-3 assume 1 == ~E_9~0;~E_9~0 := 2; 54869#L1449-3 assume 1 == ~E_10~0;~E_10~0 := 2; 54868#L1454-3 assume 1 == ~E_11~0;~E_11~0 := 2; 54867#L1459-3 assume 1 == ~E_12~0;~E_12~0 := 2; 54866#L1464-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 54865#L921-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 54852#L988-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 54851#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; 54771#L1829 assume !(0 == start_simulation_~tmp~3#1); 54770#L1829-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 54286#L921-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 54109#L988-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 54108#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret33#1;havoc stop_simulation_#t~ret33#1; 54107#L1784 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 54012#L1791 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 53877#stop_simulation_returnLabel#1 start_simulation_#t~ret35#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 52652#L1842 assume !(0 != start_simulation_~tmp___0~1#1); 52653#L1810-2 [2023-11-12 02:04:01,947 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-12 02:04:01,948 INFO L85 PathProgramCache]: Analyzing trace with hash 907144632, now seen corresponding path program 1 times [2023-11-12 02:04:01,948 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-12 02:04:01,948 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [232433742] [2023-11-12 02:04:01,948 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-12 02:04:01,948 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-12 02:04:01,966 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-12 02:04:02,052 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-12 02:04:02,052 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-12 02:04:02,053 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [232433742] [2023-11-12 02:04:02,053 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [232433742] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-12 02:04:02,053 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-12 02:04:02,053 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-12 02:04:02,053 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1747776430] [2023-11-12 02:04:02,053 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-12 02:04:02,054 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-12 02:04:02,054 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-12 02:04:02,055 INFO L85 PathProgramCache]: Analyzing trace with hash -770929124, now seen corresponding path program 1 times [2023-11-12 02:04:02,055 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-12 02:04:02,055 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1581132078] [2023-11-12 02:04:02,055 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-12 02:04:02,055 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-12 02:04:02,075 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-12 02:04:02,135 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-12 02:04:02,135 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-12 02:04:02,135 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1581132078] [2023-11-12 02:04:02,135 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1581132078] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-12 02:04:02,136 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-12 02:04:02,136 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-12 02:04:02,136 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [706105695] [2023-11-12 02:04:02,136 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-12 02:04:02,136 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-12 02:04:02,137 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-12 02:04:02,137 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2023-11-12 02:04:02,137 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2023-11-12 02:04:02,137 INFO L87 Difference]: Start difference. First operand 3463 states and 5084 transitions. cyclomatic complexity: 1623 Second operand has 4 states, 4 states have (on average 37.5) internal successors, (150), 3 states have internal predecessors, (150), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-12 02:04:02,406 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-12 02:04:02,406 INFO L93 Difference]: Finished difference Result 6581 states and 9651 transitions. [2023-11-12 02:04:02,406 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 6581 states and 9651 transitions. [2023-11-12 02:04:02,445 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 6366 [2023-11-12 02:04:02,470 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 6581 states to 6581 states and 9651 transitions. [2023-11-12 02:04:02,470 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 6581 [2023-11-12 02:04:02,478 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 6581 [2023-11-12 02:04:02,478 INFO L73 IsDeterministic]: Start isDeterministic. Operand 6581 states and 9651 transitions. [2023-11-12 02:04:02,487 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-12 02:04:02,487 INFO L218 hiAutomatonCegarLoop]: Abstraction has 6581 states and 9651 transitions. [2023-11-12 02:04:02,496 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 6581 states and 9651 transitions. [2023-11-12 02:04:02,599 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 6581 to 6579. [2023-11-12 02:04:02,609 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 6579 states, 6579 states have (on average 1.4666362669098647) internal successors, (9649), 6578 states have internal predecessors, (9649), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-12 02:04:02,628 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 6579 states to 6579 states and 9649 transitions. [2023-11-12 02:04:02,629 INFO L240 hiAutomatonCegarLoop]: Abstraction has 6579 states and 9649 transitions. [2023-11-12 02:04:02,629 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2023-11-12 02:04:02,630 INFO L428 stractBuchiCegarLoop]: Abstraction has 6579 states and 9649 transitions. [2023-11-12 02:04:02,630 INFO L335 stractBuchiCegarLoop]: ======== Iteration 16 ============ [2023-11-12 02:04:02,630 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 6579 states and 9649 transitions. [2023-11-12 02:04:02,693 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 6366 [2023-11-12 02:04:02,693 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-12 02:04:02,693 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-12 02:04:02,696 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-12 02:04:02,697 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-12 02:04:02,697 INFO L748 eck$LassoCheckResult]: Stem: 62551#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(20, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~token~0 := 0;~local~0 := 0; 62552#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~14#1;havoc main_~__retres1~14#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1; 63420#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret34#1, start_simulation_#t~ret35#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 63421#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 64064#L848 assume 1 == ~m_i~0;~m_st~0 := 0; 64065#L848-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 63086#L853-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 62871#L858-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 62263#L863-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 62264#L868-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 63534#L873-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 63637#L878-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 64147#L883-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 64148#L888-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 63010#L893-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 63011#L898-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 63560#L903-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 63484#L908-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 63048#L1201 assume !(0 == ~M_E~0); 63049#L1201-2 assume !(0 == ~T1_E~0); 63961#L1206-1 assume !(0 == ~T2_E~0); 63940#L1211-1 assume !(0 == ~T3_E~0); 63941#L1216-1 assume !(0 == ~T4_E~0); 62852#L1221-1 assume !(0 == ~T5_E~0); 62853#L1226-1 assume !(0 == ~T6_E~0); 62477#L1231-1 assume !(0 == ~T7_E~0); 62478#L1236-1 assume !(0 == ~T8_E~0); 63987#L1241-1 assume !(0 == ~T9_E~0); 62892#L1246-1 assume !(0 == ~T10_E~0); 62893#L1251-1 assume !(0 == ~T11_E~0); 63046#L1256-1 assume !(0 == ~T12_E~0); 62272#L1261-1 assume !(0 == ~E_M~0); 62273#L1266-1 assume !(0 == ~E_1~0); 64124#L1271-1 assume !(0 == ~E_2~0); 63621#L1276-1 assume !(0 == ~E_3~0); 63622#L1281-1 assume !(0 == ~E_4~0); 63572#L1286-1 assume !(0 == ~E_5~0); 62744#L1291-1 assume !(0 == ~E_6~0); 62745#L1296-1 assume !(0 == ~E_7~0); 63354#L1301-1 assume !(0 == ~E_8~0); 63355#L1306-1 assume !(0 == ~E_9~0); 63866#L1311-1 assume !(0 == ~E_10~0); 62695#L1316-1 assume !(0 == ~E_11~0); 62696#L1321-1 assume 0 == ~E_12~0;~E_12~0 := 1; 63375#L1326-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 63376#L593 assume 1 == ~m_pc~0; 63527#L594 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 62576#L604 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 63258#is_master_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 63259#L1492 assume !(0 != activate_threads_~tmp~1#1); 63582#L1492-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 63903#L612 assume !(1 == ~t1_pc~0); 63904#L612-2 is_transmit1_triggered_~__retres1~1#1 := 0; 64059#L623 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 63724#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 62579#L1500 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 62580#L1500-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 63026#L631 assume 1 == ~t2_pc~0; 62950#L632 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 62353#L642 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 62354#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 62709#L1508 assume !(0 != activate_threads_~tmp___1~0#1); 63219#L1508-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 62656#L650 assume !(1 == ~t3_pc~0); 62657#L650-2 is_transmit3_triggered_~__retres1~3#1 := 0; 63398#L661 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 63700#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 62310#L1516 assume !(0 != activate_threads_~tmp___2~0#1); 62311#L1516-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 63553#L669 assume 1 == ~t4_pc~0; 63554#L670 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 63950#L680 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 62393#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 62394#L1524 assume !(0 != activate_threads_~tmp___3~0#1); 62514#L1524-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 62755#L688 assume !(1 == ~t5_pc~0); 62533#L688-2 is_transmit5_triggered_~__retres1~5#1 := 0; 62534#L699 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 64097#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 63440#L1532 assume !(0 != activate_threads_~tmp___4~0#1); 63441#L1532-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 63567#L707 assume 1 == ~t6_pc~0; 64023#L708 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 63187#L718 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 62697#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 62698#L1540 assume !(0 != activate_threads_~tmp___5~0#1); 63513#L1540-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 63047#L726 assume 1 == ~t7_pc~0; 62938#L727 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 62621#L737 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 63714#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 64030#L1548 assume !(0 != activate_threads_~tmp___6~0#1); 62383#L1548-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 62384#L745 assume !(1 == ~t8_pc~0); 62845#L745-2 is_transmit8_triggered_~__retres1~8#1 := 0; 62865#L756 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 63969#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 63267#L1556 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 63268#L1556-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 63817#L764 assume 1 == ~t9_pc~0; 63045#L765 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 62875#L775 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 62773#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 62774#L1564 assume !(0 != activate_threads_~tmp___8~0#1); 62409#L1564-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 62410#L783 assume !(1 == ~t10_pc~0); 62464#L783-2 is_transmit10_triggered_~__retres1~10#1 := 0; 62465#L794 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 62663#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 62999#L1572 assume !(0 != activate_threads_~tmp___9~0#1); 63000#L1572-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 63952#L802 assume 1 == ~t11_pc~0; 63926#L803 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 62350#L813 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 62351#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 62854#L1580 assume !(0 != activate_threads_~tmp___10~0#1); 62855#L1580-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 62973#L821 assume !(1 == ~t12_pc~0); 63235#L821-2 is_transmit12_triggered_~__retres1~12#1 := 0; 63345#L832 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 62357#is_transmit12_triggered_returnLabel#1 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 62358#L1588 assume !(0 != activate_threads_~tmp___11~0#1); 63998#L1588-2 havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 63592#L1339 assume !(1 == ~M_E~0); 63593#L1339-2 assume !(1 == ~T1_E~0); 64033#L1344-1 assume !(1 == ~T2_E~0); 64034#L1349-1 assume !(1 == ~T3_E~0); 63367#L1354-1 assume !(1 == ~T4_E~0); 63368#L1359-1 assume !(1 == ~T5_E~0); 63790#L1364-1 assume !(1 == ~T6_E~0); 64139#L1369-1 assume !(1 == ~T7_E~0); 64492#L1374-1 assume !(1 == ~T8_E~0); 63370#L1379-1 assume 1 == ~T9_E~0;~T9_E~0 := 2; 63371#L1384-1 assume 1 == ~T10_E~0;~T10_E~0 := 2; 64409#L1389-1 assume !(1 == ~T11_E~0); 64407#L1394-1 assume !(1 == ~T12_E~0); 64404#L1399-1 assume !(1 == ~E_M~0); 64402#L1404-1 assume !(1 == ~E_1~0); 64400#L1409-1 assume !(1 == ~E_2~0); 64399#L1414-1 assume !(1 == ~E_3~0); 64349#L1419-1 assume 1 == ~E_4~0;~E_4~0 := 2; 64347#L1424-1 assume 1 == ~E_5~0;~E_5~0 := 2; 64345#L1429-1 assume !(1 == ~E_6~0); 64331#L1434-1 assume !(1 == ~E_7~0); 64329#L1439-1 assume !(1 == ~E_8~0); 64287#L1444-1 assume !(1 == ~E_9~0); 64256#L1449-1 assume !(1 == ~E_10~0); 64239#L1454-1 assume !(1 == ~E_11~0); 64230#L1459-1 assume !(1 == ~E_12~0); 64222#L1464-1 assume { :end_inline_reset_delta_events } true; 64215#L1810-2 [2023-11-12 02:04:02,699 INFO L750 eck$LassoCheckResult]: Loop: 64215#L1810-2 assume !false; 64211#L1811 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 64210#L1176-1 assume !false; 64209#L999 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 64206#L921 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 64195#L988 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 64194#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 64192#L1003 assume !(0 != eval_~tmp~0#1); 64191#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 64190#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 64189#L1201-3 assume 0 == ~M_E~0;~M_E~0 := 1; 64188#L1201-5 assume !(0 == ~T1_E~0); 64186#L1206-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 64187#L1211-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 66079#L1216-3 assume !(0 == ~T4_E~0); 66069#L1221-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 66062#L1226-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 66055#L1231-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 66047#L1236-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 66036#L1241-3 assume !(0 == ~T9_E~0); 66034#L1246-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 66032#L1251-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 66030#L1256-3 assume !(0 == ~T12_E~0); 66027#L1261-3 assume 0 == ~E_M~0;~E_M~0 := 1; 66025#L1266-3 assume 0 == ~E_1~0;~E_1~0 := 1; 66023#L1271-3 assume 0 == ~E_2~0;~E_2~0 := 1; 66021#L1276-3 assume 0 == ~E_3~0;~E_3~0 := 1; 66019#L1281-3 assume !(0 == ~E_4~0); 66017#L1286-3 assume 0 == ~E_5~0;~E_5~0 := 1; 66014#L1291-3 assume 0 == ~E_6~0;~E_6~0 := 1; 66013#L1296-3 assume !(0 == ~E_7~0); 66011#L1301-3 assume 0 == ~E_8~0;~E_8~0 := 1; 66009#L1306-3 assume 0 == ~E_9~0;~E_9~0 := 1; 66007#L1311-3 assume 0 == ~E_10~0;~E_10~0 := 1; 66006#L1316-3 assume 0 == ~E_11~0;~E_11~0 := 1; 66004#L1321-3 assume 0 == ~E_12~0;~E_12~0 := 1; 66002#L1326-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 66000#L593-42 assume !(1 == ~m_pc~0); 65999#L593-44 is_master_triggered_~__retres1~0#1 := 0; 65997#L604-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 65995#is_master_triggered_returnLabel#15 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 65993#L1492-42 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 65937#L1492-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 65935#L612-42 assume 1 == ~t1_pc~0; 65933#L613-14 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 65930#L623-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 65928#is_transmit1_triggered_returnLabel#15 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 65926#L1500-42 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 65924#L1500-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 65923#L631-42 assume 1 == ~t2_pc~0; 65921#L632-14 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 65919#L642-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 65917#is_transmit2_triggered_returnLabel#15 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 65915#L1508-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 65913#L1508-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 65911#L650-42 assume 1 == ~t3_pc~0; 65909#L651-14 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 65906#L661-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 65904#is_transmit3_triggered_returnLabel#15 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 65817#L1516-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 65816#L1516-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 65813#L669-42 assume !(1 == ~t4_pc~0); 65811#L669-44 is_transmit4_triggered_~__retres1~4#1 := 0; 65808#L680-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 65806#is_transmit4_triggered_returnLabel#15 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 65804#L1524-42 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 65802#L1524-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 65800#L688-42 assume !(1 == ~t5_pc~0); 65797#L688-44 is_transmit5_triggered_~__retres1~5#1 := 0; 65795#L699-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 65793#is_transmit5_triggered_returnLabel#15 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 65791#L1532-42 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 65789#L1532-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 65750#L707-42 assume 1 == ~t6_pc~0; 65683#L708-14 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 65681#L718-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 65679#is_transmit6_triggered_returnLabel#15 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 65614#L1540-42 assume !(0 != activate_threads_~tmp___5~0#1); 65611#L1540-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 65609#L726-42 assume !(1 == ~t7_pc~0); 65607#L726-44 is_transmit7_triggered_~__retres1~7#1 := 0; 65604#L737-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 65602#is_transmit7_triggered_returnLabel#15 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 65600#L1548-42 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 65599#L1548-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 65598#L745-42 assume 1 == ~t8_pc~0; 65597#L746-14 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 65593#L756-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 65591#is_transmit8_triggered_returnLabel#15 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 65589#L1556-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 65587#L1556-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 65487#L764-42 assume 1 == ~t9_pc~0; 65483#L765-14 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 65481#L775-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 65479#is_transmit9_triggered_returnLabel#15 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 65477#L1564-42 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 65475#L1564-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 65473#L783-42 assume !(1 == ~t10_pc~0); 65470#L783-44 is_transmit10_triggered_~__retres1~10#1 := 0; 65422#L794-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 65420#is_transmit10_triggered_returnLabel#15 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 65368#L1572-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 65367#L1572-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 65366#L802-42 assume 1 == ~t11_pc~0; 65323#L803-14 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 65321#L813-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 65213#is_transmit11_triggered_returnLabel#15 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 65211#L1580-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 65209#L1580-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 65207#L821-42 assume !(1 == ~t12_pc~0); 64830#L821-44 is_transmit12_triggered_~__retres1~12#1 := 0; 64828#L832-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 64826#is_transmit12_triggered_returnLabel#15 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 64824#L1588-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 64822#L1588-44 havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 64820#L1339-3 assume 1 == ~M_E~0;~M_E~0 := 2; 64818#L1339-5 assume !(1 == ~T1_E~0); 64816#L1344-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 63601#L1349-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 64682#L1354-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 64680#L1359-3 assume !(1 == ~T5_E~0); 64678#L1364-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 64676#L1369-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 64672#L1374-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 64670#L1379-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 62752#L1384-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 64626#L1389-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 64624#L1394-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 64622#L1399-3 assume !(1 == ~E_M~0); 64620#L1404-3 assume 1 == ~E_1~0;~E_1~0 := 2; 64562#L1409-3 assume 1 == ~E_2~0;~E_2~0 := 2; 64517#L1414-3 assume 1 == ~E_3~0;~E_3~0 := 2; 64465#L1419-3 assume 1 == ~E_4~0;~E_4~0 := 2; 64398#L1424-3 assume 1 == ~E_5~0;~E_5~0 := 2; 64396#L1429-3 assume 1 == ~E_6~0;~E_6~0 := 2; 64394#L1434-3 assume 1 == ~E_7~0;~E_7~0 := 2; 64392#L1439-3 assume !(1 == ~E_8~0); 64390#L1444-3 assume 1 == ~E_9~0;~E_9~0 := 2; 64388#L1449-3 assume 1 == ~E_10~0;~E_10~0 := 2; 64386#L1454-3 assume 1 == ~E_11~0;~E_11~0 := 2; 64348#L1459-3 assume 1 == ~E_12~0;~E_12~0 := 2; 64346#L1464-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 64344#L921-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 64330#L988-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 64328#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; 64323#L1829 assume !(0 == start_simulation_~tmp~3#1); 64321#L1829-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 64284#L921-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 64271#L988-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 64255#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret33#1;havoc stop_simulation_#t~ret33#1; 64251#L1784 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 64238#L1791 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 64229#stop_simulation_returnLabel#1 start_simulation_#t~ret35#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 64221#L1842 assume !(0 != start_simulation_~tmp___0~1#1); 64215#L1810-2 [2023-11-12 02:04:02,700 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-12 02:04:02,700 INFO L85 PathProgramCache]: Analyzing trace with hash -1065863428, now seen corresponding path program 1 times [2023-11-12 02:04:02,701 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-12 02:04:02,701 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1946792806] [2023-11-12 02:04:02,701 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-12 02:04:02,701 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-12 02:04:02,724 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-12 02:04:02,824 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-12 02:04:02,825 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-12 02:04:02,825 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1946792806] [2023-11-12 02:04:02,825 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1946792806] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-12 02:04:02,825 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-12 02:04:02,825 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-12 02:04:02,826 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [679683235] [2023-11-12 02:04:02,826 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-12 02:04:02,826 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-12 02:04:02,827 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-12 02:04:02,827 INFO L85 PathProgramCache]: Analyzing trace with hash -1007106657, now seen corresponding path program 1 times [2023-11-12 02:04:02,827 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-12 02:04:02,828 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1442377435] [2023-11-12 02:04:02,828 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-12 02:04:02,828 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-12 02:04:02,851 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-12 02:04:02,919 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-12 02:04:02,919 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-12 02:04:02,919 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1442377435] [2023-11-12 02:04:02,919 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1442377435] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-12 02:04:02,920 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-12 02:04:02,920 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-12 02:04:02,920 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1348557860] [2023-11-12 02:04:02,920 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-12 02:04:02,921 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-12 02:04:02,921 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-12 02:04:02,921 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2023-11-12 02:04:02,922 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2023-11-12 02:04:02,922 INFO L87 Difference]: Start difference. First operand 6579 states and 9649 transitions. cyclomatic complexity: 3074 Second operand has 4 states, 4 states have (on average 37.5) internal successors, (150), 3 states have internal predecessors, (150), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-12 02:04:03,218 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-12 02:04:03,219 INFO L93 Difference]: Finished difference Result 12589 states and 18436 transitions. [2023-11-12 02:04:03,219 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 12589 states and 18436 transitions. [2023-11-12 02:04:03,284 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 12360 [2023-11-12 02:04:03,333 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 12589 states to 12589 states and 18436 transitions. [2023-11-12 02:04:03,334 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 12589 [2023-11-12 02:04:03,350 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 12589 [2023-11-12 02:04:03,350 INFO L73 IsDeterministic]: Start isDeterministic. Operand 12589 states and 18436 transitions. [2023-11-12 02:04:03,363 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-12 02:04:03,363 INFO L218 hiAutomatonCegarLoop]: Abstraction has 12589 states and 18436 transitions. [2023-11-12 02:04:03,379 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 12589 states and 18436 transitions. [2023-11-12 02:04:03,544 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 12589 to 12585. [2023-11-12 02:04:03,562 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 12585 states, 12585 states have (on average 1.464600715137068) internal successors, (18432), 12584 states have internal predecessors, (18432), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-12 02:04:03,598 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 12585 states to 12585 states and 18432 transitions. [2023-11-12 02:04:03,598 INFO L240 hiAutomatonCegarLoop]: Abstraction has 12585 states and 18432 transitions. [2023-11-12 02:04:03,598 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2023-11-12 02:04:03,599 INFO L428 stractBuchiCegarLoop]: Abstraction has 12585 states and 18432 transitions. [2023-11-12 02:04:03,600 INFO L335 stractBuchiCegarLoop]: ======== Iteration 17 ============ [2023-11-12 02:04:03,600 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 12585 states and 18432 transitions. [2023-11-12 02:04:03,717 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 12360 [2023-11-12 02:04:03,717 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-12 02:04:03,717 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-12 02:04:03,720 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-12 02:04:03,720 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-12 02:04:03,720 INFO L748 eck$LassoCheckResult]: Stem: 81729#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(20, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~token~0 := 0;~local~0 := 0; 81730#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~14#1;havoc main_~__retres1~14#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1; 82582#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret34#1, start_simulation_#t~ret35#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 82583#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 83200#L848 assume 1 == ~m_i~0;~m_st~0 := 0; 83201#L848-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 82261#L853-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 82049#L858-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 81441#L863-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 81442#L868-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 82696#L873-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 82797#L878-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 83270#L883-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 83271#L888-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 82185#L893-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 82186#L898-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 82722#L903-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 82646#L908-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 82223#L1201 assume !(0 == ~M_E~0); 82224#L1201-2 assume !(0 == ~T1_E~0); 83100#L1206-1 assume !(0 == ~T2_E~0); 83080#L1211-1 assume !(0 == ~T3_E~0); 83081#L1216-1 assume !(0 == ~T4_E~0); 82030#L1221-1 assume !(0 == ~T5_E~0); 82031#L1226-1 assume !(0 == ~T6_E~0); 81655#L1231-1 assume !(0 == ~T7_E~0); 81656#L1236-1 assume !(0 == ~T8_E~0); 83126#L1241-1 assume !(0 == ~T9_E~0); 82070#L1246-1 assume !(0 == ~T10_E~0); 82071#L1251-1 assume !(0 == ~T11_E~0); 82221#L1256-1 assume !(0 == ~T12_E~0); 81450#L1261-1 assume !(0 == ~E_M~0); 81451#L1266-1 assume !(0 == ~E_1~0); 83253#L1271-1 assume !(0 == ~E_2~0); 82780#L1276-1 assume !(0 == ~E_3~0); 82781#L1281-1 assume !(0 == ~E_4~0); 82734#L1286-1 assume !(0 == ~E_5~0); 81923#L1291-1 assume !(0 == ~E_6~0); 81924#L1296-1 assume !(0 == ~E_7~0); 82517#L1301-1 assume !(0 == ~E_8~0); 82518#L1306-1 assume !(0 == ~E_9~0); 83012#L1311-1 assume !(0 == ~E_10~0); 81874#L1316-1 assume !(0 == ~E_11~0); 81875#L1321-1 assume !(0 == ~E_12~0); 82536#L1326-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 82537#L593 assume 1 == ~m_pc~0; 82689#L594 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 81754#L604 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 82425#is_master_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 82426#L1492 assume !(0 != activate_threads_~tmp~1#1); 82744#L1492-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 83049#L612 assume !(1 == ~t1_pc~0); 83050#L612-2 is_transmit1_triggered_~__retres1~1#1 := 0; 83196#L623 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 82882#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 81757#L1500 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 81758#L1500-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 82201#L631 assume 1 == ~t2_pc~0; 82128#L632 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 81531#L642 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 81532#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 81888#L1508 assume !(0 != activate_threads_~tmp___1~0#1); 82389#L1508-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 81835#L650 assume !(1 == ~t3_pc~0); 81836#L650-2 is_transmit3_triggered_~__retres1~3#1 := 0; 82560#L661 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 82860#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 81488#L1516 assume !(0 != activate_threads_~tmp___2~0#1); 81489#L1516-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 82715#L669 assume 1 == ~t4_pc~0; 82716#L670 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 83089#L680 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 81571#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 81572#L1524 assume !(0 != activate_threads_~tmp___3~0#1); 81692#L1524-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 81934#L688 assume !(1 == ~t5_pc~0); 81711#L688-2 is_transmit5_triggered_~__retres1~5#1 := 0; 81712#L699 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 83232#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 82602#L1532 assume !(0 != activate_threads_~tmp___4~0#1); 82603#L1532-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 82729#L707 assume 1 == ~t6_pc~0; 83162#L708 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 82358#L718 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 81876#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 81877#L1540 assume !(0 != activate_threads_~tmp___5~0#1); 82674#L1540-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 82222#L726 assume 1 == ~t7_pc~0; 82116#L727 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 81799#L737 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 82872#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 83167#L1548 assume !(0 != activate_threads_~tmp___6~0#1); 81561#L1548-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 81562#L745 assume !(1 == ~t8_pc~0); 82023#L745-2 is_transmit8_triggered_~__retres1~8#1 := 0; 82043#L756 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 83107#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 82434#L1556 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 82435#L1556-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 82968#L764 assume 1 == ~t9_pc~0; 82220#L765 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 82053#L775 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 81952#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 81953#L1564 assume !(0 != activate_threads_~tmp___8~0#1); 81587#L1564-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 81588#L783 assume !(1 == ~t10_pc~0); 81642#L783-2 is_transmit10_triggered_~__retres1~10#1 := 0; 81643#L794 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 81842#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 82175#L1572 assume !(0 != activate_threads_~tmp___9~0#1); 82176#L1572-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 83091#L802 assume 1 == ~t11_pc~0; 83072#L803 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 81528#L813 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 81529#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 82032#L1580 assume !(0 != activate_threads_~tmp___10~0#1); 82033#L1580-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 82150#L821 assume !(1 == ~t12_pc~0); 82403#L821-2 is_transmit12_triggered_~__retres1~12#1 := 0; 82509#L832 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 81535#is_transmit12_triggered_returnLabel#1 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 81536#L1588 assume !(0 != activate_threads_~tmp___11~0#1); 83137#L1588-2 havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 82752#L1339 assume !(1 == ~M_E~0); 82753#L1339-2 assume !(1 == ~T1_E~0); 83171#L1344-1 assume !(1 == ~T2_E~0); 83172#L1349-1 assume !(1 == ~T3_E~0); 82529#L1354-1 assume !(1 == ~T4_E~0); 82530#L1359-1 assume !(1 == ~T5_E~0); 82942#L1364-1 assume !(1 == ~T6_E~0); 81984#L1369-1 assume !(1 == ~T7_E~0); 81985#L1374-1 assume !(1 == ~T8_E~0); 82917#L1379-1 assume 1 == ~T9_E~0;~T9_E~0 := 2; 83561#L1384-1 assume 1 == ~T10_E~0;~T10_E~0 := 2; 83559#L1389-1 assume !(1 == ~T11_E~0); 83557#L1394-1 assume !(1 == ~T12_E~0); 83555#L1399-1 assume !(1 == ~E_M~0); 83552#L1404-1 assume !(1 == ~E_1~0); 83550#L1409-1 assume !(1 == ~E_2~0); 83214#L1414-1 assume !(1 == ~E_3~0); 83215#L1419-1 assume 1 == ~E_4~0;~E_4~0 := 2; 83477#L1424-1 assume 1 == ~E_5~0;~E_5~0 := 2; 83475#L1429-1 assume !(1 == ~E_6~0); 83473#L1434-1 assume !(1 == ~E_7~0); 83421#L1439-1 assume !(1 == ~E_8~0); 83394#L1444-1 assume !(1 == ~E_9~0); 83374#L1449-1 assume !(1 == ~E_10~0); 83357#L1454-1 assume !(1 == ~E_11~0); 83346#L1459-1 assume 1 == ~E_12~0;~E_12~0 := 2; 83338#L1464-1 assume { :end_inline_reset_delta_events } true; 83331#L1810-2 [2023-11-12 02:04:03,721 INFO L750 eck$LassoCheckResult]: Loop: 83331#L1810-2 assume !false; 83327#L1811 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 83326#L1176-1 assume !false; 83325#L999 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 83322#L921 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 83311#L988 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 83310#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 83308#L1003 assume !(0 != eval_~tmp~0#1); 83307#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 83306#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 83305#L1201-3 assume 0 == ~M_E~0;~M_E~0 := 1; 83304#L1201-5 assume !(0 == ~T1_E~0); 83302#L1206-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 83303#L1211-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 88279#L1216-3 assume !(0 == ~T4_E~0); 88275#L1221-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 88271#L1226-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 88268#L1231-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 88265#L1236-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 88262#L1241-3 assume !(0 == ~T9_E~0); 88259#L1246-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 88256#L1251-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 88252#L1256-3 assume !(0 == ~T12_E~0); 88249#L1261-3 assume 0 == ~E_M~0;~E_M~0 := 1; 88246#L1266-3 assume 0 == ~E_1~0;~E_1~0 := 1; 88243#L1271-3 assume 0 == ~E_2~0;~E_2~0 := 1; 88240#L1276-3 assume 0 == ~E_3~0;~E_3~0 := 1; 88237#L1281-3 assume !(0 == ~E_4~0); 88233#L1286-3 assume 0 == ~E_5~0;~E_5~0 := 1; 88230#L1291-3 assume 0 == ~E_6~0;~E_6~0 := 1; 88227#L1296-3 assume !(0 == ~E_7~0); 88224#L1301-3 assume 0 == ~E_8~0;~E_8~0 := 1; 88221#L1306-3 assume 0 == ~E_9~0;~E_9~0 := 1; 88218#L1311-3 assume 0 == ~E_10~0;~E_10~0 := 1; 88214#L1316-3 assume 0 == ~E_11~0;~E_11~0 := 1; 88211#L1321-3 assume !(0 == ~E_12~0); 88208#L1326-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 88205#L593-42 assume 1 == ~m_pc~0; 88201#L594-14 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 88198#L604-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 88194#is_master_triggered_returnLabel#15 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 88191#L1492-42 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 88188#L1492-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 88185#L612-42 assume !(1 == ~t1_pc~0); 88181#L612-44 is_transmit1_triggered_~__retres1~1#1 := 0; 88178#L623-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 88173#is_transmit1_triggered_returnLabel#15 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 88170#L1500-42 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 88167#L1500-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 88164#L631-42 assume !(1 == ~t2_pc~0); 88161#L631-44 is_transmit2_triggered_~__retres1~2#1 := 0; 88157#L642-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 88152#is_transmit2_triggered_returnLabel#15 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 88149#L1508-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 88146#L1508-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 88143#L650-42 assume !(1 == ~t3_pc~0); 88139#L650-44 is_transmit3_triggered_~__retres1~3#1 := 0; 88136#L661-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 88131#is_transmit3_triggered_returnLabel#15 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 88128#L1516-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 88125#L1516-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 88122#L669-42 assume !(1 == ~t4_pc~0); 88119#L669-44 is_transmit4_triggered_~__retres1~4#1 := 0; 88115#L680-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 88110#is_transmit4_triggered_returnLabel#15 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 88107#L1524-42 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 88104#L1524-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 88101#L688-42 assume !(1 == ~t5_pc~0); 88097#L688-44 is_transmit5_triggered_~__retres1~5#1 := 0; 88094#L699-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 88089#is_transmit5_triggered_returnLabel#15 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 88086#L1532-42 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 88083#L1532-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 88080#L707-42 assume !(1 == ~t6_pc~0); 88077#L707-44 is_transmit6_triggered_~__retres1~6#1 := 0; 88073#L718-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 88068#is_transmit6_triggered_returnLabel#15 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 88065#L1540-42 assume !(0 != activate_threads_~tmp___5~0#1); 88062#L1540-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 88059#L726-42 assume 1 == ~t7_pc~0; 88055#L727-14 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 88053#L737-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 88050#is_transmit7_triggered_returnLabel#15 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 88048#L1548-42 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 88046#L1548-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 88043#L745-42 assume 1 == ~t8_pc~0; 88041#L746-14 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 88037#L756-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 88035#is_transmit8_triggered_returnLabel#15 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 88032#L1556-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 88028#L1556-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 88025#L764-42 assume 1 == ~t9_pc~0; 88021#L765-14 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 88017#L775-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 88014#is_transmit9_triggered_returnLabel#15 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 88011#L1564-42 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 88007#L1564-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 88004#L783-42 assume 1 == ~t10_pc~0; 88001#L784-14 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 87996#L794-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 87993#is_transmit10_triggered_returnLabel#15 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 87990#L1572-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 87986#L1572-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 87983#L802-42 assume 1 == ~t11_pc~0; 87979#L803-14 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 87975#L813-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 87972#is_transmit11_triggered_returnLabel#15 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 87969#L1580-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 87965#L1580-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 84083#L821-42 assume !(1 == ~t12_pc~0); 83957#L821-44 is_transmit12_triggered_~__retres1~12#1 := 0; 83955#L832-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 83953#is_transmit12_triggered_returnLabel#15 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 83951#L1588-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 83949#L1588-44 havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 83847#L1339-3 assume 1 == ~M_E~0;~M_E~0 := 2; 83845#L1339-5 assume !(1 == ~T1_E~0); 83843#L1344-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 82761#L1349-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 83840#L1354-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 83838#L1359-3 assume !(1 == ~T5_E~0); 83836#L1364-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 83834#L1369-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 83832#L1374-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 83729#L1379-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 83725#L1384-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 83723#L1389-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 83721#L1394-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 83719#L1399-3 assume !(1 == ~E_M~0); 83717#L1404-3 assume 1 == ~E_1~0;~E_1~0 := 2; 83715#L1409-3 assume 1 == ~E_2~0;~E_2~0 := 2; 83713#L1414-3 assume 1 == ~E_3~0;~E_3~0 := 2; 83648#L1419-3 assume 1 == ~E_4~0;~E_4~0 := 2; 83644#L1424-3 assume 1 == ~E_5~0;~E_5~0 := 2; 83642#L1429-3 assume 1 == ~E_6~0;~E_6~0 := 2; 83640#L1434-3 assume 1 == ~E_7~0;~E_7~0 := 2; 83638#L1439-3 assume !(1 == ~E_8~0); 83636#L1444-3 assume 1 == ~E_9~0;~E_9~0 := 2; 83634#L1449-3 assume 1 == ~E_10~0;~E_10~0 := 2; 83569#L1454-3 assume 1 == ~E_11~0;~E_11~0 := 2; 83567#L1459-3 assume 1 == ~E_12~0;~E_12~0 := 2; 83563#L1464-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 83490#L921-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 83476#L988-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 83474#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; 83434#L1829 assume !(0 == start_simulation_~tmp~3#1); 83432#L1829-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 83406#L921-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 83395#L988-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 83393#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret33#1;havoc stop_simulation_#t~ret33#1; 83373#L1784 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 83356#L1791 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 83345#stop_simulation_returnLabel#1 start_simulation_#t~ret35#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 83337#L1842 assume !(0 != start_simulation_~tmp___0~1#1); 83331#L1810-2 [2023-11-12 02:04:03,721 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-12 02:04:03,721 INFO L85 PathProgramCache]: Analyzing trace with hash 1087243328, now seen corresponding path program 1 times [2023-11-12 02:04:03,721 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-12 02:04:03,721 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [868459569] [2023-11-12 02:04:03,722 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-12 02:04:03,722 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-12 02:04:03,739 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-12 02:04:03,807 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-12 02:04:03,807 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-12 02:04:03,808 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [868459569] [2023-11-12 02:04:03,808 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [868459569] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-12 02:04:03,808 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-12 02:04:03,808 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2023-11-12 02:04:03,808 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [854892731] [2023-11-12 02:04:03,808 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-12 02:04:03,809 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-12 02:04:03,809 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-12 02:04:03,809 INFO L85 PathProgramCache]: Analyzing trace with hash -1726191326, now seen corresponding path program 1 times [2023-11-12 02:04:03,810 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-12 02:04:03,810 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1737034129] [2023-11-12 02:04:03,810 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-12 02:04:03,810 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-12 02:04:03,828 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-12 02:04:03,885 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-12 02:04:03,886 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-12 02:04:03,886 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1737034129] [2023-11-12 02:04:03,886 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1737034129] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-12 02:04:03,886 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-12 02:04:03,886 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-12 02:04:03,887 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2095215512] [2023-11-12 02:04:03,887 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-12 02:04:03,887 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-12 02:04:03,887 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-12 02:04:03,888 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-12 02:04:03,888 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-12 02:04:03,888 INFO L87 Difference]: Start difference. First operand 12585 states and 18432 transitions. cyclomatic complexity: 5855 Second operand has 3 states, 3 states have (on average 50.0) internal successors, (150), 2 states have internal predecessors, (150), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-12 02:04:04,114 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-12 02:04:04,114 INFO L93 Difference]: Finished difference Result 24784 states and 36078 transitions. [2023-11-12 02:04:04,114 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 24784 states and 36078 transitions. [2023-11-12 02:04:04,228 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 24552 [2023-11-12 02:04:04,317 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 24784 states to 24784 states and 36078 transitions. [2023-11-12 02:04:04,317 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 24784 [2023-11-12 02:04:04,349 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 24784 [2023-11-12 02:04:04,349 INFO L73 IsDeterministic]: Start isDeterministic. Operand 24784 states and 36078 transitions. [2023-11-12 02:04:04,375 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-12 02:04:04,375 INFO L218 hiAutomatonCegarLoop]: Abstraction has 24784 states and 36078 transitions. [2023-11-12 02:04:04,401 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 24784 states and 36078 transitions. [2023-11-12 02:04:04,924 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 24784 to 24064. [2023-11-12 02:04:04,954 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 24064 states, 24064 states have (on average 1.45703125) internal successors, (35062), 24063 states have internal predecessors, (35062), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-12 02:04:05,012 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 24064 states to 24064 states and 35062 transitions. [2023-11-12 02:04:05,012 INFO L240 hiAutomatonCegarLoop]: Abstraction has 24064 states and 35062 transitions. [2023-11-12 02:04:05,012 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-12 02:04:05,013 INFO L428 stractBuchiCegarLoop]: Abstraction has 24064 states and 35062 transitions. [2023-11-12 02:04:05,013 INFO L335 stractBuchiCegarLoop]: ======== Iteration 18 ============ [2023-11-12 02:04:05,014 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 24064 states and 35062 transitions. [2023-11-12 02:04:05,297 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 23832 [2023-11-12 02:04:05,297 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-12 02:04:05,297 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-12 02:04:05,300 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-12 02:04:05,300 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-12 02:04:05,301 INFO L748 eck$LassoCheckResult]: Stem: 119103#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(20, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~token~0 := 0;~local~0 := 0; 119104#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~14#1;havoc main_~__retres1~14#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1; 120000#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret34#1, start_simulation_#t~ret35#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 120001#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 120781#L848 assume 1 == ~m_i~0;~m_st~0 := 0; 120782#L848-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 119647#L853-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 119428#L858-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 118817#L863-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 118818#L868-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 120131#L873-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 120242#L878-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 120916#L883-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 120917#L888-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 119570#L893-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 119571#L898-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 120160#L903-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 120076#L908-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 119608#L1201 assume !(0 == ~M_E~0); 119609#L1201-2 assume !(0 == ~T1_E~0); 120619#L1206-1 assume !(0 == ~T2_E~0); 120584#L1211-1 assume !(0 == ~T3_E~0); 120585#L1216-1 assume !(0 == ~T4_E~0); 119407#L1221-1 assume !(0 == ~T5_E~0); 119408#L1226-1 assume !(0 == ~T6_E~0); 119029#L1231-1 assume !(0 == ~T7_E~0); 119030#L1236-1 assume !(0 == ~T8_E~0); 120665#L1241-1 assume !(0 == ~T9_E~0); 119450#L1246-1 assume !(0 == ~T10_E~0); 119451#L1251-1 assume !(0 == ~T11_E~0); 119606#L1256-1 assume !(0 == ~T12_E~0); 118825#L1261-1 assume !(0 == ~E_M~0); 118826#L1266-1 assume !(0 == ~E_1~0); 120878#L1271-1 assume !(0 == ~E_2~0); 120225#L1276-1 assume !(0 == ~E_3~0); 120226#L1281-1 assume !(0 == ~E_4~0); 120174#L1286-1 assume !(0 == ~E_5~0); 119296#L1291-1 assume !(0 == ~E_6~0); 119297#L1296-1 assume !(0 == ~E_7~0); 119927#L1301-1 assume !(0 == ~E_8~0); 119928#L1306-1 assume !(0 == ~E_9~0); 120503#L1311-1 assume !(0 == ~E_10~0); 119247#L1316-1 assume !(0 == ~E_11~0); 119248#L1321-1 assume !(0 == ~E_12~0); 119947#L1326-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 119948#L593 assume !(1 == ~m_pc~0); 119127#L593-2 is_master_triggered_~__retres1~0#1 := 0; 119128#L604 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 119828#is_master_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 119829#L1492 assume !(0 != activate_threads_~tmp~1#1); 120184#L1492-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 120544#L612 assume !(1 == ~t1_pc~0); 120545#L612-2 is_transmit1_triggered_~__retres1~1#1 := 0; 120774#L623 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 120341#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 119131#L1500 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 119132#L1500-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 119587#L631 assume 1 == ~t2_pc~0; 119508#L632 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 118906#L642 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 118907#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 119261#L1508 assume !(0 != activate_threads_~tmp___1~0#1); 119787#L1508-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 119207#L650 assume !(1 == ~t3_pc~0); 119208#L650-2 is_transmit3_triggered_~__retres1~3#1 := 0; 119974#L661 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 120316#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 118863#L1516 assume !(0 != activate_threads_~tmp___2~0#1); 118864#L1516-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 120152#L669 assume 1 == ~t4_pc~0; 120153#L670 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 120601#L680 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 118946#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 118947#L1524 assume !(0 != activate_threads_~tmp___3~0#1); 119066#L1524-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 119309#L688 assume !(1 == ~t5_pc~0); 119085#L688-2 is_transmit5_triggered_~__retres1~5#1 := 0; 119086#L699 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 120836#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 120024#L1532 assume !(0 != activate_threads_~tmp___4~0#1); 120025#L1532-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 120168#L707 assume 1 == ~t6_pc~0; 120717#L708 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 119752#L718 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 119249#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 119250#L1540 assume !(0 != activate_threads_~tmp___5~0#1); 120105#L1540-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 119607#L726 assume 1 == ~t7_pc~0; 119496#L727 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 119172#L737 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 120331#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 120724#L1548 assume !(0 != activate_threads_~tmp___6~0#1); 118936#L1548-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 118937#L745 assume !(1 == ~t8_pc~0); 119400#L745-2 is_transmit8_triggered_~__retres1~8#1 := 0; 119421#L756 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 120631#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 119838#L1556 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 119839#L1556-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 120445#L764 assume 1 == ~t9_pc~0; 119605#L765 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 119432#L775 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 119327#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 119328#L1564 assume !(0 != activate_threads_~tmp___8~0#1); 118962#L1564-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 118963#L783 assume !(1 == ~t10_pc~0); 119017#L783-2 is_transmit10_triggered_~__retres1~10#1 := 0; 119018#L794 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 119214#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 119558#L1572 assume !(0 != activate_threads_~tmp___9~0#1); 119559#L1572-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 120604#L802 assume 1 == ~t11_pc~0; 120570#L803 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 118903#L813 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 118904#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 119409#L1580 assume !(0 != activate_threads_~tmp___10~0#1); 119410#L1580-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 119531#L821 assume !(1 == ~t12_pc~0); 119803#L821-2 is_transmit12_triggered_~__retres1~12#1 := 0; 119919#L832 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 118910#is_transmit12_triggered_returnLabel#1 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 118911#L1588 assume !(0 != activate_threads_~tmp___11~0#1); 120679#L1588-2 havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 120193#L1339 assume !(1 == ~M_E~0); 120194#L1339-2 assume !(1 == ~T1_E~0); 120728#L1344-1 assume !(1 == ~T2_E~0); 120729#L1349-1 assume !(1 == ~T3_E~0); 119940#L1354-1 assume !(1 == ~T4_E~0); 119941#L1359-1 assume !(1 == ~T5_E~0); 134011#L1364-1 assume !(1 == ~T6_E~0); 134009#L1369-1 assume !(1 == ~T7_E~0); 134007#L1374-1 assume !(1 == ~T8_E~0); 134005#L1379-1 assume 1 == ~T9_E~0;~T9_E~0 := 2; 133687#L1384-1 assume 1 == ~T10_E~0;~T10_E~0 := 2; 133684#L1389-1 assume !(1 == ~T11_E~0); 133682#L1394-1 assume !(1 == ~T12_E~0); 133680#L1399-1 assume !(1 == ~E_M~0); 133448#L1404-1 assume !(1 == ~E_1~0); 133313#L1409-1 assume !(1 == ~E_2~0); 133226#L1414-1 assume !(1 == ~E_3~0); 133223#L1419-1 assume 1 == ~E_4~0;~E_4~0 := 2; 133222#L1424-1 assume 1 == ~E_5~0;~E_5~0 := 2; 133221#L1429-1 assume !(1 == ~E_6~0); 133220#L1434-1 assume !(1 == ~E_7~0); 133219#L1439-1 assume !(1 == ~E_8~0); 133218#L1444-1 assume !(1 == ~E_9~0); 133217#L1449-1 assume !(1 == ~E_10~0); 133216#L1454-1 assume !(1 == ~E_11~0); 133214#L1459-1 assume 1 == ~E_12~0;~E_12~0 := 2; 133215#L1464-1 assume { :end_inline_reset_delta_events } true; 133263#L1810-2 [2023-11-12 02:04:05,301 INFO L750 eck$LassoCheckResult]: Loop: 133263#L1810-2 assume !false; 133154#L1811 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 133152#L1176-1 assume !false; 133150#L999 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 132942#L921 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 132931#L988 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 132930#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 132928#L1003 assume !(0 != eval_~tmp~0#1); 132929#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 141176#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 141173#L1201-3 assume 0 == ~M_E~0;~M_E~0 := 1; 141171#L1201-5 assume !(0 == ~T1_E~0); 141169#L1206-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 141167#L1211-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 141165#L1216-3 assume !(0 == ~T4_E~0); 141163#L1221-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 141160#L1226-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 141158#L1231-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 141156#L1236-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 141154#L1241-3 assume !(0 == ~T9_E~0); 141152#L1246-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 141150#L1251-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 141147#L1256-3 assume !(0 == ~T12_E~0); 141145#L1261-3 assume 0 == ~E_M~0;~E_M~0 := 1; 141143#L1266-3 assume 0 == ~E_1~0;~E_1~0 := 1; 141141#L1271-3 assume 0 == ~E_2~0;~E_2~0 := 1; 141139#L1276-3 assume 0 == ~E_3~0;~E_3~0 := 1; 141137#L1281-3 assume !(0 == ~E_4~0); 141134#L1286-3 assume 0 == ~E_5~0;~E_5~0 := 1; 141132#L1291-3 assume 0 == ~E_6~0;~E_6~0 := 1; 141130#L1296-3 assume !(0 == ~E_7~0); 141128#L1301-3 assume 0 == ~E_8~0;~E_8~0 := 1; 141126#L1306-3 assume 0 == ~E_9~0;~E_9~0 := 1; 141124#L1311-3 assume 0 == ~E_10~0;~E_10~0 := 1; 141121#L1316-3 assume 0 == ~E_11~0;~E_11~0 := 1; 141119#L1321-3 assume !(0 == ~E_12~0); 141117#L1326-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 141115#L593-42 assume !(1 == ~m_pc~0); 141113#L593-44 is_master_triggered_~__retres1~0#1 := 0; 141111#L604-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 141108#is_master_triggered_returnLabel#15 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 141106#L1492-42 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 141104#L1492-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 141102#L612-42 assume !(1 == ~t1_pc~0); 141099#L612-44 is_transmit1_triggered_~__retres1~1#1 := 0; 141097#L623-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 141094#is_transmit1_triggered_returnLabel#15 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 141092#L1500-42 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 141091#L1500-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 141090#L631-42 assume 1 == ~t2_pc~0; 141088#L632-14 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 141087#L642-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 141086#is_transmit2_triggered_returnLabel#15 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 141085#L1508-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 141083#L1508-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 141081#L650-42 assume !(1 == ~t3_pc~0); 141078#L650-44 is_transmit3_triggered_~__retres1~3#1 := 0; 141076#L661-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 141074#is_transmit3_triggered_returnLabel#15 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 141072#L1516-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 141070#L1516-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 141068#L669-42 assume !(1 == ~t4_pc~0); 141066#L669-44 is_transmit4_triggered_~__retres1~4#1 := 0; 141063#L680-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 141061#is_transmit4_triggered_returnLabel#15 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 141059#L1524-42 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 141057#L1524-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 141055#L688-42 assume !(1 == ~t5_pc~0); 141052#L688-44 is_transmit5_triggered_~__retres1~5#1 := 0; 141050#L699-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 141048#is_transmit5_triggered_returnLabel#15 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 141046#L1532-42 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 141044#L1532-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 141042#L707-42 assume !(1 == ~t6_pc~0); 141040#L707-44 is_transmit6_triggered_~__retres1~6#1 := 0; 141037#L718-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 141035#is_transmit6_triggered_returnLabel#15 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 141033#L1540-42 assume !(0 != activate_threads_~tmp___5~0#1); 141031#L1540-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 141029#L726-42 assume 1 == ~t7_pc~0; 141026#L727-14 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 141024#L737-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 141022#is_transmit7_triggered_returnLabel#15 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 141020#L1548-42 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 141018#L1548-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 141016#L745-42 assume 1 == ~t8_pc~0; 141014#L746-14 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 141011#L756-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 141009#is_transmit8_triggered_returnLabel#15 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 141006#L1556-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 141004#L1556-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 141002#L764-42 assume 1 == ~t9_pc~0; 140999#L765-14 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 140997#L775-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 140995#is_transmit9_triggered_returnLabel#15 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 140992#L1564-42 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 140990#L1564-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 140988#L783-42 assume 1 == ~t10_pc~0; 140986#L784-14 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 140983#L794-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 140981#is_transmit10_triggered_returnLabel#15 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 140978#L1572-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 140976#L1572-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 140974#L802-42 assume 1 == ~t11_pc~0; 140971#L803-14 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 140969#L813-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 140967#is_transmit11_triggered_returnLabel#15 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 140964#L1580-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 140962#L1580-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 140960#L821-42 assume 1 == ~t12_pc~0; 140958#L822-14 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 140955#L832-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 140953#is_transmit12_triggered_returnLabel#15 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 140950#L1588-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 140948#L1588-44 havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 137708#L1339-3 assume 1 == ~M_E~0;~M_E~0 := 2; 137706#L1339-5 assume !(1 == ~T1_E~0); 137704#L1344-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 122130#L1349-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 137700#L1354-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 137698#L1359-3 assume !(1 == ~T5_E~0); 137696#L1364-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 137694#L1369-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 137692#L1374-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 137689#L1379-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 137686#L1384-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 137684#L1389-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 137682#L1394-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 135757#L1399-3 assume !(1 == ~E_M~0); 135754#L1404-3 assume 1 == ~E_1~0;~E_1~0 := 2; 135752#L1409-3 assume 1 == ~E_2~0;~E_2~0 := 2; 135750#L1414-3 assume 1 == ~E_3~0;~E_3~0 := 2; 135748#L1419-3 assume 1 == ~E_4~0;~E_4~0 := 2; 134872#L1424-3 assume 1 == ~E_5~0;~E_5~0 := 2; 135745#L1429-3 assume 1 == ~E_6~0;~E_6~0 := 2; 135742#L1434-3 assume 1 == ~E_7~0;~E_7~0 := 2; 135740#L1439-3 assume !(1 == ~E_8~0); 135738#L1444-3 assume 1 == ~E_9~0;~E_9~0 := 2; 135736#L1449-3 assume 1 == ~E_10~0;~E_10~0 := 2; 135734#L1454-3 assume 1 == ~E_11~0;~E_11~0 := 2; 135732#L1459-3 assume 1 == ~E_12~0;~E_12~0 := 2; 134407#L1464-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 134762#L921-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 134748#L988-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 134746#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; 134738#L1829 assume !(0 == start_simulation_~tmp~3#1); 134736#L1829-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 134156#L921-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 134144#L988-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 134143#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret33#1;havoc stop_simulation_#t~ret33#1; 134141#L1784 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 133791#L1791 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 133529#stop_simulation_returnLabel#1 start_simulation_#t~ret35#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 133367#L1842 assume !(0 != start_simulation_~tmp___0~1#1); 133263#L1810-2 [2023-11-12 02:04:05,302 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-12 02:04:05,302 INFO L85 PathProgramCache]: Analyzing trace with hash 1374703233, now seen corresponding path program 1 times [2023-11-12 02:04:05,302 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-12 02:04:05,303 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1239714766] [2023-11-12 02:04:05,303 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-12 02:04:05,303 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-12 02:04:05,321 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-12 02:04:05,470 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-12 02:04:05,471 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-12 02:04:05,471 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1239714766] [2023-11-12 02:04:05,471 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1239714766] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-12 02:04:05,471 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-12 02:04:05,472 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2023-11-12 02:04:05,472 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [90764702] [2023-11-12 02:04:05,472 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-12 02:04:05,473 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-12 02:04:05,473 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-12 02:04:05,473 INFO L85 PathProgramCache]: Analyzing trace with hash -1722661407, now seen corresponding path program 1 times [2023-11-12 02:04:05,473 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-12 02:04:05,474 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1309186199] [2023-11-12 02:04:05,474 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-12 02:04:05,474 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-12 02:04:05,497 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-12 02:04:05,559 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-12 02:04:05,559 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-12 02:04:05,559 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1309186199] [2023-11-12 02:04:05,559 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1309186199] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-12 02:04:05,560 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-12 02:04:05,560 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-12 02:04:05,560 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [119634408] [2023-11-12 02:04:05,560 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-12 02:04:05,561 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-12 02:04:05,561 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-12 02:04:05,562 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2023-11-12 02:04:05,562 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2023-11-12 02:04:05,562 INFO L87 Difference]: Start difference. First operand 24064 states and 35062 transitions. cyclomatic complexity: 11014 Second operand has 5 states, 5 states have (on average 30.0) internal successors, (150), 5 states have internal predecessors, (150), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-12 02:04:06,266 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-12 02:04:06,266 INFO L93 Difference]: Finished difference Result 64352 states and 92834 transitions. [2023-11-12 02:04:06,266 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 64352 states and 92834 transitions. [2023-11-12 02:04:06,697 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 63864 [2023-11-12 02:04:07,036 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 64352 states to 64352 states and 92834 transitions. [2023-11-12 02:04:07,037 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 64352 [2023-11-12 02:04:07,082 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 64352 [2023-11-12 02:04:07,083 INFO L73 IsDeterministic]: Start isDeterministic. Operand 64352 states and 92834 transitions. [2023-11-12 02:04:07,174 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-12 02:04:07,175 INFO L218 hiAutomatonCegarLoop]: Abstraction has 64352 states and 92834 transitions. [2023-11-12 02:04:07,229 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 64352 states and 92834 transitions. [2023-11-12 02:04:07,815 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 64352 to 24715. [2023-11-12 02:04:07,847 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 24715 states, 24715 states have (on average 1.4449929192797897) internal successors, (35713), 24714 states have internal predecessors, (35713), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-12 02:04:07,925 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 24715 states to 24715 states and 35713 transitions. [2023-11-12 02:04:07,926 INFO L240 hiAutomatonCegarLoop]: Abstraction has 24715 states and 35713 transitions. [2023-11-12 02:04:07,927 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2023-11-12 02:04:07,927 INFO L428 stractBuchiCegarLoop]: Abstraction has 24715 states and 35713 transitions. [2023-11-12 02:04:07,927 INFO L335 stractBuchiCegarLoop]: ======== Iteration 19 ============ [2023-11-12 02:04:07,927 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 24715 states and 35713 transitions. [2023-11-12 02:04:08,144 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 24480 [2023-11-12 02:04:08,144 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-12 02:04:08,144 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-12 02:04:08,147 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-12 02:04:08,147 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-12 02:04:08,148 INFO L748 eck$LassoCheckResult]: Stem: 207534#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(20, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~token~0 := 0;~local~0 := 0; 207535#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~14#1;havoc main_~__retres1~14#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1; 208420#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret34#1, start_simulation_#t~ret35#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 208421#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 209144#L848 assume 1 == ~m_i~0;~m_st~0 := 0; 209145#L848-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 208080#L853-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 207858#L858-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 207246#L863-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 207247#L868-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 208549#L873-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 208659#L878-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 209260#L883-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 209261#L888-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 208002#L893-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 208003#L898-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 208577#L903-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 208492#L908-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 208040#L1201 assume !(0 == ~M_E~0); 208041#L1201-2 assume !(0 == ~T1_E~0); 209005#L1206-1 assume !(0 == ~T2_E~0); 208980#L1211-1 assume !(0 == ~T3_E~0); 208981#L1216-1 assume !(0 == ~T4_E~0); 207838#L1221-1 assume !(0 == ~T5_E~0); 207839#L1226-1 assume !(0 == ~T6_E~0); 207460#L1231-1 assume !(0 == ~T7_E~0); 207461#L1236-1 assume !(0 == ~T8_E~0); 209038#L1241-1 assume !(0 == ~T9_E~0); 207880#L1246-1 assume !(0 == ~T10_E~0); 207881#L1251-1 assume !(0 == ~T11_E~0); 208038#L1256-1 assume !(0 == ~T12_E~0); 207254#L1261-1 assume !(0 == ~E_M~0); 207255#L1266-1 assume !(0 == ~E_1~0); 209233#L1271-1 assume !(0 == ~E_2~0); 208642#L1276-1 assume !(0 == ~E_3~0); 208643#L1281-1 assume !(0 == ~E_4~0); 208589#L1286-1 assume !(0 == ~E_5~0); 207729#L1291-1 assume !(0 == ~E_6~0); 207730#L1296-1 assume !(0 == ~E_7~0); 208347#L1301-1 assume !(0 == ~E_8~0); 208348#L1306-1 assume !(0 == ~E_9~0); 208899#L1311-1 assume !(0 == ~E_10~0); 207679#L1316-1 assume !(0 == ~E_11~0); 207680#L1321-1 assume !(0 == ~E_12~0); 208369#L1326-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 208370#L593 assume !(1 == ~m_pc~0); 207558#L593-2 is_master_triggered_~__retres1~0#1 := 0; 207559#L604 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 208250#is_master_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 208251#L1492 assume !(0 != activate_threads_~tmp~1#1); 208600#L1492-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 208942#L612 assume !(1 == ~t1_pc~0); 208943#L612-2 is_transmit1_triggered_~__retres1~1#1 := 0; 209249#L623 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 209250#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 207562#L1500 assume !(0 != activate_threads_~tmp___0~0#1); 207563#L1500-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 208019#L631 assume 1 == ~t2_pc~0; 207941#L632 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 207335#L642 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 207336#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 207693#L1508 assume !(0 != activate_threads_~tmp___1~0#1); 208211#L1508-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 207638#L650 assume !(1 == ~t3_pc~0); 207639#L650-2 is_transmit3_triggered_~__retres1~3#1 := 0; 208396#L661 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 208730#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 207292#L1516 assume !(0 != activate_threads_~tmp___2~0#1); 207293#L1516-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 208569#L669 assume 1 == ~t4_pc~0; 208570#L670 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 208992#L680 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 207375#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 207376#L1524 assume !(0 != activate_threads_~tmp___3~0#1); 207497#L1524-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 207740#L688 assume !(1 == ~t5_pc~0); 207516#L688-2 is_transmit5_triggered_~__retres1~5#1 := 0; 207517#L699 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 209197#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 208442#L1532 assume !(0 != activate_threads_~tmp___4~0#1); 208443#L1532-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 208584#L707 assume 1 == ~t6_pc~0; 209088#L708 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 208178#L718 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 207681#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 207682#L1540 assume !(0 != activate_threads_~tmp___5~0#1); 208524#L1540-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 208039#L726 assume 1 == ~t7_pc~0; 207929#L727 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 207603#L737 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 208743#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 209097#L1548 assume !(0 != activate_threads_~tmp___6~0#1); 207365#L1548-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 207366#L745 assume !(1 == ~t8_pc~0); 207831#L745-2 is_transmit8_triggered_~__retres1~8#1 := 0; 207852#L756 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 209014#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 208259#L1556 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 208260#L1556-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 208850#L764 assume 1 == ~t9_pc~0; 208037#L765 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 207862#L775 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 207758#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 207759#L1564 assume !(0 != activate_threads_~tmp___8~0#1); 207391#L1564-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 207392#L783 assume !(1 == ~t10_pc~0); 207448#L783-2 is_transmit10_triggered_~__retres1~10#1 := 0; 207449#L794 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 207645#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 207990#L1572 assume !(0 != activate_threads_~tmp___9~0#1); 207991#L1572-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 208994#L802 assume 1 == ~t11_pc~0; 208969#L803 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 207332#L813 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 207333#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 207840#L1580 assume !(0 != activate_threads_~tmp___10~0#1); 207841#L1580-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 207963#L821 assume !(1 == ~t12_pc~0); 208226#L821-2 is_transmit12_triggered_~__retres1~12#1 := 0; 208335#L832 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 207339#is_transmit12_triggered_returnLabel#1 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 207340#L1588 assume !(0 != activate_threads_~tmp___11~0#1); 209052#L1588-2 havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 208609#L1339 assume !(1 == ~M_E~0); 208610#L1339-2 assume !(1 == ~T1_E~0); 209104#L1344-1 assume !(1 == ~T2_E~0); 209105#L1349-1 assume !(1 == ~T3_E~0); 210691#L1354-1 assume !(1 == ~T4_E~0); 210690#L1359-1 assume !(1 == ~T5_E~0); 210689#L1364-1 assume !(1 == ~T6_E~0); 210688#L1369-1 assume !(1 == ~T7_E~0); 210687#L1374-1 assume !(1 == ~T8_E~0); 210685#L1379-1 assume 1 == ~T9_E~0;~T9_E~0 := 2; 210686#L1384-1 assume 1 == ~T10_E~0;~T10_E~0 := 2; 210731#L1389-1 assume !(1 == ~T11_E~0); 210729#L1394-1 assume !(1 == ~T12_E~0); 210727#L1399-1 assume !(1 == ~E_M~0); 210705#L1404-1 assume !(1 == ~E_1~0); 210697#L1409-1 assume !(1 == ~E_2~0); 209170#L1414-1 assume !(1 == ~E_3~0); 209171#L1419-1 assume 1 == ~E_4~0;~E_4~0 := 2; 210645#L1424-1 assume 1 == ~E_5~0;~E_5~0 := 2; 210618#L1429-1 assume !(1 == ~E_6~0); 210592#L1434-1 assume !(1 == ~E_7~0); 210577#L1439-1 assume !(1 == ~E_8~0); 210564#L1444-1 assume !(1 == ~E_9~0); 210562#L1449-1 assume !(1 == ~E_10~0); 210549#L1454-1 assume !(1 == ~E_11~0); 210538#L1459-1 assume 1 == ~E_12~0;~E_12~0 := 2; 210530#L1464-1 assume { :end_inline_reset_delta_events } true; 210523#L1810-2 [2023-11-12 02:04:08,149 INFO L750 eck$LassoCheckResult]: Loop: 210523#L1810-2 assume !false; 210519#L1811 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 210518#L1176-1 assume !false; 210517#L999 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 210514#L921 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 210503#L988 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 210502#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 210500#L1003 assume !(0 != eval_~tmp~0#1); 210499#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 210498#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 210497#L1201-3 assume 0 == ~M_E~0;~M_E~0 := 1; 210496#L1201-5 assume !(0 == ~T1_E~0); 210493#L1206-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 210494#L1211-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 214490#L1216-3 assume !(0 == ~T4_E~0); 214489#L1221-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 214488#L1226-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 214487#L1231-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 214486#L1236-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 214485#L1241-3 assume !(0 == ~T9_E~0); 214484#L1246-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 214483#L1251-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 214482#L1256-3 assume !(0 == ~T12_E~0); 214481#L1261-3 assume 0 == ~E_M~0;~E_M~0 := 1; 214480#L1266-3 assume 0 == ~E_1~0;~E_1~0 := 1; 214479#L1271-3 assume 0 == ~E_2~0;~E_2~0 := 1; 214478#L1276-3 assume 0 == ~E_3~0;~E_3~0 := 1; 214477#L1281-3 assume !(0 == ~E_4~0); 214476#L1286-3 assume 0 == ~E_5~0;~E_5~0 := 1; 214475#L1291-3 assume 0 == ~E_6~0;~E_6~0 := 1; 214474#L1296-3 assume !(0 == ~E_7~0); 214473#L1301-3 assume 0 == ~E_8~0;~E_8~0 := 1; 214472#L1306-3 assume 0 == ~E_9~0;~E_9~0 := 1; 214471#L1311-3 assume 0 == ~E_10~0;~E_10~0 := 1; 214470#L1316-3 assume 0 == ~E_11~0;~E_11~0 := 1; 214469#L1321-3 assume !(0 == ~E_12~0); 214468#L1326-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 214467#L593-42 assume !(1 == ~m_pc~0); 214466#L593-44 is_master_triggered_~__retres1~0#1 := 0; 214465#L604-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 214464#is_master_triggered_returnLabel#15 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 214463#L1492-42 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 214462#L1492-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 214461#L612-42 assume 1 == ~t1_pc~0; 214459#L613-14 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 214457#L623-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 214455#is_transmit1_triggered_returnLabel#15 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 214453#L1500-42 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 214451#L1500-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 214449#L631-42 assume !(1 == ~t2_pc~0); 214447#L631-44 is_transmit2_triggered_~__retres1~2#1 := 0; 214443#L642-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 214441#is_transmit2_triggered_returnLabel#15 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 214439#L1508-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 214437#L1508-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 214436#L650-42 assume 1 == ~t3_pc~0; 214435#L651-14 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 214433#L661-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 214432#is_transmit3_triggered_returnLabel#15 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 214431#L1516-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 214430#L1516-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 214429#L669-42 assume !(1 == ~t4_pc~0); 214233#L669-44 is_transmit4_triggered_~__retres1~4#1 := 0; 214230#L680-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 214228#is_transmit4_triggered_returnLabel#15 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 214226#L1524-42 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 214224#L1524-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 214223#L688-42 assume 1 == ~t5_pc~0; 214222#L689-14 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 214218#L699-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 214216#is_transmit5_triggered_returnLabel#15 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 214214#L1532-42 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 214212#L1532-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 214210#L707-42 assume !(1 == ~t6_pc~0); 214208#L707-44 is_transmit6_triggered_~__retres1~6#1 := 0; 214204#L718-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 214202#is_transmit6_triggered_returnLabel#15 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 214200#L1540-42 assume !(0 != activate_threads_~tmp___5~0#1); 214198#L1540-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 214196#L726-42 assume !(1 == ~t7_pc~0); 214193#L726-44 is_transmit7_triggered_~__retres1~7#1 := 0; 214190#L737-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 214188#is_transmit7_triggered_returnLabel#15 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 214185#L1548-42 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 214183#L1548-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 214181#L745-42 assume 1 == ~t8_pc~0; 214179#L746-14 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 214176#L756-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 213552#is_transmit8_triggered_returnLabel#15 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 213549#L1556-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 213547#L1556-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 213545#L764-42 assume !(1 == ~t9_pc~0); 213543#L764-44 is_transmit9_triggered_~__retres1~9#1 := 0; 213540#L775-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 213538#is_transmit9_triggered_returnLabel#15 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 213535#L1564-42 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 213533#L1564-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 212090#L783-42 assume 1 == ~t10_pc~0; 212087#L784-14 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 212083#L794-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 212082#is_transmit10_triggered_returnLabel#15 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 212080#L1572-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 212078#L1572-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 211964#L802-42 assume !(1 == ~t11_pc~0); 211133#L802-44 is_transmit11_triggered_~__retres1~11#1 := 0; 211129#L813-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 211127#is_transmit11_triggered_returnLabel#15 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 211125#L1580-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 211123#L1580-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 211121#L821-42 assume 1 == ~t12_pc~0; 211006#L822-14 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 211003#L832-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 211001#is_transmit12_triggered_returnLabel#15 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 210999#L1588-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 210955#L1588-44 havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 210953#L1339-3 assume 1 == ~M_E~0;~M_E~0 := 2; 210951#L1339-5 assume !(1 == ~T1_E~0); 210949#L1344-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 208619#L1349-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 210946#L1354-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 210944#L1359-3 assume !(1 == ~T5_E~0); 210942#L1364-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 210940#L1369-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 210938#L1374-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 210929#L1379-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 207737#L1384-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 210916#L1389-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 210865#L1394-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 210825#L1399-3 assume !(1 == ~E_M~0); 210819#L1404-3 assume 1 == ~E_1~0;~E_1~0 := 2; 210813#L1409-3 assume 1 == ~E_2~0;~E_2~0 := 2; 210792#L1414-3 assume 1 == ~E_3~0;~E_3~0 := 2; 210790#L1419-3 assume 1 == ~E_4~0;~E_4~0 := 2; 210754#L1424-3 assume 1 == ~E_5~0;~E_5~0 := 2; 210752#L1429-3 assume 1 == ~E_6~0;~E_6~0 := 2; 210750#L1434-3 assume 1 == ~E_7~0;~E_7~0 := 2; 210748#L1439-3 assume !(1 == ~E_8~0); 210725#L1444-3 assume 1 == ~E_9~0;~E_9~0 := 2; 210723#L1449-3 assume 1 == ~E_10~0;~E_10~0 := 2; 210721#L1454-3 assume 1 == ~E_11~0;~E_11~0 := 2; 210704#L1459-3 assume 1 == ~E_12~0;~E_12~0 := 2; 210696#L1464-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 210662#L921-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 210648#L988-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 210646#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; 210642#L1829 assume !(0 == start_simulation_~tmp~3#1); 210641#L1829-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 210615#L921-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 210591#L988-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 210576#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret33#1;havoc stop_simulation_#t~ret33#1; 210561#L1784 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 210548#L1791 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 210537#stop_simulation_returnLabel#1 start_simulation_#t~ret35#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 210529#L1842 assume !(0 != start_simulation_~tmp___0~1#1); 210523#L1810-2 [2023-11-12 02:04:08,150 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-12 02:04:08,150 INFO L85 PathProgramCache]: Analyzing trace with hash -1568878845, now seen corresponding path program 1 times [2023-11-12 02:04:08,150 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-12 02:04:08,151 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1366136593] [2023-11-12 02:04:08,151 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-12 02:04:08,151 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-12 02:04:08,175 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-12 02:04:08,258 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-12 02:04:08,258 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-12 02:04:08,258 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1366136593] [2023-11-12 02:04:08,258 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1366136593] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-12 02:04:08,258 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-12 02:04:08,259 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-12 02:04:08,259 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [863307885] [2023-11-12 02:04:08,259 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-12 02:04:08,260 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-12 02:04:08,261 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-12 02:04:08,261 INFO L85 PathProgramCache]: Analyzing trace with hash 52712866, now seen corresponding path program 1 times [2023-11-12 02:04:08,261 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-12 02:04:08,261 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [741768480] [2023-11-12 02:04:08,261 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-12 02:04:08,262 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-12 02:04:08,284 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-12 02:04:08,335 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-12 02:04:08,335 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-12 02:04:08,336 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [741768480] [2023-11-12 02:04:08,336 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [741768480] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-12 02:04:08,338 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-12 02:04:08,339 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-12 02:04:08,339 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1274415478] [2023-11-12 02:04:08,339 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-12 02:04:08,340 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-12 02:04:08,340 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-12 02:04:08,341 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2023-11-12 02:04:08,341 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2023-11-12 02:04:08,341 INFO L87 Difference]: Start difference. First operand 24715 states and 35713 transitions. cyclomatic complexity: 11014 Second operand has 4 states, 4 states have (on average 37.5) internal successors, (150), 3 states have internal predecessors, (150), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-12 02:04:08,869 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-12 02:04:08,869 INFO L93 Difference]: Finished difference Result 60338 states and 86601 transitions. [2023-11-12 02:04:08,870 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 60338 states and 86601 transitions. [2023-11-12 02:04:09,265 INFO L131 ngComponentsAnalysis]: Automaton has 24 accepting balls. 59296 [2023-11-12 02:04:09,603 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 60338 states to 60338 states and 86601 transitions. [2023-11-12 02:04:09,603 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 60338 [2023-11-12 02:04:09,633 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 60338 [2023-11-12 02:04:09,633 INFO L73 IsDeterministic]: Start isDeterministic. Operand 60338 states and 86601 transitions. [2023-11-12 02:04:09,709 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-12 02:04:09,709 INFO L218 hiAutomatonCegarLoop]: Abstraction has 60338 states and 86601 transitions. [2023-11-12 02:04:09,752 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 60338 states and 86601 transitions. [2023-11-12 02:04:10,521 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 60338 to 47426. [2023-11-12 02:04:10,574 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 47426 states, 47426 states have (on average 1.4392105596086535) internal successors, (68256), 47425 states have internal predecessors, (68256), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-12 02:04:10,679 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 47426 states to 47426 states and 68256 transitions. [2023-11-12 02:04:10,679 INFO L240 hiAutomatonCegarLoop]: Abstraction has 47426 states and 68256 transitions. [2023-11-12 02:04:10,680 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2023-11-12 02:04:10,680 INFO L428 stractBuchiCegarLoop]: Abstraction has 47426 states and 68256 transitions. [2023-11-12 02:04:10,680 INFO L335 stractBuchiCegarLoop]: ======== Iteration 20 ============ [2023-11-12 02:04:10,681 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 47426 states and 68256 transitions. [2023-11-12 02:04:11,103 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 47184 [2023-11-12 02:04:11,112 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-12 02:04:11,112 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-12 02:04:11,114 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-12 02:04:11,114 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-12 02:04:11,115 INFO L748 eck$LassoCheckResult]: Stem: 292596#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(20, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~token~0 := 0;~local~0 := 0; 292597#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~14#1;havoc main_~__retres1~14#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1; 293479#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret34#1, start_simulation_#t~ret35#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 293480#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 294155#L848 assume 1 == ~m_i~0;~m_st~0 := 0; 294156#L848-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 293132#L853-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 292918#L858-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 292309#L863-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 292310#L868-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 293600#L873-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 293712#L878-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 294260#L883-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 294261#L888-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 293051#L893-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 293052#L898-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 293630#L903-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 293548#L908-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 293090#L1201 assume !(0 == ~M_E~0); 293091#L1201-2 assume !(0 == ~T1_E~0); 294038#L1206-1 assume !(0 == ~T2_E~0); 294017#L1211-1 assume !(0 == ~T3_E~0); 294018#L1216-1 assume !(0 == ~T4_E~0); 292900#L1221-1 assume !(0 == ~T5_E~0); 292901#L1226-1 assume !(0 == ~T6_E~0); 292522#L1231-1 assume !(0 == ~T7_E~0); 292523#L1236-1 assume !(0 == ~T8_E~0); 294066#L1241-1 assume !(0 == ~T9_E~0); 292941#L1246-1 assume !(0 == ~T10_E~0); 292942#L1251-1 assume !(0 == ~T11_E~0); 293088#L1256-1 assume !(0 == ~T12_E~0); 292317#L1261-1 assume !(0 == ~E_M~0); 292318#L1266-1 assume !(0 == ~E_1~0); 294237#L1271-1 assume !(0 == ~E_2~0); 293692#L1276-1 assume !(0 == ~E_3~0); 293693#L1281-1 assume !(0 == ~E_4~0); 293642#L1286-1 assume !(0 == ~E_5~0); 292789#L1291-1 assume !(0 == ~E_6~0); 292790#L1296-1 assume !(0 == ~E_7~0); 293411#L1301-1 assume !(0 == ~E_8~0); 293412#L1306-1 assume !(0 == ~E_9~0); 293941#L1311-1 assume !(0 == ~E_10~0); 292739#L1316-1 assume !(0 == ~E_11~0); 292740#L1321-1 assume !(0 == ~E_12~0); 293430#L1326-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 293431#L593 assume !(1 == ~m_pc~0); 292620#L593-2 is_master_triggered_~__retres1~0#1 := 0; 292621#L604 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 293305#is_master_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 293306#L1492 assume !(0 != activate_threads_~tmp~1#1); 293653#L1492-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 293979#L612 assume !(1 == ~t1_pc~0); 293980#L612-2 is_transmit1_triggered_~__retres1~1#1 := 0; 294254#L623 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 293802#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 292624#L1500 assume !(0 != activate_threads_~tmp___0~0#1); 292625#L1500-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 293068#L631 assume !(1 == ~t2_pc~0); 293069#L631-2 is_transmit2_triggered_~__retres1~2#1 := 0; 292397#L642 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 292398#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 292753#L1508 assume !(0 != activate_threads_~tmp___1~0#1); 293266#L1508-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 292702#L650 assume !(1 == ~t3_pc~0); 292703#L650-2 is_transmit3_triggered_~__retres1~3#1 := 0; 293456#L661 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 293780#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 292355#L1516 assume !(0 != activate_threads_~tmp___2~0#1); 292356#L1516-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 293622#L669 assume 1 == ~t4_pc~0; 293623#L670 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 294028#L680 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 292441#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 292442#L1524 assume !(0 != activate_threads_~tmp___3~0#1); 292559#L1524-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 292800#L688 assume !(1 == ~t5_pc~0); 292578#L688-2 is_transmit5_triggered_~__retres1~5#1 := 0; 292579#L699 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 294206#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 293501#L1532 assume !(0 != activate_threads_~tmp___4~0#1); 293502#L1532-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 293640#L707 assume 1 == ~t6_pc~0; 294108#L708 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 293235#L718 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 292741#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 292742#L1540 assume !(0 != activate_threads_~tmp___5~0#1); 293581#L1540-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 293089#L726 assume 1 == ~t7_pc~0; 292986#L727 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 292665#L737 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 293794#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 294119#L1548 assume !(0 != activate_threads_~tmp___6~0#1); 292427#L1548-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 292428#L745 assume !(1 == ~t8_pc~0); 292893#L745-2 is_transmit8_triggered_~__retres1~8#1 := 0; 292912#L756 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 294045#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 293314#L1556 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 293315#L1556-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 293895#L764 assume 1 == ~t9_pc~0; 293087#L765 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 292922#L775 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 292819#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 292820#L1564 assume !(0 != activate_threads_~tmp___8~0#1); 292453#L1564-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 292454#L783 assume !(1 == ~t10_pc~0); 292509#L783-2 is_transmit10_triggered_~__retres1~10#1 := 0; 292510#L794 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 292707#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 293046#L1572 assume !(0 != activate_threads_~tmp___9~0#1); 293047#L1572-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 294029#L802 assume 1 == ~t11_pc~0; 294006#L803 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 292394#L813 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 292395#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 292902#L1580 assume !(0 != activate_threads_~tmp___10~0#1); 292903#L1580-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 293016#L821 assume !(1 == ~t12_pc~0); 293281#L821-2 is_transmit12_triggered_~__retres1~12#1 := 0; 293401#L832 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 292403#is_transmit12_triggered_returnLabel#1 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 292404#L1588 assume !(0 != activate_threads_~tmp___11~0#1); 294080#L1588-2 havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 293661#L1339 assume !(1 == ~M_E~0); 293662#L1339-2 assume !(1 == ~T1_E~0); 294121#L1344-1 assume !(1 == ~T2_E~0); 294122#L1349-1 assume !(1 == ~T3_E~0); 293424#L1354-1 assume !(1 == ~T4_E~0); 293425#L1359-1 assume !(1 == ~T5_E~0); 294256#L1364-1 assume !(1 == ~T6_E~0); 294257#L1369-1 assume !(1 == ~T7_E~0); 293837#L1374-1 assume !(1 == ~T8_E~0); 293838#L1379-1 assume 1 == ~T9_E~0;~T9_E~0 := 2; 293543#L1384-1 assume 1 == ~T10_E~0;~T10_E~0 := 2; 293544#L1389-1 assume !(1 == ~T11_E~0); 294071#L1394-1 assume !(1 == ~T12_E~0); 294072#L1399-1 assume !(1 == ~E_M~0); 294196#L1404-1 assume !(1 == ~E_1~0); 294197#L1409-1 assume !(1 == ~E_2~0); 294176#L1414-1 assume !(1 == ~E_3~0); 294177#L1419-1 assume 1 == ~E_4~0;~E_4~0 := 2; 292568#L1424-1 assume 1 == ~E_5~0;~E_5~0 := 2; 292569#L1429-1 assume !(1 == ~E_6~0); 294092#L1434-1 assume !(1 == ~E_7~0); 294093#L1439-1 assume !(1 == ~E_8~0); 292610#L1444-1 assume !(1 == ~E_9~0); 292611#L1449-1 assume !(1 == ~E_10~0); 293002#L1454-1 assume !(1 == ~E_11~0); 293003#L1459-1 assume 1 == ~E_12~0;~E_12~0 := 2; 294117#L1464-1 assume { :end_inline_reset_delta_events } true; 316897#L1810-2 [2023-11-12 02:04:11,124 INFO L750 eck$LassoCheckResult]: Loop: 316897#L1810-2 assume !false; 316891#L1811 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 316889#L1176-1 assume !false; 316887#L999 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 316883#L921 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 316871#L988 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 316867#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 316864#L1003 assume !(0 != eval_~tmp~0#1); 316865#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 317696#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 317695#L1201-3 assume 0 == ~M_E~0;~M_E~0 := 1; 317694#L1201-5 assume !(0 == ~T1_E~0); 317693#L1206-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 317692#L1211-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 317690#L1216-3 assume !(0 == ~T4_E~0); 317689#L1221-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 317688#L1226-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 317687#L1231-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 317686#L1236-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 317684#L1241-3 assume !(0 == ~T9_E~0); 317683#L1246-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 317682#L1251-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 317681#L1256-3 assume !(0 == ~T12_E~0); 317679#L1261-3 assume 0 == ~E_M~0;~E_M~0 := 1; 317677#L1266-3 assume 0 == ~E_1~0;~E_1~0 := 1; 317675#L1271-3 assume 0 == ~E_2~0;~E_2~0 := 1; 317673#L1276-3 assume 0 == ~E_3~0;~E_3~0 := 1; 317671#L1281-3 assume !(0 == ~E_4~0); 317669#L1286-3 assume 0 == ~E_5~0;~E_5~0 := 1; 317665#L1291-3 assume 0 == ~E_6~0;~E_6~0 := 1; 317663#L1296-3 assume !(0 == ~E_7~0); 317661#L1301-3 assume 0 == ~E_8~0;~E_8~0 := 1; 317659#L1306-3 assume 0 == ~E_9~0;~E_9~0 := 1; 317656#L1311-3 assume 0 == ~E_10~0;~E_10~0 := 1; 317654#L1316-3 assume 0 == ~E_11~0;~E_11~0 := 1; 317652#L1321-3 assume !(0 == ~E_12~0); 317651#L1326-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 317649#L593-42 assume !(1 == ~m_pc~0); 317647#L593-44 is_master_triggered_~__retres1~0#1 := 0; 317645#L604-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 317643#is_master_triggered_returnLabel#15 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 317641#L1492-42 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 317638#L1492-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 317636#L612-42 assume !(1 == ~t1_pc~0); 317632#L612-44 is_transmit1_triggered_~__retres1~1#1 := 0; 317630#L623-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 317628#is_transmit1_triggered_returnLabel#15 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 317626#L1500-42 assume !(0 != activate_threads_~tmp___0~0#1); 317622#L1500-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 317620#L631-42 assume !(1 == ~t2_pc~0); 306817#L631-44 is_transmit2_triggered_~__retres1~2#1 := 0; 317617#L642-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 317615#is_transmit2_triggered_returnLabel#15 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 317613#L1508-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 317612#L1508-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 317611#L650-42 assume !(1 == ~t3_pc~0); 317609#L650-44 is_transmit3_triggered_~__retres1~3#1 := 0; 317608#L661-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 317607#is_transmit3_triggered_returnLabel#15 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 317606#L1516-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 317605#L1516-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 317604#L669-42 assume 1 == ~t4_pc~0; 317602#L670-14 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 317601#L680-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 317600#is_transmit4_triggered_returnLabel#15 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 317599#L1524-42 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 317598#L1524-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 317597#L688-42 assume 1 == ~t5_pc~0; 317596#L689-14 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 317594#L699-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 317593#is_transmit5_triggered_returnLabel#15 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 317592#L1532-42 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 317591#L1532-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 317590#L707-42 assume 1 == ~t6_pc~0; 317588#L708-14 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 317587#L718-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 317586#is_transmit6_triggered_returnLabel#15 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 317585#L1540-42 assume !(0 != activate_threads_~tmp___5~0#1); 317584#L1540-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 317583#L726-42 assume 1 == ~t7_pc~0; 317581#L727-14 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 317580#L737-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 317579#is_transmit7_triggered_returnLabel#15 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 317577#L1548-42 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 317575#L1548-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 317574#L745-42 assume !(1 == ~t8_pc~0); 317572#L745-44 is_transmit8_triggered_~__retres1~8#1 := 0; 317571#L756-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 317570#is_transmit8_triggered_returnLabel#15 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 317569#L1556-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 317567#L1556-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 317565#L764-42 assume 1 == ~t9_pc~0; 317562#L765-14 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 317560#L775-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 317558#is_transmit9_triggered_returnLabel#15 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 317556#L1564-42 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 317554#L1564-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 317551#L783-42 assume !(1 == ~t10_pc~0); 317548#L783-44 is_transmit10_triggered_~__retres1~10#1 := 0; 317546#L794-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 317543#is_transmit10_triggered_returnLabel#15 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 317541#L1572-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 317539#L1572-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 317538#L802-42 assume !(1 == ~t11_pc~0); 317536#L802-44 is_transmit11_triggered_~__retres1~11#1 := 0; 317533#L813-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 317531#is_transmit11_triggered_returnLabel#15 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 317529#L1580-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 317527#L1580-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 317524#L821-42 assume !(1 == ~t12_pc~0); 317521#L821-44 is_transmit12_triggered_~__retres1~12#1 := 0; 317519#L832-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 317517#is_transmit12_triggered_returnLabel#15 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 317515#L1588-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 317513#L1588-44 havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 317510#L1339-3 assume 1 == ~M_E~0;~M_E~0 := 2; 317508#L1339-5 assume !(1 == ~T1_E~0); 317506#L1344-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 293670#L1349-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 317503#L1354-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 317501#L1359-3 assume !(1 == ~T5_E~0); 317498#L1364-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 317496#L1369-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 317494#L1374-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 317492#L1379-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 310708#L1384-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 317489#L1389-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 317486#L1394-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 317484#L1399-3 assume !(1 == ~E_M~0); 317482#L1404-3 assume 1 == ~E_1~0;~E_1~0 := 2; 317480#L1409-3 assume 1 == ~E_2~0;~E_2~0 := 2; 317478#L1414-3 assume 1 == ~E_3~0;~E_3~0 := 2; 317476#L1419-3 assume 1 == ~E_4~0;~E_4~0 := 2; 315575#L1424-3 assume 1 == ~E_5~0;~E_5~0 := 2; 317472#L1429-3 assume 1 == ~E_6~0;~E_6~0 := 2; 317470#L1434-3 assume 1 == ~E_7~0;~E_7~0 := 2; 317468#L1439-3 assume !(1 == ~E_8~0); 317466#L1444-3 assume 1 == ~E_9~0;~E_9~0 := 2; 317464#L1449-3 assume 1 == ~E_10~0;~E_10~0 := 2; 317461#L1454-3 assume 1 == ~E_11~0;~E_11~0 := 2; 317459#L1459-3 assume 1 == ~E_12~0;~E_12~0 := 2; 293627#L1464-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 317456#L921-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 317442#L988-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 317440#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; 317345#L1829 assume !(0 == start_simulation_~tmp~3#1); 317342#L1829-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 316958#L921-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 316945#L988-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 316940#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret33#1;havoc stop_simulation_#t~ret33#1; 316925#L1784 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 316914#L1791 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 316906#stop_simulation_returnLabel#1 start_simulation_#t~ret35#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 316904#L1842 assume !(0 != start_simulation_~tmp___0~1#1); 316897#L1810-2 [2023-11-12 02:04:11,125 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-12 02:04:11,125 INFO L85 PathProgramCache]: Analyzing trace with hash -451693884, now seen corresponding path program 1 times [2023-11-12 02:04:11,126 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-12 02:04:11,126 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1700721281] [2023-11-12 02:04:11,126 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-12 02:04:11,127 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-12 02:04:11,164 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-12 02:04:11,245 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-12 02:04:11,245 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-12 02:04:11,246 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1700721281] [2023-11-12 02:04:11,246 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1700721281] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-12 02:04:11,246 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-12 02:04:11,246 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2023-11-12 02:04:11,246 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1167946807] [2023-11-12 02:04:11,246 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-12 02:04:11,247 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-12 02:04:11,247 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-12 02:04:11,248 INFO L85 PathProgramCache]: Analyzing trace with hash -1970456091, now seen corresponding path program 1 times [2023-11-12 02:04:11,248 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-12 02:04:11,248 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [265368729] [2023-11-12 02:04:11,248 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-12 02:04:11,248 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-12 02:04:11,267 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-12 02:04:11,316 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-12 02:04:11,317 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-12 02:04:11,317 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [265368729] [2023-11-12 02:04:11,317 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [265368729] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-12 02:04:11,317 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-12 02:04:11,318 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-12 02:04:11,318 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [494491979] [2023-11-12 02:04:11,318 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-12 02:04:11,318 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-12 02:04:11,318 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-12 02:04:11,319 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-12 02:04:11,319 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-12 02:04:11,319 INFO L87 Difference]: Start difference. First operand 47426 states and 68256 transitions. cyclomatic complexity: 20846 Second operand has 3 states, 3 states have (on average 50.0) internal successors, (150), 2 states have internal predecessors, (150), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-12 02:04:11,896 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-12 02:04:11,896 INFO L93 Difference]: Finished difference Result 91169 states and 130705 transitions. [2023-11-12 02:04:11,896 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 91169 states and 130705 transitions. [2023-11-12 02:04:12,265 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 90848 [2023-11-12 02:04:12,835 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 91169 states to 91169 states and 130705 transitions. [2023-11-12 02:04:12,835 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 91169 [2023-11-12 02:04:12,892 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 91169 [2023-11-12 02:04:12,892 INFO L73 IsDeterministic]: Start isDeterministic. Operand 91169 states and 130705 transitions. [2023-11-12 02:04:12,984 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-12 02:04:12,984 INFO L218 hiAutomatonCegarLoop]: Abstraction has 91169 states and 130705 transitions. [2023-11-12 02:04:13,060 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 91169 states and 130705 transitions. [2023-11-12 02:04:14,251 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 91169 to 91105. [2023-11-12 02:04:14,348 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 91105 states, 91105 states have (on average 1.4339608144448712) internal successors, (130641), 91104 states have internal predecessors, (130641), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-12 02:04:14,550 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 91105 states to 91105 states and 130641 transitions. [2023-11-12 02:04:14,550 INFO L240 hiAutomatonCegarLoop]: Abstraction has 91105 states and 130641 transitions. [2023-11-12 02:04:14,550 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-12 02:04:14,551 INFO L428 stractBuchiCegarLoop]: Abstraction has 91105 states and 130641 transitions. [2023-11-12 02:04:14,551 INFO L335 stractBuchiCegarLoop]: ======== Iteration 21 ============ [2023-11-12 02:04:14,551 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 91105 states and 130641 transitions. [2023-11-12 02:04:14,789 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 90784 [2023-11-12 02:04:14,789 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-12 02:04:14,790 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-12 02:04:14,792 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-12 02:04:14,792 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-12 02:04:14,793 INFO L748 eck$LassoCheckResult]: Stem: 431198#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(20, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~token~0 := 0;~local~0 := 0; 431199#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~14#1;havoc main_~__retres1~14#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1; 432087#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret34#1, start_simulation_#t~ret35#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 432088#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 432826#L848 assume 1 == ~m_i~0;~m_st~0 := 0; 432827#L848-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 431742#L853-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 431520#L858-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 430911#L863-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 430912#L868-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 432217#L873-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 432333#L878-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 432942#L883-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 432943#L888-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 431659#L893-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 431660#L898-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 432244#L903-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 432155#L908-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 431699#L1201 assume !(0 == ~M_E~0); 431700#L1201-2 assume !(0 == ~T1_E~0); 432683#L1206-1 assume !(0 == ~T2_E~0); 432657#L1211-1 assume !(0 == ~T3_E~0); 432658#L1216-1 assume !(0 == ~T4_E~0); 431502#L1221-1 assume !(0 == ~T5_E~0); 431503#L1226-1 assume !(0 == ~T6_E~0); 431124#L1231-1 assume !(0 == ~T7_E~0); 431125#L1236-1 assume !(0 == ~T8_E~0); 432719#L1241-1 assume !(0 == ~T9_E~0); 431543#L1246-1 assume !(0 == ~T10_E~0); 431544#L1251-1 assume !(0 == ~T11_E~0); 431697#L1256-1 assume !(0 == ~T12_E~0); 430920#L1261-1 assume !(0 == ~E_M~0); 430921#L1266-1 assume !(0 == ~E_1~0); 432909#L1271-1 assume !(0 == ~E_2~0); 432313#L1276-1 assume !(0 == ~E_3~0); 432314#L1281-1 assume !(0 == ~E_4~0); 432260#L1286-1 assume !(0 == ~E_5~0); 431393#L1291-1 assume !(0 == ~E_6~0); 431394#L1296-1 assume !(0 == ~E_7~0); 432021#L1301-1 assume !(0 == ~E_8~0); 432022#L1306-1 assume !(0 == ~E_9~0); 432581#L1311-1 assume !(0 == ~E_10~0); 431344#L1316-1 assume !(0 == ~E_11~0); 431345#L1321-1 assume !(0 == ~E_12~0); 432042#L1326-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 432043#L593 assume !(1 == ~m_pc~0); 431222#L593-2 is_master_triggered_~__retres1~0#1 := 0; 431223#L604 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 431914#is_master_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 431915#L1492 assume !(0 != activate_threads_~tmp~1#1); 432271#L1492-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 432622#L612 assume !(1 == ~t1_pc~0); 432623#L612-2 is_transmit1_triggered_~__retres1~1#1 := 0; 432928#L623 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 432426#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 431226#L1500 assume !(0 != activate_threads_~tmp___0~0#1); 431227#L1500-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 431676#L631 assume !(1 == ~t2_pc~0); 431677#L631-2 is_transmit2_triggered_~__retres1~2#1 := 0; 430999#L642 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 431000#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 431358#L1508 assume !(0 != activate_threads_~tmp___1~0#1); 431873#L1508-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 431305#L650 assume !(1 == ~t3_pc~0); 431306#L650-2 is_transmit3_triggered_~__retres1~3#1 := 0; 432066#L661 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 432400#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 430958#L1516 assume !(0 != activate_threads_~tmp___2~0#1); 430959#L1516-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 432238#L669 assume !(1 == ~t4_pc~0); 432239#L669-2 is_transmit4_triggered_~__retres1~4#1 := 0; 432670#L680 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 431043#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 431044#L1524 assume !(0 != activate_threads_~tmp___3~0#1); 431161#L1524-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 431404#L688 assume !(1 == ~t5_pc~0); 431180#L688-2 is_transmit5_triggered_~__retres1~5#1 := 0; 431181#L699 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 432868#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 432111#L1532 assume !(0 != activate_threads_~tmp___4~0#1); 432112#L1532-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 432257#L707 assume 1 == ~t6_pc~0; 432769#L708 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 431842#L718 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 431346#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 431347#L1540 assume !(0 != activate_threads_~tmp___5~0#1); 432191#L1540-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 431698#L726 assume 1 == ~t7_pc~0; 431589#L727 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 431268#L737 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 432414#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 432776#L1548 assume !(0 != activate_threads_~tmp___6~0#1); 431029#L1548-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 431030#L745 assume !(1 == ~t8_pc~0); 431494#L745-2 is_transmit8_triggered_~__retres1~8#1 := 0; 431514#L756 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 432693#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 431924#L1556 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 431925#L1556-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 432528#L764 assume 1 == ~t9_pc~0; 431696#L765 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 431524#L775 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 431422#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 431423#L1564 assume !(0 != activate_threads_~tmp___8~0#1); 431055#L1564-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 431056#L783 assume !(1 == ~t10_pc~0); 431111#L783-2 is_transmit10_triggered_~__retres1~10#1 := 0; 431112#L794 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 431310#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 431653#L1572 assume !(0 != activate_threads_~tmp___9~0#1); 431654#L1572-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 432671#L802 assume 1 == ~t11_pc~0; 432645#L803 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 430996#L813 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 430997#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 431504#L1580 assume !(0 != activate_threads_~tmp___10~0#1); 431505#L1580-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 431620#L821 assume !(1 == ~t12_pc~0); 431889#L821-2 is_transmit12_triggered_~__retres1~12#1 := 0; 432011#L832 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 431005#is_transmit12_triggered_returnLabel#1 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 431006#L1588 assume !(0 != activate_threads_~tmp___11~0#1); 432733#L1588-2 havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 432280#L1339 assume !(1 == ~M_E~0); 432281#L1339-2 assume !(1 == ~T1_E~0); 432782#L1344-1 assume !(1 == ~T2_E~0); 432783#L1349-1 assume !(1 == ~T3_E~0); 432036#L1354-1 assume !(1 == ~T4_E~0); 432037#L1359-1 assume !(1 == ~T5_E~0); 453870#L1364-1 assume !(1 == ~T6_E~0); 431454#L1369-1 assume !(1 == ~T7_E~0); 431455#L1374-1 assume !(1 == ~T8_E~0); 452041#L1379-1 assume 1 == ~T9_E~0;~T9_E~0 := 2; 452040#L1384-1 assume 1 == ~T10_E~0;~T10_E~0 := 2; 452037#L1389-1 assume !(1 == ~T11_E~0); 432725#L1394-1 assume !(1 == ~T12_E~0); 432726#L1399-1 assume !(1 == ~E_M~0); 432965#L1404-1 assume !(1 == ~E_1~0); 451800#L1409-1 assume !(1 == ~E_2~0); 451797#L1414-1 assume !(1 == ~E_3~0); 451795#L1419-1 assume 1 == ~E_4~0;~E_4~0 := 2; 431170#L1424-1 assume 1 == ~E_5~0;~E_5~0 := 2; 431171#L1429-1 assume !(1 == ~E_6~0); 432050#L1434-1 assume !(1 == ~E_7~0); 432746#L1439-1 assume !(1 == ~E_8~0); 431212#L1444-1 assume !(1 == ~E_9~0); 431213#L1449-1 assume !(1 == ~E_10~0); 431605#L1454-1 assume !(1 == ~E_11~0); 431606#L1459-1 assume 1 == ~E_12~0;~E_12~0 := 2; 432187#L1464-1 assume { :end_inline_reset_delta_events } true; 432188#L1810-2 [2023-11-12 02:04:14,793 INFO L750 eck$LassoCheckResult]: Loop: 432188#L1810-2 assume !false; 434179#L1811 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 434176#L1176-1 assume !false; 434173#L999 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 433965#L921 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 433949#L988 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 433940#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 433932#L1003 assume !(0 != eval_~tmp~0#1); 433933#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 476262#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 476260#L1201-3 assume 0 == ~M_E~0;~M_E~0 := 1; 476258#L1201-5 assume !(0 == ~T1_E~0); 476256#L1206-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 476254#L1211-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 476252#L1216-3 assume !(0 == ~T4_E~0); 476250#L1221-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 476248#L1226-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 476246#L1231-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 476244#L1236-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 476242#L1241-3 assume !(0 == ~T9_E~0); 476240#L1246-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 476238#L1251-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 476236#L1256-3 assume !(0 == ~T12_E~0); 476234#L1261-3 assume 0 == ~E_M~0;~E_M~0 := 1; 476232#L1266-3 assume 0 == ~E_1~0;~E_1~0 := 1; 476230#L1271-3 assume 0 == ~E_2~0;~E_2~0 := 1; 476228#L1276-3 assume 0 == ~E_3~0;~E_3~0 := 1; 476226#L1281-3 assume !(0 == ~E_4~0); 476224#L1286-3 assume 0 == ~E_5~0;~E_5~0 := 1; 476222#L1291-3 assume 0 == ~E_6~0;~E_6~0 := 1; 476220#L1296-3 assume !(0 == ~E_7~0); 476218#L1301-3 assume 0 == ~E_8~0;~E_8~0 := 1; 476216#L1306-3 assume 0 == ~E_9~0;~E_9~0 := 1; 476214#L1311-3 assume 0 == ~E_10~0;~E_10~0 := 1; 476212#L1316-3 assume 0 == ~E_11~0;~E_11~0 := 1; 476210#L1321-3 assume !(0 == ~E_12~0); 476208#L1326-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 476206#L593-42 assume !(1 == ~m_pc~0); 476204#L593-44 is_master_triggered_~__retres1~0#1 := 0; 476202#L604-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 476200#is_master_triggered_returnLabel#15 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 476197#L1492-42 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 476194#L1492-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 476191#L612-42 assume 1 == ~t1_pc~0; 476187#L613-14 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 475581#L623-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 475582#is_transmit1_triggered_returnLabel#15 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 475574#L1500-42 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 475575#L1500-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 475526#L631-42 assume !(1 == ~t2_pc~0); 475524#L631-44 is_transmit2_triggered_~__retres1~2#1 := 0; 475522#L642-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 475520#is_transmit2_triggered_returnLabel#15 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 475518#L1508-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 475516#L1508-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 475513#L650-42 assume 1 == ~t3_pc~0; 475511#L651-14 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 475508#L661-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 475506#is_transmit3_triggered_returnLabel#15 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 475504#L1516-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 475502#L1516-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 475500#L669-42 assume !(1 == ~t4_pc~0); 475498#L669-44 is_transmit4_triggered_~__retres1~4#1 := 0; 475496#L680-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 475494#is_transmit4_triggered_returnLabel#15 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 475492#L1524-42 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 475490#L1524-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 475487#L688-42 assume 1 == ~t5_pc~0; 475485#L689-14 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 475482#L699-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 475480#is_transmit5_triggered_returnLabel#15 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 475478#L1532-42 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 475476#L1532-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 475473#L707-42 assume !(1 == ~t6_pc~0); 475471#L707-44 is_transmit6_triggered_~__retres1~6#1 := 0; 475468#L718-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 475466#is_transmit6_triggered_returnLabel#15 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 475464#L1540-42 assume !(0 != activate_threads_~tmp___5~0#1); 475462#L1540-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 475459#L726-42 assume !(1 == ~t7_pc~0); 475457#L726-44 is_transmit7_triggered_~__retres1~7#1 := 0; 475454#L737-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 475452#is_transmit7_triggered_returnLabel#15 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 475450#L1548-42 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 475448#L1548-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 475445#L745-42 assume 1 == ~t8_pc~0; 475443#L746-14 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 475440#L756-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 475438#is_transmit8_triggered_returnLabel#15 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 475436#L1556-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 475434#L1556-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 475431#L764-42 assume !(1 == ~t9_pc~0); 475428#L764-44 is_transmit9_triggered_~__retres1~9#1 := 0; 475424#L775-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 475421#is_transmit9_triggered_returnLabel#15 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 475418#L1564-42 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 475415#L1564-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 475411#L783-42 assume 1 == ~t10_pc~0; 475408#L784-14 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 475403#L794-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 475399#is_transmit10_triggered_returnLabel#15 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 475395#L1572-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 475391#L1572-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 475387#L802-42 assume 1 == ~t11_pc~0; 475383#L803-14 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 475381#L813-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 475378#is_transmit11_triggered_returnLabel#15 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 475375#L1580-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 475372#L1580-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 475368#L821-42 assume 1 == ~t12_pc~0; 475365#L822-14 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 475360#L832-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 475357#is_transmit12_triggered_returnLabel#15 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 475354#L1588-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 475351#L1588-44 havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 475348#L1339-3 assume 1 == ~M_E~0;~M_E~0 := 2; 475346#L1339-5 assume !(1 == ~T1_E~0); 475343#L1344-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 452177#L1349-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 475336#L1354-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 475333#L1359-3 assume !(1 == ~T5_E~0); 475330#L1364-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 475328#L1369-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 475325#L1374-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 475323#L1379-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 475318#L1384-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 475315#L1389-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 475312#L1394-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 475309#L1399-3 assume !(1 == ~E_M~0); 475305#L1404-3 assume 1 == ~E_1~0;~E_1~0 := 2; 475302#L1409-3 assume 1 == ~E_2~0;~E_2~0 := 2; 475299#L1414-3 assume 1 == ~E_3~0;~E_3~0 := 2; 475295#L1419-3 assume 1 == ~E_4~0;~E_4~0 := 2; 454900#L1424-3 assume 1 == ~E_5~0;~E_5~0 := 2; 475288#L1429-3 assume 1 == ~E_6~0;~E_6~0 := 2; 472281#L1434-3 assume 1 == ~E_7~0;~E_7~0 := 2; 472282#L1439-3 assume !(1 == ~E_8~0); 475281#L1444-3 assume 1 == ~E_9~0;~E_9~0 := 2; 475279#L1449-3 assume 1 == ~E_10~0;~E_10~0 := 2; 475151#L1454-3 assume 1 == ~E_11~0;~E_11~0 := 2; 475150#L1459-3 assume 1 == ~E_12~0;~E_12~0 := 2; 470264#L1464-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 475127#L921-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 475114#L988-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 435693#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; 435694#L1829 assume !(0 == start_simulation_~tmp~3#1); 474009#L1829-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 435592#L921-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 435580#L988-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 435578#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret33#1;havoc stop_simulation_#t~ret33#1; 435576#L1784 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 435575#L1791 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 434765#stop_simulation_returnLabel#1 start_simulation_#t~ret35#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 434198#L1842 assume !(0 != start_simulation_~tmp___0~1#1); 432188#L1810-2 [2023-11-12 02:04:14,794 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-12 02:04:14,794 INFO L85 PathProgramCache]: Analyzing trace with hash 1008300037, now seen corresponding path program 1 times [2023-11-12 02:04:14,794 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-12 02:04:14,795 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [752264213] [2023-11-12 02:04:14,795 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-12 02:04:14,795 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-12 02:04:14,813 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-12 02:04:14,885 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-12 02:04:14,885 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-12 02:04:14,885 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [752264213] [2023-11-12 02:04:14,885 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [752264213] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-12 02:04:14,885 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-12 02:04:14,886 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-12 02:04:14,886 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [562699137] [2023-11-12 02:04:14,886 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-12 02:04:14,886 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-12 02:04:14,887 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-12 02:04:14,887 INFO L85 PathProgramCache]: Analyzing trace with hash -2141413215, now seen corresponding path program 1 times [2023-11-12 02:04:14,887 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-12 02:04:14,887 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [184735937] [2023-11-12 02:04:14,887 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-12 02:04:14,888 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-12 02:04:14,903 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-12 02:04:14,947 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-12 02:04:14,947 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-12 02:04:14,947 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [184735937] [2023-11-12 02:04:14,948 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [184735937] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-12 02:04:14,948 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-12 02:04:14,948 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-12 02:04:14,948 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [378519230] [2023-11-12 02:04:14,948 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-12 02:04:14,949 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-12 02:04:14,949 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-12 02:04:14,949 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2023-11-12 02:04:14,950 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2023-11-12 02:04:14,950 INFO L87 Difference]: Start difference. First operand 91105 states and 130641 transitions. cyclomatic complexity: 39568 Second operand has 4 states, 4 states have (on average 37.5) internal successors, (150), 3 states have internal predecessors, (150), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-12 02:04:16,436 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-12 02:04:16,436 INFO L93 Difference]: Finished difference Result 221392 states and 315562 transitions. [2023-11-12 02:04:16,436 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 221392 states and 315562 transitions. [2023-11-12 02:04:18,029 INFO L131 ngComponentsAnalysis]: Automaton has 48 accepting balls. 217776 [2023-11-12 02:04:18,937 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 221392 states to 221392 states and 315562 transitions. [2023-11-12 02:04:18,937 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 221392 [2023-11-12 02:04:19,030 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 221392 [2023-11-12 02:04:19,031 INFO L73 IsDeterministic]: Start isDeterministic. Operand 221392 states and 315562 transitions. [2023-11-12 02:04:19,243 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-12 02:04:19,243 INFO L218 hiAutomatonCegarLoop]: Abstraction has 221392 states and 315562 transitions. [2023-11-12 02:04:19,374 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 221392 states and 315562 transitions. [2023-11-12 02:04:21,237 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 221392 to 175008. [2023-11-12 02:04:21,371 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 175008 states, 175008 states have (on average 1.429088955933443) internal successors, (250102), 175007 states have internal predecessors, (250102), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-12 02:04:22,406 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 175008 states to 175008 states and 250102 transitions. [2023-11-12 02:04:22,406 INFO L240 hiAutomatonCegarLoop]: Abstraction has 175008 states and 250102 transitions. [2023-11-12 02:04:22,407 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2023-11-12 02:04:22,407 INFO L428 stractBuchiCegarLoop]: Abstraction has 175008 states and 250102 transitions. [2023-11-12 02:04:22,408 INFO L335 stractBuchiCegarLoop]: ======== Iteration 22 ============ [2023-11-12 02:04:22,408 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 175008 states and 250102 transitions. [2023-11-12 02:04:22,812 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 174592 [2023-11-12 02:04:22,813 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-12 02:04:22,813 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-12 02:04:22,815 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-12 02:04:22,815 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-12 02:04:22,816 INFO L748 eck$LassoCheckResult]: Stem: 743702#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(20, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~token~0 := 0;~local~0 := 0; 743703#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~14#1;havoc main_~__retres1~14#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1; 744585#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret34#1, start_simulation_#t~ret35#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 744586#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 745294#L848 assume 1 == ~m_i~0;~m_st~0 := 0; 745295#L848-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 744245#L853-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 744030#L858-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 743418#L863-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 743419#L868-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 744711#L873-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 744822#L878-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 745399#L883-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 745400#L888-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 744166#L893-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 744167#L898-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 744740#L903-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 744654#L908-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 744206#L1201 assume !(0 == ~M_E~0); 744207#L1201-2 assume !(0 == ~T1_E~0); 745163#L1206-1 assume !(0 == ~T2_E~0); 745142#L1211-1 assume !(0 == ~T3_E~0); 745143#L1216-1 assume !(0 == ~T4_E~0); 744011#L1221-1 assume !(0 == ~T5_E~0); 744012#L1226-1 assume !(0 == ~T6_E~0); 743628#L1231-1 assume !(0 == ~T7_E~0); 743629#L1236-1 assume !(0 == ~T8_E~0); 745191#L1241-1 assume !(0 == ~T9_E~0); 744053#L1246-1 assume !(0 == ~T10_E~0); 744054#L1251-1 assume !(0 == ~T11_E~0); 744204#L1256-1 assume !(0 == ~T12_E~0); 743426#L1261-1 assume !(0 == ~E_M~0); 743427#L1266-1 assume !(0 == ~E_1~0); 745373#L1271-1 assume !(0 == ~E_2~0); 744802#L1276-1 assume !(0 == ~E_3~0); 744803#L1281-1 assume !(0 == ~E_4~0); 744752#L1286-1 assume !(0 == ~E_5~0); 743898#L1291-1 assume !(0 == ~E_6~0); 743899#L1296-1 assume !(0 == ~E_7~0); 744517#L1301-1 assume !(0 == ~E_8~0); 744518#L1306-1 assume !(0 == ~E_9~0); 745065#L1311-1 assume !(0 == ~E_10~0); 743849#L1316-1 assume !(0 == ~E_11~0); 743850#L1321-1 assume !(0 == ~E_12~0); 744538#L1326-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 744539#L593 assume !(1 == ~m_pc~0); 743726#L593-2 is_master_triggered_~__retres1~0#1 := 0; 743727#L604 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 744413#is_master_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 744414#L1492 assume !(0 != activate_threads_~tmp~1#1); 744763#L1492-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 745107#L612 assume !(1 == ~t1_pc~0); 745108#L612-2 is_transmit1_triggered_~__retres1~1#1 := 0; 745391#L623 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 744910#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 743730#L1500 assume !(0 != activate_threads_~tmp___0~0#1); 743731#L1500-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 744182#L631 assume !(1 == ~t2_pc~0); 744183#L631-2 is_transmit2_triggered_~__retres1~2#1 := 0; 743505#L642 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 743506#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 743863#L1508 assume !(0 != activate_threads_~tmp___1~0#1); 744374#L1508-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 743808#L650 assume !(1 == ~t3_pc~0); 743809#L650-2 is_transmit3_triggered_~__retres1~3#1 := 0; 744561#L661 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 744886#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 743464#L1516 assume !(0 != activate_threads_~tmp___2~0#1); 743465#L1516-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 744733#L669 assume !(1 == ~t4_pc~0); 744734#L669-2 is_transmit4_triggered_~__retres1~4#1 := 0; 745152#L680 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 743549#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 743550#L1524 assume !(0 != activate_threads_~tmp___3~0#1); 743665#L1524-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 743909#L688 assume !(1 == ~t5_pc~0); 743684#L688-2 is_transmit5_triggered_~__retres1~5#1 := 0; 743685#L699 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 745336#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 744609#L1532 assume !(0 != activate_threads_~tmp___4~0#1); 744610#L1532-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 744750#L707 assume !(1 == ~t6_pc~0); 744991#L707-2 is_transmit6_triggered_~__retres1~6#1 := 0; 744342#L718 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 743851#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 743852#L1540 assume !(0 != activate_threads_~tmp___5~0#1); 744693#L1540-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 744205#L726 assume 1 == ~t7_pc~0; 744100#L727 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 743771#L737 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 744901#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 745244#L1548 assume !(0 != activate_threads_~tmp___6~0#1); 743535#L1548-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 743536#L745 assume !(1 == ~t8_pc~0); 744003#L745-2 is_transmit8_triggered_~__retres1~8#1 := 0; 744024#L756 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 745169#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 744422#L1556 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 744423#L1556-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 745012#L764 assume 1 == ~t9_pc~0; 744203#L765 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 744034#L775 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 743927#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 743928#L1564 assume !(0 != activate_threads_~tmp___8~0#1); 743561#L1564-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 743562#L783 assume !(1 == ~t10_pc~0); 743616#L783-2 is_transmit10_triggered_~__retres1~10#1 := 0; 743617#L794 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 743813#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 744161#L1572 assume !(0 != activate_threads_~tmp___9~0#1); 744162#L1572-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 745153#L802 assume 1 == ~t11_pc~0; 745131#L803 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 743502#L813 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 743503#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 744013#L1580 assume !(0 != activate_threads_~tmp___10~0#1); 744014#L1580-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 744130#L821 assume !(1 == ~t12_pc~0); 744389#L821-2 is_transmit12_triggered_~__retres1~12#1 := 0; 744506#L832 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 743511#is_transmit12_triggered_returnLabel#1 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 743512#L1588 assume !(0 != activate_threads_~tmp___11~0#1); 745207#L1588-2 havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 744771#L1339 assume !(1 == ~M_E~0); 744772#L1339-2 assume !(1 == ~T1_E~0); 745250#L1344-1 assume !(1 == ~T2_E~0); 745251#L1349-1 assume !(1 == ~T3_E~0); 745451#L1354-1 assume !(1 == ~T4_E~0); 744983#L1359-1 assume !(1 == ~T5_E~0); 744984#L1364-1 assume !(1 == ~T6_E~0); 743963#L1369-1 assume !(1 == ~T7_E~0); 743964#L1374-1 assume !(1 == ~T8_E~0); 744535#L1379-1 assume 1 == ~T9_E~0;~T9_E~0 := 2; 744536#L1384-1 assume 1 == ~T10_E~0;~T10_E~0 := 2; 806349#L1389-1 assume !(1 == ~T11_E~0); 806344#L1394-1 assume !(1 == ~T12_E~0); 806341#L1399-1 assume !(1 == ~E_M~0); 806335#L1404-1 assume !(1 == ~E_1~0); 806300#L1409-1 assume !(1 == ~E_2~0); 806297#L1414-1 assume !(1 == ~E_3~0); 806294#L1419-1 assume 1 == ~E_4~0;~E_4~0 := 2; 743674#L1424-1 assume 1 == ~E_5~0;~E_5~0 := 2; 743675#L1429-1 assume !(1 == ~E_6~0); 744546#L1434-1 assume !(1 == ~E_7~0); 745221#L1439-1 assume !(1 == ~E_8~0); 743716#L1444-1 assume !(1 == ~E_9~0); 743717#L1449-1 assume !(1 == ~E_10~0); 812960#L1454-1 assume !(1 == ~E_11~0); 812956#L1459-1 assume 1 == ~E_12~0;~E_12~0 := 2; 745242#L1464-1 assume { :end_inline_reset_delta_events } true; 822002#L1810-2 [2023-11-12 02:04:22,817 INFO L750 eck$LassoCheckResult]: Loop: 822002#L1810-2 assume !false; 821993#L1811 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 821985#L1176-1 assume !false; 821968#L999 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 821956#L921 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 821940#L988 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 821934#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 821927#L1003 assume !(0 != eval_~tmp~0#1); 821928#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 827582#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 827549#L1201-3 assume 0 == ~M_E~0;~M_E~0 := 1; 827541#L1201-5 assume !(0 == ~T1_E~0); 827534#L1206-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 827526#L1211-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 827519#L1216-3 assume !(0 == ~T4_E~0); 827512#L1221-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 827503#L1226-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 827496#L1231-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 827491#L1236-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 827440#L1241-3 assume !(0 == ~T9_E~0); 827434#L1246-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 827428#L1251-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 827376#L1256-3 assume !(0 == ~T12_E~0); 827370#L1261-3 assume 0 == ~E_M~0;~E_M~0 := 1; 827364#L1266-3 assume 0 == ~E_1~0;~E_1~0 := 1; 827356#L1271-3 assume 0 == ~E_2~0;~E_2~0 := 1; 827350#L1276-3 assume 0 == ~E_3~0;~E_3~0 := 1; 827343#L1281-3 assume !(0 == ~E_4~0); 827335#L1286-3 assume 0 == ~E_5~0;~E_5~0 := 1; 827329#L1291-3 assume 0 == ~E_6~0;~E_6~0 := 1; 827323#L1296-3 assume !(0 == ~E_7~0); 827315#L1301-3 assume 0 == ~E_8~0;~E_8~0 := 1; 827309#L1306-3 assume 0 == ~E_9~0;~E_9~0 := 1; 827302#L1311-3 assume 0 == ~E_10~0;~E_10~0 := 1; 827294#L1316-3 assume 0 == ~E_11~0;~E_11~0 := 1; 827288#L1321-3 assume !(0 == ~E_12~0); 827282#L1326-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 827274#L593-42 assume !(1 == ~m_pc~0); 827268#L593-44 is_master_triggered_~__retres1~0#1 := 0; 827261#L604-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 827253#is_master_triggered_returnLabel#15 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 825750#L1492-42 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 825749#L1492-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 825748#L612-42 assume !(1 == ~t1_pc~0); 825746#L612-44 is_transmit1_triggered_~__retres1~1#1 := 0; 825744#L623-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 825742#is_transmit1_triggered_returnLabel#15 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 825741#L1500-42 assume !(0 != activate_threads_~tmp___0~0#1); 825163#L1500-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 823196#L631-42 assume !(1 == ~t2_pc~0); 823194#L631-44 is_transmit2_triggered_~__retres1~2#1 := 0; 823192#L642-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 823191#is_transmit2_triggered_returnLabel#15 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 823189#L1508-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 823187#L1508-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 823185#L650-42 assume !(1 == ~t3_pc~0); 823182#L650-44 is_transmit3_triggered_~__retres1~3#1 := 0; 823180#L661-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 823177#is_transmit3_triggered_returnLabel#15 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 823175#L1516-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 823173#L1516-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 823171#L669-42 assume !(1 == ~t4_pc~0); 823169#L669-44 is_transmit4_triggered_~__retres1~4#1 := 0; 823167#L680-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 823164#is_transmit4_triggered_returnLabel#15 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 823162#L1524-42 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 823160#L1524-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 823158#L688-42 assume 1 == ~t5_pc~0; 823156#L689-14 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 823153#L699-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 823150#is_transmit5_triggered_returnLabel#15 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 823148#L1532-42 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 823146#L1532-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 823144#L707-42 assume !(1 == ~t6_pc~0); 788623#L707-44 is_transmit6_triggered_~__retres1~6#1 := 0; 823141#L718-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 823138#is_transmit6_triggered_returnLabel#15 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 823136#L1540-42 assume !(0 != activate_threads_~tmp___5~0#1); 823134#L1540-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 823132#L726-42 assume 1 == ~t7_pc~0; 823129#L727-14 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 823127#L737-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 823124#is_transmit7_triggered_returnLabel#15 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 823122#L1548-42 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 823120#L1548-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 823118#L745-42 assume 1 == ~t8_pc~0; 823116#L746-14 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 823113#L756-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 823110#is_transmit8_triggered_returnLabel#15 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 823108#L1556-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 823106#L1556-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 823104#L764-42 assume 1 == ~t9_pc~0; 823101#L765-14 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 823099#L775-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 823097#is_transmit9_triggered_returnLabel#15 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 823096#L1564-42 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 823095#L1564-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 823094#L783-42 assume !(1 == ~t10_pc~0); 823092#L783-44 is_transmit10_triggered_~__retres1~10#1 := 0; 823091#L794-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 823089#is_transmit10_triggered_returnLabel#15 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 823087#L1572-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 823085#L1572-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 823083#L802-42 assume 1 == ~t11_pc~0; 823080#L803-14 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 823078#L813-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 823076#is_transmit11_triggered_returnLabel#15 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 823073#L1580-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 823071#L1580-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 823069#L821-42 assume !(1 == ~t12_pc~0); 823066#L821-44 is_transmit12_triggered_~__retres1~12#1 := 0; 823064#L832-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 823062#is_transmit12_triggered_returnLabel#15 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 823060#L1588-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 823058#L1588-44 havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 823056#L1339-3 assume 1 == ~M_E~0;~M_E~0 := 2; 823054#L1339-5 assume !(1 == ~T1_E~0); 823052#L1344-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 801322#L1349-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 823046#L1354-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 823044#L1359-3 assume !(1 == ~T5_E~0); 823042#L1364-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 823040#L1369-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 823038#L1374-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 823036#L1379-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 823033#L1384-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 823031#L1389-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 823029#L1394-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 823027#L1399-3 assume !(1 == ~E_M~0); 823025#L1404-3 assume 1 == ~E_1~0;~E_1~0 := 2; 823023#L1409-3 assume 1 == ~E_2~0;~E_2~0 := 2; 823020#L1414-3 assume 1 == ~E_3~0;~E_3~0 := 2; 823018#L1419-3 assume 1 == ~E_4~0;~E_4~0 := 2; 802862#L1424-3 assume 1 == ~E_5~0;~E_5~0 := 2; 823015#L1429-3 assume 1 == ~E_6~0;~E_6~0 := 2; 823013#L1434-3 assume 1 == ~E_7~0;~E_7~0 := 2; 823011#L1439-3 assume !(1 == ~E_8~0); 823008#L1444-3 assume 1 == ~E_9~0;~E_9~0 := 2; 823006#L1449-3 assume 1 == ~E_10~0;~E_10~0 := 2; 823004#L1454-3 assume 1 == ~E_11~0;~E_11~0 := 2; 823002#L1459-3 assume 1 == ~E_12~0;~E_12~0 := 2; 812246#L1464-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 822999#L921-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 822980#L988-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 822585#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; 822573#L1829 assume !(0 == start_simulation_~tmp~3#1); 822567#L1829-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 822072#L921-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 822059#L988-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 822057#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret33#1;havoc stop_simulation_#t~ret33#1; 822055#L1784 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 822054#L1791 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 822052#stop_simulation_returnLabel#1 start_simulation_#t~ret35#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 822024#L1842 assume !(0 != start_simulation_~tmp___0~1#1); 822002#L1810-2 [2023-11-12 02:04:22,817 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-12 02:04:22,817 INFO L85 PathProgramCache]: Analyzing trace with hash 2145928902, now seen corresponding path program 1 times [2023-11-12 02:04:22,818 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-12 02:04:22,818 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1813738930] [2023-11-12 02:04:22,818 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-12 02:04:22,818 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-12 02:04:22,835 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-12 02:04:22,903 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-12 02:04:22,904 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-12 02:04:22,904 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1813738930] [2023-11-12 02:04:22,904 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1813738930] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-12 02:04:22,904 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-12 02:04:22,904 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-12 02:04:22,904 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1324679118] [2023-11-12 02:04:22,905 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-12 02:04:22,905 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-12 02:04:22,905 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-12 02:04:22,906 INFO L85 PathProgramCache]: Analyzing trace with hash 1569935141, now seen corresponding path program 1 times [2023-11-12 02:04:22,906 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-12 02:04:22,906 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1153814733] [2023-11-12 02:04:22,906 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-12 02:04:22,906 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-12 02:04:22,922 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-12 02:04:22,962 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-12 02:04:22,963 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-12 02:04:22,963 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1153814733] [2023-11-12 02:04:22,963 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1153814733] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-12 02:04:22,963 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-12 02:04:22,963 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-12 02:04:22,964 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1070856586] [2023-11-12 02:04:22,964 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-12 02:04:22,964 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-12 02:04:22,964 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-12 02:04:22,965 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2023-11-12 02:04:22,965 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2023-11-12 02:04:22,965 INFO L87 Difference]: Start difference. First operand 175008 states and 250102 transitions. cyclomatic complexity: 75126 Second operand has 4 states, 4 states have (on average 37.5) internal successors, (150), 3 states have internal predecessors, (150), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-12 02:04:25,044 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-12 02:04:25,044 INFO L93 Difference]: Finished difference Result 424415 states and 603019 transitions. [2023-11-12 02:04:25,044 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 424415 states and 603019 transitions. [2023-11-12 02:04:27,549 INFO L131 ngComponentsAnalysis]: Automaton has 48 accepting balls. 417440 [2023-11-12 02:04:29,116 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 424415 states to 424415 states and 603019 transitions. [2023-11-12 02:04:29,117 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 424415 [2023-11-12 02:04:29,288 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 424415 [2023-11-12 02:04:29,288 INFO L73 IsDeterministic]: Start isDeterministic. Operand 424415 states and 603019 transitions. [2023-11-12 02:04:29,422 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-12 02:04:29,423 INFO L218 hiAutomatonCegarLoop]: Abstraction has 424415 states and 603019 transitions. [2023-11-12 02:04:29,626 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 424415 states and 603019 transitions. [2023-11-12 02:04:32,837 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 424415 to 335967. [2023-11-12 02:04:33,993 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 335967 states, 335967 states have (on average 1.424529790128197) internal successors, (478595), 335966 states have internal predecessors, (478595), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0)