./Ultimate.py --spec ../../sv-benchmarks/c/properties/termination.prp --file ../../sv-benchmarks/c/systemc/transmitter.03.cil.c --full-output --architecture 32bit -------------------------------------------------------------------------------- Checking for termination Using default analysis Version cf1a7837 Calling Ultimate with: /usr/lib/jvm/java-1.11.0-openjdk-amd64/bin/java -Dosgi.configuration.area=/tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_215f6841-0d75-460b-aa2b-6df37e285065/bin/uautomizer-verify-uTZkv6EMXl/data/config -Xmx15G -Xms4m -jar /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_215f6841-0d75-460b-aa2b-6df37e285065/bin/uautomizer-verify-uTZkv6EMXl/plugins/org.eclipse.equinox.launcher_1.5.800.v20200727-1323.jar -data @noDefault -ultimatedata /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_215f6841-0d75-460b-aa2b-6df37e285065/bin/uautomizer-verify-uTZkv6EMXl/data -tc /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_215f6841-0d75-460b-aa2b-6df37e285065/bin/uautomizer-verify-uTZkv6EMXl/config/AutomizerTermination.xml -i ../../sv-benchmarks/c/systemc/transmitter.03.cil.c -s /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_215f6841-0d75-460b-aa2b-6df37e285065/bin/uautomizer-verify-uTZkv6EMXl/config/svcomp-Termination-32bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_215f6841-0d75-460b-aa2b-6df37e285065/bin/uautomizer-verify-uTZkv6EMXl --witnessprinter.witness.filename witness --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(F end) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 32bit --witnessprinter.graph.data.programhash 4edad7c083448b81b05575191757512095bfff0f094103ddb1a592d0cd702494 --- Real Ultimate output --- This is Ultimate 0.2.3-dev-cf1a783 [2023-11-12 02:32:07,432 INFO L188 SettingsManager]: Resetting all preferences to default values... [2023-11-12 02:32:07,572 INFO L114 SettingsManager]: Loading settings from /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_215f6841-0d75-460b-aa2b-6df37e285065/bin/uautomizer-verify-uTZkv6EMXl/config/svcomp-Termination-32bit-Automizer_Default.epf [2023-11-12 02:32:07,581 WARN L101 SettingsManager]: Preference file contains the following unknown settings: [2023-11-12 02:32:07,582 WARN L103 SettingsManager]: * de.uni_freiburg.informatik.ultimate.core.Log level for class [2023-11-12 02:32:07,630 INFO L130 SettingsManager]: Preferences different from defaults after loading the file: [2023-11-12 02:32:07,631 INFO L151 SettingsManager]: Preferences of UltimateCore differ from their defaults: [2023-11-12 02:32:07,631 INFO L153 SettingsManager]: * Log level for class=de.uni_freiburg.informatik.ultimate.lib.smtlibutils.quantifier.QuantifierPusher=ERROR; [2023-11-12 02:32:07,633 INFO L151 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2023-11-12 02:32:07,639 INFO L153 SettingsManager]: * Create parallel compositions if possible=false [2023-11-12 02:32:07,640 INFO L153 SettingsManager]: * Use SBE=true [2023-11-12 02:32:07,641 INFO L151 SettingsManager]: Preferences of BuchiAutomizer differ from their defaults: [2023-11-12 02:32:07,641 INFO L153 SettingsManager]: * NCSB implementation=INTSET_LAZY3 [2023-11-12 02:32:07,644 INFO L153 SettingsManager]: * Use old map elimination=false [2023-11-12 02:32:07,644 INFO L153 SettingsManager]: * Use external solver (rank synthesis)=false [2023-11-12 02:32:07,645 INFO L153 SettingsManager]: * Use only trivial implications for array writes=true [2023-11-12 02:32:07,646 INFO L153 SettingsManager]: * Rank analysis=LINEAR_WITH_GUESSES [2023-11-12 02:32:07,647 INFO L151 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2023-11-12 02:32:07,647 INFO L153 SettingsManager]: * Pointer base address is valid at dereference=ASSUME [2023-11-12 02:32:07,648 INFO L153 SettingsManager]: * sizeof long=4 [2023-11-12 02:32:07,649 INFO L153 SettingsManager]: * Overapproximate operations on floating types=true [2023-11-12 02:32:07,650 INFO L153 SettingsManager]: * sizeof POINTER=4 [2023-11-12 02:32:07,650 INFO L153 SettingsManager]: * Check division by zero=IGNORE [2023-11-12 02:32:07,651 INFO L153 SettingsManager]: * Pointer to allocated memory at dereference=ASSUME [2023-11-12 02:32:07,651 INFO L153 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=ASSUME [2023-11-12 02:32:07,652 INFO L153 SettingsManager]: * Check array bounds for arrays that are off heap=ASSUME [2023-11-12 02:32:07,653 INFO L153 SettingsManager]: * Check unreachability of reach_error function=false [2023-11-12 02:32:07,653 INFO L153 SettingsManager]: * sizeof long double=12 [2023-11-12 02:32:07,654 INFO L153 SettingsManager]: * Check if freed pointer was valid=false [2023-11-12 02:32:07,654 INFO L153 SettingsManager]: * Assume nondeterminstic values are in range=false [2023-11-12 02:32:07,656 INFO L153 SettingsManager]: * Use constant arrays=true [2023-11-12 02:32:07,657 INFO L151 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2023-11-12 02:32:07,657 INFO L153 SettingsManager]: * Size of a code block=SequenceOfStatements [2023-11-12 02:32:07,658 INFO L151 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2023-11-12 02:32:07,658 INFO L153 SettingsManager]: * Trace refinement strategy=CAMEL [2023-11-12 02:32:07,659 INFO L151 SettingsManager]: Preferences of IcfgTransformer differ from their defaults: [2023-11-12 02:32:07,660 INFO L153 SettingsManager]: * TransformationType=MODULO_NEIGHBOR WARNING: An illegal reflective access operation has occurred WARNING: Illegal reflective access by com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 (file:/tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_215f6841-0d75-460b-aa2b-6df37e285065/bin/uautomizer-verify-uTZkv6EMXl/plugins/com.sun.xml.bind_2.2.0.v201505121915.jar) to method java.lang.ClassLoader.defineClass(java.lang.String,byte[],int,int) WARNING: Please consider reporting this to the maintainers of com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 WARNING: Use --illegal-access=warn to enable warnings of further illegal reflective access operations WARNING: All illegal access operations will be denied in a future release Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_215f6841-0d75-460b-aa2b-6df37e285065/bin/uautomizer-verify-uTZkv6EMXl Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(F end) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 32bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> 4edad7c083448b81b05575191757512095bfff0f094103ddb1a592d0cd702494 [2023-11-12 02:32:08,053 INFO L75 nceAwareModelManager]: Repository-Root is: /tmp [2023-11-12 02:32:08,090 INFO L261 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2023-11-12 02:32:08,093 INFO L217 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2023-11-12 02:32:08,095 INFO L270 PluginConnector]: Initializing CDTParser... [2023-11-12 02:32:08,096 INFO L274 PluginConnector]: CDTParser initialized [2023-11-12 02:32:08,098 INFO L431 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_215f6841-0d75-460b-aa2b-6df37e285065/bin/uautomizer-verify-uTZkv6EMXl/../../sv-benchmarks/c/systemc/transmitter.03.cil.c [2023-11-12 02:32:11,396 INFO L533 CDTParser]: Created temporary CDT project at NULL [2023-11-12 02:32:11,667 INFO L384 CDTParser]: Found 1 translation units. [2023-11-12 02:32:11,667 INFO L180 CDTParser]: Scanning /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_215f6841-0d75-460b-aa2b-6df37e285065/sv-benchmarks/c/systemc/transmitter.03.cil.c [2023-11-12 02:32:11,680 INFO L427 CDTParser]: About to delete temporary CDT project at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_215f6841-0d75-460b-aa2b-6df37e285065/bin/uautomizer-verify-uTZkv6EMXl/data/b859f9cf0/d36353e3d18e4a0ba51c27552db9aa21/FLAG350108df0 [2023-11-12 02:32:11,696 INFO L435 CDTParser]: Successfully deleted /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_215f6841-0d75-460b-aa2b-6df37e285065/bin/uautomizer-verify-uTZkv6EMXl/data/b859f9cf0/d36353e3d18e4a0ba51c27552db9aa21 [2023-11-12 02:32:11,699 INFO L299 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2023-11-12 02:32:11,701 INFO L133 ToolchainWalker]: Walking toolchain with 6 elements. [2023-11-12 02:32:11,703 INFO L112 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2023-11-12 02:32:11,703 INFO L270 PluginConnector]: Initializing CACSL2BoogieTranslator... [2023-11-12 02:32:11,710 INFO L274 PluginConnector]: CACSL2BoogieTranslator initialized [2023-11-12 02:32:11,711 INFO L184 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 12.11 02:32:11" (1/1) ... [2023-11-12 02:32:11,712 INFO L204 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@6fd16501 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 12.11 02:32:11, skipping insertion in model container [2023-11-12 02:32:11,713 INFO L184 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 12.11 02:32:11" (1/1) ... [2023-11-12 02:32:11,756 INFO L177 MainTranslator]: Built tables and reachable declarations [2023-11-12 02:32:11,990 INFO L209 PostProcessor]: Analyzing one entry point: main [2023-11-12 02:32:12,007 INFO L202 MainTranslator]: Completed pre-run [2023-11-12 02:32:12,059 INFO L209 PostProcessor]: Analyzing one entry point: main [2023-11-12 02:32:12,083 INFO L206 MainTranslator]: Completed translation [2023-11-12 02:32:12,083 INFO L201 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 12.11 02:32:12 WrapperNode [2023-11-12 02:32:12,084 INFO L131 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2023-11-12 02:32:12,085 INFO L112 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2023-11-12 02:32:12,086 INFO L270 PluginConnector]: Initializing Boogie Procedure Inliner... [2023-11-12 02:32:12,086 INFO L274 PluginConnector]: Boogie Procedure Inliner initialized [2023-11-12 02:32:12,095 INFO L184 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 12.11 02:32:12" (1/1) ... [2023-11-12 02:32:12,107 INFO L184 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 12.11 02:32:12" (1/1) ... [2023-11-12 02:32:12,165 INFO L138 Inliner]: procedures = 34, calls = 40, calls flagged for inlining = 35, calls inlined = 57, statements flattened = 741 [2023-11-12 02:32:12,165 INFO L131 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2023-11-12 02:32:12,166 INFO L112 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2023-11-12 02:32:12,166 INFO L270 PluginConnector]: Initializing Boogie Preprocessor... [2023-11-12 02:32:12,167 INFO L274 PluginConnector]: Boogie Preprocessor initialized [2023-11-12 02:32:12,176 INFO L184 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 12.11 02:32:12" (1/1) ... [2023-11-12 02:32:12,177 INFO L184 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 12.11 02:32:12" (1/1) ... [2023-11-12 02:32:12,182 INFO L184 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 12.11 02:32:12" (1/1) ... [2023-11-12 02:32:12,183 INFO L184 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 12.11 02:32:12" (1/1) ... [2023-11-12 02:32:12,197 INFO L184 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 12.11 02:32:12" (1/1) ... [2023-11-12 02:32:12,209 INFO L184 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 12.11 02:32:12" (1/1) ... [2023-11-12 02:32:12,214 INFO L184 PluginConnector]: Executing the observer LTLStepAnnotator from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 12.11 02:32:12" (1/1) ... [2023-11-12 02:32:12,217 INFO L184 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 12.11 02:32:12" (1/1) ... [2023-11-12 02:32:12,225 INFO L131 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2023-11-12 02:32:12,226 INFO L112 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2023-11-12 02:32:12,226 INFO L270 PluginConnector]: Initializing RCFGBuilder... [2023-11-12 02:32:12,226 INFO L274 PluginConnector]: RCFGBuilder initialized [2023-11-12 02:32:12,227 INFO L184 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 12.11 02:32:12" (1/1) ... [2023-11-12 02:32:12,237 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2023-11-12 02:32:12,265 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_215f6841-0d75-460b-aa2b-6df37e285065/bin/uautomizer-verify-uTZkv6EMXl/z3 [2023-11-12 02:32:12,288 INFO L229 MonitoredProcess]: Starting monitored process 1 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_215f6841-0d75-460b-aa2b-6df37e285065/bin/uautomizer-verify-uTZkv6EMXl/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2023-11-12 02:32:12,317 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_215f6841-0d75-460b-aa2b-6df37e285065/bin/uautomizer-verify-uTZkv6EMXl/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (1)] Waiting until timeout for monitored process [2023-11-12 02:32:12,342 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocInit [2023-11-12 02:32:12,342 INFO L130 BoogieDeclarations]: Found specification of procedure write~init~int [2023-11-12 02:32:12,342 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2023-11-12 02:32:12,342 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2023-11-12 02:32:12,440 INFO L236 CfgBuilder]: Building ICFG [2023-11-12 02:32:12,442 INFO L262 CfgBuilder]: Building CFG for each procedure with an implementation [2023-11-12 02:32:13,363 INFO L277 CfgBuilder]: Performing block encoding [2023-11-12 02:32:13,378 INFO L297 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2023-11-12 02:32:13,378 INFO L302 CfgBuilder]: Removed 7 assume(true) statements. [2023-11-12 02:32:13,381 INFO L201 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 12.11 02:32:13 BoogieIcfgContainer [2023-11-12 02:32:13,382 INFO L131 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2023-11-12 02:32:13,383 INFO L112 PluginConnector]: ------------------------BuchiAutomizer---------------------------- [2023-11-12 02:32:13,383 INFO L270 PluginConnector]: Initializing BuchiAutomizer... [2023-11-12 02:32:13,388 INFO L274 PluginConnector]: BuchiAutomizer initialized [2023-11-12 02:32:13,389 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2023-11-12 02:32:13,389 INFO L184 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "CDTParser AST 12.11 02:32:11" (1/3) ... [2023-11-12 02:32:13,391 INFO L204 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@696a23a1 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 12.11 02:32:13, skipping insertion in model container [2023-11-12 02:32:13,391 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2023-11-12 02:32:13,391 INFO L184 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 12.11 02:32:12" (2/3) ... [2023-11-12 02:32:13,392 INFO L204 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@696a23a1 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 12.11 02:32:13, skipping insertion in model container [2023-11-12 02:32:13,392 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2023-11-12 02:32:13,392 INFO L184 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 12.11 02:32:13" (3/3) ... [2023-11-12 02:32:13,394 INFO L332 chiAutomizerObserver]: Analyzing ICFG transmitter.03.cil.c [2023-11-12 02:32:13,491 INFO L303 stractBuchiCegarLoop]: Interprodecural is true [2023-11-12 02:32:13,491 INFO L304 stractBuchiCegarLoop]: Hoare is false [2023-11-12 02:32:13,491 INFO L305 stractBuchiCegarLoop]: Compute interpolants for ForwardPredicates [2023-11-12 02:32:13,491 INFO L306 stractBuchiCegarLoop]: Backedges is STRAIGHT_LINE [2023-11-12 02:32:13,492 INFO L307 stractBuchiCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2023-11-12 02:32:13,492 INFO L308 stractBuchiCegarLoop]: Difference is false [2023-11-12 02:32:13,493 INFO L309 stractBuchiCegarLoop]: Minimize is MINIMIZE_SEVPA [2023-11-12 02:32:13,493 INFO L313 stractBuchiCegarLoop]: ======== Iteration 0 == of CEGAR loop == BuchiAutomatonCegarLoop ======== [2023-11-12 02:32:13,503 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 296 states, 295 states have (on average 1.5322033898305085) internal successors, (452), 295 states have internal predecessors, (452), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-12 02:32:13,571 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 239 [2023-11-12 02:32:13,572 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-12 02:32:13,572 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-12 02:32:13,586 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-12 02:32:13,586 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-12 02:32:13,587 INFO L335 stractBuchiCegarLoop]: ======== Iteration 1 ============ [2023-11-12 02:32:13,588 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 296 states, 295 states have (on average 1.5322033898305085) internal successors, (452), 295 states have internal predecessors, (452), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-12 02:32:13,607 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 239 [2023-11-12 02:32:13,610 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-12 02:32:13,610 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-12 02:32:13,614 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-12 02:32:13,614 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-12 02:32:13,629 INFO L748 eck$LassoCheckResult]: Stem: 192#$Ultimate##0true assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2; 205#L-1true assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~5#1;havoc main_~__retres1~5#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1; 292#init_model_returnLabel#1true assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret14#1, start_simulation_#t~ret15#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 200#update_channels_returnLabel#1true assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 178#L281true assume !(1 == ~m_i~0);~m_st~0 := 2; 241#L281-2true assume 1 == ~t1_i~0;~t1_st~0 := 0; 35#L286-1true assume !(1 == ~t2_i~0);~t2_st~0 := 2; 219#L291-1true assume !(1 == ~t3_i~0);~t3_st~0 := 2; 236#L296-1true assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 17#L418true assume !(0 == ~M_E~0); 177#L418-2true assume !(0 == ~T1_E~0); 227#L423-1true assume 0 == ~T2_E~0;~T2_E~0 := 1; 239#L428-1true assume !(0 == ~T3_E~0); 223#L433-1true assume !(0 == ~E_1~0); 209#L438-1true assume !(0 == ~E_2~0); 135#L443-1true assume !(0 == ~E_3~0); 130#L448-1true assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 96#L197true assume !(1 == ~m_pc~0); 268#L197-2true is_master_triggered_~__retres1~0#1 := 0; 271#L208true is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 170#is_master_triggered_returnLabel#1true activate_threads_#t~ret9#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 247#L510true assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 7#L510-2true assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 269#L216true assume 1 == ~t1_pc~0; 29#L217true assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 125#L227true is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 49#is_transmit1_triggered_returnLabel#1true activate_threads_#t~ret10#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 8#L518true assume !(0 != activate_threads_~tmp___0~0#1); 143#L518-2true assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 278#L235true assume !(1 == ~t2_pc~0); 215#L235-2true is_transmit2_triggered_~__retres1~2#1 := 0; 85#L246true is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 293#is_transmit2_triggered_returnLabel#1true activate_threads_#t~ret11#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 256#L526true assume !(0 != activate_threads_~tmp___1~0#1); 267#L526-2true assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 75#L254true assume 1 == ~t3_pc~0; 22#L255true assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 91#L265true is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 13#is_transmit3_triggered_returnLabel#1true activate_threads_#t~ret12#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 116#L534true assume !(0 != activate_threads_~tmp___2~0#1); 81#L534-2true havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 2#L461true assume !(1 == ~M_E~0); 36#L461-2true assume !(1 == ~T1_E~0); 237#L466-1true assume !(1 == ~T2_E~0); 274#L471-1true assume 1 == ~T3_E~0;~T3_E~0 := 2; 50#L476-1true assume !(1 == ~E_1~0); 277#L481-1true assume !(1 == ~E_2~0); 157#L486-1true assume !(1 == ~E_3~0); 59#L491-1true assume { :end_inline_reset_delta_events } true; 11#L652-2true [2023-11-12 02:32:13,638 INFO L750 eck$LassoCheckResult]: Loop: 11#L652-2true assume !false; 67#L653true start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 162#L393-1true assume false; 114#eval_returnLabel#1true havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 147#update_channels_returnLabel#2true assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 294#L418-3true assume 0 == ~M_E~0;~M_E~0 := 1; 142#L418-5true assume 0 == ~T1_E~0;~T1_E~0 := 1; 166#L423-3true assume 0 == ~T2_E~0;~T2_E~0 := 1; 137#L428-3true assume 0 == ~T3_E~0;~T3_E~0 := 1; 95#L433-3true assume !(0 == ~E_1~0); 186#L438-3true assume 0 == ~E_2~0;~E_2~0 := 1; 193#L443-3true assume 0 == ~E_3~0;~E_3~0 := 1; 3#L448-3true assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 195#L197-12true assume 1 == ~m_pc~0; 201#L198-4true assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 73#L208-4true is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 141#is_master_triggered_returnLabel#5true activate_threads_#t~ret9#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 10#L510-12true assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 111#L510-14true assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 72#L216-12true assume 1 == ~t1_pc~0; 286#L217-4true assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 108#L227-4true is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 243#is_transmit1_triggered_returnLabel#5true activate_threads_#t~ret10#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 78#L518-12true assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 34#L518-14true assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 282#L235-12true assume 1 == ~t2_pc~0; 207#L236-4true assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 257#L246-4true is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 79#is_transmit2_triggered_returnLabel#5true activate_threads_#t~ret11#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 289#L526-12true assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 131#L526-14true assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 250#L254-12true assume 1 == ~t3_pc~0; 25#L255-4true assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 134#L265-4true is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 51#is_transmit3_triggered_returnLabel#5true activate_threads_#t~ret12#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 113#L534-12true assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 158#L534-14true havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 74#L461-3true assume 1 == ~M_E~0;~M_E~0 := 2; 295#L461-5true assume 1 == ~T1_E~0;~T1_E~0 := 2; 148#L466-3true assume 1 == ~T2_E~0;~T2_E~0 := 2; 246#L471-3true assume 1 == ~T3_E~0;~T3_E~0 := 2; 69#L476-3true assume 1 == ~E_1~0;~E_1~0 := 2; 139#L481-3true assume !(1 == ~E_2~0); 90#L486-3true assume 1 == ~E_3~0;~E_3~0 := 2; 264#L491-3true assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 24#L309-1true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 37#L331-1true exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 259#exists_runnable_thread_returnLabel#2true start_simulation_#t~ret14#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret14#1;havoc start_simulation_#t~ret14#1; 149#L671true assume !(0 == start_simulation_~tmp~3#1); 183#L671-2true assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret13#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 296#L309-2true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 155#L331-2true exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 48#exists_runnable_thread_returnLabel#3true stop_simulation_#t~ret13#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret13#1;havoc stop_simulation_#t~ret13#1; 234#L626true assume !(0 != stop_simulation_~tmp~2#1);stop_simulation_~__retres2~0#1 := 1; 161#L633true stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 164#stop_simulation_returnLabel#1true start_simulation_#t~ret15#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret13#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret15#1;havoc start_simulation_#t~ret15#1; 169#L684true assume !(0 != start_simulation_~tmp___0~1#1); 11#L652-2true [2023-11-12 02:32:13,648 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-12 02:32:13,649 INFO L85 PathProgramCache]: Analyzing trace with hash -1773697160, now seen corresponding path program 1 times [2023-11-12 02:32:13,662 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-12 02:32:13,663 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [529332715] [2023-11-12 02:32:13,663 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-12 02:32:13,665 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-12 02:32:13,814 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-12 02:32:14,028 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-12 02:32:14,029 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-12 02:32:14,029 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [529332715] [2023-11-12 02:32:14,030 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [529332715] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-12 02:32:14,031 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-12 02:32:14,031 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-12 02:32:14,033 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1984799586] [2023-11-12 02:32:14,035 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-12 02:32:14,042 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-12 02:32:14,045 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-12 02:32:14,045 INFO L85 PathProgramCache]: Analyzing trace with hash -1698573144, now seen corresponding path program 1 times [2023-11-12 02:32:14,045 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-12 02:32:14,046 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1750741454] [2023-11-12 02:32:14,046 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-12 02:32:14,046 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-12 02:32:14,084 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-12 02:32:14,139 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-12 02:32:14,141 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-12 02:32:14,141 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1750741454] [2023-11-12 02:32:14,142 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1750741454] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-12 02:32:14,142 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-12 02:32:14,142 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2023-11-12 02:32:14,142 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [827574158] [2023-11-12 02:32:14,143 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-12 02:32:14,154 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-12 02:32:14,155 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-12 02:32:14,208 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-12 02:32:14,209 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-12 02:32:14,213 INFO L87 Difference]: Start difference. First operand has 296 states, 295 states have (on average 1.5322033898305085) internal successors, (452), 295 states have internal predecessors, (452), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand has 3 states, 3 states have (on average 16.333333333333332) internal successors, (49), 3 states have internal predecessors, (49), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-12 02:32:14,291 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-12 02:32:14,293 INFO L93 Difference]: Finished difference Result 294 states and 434 transitions. [2023-11-12 02:32:14,295 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 294 states and 434 transitions. [2023-11-12 02:32:14,305 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 235 [2023-11-12 02:32:14,319 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 294 states to 288 states and 428 transitions. [2023-11-12 02:32:14,321 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 288 [2023-11-12 02:32:14,322 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 288 [2023-11-12 02:32:14,323 INFO L73 IsDeterministic]: Start isDeterministic. Operand 288 states and 428 transitions. [2023-11-12 02:32:14,325 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-12 02:32:14,326 INFO L218 hiAutomatonCegarLoop]: Abstraction has 288 states and 428 transitions. [2023-11-12 02:32:14,345 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 288 states and 428 transitions. [2023-11-12 02:32:14,368 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 288 to 288. [2023-11-12 02:32:14,370 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 288 states, 288 states have (on average 1.4861111111111112) internal successors, (428), 287 states have internal predecessors, (428), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-12 02:32:14,371 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 288 states to 288 states and 428 transitions. [2023-11-12 02:32:14,372 INFO L240 hiAutomatonCegarLoop]: Abstraction has 288 states and 428 transitions. [2023-11-12 02:32:14,374 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-12 02:32:14,377 INFO L428 stractBuchiCegarLoop]: Abstraction has 288 states and 428 transitions. [2023-11-12 02:32:14,378 INFO L335 stractBuchiCegarLoop]: ======== Iteration 2 ============ [2023-11-12 02:32:14,378 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 288 states and 428 transitions. [2023-11-12 02:32:14,381 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 235 [2023-11-12 02:32:14,381 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-12 02:32:14,381 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-12 02:32:14,383 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-12 02:32:14,383 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-12 02:32:14,384 INFO L748 eck$LassoCheckResult]: Stem: 857#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2; 858#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~5#1;havoc main_~__retres1~5#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1; 867#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret14#1, start_simulation_#t~ret15#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 866#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 841#L281 assume 1 == ~m_i~0;~m_st~0 := 0; 842#L281-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 668#L286-1 assume !(1 == ~t2_i~0);~t2_st~0 := 2; 669#L291-1 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 874#L296-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 628#L418 assume !(0 == ~M_E~0); 629#L418-2 assume !(0 == ~T1_E~0); 840#L423-1 assume 0 == ~T2_E~0;~T2_E~0 := 1; 877#L428-1 assume !(0 == ~T3_E~0); 875#L433-1 assume !(0 == ~E_1~0); 869#L438-1 assume !(0 == ~E_2~0); 806#L443-1 assume !(0 == ~E_3~0); 800#L448-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 767#L197 assume !(1 == ~m_pc~0); 764#L197-2 is_master_triggered_~__retres1~0#1 := 0; 763#L208 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 833#is_master_triggered_returnLabel#1 activate_threads_#t~ret9#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 834#L510 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 607#L510-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 608#L216 assume 1 == ~t1_pc~0; 656#L217 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 657#L227 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 693#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret10#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 609#L518 assume !(0 != activate_threads_~tmp___0~0#1); 610#L518-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 814#L235 assume !(1 == ~t2_pc~0); 871#L235-2 is_transmit2_triggered_~__retres1~2#1 := 0; 752#L246 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 753#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret11#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 882#L526 assume !(0 != activate_threads_~tmp___1~0#1); 883#L526-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 735#L254 assume 1 == ~t3_pc~0; 638#L255 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 639#L265 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 620#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 621#L534 assume !(0 != activate_threads_~tmp___2~0#1); 746#L534-2 havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 599#L461 assume !(1 == ~M_E~0); 600#L461-2 assume !(1 == ~T1_E~0); 670#L466-1 assume !(1 == ~T2_E~0); 880#L471-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 696#L476-1 assume !(1 == ~E_1~0); 697#L481-1 assume !(1 == ~E_2~0); 828#L486-1 assume !(1 == ~E_3~0); 711#L491-1 assume { :end_inline_reset_delta_events } true; 618#L652-2 [2023-11-12 02:32:14,384 INFO L750 eck$LassoCheckResult]: Loop: 618#L652-2 assume !false; 619#L653 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 688#L393-1 assume !false; 685#L342 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 686#L309 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 664#L331 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 622#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 623#L346 assume !(0 != eval_~tmp~0#1); 716#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 787#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 818#L418-3 assume 0 == ~M_E~0;~M_E~0 := 1; 811#L418-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 812#L423-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 809#L428-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 765#L433-3 assume !(0 == ~E_1~0); 766#L438-3 assume 0 == ~E_2~0;~E_2~0 := 1; 853#L443-3 assume 0 == ~E_3~0;~E_3~0 := 1; 601#L448-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 602#L197-12 assume 1 == ~m_pc~0; 859#L198-4 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 731#L208-4 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 732#is_master_triggered_returnLabel#5 activate_threads_#t~ret9#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 614#L510-12 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 615#L510-14 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 728#L216-12 assume !(1 == ~t1_pc~0); 729#L216-14 is_transmit1_triggered_~__retres1~1#1 := 0; 781#L227-4 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 782#is_transmit1_triggered_returnLabel#5 activate_threads_#t~ret10#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 741#L518-12 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 666#L518-14 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 667#L235-12 assume 1 == ~t2_pc~0; 868#L236-4 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 750#L246-4 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 742#is_transmit2_triggered_returnLabel#5 activate_threads_#t~ret11#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 743#L526-12 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 801#L526-14 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 802#L254-12 assume 1 == ~t3_pc~0; 647#L255-4 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 648#L265-4 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 694#is_transmit3_triggered_returnLabel#5 activate_threads_#t~ret12#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 695#L534-12 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 786#L534-14 havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 733#L461-3 assume 1 == ~M_E~0;~M_E~0 := 2; 734#L461-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 819#L466-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 820#L471-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 725#L476-3 assume 1 == ~E_1~0;~E_1~0 := 2; 726#L481-3 assume !(1 == ~E_2~0); 757#L486-3 assume 1 == ~E_3~0;~E_3~0 := 2; 758#L491-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 641#L309-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 642#L331-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 671#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret14#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret14#1;havoc start_simulation_#t~ret14#1; 821#L671 assume !(0 == start_simulation_~tmp~3#1); 625#L671-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret13#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 846#L309-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 723#L331-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 691#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret13#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret13#1;havoc stop_simulation_#t~ret13#1; 692#L626 assume !(0 != stop_simulation_~tmp~2#1);stop_simulation_~__retres2~0#1 := 1; 829#L633 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 830#stop_simulation_returnLabel#1 start_simulation_#t~ret15#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret13#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret15#1;havoc start_simulation_#t~ret15#1; 831#L684 assume !(0 != start_simulation_~tmp___0~1#1); 618#L652-2 [2023-11-12 02:32:14,385 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-12 02:32:14,385 INFO L85 PathProgramCache]: Analyzing trace with hash 1627783798, now seen corresponding path program 1 times [2023-11-12 02:32:14,385 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-12 02:32:14,386 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [29716863] [2023-11-12 02:32:14,386 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-12 02:32:14,386 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-12 02:32:14,399 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-12 02:32:14,444 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-12 02:32:14,444 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-12 02:32:14,444 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [29716863] [2023-11-12 02:32:14,445 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [29716863] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-12 02:32:14,445 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-12 02:32:14,445 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-12 02:32:14,445 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1491807756] [2023-11-12 02:32:14,446 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-12 02:32:14,446 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-12 02:32:14,446 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-12 02:32:14,447 INFO L85 PathProgramCache]: Analyzing trace with hash 1274205792, now seen corresponding path program 1 times [2023-11-12 02:32:14,447 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-12 02:32:14,447 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [235227473] [2023-11-12 02:32:14,447 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-12 02:32:14,448 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-12 02:32:14,513 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-12 02:32:14,646 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-12 02:32:14,647 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-12 02:32:14,647 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [235227473] [2023-11-12 02:32:14,647 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [235227473] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-12 02:32:14,647 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-12 02:32:14,648 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-12 02:32:14,648 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1579140850] [2023-11-12 02:32:14,648 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-12 02:32:14,649 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-12 02:32:14,649 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-12 02:32:14,649 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-12 02:32:14,650 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-12 02:32:14,650 INFO L87 Difference]: Start difference. First operand 288 states and 428 transitions. cyclomatic complexity: 141 Second operand has 3 states, 3 states have (on average 16.333333333333332) internal successors, (49), 3 states have internal predecessors, (49), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-12 02:32:14,669 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-12 02:32:14,669 INFO L93 Difference]: Finished difference Result 288 states and 427 transitions. [2023-11-12 02:32:14,669 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 288 states and 427 transitions. [2023-11-12 02:32:14,673 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 235 [2023-11-12 02:32:14,676 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 288 states to 288 states and 427 transitions. [2023-11-12 02:32:14,677 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 288 [2023-11-12 02:32:14,678 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 288 [2023-11-12 02:32:14,678 INFO L73 IsDeterministic]: Start isDeterministic. Operand 288 states and 427 transitions. [2023-11-12 02:32:14,680 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-12 02:32:14,680 INFO L218 hiAutomatonCegarLoop]: Abstraction has 288 states and 427 transitions. [2023-11-12 02:32:14,681 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 288 states and 427 transitions. [2023-11-12 02:32:14,694 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 288 to 288. [2023-11-12 02:32:14,695 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 288 states, 288 states have (on average 1.4826388888888888) internal successors, (427), 287 states have internal predecessors, (427), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-12 02:32:14,696 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 288 states to 288 states and 427 transitions. [2023-11-12 02:32:14,697 INFO L240 hiAutomatonCegarLoop]: Abstraction has 288 states and 427 transitions. [2023-11-12 02:32:14,697 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-12 02:32:14,698 INFO L428 stractBuchiCegarLoop]: Abstraction has 288 states and 427 transitions. [2023-11-12 02:32:14,698 INFO L335 stractBuchiCegarLoop]: ======== Iteration 3 ============ [2023-11-12 02:32:14,698 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 288 states and 427 transitions. [2023-11-12 02:32:14,701 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 235 [2023-11-12 02:32:14,701 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-12 02:32:14,702 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-12 02:32:14,704 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-12 02:32:14,704 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-12 02:32:14,705 INFO L748 eck$LassoCheckResult]: Stem: 1440#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2; 1441#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~5#1;havoc main_~__retres1~5#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1; 1450#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret14#1, start_simulation_#t~ret15#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 1449#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 1424#L281 assume 1 == ~m_i~0;~m_st~0 := 0; 1425#L281-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 1251#L286-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 1252#L291-1 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 1457#L296-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 1214#L418 assume !(0 == ~M_E~0); 1215#L418-2 assume !(0 == ~T1_E~0); 1423#L423-1 assume 0 == ~T2_E~0;~T2_E~0 := 1; 1460#L428-1 assume !(0 == ~T3_E~0); 1458#L433-1 assume !(0 == ~E_1~0); 1452#L438-1 assume !(0 == ~E_2~0); 1389#L443-1 assume !(0 == ~E_3~0); 1383#L448-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1350#L197 assume !(1 == ~m_pc~0); 1347#L197-2 is_master_triggered_~__retres1~0#1 := 0; 1346#L208 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1416#is_master_triggered_returnLabel#1 activate_threads_#t~ret9#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 1417#L510 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 1190#L510-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1191#L216 assume 1 == ~t1_pc~0; 1239#L217 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 1240#L227 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1276#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret10#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 1192#L518 assume !(0 != activate_threads_~tmp___0~0#1); 1193#L518-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1398#L235 assume !(1 == ~t2_pc~0); 1456#L235-2 is_transmit2_triggered_~__retres1~2#1 := 0; 1335#L246 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1336#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret11#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 1465#L526 assume !(0 != activate_threads_~tmp___1~0#1); 1466#L526-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1318#L254 assume 1 == ~t3_pc~0; 1221#L255 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 1222#L265 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1203#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 1204#L534 assume !(0 != activate_threads_~tmp___2~0#1); 1329#L534-2 havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1182#L461 assume !(1 == ~M_E~0); 1183#L461-2 assume !(1 == ~T1_E~0); 1253#L466-1 assume !(1 == ~T2_E~0); 1463#L471-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 1279#L476-1 assume !(1 == ~E_1~0); 1280#L481-1 assume !(1 == ~E_2~0); 1411#L486-1 assume !(1 == ~E_3~0); 1298#L491-1 assume { :end_inline_reset_delta_events } true; 1201#L652-2 [2023-11-12 02:32:14,705 INFO L750 eck$LassoCheckResult]: Loop: 1201#L652-2 assume !false; 1202#L653 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 1271#L393-1 assume !false; 1268#L342 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 1269#L309 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 1247#L331 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 1205#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 1206#L346 assume !(0 != eval_~tmp~0#1); 1299#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 1370#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 1401#L418-3 assume 0 == ~M_E~0;~M_E~0 := 1; 1394#L418-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 1395#L423-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 1392#L428-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 1348#L433-3 assume !(0 == ~E_1~0); 1349#L438-3 assume 0 == ~E_2~0;~E_2~0 := 1; 1436#L443-3 assume 0 == ~E_3~0;~E_3~0 := 1; 1184#L448-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1185#L197-12 assume 1 == ~m_pc~0; 1442#L198-4 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 1314#L208-4 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1315#is_master_triggered_returnLabel#5 activate_threads_#t~ret9#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 1197#L510-12 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 1198#L510-14 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1311#L216-12 assume !(1 == ~t1_pc~0); 1312#L216-14 is_transmit1_triggered_~__retres1~1#1 := 0; 1364#L227-4 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1365#is_transmit1_triggered_returnLabel#5 activate_threads_#t~ret10#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 1322#L518-12 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 1249#L518-14 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1250#L235-12 assume !(1 == ~t2_pc~0); 1332#L235-14 is_transmit2_triggered_~__retres1~2#1 := 0; 1333#L246-4 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1325#is_transmit2_triggered_returnLabel#5 activate_threads_#t~ret11#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 1326#L526-12 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 1384#L526-14 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1385#L254-12 assume !(1 == ~t3_pc~0); 1232#L254-14 is_transmit3_triggered_~__retres1~3#1 := 0; 1231#L265-4 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1277#is_transmit3_triggered_returnLabel#5 activate_threads_#t~ret12#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 1278#L534-12 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 1369#L534-14 havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1316#L461-3 assume 1 == ~M_E~0;~M_E~0 := 2; 1317#L461-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 1402#L466-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 1403#L471-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 1308#L476-3 assume 1 == ~E_1~0;~E_1~0 := 2; 1309#L481-3 assume !(1 == ~E_2~0); 1340#L486-3 assume 1 == ~E_3~0;~E_3~0 := 2; 1341#L491-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 1224#L309-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 1225#L331-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 1254#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret14#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret14#1;havoc start_simulation_#t~ret14#1; 1404#L671 assume !(0 == start_simulation_~tmp~3#1); 1208#L671-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret13#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 1429#L309-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 1306#L331-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 1274#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret13#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret13#1;havoc stop_simulation_#t~ret13#1; 1275#L626 assume !(0 != stop_simulation_~tmp~2#1);stop_simulation_~__retres2~0#1 := 1; 1412#L633 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 1413#stop_simulation_returnLabel#1 start_simulation_#t~ret15#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret13#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret15#1;havoc start_simulation_#t~ret15#1; 1414#L684 assume !(0 != start_simulation_~tmp___0~1#1); 1201#L652-2 [2023-11-12 02:32:14,706 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-12 02:32:14,706 INFO L85 PathProgramCache]: Analyzing trace with hash -1769790220, now seen corresponding path program 1 times [2023-11-12 02:32:14,706 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-12 02:32:14,707 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1950997482] [2023-11-12 02:32:14,707 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-12 02:32:14,707 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-12 02:32:14,719 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-12 02:32:14,766 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-12 02:32:14,766 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-12 02:32:14,767 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1950997482] [2023-11-12 02:32:14,767 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1950997482] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-12 02:32:14,767 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-12 02:32:14,767 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-12 02:32:14,768 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1850335690] [2023-11-12 02:32:14,768 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-12 02:32:14,768 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-12 02:32:14,769 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-12 02:32:14,769 INFO L85 PathProgramCache]: Analyzing trace with hash -1463002402, now seen corresponding path program 1 times [2023-11-12 02:32:14,769 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-12 02:32:14,770 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [18670971] [2023-11-12 02:32:14,770 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-12 02:32:14,770 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-12 02:32:14,785 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-12 02:32:14,829 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-12 02:32:14,829 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-12 02:32:14,829 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [18670971] [2023-11-12 02:32:14,830 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [18670971] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-12 02:32:14,830 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-12 02:32:14,830 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-12 02:32:14,830 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1801511441] [2023-11-12 02:32:14,831 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-12 02:32:14,831 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-12 02:32:14,831 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-12 02:32:14,832 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-12 02:32:14,832 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-12 02:32:14,832 INFO L87 Difference]: Start difference. First operand 288 states and 427 transitions. cyclomatic complexity: 140 Second operand has 3 states, 3 states have (on average 16.333333333333332) internal successors, (49), 3 states have internal predecessors, (49), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-12 02:32:14,845 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-12 02:32:14,846 INFO L93 Difference]: Finished difference Result 288 states and 426 transitions. [2023-11-12 02:32:14,846 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 288 states and 426 transitions. [2023-11-12 02:32:14,849 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 235 [2023-11-12 02:32:14,853 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 288 states to 288 states and 426 transitions. [2023-11-12 02:32:14,853 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 288 [2023-11-12 02:32:14,854 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 288 [2023-11-12 02:32:14,854 INFO L73 IsDeterministic]: Start isDeterministic. Operand 288 states and 426 transitions. [2023-11-12 02:32:14,855 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-12 02:32:14,856 INFO L218 hiAutomatonCegarLoop]: Abstraction has 288 states and 426 transitions. [2023-11-12 02:32:14,857 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 288 states and 426 transitions. [2023-11-12 02:32:14,869 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 288 to 288. [2023-11-12 02:32:14,870 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 288 states, 288 states have (on average 1.4791666666666667) internal successors, (426), 287 states have internal predecessors, (426), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-12 02:32:14,871 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 288 states to 288 states and 426 transitions. [2023-11-12 02:32:14,872 INFO L240 hiAutomatonCegarLoop]: Abstraction has 288 states and 426 transitions. [2023-11-12 02:32:14,872 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-12 02:32:14,873 INFO L428 stractBuchiCegarLoop]: Abstraction has 288 states and 426 transitions. [2023-11-12 02:32:14,873 INFO L335 stractBuchiCegarLoop]: ======== Iteration 4 ============ [2023-11-12 02:32:14,874 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 288 states and 426 transitions. [2023-11-12 02:32:14,877 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 235 [2023-11-12 02:32:14,877 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-12 02:32:14,877 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-12 02:32:14,879 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-12 02:32:14,879 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-12 02:32:14,879 INFO L748 eck$LassoCheckResult]: Stem: 2023#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2; 2024#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~5#1;havoc main_~__retres1~5#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1; 2033#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret14#1, start_simulation_#t~ret15#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 2032#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 2007#L281 assume 1 == ~m_i~0;~m_st~0 := 0; 2008#L281-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 1834#L286-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 1835#L291-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 2040#L296-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 1799#L418 assume !(0 == ~M_E~0); 1800#L418-2 assume !(0 == ~T1_E~0); 2006#L423-1 assume 0 == ~T2_E~0;~T2_E~0 := 1; 2043#L428-1 assume !(0 == ~T3_E~0); 2041#L433-1 assume !(0 == ~E_1~0); 2035#L438-1 assume !(0 == ~E_2~0); 1972#L443-1 assume !(0 == ~E_3~0); 1966#L448-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1933#L197 assume !(1 == ~m_pc~0); 1930#L197-2 is_master_triggered_~__retres1~0#1 := 0; 1929#L208 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1999#is_master_triggered_returnLabel#1 activate_threads_#t~ret9#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 2000#L510 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 1773#L510-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1774#L216 assume 1 == ~t1_pc~0; 1822#L217 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 1823#L227 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1859#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret10#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 1778#L518 assume !(0 != activate_threads_~tmp___0~0#1); 1779#L518-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1981#L235 assume !(1 == ~t2_pc~0); 2039#L235-2 is_transmit2_triggered_~__retres1~2#1 := 0; 1918#L246 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1919#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret11#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 2048#L526 assume !(0 != activate_threads_~tmp___1~0#1); 2049#L526-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1904#L254 assume 1 == ~t3_pc~0; 1804#L255 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 1805#L265 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1788#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 1789#L534 assume !(0 != activate_threads_~tmp___2~0#1); 1912#L534-2 havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1765#L461 assume !(1 == ~M_E~0); 1766#L461-2 assume !(1 == ~T1_E~0); 1836#L466-1 assume !(1 == ~T2_E~0); 2046#L471-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 1862#L476-1 assume !(1 == ~E_1~0); 1863#L481-1 assume !(1 == ~E_2~0); 1994#L486-1 assume !(1 == ~E_3~0); 1881#L491-1 assume { :end_inline_reset_delta_events } true; 1784#L652-2 [2023-11-12 02:32:14,880 INFO L750 eck$LassoCheckResult]: Loop: 1784#L652-2 assume !false; 1785#L653 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 1852#L393-1 assume !false; 1855#L342 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 1856#L309 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 1830#L331 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 1786#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 1787#L346 assume !(0 != eval_~tmp~0#1); 1882#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 1953#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 1984#L418-3 assume 0 == ~M_E~0;~M_E~0 := 1; 1977#L418-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 1978#L423-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 1973#L428-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 1931#L433-3 assume !(0 == ~E_1~0); 1932#L438-3 assume 0 == ~E_2~0;~E_2~0 := 1; 2017#L443-3 assume 0 == ~E_3~0;~E_3~0 := 1; 1767#L448-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1768#L197-12 assume 1 == ~m_pc~0; 2025#L198-4 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 1897#L208-4 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1898#is_master_triggered_returnLabel#5 activate_threads_#t~ret9#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 1780#L510-12 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 1781#L510-14 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1894#L216-12 assume !(1 == ~t1_pc~0); 1895#L216-14 is_transmit1_triggered_~__retres1~1#1 := 0; 1947#L227-4 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1948#is_transmit1_triggered_returnLabel#5 activate_threads_#t~ret10#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 1907#L518-12 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 1832#L518-14 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1833#L235-12 assume 1 == ~t2_pc~0; 2034#L236-4 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 1916#L246-4 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1908#is_transmit2_triggered_returnLabel#5 activate_threads_#t~ret11#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 1909#L526-12 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 1967#L526-14 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1968#L254-12 assume 1 == ~t3_pc~0; 1813#L255-4 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 1814#L265-4 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1860#is_transmit3_triggered_returnLabel#5 activate_threads_#t~ret12#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 1861#L534-12 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 1952#L534-14 havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1899#L461-3 assume 1 == ~M_E~0;~M_E~0 := 2; 1900#L461-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 1985#L466-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 1986#L471-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 1891#L476-3 assume 1 == ~E_1~0;~E_1~0 := 2; 1892#L481-3 assume !(1 == ~E_2~0); 1923#L486-3 assume 1 == ~E_3~0;~E_3~0 := 2; 1924#L491-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 1810#L309-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 1811#L331-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 1837#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret14#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret14#1;havoc start_simulation_#t~ret14#1; 1987#L671 assume !(0 == start_simulation_~tmp~3#1); 1793#L671-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret13#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 2012#L309-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 1889#L331-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 1857#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret13#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret13#1;havoc stop_simulation_#t~ret13#1; 1858#L626 assume !(0 != stop_simulation_~tmp~2#1);stop_simulation_~__retres2~0#1 := 1; 1995#L633 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 1996#stop_simulation_returnLabel#1 start_simulation_#t~ret15#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret13#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret15#1;havoc start_simulation_#t~ret15#1; 1997#L684 assume !(0 != start_simulation_~tmp___0~1#1); 1784#L652-2 [2023-11-12 02:32:14,880 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-12 02:32:14,880 INFO L85 PathProgramCache]: Analyzing trace with hash -2017936714, now seen corresponding path program 1 times [2023-11-12 02:32:14,881 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-12 02:32:14,881 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2012283826] [2023-11-12 02:32:14,881 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-12 02:32:14,882 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-12 02:32:14,898 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-12 02:32:14,958 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-12 02:32:14,958 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-12 02:32:14,959 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2012283826] [2023-11-12 02:32:14,959 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2012283826] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-12 02:32:14,959 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-12 02:32:14,959 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2023-11-12 02:32:14,960 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [7514631] [2023-11-12 02:32:14,960 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-12 02:32:14,960 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-12 02:32:14,961 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-12 02:32:14,961 INFO L85 PathProgramCache]: Analyzing trace with hash 1274205792, now seen corresponding path program 2 times [2023-11-12 02:32:14,961 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-12 02:32:14,962 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [936338912] [2023-11-12 02:32:14,962 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-12 02:32:14,962 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-12 02:32:14,976 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-12 02:32:15,017 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-12 02:32:15,017 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-12 02:32:15,017 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [936338912] [2023-11-12 02:32:15,018 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [936338912] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-12 02:32:15,018 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-12 02:32:15,018 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-12 02:32:15,018 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1763967537] [2023-11-12 02:32:15,018 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-12 02:32:15,019 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-12 02:32:15,019 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-12 02:32:15,020 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-12 02:32:15,020 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-12 02:32:15,020 INFO L87 Difference]: Start difference. First operand 288 states and 426 transitions. cyclomatic complexity: 139 Second operand has 3 states, 3 states have (on average 16.333333333333332) internal successors, (49), 2 states have internal predecessors, (49), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-12 02:32:15,041 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-12 02:32:15,042 INFO L93 Difference]: Finished difference Result 288 states and 421 transitions. [2023-11-12 02:32:15,042 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 288 states and 421 transitions. [2023-11-12 02:32:15,045 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 235 [2023-11-12 02:32:15,048 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 288 states to 288 states and 421 transitions. [2023-11-12 02:32:15,049 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 288 [2023-11-12 02:32:15,049 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 288 [2023-11-12 02:32:15,049 INFO L73 IsDeterministic]: Start isDeterministic. Operand 288 states and 421 transitions. [2023-11-12 02:32:15,050 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-12 02:32:15,051 INFO L218 hiAutomatonCegarLoop]: Abstraction has 288 states and 421 transitions. [2023-11-12 02:32:15,051 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 288 states and 421 transitions. [2023-11-12 02:32:15,058 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 288 to 288. [2023-11-12 02:32:15,059 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 288 states, 288 states have (on average 1.4618055555555556) internal successors, (421), 287 states have internal predecessors, (421), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-12 02:32:15,060 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 288 states to 288 states and 421 transitions. [2023-11-12 02:32:15,060 INFO L240 hiAutomatonCegarLoop]: Abstraction has 288 states and 421 transitions. [2023-11-12 02:32:15,061 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-12 02:32:15,062 INFO L428 stractBuchiCegarLoop]: Abstraction has 288 states and 421 transitions. [2023-11-12 02:32:15,062 INFO L335 stractBuchiCegarLoop]: ======== Iteration 5 ============ [2023-11-12 02:32:15,062 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 288 states and 421 transitions. [2023-11-12 02:32:15,065 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 235 [2023-11-12 02:32:15,065 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-12 02:32:15,065 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-12 02:32:15,067 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-12 02:32:15,067 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-12 02:32:15,067 INFO L748 eck$LassoCheckResult]: Stem: 2606#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2; 2607#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~5#1;havoc main_~__retres1~5#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1; 2616#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret14#1, start_simulation_#t~ret15#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 2615#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 2590#L281 assume 1 == ~m_i~0;~m_st~0 := 0; 2591#L281-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 2417#L286-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 2418#L291-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 2623#L296-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 2377#L418 assume !(0 == ~M_E~0); 2378#L418-2 assume !(0 == ~T1_E~0); 2589#L423-1 assume !(0 == ~T2_E~0); 2626#L428-1 assume !(0 == ~T3_E~0); 2624#L433-1 assume !(0 == ~E_1~0); 2618#L438-1 assume !(0 == ~E_2~0); 2555#L443-1 assume !(0 == ~E_3~0); 2549#L448-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 2516#L197 assume !(1 == ~m_pc~0); 2513#L197-2 is_master_triggered_~__retres1~0#1 := 0; 2512#L208 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 2582#is_master_triggered_returnLabel#1 activate_threads_#t~ret9#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 2583#L510 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 2356#L510-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 2357#L216 assume 1 == ~t1_pc~0; 2405#L217 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 2406#L227 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 2442#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret10#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 2358#L518 assume !(0 != activate_threads_~tmp___0~0#1); 2359#L518-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 2562#L235 assume !(1 == ~t2_pc~0); 2620#L235-2 is_transmit2_triggered_~__retres1~2#1 := 0; 2500#L246 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 2501#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret11#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 2631#L526 assume !(0 != activate_threads_~tmp___1~0#1); 2632#L526-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 2484#L254 assume 1 == ~t3_pc~0; 2387#L255 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 2388#L265 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 2369#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 2370#L534 assume !(0 != activate_threads_~tmp___2~0#1); 2495#L534-2 havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 2348#L461 assume !(1 == ~M_E~0); 2349#L461-2 assume !(1 == ~T1_E~0); 2419#L466-1 assume !(1 == ~T2_E~0); 2629#L471-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 2443#L476-1 assume !(1 == ~E_1~0); 2444#L481-1 assume !(1 == ~E_2~0); 2577#L486-1 assume !(1 == ~E_3~0); 2460#L491-1 assume { :end_inline_reset_delta_events } true; 2365#L652-2 [2023-11-12 02:32:15,068 INFO L750 eck$LassoCheckResult]: Loop: 2365#L652-2 assume !false; 2366#L653 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 2437#L393-1 assume !false; 2434#L342 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 2435#L309 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 2413#L331 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 2371#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 2372#L346 assume !(0 != eval_~tmp~0#1); 2465#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 2536#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 2567#L418-3 assume 0 == ~M_E~0;~M_E~0 := 1; 2560#L418-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 2561#L423-3 assume !(0 == ~T2_E~0); 2556#L428-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 2514#L433-3 assume !(0 == ~E_1~0); 2515#L438-3 assume 0 == ~E_2~0;~E_2~0 := 1; 2600#L443-3 assume 0 == ~E_3~0;~E_3~0 := 1; 2350#L448-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 2351#L197-12 assume 1 == ~m_pc~0; 2608#L198-4 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 2480#L208-4 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 2481#is_master_triggered_returnLabel#5 activate_threads_#t~ret9#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 2363#L510-12 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 2364#L510-14 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 2477#L216-12 assume !(1 == ~t1_pc~0); 2478#L216-14 is_transmit1_triggered_~__retres1~1#1 := 0; 2530#L227-4 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 2531#is_transmit1_triggered_returnLabel#5 activate_threads_#t~ret10#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 2490#L518-12 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 2415#L518-14 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 2416#L235-12 assume !(1 == ~t2_pc~0); 2498#L235-14 is_transmit2_triggered_~__retres1~2#1 := 0; 2499#L246-4 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 2491#is_transmit2_triggered_returnLabel#5 activate_threads_#t~ret11#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 2492#L526-12 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 2550#L526-14 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 2551#L254-12 assume 1 == ~t3_pc~0; 2396#L255-4 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 2397#L265-4 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 2445#is_transmit3_triggered_returnLabel#5 activate_threads_#t~ret12#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 2446#L534-12 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 2535#L534-14 havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 2482#L461-3 assume 1 == ~M_E~0;~M_E~0 := 2; 2483#L461-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 2568#L466-3 assume !(1 == ~T2_E~0); 2569#L471-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 2474#L476-3 assume 1 == ~E_1~0;~E_1~0 := 2; 2475#L481-3 assume !(1 == ~E_2~0); 2506#L486-3 assume 1 == ~E_3~0;~E_3~0 := 2; 2507#L491-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 2393#L309-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 2394#L331-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 2420#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret14#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret14#1;havoc start_simulation_#t~ret14#1; 2570#L671 assume !(0 == start_simulation_~tmp~3#1); 2376#L671-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret13#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 2595#L309-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 2472#L331-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 2440#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret13#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret13#1;havoc stop_simulation_#t~ret13#1; 2441#L626 assume !(0 != stop_simulation_~tmp~2#1);stop_simulation_~__retres2~0#1 := 1; 2578#L633 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 2579#stop_simulation_returnLabel#1 start_simulation_#t~ret15#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret13#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret15#1;havoc start_simulation_#t~ret15#1; 2580#L684 assume !(0 != start_simulation_~tmp___0~1#1); 2365#L652-2 [2023-11-12 02:32:15,068 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-12 02:32:15,069 INFO L85 PathProgramCache]: Analyzing trace with hash 1247671284, now seen corresponding path program 1 times [2023-11-12 02:32:15,069 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-12 02:32:15,069 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1292977718] [2023-11-12 02:32:15,069 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-12 02:32:15,070 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-12 02:32:15,080 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-12 02:32:15,139 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-12 02:32:15,139 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-12 02:32:15,140 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1292977718] [2023-11-12 02:32:15,140 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1292977718] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-12 02:32:15,140 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-12 02:32:15,140 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2023-11-12 02:32:15,140 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [55806770] [2023-11-12 02:32:15,141 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-12 02:32:15,141 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-12 02:32:15,141 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-12 02:32:15,142 INFO L85 PathProgramCache]: Analyzing trace with hash -282044549, now seen corresponding path program 1 times [2023-11-12 02:32:15,142 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-12 02:32:15,142 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [534125689] [2023-11-12 02:32:15,142 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-12 02:32:15,143 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-12 02:32:15,153 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-12 02:32:15,188 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-12 02:32:15,189 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-12 02:32:15,189 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [534125689] [2023-11-12 02:32:15,189 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [534125689] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-12 02:32:15,190 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-12 02:32:15,190 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-12 02:32:15,190 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1779153787] [2023-11-12 02:32:15,190 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-12 02:32:15,191 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-12 02:32:15,191 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-12 02:32:15,192 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2023-11-12 02:32:15,192 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2023-11-12 02:32:15,192 INFO L87 Difference]: Start difference. First operand 288 states and 421 transitions. cyclomatic complexity: 134 Second operand has 5 states, 5 states have (on average 9.8) internal successors, (49), 5 states have internal predecessors, (49), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-12 02:32:15,390 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-12 02:32:15,390 INFO L93 Difference]: Finished difference Result 673 states and 968 transitions. [2023-11-12 02:32:15,391 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 673 states and 968 transitions. [2023-11-12 02:32:15,397 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 565 [2023-11-12 02:32:15,404 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 673 states to 673 states and 968 transitions. [2023-11-12 02:32:15,404 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 673 [2023-11-12 02:32:15,405 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 673 [2023-11-12 02:32:15,405 INFO L73 IsDeterministic]: Start isDeterministic. Operand 673 states and 968 transitions. [2023-11-12 02:32:15,406 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-12 02:32:15,407 INFO L218 hiAutomatonCegarLoop]: Abstraction has 673 states and 968 transitions. [2023-11-12 02:32:15,408 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 673 states and 968 transitions. [2023-11-12 02:32:15,421 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 673 to 306. [2023-11-12 02:32:15,422 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 306 states, 306 states have (on average 1.434640522875817) internal successors, (439), 305 states have internal predecessors, (439), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-12 02:32:15,424 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 306 states to 306 states and 439 transitions. [2023-11-12 02:32:15,424 INFO L240 hiAutomatonCegarLoop]: Abstraction has 306 states and 439 transitions. [2023-11-12 02:32:15,425 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2023-11-12 02:32:15,425 INFO L428 stractBuchiCegarLoop]: Abstraction has 306 states and 439 transitions. [2023-11-12 02:32:15,426 INFO L335 stractBuchiCegarLoop]: ======== Iteration 6 ============ [2023-11-12 02:32:15,426 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 306 states and 439 transitions. [2023-11-12 02:32:15,428 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 250 [2023-11-12 02:32:15,428 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-12 02:32:15,428 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-12 02:32:15,430 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-12 02:32:15,430 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-12 02:32:15,430 INFO L748 eck$LassoCheckResult]: Stem: 3588#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2; 3589#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~5#1;havoc main_~__retres1~5#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1; 3599#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret14#1, start_simulation_#t~ret15#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 3597#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 3571#L281 assume 1 == ~m_i~0;~m_st~0 := 0; 3572#L281-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 3391#L286-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 3392#L291-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 3607#L296-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 3354#L418 assume !(0 == ~M_E~0); 3355#L418-2 assume !(0 == ~T1_E~0); 3570#L423-1 assume !(0 == ~T2_E~0); 3610#L428-1 assume !(0 == ~T3_E~0); 3608#L433-1 assume !(0 == ~E_1~0); 3601#L438-1 assume !(0 == ~E_2~0); 3533#L443-1 assume !(0 == ~E_3~0); 3527#L448-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 3490#L197 assume !(1 == ~m_pc~0); 3487#L197-2 is_master_triggered_~__retres1~0#1 := 0; 3624#L208 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 3625#is_master_triggered_returnLabel#1 activate_threads_#t~ret9#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 3616#L510 assume !(0 != activate_threads_~tmp~1#1); 3330#L510-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 3331#L216 assume 1 == ~t1_pc~0; 3379#L217 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 3380#L227 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 3416#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret10#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 3332#L518 assume !(0 != activate_threads_~tmp___0~0#1); 3333#L518-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 3543#L235 assume !(1 == ~t2_pc~0); 3603#L235-2 is_transmit2_triggered_~__retres1~2#1 := 0; 3475#L246 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 3476#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret11#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 3618#L526 assume !(0 != activate_threads_~tmp___1~0#1); 3619#L526-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 3458#L254 assume 1 == ~t3_pc~0; 3361#L255 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 3362#L265 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 3343#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 3344#L534 assume !(0 != activate_threads_~tmp___2~0#1); 3469#L534-2 havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 3322#L461 assume !(1 == ~M_E~0); 3323#L461-2 assume !(1 == ~T1_E~0); 3393#L466-1 assume !(1 == ~T2_E~0); 3614#L471-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 3419#L476-1 assume !(1 == ~E_1~0); 3420#L481-1 assume !(1 == ~E_2~0); 3558#L486-1 assume !(1 == ~E_3~0); 3436#L491-1 assume { :end_inline_reset_delta_events } true; 3341#L652-2 [2023-11-12 02:32:15,431 INFO L750 eck$LassoCheckResult]: Loop: 3341#L652-2 assume !false; 3342#L653 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 3411#L393-1 assume !false; 3408#L342 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 3409#L309 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 3387#L331 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 3345#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 3346#L346 assume !(0 != eval_~tmp~0#1); 3439#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 3512#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 3547#L418-3 assume 0 == ~M_E~0;~M_E~0 := 1; 3540#L418-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 3541#L423-3 assume !(0 == ~T2_E~0); 3536#L428-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 3488#L433-3 assume !(0 == ~E_1~0); 3489#L438-3 assume 0 == ~E_2~0;~E_2~0 := 1; 3583#L443-3 assume 0 == ~E_3~0;~E_3~0 := 1; 3324#L448-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 3325#L197-12 assume 1 == ~m_pc~0; 3590#L198-4 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 3598#L208-4 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 3538#is_master_triggered_returnLabel#5 activate_threads_#t~ret9#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 3539#L510-12 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 3338#L510-14 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 3451#L216-12 assume !(1 == ~t1_pc~0); 3452#L216-14 is_transmit1_triggered_~__retres1~1#1 := 0; 3506#L227-4 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 3507#is_transmit1_triggered_returnLabel#5 activate_threads_#t~ret10#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 3464#L518-12 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 3389#L518-14 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 3390#L235-12 assume 1 == ~t2_pc~0; 3600#L236-4 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 3473#L246-4 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 3465#is_transmit2_triggered_returnLabel#5 activate_threads_#t~ret11#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 3466#L526-12 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 3528#L526-14 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 3529#L254-12 assume 1 == ~t3_pc~0; 3370#L255-4 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 3371#L265-4 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 3417#is_transmit3_triggered_returnLabel#5 activate_threads_#t~ret12#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 3418#L534-12 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 3511#L534-14 havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 3456#L461-3 assume 1 == ~M_E~0;~M_E~0 := 2; 3457#L461-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 3548#L466-3 assume !(1 == ~T2_E~0); 3549#L471-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 3448#L476-3 assume 1 == ~E_1~0;~E_1~0 := 2; 3449#L481-3 assume !(1 == ~E_2~0); 3480#L486-3 assume 1 == ~E_3~0;~E_3~0 := 2; 3481#L491-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 3364#L309-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 3365#L331-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 3394#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret14#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret14#1;havoc start_simulation_#t~ret14#1; 3550#L671 assume !(0 == start_simulation_~tmp~3#1); 3348#L671-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret13#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 3576#L309-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 3446#L331-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 3414#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret13#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret13#1;havoc stop_simulation_#t~ret13#1; 3415#L626 assume !(0 != stop_simulation_~tmp~2#1);stop_simulation_~__retres2~0#1 := 1; 3559#L633 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 3560#stop_simulation_returnLabel#1 start_simulation_#t~ret15#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret13#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret15#1;havoc start_simulation_#t~ret15#1; 3561#L684 assume !(0 != start_simulation_~tmp___0~1#1); 3341#L652-2 [2023-11-12 02:32:15,431 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-12 02:32:15,431 INFO L85 PathProgramCache]: Analyzing trace with hash 738198194, now seen corresponding path program 1 times [2023-11-12 02:32:15,431 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-12 02:32:15,432 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1057514137] [2023-11-12 02:32:15,432 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-12 02:32:15,432 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-12 02:32:15,441 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-12 02:32:15,490 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-12 02:32:15,490 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-12 02:32:15,490 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1057514137] [2023-11-12 02:32:15,491 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1057514137] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-12 02:32:15,491 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-12 02:32:15,491 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-12 02:32:15,491 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [268795105] [2023-11-12 02:32:15,491 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-12 02:32:15,492 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-12 02:32:15,492 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-12 02:32:15,492 INFO L85 PathProgramCache]: Analyzing trace with hash -1201019172, now seen corresponding path program 1 times [2023-11-12 02:32:15,493 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-12 02:32:15,493 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1994875638] [2023-11-12 02:32:15,493 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-12 02:32:15,493 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-12 02:32:15,503 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-12 02:32:15,534 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-12 02:32:15,534 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-12 02:32:15,534 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1994875638] [2023-11-12 02:32:15,535 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1994875638] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-12 02:32:15,535 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-12 02:32:15,535 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-12 02:32:15,535 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [817127822] [2023-11-12 02:32:15,535 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-12 02:32:15,536 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-12 02:32:15,536 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-12 02:32:15,536 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2023-11-12 02:32:15,537 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2023-11-12 02:32:15,537 INFO L87 Difference]: Start difference. First operand 306 states and 439 transitions. cyclomatic complexity: 134 Second operand has 4 states, 4 states have (on average 12.25) internal successors, (49), 3 states have internal predecessors, (49), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-12 02:32:15,683 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-12 02:32:15,683 INFO L93 Difference]: Finished difference Result 728 states and 1024 transitions. [2023-11-12 02:32:15,684 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 728 states and 1024 transitions. [2023-11-12 02:32:15,690 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 640 [2023-11-12 02:32:15,697 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 728 states to 728 states and 1024 transitions. [2023-11-12 02:32:15,697 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 728 [2023-11-12 02:32:15,698 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 728 [2023-11-12 02:32:15,699 INFO L73 IsDeterministic]: Start isDeterministic. Operand 728 states and 1024 transitions. [2023-11-12 02:32:15,701 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-12 02:32:15,701 INFO L218 hiAutomatonCegarLoop]: Abstraction has 728 states and 1024 transitions. [2023-11-12 02:32:15,702 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 728 states and 1024 transitions. [2023-11-12 02:32:15,717 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 728 to 674. [2023-11-12 02:32:15,719 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 674 states, 674 states have (on average 1.416913946587537) internal successors, (955), 673 states have internal predecessors, (955), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-12 02:32:15,722 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 674 states to 674 states and 955 transitions. [2023-11-12 02:32:15,722 INFO L240 hiAutomatonCegarLoop]: Abstraction has 674 states and 955 transitions. [2023-11-12 02:32:15,722 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2023-11-12 02:32:15,724 INFO L428 stractBuchiCegarLoop]: Abstraction has 674 states and 955 transitions. [2023-11-12 02:32:15,725 INFO L335 stractBuchiCegarLoop]: ======== Iteration 7 ============ [2023-11-12 02:32:15,725 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 674 states and 955 transitions. [2023-11-12 02:32:15,729 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 618 [2023-11-12 02:32:15,730 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-12 02:32:15,730 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-12 02:32:15,734 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-12 02:32:15,734 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-12 02:32:15,735 INFO L748 eck$LassoCheckResult]: Stem: 4647#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2; 4648#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~5#1;havoc main_~__retres1~5#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1; 4662#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret14#1, start_simulation_#t~ret15#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 4656#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 4630#L281 assume 1 == ~m_i~0;~m_st~0 := 0; 4631#L281-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 4435#L286-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 4436#L291-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 4672#L296-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 4395#L418 assume !(0 == ~M_E~0); 4396#L418-2 assume !(0 == ~T1_E~0); 4629#L423-1 assume !(0 == ~T2_E~0); 4677#L428-1 assume !(0 == ~T3_E~0); 4675#L433-1 assume !(0 == ~E_1~0); 4665#L438-1 assume !(0 == ~E_2~0); 4581#L443-1 assume !(0 == ~E_3~0); 4574#L448-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 4531#L197 assume !(1 == ~m_pc~0); 4532#L197-2 is_master_triggered_~__retres1~0#1 := 0; 4693#L208 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 4620#is_master_triggered_returnLabel#1 activate_threads_#t~ret9#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 4621#L510 assume !(0 != activate_threads_~tmp~1#1); 4374#L510-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 4375#L216 assume !(1 == ~t1_pc~0); 4431#L216-2 is_transmit1_triggered_~__retres1~1#1 := 0; 4432#L227 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 4460#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret10#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 4376#L518 assume !(0 != activate_threads_~tmp___0~0#1); 4377#L518-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 4590#L235 assume !(1 == ~t2_pc~0); 4669#L235-2 is_transmit2_triggered_~__retres1~2#1 := 0; 4519#L246 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 4520#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret11#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 4685#L526 assume !(0 != activate_threads_~tmp___1~0#1); 4686#L526-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 4505#L254 assume 1 == ~t3_pc~0; 4406#L255 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 4407#L265 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 4387#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 4388#L534 assume !(0 != activate_threads_~tmp___2~0#1); 4513#L534-2 havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 4366#L461 assume !(1 == ~M_E~0); 4367#L461-2 assume !(1 == ~T1_E~0); 4437#L466-1 assume !(1 == ~T2_E~0); 4681#L471-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 4463#L476-1 assume !(1 == ~E_1~0); 4464#L481-1 assume !(1 == ~E_2~0); 4609#L486-1 assume !(1 == ~E_3~0); 4478#L491-1 assume { :end_inline_reset_delta_events } true; 4385#L652-2 [2023-11-12 02:32:15,735 INFO L750 eck$LassoCheckResult]: Loop: 4385#L652-2 assume !false; 4386#L653 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 4457#L393-1 assume !false; 4614#L342 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 4925#L309 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 4625#L331 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 4389#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 4390#L346 assume !(0 != eval_~tmp~0#1); 4483#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 4555#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 4701#L418-3 assume 0 == ~M_E~0;~M_E~0 := 1; 4702#L418-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 4616#L423-3 assume !(0 == ~T2_E~0); 4617#L428-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 4529#L433-3 assume !(0 == ~E_1~0); 4530#L438-3 assume 0 == ~E_2~0;~E_2~0 := 1; 4640#L443-3 assume 0 == ~E_3~0;~E_3~0 := 1; 4368#L448-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 4369#L197-12 assume !(1 == ~m_pc~0); 4650#L197-14 is_master_triggered_~__retres1~0#1 := 0; 4499#L208-4 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 4500#is_master_triggered_returnLabel#5 activate_threads_#t~ret9#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 4381#L510-12 assume !(0 != activate_threads_~tmp~1#1); 4382#L510-14 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 4497#L216-12 assume !(1 == ~t1_pc~0); 4498#L216-14 is_transmit1_triggered_~__retres1~1#1 := 0; 4547#L227-4 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 4548#is_transmit1_triggered_returnLabel#5 activate_threads_#t~ret10#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 4506#L518-12 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 4433#L518-14 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 4434#L235-12 assume !(1 == ~t2_pc~0); 4516#L235-14 is_transmit2_triggered_~__retres1~2#1 := 0; 4517#L246-4 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 4509#is_transmit2_triggered_returnLabel#5 activate_threads_#t~ret11#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 4510#L526-12 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 4575#L526-14 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 4576#L254-12 assume !(1 == ~t3_pc~0); 4416#L254-14 is_transmit3_triggered_~__retres1~3#1 := 0; 4415#L265-4 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 4461#is_transmit3_triggered_returnLabel#5 activate_threads_#t~ret12#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 4462#L534-12 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 4554#L534-14 havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 4501#L461-3 assume 1 == ~M_E~0;~M_E~0 := 2; 4502#L461-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 4597#L466-3 assume !(1 == ~T2_E~0); 4598#L471-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 4493#L476-3 assume 1 == ~E_1~0;~E_1~0 := 2; 4494#L481-3 assume !(1 == ~E_2~0); 4524#L486-3 assume 1 == ~E_3~0;~E_3~0 := 2; 4525#L491-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 4409#L309-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 4410#L331-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 4438#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret14#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret14#1;havoc start_simulation_#t~ret14#1; 4596#L671 assume !(0 == start_simulation_~tmp~3#1); 4392#L671-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret13#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 4635#L309-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 4491#L331-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 4458#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret13#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret13#1;havoc stop_simulation_#t~ret13#1; 4459#L626 assume !(0 != stop_simulation_~tmp~2#1);stop_simulation_~__retres2~0#1 := 1; 4680#L633 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 4934#stop_simulation_returnLabel#1 start_simulation_#t~ret15#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret13#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret15#1;havoc start_simulation_#t~ret15#1; 4933#L684 assume !(0 != start_simulation_~tmp___0~1#1); 4385#L652-2 [2023-11-12 02:32:15,735 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-12 02:32:15,736 INFO L85 PathProgramCache]: Analyzing trace with hash 1376982673, now seen corresponding path program 1 times [2023-11-12 02:32:15,736 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-12 02:32:15,736 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2115641013] [2023-11-12 02:32:15,736 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-12 02:32:15,737 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-12 02:32:15,751 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-12 02:32:15,847 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-12 02:32:15,847 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-12 02:32:15,847 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2115641013] [2023-11-12 02:32:15,848 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2115641013] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-12 02:32:15,848 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-12 02:32:15,848 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-12 02:32:15,848 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1126617709] [2023-11-12 02:32:15,848 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-12 02:32:15,849 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-12 02:32:15,849 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-12 02:32:15,849 INFO L85 PathProgramCache]: Analyzing trace with hash 2004797239, now seen corresponding path program 1 times [2023-11-12 02:32:15,849 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-12 02:32:15,850 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [915743790] [2023-11-12 02:32:15,850 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-12 02:32:15,850 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-12 02:32:15,860 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-12 02:32:15,886 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-12 02:32:15,887 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-12 02:32:15,887 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [915743790] [2023-11-12 02:32:15,887 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [915743790] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-12 02:32:15,887 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-12 02:32:15,887 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-12 02:32:15,888 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1266359461] [2023-11-12 02:32:15,888 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-12 02:32:15,888 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-12 02:32:15,888 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-12 02:32:15,889 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2023-11-12 02:32:15,889 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2023-11-12 02:32:15,889 INFO L87 Difference]: Start difference. First operand 674 states and 955 transitions. cyclomatic complexity: 283 Second operand has 4 states, 4 states have (on average 12.25) internal successors, (49), 3 states have internal predecessors, (49), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-12 02:32:16,058 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-12 02:32:16,059 INFO L93 Difference]: Finished difference Result 1845 states and 2569 transitions. [2023-11-12 02:32:16,059 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1845 states and 2569 transitions. [2023-11-12 02:32:16,075 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 1703 [2023-11-12 02:32:16,091 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1845 states to 1845 states and 2569 transitions. [2023-11-12 02:32:16,091 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1845 [2023-11-12 02:32:16,093 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1845 [2023-11-12 02:32:16,093 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1845 states and 2569 transitions. [2023-11-12 02:32:16,096 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-12 02:32:16,096 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1845 states and 2569 transitions. [2023-11-12 02:32:16,099 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1845 states and 2569 transitions. [2023-11-12 02:32:16,124 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1845 to 1762. [2023-11-12 02:32:16,128 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1762 states, 1762 states have (on average 1.3995459704880817) internal successors, (2466), 1761 states have internal predecessors, (2466), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-12 02:32:16,135 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1762 states to 1762 states and 2466 transitions. [2023-11-12 02:32:16,135 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1762 states and 2466 transitions. [2023-11-12 02:32:16,135 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2023-11-12 02:32:16,136 INFO L428 stractBuchiCegarLoop]: Abstraction has 1762 states and 2466 transitions. [2023-11-12 02:32:16,136 INFO L335 stractBuchiCegarLoop]: ======== Iteration 8 ============ [2023-11-12 02:32:16,136 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1762 states and 2466 transitions. [2023-11-12 02:32:16,147 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 1697 [2023-11-12 02:32:16,147 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-12 02:32:16,147 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-12 02:32:16,148 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-12 02:32:16,148 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-12 02:32:16,149 INFO L748 eck$LassoCheckResult]: Stem: 7173#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2; 7174#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~5#1;havoc main_~__retres1~5#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1; 7188#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret14#1, start_simulation_#t~ret15#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 7183#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 7156#L281 assume 1 == ~m_i~0;~m_st~0 := 0; 7157#L281-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 6959#L286-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 6960#L291-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 7200#L296-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 6924#L418 assume !(0 == ~M_E~0); 6925#L418-2 assume !(0 == ~T1_E~0); 7155#L423-1 assume !(0 == ~T2_E~0); 7204#L428-1 assume !(0 == ~T3_E~0); 7202#L433-1 assume !(0 == ~E_1~0); 7191#L438-1 assume !(0 == ~E_2~0); 7108#L443-1 assume !(0 == ~E_3~0); 7101#L448-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 7060#L197 assume !(1 == ~m_pc~0); 7061#L197-2 is_master_triggered_~__retres1~0#1 := 0; 7232#L208 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 7146#is_master_triggered_returnLabel#1 activate_threads_#t~ret9#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 7147#L510 assume !(0 != activate_threads_~tmp~1#1); 6903#L510-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 6904#L216 assume !(1 == ~t1_pc~0); 6955#L216-2 is_transmit1_triggered_~__retres1~1#1 := 0; 6956#L227 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 6987#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret10#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 6905#L518 assume !(0 != activate_threads_~tmp___0~0#1); 6906#L518-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 7117#L235 assume !(1 == ~t2_pc~0); 7196#L235-2 is_transmit2_triggered_~__retres1~2#1 := 0; 7047#L246 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 7048#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret11#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 7216#L526 assume !(0 != activate_threads_~tmp___1~0#1); 7217#L526-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 7032#L254 assume !(1 == ~t3_pc~0); 6963#L254-2 is_transmit3_triggered_~__retres1~3#1 := 0; 6964#L265 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 6916#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 6917#L534 assume !(0 != activate_threads_~tmp___2~0#1); 7042#L534-2 havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 6895#L461 assume !(1 == ~M_E~0); 6896#L461-2 assume !(1 == ~T1_E~0); 6961#L466-1 assume !(1 == ~T2_E~0); 7208#L471-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 6988#L476-1 assume !(1 == ~E_1~0); 6989#L481-1 assume !(1 == ~E_2~0); 7136#L486-1 assume !(1 == ~E_3~0); 7004#L491-1 assume { :end_inline_reset_delta_events } true; 7005#L652-2 [2023-11-12 02:32:16,149 INFO L750 eck$LassoCheckResult]: Loop: 7005#L652-2 assume !false; 8574#L653 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 8542#L393-1 assume !false; 6978#L342 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 6979#L309 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 7150#L331 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 7151#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 8378#L346 assume !(0 != eval_~tmp~0#1); 7082#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 7083#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 7121#L418-3 assume 0 == ~M_E~0;~M_E~0 := 1; 7115#L418-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 7116#L423-3 assume !(0 == ~T2_E~0); 7110#L428-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 7058#L433-3 assume !(0 == ~E_1~0); 7059#L438-3 assume 0 == ~E_2~0;~E_2~0 := 1; 7167#L443-3 assume 0 == ~E_3~0;~E_3~0 := 1; 6897#L448-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 6898#L197-12 assume !(1 == ~m_pc~0); 7176#L197-14 is_master_triggered_~__retres1~0#1 := 0; 7028#L208-4 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 7029#is_master_triggered_returnLabel#5 activate_threads_#t~ret9#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 6910#L510-12 assume !(0 != activate_threads_~tmp~1#1); 6911#L510-14 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 7026#L216-12 assume !(1 == ~t1_pc~0); 7027#L216-14 is_transmit1_triggered_~__retres1~1#1 := 0; 7075#L227-4 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 7076#is_transmit1_triggered_returnLabel#5 activate_threads_#t~ret10#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 7035#L518-12 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 6957#L518-14 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 6958#L235-12 assume !(1 == ~t2_pc~0); 7045#L235-14 is_transmit2_triggered_~__retres1~2#1 := 0; 7046#L246-4 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 7038#is_transmit2_triggered_returnLabel#5 activate_threads_#t~ret11#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 7039#L526-12 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 7102#L526-14 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 7103#L254-12 assume !(1 == ~t3_pc~0); 7213#L254-14 is_transmit3_triggered_~__retres1~3#1 := 0; 7107#L265-4 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 6990#is_transmit3_triggered_returnLabel#5 activate_threads_#t~ret12#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 6991#L534-12 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 7081#L534-14 havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 7030#L461-3 assume 1 == ~M_E~0;~M_E~0 := 2; 7031#L461-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 7122#L466-3 assume !(1 == ~T2_E~0); 7123#L471-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 7020#L476-3 assume 1 == ~E_1~0;~E_1~0 := 2; 7021#L481-3 assume !(1 == ~E_2~0); 7054#L486-3 assume 1 == ~E_3~0;~E_3~0 := 2; 7055#L491-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 6936#L309-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 6937#L331-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 6962#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret14#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret14#1;havoc start_simulation_#t~ret14#1; 7218#L671 assume !(0 == start_simulation_~tmp~3#1); 7161#L671-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret13#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 7162#L309-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 8580#L331-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 8579#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret13#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret13#1;havoc stop_simulation_#t~ret13#1; 8578#L626 assume !(0 != stop_simulation_~tmp~2#1);stop_simulation_~__retres2~0#1 := 1; 8577#L633 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 8576#stop_simulation_returnLabel#1 start_simulation_#t~ret15#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret13#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret15#1;havoc start_simulation_#t~ret15#1; 8575#L684 assume !(0 != start_simulation_~tmp___0~1#1); 7005#L652-2 [2023-11-12 02:32:16,150 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-12 02:32:16,150 INFO L85 PathProgramCache]: Analyzing trace with hash 372621552, now seen corresponding path program 1 times [2023-11-12 02:32:16,150 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-12 02:32:16,151 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2050238658] [2023-11-12 02:32:16,151 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-12 02:32:16,151 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-12 02:32:16,159 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-12 02:32:16,200 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-12 02:32:16,200 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-12 02:32:16,201 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2050238658] [2023-11-12 02:32:16,201 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2050238658] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-12 02:32:16,201 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-12 02:32:16,201 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-12 02:32:16,202 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [904015115] [2023-11-12 02:32:16,202 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-12 02:32:16,202 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-12 02:32:16,203 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-12 02:32:16,203 INFO L85 PathProgramCache]: Analyzing trace with hash 2004797239, now seen corresponding path program 2 times [2023-11-12 02:32:16,203 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-12 02:32:16,203 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1815059608] [2023-11-12 02:32:16,204 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-12 02:32:16,204 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-12 02:32:16,212 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-12 02:32:16,262 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-12 02:32:16,263 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-12 02:32:16,263 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1815059608] [2023-11-12 02:32:16,264 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1815059608] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-12 02:32:16,267 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-12 02:32:16,267 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-12 02:32:16,268 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1434574965] [2023-11-12 02:32:16,268 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-12 02:32:16,269 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-12 02:32:16,269 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-12 02:32:16,270 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2023-11-12 02:32:16,270 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2023-11-12 02:32:16,271 INFO L87 Difference]: Start difference. First operand 1762 states and 2466 transitions. cyclomatic complexity: 708 Second operand has 4 states, 4 states have (on average 12.25) internal successors, (49), 3 states have internal predecessors, (49), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-12 02:32:16,357 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-12 02:32:16,357 INFO L93 Difference]: Finished difference Result 3830 states and 5320 transitions. [2023-11-12 02:32:16,358 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 3830 states and 5320 transitions. [2023-11-12 02:32:16,391 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 3713 [2023-11-12 02:32:16,424 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 3830 states to 3830 states and 5320 transitions. [2023-11-12 02:32:16,424 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 3830 [2023-11-12 02:32:16,429 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 3830 [2023-11-12 02:32:16,429 INFO L73 IsDeterministic]: Start isDeterministic. Operand 3830 states and 5320 transitions. [2023-11-12 02:32:16,435 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-12 02:32:16,435 INFO L218 hiAutomatonCegarLoop]: Abstraction has 3830 states and 5320 transitions. [2023-11-12 02:32:16,440 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3830 states and 5320 transitions. [2023-11-12 02:32:16,480 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3830 to 2114. [2023-11-12 02:32:16,485 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2114 states, 2114 states have (on average 1.3874172185430464) internal successors, (2933), 2113 states have internal predecessors, (2933), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-12 02:32:16,538 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2114 states to 2114 states and 2933 transitions. [2023-11-12 02:32:16,538 INFO L240 hiAutomatonCegarLoop]: Abstraction has 2114 states and 2933 transitions. [2023-11-12 02:32:16,544 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2023-11-12 02:32:16,545 INFO L428 stractBuchiCegarLoop]: Abstraction has 2114 states and 2933 transitions. [2023-11-12 02:32:16,545 INFO L335 stractBuchiCegarLoop]: ======== Iteration 9 ============ [2023-11-12 02:32:16,545 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2114 states and 2933 transitions. [2023-11-12 02:32:16,561 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 2016 [2023-11-12 02:32:16,561 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-12 02:32:16,561 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-12 02:32:16,562 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-12 02:32:16,563 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-12 02:32:16,563 INFO L748 eck$LassoCheckResult]: Stem: 12789#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2; 12790#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~5#1;havoc main_~__retres1~5#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1; 12805#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret14#1, start_simulation_#t~ret15#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 12802#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 12772#L281 assume 1 == ~m_i~0;~m_st~0 := 0; 12773#L281-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 12561#L286-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 12562#L291-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 12821#L296-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 12526#L418 assume !(0 == ~M_E~0); 12527#L418-2 assume !(0 == ~T1_E~0); 12771#L423-1 assume !(0 == ~T2_E~0); 12825#L428-1 assume 0 == ~T3_E~0;~T3_E~0 := 1; 12830#L433-1 assume !(0 == ~E_1~0); 12808#L438-1 assume !(0 == ~E_2~0); 12723#L443-1 assume !(0 == ~E_3~0); 12717#L448-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 12665#L197 assume !(1 == ~m_pc~0); 12666#L197-2 is_master_triggered_~__retres1~0#1 := 0; 12853#L208 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 12764#is_master_triggered_returnLabel#1 activate_threads_#t~ret9#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 12765#L510 assume !(0 != activate_threads_~tmp~1#1); 12505#L510-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 12506#L216 assume !(1 == ~t1_pc~0); 12557#L216-2 is_transmit1_triggered_~__retres1~1#1 := 0; 12558#L227 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 12590#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret10#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 12507#L518 assume !(0 != activate_threads_~tmp___0~0#1); 12508#L518-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 12735#L235 assume !(1 == ~t2_pc~0); 12814#L235-2 is_transmit2_triggered_~__retres1~2#1 := 0; 12815#L246 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 12865#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret11#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 12843#L526 assume !(0 != activate_threads_~tmp___1~0#1); 12844#L526-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 12852#L254 assume !(1 == ~t3_pc~0); 12566#L254-2 is_transmit3_triggered_~__retres1~3#1 := 0; 12567#L265 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 12518#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 12519#L534 assume !(0 != activate_threads_~tmp___2~0#1); 12701#L534-2 havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 12873#L461 assume !(1 == ~M_E~0); 12563#L461-2 assume !(1 == ~T1_E~0); 12564#L466-1 assume !(1 == ~T2_E~0); 12829#L471-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 12591#L476-1 assume !(1 == ~E_1~0); 12592#L481-1 assume !(1 == ~E_2~0); 12752#L486-1 assume !(1 == ~E_3~0); 12607#L491-1 assume { :end_inline_reset_delta_events } true; 12608#L652-2 [2023-11-12 02:32:16,563 INFO L750 eck$LassoCheckResult]: Loop: 12608#L652-2 assume !false; 13925#L653 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 13913#L393-1 assume !false; 13924#L342 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 13923#L309 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 13919#L331 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 13918#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 13917#L346 assume !(0 != eval_~tmp~0#1); 12696#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 12697#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 12739#L418-3 assume 0 == ~M_E~0;~M_E~0 := 1; 12866#L418-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 14455#L423-3 assume !(0 == ~T2_E~0); 14454#L428-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 14453#L433-3 assume !(0 == ~E_1~0); 14452#L438-3 assume 0 == ~E_2~0;~E_2~0 := 1; 14451#L443-3 assume 0 == ~E_3~0;~E_3~0 := 1; 14450#L448-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 14449#L197-12 assume !(1 == ~m_pc~0); 14448#L197-14 is_master_triggered_~__retres1~0#1 := 0; 14447#L208-4 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 14446#is_master_triggered_returnLabel#5 activate_threads_#t~ret9#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 14445#L510-12 assume !(0 != activate_threads_~tmp~1#1); 14444#L510-14 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 14443#L216-12 assume !(1 == ~t1_pc~0); 14442#L216-14 is_transmit1_triggered_~__retres1~1#1 := 0; 14441#L227-4 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 14440#is_transmit1_triggered_returnLabel#5 activate_threads_#t~ret10#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 14439#L518-12 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 14438#L518-14 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 14437#L235-12 assume 1 == ~t2_pc~0; 14435#L236-4 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 14434#L246-4 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 14433#is_transmit2_triggered_returnLabel#5 activate_threads_#t~ret11#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 14432#L526-12 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 14431#L526-14 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 14430#L254-12 assume !(1 == ~t3_pc~0); 14429#L254-14 is_transmit3_triggered_~__retres1~3#1 := 0; 14428#L265-4 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 14427#is_transmit3_triggered_returnLabel#5 activate_threads_#t~ret12#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 13737#L534-12 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 13738#L534-14 havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 13733#L461-3 assume 1 == ~M_E~0;~M_E~0 := 2; 13734#L461-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 13728#L466-3 assume !(1 == ~T2_E~0); 13729#L471-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 14211#L476-3 assume 1 == ~E_1~0;~E_1~0 := 2; 14210#L481-3 assume !(1 == ~E_2~0); 14209#L486-3 assume 1 == ~E_3~0;~E_3~0 := 2; 14208#L491-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 14207#L309-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 14201#L331-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 14199#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret14#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret14#1;havoc start_simulation_#t~ret14#1; 13937#L671 assume !(0 == start_simulation_~tmp~3#1); 13936#L671-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret13#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 13934#L309-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 13931#L331-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 13930#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret13#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret13#1;havoc stop_simulation_#t~ret13#1; 13929#L626 assume !(0 != stop_simulation_~tmp~2#1);stop_simulation_~__retres2~0#1 := 1; 13928#L633 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 13927#stop_simulation_returnLabel#1 start_simulation_#t~ret15#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret13#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret15#1;havoc start_simulation_#t~ret15#1; 13926#L684 assume !(0 != start_simulation_~tmp___0~1#1); 12608#L652-2 [2023-11-12 02:32:16,564 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-12 02:32:16,564 INFO L85 PathProgramCache]: Analyzing trace with hash -286909970, now seen corresponding path program 1 times [2023-11-12 02:32:16,564 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-12 02:32:16,564 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [557395435] [2023-11-12 02:32:16,565 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-12 02:32:16,565 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-12 02:32:16,573 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-12 02:32:16,613 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-12 02:32:16,614 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-12 02:32:16,614 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [557395435] [2023-11-12 02:32:16,614 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [557395435] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-12 02:32:16,615 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-12 02:32:16,615 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-12 02:32:16,615 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [832783610] [2023-11-12 02:32:16,615 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-12 02:32:16,616 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-12 02:32:16,616 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-12 02:32:16,616 INFO L85 PathProgramCache]: Analyzing trace with hash 1085822616, now seen corresponding path program 1 times [2023-11-12 02:32:16,616 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-12 02:32:16,617 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [397730203] [2023-11-12 02:32:16,617 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-12 02:32:16,617 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-12 02:32:16,628 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-12 02:32:16,656 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-12 02:32:16,656 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-12 02:32:16,657 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [397730203] [2023-11-12 02:32:16,657 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [397730203] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-12 02:32:16,657 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-12 02:32:16,657 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-12 02:32:16,657 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1757537148] [2023-11-12 02:32:16,658 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-12 02:32:16,658 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-12 02:32:16,658 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-12 02:32:16,659 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2023-11-12 02:32:16,659 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2023-11-12 02:32:16,659 INFO L87 Difference]: Start difference. First operand 2114 states and 2933 transitions. cyclomatic complexity: 823 Second operand has 4 states, 4 states have (on average 12.25) internal successors, (49), 3 states have internal predecessors, (49), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-12 02:32:16,705 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-12 02:32:16,706 INFO L93 Difference]: Finished difference Result 1762 states and 2437 transitions. [2023-11-12 02:32:16,706 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1762 states and 2437 transitions. [2023-11-12 02:32:16,723 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 1697 [2023-11-12 02:32:16,737 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1762 states to 1762 states and 2437 transitions. [2023-11-12 02:32:16,738 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1762 [2023-11-12 02:32:16,740 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1762 [2023-11-12 02:32:16,740 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1762 states and 2437 transitions. [2023-11-12 02:32:16,743 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-12 02:32:16,743 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1762 states and 2437 transitions. [2023-11-12 02:32:16,746 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1762 states and 2437 transitions. [2023-11-12 02:32:16,768 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1762 to 1762. [2023-11-12 02:32:16,772 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1762 states, 1762 states have (on average 1.3830874006810443) internal successors, (2437), 1761 states have internal predecessors, (2437), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-12 02:32:16,779 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1762 states to 1762 states and 2437 transitions. [2023-11-12 02:32:16,779 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1762 states and 2437 transitions. [2023-11-12 02:32:16,779 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-12 02:32:16,780 INFO L428 stractBuchiCegarLoop]: Abstraction has 1762 states and 2437 transitions. [2023-11-12 02:32:16,780 INFO L335 stractBuchiCegarLoop]: ======== Iteration 10 ============ [2023-11-12 02:32:16,780 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1762 states and 2437 transitions. [2023-11-12 02:32:16,791 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 1697 [2023-11-12 02:32:16,791 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-12 02:32:16,791 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-12 02:32:16,792 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-12 02:32:16,792 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-12 02:32:16,792 INFO L748 eck$LassoCheckResult]: Stem: 16647#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2; 16648#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~5#1;havoc main_~__retres1~5#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1; 16662#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret14#1, start_simulation_#t~ret15#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 16657#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 16631#L281 assume 1 == ~m_i~0;~m_st~0 := 0; 16632#L281-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 16446#L286-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 16447#L291-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 16675#L296-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 16412#L418 assume !(0 == ~M_E~0); 16413#L418-2 assume !(0 == ~T1_E~0); 16630#L423-1 assume !(0 == ~T2_E~0); 16679#L428-1 assume !(0 == ~T3_E~0); 16677#L433-1 assume !(0 == ~E_1~0); 16665#L438-1 assume !(0 == ~E_2~0); 16586#L443-1 assume !(0 == ~E_3~0); 16580#L448-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 16540#L197 assume !(1 == ~m_pc~0); 16541#L197-2 is_master_triggered_~__retres1~0#1 := 0; 16703#L208 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 16623#is_master_triggered_returnLabel#1 activate_threads_#t~ret9#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 16624#L510 assume !(0 != activate_threads_~tmp~1#1); 16391#L510-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 16392#L216 assume !(1 == ~t1_pc~0); 16442#L216-2 is_transmit1_triggered_~__retres1~1#1 := 0; 16443#L227 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 16473#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret10#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 16393#L518 assume !(0 != activate_threads_~tmp___0~0#1); 16394#L518-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 16595#L235 assume !(1 == ~t2_pc~0); 16671#L235-2 is_transmit2_triggered_~__retres1~2#1 := 0; 16528#L246 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 16529#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret11#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 16693#L526 assume !(0 != activate_threads_~tmp___1~0#1); 16694#L526-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 16513#L254 assume !(1 == ~t3_pc~0); 16450#L254-2 is_transmit3_triggered_~__retres1~3#1 := 0; 16451#L265 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 16404#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 16405#L534 assume !(0 != activate_threads_~tmp___2~0#1); 16523#L534-2 havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 16383#L461 assume !(1 == ~M_E~0); 16384#L461-2 assume !(1 == ~T1_E~0); 16448#L466-1 assume !(1 == ~T2_E~0); 16682#L471-1 assume !(1 == ~T3_E~0); 16474#L476-1 assume !(1 == ~E_1~0); 16475#L481-1 assume !(1 == ~E_2~0); 16612#L486-1 assume !(1 == ~E_3~0); 16490#L491-1 assume { :end_inline_reset_delta_events } true; 16400#L652-2 [2023-11-12 02:32:16,793 INFO L750 eck$LassoCheckResult]: Loop: 16400#L652-2 assume !false; 16401#L653 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 16468#L393-1 assume !false; 16465#L342 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 16466#L309 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 16440#L331 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 16406#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 16407#L346 assume !(0 != eval_~tmp~0#1); 16495#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 16562#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 16599#L418-3 assume 0 == ~M_E~0;~M_E~0 := 1; 16713#L418-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 18082#L423-3 assume !(0 == ~T2_E~0); 18081#L428-3 assume !(0 == ~T3_E~0); 18079#L433-3 assume !(0 == ~E_1~0); 18077#L438-3 assume 0 == ~E_2~0;~E_2~0 := 1; 18075#L443-3 assume 0 == ~E_3~0;~E_3~0 := 1; 18073#L448-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 18071#L197-12 assume !(1 == ~m_pc~0); 18069#L197-14 is_master_triggered_~__retres1~0#1 := 0; 18067#L208-4 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 18065#is_master_triggered_returnLabel#5 activate_threads_#t~ret9#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 18063#L510-12 assume !(0 != activate_threads_~tmp~1#1); 18061#L510-14 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 18059#L216-12 assume !(1 == ~t1_pc~0); 18057#L216-14 is_transmit1_triggered_~__retres1~1#1 := 0; 18055#L227-4 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 18053#is_transmit1_triggered_returnLabel#5 activate_threads_#t~ret10#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 18051#L518-12 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 18050#L518-14 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 18049#L235-12 assume !(1 == ~t2_pc~0); 18048#L235-14 is_transmit2_triggered_~__retres1~2#1 := 0; 18045#L246-4 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 18043#is_transmit2_triggered_returnLabel#5 activate_threads_#t~ret11#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 18041#L526-12 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 18039#L526-14 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 18037#L254-12 assume !(1 == ~t3_pc~0); 18035#L254-14 is_transmit3_triggered_~__retres1~3#1 := 0; 18033#L265-4 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 18031#is_transmit3_triggered_returnLabel#5 activate_threads_#t~ret12#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 18029#L534-12 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 18027#L534-14 havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 18025#L461-3 assume 1 == ~M_E~0;~M_E~0 := 2; 18023#L461-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 18022#L466-3 assume !(1 == ~T2_E~0); 18021#L471-3 assume !(1 == ~T3_E~0); 18020#L476-3 assume 1 == ~E_1~0;~E_1~0 := 2; 18019#L481-3 assume !(1 == ~E_2~0); 18015#L486-3 assume 1 == ~E_3~0;~E_3~0 := 2; 18014#L491-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 16423#L309-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 16424#L331-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 16449#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret14#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret14#1;havoc start_simulation_#t~ret14#1; 16602#L671 assume !(0 == start_simulation_~tmp~3#1); 16411#L671-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret13#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 16636#L309-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 16502#L331-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 16471#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret13#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret13#1;havoc stop_simulation_#t~ret13#1; 16472#L626 assume !(0 != stop_simulation_~tmp~2#1);stop_simulation_~__retres2~0#1 := 1; 16618#L633 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 16619#stop_simulation_returnLabel#1 start_simulation_#t~ret15#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret13#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret15#1;havoc start_simulation_#t~ret15#1; 16621#L684 assume !(0 != start_simulation_~tmp___0~1#1); 16400#L652-2 [2023-11-12 02:32:16,793 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-12 02:32:16,793 INFO L85 PathProgramCache]: Analyzing trace with hash 374468594, now seen corresponding path program 1 times [2023-11-12 02:32:16,794 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-12 02:32:16,794 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2050506640] [2023-11-12 02:32:16,794 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-12 02:32:16,794 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-12 02:32:16,802 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-12 02:32:16,802 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-12 02:32:16,807 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-12 02:32:16,840 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-12 02:32:16,841 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-12 02:32:16,842 INFO L85 PathProgramCache]: Analyzing trace with hash 400930619, now seen corresponding path program 1 times [2023-11-12 02:32:16,842 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-12 02:32:16,842 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1045152867] [2023-11-12 02:32:16,843 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-12 02:32:16,847 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-12 02:32:16,857 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-12 02:32:16,879 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-12 02:32:16,879 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-12 02:32:16,879 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1045152867] [2023-11-12 02:32:16,880 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1045152867] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-12 02:32:16,880 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-12 02:32:16,880 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-12 02:32:16,880 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2111530395] [2023-11-12 02:32:16,880 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-12 02:32:16,881 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-12 02:32:16,881 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-12 02:32:16,881 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-12 02:32:16,881 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-12 02:32:16,882 INFO L87 Difference]: Start difference. First operand 1762 states and 2437 transitions. cyclomatic complexity: 679 Second operand has 3 states, 3 states have (on average 20.666666666666668) internal successors, (62), 3 states have internal predecessors, (62), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-12 02:32:16,947 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-12 02:32:16,947 INFO L93 Difference]: Finished difference Result 3038 states and 4146 transitions. [2023-11-12 02:32:16,947 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 3038 states and 4146 transitions. [2023-11-12 02:32:16,968 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 2925 [2023-11-12 02:32:16,992 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 3038 states to 3038 states and 4146 transitions. [2023-11-12 02:32:16,992 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 3038 [2023-11-12 02:32:16,996 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 3038 [2023-11-12 02:32:16,996 INFO L73 IsDeterministic]: Start isDeterministic. Operand 3038 states and 4146 transitions. [2023-11-12 02:32:17,001 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-12 02:32:17,001 INFO L218 hiAutomatonCegarLoop]: Abstraction has 3038 states and 4146 transitions. [2023-11-12 02:32:17,006 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3038 states and 4146 transitions. [2023-11-12 02:32:17,095 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3038 to 3035. [2023-11-12 02:32:17,102 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 3035 states, 3035 states have (on average 1.3650741350906095) internal successors, (4143), 3034 states have internal predecessors, (4143), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-12 02:32:17,113 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3035 states to 3035 states and 4143 transitions. [2023-11-12 02:32:17,113 INFO L240 hiAutomatonCegarLoop]: Abstraction has 3035 states and 4143 transitions. [2023-11-12 02:32:17,114 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-12 02:32:17,115 INFO L428 stractBuchiCegarLoop]: Abstraction has 3035 states and 4143 transitions. [2023-11-12 02:32:17,115 INFO L335 stractBuchiCegarLoop]: ======== Iteration 11 ============ [2023-11-12 02:32:17,115 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 3035 states and 4143 transitions. [2023-11-12 02:32:17,129 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 2922 [2023-11-12 02:32:17,129 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-12 02:32:17,129 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-12 02:32:17,130 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-12 02:32:17,130 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-12 02:32:17,131 INFO L748 eck$LassoCheckResult]: Stem: 21477#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2; 21478#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~5#1;havoc main_~__retres1~5#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1; 21494#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret14#1, start_simulation_#t~ret15#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 21489#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 21462#L281 assume 1 == ~m_i~0;~m_st~0 := 0; 21463#L281-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 21253#L286-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 21254#L291-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 21508#L296-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 21222#L418 assume !(0 == ~M_E~0); 21223#L418-2 assume !(0 == ~T1_E~0); 21461#L423-1 assume !(0 == ~T2_E~0); 21514#L428-1 assume !(0 == ~T3_E~0); 21512#L433-1 assume !(0 == ~E_1~0); 21497#L438-1 assume 0 == ~E_2~0;~E_2~0 := 1; 21498#L443-1 assume !(0 == ~E_3~0); 21625#L448-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 21354#L197 assume !(1 == ~m_pc~0); 21355#L197-2 is_master_triggered_~__retres1~0#1 := 0; 21554#L208 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 21555#is_master_triggered_returnLabel#1 activate_threads_#t~ret9#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 21528#L510 assume !(0 != activate_threads_~tmp~1#1); 21529#L510-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 21553#L216 assume !(1 == ~t1_pc~0); 21251#L216-2 is_transmit1_triggered_~__retres1~1#1 := 0; 21252#L227 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 21281#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret10#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 21199#L518 assume !(0 != activate_threads_~tmp___0~0#1); 21200#L518-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 21560#L235 assume !(1 == ~t2_pc~0); 21507#L235-2 is_transmit2_triggered_~__retres1~2#1 := 0; 21342#L246 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 21343#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret11#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 21598#L526 assume !(0 != activate_threads_~tmp___1~0#1); 21596#L526-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 21593#L254 assume !(1 == ~t3_pc~0); 21591#L254-2 is_transmit3_triggered_~__retres1~3#1 := 0; 21589#L265 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 21587#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 21585#L534 assume !(0 != activate_threads_~tmp___2~0#1); 21583#L534-2 havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 21580#L461 assume !(1 == ~M_E~0); 21578#L461-2 assume !(1 == ~T1_E~0); 21576#L466-1 assume !(1 == ~T2_E~0); 21574#L471-1 assume !(1 == ~T3_E~0); 21282#L476-1 assume !(1 == ~E_1~0); 21283#L481-1 assume 1 == ~E_2~0;~E_2~0 := 2; 21438#L486-1 assume !(1 == ~E_3~0); 21300#L491-1 assume { :end_inline_reset_delta_events } true; 21301#L652-2 [2023-11-12 02:32:17,131 INFO L750 eck$LassoCheckResult]: Loop: 21301#L652-2 assume !false; 21314#L653 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 21276#L393-1 assume !false; 21273#L342 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 21274#L309 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 21454#L331 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 21455#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 23815#L346 assume !(0 != eval_~tmp~0#1); 23816#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 24178#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 24175#L418-3 assume 0 == ~M_E~0;~M_E~0 := 1; 24171#L418-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 24170#L423-3 assume !(0 == ~T2_E~0); 24167#L428-3 assume !(0 == ~T3_E~0); 24164#L433-3 assume !(0 == ~E_1~0); 24162#L438-3 assume !(0 == ~E_2~0); 24128#L443-3 assume 0 == ~E_3~0;~E_3~0 := 1; 24127#L448-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 24126#L197-12 assume !(1 == ~m_pc~0); 24125#L197-14 is_master_triggered_~__retres1~0#1 := 0; 24124#L208-4 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 24123#is_master_triggered_returnLabel#5 activate_threads_#t~ret9#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 24112#L510-12 assume !(0 != activate_threads_~tmp~1#1); 24111#L510-14 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 24109#L216-12 assume !(1 == ~t1_pc~0); 24107#L216-14 is_transmit1_triggered_~__retres1~1#1 := 0; 24105#L227-4 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 24103#is_transmit1_triggered_returnLabel#5 activate_threads_#t~ret10#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 24101#L518-12 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 24099#L518-14 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 24096#L235-12 assume !(1 == ~t2_pc~0); 24092#L235-14 is_transmit2_triggered_~__retres1~2#1 := 0; 24090#L246-4 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 24089#is_transmit2_triggered_returnLabel#5 activate_threads_#t~ret11#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 24088#L526-12 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 24087#L526-14 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 24086#L254-12 assume !(1 == ~t3_pc~0); 24085#L254-14 is_transmit3_triggered_~__retres1~3#1 := 0; 24084#L265-4 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 24083#is_transmit3_triggered_returnLabel#5 activate_threads_#t~ret12#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 24082#L534-12 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 24081#L534-14 havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 24080#L461-3 assume 1 == ~M_E~0;~M_E~0 := 2; 24078#L461-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 24076#L466-3 assume !(1 == ~T2_E~0); 24075#L471-3 assume !(1 == ~T3_E~0); 24074#L476-3 assume 1 == ~E_1~0;~E_1~0 := 2; 24073#L481-3 assume !(1 == ~E_2~0); 21348#L486-3 assume 1 == ~E_3~0;~E_3~0 := 2; 21349#L491-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 23849#L309-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 21256#L331-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 21257#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret14#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret14#1;havoc start_simulation_#t~ret14#1; 21424#L671 assume !(0 == start_simulation_~tmp~3#1); 21215#L671-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret13#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 21467#L309-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 21437#L331-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 21279#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret13#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret13#1;havoc stop_simulation_#t~ret13#1; 21280#L626 assume !(0 != stop_simulation_~tmp~2#1);stop_simulation_~__retres2~0#1 := 1; 21518#L633 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 21446#stop_simulation_returnLabel#1 start_simulation_#t~ret15#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret13#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret15#1;havoc start_simulation_#t~ret15#1; 21447#L684 assume !(0 != start_simulation_~tmp___0~1#1); 21301#L652-2 [2023-11-12 02:32:17,132 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-12 02:32:17,132 INFO L85 PathProgramCache]: Analyzing trace with hash 1218472174, now seen corresponding path program 1 times [2023-11-12 02:32:17,132 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-12 02:32:17,132 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [300272928] [2023-11-12 02:32:17,132 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-12 02:32:17,133 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-12 02:32:17,139 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-12 02:32:17,169 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-12 02:32:17,170 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-12 02:32:17,170 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [300272928] [2023-11-12 02:32:17,170 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [300272928] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-12 02:32:17,170 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-12 02:32:17,171 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2023-11-12 02:32:17,171 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1763095754] [2023-11-12 02:32:17,171 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-12 02:32:17,171 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-12 02:32:17,173 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-12 02:32:17,174 INFO L85 PathProgramCache]: Analyzing trace with hash 47842237, now seen corresponding path program 1 times [2023-11-12 02:32:17,174 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-12 02:32:17,175 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1937602422] [2023-11-12 02:32:17,175 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-12 02:32:17,175 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-12 02:32:17,191 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-12 02:32:17,244 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-12 02:32:17,244 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-12 02:32:17,245 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1937602422] [2023-11-12 02:32:17,245 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1937602422] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-12 02:32:17,245 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-12 02:32:17,245 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2023-11-12 02:32:17,245 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [865805711] [2023-11-12 02:32:17,246 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-12 02:32:17,246 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-12 02:32:17,246 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-12 02:32:17,247 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-12 02:32:17,247 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-12 02:32:17,247 INFO L87 Difference]: Start difference. First operand 3035 states and 4143 transitions. cyclomatic complexity: 1112 Second operand has 3 states, 3 states have (on average 16.333333333333332) internal successors, (49), 2 states have internal predecessors, (49), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-12 02:32:17,290 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-12 02:32:17,290 INFO L93 Difference]: Finished difference Result 1762 states and 2373 transitions. [2023-11-12 02:32:17,290 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1762 states and 2373 transitions. [2023-11-12 02:32:17,301 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 1697 [2023-11-12 02:32:17,315 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1762 states to 1762 states and 2373 transitions. [2023-11-12 02:32:17,316 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1762 [2023-11-12 02:32:17,319 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1762 [2023-11-12 02:32:17,319 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1762 states and 2373 transitions. [2023-11-12 02:32:17,322 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-12 02:32:17,323 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1762 states and 2373 transitions. [2023-11-12 02:32:17,325 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1762 states and 2373 transitions. [2023-11-12 02:32:17,355 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1762 to 1762. [2023-11-12 02:32:17,359 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1762 states, 1762 states have (on average 1.3467650397275823) internal successors, (2373), 1761 states have internal predecessors, (2373), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-12 02:32:17,366 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1762 states to 1762 states and 2373 transitions. [2023-11-12 02:32:17,366 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1762 states and 2373 transitions. [2023-11-12 02:32:17,366 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-12 02:32:17,367 INFO L428 stractBuchiCegarLoop]: Abstraction has 1762 states and 2373 transitions. [2023-11-12 02:32:17,367 INFO L335 stractBuchiCegarLoop]: ======== Iteration 12 ============ [2023-11-12 02:32:17,367 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1762 states and 2373 transitions. [2023-11-12 02:32:17,376 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 1697 [2023-11-12 02:32:17,376 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-12 02:32:17,376 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-12 02:32:17,377 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-12 02:32:17,377 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-12 02:32:17,378 INFO L748 eck$LassoCheckResult]: Stem: 26266#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2; 26267#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~5#1;havoc main_~__retres1~5#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1; 26280#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret14#1, start_simulation_#t~ret15#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 26275#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 26250#L281 assume 1 == ~m_i~0;~m_st~0 := 0; 26251#L281-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 26058#L286-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 26059#L291-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 26294#L296-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 26028#L418 assume !(0 == ~M_E~0); 26029#L418-2 assume !(0 == ~T1_E~0); 26249#L423-1 assume !(0 == ~T2_E~0); 26299#L428-1 assume !(0 == ~T3_E~0); 26297#L433-1 assume !(0 == ~E_1~0); 26282#L438-1 assume !(0 == ~E_2~0); 26205#L443-1 assume !(0 == ~E_3~0); 26197#L448-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 26156#L197 assume !(1 == ~m_pc~0); 26157#L197-2 is_master_triggered_~__retres1~0#1 := 0; 26323#L208 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 26241#is_master_triggered_returnLabel#1 activate_threads_#t~ret9#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 26242#L510 assume !(0 != activate_threads_~tmp~1#1); 26003#L510-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 26004#L216 assume !(1 == ~t1_pc~0); 26056#L216-2 is_transmit1_triggered_~__retres1~1#1 := 0; 26057#L227 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 26086#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret10#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 26008#L518 assume !(0 != activate_threads_~tmp___0~0#1); 26009#L518-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 26214#L235 assume !(1 == ~t2_pc~0); 26292#L235-2 is_transmit2_triggered_~__retres1~2#1 := 0; 26144#L246 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 26145#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret11#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 26313#L526 assume !(0 != activate_threads_~tmp___1~0#1); 26314#L526-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 26130#L254 assume !(1 == ~t3_pc~0); 26062#L254-2 is_transmit3_triggered_~__retres1~3#1 := 0; 26063#L265 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 26018#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 26019#L534 assume !(0 != activate_threads_~tmp___2~0#1); 26138#L534-2 havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 25995#L461 assume !(1 == ~M_E~0); 25996#L461-2 assume !(1 == ~T1_E~0); 26060#L466-1 assume !(1 == ~T2_E~0); 26303#L471-1 assume !(1 == ~T3_E~0); 26089#L476-1 assume !(1 == ~E_1~0); 26090#L481-1 assume !(1 == ~E_2~0); 26230#L486-1 assume !(1 == ~E_3~0); 26107#L491-1 assume { :end_inline_reset_delta_events } true; 26014#L652-2 [2023-11-12 02:32:17,378 INFO L750 eck$LassoCheckResult]: Loop: 26014#L652-2 assume !false; 26015#L653 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 26081#L393-1 assume !false; 26238#L342 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 27518#L309 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 27510#L331 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 27508#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 27507#L346 assume !(0 != eval_~tmp~0#1); 26182#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 26183#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 26217#L418-3 assume 0 == ~M_E~0;~M_E~0 := 1; 26211#L418-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 26212#L423-3 assume !(0 == ~T2_E~0); 26206#L428-3 assume !(0 == ~T3_E~0); 26154#L433-3 assume !(0 == ~E_1~0); 26155#L438-3 assume !(0 == ~E_2~0); 26262#L443-3 assume 0 == ~E_3~0;~E_3~0 := 1; 25997#L448-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 25998#L197-12 assume !(1 == ~m_pc~0); 26268#L197-14 is_master_triggered_~__retres1~0#1 := 0; 26124#L208-4 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 26125#is_master_triggered_returnLabel#5 activate_threads_#t~ret9#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 26010#L510-12 assume !(0 != activate_threads_~tmp~1#1); 26011#L510-14 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 26122#L216-12 assume !(1 == ~t1_pc~0); 26123#L216-14 is_transmit1_triggered_~__retres1~1#1 := 0; 26172#L227-4 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 26173#is_transmit1_triggered_returnLabel#5 activate_threads_#t~ret10#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 26133#L518-12 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 26054#L518-14 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 26055#L235-12 assume !(1 == ~t2_pc~0); 26141#L235-14 is_transmit2_triggered_~__retres1~2#1 := 0; 26142#L246-4 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 26134#is_transmit2_triggered_returnLabel#5 activate_threads_#t~ret11#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 26135#L526-12 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 26198#L526-14 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 26199#L254-12 assume !(1 == ~t3_pc~0); 26308#L254-14 is_transmit3_triggered_~__retres1~3#1 := 0; 26201#L265-4 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 26087#is_transmit3_triggered_returnLabel#5 activate_threads_#t~ret12#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 26088#L534-12 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 26178#L534-14 havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 26231#L461-3 assume 1 == ~M_E~0;~M_E~0 := 2; 27711#L461-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 27710#L466-3 assume !(1 == ~T2_E~0); 27709#L471-3 assume !(1 == ~T3_E~0); 27708#L476-3 assume 1 == ~E_1~0;~E_1~0 := 2; 27707#L481-3 assume !(1 == ~E_2~0); 27706#L486-3 assume 1 == ~E_3~0;~E_3~0 := 2; 27704#L491-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 27702#L309-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 27697#L331-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 27695#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret14#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret14#1;havoc start_simulation_#t~ret14#1; 27640#L671 assume !(0 == start_simulation_~tmp~3#1); 27638#L671-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret13#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 26332#L309-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 26115#L331-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 26084#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret13#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret13#1;havoc stop_simulation_#t~ret13#1; 26085#L626 assume !(0 != stop_simulation_~tmp~2#1);stop_simulation_~__retres2~0#1 := 1; 26236#L633 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 26237#stop_simulation_returnLabel#1 start_simulation_#t~ret15#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret13#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret15#1;havoc start_simulation_#t~ret15#1; 26239#L684 assume !(0 != start_simulation_~tmp___0~1#1); 26014#L652-2 [2023-11-12 02:32:17,379 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-12 02:32:17,379 INFO L85 PathProgramCache]: Analyzing trace with hash 374468594, now seen corresponding path program 2 times [2023-11-12 02:32:17,379 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-12 02:32:17,380 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [976028499] [2023-11-12 02:32:17,380 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-12 02:32:17,380 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-12 02:32:17,394 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-12 02:32:17,394 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-12 02:32:17,401 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-12 02:32:17,415 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-12 02:32:17,416 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-12 02:32:17,416 INFO L85 PathProgramCache]: Analyzing trace with hash 47842237, now seen corresponding path program 2 times [2023-11-12 02:32:17,416 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-12 02:32:17,417 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1662440094] [2023-11-12 02:32:17,417 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-12 02:32:17,417 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-12 02:32:17,437 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-12 02:32:17,484 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-12 02:32:17,485 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-12 02:32:17,485 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1662440094] [2023-11-12 02:32:17,492 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1662440094] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-12 02:32:17,493 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-12 02:32:17,493 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2023-11-12 02:32:17,496 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1420373037] [2023-11-12 02:32:17,497 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-12 02:32:17,497 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-12 02:32:17,497 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-12 02:32:17,498 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2023-11-12 02:32:17,498 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2023-11-12 02:32:17,498 INFO L87 Difference]: Start difference. First operand 1762 states and 2373 transitions. cyclomatic complexity: 615 Second operand has 5 states, 5 states have (on average 12.4) internal successors, (62), 5 states have internal predecessors, (62), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-12 02:32:17,647 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-12 02:32:17,647 INFO L93 Difference]: Finished difference Result 3047 states and 4043 transitions. [2023-11-12 02:32:17,647 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 3047 states and 4043 transitions. [2023-11-12 02:32:17,662 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 2967 [2023-11-12 02:32:17,681 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 3047 states to 3047 states and 4043 transitions. [2023-11-12 02:32:17,682 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 3047 [2023-11-12 02:32:17,685 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 3047 [2023-11-12 02:32:17,685 INFO L73 IsDeterministic]: Start isDeterministic. Operand 3047 states and 4043 transitions. [2023-11-12 02:32:17,690 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-12 02:32:17,690 INFO L218 hiAutomatonCegarLoop]: Abstraction has 3047 states and 4043 transitions. [2023-11-12 02:32:17,694 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3047 states and 4043 transitions. [2023-11-12 02:32:17,727 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3047 to 1789. [2023-11-12 02:32:17,731 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1789 states, 1789 states have (on average 1.3415315818893236) internal successors, (2400), 1788 states have internal predecessors, (2400), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-12 02:32:17,736 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1789 states to 1789 states and 2400 transitions. [2023-11-12 02:32:17,736 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1789 states and 2400 transitions. [2023-11-12 02:32:17,737 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 9 states. [2023-11-12 02:32:17,739 INFO L428 stractBuchiCegarLoop]: Abstraction has 1789 states and 2400 transitions. [2023-11-12 02:32:17,739 INFO L335 stractBuchiCegarLoop]: ======== Iteration 13 ============ [2023-11-12 02:32:17,740 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1789 states and 2400 transitions. [2023-11-12 02:32:17,747 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 1724 [2023-11-12 02:32:17,747 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-12 02:32:17,747 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-12 02:32:17,751 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-12 02:32:17,751 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-12 02:32:17,751 INFO L748 eck$LassoCheckResult]: Stem: 31106#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2; 31107#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~5#1;havoc main_~__retres1~5#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1; 31122#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret14#1, start_simulation_#t~ret15#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 31117#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 31087#L281 assume 1 == ~m_i~0;~m_st~0 := 0; 31088#L281-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 30884#L286-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 30885#L291-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 31136#L296-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 30854#L418 assume !(0 == ~M_E~0); 30855#L418-2 assume !(0 == ~T1_E~0); 31086#L423-1 assume !(0 == ~T2_E~0); 31140#L428-1 assume !(0 == ~T3_E~0); 31138#L433-1 assume !(0 == ~E_1~0); 31125#L438-1 assume !(0 == ~E_2~0); 31034#L443-1 assume !(0 == ~E_3~0); 31026#L448-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 30981#L197 assume !(1 == ~m_pc~0); 30982#L197-2 is_master_triggered_~__retres1~0#1 := 0; 31177#L208 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 31077#is_master_triggered_returnLabel#1 activate_threads_#t~ret9#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 31078#L510 assume !(0 != activate_threads_~tmp~1#1); 30829#L510-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 30830#L216 assume !(1 == ~t1_pc~0); 30882#L216-2 is_transmit1_triggered_~__retres1~1#1 := 0; 30883#L227 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 30911#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret10#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 30834#L518 assume !(0 != activate_threads_~tmp___0~0#1); 30835#L518-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 31048#L235 assume !(1 == ~t2_pc~0); 31135#L235-2 is_transmit2_triggered_~__retres1~2#1 := 0; 30969#L246 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 30970#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret11#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 31165#L526 assume !(0 != activate_threads_~tmp___1~0#1); 31166#L526-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 30954#L254 assume !(1 == ~t3_pc~0); 30888#L254-2 is_transmit3_triggered_~__retres1~3#1 := 0; 30889#L265 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 30844#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 30845#L534 assume !(0 != activate_threads_~tmp___2~0#1); 30963#L534-2 havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 30821#L461 assume !(1 == ~M_E~0); 30822#L461-2 assume !(1 == ~T1_E~0); 30886#L466-1 assume !(1 == ~T2_E~0); 31144#L471-1 assume !(1 == ~T3_E~0); 30914#L476-1 assume !(1 == ~E_1~0); 30915#L481-1 assume !(1 == ~E_2~0); 31065#L486-1 assume !(1 == ~E_3~0); 30933#L491-1 assume { :end_inline_reset_delta_events } true; 30838#L652-2 [2023-11-12 02:32:17,752 INFO L750 eck$LassoCheckResult]: Loop: 30838#L652-2 assume !false; 30839#L653 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 30904#L393-1 assume !false; 30905#L342 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 30906#L309 assume !(0 == ~m_st~0); 31153#L313 assume !(0 == ~t1_st~0); 32390#L317 assume !(0 == ~t2_st~0); 32387#L321 assume !(0 == ~t3_st~0);exists_runnable_thread_~__retres1~4#1 := 0; 32385#L331 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 32373#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 32160#L346 assume !(0 != eval_~tmp~0#1); 32161#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 32527#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 32526#L418-3 assume 0 == ~M_E~0;~M_E~0 := 1; 32525#L418-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 32524#L423-3 assume !(0 == ~T2_E~0); 32523#L428-3 assume !(0 == ~T3_E~0); 32522#L433-3 assume !(0 == ~E_1~0); 32521#L438-3 assume !(0 == ~E_2~0); 32520#L443-3 assume 0 == ~E_3~0;~E_3~0 := 1; 32519#L448-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 32518#L197-12 assume !(1 == ~m_pc~0); 32517#L197-14 is_master_triggered_~__retres1~0#1 := 0; 32516#L208-4 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 32515#is_master_triggered_returnLabel#5 activate_threads_#t~ret9#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 32514#L510-12 assume !(0 != activate_threads_~tmp~1#1); 32513#L510-14 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 32512#L216-12 assume !(1 == ~t1_pc~0); 32511#L216-14 is_transmit1_triggered_~__retres1~1#1 := 0; 32510#L227-4 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 32509#is_transmit1_triggered_returnLabel#5 activate_threads_#t~ret10#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 32508#L518-12 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 32507#L518-14 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 32506#L235-12 assume !(1 == ~t2_pc~0); 32504#L235-14 is_transmit2_triggered_~__retres1~2#1 := 0; 32503#L246-4 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 32502#is_transmit2_triggered_returnLabel#5 activate_threads_#t~ret11#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 32501#L526-12 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 32500#L526-14 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 32499#L254-12 assume !(1 == ~t3_pc~0); 32498#L254-14 is_transmit3_triggered_~__retres1~3#1 := 0; 32497#L265-4 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 32496#is_transmit3_triggered_returnLabel#5 activate_threads_#t~ret12#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 32495#L534-12 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 32494#L534-14 havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 32493#L461-3 assume 1 == ~M_E~0;~M_E~0 := 2; 32492#L461-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 32491#L466-3 assume !(1 == ~T2_E~0); 32490#L471-3 assume !(1 == ~T3_E~0); 32489#L476-3 assume 1 == ~E_1~0;~E_1~0 := 2; 32488#L481-3 assume !(1 == ~E_2~0); 32487#L486-3 assume 1 == ~E_3~0;~E_3~0 := 2; 32486#L491-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 32485#L309-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 32481#L331-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 32478#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret14#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret14#1;havoc start_simulation_#t~ret14#1; 32475#L671 assume !(0 == start_simulation_~tmp~3#1); 32473#L671-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret13#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 31191#L309-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 30940#L331-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 30909#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret13#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret13#1;havoc stop_simulation_#t~ret13#1; 30910#L626 assume !(0 != stop_simulation_~tmp~2#1);stop_simulation_~__retres2~0#1 := 1; 31070#L633 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 31071#stop_simulation_returnLabel#1 start_simulation_#t~ret15#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret13#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret15#1;havoc start_simulation_#t~ret15#1; 31073#L684 assume !(0 != start_simulation_~tmp___0~1#1); 30838#L652-2 [2023-11-12 02:32:17,752 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-12 02:32:17,752 INFO L85 PathProgramCache]: Analyzing trace with hash 374468594, now seen corresponding path program 3 times [2023-11-12 02:32:17,752 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-12 02:32:17,753 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1187509208] [2023-11-12 02:32:17,753 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-12 02:32:17,753 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-12 02:32:17,767 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-12 02:32:17,767 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-12 02:32:17,774 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-12 02:32:17,794 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-12 02:32:17,796 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-12 02:32:17,796 INFO L85 PathProgramCache]: Analyzing trace with hash -182477129, now seen corresponding path program 1 times [2023-11-12 02:32:17,796 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-12 02:32:17,796 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [609394548] [2023-11-12 02:32:17,796 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-12 02:32:17,797 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-12 02:32:17,805 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-12 02:32:17,826 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-12 02:32:17,827 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-12 02:32:17,827 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [609394548] [2023-11-12 02:32:17,827 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [609394548] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-12 02:32:17,827 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-12 02:32:17,827 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-12 02:32:17,827 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1346706488] [2023-11-12 02:32:17,828 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-12 02:32:17,828 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-12 02:32:17,828 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-12 02:32:17,828 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-12 02:32:17,829 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-12 02:32:17,829 INFO L87 Difference]: Start difference. First operand 1789 states and 2400 transitions. cyclomatic complexity: 615 Second operand has 3 states, 3 states have (on average 21.666666666666668) internal successors, (65), 3 states have internal predecessors, (65), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-12 02:32:17,876 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-12 02:32:17,877 INFO L93 Difference]: Finished difference Result 2802 states and 3697 transitions. [2023-11-12 02:32:17,877 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2802 states and 3697 transitions. [2023-11-12 02:32:17,891 INFO L131 ngComponentsAnalysis]: Automaton has 7 accepting balls. 2735 [2023-11-12 02:32:17,911 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2802 states to 2802 states and 3697 transitions. [2023-11-12 02:32:17,911 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2802 [2023-11-12 02:32:17,914 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2802 [2023-11-12 02:32:17,915 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2802 states and 3697 transitions. [2023-11-12 02:32:17,919 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-12 02:32:17,919 INFO L218 hiAutomatonCegarLoop]: Abstraction has 2802 states and 3697 transitions. [2023-11-12 02:32:17,923 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2802 states and 3697 transitions. [2023-11-12 02:32:17,960 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2802 to 2706. [2023-11-12 02:32:17,965 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2706 states, 2706 states have (on average 1.3218773096821876) internal successors, (3577), 2705 states have internal predecessors, (3577), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-12 02:32:17,972 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2706 states to 2706 states and 3577 transitions. [2023-11-12 02:32:17,972 INFO L240 hiAutomatonCegarLoop]: Abstraction has 2706 states and 3577 transitions. [2023-11-12 02:32:17,973 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-12 02:32:17,973 INFO L428 stractBuchiCegarLoop]: Abstraction has 2706 states and 3577 transitions. [2023-11-12 02:32:17,974 INFO L335 stractBuchiCegarLoop]: ======== Iteration 14 ============ [2023-11-12 02:32:17,974 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2706 states and 3577 transitions. [2023-11-12 02:32:17,985 INFO L131 ngComponentsAnalysis]: Automaton has 7 accepting balls. 2639 [2023-11-12 02:32:17,985 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-12 02:32:17,985 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-12 02:32:17,986 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-12 02:32:17,986 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-12 02:32:17,987 INFO L748 eck$LassoCheckResult]: Stem: 35688#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2; 35689#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~5#1;havoc main_~__retres1~5#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1; 35703#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret14#1, start_simulation_#t~ret15#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 35698#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 35672#L281 assume 1 == ~m_i~0;~m_st~0 := 0; 35673#L281-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 35479#L286-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 35480#L291-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 35714#L296-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 35451#L418 assume !(0 == ~M_E~0); 35452#L418-2 assume !(0 == ~T1_E~0); 35671#L423-1 assume !(0 == ~T2_E~0); 35720#L428-1 assume !(0 == ~T3_E~0); 35718#L433-1 assume !(0 == ~E_1~0); 35705#L438-1 assume !(0 == ~E_2~0); 35631#L443-1 assume !(0 == ~E_3~0); 35623#L448-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 35581#L197 assume !(1 == ~m_pc~0); 35582#L197-2 is_master_triggered_~__retres1~0#1 := 0; 35748#L208 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 35663#is_master_triggered_returnLabel#1 activate_threads_#t~ret9#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 35664#L510 assume !(0 != activate_threads_~tmp~1#1); 35426#L510-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 35427#L216 assume !(1 == ~t1_pc~0); 35477#L216-2 is_transmit1_triggered_~__retres1~1#1 := 0; 35478#L227 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 35507#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret10#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 35431#L518 assume !(0 != activate_threads_~tmp___0~0#1); 35432#L518-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 35640#L235 assume !(1 == ~t2_pc~0); 35713#L235-2 is_transmit2_triggered_~__retres1~2#1 := 0; 35569#L246 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 35570#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret11#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 35737#L526 assume !(0 != activate_threads_~tmp___1~0#1); 35738#L526-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 35554#L254 assume !(1 == ~t3_pc~0); 35484#L254-2 is_transmit3_triggered_~__retres1~3#1 := 0; 35485#L265 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 35441#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 35442#L534 assume !(0 != activate_threads_~tmp___2~0#1); 35563#L534-2 havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 35418#L461 assume !(1 == ~M_E~0); 35419#L461-2 assume !(1 == ~T1_E~0); 35481#L466-1 assume !(1 == ~T2_E~0); 35724#L471-1 assume !(1 == ~T3_E~0); 35510#L476-1 assume !(1 == ~E_1~0); 35511#L481-1 assume !(1 == ~E_2~0); 35656#L486-1 assume !(1 == ~E_3~0); 35529#L491-1 assume { :end_inline_reset_delta_events } true; 35530#L652-2 assume !false; 36492#L653 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 36493#L393-1 [2023-11-12 02:32:17,987 INFO L750 eck$LassoCheckResult]: Loop: 36493#L393-1 assume !false; 37541#L342 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 36484#L309 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 36482#L331 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 36481#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 36479#L346 assume 0 != eval_~tmp~0#1; 36476#L346-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;havoc eval_#t~nondet5#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet5#1;havoc eval_#t~nondet5#1; 36477#L354 assume !(0 != eval_~tmp_ndt_1~0#1); 36469#L354-2 havoc eval_~tmp_ndt_1~0#1; 36470#L351-1 assume !(0 == ~t1_st~0); 37546#L365-1 assume !(0 == ~t2_st~0); 37543#L379-1 assume !(0 == ~t3_st~0); 36493#L393-1 [2023-11-12 02:32:17,987 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-12 02:32:17,987 INFO L85 PathProgramCache]: Analyzing trace with hash -912926924, now seen corresponding path program 1 times [2023-11-12 02:32:17,988 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-12 02:32:17,988 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [309735152] [2023-11-12 02:32:17,988 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-12 02:32:17,988 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-12 02:32:17,996 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-12 02:32:17,996 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-12 02:32:18,001 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-12 02:32:18,024 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-12 02:32:18,025 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-12 02:32:18,025 INFO L85 PathProgramCache]: Analyzing trace with hash -1356345121, now seen corresponding path program 1 times [2023-11-12 02:32:18,025 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-12 02:32:18,025 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [787255497] [2023-11-12 02:32:18,025 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-12 02:32:18,026 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-12 02:32:18,029 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-12 02:32:18,029 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-12 02:32:18,031 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-12 02:32:18,032 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-12 02:32:18,033 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-12 02:32:18,033 INFO L85 PathProgramCache]: Analyzing trace with hash 1338864530, now seen corresponding path program 1 times [2023-11-12 02:32:18,033 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-12 02:32:18,034 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1953017570] [2023-11-12 02:32:18,034 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-12 02:32:18,034 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-12 02:32:18,042 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-12 02:32:18,066 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-12 02:32:18,066 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-12 02:32:18,066 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1953017570] [2023-11-12 02:32:18,066 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1953017570] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-12 02:32:18,066 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-12 02:32:18,067 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-12 02:32:18,067 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2017403605] [2023-11-12 02:32:18,067 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-12 02:32:18,144 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-12 02:32:18,144 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-12 02:32:18,144 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-12 02:32:18,144 INFO L87 Difference]: Start difference. First operand 2706 states and 3577 transitions. cyclomatic complexity: 878 Second operand has 3 states, 3 states have (on average 21.0) internal successors, (63), 3 states have internal predecessors, (63), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-12 02:32:18,202 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-12 02:32:18,202 INFO L93 Difference]: Finished difference Result 4937 states and 6433 transitions. [2023-11-12 02:32:18,203 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 4937 states and 6433 transitions. [2023-11-12 02:32:18,228 INFO L131 ngComponentsAnalysis]: Automaton has 11 accepting balls. 4591 [2023-11-12 02:32:18,254 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 4937 states to 4937 states and 6433 transitions. [2023-11-12 02:32:18,255 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 4937 [2023-11-12 02:32:18,260 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 4937 [2023-11-12 02:32:18,260 INFO L73 IsDeterministic]: Start isDeterministic. Operand 4937 states and 6433 transitions. [2023-11-12 02:32:18,268 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-12 02:32:18,268 INFO L218 hiAutomatonCegarLoop]: Abstraction has 4937 states and 6433 transitions. [2023-11-12 02:32:18,275 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 4937 states and 6433 transitions. [2023-11-12 02:32:18,343 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 4937 to 4833. [2023-11-12 02:32:18,353 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 4833 states, 4833 states have (on average 1.3049865507966067) internal successors, (6307), 4832 states have internal predecessors, (6307), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-12 02:32:18,365 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 4833 states to 4833 states and 6307 transitions. [2023-11-12 02:32:18,365 INFO L240 hiAutomatonCegarLoop]: Abstraction has 4833 states and 6307 transitions. [2023-11-12 02:32:18,365 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-12 02:32:18,366 INFO L428 stractBuchiCegarLoop]: Abstraction has 4833 states and 6307 transitions. [2023-11-12 02:32:18,366 INFO L335 stractBuchiCegarLoop]: ======== Iteration 15 ============ [2023-11-12 02:32:18,366 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 4833 states and 6307 transitions. [2023-11-12 02:32:18,384 INFO L131 ngComponentsAnalysis]: Automaton has 11 accepting balls. 4487 [2023-11-12 02:32:18,384 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-12 02:32:18,384 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-12 02:32:18,385 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-12 02:32:18,385 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-12 02:32:18,385 INFO L748 eck$LassoCheckResult]: Stem: 43362#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2; 43363#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~5#1;havoc main_~__retres1~5#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1; 43377#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret14#1, start_simulation_#t~ret15#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 43372#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 43344#L281 assume 1 == ~m_i~0;~m_st~0 := 0; 43345#L281-2 assume !(1 == ~t1_i~0);~t1_st~0 := 2; 43132#L286-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 43133#L291-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 43390#L296-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 43103#L418 assume !(0 == ~M_E~0); 43104#L418-2 assume !(0 == ~T1_E~0); 43343#L423-1 assume !(0 == ~T2_E~0); 43395#L428-1 assume !(0 == ~T3_E~0); 43392#L433-1 assume !(0 == ~E_1~0); 43380#L438-1 assume !(0 == ~E_2~0); 43293#L443-1 assume !(0 == ~E_3~0); 43283#L448-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 43237#L197 assume !(1 == ~m_pc~0); 43238#L197-2 is_master_triggered_~__retres1~0#1 := 0; 43421#L208 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 43333#is_master_triggered_returnLabel#1 activate_threads_#t~ret9#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 43334#L510 assume !(0 != activate_threads_~tmp~1#1); 43077#L510-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 43078#L216 assume !(1 == ~t1_pc~0); 43130#L216-2 is_transmit1_triggered_~__retres1~1#1 := 0; 43131#L227 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 43160#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret10#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 43082#L518 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 43083#L518-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 46349#L235 assume !(1 == ~t2_pc~0); 46347#L235-2 is_transmit2_triggered_~__retres1~2#1 := 0; 46346#L246 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 46345#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret11#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 46344#L526 assume !(0 != activate_threads_~tmp___1~0#1); 46343#L526-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 46342#L254 assume !(1 == ~t3_pc~0); 46341#L254-2 is_transmit3_triggered_~__retres1~3#1 := 0; 46340#L265 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 46339#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 46338#L534 assume !(0 != activate_threads_~tmp___2~0#1); 46337#L534-2 havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 46336#L461 assume !(1 == ~M_E~0); 46335#L461-2 assume !(1 == ~T1_E~0); 46334#L466-1 assume !(1 == ~T2_E~0); 46333#L471-1 assume !(1 == ~T3_E~0); 46332#L476-1 assume !(1 == ~E_1~0); 46330#L481-1 assume !(1 == ~E_2~0); 43324#L486-1 assume !(1 == ~E_3~0); 43180#L491-1 assume { :end_inline_reset_delta_events } true; 43181#L652-2 assume !false; 46313#L653 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 46309#L393-1 [2023-11-12 02:32:18,386 INFO L750 eck$LassoCheckResult]: Loop: 46309#L393-1 assume !false; 46305#L342 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 46299#L309 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 46294#L331 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 46290#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 46286#L346 assume 0 != eval_~tmp~0#1; 46276#L346-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;havoc eval_#t~nondet5#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet5#1;havoc eval_#t~nondet5#1; 46273#L354 assume !(0 != eval_~tmp_ndt_1~0#1); 46262#L354-2 havoc eval_~tmp_ndt_1~0#1; 45501#L351-1 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0#1;havoc eval_#t~nondet6#1;eval_~tmp_ndt_2~0#1 := eval_#t~nondet6#1;havoc eval_#t~nondet6#1; 43584#L368 assume !(0 != eval_~tmp_ndt_2~0#1); 43585#L368-2 havoc eval_~tmp_ndt_2~0#1; 46257#L365-1 assume !(0 == ~t2_st~0); 46256#L379-1 assume !(0 == ~t3_st~0); 46309#L393-1 [2023-11-12 02:32:18,386 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-12 02:32:18,386 INFO L85 PathProgramCache]: Analyzing trace with hash 1149359284, now seen corresponding path program 1 times [2023-11-12 02:32:18,386 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-12 02:32:18,387 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1271693832] [2023-11-12 02:32:18,387 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-12 02:32:18,387 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-12 02:32:18,393 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-12 02:32:18,440 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-12 02:32:18,440 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-12 02:32:18,440 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1271693832] [2023-11-12 02:32:18,440 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1271693832] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-12 02:32:18,440 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-12 02:32:18,441 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-12 02:32:18,441 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1009139777] [2023-11-12 02:32:18,441 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-12 02:32:18,441 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-12 02:32:18,441 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-12 02:32:18,442 INFO L85 PathProgramCache]: Analyzing trace with hash 2096165373, now seen corresponding path program 1 times [2023-11-12 02:32:18,442 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-12 02:32:18,442 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2147338426] [2023-11-12 02:32:18,442 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-12 02:32:18,442 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-12 02:32:18,446 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-12 02:32:18,446 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-12 02:32:18,448 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-12 02:32:18,450 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-12 02:32:18,534 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-12 02:32:18,535 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-12 02:32:18,535 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-12 02:32:18,535 INFO L87 Difference]: Start difference. First operand 4833 states and 6307 transitions. cyclomatic complexity: 1485 Second operand has 3 states, 3 states have (on average 17.0) internal successors, (51), 3 states have internal predecessors, (51), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-12 02:32:18,561 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-12 02:32:18,561 INFO L93 Difference]: Finished difference Result 3959 states and 5183 transitions. [2023-11-12 02:32:18,562 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 3959 states and 5183 transitions. [2023-11-12 02:32:18,585 INFO L131 ngComponentsAnalysis]: Automaton has 7 accepting balls. 3882 [2023-11-12 02:32:18,615 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 3959 states to 3959 states and 5183 transitions. [2023-11-12 02:32:18,615 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 3959 [2023-11-12 02:32:18,619 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 3959 [2023-11-12 02:32:18,620 INFO L73 IsDeterministic]: Start isDeterministic. Operand 3959 states and 5183 transitions. [2023-11-12 02:32:18,626 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-12 02:32:18,627 INFO L218 hiAutomatonCegarLoop]: Abstraction has 3959 states and 5183 transitions. [2023-11-12 02:32:18,632 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3959 states and 5183 transitions. [2023-11-12 02:32:18,706 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3959 to 3959. [2023-11-12 02:32:18,723 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 3959 states, 3959 states have (on average 1.3091689820661783) internal successors, (5183), 3958 states have internal predecessors, (5183), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-12 02:32:18,744 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3959 states to 3959 states and 5183 transitions. [2023-11-12 02:32:18,745 INFO L240 hiAutomatonCegarLoop]: Abstraction has 3959 states and 5183 transitions. [2023-11-12 02:32:18,745 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-12 02:32:18,746 INFO L428 stractBuchiCegarLoop]: Abstraction has 3959 states and 5183 transitions. [2023-11-12 02:32:18,746 INFO L335 stractBuchiCegarLoop]: ======== Iteration 16 ============ [2023-11-12 02:32:18,747 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 3959 states and 5183 transitions. [2023-11-12 02:32:18,765 INFO L131 ngComponentsAnalysis]: Automaton has 7 accepting balls. 3882 [2023-11-12 02:32:18,765 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-12 02:32:18,765 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-12 02:32:18,766 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-12 02:32:18,766 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-12 02:32:18,767 INFO L748 eck$LassoCheckResult]: Stem: 52144#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2; 52145#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~5#1;havoc main_~__retres1~5#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1; 52160#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret14#1, start_simulation_#t~ret15#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 52154#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 52129#L281 assume 1 == ~m_i~0;~m_st~0 := 0; 52130#L281-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 51928#L286-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 51929#L291-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 52172#L296-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 51901#L418 assume !(0 == ~M_E~0); 51902#L418-2 assume !(0 == ~T1_E~0); 52128#L423-1 assume !(0 == ~T2_E~0); 52177#L428-1 assume !(0 == ~T3_E~0); 52175#L433-1 assume !(0 == ~E_1~0); 52162#L438-1 assume !(0 == ~E_2~0); 52080#L443-1 assume !(0 == ~E_3~0); 52071#L448-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 52027#L197 assume !(1 == ~m_pc~0); 52028#L197-2 is_master_triggered_~__retres1~0#1 := 0; 52204#L208 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 52119#is_master_triggered_returnLabel#1 activate_threads_#t~ret9#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 52120#L510 assume !(0 != activate_threads_~tmp~1#1); 51875#L510-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 51876#L216 assume !(1 == ~t1_pc~0); 51926#L216-2 is_transmit1_triggered_~__retres1~1#1 := 0; 51927#L227 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 51956#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret10#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 51880#L518 assume !(0 != activate_threads_~tmp___0~0#1); 51881#L518-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 52089#L235 assume !(1 == ~t2_pc~0); 52171#L235-2 is_transmit2_triggered_~__retres1~2#1 := 0; 52016#L246 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 52017#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret11#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 52193#L526 assume !(0 != activate_threads_~tmp___1~0#1); 52194#L526-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 52000#L254 assume !(1 == ~t3_pc~0); 51933#L254-2 is_transmit3_triggered_~__retres1~3#1 := 0; 51934#L265 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 51890#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 51891#L534 assume !(0 != activate_threads_~tmp___2~0#1); 52009#L534-2 havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 51867#L461 assume !(1 == ~M_E~0); 51868#L461-2 assume !(1 == ~T1_E~0); 51930#L466-1 assume !(1 == ~T2_E~0); 52181#L471-1 assume !(1 == ~T3_E~0); 51959#L476-1 assume !(1 == ~E_1~0); 51960#L481-1 assume !(1 == ~E_2~0); 52105#L486-1 assume !(1 == ~E_3~0); 51978#L491-1 assume { :end_inline_reset_delta_events } true; 51979#L652-2 assume !false; 54100#L653 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 54062#L393-1 [2023-11-12 02:32:18,767 INFO L750 eck$LassoCheckResult]: Loop: 54062#L393-1 assume !false; 54096#L342 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 54093#L309 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 54091#L331 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 54089#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 54087#L346 assume 0 != eval_~tmp~0#1; 54085#L346-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;havoc eval_#t~nondet5#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet5#1;havoc eval_#t~nondet5#1; 54083#L354 assume !(0 != eval_~tmp_ndt_1~0#1); 54081#L354-2 havoc eval_~tmp_ndt_1~0#1; 52439#L351-1 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0#1;havoc eval_#t~nondet6#1;eval_~tmp_ndt_2~0#1 := eval_#t~nondet6#1;havoc eval_#t~nondet6#1; 52440#L368 assume !(0 != eval_~tmp_ndt_2~0#1); 54078#L368-2 havoc eval_~tmp_ndt_2~0#1; 54102#L365-1 assume !(0 == ~t2_st~0); 54061#L379-1 assume !(0 == ~t3_st~0); 54062#L393-1 [2023-11-12 02:32:18,767 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-12 02:32:18,768 INFO L85 PathProgramCache]: Analyzing trace with hash -912926924, now seen corresponding path program 2 times [2023-11-12 02:32:18,768 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-12 02:32:18,768 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [383244019] [2023-11-12 02:32:18,768 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-12 02:32:18,768 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-12 02:32:18,779 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-12 02:32:18,780 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-12 02:32:18,786 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-12 02:32:18,804 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-12 02:32:18,804 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-12 02:32:18,804 INFO L85 PathProgramCache]: Analyzing trace with hash 2096165373, now seen corresponding path program 2 times [2023-11-12 02:32:18,805 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-12 02:32:18,805 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1545058983] [2023-11-12 02:32:18,805 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-12 02:32:18,805 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-12 02:32:18,808 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-12 02:32:18,809 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-12 02:32:18,811 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-12 02:32:18,812 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-12 02:32:18,813 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-12 02:32:18,813 INFO L85 PathProgramCache]: Analyzing trace with hash -1967606800, now seen corresponding path program 1 times [2023-11-12 02:32:18,813 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-12 02:32:18,814 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [287062420] [2023-11-12 02:32:18,814 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-12 02:32:18,814 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-12 02:32:18,829 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-12 02:32:18,857 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-12 02:32:18,857 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-12 02:32:18,858 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [287062420] [2023-11-12 02:32:18,858 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [287062420] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-12 02:32:18,858 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-12 02:32:18,858 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-12 02:32:18,858 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [4533752] [2023-11-12 02:32:18,858 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-12 02:32:18,932 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-12 02:32:18,933 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-12 02:32:18,933 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-12 02:32:18,934 INFO L87 Difference]: Start difference. First operand 3959 states and 5183 transitions. cyclomatic complexity: 1231 Second operand has 3 states, 3 states have (on average 21.666666666666668) internal successors, (65), 3 states have internal predecessors, (65), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-12 02:32:19,001 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-12 02:32:19,001 INFO L93 Difference]: Finished difference Result 6753 states and 8769 transitions. [2023-11-12 02:32:19,001 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 6753 states and 8769 transitions. [2023-11-12 02:32:19,039 INFO L131 ngComponentsAnalysis]: Automaton has 7 accepting balls. 6651 [2023-11-12 02:32:19,097 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 6753 states to 6753 states and 8769 transitions. [2023-11-12 02:32:19,098 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 6753 [2023-11-12 02:32:19,105 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 6753 [2023-11-12 02:32:19,105 INFO L73 IsDeterministic]: Start isDeterministic. Operand 6753 states and 8769 transitions. [2023-11-12 02:32:19,113 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-12 02:32:19,113 INFO L218 hiAutomatonCegarLoop]: Abstraction has 6753 states and 8769 transitions. [2023-11-12 02:32:19,122 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 6753 states and 8769 transitions. [2023-11-12 02:32:19,190 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 6753 to 6443. [2023-11-12 02:32:19,200 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 6443 states, 6443 states have (on average 1.3051373583734285) internal successors, (8409), 6442 states have internal predecessors, (8409), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-12 02:32:19,216 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 6443 states to 6443 states and 8409 transitions. [2023-11-12 02:32:19,217 INFO L240 hiAutomatonCegarLoop]: Abstraction has 6443 states and 8409 transitions. [2023-11-12 02:32:19,221 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-12 02:32:19,222 INFO L428 stractBuchiCegarLoop]: Abstraction has 6443 states and 8409 transitions. [2023-11-12 02:32:19,222 INFO L335 stractBuchiCegarLoop]: ======== Iteration 17 ============ [2023-11-12 02:32:19,223 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 6443 states and 8409 transitions. [2023-11-12 02:32:19,246 INFO L131 ngComponentsAnalysis]: Automaton has 7 accepting balls. 6341 [2023-11-12 02:32:19,246 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-12 02:32:19,246 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-12 02:32:19,247 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-12 02:32:19,247 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-12 02:32:19,247 INFO L748 eck$LassoCheckResult]: Stem: 62874#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2; 62875#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~5#1;havoc main_~__retres1~5#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1; 62896#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret14#1, start_simulation_#t~ret15#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 62889#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 62857#L281 assume 1 == ~m_i~0;~m_st~0 := 0; 62858#L281-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 62648#L286-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 62649#L291-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 62912#L296-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 62615#L418 assume !(0 == ~M_E~0); 62616#L418-2 assume !(0 == ~T1_E~0); 62856#L423-1 assume !(0 == ~T2_E~0); 62919#L428-1 assume !(0 == ~T3_E~0); 62917#L433-1 assume !(0 == ~E_1~0); 62901#L438-1 assume !(0 == ~E_2~0); 62805#L443-1 assume !(0 == ~E_3~0); 62796#L448-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 62749#L197 assume !(1 == ~m_pc~0); 62750#L197-2 is_master_triggered_~__retres1~0#1 := 0; 62957#L208 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 62847#is_master_triggered_returnLabel#1 activate_threads_#t~ret9#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 62848#L510 assume !(0 != activate_threads_~tmp~1#1); 62595#L510-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 62596#L216 assume !(1 == ~t1_pc~0); 62644#L216-2 is_transmit1_triggered_~__retres1~1#1 := 0; 62645#L227 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 62677#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret10#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 62597#L518 assume !(0 != activate_threads_~tmp___0~0#1); 62598#L518-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 62814#L235 assume !(1 == ~t2_pc~0); 62908#L235-2 is_transmit2_triggered_~__retres1~2#1 := 0; 62736#L246 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 62737#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret11#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 62942#L526 assume !(0 != activate_threads_~tmp___1~0#1); 62943#L526-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 62719#L254 assume !(1 == ~t3_pc~0); 62653#L254-2 is_transmit3_triggered_~__retres1~3#1 := 0; 62654#L265 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 62607#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 62608#L534 assume !(0 != activate_threads_~tmp___2~0#1); 62730#L534-2 havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 62587#L461 assume !(1 == ~M_E~0); 62588#L461-2 assume !(1 == ~T1_E~0); 62650#L466-1 assume !(1 == ~T2_E~0); 62928#L471-1 assume !(1 == ~T3_E~0); 62678#L476-1 assume !(1 == ~E_1~0); 62679#L481-1 assume !(1 == ~E_2~0); 62833#L486-1 assume !(1 == ~E_3~0); 62694#L491-1 assume { :end_inline_reset_delta_events } true; 62695#L652-2 assume !false; 64155#L653 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 64150#L393-1 [2023-11-12 02:32:19,248 INFO L750 eck$LassoCheckResult]: Loop: 64150#L393-1 assume !false; 64144#L342 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 64065#L309 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 64061#L331 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 64038#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 64034#L346 assume 0 != eval_~tmp~0#1; 64028#L346-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;havoc eval_#t~nondet5#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet5#1;havoc eval_#t~nondet5#1; 64006#L354 assume !(0 != eval_~tmp_ndt_1~0#1); 63975#L354-2 havoc eval_~tmp_ndt_1~0#1; 63719#L351-1 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0#1;havoc eval_#t~nondet6#1;eval_~tmp_ndt_2~0#1 := eval_#t~nondet6#1;havoc eval_#t~nondet6#1; 63633#L368 assume !(0 != eval_~tmp_ndt_2~0#1); 63634#L368-2 havoc eval_~tmp_ndt_2~0#1; 64246#L365-1 assume 0 == ~t2_st~0;havoc eval_~tmp_ndt_3~0#1;havoc eval_#t~nondet7#1;eval_~tmp_ndt_3~0#1 := eval_#t~nondet7#1;havoc eval_#t~nondet7#1; 63746#L382 assume !(0 != eval_~tmp_ndt_3~0#1); 64176#L382-2 havoc eval_~tmp_ndt_3~0#1; 64157#L379-1 assume !(0 == ~t3_st~0); 64150#L393-1 [2023-11-12 02:32:19,248 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-12 02:32:19,249 INFO L85 PathProgramCache]: Analyzing trace with hash -912926924, now seen corresponding path program 3 times [2023-11-12 02:32:19,249 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-12 02:32:19,249 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1208980277] [2023-11-12 02:32:19,249 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-12 02:32:19,249 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-12 02:32:19,257 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-12 02:32:19,257 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-12 02:32:19,263 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-12 02:32:19,269 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-12 02:32:19,270 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-12 02:32:19,270 INFO L85 PathProgramCache]: Analyzing trace with hash 71302111, now seen corresponding path program 1 times [2023-11-12 02:32:19,270 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-12 02:32:19,270 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1644680624] [2023-11-12 02:32:19,271 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-12 02:32:19,271 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-12 02:32:19,276 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-12 02:32:19,276 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-12 02:32:19,279 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-12 02:32:19,281 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-12 02:32:19,282 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-12 02:32:19,282 INFO L85 PathProgramCache]: Analyzing trace with hash -1088484078, now seen corresponding path program 1 times [2023-11-12 02:32:19,282 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-12 02:32:19,282 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1204159300] [2023-11-12 02:32:19,282 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-12 02:32:19,283 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-12 02:32:19,291 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-12 02:32:19,318 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-12 02:32:19,318 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-12 02:32:19,319 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1204159300] [2023-11-12 02:32:19,319 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1204159300] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-12 02:32:19,319 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-12 02:32:19,319 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2023-11-12 02:32:19,319 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1148826429] [2023-11-12 02:32:19,319 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-12 02:32:19,400 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-12 02:32:19,401 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-12 02:32:19,401 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-12 02:32:19,401 INFO L87 Difference]: Start difference. First operand 6443 states and 8409 transitions. cyclomatic complexity: 1973 Second operand has 3 states, 2 states have (on average 33.5) internal successors, (67), 3 states have internal predecessors, (67), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-12 02:32:19,478 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-12 02:32:19,478 INFO L93 Difference]: Finished difference Result 10148 states and 13230 transitions. [2023-11-12 02:32:19,478 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 10148 states and 13230 transitions. [2023-11-12 02:32:19,520 INFO L131 ngComponentsAnalysis]: Automaton has 7 accepting balls. 10026 [2023-11-12 02:32:19,608 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 10148 states to 10148 states and 13230 transitions. [2023-11-12 02:32:19,608 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 10148 [2023-11-12 02:32:19,617 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 10148 [2023-11-12 02:32:19,618 INFO L73 IsDeterministic]: Start isDeterministic. Operand 10148 states and 13230 transitions. [2023-11-12 02:32:19,625 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-12 02:32:19,625 INFO L218 hiAutomatonCegarLoop]: Abstraction has 10148 states and 13230 transitions. [2023-11-12 02:32:19,637 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 10148 states and 13230 transitions. [2023-11-12 02:32:19,736 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 10148 to 10148. [2023-11-12 02:32:19,752 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 10148 states, 10148 states have (on average 1.3037051635790304) internal successors, (13230), 10147 states have internal predecessors, (13230), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-12 02:32:19,778 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 10148 states to 10148 states and 13230 transitions. [2023-11-12 02:32:19,778 INFO L240 hiAutomatonCegarLoop]: Abstraction has 10148 states and 13230 transitions. [2023-11-12 02:32:19,779 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-12 02:32:19,779 INFO L428 stractBuchiCegarLoop]: Abstraction has 10148 states and 13230 transitions. [2023-11-12 02:32:19,779 INFO L335 stractBuchiCegarLoop]: ======== Iteration 18 ============ [2023-11-12 02:32:19,779 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 10148 states and 13230 transitions. [2023-11-12 02:32:19,811 INFO L131 ngComponentsAnalysis]: Automaton has 7 accepting balls. 10026 [2023-11-12 02:32:19,811 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-12 02:32:19,812 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-12 02:32:19,812 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-12 02:32:19,812 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-12 02:32:19,813 INFO L748 eck$LassoCheckResult]: Stem: 79473#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2; 79474#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~5#1;havoc main_~__retres1~5#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1; 79493#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret14#1, start_simulation_#t~ret15#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 79488#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 79457#L281 assume 1 == ~m_i~0;~m_st~0 := 0; 79458#L281-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 79246#L286-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 79247#L291-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 79506#L296-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 79214#L418 assume !(0 == ~M_E~0); 79215#L418-2 assume !(0 == ~T1_E~0); 79456#L423-1 assume !(0 == ~T2_E~0); 79513#L428-1 assume !(0 == ~T3_E~0); 79511#L433-1 assume !(0 == ~E_1~0); 79496#L438-1 assume !(0 == ~E_2~0); 79397#L443-1 assume !(0 == ~E_3~0); 79389#L448-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 79344#L197 assume !(1 == ~m_pc~0); 79345#L197-2 is_master_triggered_~__retres1~0#1 := 0; 79548#L208 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 79447#is_master_triggered_returnLabel#1 activate_threads_#t~ret9#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 79448#L510 assume !(0 != activate_threads_~tmp~1#1); 79194#L510-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 79195#L216 assume !(1 == ~t1_pc~0); 79242#L216-2 is_transmit1_triggered_~__retres1~1#1 := 0; 79243#L227 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 79273#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret10#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 79196#L518 assume !(0 != activate_threads_~tmp___0~0#1); 79197#L518-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 79409#L235 assume !(1 == ~t2_pc~0); 79502#L235-2 is_transmit2_triggered_~__retres1~2#1 := 0; 79332#L246 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 79333#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret11#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 79537#L526 assume !(0 != activate_threads_~tmp___1~0#1); 79538#L526-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 79314#L254 assume !(1 == ~t3_pc~0); 79251#L254-2 is_transmit3_triggered_~__retres1~3#1 := 0; 79252#L265 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 79206#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 79207#L534 assume !(0 != activate_threads_~tmp___2~0#1); 79326#L534-2 havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 79186#L461 assume !(1 == ~M_E~0); 79187#L461-2 assume !(1 == ~T1_E~0); 79248#L466-1 assume !(1 == ~T2_E~0); 79519#L471-1 assume !(1 == ~T3_E~0); 79274#L476-1 assume !(1 == ~E_1~0); 79275#L481-1 assume !(1 == ~E_2~0); 79432#L486-1 assume !(1 == ~E_3~0); 79290#L491-1 assume { :end_inline_reset_delta_events } true; 79291#L652-2 assume !false; 88767#L653 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 88766#L393-1 [2023-11-12 02:32:19,813 INFO L750 eck$LassoCheckResult]: Loop: 88766#L393-1 assume !false; 88765#L342 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 88762#L309 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 88760#L331 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 88759#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 88757#L346 assume 0 != eval_~tmp~0#1; 88756#L346-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;havoc eval_#t~nondet5#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet5#1;havoc eval_#t~nondet5#1; 88753#L354 assume !(0 != eval_~tmp_ndt_1~0#1); 88749#L354-2 havoc eval_~tmp_ndt_1~0#1; 84850#L351-1 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0#1;havoc eval_#t~nondet6#1;eval_~tmp_ndt_2~0#1 := eval_#t~nondet6#1;havoc eval_#t~nondet6#1; 84797#L368 assume !(0 != eval_~tmp_ndt_2~0#1); 84798#L368-2 havoc eval_~tmp_ndt_2~0#1; 84537#L365-1 assume 0 == ~t2_st~0;havoc eval_~tmp_ndt_3~0#1;havoc eval_#t~nondet7#1;eval_~tmp_ndt_3~0#1 := eval_#t~nondet7#1;havoc eval_#t~nondet7#1; 84538#L382 assume !(0 != eval_~tmp_ndt_3~0#1); 84530#L382-2 havoc eval_~tmp_ndt_3~0#1; 84531#L379-1 assume 0 == ~t3_st~0;havoc eval_~tmp_ndt_4~0#1;havoc eval_#t~nondet8#1;eval_~tmp_ndt_4~0#1 := eval_#t~nondet8#1;havoc eval_#t~nondet8#1; 88769#L396 assume !(0 != eval_~tmp_ndt_4~0#1); 88768#L396-2 havoc eval_~tmp_ndt_4~0#1; 88766#L393-1 [2023-11-12 02:32:19,813 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-12 02:32:19,814 INFO L85 PathProgramCache]: Analyzing trace with hash -912926924, now seen corresponding path program 4 times [2023-11-12 02:32:19,814 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-12 02:32:19,814 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1706044785] [2023-11-12 02:32:19,878 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-12 02:32:19,878 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-12 02:32:19,885 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-12 02:32:19,885 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-12 02:32:19,890 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-12 02:32:19,897 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-12 02:32:19,897 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-12 02:32:19,898 INFO L85 PathProgramCache]: Analyzing trace with hash -198166090, now seen corresponding path program 1 times [2023-11-12 02:32:19,898 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-12 02:32:19,898 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [999274375] [2023-11-12 02:32:19,898 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-12 02:32:19,898 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-12 02:32:19,901 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-12 02:32:19,902 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-12 02:32:19,903 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-12 02:32:19,905 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-12 02:32:19,906 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-12 02:32:19,906 INFO L85 PathProgramCache]: Analyzing trace with hash 1938803241, now seen corresponding path program 1 times [2023-11-12 02:32:19,906 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-12 02:32:19,906 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1649760884] [2023-11-12 02:32:19,906 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-12 02:32:19,907 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-12 02:32:19,915 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-12 02:32:19,915 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-12 02:32:19,920 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-12 02:32:19,929 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-12 02:32:21,062 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-12 02:32:21,062 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-12 02:32:21,080 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-12 02:32:21,216 INFO L201 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer CFG 12.11 02:32:21 BoogieIcfgContainer [2023-11-12 02:32:21,221 INFO L131 PluginConnector]: ------------------------ END BuchiAutomizer---------------------------- [2023-11-12 02:32:21,222 INFO L112 PluginConnector]: ------------------------Witness Printer---------------------------- [2023-11-12 02:32:21,222 INFO L270 PluginConnector]: Initializing Witness Printer... [2023-11-12 02:32:21,222 INFO L274 PluginConnector]: Witness Printer initialized [2023-11-12 02:32:21,223 INFO L184 PluginConnector]: Executing the observer RCFGCatcher from plugin Witness Printer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 12.11 02:32:13" (3/4) ... [2023-11-12 02:32:21,224 INFO L134 WitnessPrinter]: Generating witness for non-termination counterexample [2023-11-12 02:32:21,330 INFO L149 WitnessManager]: Wrote witness to /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_215f6841-0d75-460b-aa2b-6df37e285065/bin/uautomizer-verify-uTZkv6EMXl/witness.graphml [2023-11-12 02:32:21,330 INFO L131 PluginConnector]: ------------------------ END Witness Printer---------------------------- [2023-11-12 02:32:21,331 INFO L158 Benchmark]: Toolchain (without parser) took 9629.76ms. Allocated memory was 119.5MB in the beginning and 415.2MB in the end (delta: 295.7MB). Free memory was 74.6MB in the beginning and 222.6MB in the end (delta: -148.0MB). Peak memory consumption was 149.0MB. Max. memory is 16.1GB. [2023-11-12 02:32:21,331 INFO L158 Benchmark]: CDTParser took 0.74ms. Allocated memory is still 119.5MB. Free memory is still 94.5MB. There was no memory consumed. Max. memory is 16.1GB. [2023-11-12 02:32:21,332 INFO L158 Benchmark]: CACSL2BoogieTranslator took 381.21ms. Allocated memory is still 119.5MB. Free memory was 74.4MB in the beginning and 60.2MB in the end (delta: 14.2MB). Peak memory consumption was 14.7MB. Max. memory is 16.1GB. [2023-11-12 02:32:21,332 INFO L158 Benchmark]: Boogie Procedure Inliner took 80.21ms. Allocated memory is still 119.5MB. Free memory was 60.0MB in the beginning and 56.6MB in the end (delta: 3.3MB). Peak memory consumption was 4.2MB. Max. memory is 16.1GB. [2023-11-12 02:32:21,333 INFO L158 Benchmark]: Boogie Preprocessor took 59.03ms. Allocated memory is still 119.5MB. Free memory was 56.6MB in the beginning and 53.7MB in the end (delta: 3.0MB). Peak memory consumption was 2.1MB. Max. memory is 16.1GB. [2023-11-12 02:32:21,333 INFO L158 Benchmark]: RCFGBuilder took 1155.98ms. Allocated memory was 119.5MB in the beginning and 153.1MB in the end (delta: 33.6MB). Free memory was 53.7MB in the beginning and 102.2MB in the end (delta: -48.6MB). Peak memory consumption was 25.3MB. Max. memory is 16.1GB. [2023-11-12 02:32:21,334 INFO L158 Benchmark]: BuchiAutomizer took 7838.10ms. Allocated memory was 153.1MB in the beginning and 415.2MB in the end (delta: 262.1MB). Free memory was 102.2MB in the beginning and 228.9MB in the end (delta: -126.7MB). Peak memory consumption was 134.2MB. Max. memory is 16.1GB. [2023-11-12 02:32:21,334 INFO L158 Benchmark]: Witness Printer took 108.68ms. Allocated memory is still 415.2MB. Free memory was 227.9MB in the beginning and 222.6MB in the end (delta: 5.2MB). Peak memory consumption was 4.2MB. Max. memory is 16.1GB. [2023-11-12 02:32:21,336 INFO L338 ainManager$Toolchain]: ####################### End [Toolchain 1] ####################### --- Results --- * Results from de.uni_freiburg.informatik.ultimate.core: - StatisticsResult: Toolchain Benchmarks Benchmark results are: * CDTParser took 0.74ms. Allocated memory is still 119.5MB. Free memory is still 94.5MB. There was no memory consumed. Max. memory is 16.1GB. * CACSL2BoogieTranslator took 381.21ms. Allocated memory is still 119.5MB. Free memory was 74.4MB in the beginning and 60.2MB in the end (delta: 14.2MB). Peak memory consumption was 14.7MB. Max. memory is 16.1GB. * Boogie Procedure Inliner took 80.21ms. Allocated memory is still 119.5MB. Free memory was 60.0MB in the beginning and 56.6MB in the end (delta: 3.3MB). Peak memory consumption was 4.2MB. Max. memory is 16.1GB. * Boogie Preprocessor took 59.03ms. Allocated memory is still 119.5MB. Free memory was 56.6MB in the beginning and 53.7MB in the end (delta: 3.0MB). Peak memory consumption was 2.1MB. Max. memory is 16.1GB. * RCFGBuilder took 1155.98ms. Allocated memory was 119.5MB in the beginning and 153.1MB in the end (delta: 33.6MB). Free memory was 53.7MB in the beginning and 102.2MB in the end (delta: -48.6MB). Peak memory consumption was 25.3MB. Max. memory is 16.1GB. * BuchiAutomizer took 7838.10ms. Allocated memory was 153.1MB in the beginning and 415.2MB in the end (delta: 262.1MB). Free memory was 102.2MB in the beginning and 228.9MB in the end (delta: -126.7MB). Peak memory consumption was 134.2MB. Max. memory is 16.1GB. * Witness Printer took 108.68ms. Allocated memory is still 415.2MB. Free memory was 227.9MB in the beginning and 222.6MB in the end (delta: 5.2MB). Peak memory consumption was 4.2MB. Max. memory is 16.1GB. * Results from de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction: - StatisticsResult: Constructed decomposition of program Your program was decomposed into 17 terminating modules (17 trivial, 0 deterministic, 0 nondeterministic) and one nonterminating remainder module.17 modules have a trivial ranking function, the largest among these consists of 5 locations. The remainder module has 10148 locations. - StatisticsResult: Timing statistics BüchiAutomizer plugin needed 7.6s and 18 iterations. TraceHistogramMax:1. Analysis of lassos took 3.9s. Construction of modules took 0.5s. Büchi inclusion checks took 2.6s. Highest rank in rank-based complementation 0. Minimization of det autom 17. Minimization of nondet autom 0. Automata minimization 1.0s AutomataMinimizationTime, 17 MinimizatonAttempts, 3991 StatesRemovedByMinimization, 9 NontrivialMinimizations. Non-live state removal took 0.6s Buchi closure took 0.0s. Biggest automaton had -1 states and ocurred in iteration -1. Nontrivial modules had stage [0, 0, 0, 0, 0]. InterpolantCoveringCapabilityFinite: 0/0 InterpolantCoveringCapabilityBuchi: 0/0 HoareTripleCheckerStatistics: 0 mSolverCounterUnknown, 8323 SdHoareTripleChecker+Valid, 0.7s IncrementalHoareTripleChecker+Time, 0 mSdLazyCounter, 8323 mSDsluCounter, 14456 SdHoareTripleChecker+Invalid, 0.6s Time, 0 mProtectedAction, 0 SdHoareTripleChecker+Unchecked, 0 IncrementalHoareTripleChecker+Unchecked, 6635 mSDsCounter, 185 IncrementalHoareTripleChecker+Valid, 0 mProtectedPredicate, 448 IncrementalHoareTripleChecker+Invalid, 633 SdHoareTripleChecker+Unknown, 0 mSolverCounterNotChecked, 185 mSolverCounterUnsat, 7821 mSDtfsCounter, 448 mSolverCounterSat, 0.1s SdHoareTripleChecker+Time, 0 IncrementalHoareTripleChecker+Unknown LassoAnalysisResults: nont1 unkn0 SFLI3 SFLT0 conc3 concLT0 SILN1 SILU0 SILI10 SILT0 lasso0 LassoPreprocessingBenchmarks: LassoTerminationAnalysisBenchmarks: not availableLassoTerminationAnalysisBenchmarks: LassoNonterminationAnalysisSatFixpoint: 0 LassoNonterminationAnalysisSatUnbounded: 0 LassoNonterminationAnalysisUnsat: 0 LassoNonterminationAnalysisUnknown: 0 LassoNonterminationAnalysisTime: 0.0s InitialAbstractionConstructionTime: 0.0s - TerminationAnalysisResult: Nontermination possible Buchi Automizer proved that your program is nonterminating for some inputs - LassoShapedNonTerminationArgument [Line: 341]: Nontermination argument in form of an infinite program execution. Nontermination argument in form of an infinite program execution. Stem: [L25] int m_pc = 0; [L26] int t1_pc = 0; [L27] int t2_pc = 0; [L28] int t3_pc = 0; [L29] int m_st ; [L30] int t1_st ; [L31] int t2_st ; [L32] int t3_st ; [L33] int m_i ; [L34] int t1_i ; [L35] int t2_i ; [L36] int t3_i ; [L37] int M_E = 2; [L38] int T1_E = 2; [L39] int T2_E = 2; [L40] int T3_E = 2; [L41] int E_1 = 2; [L42] int E_2 = 2; [L43] int E_3 = 2; VAL [E_1=2, E_2=2, E_3=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, m_i=0, m_pc=0, m_st=0, t1_i=0, t1_pc=0, t1_st=0, t2_i=0, t2_pc=0, t2_st=0, t3_i=0, t3_pc=0, t3_st=0] [L697] int __retres1 ; [L701] CALL init_model() [L610] m_i = 1 [L611] t1_i = 1 [L612] t2_i = 1 [L613] t3_i = 1 VAL [E_1=2, E_2=2, E_3=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0] [L701] RET init_model() [L702] CALL start_simulation() [L638] int kernel_st ; [L639] int tmp ; [L640] int tmp___0 ; [L644] kernel_st = 0 [L645] FCALL update_channels() [L646] CALL init_threads() [L281] COND TRUE m_i == 1 [L282] m_st = 0 VAL [E_1=2, E_2=2, E_3=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0] [L286] COND TRUE t1_i == 1 [L287] t1_st = 0 VAL [E_1=2, E_2=2, E_3=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0] [L291] COND TRUE t2_i == 1 [L292] t2_st = 0 VAL [E_1=2, E_2=2, E_3=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0] [L296] COND TRUE t3_i == 1 [L297] t3_st = 0 VAL [E_1=2, E_2=2, E_3=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0] [L646] RET init_threads() [L647] CALL fire_delta_events() [L418] COND FALSE !(M_E == 0) VAL [E_1=2, E_2=2, E_3=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0] [L423] COND FALSE !(T1_E == 0) VAL [E_1=2, E_2=2, E_3=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0] [L428] COND FALSE !(T2_E == 0) VAL [E_1=2, E_2=2, E_3=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0] [L433] COND FALSE !(T3_E == 0) VAL [E_1=2, E_2=2, E_3=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0] [L438] COND FALSE !(E_1 == 0) VAL [E_1=2, E_2=2, E_3=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0] [L443] COND FALSE !(E_2 == 0) VAL [E_1=2, E_2=2, E_3=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0] [L448] COND FALSE !(E_3 == 0) VAL [E_1=2, E_2=2, E_3=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0] [L647] RET fire_delta_events() [L648] CALL activate_threads() [L501] int tmp ; [L502] int tmp___0 ; [L503] int tmp___1 ; [L504] int tmp___2 ; [L508] CALL, EXPR is_master_triggered() [L194] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0] [L197] COND FALSE !(m_pc == 1) VAL [E_1=2, E_2=2, E_3=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0] [L207] __retres1 = 0 VAL [E_1=2, E_2=2, E_3=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, __retres1=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0] [L209] return (__retres1); VAL [E_1=2, E_2=2, E_3=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, \result=0, __retres1=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0] [L508] RET, EXPR is_master_triggered() [L508] tmp = is_master_triggered() [L510] COND FALSE !(\read(tmp)) VAL [E_1=2, E_2=2, E_3=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, tmp=0] [L516] CALL, EXPR is_transmit1_triggered() [L213] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0] [L216] COND FALSE !(t1_pc == 1) VAL [E_1=2, E_2=2, E_3=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0] [L226] __retres1 = 0 VAL [E_1=2, E_2=2, E_3=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, __retres1=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0] [L228] return (__retres1); VAL [E_1=2, E_2=2, E_3=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, \result=0, __retres1=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0] [L516] RET, EXPR is_transmit1_triggered() [L516] tmp___0 = is_transmit1_triggered() [L518] COND FALSE !(\read(tmp___0)) VAL [E_1=2, E_2=2, E_3=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, tmp=0, tmp___0=0] [L524] CALL, EXPR is_transmit2_triggered() [L232] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0] [L235] COND FALSE !(t2_pc == 1) VAL [E_1=2, E_2=2, E_3=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0] [L245] __retres1 = 0 VAL [E_1=2, E_2=2, E_3=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, __retres1=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0] [L247] return (__retres1); VAL [E_1=2, E_2=2, E_3=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, \result=0, __retres1=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0] [L524] RET, EXPR is_transmit2_triggered() [L524] tmp___1 = is_transmit2_triggered() [L526] COND FALSE !(\read(tmp___1)) VAL [E_1=2, E_2=2, E_3=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, tmp=0, tmp___0=0, tmp___1=0] [L532] CALL, EXPR is_transmit3_triggered() [L251] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0] [L254] COND FALSE !(t3_pc == 1) VAL [E_1=2, E_2=2, E_3=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0] [L264] __retres1 = 0 VAL [E_1=2, E_2=2, E_3=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, __retres1=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0] [L266] return (__retres1); VAL [E_1=2, E_2=2, E_3=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, \result=0, __retres1=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0] [L532] RET, EXPR is_transmit3_triggered() [L532] tmp___2 = is_transmit3_triggered() [L534] COND FALSE !(\read(tmp___2)) VAL [E_1=2, E_2=2, E_3=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, tmp=0, tmp___0=0, tmp___1=0, tmp___2=0] [L648] RET activate_threads() [L649] CALL reset_delta_events() [L461] COND FALSE !(M_E == 1) VAL [E_1=2, E_2=2, E_3=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0] [L466] COND FALSE !(T1_E == 1) VAL [E_1=2, E_2=2, E_3=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0] [L471] COND FALSE !(T2_E == 1) VAL [E_1=2, E_2=2, E_3=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0] [L476] COND FALSE !(T3_E == 1) VAL [E_1=2, E_2=2, E_3=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0] [L481] COND FALSE !(E_1 == 1) VAL [E_1=2, E_2=2, E_3=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0] [L486] COND FALSE !(E_2 == 1) VAL [E_1=2, E_2=2, E_3=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0] [L491] COND FALSE !(E_3 == 1) VAL [E_1=2, E_2=2, E_3=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0] [L649] RET reset_delta_events() [L652] COND TRUE 1 VAL [E_1=2, E_2=2, E_3=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, kernel_st=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0] [L655] kernel_st = 1 [L656] CALL eval() [L337] int tmp ; VAL [E_1=2, E_2=2, E_3=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0] Loop: [L341] COND TRUE 1 [L344] CALL, EXPR exists_runnable_thread() [L306] int __retres1 ; [L309] COND TRUE m_st == 0 [L310] __retres1 = 1 [L332] return (__retres1); [L344] RET, EXPR exists_runnable_thread() [L344] tmp = exists_runnable_thread() [L346] COND TRUE \read(tmp) [L351] COND TRUE m_st == 0 [L352] int tmp_ndt_1; [L353] EXPR tmp_ndt_1 = __VERIFIER_nondet_int() [L354] COND FALSE, EXPR !(\read(tmp_ndt_1)) [L351-L362] { int tmp_ndt_1; tmp_ndt_1 = __VERIFIER_nondet_int(); if (tmp_ndt_1) { { m_st = 1; master(); } } else { } } [L365] COND TRUE t1_st == 0 [L366] int tmp_ndt_2; [L367] EXPR tmp_ndt_2 = __VERIFIER_nondet_int() [L368] COND FALSE, EXPR !(\read(tmp_ndt_2)) [L365-L376] { int tmp_ndt_2; tmp_ndt_2 = __VERIFIER_nondet_int(); if (tmp_ndt_2) { { t1_st = 1; transmit1(); } } else { } } [L379] COND TRUE t2_st == 0 [L380] int tmp_ndt_3; [L381] EXPR tmp_ndt_3 = __VERIFIER_nondet_int() [L382] COND FALSE, EXPR !(\read(tmp_ndt_3)) [L379-L390] { int tmp_ndt_3; tmp_ndt_3 = __VERIFIER_nondet_int(); if (tmp_ndt_3) { { t2_st = 1; transmit2(); } } else { } } [L393] COND TRUE t3_st == 0 [L394] int tmp_ndt_4; [L395] EXPR tmp_ndt_4 = __VERIFIER_nondet_int() [L396] COND FALSE, EXPR !(\read(tmp_ndt_4)) [L393-L404] { int tmp_ndt_4; tmp_ndt_4 = __VERIFIER_nondet_int(); if (tmp_ndt_4) { { t3_st = 1; transmit3(); } } else { } } End of lasso representation. - StatisticsResult: NonterminationArgumentStatistics Fixpoint - NonterminatingLassoResult [Line: 341]: Nonterminating execution Found a nonterminating execution for the following lasso shaped sequence of statements. Stem: [L25] int m_pc = 0; [L26] int t1_pc = 0; [L27] int t2_pc = 0; [L28] int t3_pc = 0; [L29] int m_st ; [L30] int t1_st ; [L31] int t2_st ; [L32] int t3_st ; [L33] int m_i ; [L34] int t1_i ; [L35] int t2_i ; [L36] int t3_i ; [L37] int M_E = 2; [L38] int T1_E = 2; [L39] int T2_E = 2; [L40] int T3_E = 2; [L41] int E_1 = 2; [L42] int E_2 = 2; [L43] int E_3 = 2; VAL [E_1=2, E_2=2, E_3=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, m_i=0, m_pc=0, m_st=0, t1_i=0, t1_pc=0, t1_st=0, t2_i=0, t2_pc=0, t2_st=0, t3_i=0, t3_pc=0, t3_st=0] [L697] int __retres1 ; [L701] CALL init_model() [L610] m_i = 1 [L611] t1_i = 1 [L612] t2_i = 1 [L613] t3_i = 1 VAL [E_1=2, E_2=2, E_3=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0] [L701] RET init_model() [L702] CALL start_simulation() [L638] int kernel_st ; [L639] int tmp ; [L640] int tmp___0 ; [L644] kernel_st = 0 [L645] FCALL update_channels() [L646] CALL init_threads() [L281] COND TRUE m_i == 1 [L282] m_st = 0 VAL [E_1=2, E_2=2, E_3=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0] [L286] COND TRUE t1_i == 1 [L287] t1_st = 0 VAL [E_1=2, E_2=2, E_3=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0] [L291] COND TRUE t2_i == 1 [L292] t2_st = 0 VAL [E_1=2, E_2=2, E_3=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0] [L296] COND TRUE t3_i == 1 [L297] t3_st = 0 VAL [E_1=2, E_2=2, E_3=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0] [L646] RET init_threads() [L647] CALL fire_delta_events() [L418] COND FALSE !(M_E == 0) VAL [E_1=2, E_2=2, E_3=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0] [L423] COND FALSE !(T1_E == 0) VAL [E_1=2, E_2=2, E_3=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0] [L428] COND FALSE !(T2_E == 0) VAL [E_1=2, E_2=2, E_3=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0] [L433] COND FALSE !(T3_E == 0) VAL [E_1=2, E_2=2, E_3=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0] [L438] COND FALSE !(E_1 == 0) VAL [E_1=2, E_2=2, E_3=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0] [L443] COND FALSE !(E_2 == 0) VAL [E_1=2, E_2=2, E_3=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0] [L448] COND FALSE !(E_3 == 0) VAL [E_1=2, E_2=2, E_3=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0] [L647] RET fire_delta_events() [L648] CALL activate_threads() [L501] int tmp ; [L502] int tmp___0 ; [L503] int tmp___1 ; [L504] int tmp___2 ; [L508] CALL, EXPR is_master_triggered() [L194] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0] [L197] COND FALSE !(m_pc == 1) VAL [E_1=2, E_2=2, E_3=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0] [L207] __retres1 = 0 VAL [E_1=2, E_2=2, E_3=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, __retres1=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0] [L209] return (__retres1); VAL [E_1=2, E_2=2, E_3=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, \result=0, __retres1=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0] [L508] RET, EXPR is_master_triggered() [L508] tmp = is_master_triggered() [L510] COND FALSE !(\read(tmp)) VAL [E_1=2, E_2=2, E_3=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, tmp=0] [L516] CALL, EXPR is_transmit1_triggered() [L213] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0] [L216] COND FALSE !(t1_pc == 1) VAL [E_1=2, E_2=2, E_3=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0] [L226] __retres1 = 0 VAL [E_1=2, E_2=2, E_3=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, __retres1=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0] [L228] return (__retres1); VAL [E_1=2, E_2=2, E_3=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, \result=0, __retres1=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0] [L516] RET, EXPR is_transmit1_triggered() [L516] tmp___0 = is_transmit1_triggered() [L518] COND FALSE !(\read(tmp___0)) VAL [E_1=2, E_2=2, E_3=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, tmp=0, tmp___0=0] [L524] CALL, EXPR is_transmit2_triggered() [L232] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0] [L235] COND FALSE !(t2_pc == 1) VAL [E_1=2, E_2=2, E_3=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0] [L245] __retres1 = 0 VAL [E_1=2, E_2=2, E_3=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, __retres1=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0] [L247] return (__retres1); VAL [E_1=2, E_2=2, E_3=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, \result=0, __retres1=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0] [L524] RET, EXPR is_transmit2_triggered() [L524] tmp___1 = is_transmit2_triggered() [L526] COND FALSE !(\read(tmp___1)) VAL [E_1=2, E_2=2, E_3=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, tmp=0, tmp___0=0, tmp___1=0] [L532] CALL, EXPR is_transmit3_triggered() [L251] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0] [L254] COND FALSE !(t3_pc == 1) VAL [E_1=2, E_2=2, E_3=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0] [L264] __retres1 = 0 VAL [E_1=2, E_2=2, E_3=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, __retres1=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0] [L266] return (__retres1); VAL [E_1=2, E_2=2, E_3=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, \result=0, __retres1=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0] [L532] RET, EXPR is_transmit3_triggered() [L532] tmp___2 = is_transmit3_triggered() [L534] COND FALSE !(\read(tmp___2)) VAL [E_1=2, E_2=2, E_3=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, tmp=0, tmp___0=0, tmp___1=0, tmp___2=0] [L648] RET activate_threads() [L649] CALL reset_delta_events() [L461] COND FALSE !(M_E == 1) VAL [E_1=2, E_2=2, E_3=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0] [L466] COND FALSE !(T1_E == 1) VAL [E_1=2, E_2=2, E_3=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0] [L471] COND FALSE !(T2_E == 1) VAL [E_1=2, E_2=2, E_3=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0] [L476] COND FALSE !(T3_E == 1) VAL [E_1=2, E_2=2, E_3=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0] [L481] COND FALSE !(E_1 == 1) VAL [E_1=2, E_2=2, E_3=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0] [L486] COND FALSE !(E_2 == 1) VAL [E_1=2, E_2=2, E_3=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0] [L491] COND FALSE !(E_3 == 1) VAL [E_1=2, E_2=2, E_3=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0] [L649] RET reset_delta_events() [L652] COND TRUE 1 VAL [E_1=2, E_2=2, E_3=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, kernel_st=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0] [L655] kernel_st = 1 [L656] CALL eval() [L337] int tmp ; VAL [E_1=2, E_2=2, E_3=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0] Loop: [L341] COND TRUE 1 [L344] CALL, EXPR exists_runnable_thread() [L306] int __retres1 ; [L309] COND TRUE m_st == 0 [L310] __retres1 = 1 [L332] return (__retres1); [L344] RET, EXPR exists_runnable_thread() [L344] tmp = exists_runnable_thread() [L346] COND TRUE \read(tmp) [L351] COND TRUE m_st == 0 [L352] int tmp_ndt_1; [L353] EXPR tmp_ndt_1 = __VERIFIER_nondet_int() [L354] COND FALSE, EXPR !(\read(tmp_ndt_1)) [L351-L362] { int tmp_ndt_1; tmp_ndt_1 = __VERIFIER_nondet_int(); if (tmp_ndt_1) { { m_st = 1; master(); } } else { } } [L365] COND TRUE t1_st == 0 [L366] int tmp_ndt_2; [L367] EXPR tmp_ndt_2 = __VERIFIER_nondet_int() [L368] COND FALSE, EXPR !(\read(tmp_ndt_2)) [L365-L376] { int tmp_ndt_2; tmp_ndt_2 = __VERIFIER_nondet_int(); if (tmp_ndt_2) { { t1_st = 1; transmit1(); } } else { } } [L379] COND TRUE t2_st == 0 [L380] int tmp_ndt_3; [L381] EXPR tmp_ndt_3 = __VERIFIER_nondet_int() [L382] COND FALSE, EXPR !(\read(tmp_ndt_3)) [L379-L390] { int tmp_ndt_3; tmp_ndt_3 = __VERIFIER_nondet_int(); if (tmp_ndt_3) { { t2_st = 1; transmit2(); } } else { } } [L393] COND TRUE t3_st == 0 [L394] int tmp_ndt_4; [L395] EXPR tmp_ndt_4 = __VERIFIER_nondet_int() [L396] COND FALSE, EXPR !(\read(tmp_ndt_4)) [L393-L404] { int tmp_ndt_4; tmp_ndt_4 = __VERIFIER_nondet_int(); if (tmp_ndt_4) { { t3_st = 1; transmit3(); } } else { } } End of lasso representation. RESULT: Ultimate proved your program to be incorrect! [2023-11-12 02:32:21,438 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_215f6841-0d75-460b-aa2b-6df37e285065/bin/uautomizer-verify-uTZkv6EMXl/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (1)] Forceful destruction successful, exit code 0 Received shutdown request... --- End real Ultimate output --- Execution finished normally Writing output log to file Ultimate.log Writing human readable error path to file UltimateCounterExample.errorpath Result: FALSE(TERM)