./Ultimate.py --spec ../../sv-benchmarks/c/properties/termination.prp --file ../../sv-benchmarks/c/systemc/transmitter.04.cil.c --full-output --architecture 32bit -------------------------------------------------------------------------------- Checking for termination Using default analysis Version cf1a7837 Calling Ultimate with: /usr/lib/jvm/java-1.11.0-openjdk-amd64/bin/java -Dosgi.configuration.area=/tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_b9c4b66b-8a73-49ee-9f7b-92ffbd0a3c3e/bin/uautomizer-verify-uTZkv6EMXl/data/config -Xmx15G -Xms4m -jar /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_b9c4b66b-8a73-49ee-9f7b-92ffbd0a3c3e/bin/uautomizer-verify-uTZkv6EMXl/plugins/org.eclipse.equinox.launcher_1.5.800.v20200727-1323.jar -data @noDefault -ultimatedata /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_b9c4b66b-8a73-49ee-9f7b-92ffbd0a3c3e/bin/uautomizer-verify-uTZkv6EMXl/data -tc /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_b9c4b66b-8a73-49ee-9f7b-92ffbd0a3c3e/bin/uautomizer-verify-uTZkv6EMXl/config/AutomizerTermination.xml -i ../../sv-benchmarks/c/systemc/transmitter.04.cil.c -s /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_b9c4b66b-8a73-49ee-9f7b-92ffbd0a3c3e/bin/uautomizer-verify-uTZkv6EMXl/config/svcomp-Termination-32bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_b9c4b66b-8a73-49ee-9f7b-92ffbd0a3c3e/bin/uautomizer-verify-uTZkv6EMXl --witnessprinter.witness.filename witness --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(F end) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 32bit --witnessprinter.graph.data.programhash 1de07d37d630bd073064bf436fb9512b72ab982b0eaf3fcb1582f689c57482fa --- Real Ultimate output --- This is Ultimate 0.2.3-dev-cf1a783 [2023-11-12 02:11:53,006 INFO L188 SettingsManager]: Resetting all preferences to default values... [2023-11-12 02:11:53,089 INFO L114 SettingsManager]: Loading settings from /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_b9c4b66b-8a73-49ee-9f7b-92ffbd0a3c3e/bin/uautomizer-verify-uTZkv6EMXl/config/svcomp-Termination-32bit-Automizer_Default.epf [2023-11-12 02:11:53,096 WARN L101 SettingsManager]: Preference file contains the following unknown settings: [2023-11-12 02:11:53,096 WARN L103 SettingsManager]: * de.uni_freiburg.informatik.ultimate.core.Log level for class [2023-11-12 02:11:53,129 INFO L130 SettingsManager]: Preferences different from defaults after loading the file: [2023-11-12 02:11:53,130 INFO L151 SettingsManager]: Preferences of UltimateCore differ from their defaults: [2023-11-12 02:11:53,131 INFO L153 SettingsManager]: * Log level for class=de.uni_freiburg.informatik.ultimate.lib.smtlibutils.quantifier.QuantifierPusher=ERROR; [2023-11-12 02:11:53,132 INFO L151 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2023-11-12 02:11:53,133 INFO L153 SettingsManager]: * Create parallel compositions if possible=false [2023-11-12 02:11:53,134 INFO L153 SettingsManager]: * Use SBE=true [2023-11-12 02:11:53,134 INFO L151 SettingsManager]: Preferences of BuchiAutomizer differ from their defaults: [2023-11-12 02:11:53,135 INFO L153 SettingsManager]: * NCSB implementation=INTSET_LAZY3 [2023-11-12 02:11:53,136 INFO L153 SettingsManager]: * Use old map elimination=false [2023-11-12 02:11:53,137 INFO L153 SettingsManager]: * Use external solver (rank synthesis)=false [2023-11-12 02:11:53,138 INFO L153 SettingsManager]: * Use only trivial implications for array writes=true [2023-11-12 02:11:53,138 INFO L153 SettingsManager]: * Rank analysis=LINEAR_WITH_GUESSES [2023-11-12 02:11:53,139 INFO L151 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2023-11-12 02:11:53,140 INFO L153 SettingsManager]: * Pointer base address is valid at dereference=ASSUME [2023-11-12 02:11:53,141 INFO L153 SettingsManager]: * sizeof long=4 [2023-11-12 02:11:53,142 INFO L153 SettingsManager]: * Overapproximate operations on floating types=true [2023-11-12 02:11:53,143 INFO L153 SettingsManager]: * sizeof POINTER=4 [2023-11-12 02:11:53,143 INFO L153 SettingsManager]: * Check division by zero=IGNORE [2023-11-12 02:11:53,144 INFO L153 SettingsManager]: * Pointer to allocated memory at dereference=ASSUME [2023-11-12 02:11:53,145 INFO L153 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=ASSUME [2023-11-12 02:11:53,145 INFO L153 SettingsManager]: * Check array bounds for arrays that are off heap=ASSUME [2023-11-12 02:11:53,146 INFO L153 SettingsManager]: * Check unreachability of reach_error function=false [2023-11-12 02:11:53,147 INFO L153 SettingsManager]: * sizeof long double=12 [2023-11-12 02:11:53,147 INFO L153 SettingsManager]: * Check if freed pointer was valid=false [2023-11-12 02:11:53,148 INFO L153 SettingsManager]: * Assume nondeterminstic values are in range=false [2023-11-12 02:11:53,149 INFO L153 SettingsManager]: * Use constant arrays=true [2023-11-12 02:11:53,149 INFO L151 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2023-11-12 02:11:53,150 INFO L153 SettingsManager]: * Size of a code block=SequenceOfStatements [2023-11-12 02:11:53,150 INFO L151 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2023-11-12 02:11:53,151 INFO L153 SettingsManager]: * Trace refinement strategy=CAMEL [2023-11-12 02:11:53,151 INFO L151 SettingsManager]: Preferences of IcfgTransformer differ from their defaults: [2023-11-12 02:11:53,152 INFO L153 SettingsManager]: * TransformationType=MODULO_NEIGHBOR WARNING: An illegal reflective access operation has occurred WARNING: Illegal reflective access by com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 (file:/tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_b9c4b66b-8a73-49ee-9f7b-92ffbd0a3c3e/bin/uautomizer-verify-uTZkv6EMXl/plugins/com.sun.xml.bind_2.2.0.v201505121915.jar) to method java.lang.ClassLoader.defineClass(java.lang.String,byte[],int,int) WARNING: Please consider reporting this to the maintainers of com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 WARNING: Use --illegal-access=warn to enable warnings of further illegal reflective access operations WARNING: All illegal access operations will be denied in a future release Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_b9c4b66b-8a73-49ee-9f7b-92ffbd0a3c3e/bin/uautomizer-verify-uTZkv6EMXl Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(F end) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 32bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> 1de07d37d630bd073064bf436fb9512b72ab982b0eaf3fcb1582f689c57482fa [2023-11-12 02:11:53,479 INFO L75 nceAwareModelManager]: Repository-Root is: /tmp [2023-11-12 02:11:53,532 INFO L261 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2023-11-12 02:11:53,538 INFO L217 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2023-11-12 02:11:53,540 INFO L270 PluginConnector]: Initializing CDTParser... [2023-11-12 02:11:53,541 INFO L274 PluginConnector]: CDTParser initialized [2023-11-12 02:11:53,543 INFO L431 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_b9c4b66b-8a73-49ee-9f7b-92ffbd0a3c3e/bin/uautomizer-verify-uTZkv6EMXl/../../sv-benchmarks/c/systemc/transmitter.04.cil.c [2023-11-12 02:11:56,937 INFO L533 CDTParser]: Created temporary CDT project at NULL [2023-11-12 02:11:57,253 INFO L384 CDTParser]: Found 1 translation units. [2023-11-12 02:11:57,255 INFO L180 CDTParser]: Scanning /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_b9c4b66b-8a73-49ee-9f7b-92ffbd0a3c3e/sv-benchmarks/c/systemc/transmitter.04.cil.c [2023-11-12 02:11:57,267 INFO L427 CDTParser]: About to delete temporary CDT project at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_b9c4b66b-8a73-49ee-9f7b-92ffbd0a3c3e/bin/uautomizer-verify-uTZkv6EMXl/data/55a4d01aa/ac5dfbbda0054165947276e08a33bfdf/FLAGbc653532c [2023-11-12 02:11:57,284 INFO L435 CDTParser]: Successfully deleted /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_b9c4b66b-8a73-49ee-9f7b-92ffbd0a3c3e/bin/uautomizer-verify-uTZkv6EMXl/data/55a4d01aa/ac5dfbbda0054165947276e08a33bfdf [2023-11-12 02:11:57,287 INFO L299 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2023-11-12 02:11:57,288 INFO L133 ToolchainWalker]: Walking toolchain with 6 elements. [2023-11-12 02:11:57,290 INFO L112 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2023-11-12 02:11:57,290 INFO L270 PluginConnector]: Initializing CACSL2BoogieTranslator... [2023-11-12 02:11:57,296 INFO L274 PluginConnector]: CACSL2BoogieTranslator initialized [2023-11-12 02:11:57,297 INFO L184 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 12.11 02:11:57" (1/1) ... [2023-11-12 02:11:57,298 INFO L204 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@496324dc and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 12.11 02:11:57, skipping insertion in model container [2023-11-12 02:11:57,299 INFO L184 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 12.11 02:11:57" (1/1) ... [2023-11-12 02:11:57,367 INFO L177 MainTranslator]: Built tables and reachable declarations [2023-11-12 02:11:57,585 INFO L209 PostProcessor]: Analyzing one entry point: main [2023-11-12 02:11:57,602 INFO L202 MainTranslator]: Completed pre-run [2023-11-12 02:11:57,656 INFO L209 PostProcessor]: Analyzing one entry point: main [2023-11-12 02:11:57,681 INFO L206 MainTranslator]: Completed translation [2023-11-12 02:11:57,683 INFO L201 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 12.11 02:11:57 WrapperNode [2023-11-12 02:11:57,683 INFO L131 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2023-11-12 02:11:57,684 INFO L112 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2023-11-12 02:11:57,684 INFO L270 PluginConnector]: Initializing Boogie Procedure Inliner... [2023-11-12 02:11:57,685 INFO L274 PluginConnector]: Boogie Procedure Inliner initialized [2023-11-12 02:11:57,693 INFO L184 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 12.11 02:11:57" (1/1) ... [2023-11-12 02:11:57,703 INFO L184 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 12.11 02:11:57" (1/1) ... [2023-11-12 02:11:57,774 INFO L138 Inliner]: procedures = 36, calls = 43, calls flagged for inlining = 38, calls inlined = 71, statements flattened = 976 [2023-11-12 02:11:57,774 INFO L131 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2023-11-12 02:11:57,775 INFO L112 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2023-11-12 02:11:57,776 INFO L270 PluginConnector]: Initializing Boogie Preprocessor... [2023-11-12 02:11:57,776 INFO L274 PluginConnector]: Boogie Preprocessor initialized [2023-11-12 02:11:57,786 INFO L184 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 12.11 02:11:57" (1/1) ... [2023-11-12 02:11:57,786 INFO L184 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 12.11 02:11:57" (1/1) ... [2023-11-12 02:11:57,791 INFO L184 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 12.11 02:11:57" (1/1) ... [2023-11-12 02:11:57,792 INFO L184 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 12.11 02:11:57" (1/1) ... [2023-11-12 02:11:57,811 INFO L184 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 12.11 02:11:57" (1/1) ... [2023-11-12 02:11:57,826 INFO L184 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 12.11 02:11:57" (1/1) ... [2023-11-12 02:11:57,831 INFO L184 PluginConnector]: Executing the observer LTLStepAnnotator from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 12.11 02:11:57" (1/1) ... [2023-11-12 02:11:57,836 INFO L184 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 12.11 02:11:57" (1/1) ... [2023-11-12 02:11:57,845 INFO L131 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2023-11-12 02:11:57,846 INFO L112 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2023-11-12 02:11:57,846 INFO L270 PluginConnector]: Initializing RCFGBuilder... [2023-11-12 02:11:57,846 INFO L274 PluginConnector]: RCFGBuilder initialized [2023-11-12 02:11:57,847 INFO L184 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 12.11 02:11:57" (1/1) ... [2023-11-12 02:11:57,856 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2023-11-12 02:11:57,889 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_b9c4b66b-8a73-49ee-9f7b-92ffbd0a3c3e/bin/uautomizer-verify-uTZkv6EMXl/z3 [2023-11-12 02:11:57,907 INFO L229 MonitoredProcess]: Starting monitored process 1 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_b9c4b66b-8a73-49ee-9f7b-92ffbd0a3c3e/bin/uautomizer-verify-uTZkv6EMXl/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2023-11-12 02:11:57,938 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_b9c4b66b-8a73-49ee-9f7b-92ffbd0a3c3e/bin/uautomizer-verify-uTZkv6EMXl/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (1)] Waiting until timeout for monitored process [2023-11-12 02:11:57,969 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocInit [2023-11-12 02:11:57,969 INFO L130 BoogieDeclarations]: Found specification of procedure write~init~int [2023-11-12 02:11:57,969 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2023-11-12 02:11:57,970 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2023-11-12 02:11:58,119 INFO L236 CfgBuilder]: Building ICFG [2023-11-12 02:11:58,122 INFO L262 CfgBuilder]: Building CFG for each procedure with an implementation [2023-11-12 02:11:59,177 INFO L277 CfgBuilder]: Performing block encoding [2023-11-12 02:11:59,198 INFO L297 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2023-11-12 02:11:59,199 INFO L302 CfgBuilder]: Removed 8 assume(true) statements. [2023-11-12 02:11:59,202 INFO L201 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 12.11 02:11:59 BoogieIcfgContainer [2023-11-12 02:11:59,202 INFO L131 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2023-11-12 02:11:59,203 INFO L112 PluginConnector]: ------------------------BuchiAutomizer---------------------------- [2023-11-12 02:11:59,203 INFO L270 PluginConnector]: Initializing BuchiAutomizer... [2023-11-12 02:11:59,207 INFO L274 PluginConnector]: BuchiAutomizer initialized [2023-11-12 02:11:59,208 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2023-11-12 02:11:59,208 INFO L184 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "CDTParser AST 12.11 02:11:57" (1/3) ... [2023-11-12 02:11:59,213 INFO L204 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@3601fce8 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 12.11 02:11:59, skipping insertion in model container [2023-11-12 02:11:59,213 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2023-11-12 02:11:59,213 INFO L184 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 12.11 02:11:57" (2/3) ... [2023-11-12 02:11:59,215 INFO L204 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@3601fce8 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 12.11 02:11:59, skipping insertion in model container [2023-11-12 02:11:59,215 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2023-11-12 02:11:59,215 INFO L184 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 12.11 02:11:59" (3/3) ... [2023-11-12 02:11:59,219 INFO L332 chiAutomizerObserver]: Analyzing ICFG transmitter.04.cil.c [2023-11-12 02:11:59,305 INFO L303 stractBuchiCegarLoop]: Interprodecural is true [2023-11-12 02:11:59,305 INFO L304 stractBuchiCegarLoop]: Hoare is false [2023-11-12 02:11:59,305 INFO L305 stractBuchiCegarLoop]: Compute interpolants for ForwardPredicates [2023-11-12 02:11:59,306 INFO L306 stractBuchiCegarLoop]: Backedges is STRAIGHT_LINE [2023-11-12 02:11:59,306 INFO L307 stractBuchiCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2023-11-12 02:11:59,306 INFO L308 stractBuchiCegarLoop]: Difference is false [2023-11-12 02:11:59,306 INFO L309 stractBuchiCegarLoop]: Minimize is MINIMIZE_SEVPA [2023-11-12 02:11:59,306 INFO L313 stractBuchiCegarLoop]: ======== Iteration 0 == of CEGAR loop == BuchiAutomatonCegarLoop ======== [2023-11-12 02:11:59,313 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 397 states, 396 states have (on average 1.5303030303030303) internal successors, (606), 396 states have internal predecessors, (606), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-12 02:11:59,357 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 328 [2023-11-12 02:11:59,358 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-12 02:11:59,358 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-12 02:11:59,371 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-12 02:11:59,371 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-12 02:11:59,372 INFO L335 stractBuchiCegarLoop]: ======== Iteration 1 ============ [2023-11-12 02:11:59,373 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 397 states, 396 states have (on average 1.5303030303030303) internal successors, (606), 396 states have internal predecessors, (606), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-12 02:11:59,392 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 328 [2023-11-12 02:11:59,392 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-12 02:11:59,393 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-12 02:11:59,398 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-12 02:11:59,398 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-12 02:11:59,409 INFO L748 eck$LassoCheckResult]: Stem: 119#$Ultimate##0true assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2; 330#L-1true assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~6#1;havoc main_~__retres1~6#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 183#init_model_returnLabel#1true assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret16#1, start_simulation_#t~ret17#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 326#update_channels_returnLabel#1true assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 56#L341true assume !(1 == ~m_i~0);~m_st~0 := 2; 368#L341-2true assume 1 == ~t1_i~0;~t1_st~0 := 0; 213#L346-1true assume !(1 == ~t2_i~0);~t2_st~0 := 2; 117#L351-1true assume !(1 == ~t3_i~0);~t3_st~0 := 2; 22#L356-1true assume !(1 == ~t4_i~0);~t4_st~0 := 2; 108#L361-1true assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 32#L502true assume !(0 == ~M_E~0); 85#L502-2true assume 0 == ~T1_E~0;~T1_E~0 := 1; 16#L507-1true assume !(0 == ~T2_E~0); 57#L512-1true assume !(0 == ~T3_E~0); 316#L517-1true assume !(0 == ~T4_E~0); 10#L522-1true assume !(0 == ~E_1~0); 281#L527-1true assume !(0 == ~E_2~0); 121#L532-1true assume !(0 == ~E_3~0); 360#L537-1true assume !(0 == ~E_4~0); 136#L542-1true assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 116#L238true assume 1 == ~m_pc~0; 321#L239true assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 192#L249true is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 102#is_master_triggered_returnLabel#1true activate_threads_#t~ret10#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 101#L615true assume !(0 != activate_threads_~tmp~1#1); 199#L615-2true assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 91#L257true assume 1 == ~t1_pc~0; 322#L258true assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 113#L268true is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 31#is_transmit1_triggered_returnLabel#1true activate_threads_#t~ret11#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 189#L623true assume !(0 != activate_threads_~tmp___0~0#1); 23#L623-2true assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 188#L276true assume !(1 == ~t2_pc~0); 283#L276-2true is_transmit2_triggered_~__retres1~2#1 := 0; 341#L287true is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 187#is_transmit2_triggered_returnLabel#1true activate_threads_#t~ret12#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 345#L631true assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 358#L631-2true assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 100#L295true assume 1 == ~t3_pc~0; 37#L296true assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 93#L306true is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 8#is_transmit3_triggered_returnLabel#1true activate_threads_#t~ret13#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 324#L639true assume !(0 != activate_threads_~tmp___2~0#1); 319#L639-2true assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 378#L314true assume !(1 == ~t4_pc~0); 349#L314-2true is_transmit4_triggered_~__retres1~4#1 := 0; 143#L325true is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 51#is_transmit4_triggered_returnLabel#1true activate_threads_#t~ret14#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 90#L647true assume !(0 != activate_threads_~tmp___3~0#1); 277#L647-2true havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 392#L555true assume !(1 == ~M_E~0); 39#L555-2true assume !(1 == ~T1_E~0); 371#L560-1true assume !(1 == ~T2_E~0); 11#L565-1true assume !(1 == ~T3_E~0); 95#L570-1true assume !(1 == ~T4_E~0); 219#L575-1true assume !(1 == ~E_1~0); 295#L580-1true assume !(1 == ~E_2~0); 129#L585-1true assume 1 == ~E_3~0;~E_3~0 := 2; 29#L590-1true assume !(1 == ~E_4~0); 26#L595-1true assume { :end_inline_reset_delta_events } true; 175#L776-2true [2023-11-12 02:11:59,412 INFO L750 eck$LassoCheckResult]: Loop: 175#L776-2true assume !false; 18#L777true start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 272#L477-1true assume false; 54#eval_returnLabel#1true havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 289#update_channels_returnLabel#2true assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 78#L502-3true assume 0 == ~M_E~0;~M_E~0 := 1; 303#L502-5true assume 0 == ~T1_E~0;~T1_E~0 := 1; 314#L507-3true assume 0 == ~T2_E~0;~T2_E~0 := 1; 55#L512-3true assume 0 == ~T3_E~0;~T3_E~0 := 1; 397#L517-3true assume 0 == ~T4_E~0;~T4_E~0 := 1; 48#L522-3true assume 0 == ~E_1~0;~E_1~0 := 1; 92#L527-3true assume 0 == ~E_2~0;~E_2~0 := 1; 142#L532-3true assume !(0 == ~E_3~0); 268#L537-3true assume 0 == ~E_4~0;~E_4~0 := 1; 60#L542-3true assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 86#L238-15true assume 1 == ~m_pc~0; 9#L239-5true assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 311#L249-5true is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 50#is_master_triggered_returnLabel#6true activate_threads_#t~ret10#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 227#L615-15true assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 155#L615-17true assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 211#L257-15true assume !(1 == ~t1_pc~0); 74#L257-17true is_transmit1_triggered_~__retres1~1#1 := 0; 338#L268-5true is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 246#is_transmit1_triggered_returnLabel#6true activate_threads_#t~ret11#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 307#L623-15true assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 315#L623-17true assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 372#L276-15true assume !(1 == ~t2_pc~0); 382#L276-17true is_transmit2_triggered_~__retres1~2#1 := 0; 248#L287-5true is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 367#is_transmit2_triggered_returnLabel#6true activate_threads_#t~ret12#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 179#L631-15true assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 290#L631-17true assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 24#L295-15true assume !(1 == ~t3_pc~0); 172#L295-17true is_transmit3_triggered_~__retres1~3#1 := 0; 335#L306-5true is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 343#is_transmit3_triggered_returnLabel#6true activate_threads_#t~ret13#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 162#L639-15true assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 122#L639-17true assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 161#L314-15true assume 1 == ~t4_pc~0; 285#L315-5true assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 181#L325-5true is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 308#is_transmit4_triggered_returnLabel#6true activate_threads_#t~ret14#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 318#L647-15true assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 120#L647-17true havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 84#L555-3true assume 1 == ~M_E~0;~M_E~0 := 2; 195#L555-5true assume 1 == ~T1_E~0;~T1_E~0 := 2; 42#L560-3true assume 1 == ~T2_E~0;~T2_E~0 := 2; 309#L565-3true assume 1 == ~T3_E~0;~T3_E~0 := 2; 350#L570-3true assume 1 == ~T4_E~0;~T4_E~0 := 2; 291#L575-3true assume !(1 == ~E_1~0); 191#L580-3true assume 1 == ~E_2~0;~E_2~0 := 2; 395#L585-3true assume 1 == ~E_3~0;~E_3~0 := 2; 234#L590-3true assume 1 == ~E_4~0;~E_4~0 := 2; 276#L595-3true assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 163#L374-1true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 73#L401-1true exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 160#exists_runnable_thread_returnLabel#2true start_simulation_#t~ret16#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret16#1;havoc start_simulation_#t~ret16#1; 99#L795true assume !(0 == start_simulation_~tmp~3#1); 320#L795-2true assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret15#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 110#L374-2true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 273#L401-2true exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 30#exists_runnable_thread_returnLabel#3true stop_simulation_#t~ret15#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret15#1;havoc stop_simulation_#t~ret15#1; 168#L750true assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 40#L757true stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 299#stop_simulation_returnLabel#1true start_simulation_#t~ret17#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret15#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret17#1;havoc start_simulation_#t~ret17#1; 280#L808true assume !(0 != start_simulation_~tmp___0~1#1); 175#L776-2true [2023-11-12 02:11:59,419 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-12 02:11:59,420 INFO L85 PathProgramCache]: Analyzing trace with hash 1110077256, now seen corresponding path program 1 times [2023-11-12 02:11:59,432 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-12 02:11:59,433 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [205059249] [2023-11-12 02:11:59,433 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-12 02:11:59,434 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-12 02:11:59,569 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-12 02:11:59,770 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-12 02:11:59,771 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-12 02:11:59,771 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [205059249] [2023-11-12 02:11:59,772 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [205059249] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-12 02:11:59,773 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-12 02:11:59,773 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-12 02:11:59,775 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [334638209] [2023-11-12 02:11:59,776 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-12 02:11:59,782 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-12 02:11:59,783 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-12 02:11:59,783 INFO L85 PathProgramCache]: Analyzing trace with hash -782872547, now seen corresponding path program 1 times [2023-11-12 02:11:59,784 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-12 02:11:59,784 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1066918000] [2023-11-12 02:11:59,784 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-12 02:11:59,785 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-12 02:11:59,801 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-12 02:11:59,837 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-12 02:11:59,837 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-12 02:11:59,838 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1066918000] [2023-11-12 02:11:59,838 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1066918000] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-12 02:11:59,838 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-12 02:11:59,839 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2023-11-12 02:11:59,839 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [767318276] [2023-11-12 02:11:59,839 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-12 02:11:59,841 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-12 02:11:59,842 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-12 02:11:59,880 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-12 02:11:59,881 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-12 02:11:59,885 INFO L87 Difference]: Start difference. First operand has 397 states, 396 states have (on average 1.5303030303030303) internal successors, (606), 396 states have internal predecessors, (606), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand has 3 states, 3 states have (on average 20.0) internal successors, (60), 3 states have internal predecessors, (60), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-12 02:11:59,965 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-12 02:11:59,965 INFO L93 Difference]: Finished difference Result 395 states and 586 transitions. [2023-11-12 02:11:59,967 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 395 states and 586 transitions. [2023-11-12 02:11:59,975 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 324 [2023-11-12 02:11:59,985 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 395 states to 389 states and 580 transitions. [2023-11-12 02:11:59,986 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 389 [2023-11-12 02:11:59,988 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 389 [2023-11-12 02:11:59,989 INFO L73 IsDeterministic]: Start isDeterministic. Operand 389 states and 580 transitions. [2023-11-12 02:11:59,993 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-12 02:11:59,993 INFO L218 hiAutomatonCegarLoop]: Abstraction has 389 states and 580 transitions. [2023-11-12 02:12:00,015 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 389 states and 580 transitions. [2023-11-12 02:12:00,059 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 389 to 389. [2023-11-12 02:12:00,062 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 389 states, 389 states have (on average 1.4910025706940875) internal successors, (580), 388 states have internal predecessors, (580), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-12 02:12:00,064 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 389 states to 389 states and 580 transitions. [2023-11-12 02:12:00,067 INFO L240 hiAutomatonCegarLoop]: Abstraction has 389 states and 580 transitions. [2023-11-12 02:12:00,068 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-12 02:12:00,076 INFO L428 stractBuchiCegarLoop]: Abstraction has 389 states and 580 transitions. [2023-11-12 02:12:00,077 INFO L335 stractBuchiCegarLoop]: ======== Iteration 2 ============ [2023-11-12 02:12:00,077 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 389 states and 580 transitions. [2023-11-12 02:12:00,098 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 324 [2023-11-12 02:12:00,106 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-12 02:12:00,107 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-12 02:12:00,118 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-12 02:12:00,119 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-12 02:12:00,122 INFO L748 eck$LassoCheckResult]: Stem: 1010#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2; 1011#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~6#1;havoc main_~__retres1~6#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 1077#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret16#1, start_simulation_#t~ret17#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 1078#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 910#L341 assume 1 == ~m_i~0;~m_st~0 := 0; 911#L341-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 1104#L346-1 assume !(1 == ~t2_i~0);~t2_st~0 := 2; 1008#L351-1 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 845#L356-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 846#L361-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 865#L502 assume !(0 == ~M_E~0); 866#L502-2 assume 0 == ~T1_E~0;~T1_E~0 := 1; 831#L507-1 assume !(0 == ~T2_E~0); 832#L512-1 assume !(0 == ~T3_E~0); 912#L517-1 assume !(0 == ~T4_E~0); 819#L522-1 assume !(0 == ~E_1~0); 820#L527-1 assume !(0 == ~E_2~0); 1013#L532-1 assume !(0 == ~E_3~0); 1014#L537-1 assume !(0 == ~E_4~0); 1029#L542-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1005#L238 assume 1 == ~m_pc~0; 1006#L239 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 1052#L249 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 988#is_master_triggered_returnLabel#1 activate_threads_#t~ret10#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 986#L615 assume !(0 != activate_threads_~tmp~1#1); 987#L615-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 968#L257 assume 1 == ~t1_pc~0; 969#L258 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 1003#L268 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 863#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret11#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 864#L623 assume !(0 != activate_threads_~tmp___0~0#1); 847#L623-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 848#L276 assume !(1 == ~t2_pc~0); 1082#L276-2 is_transmit2_triggered_~__retres1~2#1 := 0; 1158#L287 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1080#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 1081#L631 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 1182#L631-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 985#L295 assume 1 == ~t3_pc~0; 877#L296 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 853#L306 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 814#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 815#L639 assume !(0 != activate_threads_~tmp___2~0#1); 1176#L639-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1177#L314 assume !(1 == ~t4_pc~0); 871#L314-2 is_transmit4_triggered_~__retres1~4#1 := 0; 870#L325 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 902#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 903#L647 assume !(0 != activate_threads_~tmp___3~0#1); 967#L647-2 havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1154#L555 assume !(1 == ~M_E~0); 880#L555-2 assume !(1 == ~T1_E~0); 881#L560-1 assume !(1 == ~T2_E~0); 821#L565-1 assume !(1 == ~T3_E~0); 822#L570-1 assume !(1 == ~T4_E~0); 974#L575-1 assume !(1 == ~E_1~0); 1109#L580-1 assume !(1 == ~E_2~0); 1021#L585-1 assume 1 == ~E_3~0;~E_3~0 := 2; 860#L590-1 assume !(1 == ~E_4~0); 854#L595-1 assume { :end_inline_reset_delta_events } true; 855#L776-2 [2023-11-12 02:12:00,124 INFO L750 eck$LassoCheckResult]: Loop: 855#L776-2 assume !false; 836#L777 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 837#L477-1 assume !false; 1127#L412 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 1128#L374 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 956#L401 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 1089#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 1093#L416 assume !(0 != eval_~tmp~0#1); 906#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 907#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 948#L502-3 assume 0 == ~M_E~0;~M_E~0 := 1; 949#L502-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 1168#L507-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 908#L512-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 909#L517-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 896#L522-3 assume 0 == ~E_1~0;~E_1~0 := 1; 897#L527-3 assume 0 == ~E_2~0;~E_2~0 := 1; 971#L532-3 assume !(0 == ~E_3~0); 1037#L537-3 assume 0 == ~E_4~0;~E_4~0 := 1; 916#L542-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 917#L238-15 assume 1 == ~m_pc~0; 816#L239-5 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 817#L249-5 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 900#is_master_triggered_returnLabel#6 activate_threads_#t~ret10#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 901#L615-15 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 1047#L615-17 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1048#L257-15 assume 1 == ~t1_pc~0; 1057#L258-5 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 942#L268-5 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1132#is_transmit1_triggered_returnLabel#6 activate_threads_#t~ret11#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 1133#L623-15 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 1169#L623-17 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1175#L276-15 assume 1 == ~t2_pc~0; 1143#L277-5 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 1138#L287-5 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1139#is_transmit2_triggered_returnLabel#6 activate_threads_#t~ret12#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 1070#L631-15 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 1071#L631-17 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 849#L295-15 assume 1 == ~t3_pc~0; 850#L296-5 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 1065#L306-5 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1179#is_transmit3_triggered_returnLabel#6 activate_threads_#t~ret13#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 1055#L639-15 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 1015#L639-17 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1016#L314-15 assume !(1 == ~t4_pc~0); 1053#L314-17 is_transmit4_triggered_~__retres1~4#1 := 0; 1074#L325-5 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1075#is_transmit4_triggered_returnLabel#6 activate_threads_#t~ret14#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 1170#L647-15 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 1012#L647-17 havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 961#L555-3 assume 1 == ~M_E~0;~M_E~0 := 2; 962#L555-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 887#L560-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 888#L565-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 1171#L570-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 1161#L575-3 assume !(1 == ~E_1~0); 1085#L580-3 assume 1 == ~E_2~0;~E_2~0 := 2; 1086#L585-3 assume 1 == ~E_3~0;~E_3~0 := 2; 1123#L590-3 assume 1 == ~E_4~0;~E_4~0 := 2; 1124#L595-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 1056#L374-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 841#L401-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 940#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret16#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret16#1;havoc start_simulation_#t~ret16#1; 983#L795 assume !(0 == start_simulation_~tmp~3#1); 984#L795-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret15#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 999#L374-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 1000#L401-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 861#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret15#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret15#1;havoc stop_simulation_#t~ret15#1; 862#L750 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 882#L757 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 883#stop_simulation_returnLabel#1 start_simulation_#t~ret17#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret15#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret17#1;havoc start_simulation_#t~ret17#1; 1157#L808 assume !(0 != start_simulation_~tmp___0~1#1); 855#L776-2 [2023-11-12 02:12:00,126 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-12 02:12:00,127 INFO L85 PathProgramCache]: Analyzing trace with hash 1069402506, now seen corresponding path program 1 times [2023-11-12 02:12:00,128 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-12 02:12:00,129 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1647750224] [2023-11-12 02:12:00,130 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-12 02:12:00,130 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-12 02:12:00,209 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-12 02:12:00,301 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-12 02:12:00,301 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-12 02:12:00,301 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1647750224] [2023-11-12 02:12:00,302 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1647750224] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-12 02:12:00,302 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-12 02:12:00,302 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-12 02:12:00,302 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1858245968] [2023-11-12 02:12:00,303 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-12 02:12:00,303 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-12 02:12:00,304 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-12 02:12:00,304 INFO L85 PathProgramCache]: Analyzing trace with hash -1797968696, now seen corresponding path program 1 times [2023-11-12 02:12:00,305 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-12 02:12:00,305 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1036501870] [2023-11-12 02:12:00,305 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-12 02:12:00,305 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-12 02:12:00,347 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-12 02:12:00,476 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-12 02:12:00,478 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-12 02:12:00,479 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1036501870] [2023-11-12 02:12:00,479 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1036501870] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-12 02:12:00,480 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-12 02:12:00,480 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-12 02:12:00,480 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1542075673] [2023-11-12 02:12:00,481 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-12 02:12:00,482 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-12 02:12:00,484 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-12 02:12:00,485 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-12 02:12:00,485 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-12 02:12:00,486 INFO L87 Difference]: Start difference. First operand 389 states and 580 transitions. cyclomatic complexity: 192 Second operand has 3 states, 3 states have (on average 20.0) internal successors, (60), 3 states have internal predecessors, (60), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-12 02:12:00,527 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-12 02:12:00,528 INFO L93 Difference]: Finished difference Result 389 states and 579 transitions. [2023-11-12 02:12:00,528 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 389 states and 579 transitions. [2023-11-12 02:12:00,534 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 324 [2023-11-12 02:12:00,540 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 389 states to 389 states and 579 transitions. [2023-11-12 02:12:00,541 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 389 [2023-11-12 02:12:00,543 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 389 [2023-11-12 02:12:00,544 INFO L73 IsDeterministic]: Start isDeterministic. Operand 389 states and 579 transitions. [2023-11-12 02:12:00,552 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-12 02:12:00,552 INFO L218 hiAutomatonCegarLoop]: Abstraction has 389 states and 579 transitions. [2023-11-12 02:12:00,555 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 389 states and 579 transitions. [2023-11-12 02:12:00,575 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 389 to 389. [2023-11-12 02:12:00,576 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 389 states, 389 states have (on average 1.4884318766066837) internal successors, (579), 388 states have internal predecessors, (579), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-12 02:12:00,584 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 389 states to 389 states and 579 transitions. [2023-11-12 02:12:00,587 INFO L240 hiAutomatonCegarLoop]: Abstraction has 389 states and 579 transitions. [2023-11-12 02:12:00,589 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-12 02:12:00,590 INFO L428 stractBuchiCegarLoop]: Abstraction has 389 states and 579 transitions. [2023-11-12 02:12:00,590 INFO L335 stractBuchiCegarLoop]: ======== Iteration 3 ============ [2023-11-12 02:12:00,591 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 389 states and 579 transitions. [2023-11-12 02:12:00,596 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 324 [2023-11-12 02:12:00,597 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-12 02:12:00,597 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-12 02:12:00,600 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-12 02:12:00,607 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-12 02:12:00,608 INFO L748 eck$LassoCheckResult]: Stem: 1795#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2; 1796#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~6#1;havoc main_~__retres1~6#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 1862#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret16#1, start_simulation_#t~ret17#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 1863#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 1695#L341 assume 1 == ~m_i~0;~m_st~0 := 0; 1696#L341-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 1889#L346-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 1793#L351-1 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 1630#L356-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 1631#L361-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 1650#L502 assume !(0 == ~M_E~0); 1651#L502-2 assume 0 == ~T1_E~0;~T1_E~0 := 1; 1616#L507-1 assume !(0 == ~T2_E~0); 1617#L512-1 assume !(0 == ~T3_E~0); 1697#L517-1 assume !(0 == ~T4_E~0); 1604#L522-1 assume !(0 == ~E_1~0); 1605#L527-1 assume !(0 == ~E_2~0); 1798#L532-1 assume !(0 == ~E_3~0); 1799#L537-1 assume !(0 == ~E_4~0); 1814#L542-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1790#L238 assume 1 == ~m_pc~0; 1791#L239 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 1837#L249 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1773#is_master_triggered_returnLabel#1 activate_threads_#t~ret10#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 1771#L615 assume !(0 != activate_threads_~tmp~1#1); 1772#L615-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1753#L257 assume 1 == ~t1_pc~0; 1754#L258 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 1788#L268 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1648#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret11#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 1649#L623 assume !(0 != activate_threads_~tmp___0~0#1); 1632#L623-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1633#L276 assume !(1 == ~t2_pc~0); 1867#L276-2 is_transmit2_triggered_~__retres1~2#1 := 0; 1943#L287 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1865#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 1866#L631 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 1967#L631-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1770#L295 assume 1 == ~t3_pc~0; 1662#L296 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 1638#L306 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1599#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 1600#L639 assume !(0 != activate_threads_~tmp___2~0#1); 1961#L639-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1962#L314 assume !(1 == ~t4_pc~0); 1656#L314-2 is_transmit4_triggered_~__retres1~4#1 := 0; 1655#L325 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1687#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 1688#L647 assume !(0 != activate_threads_~tmp___3~0#1); 1752#L647-2 havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1939#L555 assume !(1 == ~M_E~0); 1665#L555-2 assume !(1 == ~T1_E~0); 1666#L560-1 assume !(1 == ~T2_E~0); 1606#L565-1 assume !(1 == ~T3_E~0); 1607#L570-1 assume !(1 == ~T4_E~0); 1759#L575-1 assume !(1 == ~E_1~0); 1894#L580-1 assume !(1 == ~E_2~0); 1806#L585-1 assume 1 == ~E_3~0;~E_3~0 := 2; 1645#L590-1 assume !(1 == ~E_4~0); 1639#L595-1 assume { :end_inline_reset_delta_events } true; 1640#L776-2 [2023-11-12 02:12:00,608 INFO L750 eck$LassoCheckResult]: Loop: 1640#L776-2 assume !false; 1621#L777 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 1622#L477-1 assume !false; 1912#L412 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 1913#L374 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 1741#L401 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 1874#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 1878#L416 assume !(0 != eval_~tmp~0#1); 1691#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 1692#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 1733#L502-3 assume 0 == ~M_E~0;~M_E~0 := 1; 1734#L502-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 1953#L507-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 1693#L512-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 1694#L517-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 1681#L522-3 assume 0 == ~E_1~0;~E_1~0 := 1; 1682#L527-3 assume 0 == ~E_2~0;~E_2~0 := 1; 1756#L532-3 assume !(0 == ~E_3~0); 1822#L537-3 assume 0 == ~E_4~0;~E_4~0 := 1; 1701#L542-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1702#L238-15 assume 1 == ~m_pc~0; 1601#L239-5 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 1602#L249-5 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1685#is_master_triggered_returnLabel#6 activate_threads_#t~ret10#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 1686#L615-15 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 1832#L615-17 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1833#L257-15 assume 1 == ~t1_pc~0; 1842#L258-5 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 1727#L268-5 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1917#is_transmit1_triggered_returnLabel#6 activate_threads_#t~ret11#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 1918#L623-15 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 1954#L623-17 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1960#L276-15 assume 1 == ~t2_pc~0; 1928#L277-5 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 1923#L287-5 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1924#is_transmit2_triggered_returnLabel#6 activate_threads_#t~ret12#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 1855#L631-15 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 1856#L631-17 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1634#L295-15 assume 1 == ~t3_pc~0; 1635#L296-5 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 1850#L306-5 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1964#is_transmit3_triggered_returnLabel#6 activate_threads_#t~ret13#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 1840#L639-15 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 1800#L639-17 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1801#L314-15 assume !(1 == ~t4_pc~0); 1838#L314-17 is_transmit4_triggered_~__retres1~4#1 := 0; 1859#L325-5 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1860#is_transmit4_triggered_returnLabel#6 activate_threads_#t~ret14#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 1955#L647-15 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 1797#L647-17 havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1746#L555-3 assume 1 == ~M_E~0;~M_E~0 := 2; 1747#L555-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 1672#L560-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 1673#L565-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 1956#L570-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 1946#L575-3 assume !(1 == ~E_1~0); 1870#L580-3 assume 1 == ~E_2~0;~E_2~0 := 2; 1871#L585-3 assume 1 == ~E_3~0;~E_3~0 := 2; 1908#L590-3 assume 1 == ~E_4~0;~E_4~0 := 2; 1909#L595-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 1841#L374-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 1626#L401-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 1725#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret16#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret16#1;havoc start_simulation_#t~ret16#1; 1768#L795 assume !(0 == start_simulation_~tmp~3#1); 1769#L795-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret15#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 1784#L374-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 1785#L401-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 1646#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret15#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret15#1;havoc stop_simulation_#t~ret15#1; 1647#L750 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 1667#L757 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 1668#stop_simulation_returnLabel#1 start_simulation_#t~ret17#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret15#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret17#1;havoc start_simulation_#t~ret17#1; 1942#L808 assume !(0 != start_simulation_~tmp___0~1#1); 1640#L776-2 [2023-11-12 02:12:00,609 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-12 02:12:00,610 INFO L85 PathProgramCache]: Analyzing trace with hash 193383500, now seen corresponding path program 1 times [2023-11-12 02:12:00,610 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-12 02:12:00,610 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1017809385] [2023-11-12 02:12:00,611 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-12 02:12:00,611 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-12 02:12:00,629 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-12 02:12:00,692 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-12 02:12:00,692 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-12 02:12:00,693 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1017809385] [2023-11-12 02:12:00,693 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1017809385] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-12 02:12:00,693 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-12 02:12:00,693 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-12 02:12:00,694 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1196985060] [2023-11-12 02:12:00,694 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-12 02:12:00,695 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-12 02:12:00,695 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-12 02:12:00,696 INFO L85 PathProgramCache]: Analyzing trace with hash -1797968696, now seen corresponding path program 2 times [2023-11-12 02:12:00,696 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-12 02:12:00,696 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [79975798] [2023-11-12 02:12:00,696 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-12 02:12:00,697 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-12 02:12:00,716 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-12 02:12:00,769 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-12 02:12:00,770 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-12 02:12:00,770 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [79975798] [2023-11-12 02:12:00,771 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [79975798] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-12 02:12:00,771 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-12 02:12:00,771 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-12 02:12:00,772 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2117381176] [2023-11-12 02:12:00,772 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-12 02:12:00,772 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-12 02:12:00,773 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-12 02:12:00,773 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-12 02:12:00,774 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-12 02:12:00,774 INFO L87 Difference]: Start difference. First operand 389 states and 579 transitions. cyclomatic complexity: 191 Second operand has 3 states, 3 states have (on average 20.0) internal successors, (60), 3 states have internal predecessors, (60), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-12 02:12:00,792 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-12 02:12:00,793 INFO L93 Difference]: Finished difference Result 389 states and 578 transitions. [2023-11-12 02:12:00,793 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 389 states and 578 transitions. [2023-11-12 02:12:00,798 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 324 [2023-11-12 02:12:00,802 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 389 states to 389 states and 578 transitions. [2023-11-12 02:12:00,803 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 389 [2023-11-12 02:12:00,804 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 389 [2023-11-12 02:12:00,804 INFO L73 IsDeterministic]: Start isDeterministic. Operand 389 states and 578 transitions. [2023-11-12 02:12:00,805 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-12 02:12:00,805 INFO L218 hiAutomatonCegarLoop]: Abstraction has 389 states and 578 transitions. [2023-11-12 02:12:00,806 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 389 states and 578 transitions. [2023-11-12 02:12:00,816 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 389 to 389. [2023-11-12 02:12:00,818 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 389 states, 389 states have (on average 1.4858611825192802) internal successors, (578), 388 states have internal predecessors, (578), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-12 02:12:00,820 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 389 states to 389 states and 578 transitions. [2023-11-12 02:12:00,820 INFO L240 hiAutomatonCegarLoop]: Abstraction has 389 states and 578 transitions. [2023-11-12 02:12:00,821 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-12 02:12:00,822 INFO L428 stractBuchiCegarLoop]: Abstraction has 389 states and 578 transitions. [2023-11-12 02:12:00,822 INFO L335 stractBuchiCegarLoop]: ======== Iteration 4 ============ [2023-11-12 02:12:00,822 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 389 states and 578 transitions. [2023-11-12 02:12:00,826 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 324 [2023-11-12 02:12:00,826 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-12 02:12:00,827 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-12 02:12:00,828 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-12 02:12:00,829 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-12 02:12:00,829 INFO L748 eck$LassoCheckResult]: Stem: 2580#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2; 2581#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~6#1;havoc main_~__retres1~6#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 2647#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret16#1, start_simulation_#t~ret17#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 2648#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 2480#L341 assume 1 == ~m_i~0;~m_st~0 := 0; 2481#L341-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 2674#L346-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 2578#L351-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 2415#L356-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 2416#L361-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 2435#L502 assume !(0 == ~M_E~0); 2436#L502-2 assume 0 == ~T1_E~0;~T1_E~0 := 1; 2404#L507-1 assume !(0 == ~T2_E~0); 2405#L512-1 assume !(0 == ~T3_E~0); 2483#L517-1 assume !(0 == ~T4_E~0); 2391#L522-1 assume !(0 == ~E_1~0); 2392#L527-1 assume !(0 == ~E_2~0); 2583#L532-1 assume !(0 == ~E_3~0); 2584#L537-1 assume !(0 == ~E_4~0); 2599#L542-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 2575#L238 assume 1 == ~m_pc~0; 2576#L239 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 2622#L249 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 2558#is_master_triggered_returnLabel#1 activate_threads_#t~ret10#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 2556#L615 assume !(0 != activate_threads_~tmp~1#1); 2557#L615-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 2538#L257 assume 1 == ~t1_pc~0; 2539#L258 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 2574#L268 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 2433#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret11#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 2434#L623 assume !(0 != activate_threads_~tmp___0~0#1); 2417#L623-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 2418#L276 assume !(1 == ~t2_pc~0); 2652#L276-2 is_transmit2_triggered_~__retres1~2#1 := 0; 2728#L287 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 2650#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 2651#L631 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 2753#L631-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 2555#L295 assume 1 == ~t3_pc~0; 2447#L296 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 2423#L306 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 2384#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 2385#L639 assume !(0 != activate_threads_~tmp___2~0#1); 2746#L639-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 2747#L314 assume !(1 == ~t4_pc~0); 2441#L314-2 is_transmit4_triggered_~__retres1~4#1 := 0; 2440#L325 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 2473#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 2474#L647 assume !(0 != activate_threads_~tmp___3~0#1); 2537#L647-2 havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 2724#L555 assume !(1 == ~M_E~0); 2450#L555-2 assume !(1 == ~T1_E~0); 2451#L560-1 assume !(1 == ~T2_E~0); 2393#L565-1 assume !(1 == ~T3_E~0); 2394#L570-1 assume !(1 == ~T4_E~0); 2544#L575-1 assume !(1 == ~E_1~0); 2679#L580-1 assume !(1 == ~E_2~0); 2592#L585-1 assume 1 == ~E_3~0;~E_3~0 := 2; 2432#L590-1 assume !(1 == ~E_4~0); 2424#L595-1 assume { :end_inline_reset_delta_events } true; 2425#L776-2 [2023-11-12 02:12:00,830 INFO L750 eck$LassoCheckResult]: Loop: 2425#L776-2 assume !false; 2406#L777 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 2407#L477-1 assume !false; 2697#L412 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 2698#L374 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 2526#L401 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 2659#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 2663#L416 assume !(0 != eval_~tmp~0#1); 2476#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 2477#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 2518#L502-3 assume 0 == ~M_E~0;~M_E~0 := 1; 2519#L502-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 2738#L507-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 2478#L512-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 2479#L517-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 2466#L522-3 assume 0 == ~E_1~0;~E_1~0 := 1; 2467#L527-3 assume 0 == ~E_2~0;~E_2~0 := 1; 2541#L532-3 assume !(0 == ~E_3~0); 2607#L537-3 assume 0 == ~E_4~0;~E_4~0 := 1; 2486#L542-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 2487#L238-15 assume 1 == ~m_pc~0; 2386#L239-5 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 2387#L249-5 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 2470#is_master_triggered_returnLabel#6 activate_threads_#t~ret10#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 2471#L615-15 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 2617#L615-17 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 2618#L257-15 assume 1 == ~t1_pc~0; 2627#L258-5 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 2512#L268-5 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 2702#is_transmit1_triggered_returnLabel#6 activate_threads_#t~ret11#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 2703#L623-15 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 2739#L623-17 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 2745#L276-15 assume 1 == ~t2_pc~0; 2713#L277-5 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 2708#L287-5 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 2709#is_transmit2_triggered_returnLabel#6 activate_threads_#t~ret12#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 2640#L631-15 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 2641#L631-17 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 2419#L295-15 assume 1 == ~t3_pc~0; 2420#L296-5 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 2635#L306-5 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 2749#is_transmit3_triggered_returnLabel#6 activate_threads_#t~ret13#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 2625#L639-15 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 2585#L639-17 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 2586#L314-15 assume 1 == ~t4_pc~0; 2624#L315-5 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 2644#L325-5 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 2645#is_transmit4_triggered_returnLabel#6 activate_threads_#t~ret14#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 2740#L647-15 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 2582#L647-17 havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 2531#L555-3 assume 1 == ~M_E~0;~M_E~0 := 2; 2532#L555-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 2457#L560-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 2458#L565-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 2741#L570-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 2731#L575-3 assume !(1 == ~E_1~0); 2655#L580-3 assume 1 == ~E_2~0;~E_2~0 := 2; 2656#L585-3 assume 1 == ~E_3~0;~E_3~0 := 2; 2693#L590-3 assume 1 == ~E_4~0;~E_4~0 := 2; 2694#L595-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 2626#L374-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 2411#L401-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 2510#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret16#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret16#1;havoc start_simulation_#t~ret16#1; 2553#L795 assume !(0 == start_simulation_~tmp~3#1); 2554#L795-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret15#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 2569#L374-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 2570#L401-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 2430#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret15#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret15#1;havoc stop_simulation_#t~ret15#1; 2431#L750 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 2452#L757 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 2453#stop_simulation_returnLabel#1 start_simulation_#t~ret17#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret15#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret17#1;havoc start_simulation_#t~ret17#1; 2727#L808 assume !(0 != start_simulation_~tmp___0~1#1); 2425#L776-2 [2023-11-12 02:12:00,831 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-12 02:12:00,831 INFO L85 PathProgramCache]: Analyzing trace with hash -250517174, now seen corresponding path program 1 times [2023-11-12 02:12:00,832 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-12 02:12:00,832 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [822123758] [2023-11-12 02:12:00,832 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-12 02:12:00,833 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-12 02:12:00,850 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-12 02:12:00,883 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-12 02:12:00,883 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-12 02:12:00,884 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [822123758] [2023-11-12 02:12:00,884 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [822123758] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-12 02:12:00,884 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-12 02:12:00,885 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-12 02:12:00,885 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [935699013] [2023-11-12 02:12:00,885 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-12 02:12:00,886 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-12 02:12:00,886 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-12 02:12:00,887 INFO L85 PathProgramCache]: Analyzing trace with hash -1489529687, now seen corresponding path program 1 times [2023-11-12 02:12:00,887 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-12 02:12:00,887 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [154199027] [2023-11-12 02:12:00,888 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-12 02:12:00,888 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-12 02:12:00,906 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-12 02:12:00,958 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-12 02:12:00,959 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-12 02:12:00,959 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [154199027] [2023-11-12 02:12:00,959 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [154199027] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-12 02:12:00,960 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-12 02:12:00,960 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-12 02:12:00,960 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [231865606] [2023-11-12 02:12:00,961 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-12 02:12:00,961 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-12 02:12:00,961 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-12 02:12:00,962 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-12 02:12:00,962 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-12 02:12:00,963 INFO L87 Difference]: Start difference. First operand 389 states and 578 transitions. cyclomatic complexity: 190 Second operand has 3 states, 3 states have (on average 20.0) internal successors, (60), 3 states have internal predecessors, (60), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-12 02:12:00,980 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-12 02:12:00,980 INFO L93 Difference]: Finished difference Result 389 states and 577 transitions. [2023-11-12 02:12:00,980 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 389 states and 577 transitions. [2023-11-12 02:12:00,985 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 324 [2023-11-12 02:12:00,989 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 389 states to 389 states and 577 transitions. [2023-11-12 02:12:00,990 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 389 [2023-11-12 02:12:00,990 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 389 [2023-11-12 02:12:00,991 INFO L73 IsDeterministic]: Start isDeterministic. Operand 389 states and 577 transitions. [2023-11-12 02:12:00,992 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-12 02:12:00,992 INFO L218 hiAutomatonCegarLoop]: Abstraction has 389 states and 577 transitions. [2023-11-12 02:12:00,993 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 389 states and 577 transitions. [2023-11-12 02:12:01,000 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 389 to 389. [2023-11-12 02:12:01,001 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 389 states, 389 states have (on average 1.4832904884318765) internal successors, (577), 388 states have internal predecessors, (577), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-12 02:12:01,003 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 389 states to 389 states and 577 transitions. [2023-11-12 02:12:01,004 INFO L240 hiAutomatonCegarLoop]: Abstraction has 389 states and 577 transitions. [2023-11-12 02:12:01,004 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-12 02:12:01,005 INFO L428 stractBuchiCegarLoop]: Abstraction has 389 states and 577 transitions. [2023-11-12 02:12:01,006 INFO L335 stractBuchiCegarLoop]: ======== Iteration 5 ============ [2023-11-12 02:12:01,006 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 389 states and 577 transitions. [2023-11-12 02:12:01,009 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 324 [2023-11-12 02:12:01,009 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-12 02:12:01,009 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-12 02:12:01,011 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-12 02:12:01,011 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-12 02:12:01,011 INFO L748 eck$LassoCheckResult]: Stem: 3365#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2; 3366#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~6#1;havoc main_~__retres1~6#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 3432#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret16#1, start_simulation_#t~ret17#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 3433#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 3265#L341 assume 1 == ~m_i~0;~m_st~0 := 0; 3266#L341-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 3459#L346-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 3363#L351-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 3200#L356-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 3201#L361-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 3220#L502 assume !(0 == ~M_E~0); 3221#L502-2 assume 0 == ~T1_E~0;~T1_E~0 := 1; 3186#L507-1 assume !(0 == ~T2_E~0); 3187#L512-1 assume !(0 == ~T3_E~0); 3267#L517-1 assume !(0 == ~T4_E~0); 3174#L522-1 assume !(0 == ~E_1~0); 3175#L527-1 assume !(0 == ~E_2~0); 3368#L532-1 assume !(0 == ~E_3~0); 3369#L537-1 assume !(0 == ~E_4~0); 3384#L542-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 3360#L238 assume 1 == ~m_pc~0; 3361#L239 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 3407#L249 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 3343#is_master_triggered_returnLabel#1 activate_threads_#t~ret10#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 3341#L615 assume !(0 != activate_threads_~tmp~1#1); 3342#L615-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 3323#L257 assume 1 == ~t1_pc~0; 3324#L258 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 3359#L268 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 3218#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret11#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 3219#L623 assume !(0 != activate_threads_~tmp___0~0#1); 3202#L623-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 3203#L276 assume !(1 == ~t2_pc~0); 3437#L276-2 is_transmit2_triggered_~__retres1~2#1 := 0; 3513#L287 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 3435#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 3436#L631 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 3537#L631-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 3340#L295 assume 1 == ~t3_pc~0; 3232#L296 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 3208#L306 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 3169#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 3170#L639 assume !(0 != activate_threads_~tmp___2~0#1); 3531#L639-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 3532#L314 assume !(1 == ~t4_pc~0); 3226#L314-2 is_transmit4_triggered_~__retres1~4#1 := 0; 3225#L325 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 3258#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 3259#L647 assume !(0 != activate_threads_~tmp___3~0#1); 3322#L647-2 havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 3509#L555 assume !(1 == ~M_E~0); 3235#L555-2 assume !(1 == ~T1_E~0); 3236#L560-1 assume !(1 == ~T2_E~0); 3176#L565-1 assume !(1 == ~T3_E~0); 3177#L570-1 assume !(1 == ~T4_E~0); 3329#L575-1 assume !(1 == ~E_1~0); 3464#L580-1 assume !(1 == ~E_2~0); 3376#L585-1 assume 1 == ~E_3~0;~E_3~0 := 2; 3217#L590-1 assume !(1 == ~E_4~0); 3209#L595-1 assume { :end_inline_reset_delta_events } true; 3210#L776-2 [2023-11-12 02:12:01,012 INFO L750 eck$LassoCheckResult]: Loop: 3210#L776-2 assume !false; 3191#L777 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 3192#L477-1 assume !false; 3482#L412 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 3483#L374 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 3311#L401 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 3446#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 3448#L416 assume !(0 != eval_~tmp~0#1); 3261#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 3262#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 3303#L502-3 assume 0 == ~M_E~0;~M_E~0 := 1; 3304#L502-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 3523#L507-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 3263#L512-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 3264#L517-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 3251#L522-3 assume 0 == ~E_1~0;~E_1~0 := 1; 3252#L527-3 assume 0 == ~E_2~0;~E_2~0 := 1; 3326#L532-3 assume !(0 == ~E_3~0); 3392#L537-3 assume 0 == ~E_4~0;~E_4~0 := 1; 3271#L542-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 3272#L238-15 assume 1 == ~m_pc~0; 3171#L239-5 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 3172#L249-5 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 3255#is_master_triggered_returnLabel#6 activate_threads_#t~ret10#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 3256#L615-15 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 3402#L615-17 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 3403#L257-15 assume !(1 == ~t1_pc~0); 3296#L257-17 is_transmit1_triggered_~__retres1~1#1 := 0; 3297#L268-5 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 3489#is_transmit1_triggered_returnLabel#6 activate_threads_#t~ret11#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 3490#L623-15 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 3524#L623-17 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 3530#L276-15 assume 1 == ~t2_pc~0; 3498#L277-5 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 3493#L287-5 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 3494#is_transmit2_triggered_returnLabel#6 activate_threads_#t~ret12#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 3427#L631-15 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 3428#L631-17 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 3204#L295-15 assume 1 == ~t3_pc~0; 3205#L296-5 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 3420#L306-5 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 3534#is_transmit3_triggered_returnLabel#6 activate_threads_#t~ret13#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 3410#L639-15 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 3370#L639-17 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 3371#L314-15 assume !(1 == ~t4_pc~0); 3408#L314-17 is_transmit4_triggered_~__retres1~4#1 := 0; 3425#L325-5 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 3426#is_transmit4_triggered_returnLabel#6 activate_threads_#t~ret14#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 3525#L647-15 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 3367#L647-17 havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 3316#L555-3 assume 1 == ~M_E~0;~M_E~0 := 2; 3317#L555-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 3242#L560-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 3243#L565-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 3526#L570-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 3516#L575-3 assume !(1 == ~E_1~0); 3440#L580-3 assume 1 == ~E_2~0;~E_2~0 := 2; 3441#L585-3 assume 1 == ~E_3~0;~E_3~0 := 2; 3478#L590-3 assume 1 == ~E_4~0;~E_4~0 := 2; 3479#L595-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 3411#L374-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 3196#L401-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 3295#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret16#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret16#1;havoc start_simulation_#t~ret16#1; 3338#L795 assume !(0 == start_simulation_~tmp~3#1); 3339#L795-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret15#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 3353#L374-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 3354#L401-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 3215#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret15#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret15#1;havoc stop_simulation_#t~ret15#1; 3216#L750 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 3237#L757 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 3238#stop_simulation_returnLabel#1 start_simulation_#t~ret17#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret15#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret17#1;havoc start_simulation_#t~ret17#1; 3512#L808 assume !(0 != start_simulation_~tmp___0~1#1); 3210#L776-2 [2023-11-12 02:12:01,013 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-12 02:12:01,013 INFO L85 PathProgramCache]: Analyzing trace with hash -1788857204, now seen corresponding path program 1 times [2023-11-12 02:12:01,013 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-12 02:12:01,014 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [845523024] [2023-11-12 02:12:01,014 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-12 02:12:01,014 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-12 02:12:01,028 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-12 02:12:01,066 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-12 02:12:01,066 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-12 02:12:01,066 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [845523024] [2023-11-12 02:12:01,067 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [845523024] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-12 02:12:01,067 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-12 02:12:01,067 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2023-11-12 02:12:01,067 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [184248892] [2023-11-12 02:12:01,068 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-12 02:12:01,068 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-12 02:12:01,068 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-12 02:12:01,069 INFO L85 PathProgramCache]: Analyzing trace with hash 1188993831, now seen corresponding path program 1 times [2023-11-12 02:12:01,069 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-12 02:12:01,069 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1214604332] [2023-11-12 02:12:01,069 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-12 02:12:01,070 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-12 02:12:01,082 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-12 02:12:01,115 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-12 02:12:01,115 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-12 02:12:01,115 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1214604332] [2023-11-12 02:12:01,116 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1214604332] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-12 02:12:01,116 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-12 02:12:01,116 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-12 02:12:01,116 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1542652351] [2023-11-12 02:12:01,116 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-12 02:12:01,117 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-12 02:12:01,117 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-12 02:12:01,118 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-12 02:12:01,118 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-12 02:12:01,118 INFO L87 Difference]: Start difference. First operand 389 states and 577 transitions. cyclomatic complexity: 189 Second operand has 3 states, 3 states have (on average 20.0) internal successors, (60), 2 states have internal predecessors, (60), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-12 02:12:01,140 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-12 02:12:01,141 INFO L93 Difference]: Finished difference Result 389 states and 572 transitions. [2023-11-12 02:12:01,141 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 389 states and 572 transitions. [2023-11-12 02:12:01,145 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 324 [2023-11-12 02:12:01,149 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 389 states to 389 states and 572 transitions. [2023-11-12 02:12:01,149 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 389 [2023-11-12 02:12:01,150 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 389 [2023-11-12 02:12:01,150 INFO L73 IsDeterministic]: Start isDeterministic. Operand 389 states and 572 transitions. [2023-11-12 02:12:01,151 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-12 02:12:01,151 INFO L218 hiAutomatonCegarLoop]: Abstraction has 389 states and 572 transitions. [2023-11-12 02:12:01,152 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 389 states and 572 transitions. [2023-11-12 02:12:01,158 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 389 to 389. [2023-11-12 02:12:01,159 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 389 states, 389 states have (on average 1.4704370179948587) internal successors, (572), 388 states have internal predecessors, (572), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-12 02:12:01,161 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 389 states to 389 states and 572 transitions. [2023-11-12 02:12:01,162 INFO L240 hiAutomatonCegarLoop]: Abstraction has 389 states and 572 transitions. [2023-11-12 02:12:01,162 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-12 02:12:01,163 INFO L428 stractBuchiCegarLoop]: Abstraction has 389 states and 572 transitions. [2023-11-12 02:12:01,163 INFO L335 stractBuchiCegarLoop]: ======== Iteration 6 ============ [2023-11-12 02:12:01,163 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 389 states and 572 transitions. [2023-11-12 02:12:01,167 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 324 [2023-11-12 02:12:01,167 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-12 02:12:01,167 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-12 02:12:01,168 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-12 02:12:01,169 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-12 02:12:01,169 INFO L748 eck$LassoCheckResult]: Stem: 4150#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2; 4151#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~6#1;havoc main_~__retres1~6#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 4217#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret16#1, start_simulation_#t~ret17#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 4218#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 4050#L341 assume 1 == ~m_i~0;~m_st~0 := 0; 4051#L341-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 4244#L346-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 4148#L351-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 3985#L356-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 3986#L361-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 4005#L502 assume !(0 == ~M_E~0); 4006#L502-2 assume !(0 == ~T1_E~0); 3971#L507-1 assume !(0 == ~T2_E~0); 3972#L512-1 assume !(0 == ~T3_E~0); 4052#L517-1 assume !(0 == ~T4_E~0); 3959#L522-1 assume !(0 == ~E_1~0); 3960#L527-1 assume !(0 == ~E_2~0); 4153#L532-1 assume !(0 == ~E_3~0); 4154#L537-1 assume !(0 == ~E_4~0); 4169#L542-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 4145#L238 assume 1 == ~m_pc~0; 4146#L239 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 4192#L249 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 4128#is_master_triggered_returnLabel#1 activate_threads_#t~ret10#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 4126#L615 assume !(0 != activate_threads_~tmp~1#1); 4127#L615-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 4108#L257 assume 1 == ~t1_pc~0; 4109#L258 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 4143#L268 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 4003#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret11#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 4004#L623 assume !(0 != activate_threads_~tmp___0~0#1); 3987#L623-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 3988#L276 assume !(1 == ~t2_pc~0); 4222#L276-2 is_transmit2_triggered_~__retres1~2#1 := 0; 4298#L287 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 4220#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 4221#L631 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 4322#L631-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 4125#L295 assume 1 == ~t3_pc~0; 4017#L296 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 3993#L306 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 3954#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 3955#L639 assume !(0 != activate_threads_~tmp___2~0#1); 4316#L639-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 4317#L314 assume !(1 == ~t4_pc~0); 4011#L314-2 is_transmit4_triggered_~__retres1~4#1 := 0; 4010#L325 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 4042#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 4043#L647 assume !(0 != activate_threads_~tmp___3~0#1); 4107#L647-2 havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 4294#L555 assume !(1 == ~M_E~0); 4020#L555-2 assume !(1 == ~T1_E~0); 4021#L560-1 assume !(1 == ~T2_E~0); 3961#L565-1 assume !(1 == ~T3_E~0); 3962#L570-1 assume !(1 == ~T4_E~0); 4114#L575-1 assume !(1 == ~E_1~0); 4249#L580-1 assume !(1 == ~E_2~0); 4161#L585-1 assume 1 == ~E_3~0;~E_3~0 := 2; 4000#L590-1 assume !(1 == ~E_4~0); 3994#L595-1 assume { :end_inline_reset_delta_events } true; 3995#L776-2 [2023-11-12 02:12:01,170 INFO L750 eck$LassoCheckResult]: Loop: 3995#L776-2 assume !false; 3976#L777 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 3977#L477-1 assume !false; 4267#L412 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 4268#L374 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 4096#L401 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 4229#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 4233#L416 assume !(0 != eval_~tmp~0#1); 4046#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 4047#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 4088#L502-3 assume 0 == ~M_E~0;~M_E~0 := 1; 4089#L502-5 assume !(0 == ~T1_E~0); 4308#L507-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 4048#L512-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 4049#L517-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 4036#L522-3 assume 0 == ~E_1~0;~E_1~0 := 1; 4037#L527-3 assume 0 == ~E_2~0;~E_2~0 := 1; 4111#L532-3 assume !(0 == ~E_3~0); 4177#L537-3 assume 0 == ~E_4~0;~E_4~0 := 1; 4056#L542-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 4057#L238-15 assume 1 == ~m_pc~0; 3956#L239-5 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 3957#L249-5 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 4040#is_master_triggered_returnLabel#6 activate_threads_#t~ret10#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 4041#L615-15 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 4187#L615-17 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 4188#L257-15 assume !(1 == ~t1_pc~0); 4081#L257-17 is_transmit1_triggered_~__retres1~1#1 := 0; 4082#L268-5 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 4272#is_transmit1_triggered_returnLabel#6 activate_threads_#t~ret11#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 4273#L623-15 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 4309#L623-17 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 4315#L276-15 assume 1 == ~t2_pc~0; 4283#L277-5 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 4278#L287-5 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 4279#is_transmit2_triggered_returnLabel#6 activate_threads_#t~ret12#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 4210#L631-15 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 4211#L631-17 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 3989#L295-15 assume 1 == ~t3_pc~0; 3990#L296-5 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 4205#L306-5 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 4319#is_transmit3_triggered_returnLabel#6 activate_threads_#t~ret13#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 4195#L639-15 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 4155#L639-17 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 4156#L314-15 assume !(1 == ~t4_pc~0); 4193#L314-17 is_transmit4_triggered_~__retres1~4#1 := 0; 4214#L325-5 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 4215#is_transmit4_triggered_returnLabel#6 activate_threads_#t~ret14#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 4310#L647-15 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 4152#L647-17 havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 4101#L555-3 assume 1 == ~M_E~0;~M_E~0 := 2; 4102#L555-5 assume !(1 == ~T1_E~0); 4027#L560-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 4028#L565-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 4311#L570-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 4301#L575-3 assume !(1 == ~E_1~0); 4225#L580-3 assume 1 == ~E_2~0;~E_2~0 := 2; 4226#L585-3 assume 1 == ~E_3~0;~E_3~0 := 2; 4263#L590-3 assume 1 == ~E_4~0;~E_4~0 := 2; 4264#L595-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 4196#L374-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 3981#L401-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 4080#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret16#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret16#1;havoc start_simulation_#t~ret16#1; 4123#L795 assume !(0 == start_simulation_~tmp~3#1); 4124#L795-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret15#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 4139#L374-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 4140#L401-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 4001#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret15#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret15#1;havoc stop_simulation_#t~ret15#1; 4002#L750 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 4022#L757 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 4023#stop_simulation_returnLabel#1 start_simulation_#t~ret17#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret15#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret17#1;havoc start_simulation_#t~ret17#1; 4297#L808 assume !(0 != start_simulation_~tmp___0~1#1); 3995#L776-2 [2023-11-12 02:12:01,170 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-12 02:12:01,171 INFO L85 PathProgramCache]: Analyzing trace with hash -1804375922, now seen corresponding path program 1 times [2023-11-12 02:12:01,171 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-12 02:12:01,171 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1116099103] [2023-11-12 02:12:01,171 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-12 02:12:01,172 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-12 02:12:01,186 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-12 02:12:01,234 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-12 02:12:01,234 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-12 02:12:01,234 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1116099103] [2023-11-12 02:12:01,235 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1116099103] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-12 02:12:01,235 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-12 02:12:01,235 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2023-11-12 02:12:01,235 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1090045930] [2023-11-12 02:12:01,235 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-12 02:12:01,236 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-12 02:12:01,236 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-12 02:12:01,237 INFO L85 PathProgramCache]: Analyzing trace with hash -721696981, now seen corresponding path program 1 times [2023-11-12 02:12:01,237 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-12 02:12:01,237 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2134144624] [2023-11-12 02:12:01,237 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-12 02:12:01,238 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-12 02:12:01,250 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-12 02:12:01,282 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-12 02:12:01,282 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-12 02:12:01,282 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2134144624] [2023-11-12 02:12:01,282 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2134144624] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-12 02:12:01,283 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-12 02:12:01,283 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-12 02:12:01,283 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [753258731] [2023-11-12 02:12:01,283 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-12 02:12:01,284 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-12 02:12:01,284 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-12 02:12:01,284 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-12 02:12:01,285 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-12 02:12:01,285 INFO L87 Difference]: Start difference. First operand 389 states and 572 transitions. cyclomatic complexity: 184 Second operand has 3 states, 3 states have (on average 20.0) internal successors, (60), 2 states have internal predecessors, (60), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-12 02:12:01,345 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-12 02:12:01,345 INFO L93 Difference]: Finished difference Result 704 states and 1022 transitions. [2023-11-12 02:12:01,346 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 704 states and 1022 transitions. [2023-11-12 02:12:01,353 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 639 [2023-11-12 02:12:01,360 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 704 states to 704 states and 1022 transitions. [2023-11-12 02:12:01,361 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 704 [2023-11-12 02:12:01,362 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 704 [2023-11-12 02:12:01,362 INFO L73 IsDeterministic]: Start isDeterministic. Operand 704 states and 1022 transitions. [2023-11-12 02:12:01,364 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-12 02:12:01,364 INFO L218 hiAutomatonCegarLoop]: Abstraction has 704 states and 1022 transitions. [2023-11-12 02:12:01,366 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 704 states and 1022 transitions. [2023-11-12 02:12:01,380 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 704 to 668. [2023-11-12 02:12:01,382 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 668 states, 668 states have (on average 1.4565868263473054) internal successors, (973), 667 states have internal predecessors, (973), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-12 02:12:01,385 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 668 states to 668 states and 973 transitions. [2023-11-12 02:12:01,385 INFO L240 hiAutomatonCegarLoop]: Abstraction has 668 states and 973 transitions. [2023-11-12 02:12:01,386 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-12 02:12:01,388 INFO L428 stractBuchiCegarLoop]: Abstraction has 668 states and 973 transitions. [2023-11-12 02:12:01,388 INFO L335 stractBuchiCegarLoop]: ======== Iteration 7 ============ [2023-11-12 02:12:01,389 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 668 states and 973 transitions. [2023-11-12 02:12:01,394 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 603 [2023-11-12 02:12:01,394 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-12 02:12:01,397 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-12 02:12:01,403 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-12 02:12:01,403 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-12 02:12:01,403 INFO L748 eck$LassoCheckResult]: Stem: 5251#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2; 5252#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~6#1;havoc main_~__retres1~6#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 5318#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret16#1, start_simulation_#t~ret17#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 5319#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 5150#L341 assume 1 == ~m_i~0;~m_st~0 := 0; 5151#L341-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 5348#L346-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 5249#L351-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 5085#L356-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 5086#L361-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 5105#L502 assume !(0 == ~M_E~0); 5106#L502-2 assume !(0 == ~T1_E~0); 5071#L507-1 assume !(0 == ~T2_E~0); 5072#L512-1 assume !(0 == ~T3_E~0); 5152#L517-1 assume !(0 == ~T4_E~0); 5059#L522-1 assume !(0 == ~E_1~0); 5060#L527-1 assume !(0 == ~E_2~0); 5254#L532-1 assume !(0 == ~E_3~0); 5255#L537-1 assume !(0 == ~E_4~0); 5270#L542-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 5247#L238 assume !(1 == ~m_pc~0); 5248#L238-2 is_master_triggered_~__retres1~0#1 := 0; 5293#L249 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 5230#is_master_triggered_returnLabel#1 activate_threads_#t~ret10#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 5228#L615 assume !(0 != activate_threads_~tmp~1#1); 5229#L615-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 5210#L257 assume 1 == ~t1_pc~0; 5211#L258 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 5245#L268 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 5103#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret11#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 5104#L623 assume !(0 != activate_threads_~tmp___0~0#1); 5087#L623-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 5088#L276 assume !(1 == ~t2_pc~0); 5325#L276-2 is_transmit2_triggered_~__retres1~2#1 := 0; 5406#L287 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 5323#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 5324#L631 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 5433#L631-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 5227#L295 assume 1 == ~t3_pc~0; 5117#L296 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 5093#L306 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 5054#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 5055#L639 assume !(0 != activate_threads_~tmp___2~0#1); 5424#L639-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 5425#L314 assume !(1 == ~t4_pc~0); 5111#L314-2 is_transmit4_triggered_~__retres1~4#1 := 0; 5110#L325 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 5142#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 5143#L647 assume !(0 != activate_threads_~tmp___3~0#1); 5209#L647-2 havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 5402#L555 assume !(1 == ~M_E~0); 5120#L555-2 assume !(1 == ~T1_E~0); 5121#L560-1 assume !(1 == ~T2_E~0); 5061#L565-1 assume !(1 == ~T3_E~0); 5062#L570-1 assume !(1 == ~T4_E~0); 5216#L575-1 assume !(1 == ~E_1~0); 5353#L580-1 assume !(1 == ~E_2~0); 5262#L585-1 assume 1 == ~E_3~0;~E_3~0 := 2; 5100#L590-1 assume !(1 == ~E_4~0); 5094#L595-1 assume { :end_inline_reset_delta_events } true; 5095#L776-2 [2023-11-12 02:12:01,404 INFO L750 eck$LassoCheckResult]: Loop: 5095#L776-2 assume !false; 5076#L777 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 5077#L477-1 assume !false; 5372#L412 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 5373#L374 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 5196#L401 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 5332#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 5336#L416 assume !(0 != eval_~tmp~0#1); 5342#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 5665#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 5663#L502-3 assume 0 == ~M_E~0;~M_E~0 := 1; 5661#L502-5 assume !(0 == ~T1_E~0); 5659#L507-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 5656#L512-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 5654#L517-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 5652#L522-3 assume 0 == ~E_1~0;~E_1~0 := 1; 5650#L527-3 assume 0 == ~E_2~0;~E_2~0 := 1; 5648#L532-3 assume !(0 == ~E_3~0); 5646#L537-3 assume 0 == ~E_4~0;~E_4~0 := 1; 5644#L542-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 5203#L238-15 assume !(1 == ~m_pc~0); 5204#L238-17 is_master_triggered_~__retres1~0#1 := 0; 5696#L249-5 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 5695#is_master_triggered_returnLabel#6 activate_threads_#t~ret10#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 5694#L615-15 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 5693#L615-17 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 5692#L257-15 assume 1 == ~t1_pc~0; 5690#L258-5 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 5689#L268-5 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 5688#is_transmit1_triggered_returnLabel#6 activate_threads_#t~ret11#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 5687#L623-15 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 5686#L623-17 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 5685#L276-15 assume !(1 == ~t2_pc~0); 5683#L276-17 is_transmit2_triggered_~__retres1~2#1 := 0; 5682#L287-5 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 5681#is_transmit2_triggered_returnLabel#6 activate_threads_#t~ret12#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 5680#L631-15 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 5409#L631-17 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 5089#L295-15 assume 1 == ~t3_pc~0; 5090#L296-5 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 5306#L306-5 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 5430#is_transmit3_triggered_returnLabel#6 activate_threads_#t~ret13#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 5296#L639-15 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 5256#L639-17 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 5257#L314-15 assume !(1 == ~t4_pc~0); 5294#L314-17 is_transmit4_triggered_~__retres1~4#1 := 0; 5315#L325-5 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 5316#is_transmit4_triggered_returnLabel#6 activate_threads_#t~ret14#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 5419#L647-15 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 5253#L647-17 havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 5201#L555-3 assume 1 == ~M_E~0;~M_E~0 := 2; 5202#L555-5 assume !(1 == ~T1_E~0); 5127#L560-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 5128#L565-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 5420#L570-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 5410#L575-3 assume !(1 == ~E_1~0); 5328#L580-3 assume 1 == ~E_2~0;~E_2~0 := 2; 5329#L585-3 assume 1 == ~E_3~0;~E_3~0 := 2; 5367#L590-3 assume 1 == ~E_4~0;~E_4~0 := 2; 5368#L595-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 5297#L374-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 5081#L401-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 5180#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret16#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret16#1;havoc start_simulation_#t~ret16#1; 5225#L795 assume !(0 == start_simulation_~tmp~3#1); 5226#L795-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret15#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 5241#L374-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 5242#L401-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 5101#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret15#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret15#1;havoc stop_simulation_#t~ret15#1; 5102#L750 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 5122#L757 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 5123#stop_simulation_returnLabel#1 start_simulation_#t~ret17#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret15#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret17#1;havoc start_simulation_#t~ret17#1; 5405#L808 assume !(0 != start_simulation_~tmp___0~1#1); 5095#L776-2 [2023-11-12 02:12:01,405 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-12 02:12:01,406 INFO L85 PathProgramCache]: Analyzing trace with hash -1404384723, now seen corresponding path program 1 times [2023-11-12 02:12:01,406 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-12 02:12:01,406 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [220925841] [2023-11-12 02:12:01,406 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-12 02:12:01,407 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-12 02:12:01,445 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-12 02:12:01,507 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-12 02:12:01,508 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-12 02:12:01,508 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [220925841] [2023-11-12 02:12:01,508 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [220925841] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-12 02:12:01,508 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-12 02:12:01,508 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-12 02:12:01,509 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1324730797] [2023-11-12 02:12:01,510 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-12 02:12:01,510 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-12 02:12:01,510 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-12 02:12:01,511 INFO L85 PathProgramCache]: Analyzing trace with hash 284730762, now seen corresponding path program 1 times [2023-11-12 02:12:01,511 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-12 02:12:01,511 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [667886870] [2023-11-12 02:12:01,511 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-12 02:12:01,512 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-12 02:12:01,534 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-12 02:12:01,563 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-12 02:12:01,564 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-12 02:12:01,564 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [667886870] [2023-11-12 02:12:01,564 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [667886870] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-12 02:12:01,565 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-12 02:12:01,565 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-12 02:12:01,566 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [220629137] [2023-11-12 02:12:01,566 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-12 02:12:01,567 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-12 02:12:01,567 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-12 02:12:01,567 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2023-11-12 02:12:01,567 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2023-11-12 02:12:01,568 INFO L87 Difference]: Start difference. First operand 668 states and 973 transitions. cyclomatic complexity: 307 Second operand has 4 states, 4 states have (on average 15.0) internal successors, (60), 3 states have internal predecessors, (60), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-12 02:12:01,799 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-12 02:12:01,799 INFO L93 Difference]: Finished difference Result 1515 states and 2178 transitions. [2023-11-12 02:12:01,799 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1515 states and 2178 transitions. [2023-11-12 02:12:01,814 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 1407 [2023-11-12 02:12:01,827 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1515 states to 1515 states and 2178 transitions. [2023-11-12 02:12:01,828 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1515 [2023-11-12 02:12:01,830 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1515 [2023-11-12 02:12:01,830 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1515 states and 2178 transitions. [2023-11-12 02:12:01,832 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-12 02:12:01,832 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1515 states and 2178 transitions. [2023-11-12 02:12:01,835 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1515 states and 2178 transitions. [2023-11-12 02:12:01,855 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1515 to 1183. [2023-11-12 02:12:01,857 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1183 states, 1183 states have (on average 1.448013524936602) internal successors, (1713), 1182 states have internal predecessors, (1713), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-12 02:12:01,863 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1183 states to 1183 states and 1713 transitions. [2023-11-12 02:12:01,863 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1183 states and 1713 transitions. [2023-11-12 02:12:01,863 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2023-11-12 02:12:01,866 INFO L428 stractBuchiCegarLoop]: Abstraction has 1183 states and 1713 transitions. [2023-11-12 02:12:01,866 INFO L335 stractBuchiCegarLoop]: ======== Iteration 8 ============ [2023-11-12 02:12:01,866 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1183 states and 1713 transitions. [2023-11-12 02:12:01,875 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 1118 [2023-11-12 02:12:01,875 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-12 02:12:01,875 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-12 02:12:01,877 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-12 02:12:01,877 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-12 02:12:01,878 INFO L748 eck$LassoCheckResult]: Stem: 7443#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2; 7444#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~6#1;havoc main_~__retres1~6#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 7520#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret16#1, start_simulation_#t~ret17#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 7521#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 7345#L341 assume 1 == ~m_i~0;~m_st~0 := 0; 7346#L341-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 7552#L346-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 7441#L351-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 7278#L356-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 7279#L361-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 7298#L502 assume !(0 == ~M_E~0); 7299#L502-2 assume !(0 == ~T1_E~0); 7267#L507-1 assume !(0 == ~T2_E~0); 7268#L512-1 assume !(0 == ~T3_E~0); 7348#L517-1 assume !(0 == ~T4_E~0); 7254#L522-1 assume !(0 == ~E_1~0); 7255#L527-1 assume !(0 == ~E_2~0); 7446#L532-1 assume !(0 == ~E_3~0); 7447#L537-1 assume !(0 == ~E_4~0); 7465#L542-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 7439#L238 assume !(1 == ~m_pc~0); 7440#L238-2 is_master_triggered_~__retres1~0#1 := 0; 7493#L249 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 7421#is_master_triggered_returnLabel#1 activate_threads_#t~ret10#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 7419#L615 assume !(0 != activate_threads_~tmp~1#1); 7420#L615-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 7402#L257 assume !(1 == ~t1_pc~0); 7403#L257-2 is_transmit1_triggered_~__retres1~1#1 := 0; 7438#L268 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 7296#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret11#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 7297#L623 assume !(0 != activate_threads_~tmp___0~0#1); 7280#L623-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 7281#L276 assume !(1 == ~t2_pc~0); 7527#L276-2 is_transmit2_triggered_~__retres1~2#1 := 0; 7614#L287 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 7525#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 7526#L631 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 7645#L631-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 7418#L295 assume 1 == ~t3_pc~0; 7310#L296 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 7286#L306 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 7247#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 7248#L639 assume !(0 != activate_threads_~tmp___2~0#1); 7634#L639-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 7635#L314 assume !(1 == ~t4_pc~0); 7304#L314-2 is_transmit4_triggered_~__retres1~4#1 := 0; 7303#L325 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 7338#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 7339#L647 assume !(0 != activate_threads_~tmp___3~0#1); 7401#L647-2 havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 7609#L555 assume !(1 == ~M_E~0); 7313#L555-2 assume !(1 == ~T1_E~0); 7314#L560-1 assume !(1 == ~T2_E~0); 7256#L565-1 assume !(1 == ~T3_E~0); 7257#L570-1 assume !(1 == ~T4_E~0); 7408#L575-1 assume !(1 == ~E_1~0); 7557#L580-1 assume !(1 == ~E_2~0); 7458#L585-1 assume 1 == ~E_3~0;~E_3~0 := 2; 7295#L590-1 assume !(1 == ~E_4~0); 7287#L595-1 assume { :end_inline_reset_delta_events } true; 7288#L776-2 [2023-11-12 02:12:01,878 INFO L750 eck$LassoCheckResult]: Loop: 7288#L776-2 assume !false; 7269#L777 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 7270#L477-1 assume !false; 7576#L412 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 7577#L374 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 7390#L401 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 7534#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 7538#L416 assume !(0 != eval_~tmp~0#1); 7341#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 7342#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 7383#L502-3 assume 0 == ~M_E~0;~M_E~0 := 1; 7384#L502-5 assume !(0 == ~T1_E~0); 7625#L507-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 7343#L512-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 7344#L517-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 7331#L522-3 assume 0 == ~E_1~0;~E_1~0 := 1; 7332#L527-3 assume 0 == ~E_2~0;~E_2~0 := 1; 7404#L532-3 assume !(0 == ~E_3~0); 7473#L537-3 assume 0 == ~E_4~0;~E_4~0 := 1; 7351#L542-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 7352#L238-15 assume !(1 == ~m_pc~0); 7397#L238-17 is_master_triggered_~__retres1~0#1 := 0; 7436#L249-5 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 7335#is_master_triggered_returnLabel#6 activate_threads_#t~ret10#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 7336#L615-15 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 7488#L615-17 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 7489#L257-15 assume !(1 == ~t1_pc~0); 7375#L257-17 is_transmit1_triggered_~__retres1~1#1 := 0; 7376#L268-5 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 7582#is_transmit1_triggered_returnLabel#6 activate_threads_#t~ret11#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 7583#L623-15 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 7626#L623-17 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 7631#L276-15 assume 1 == ~t2_pc~0; 7595#L277-5 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 7589#L287-5 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 7590#is_transmit2_triggered_returnLabel#6 activate_threads_#t~ret12#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 7517#L631-15 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 7518#L631-17 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 7282#L295-15 assume 1 == ~t3_pc~0; 7283#L296-5 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 7508#L306-5 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 7639#is_transmit3_triggered_returnLabel#6 activate_threads_#t~ret13#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 7496#L639-15 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 7448#L639-17 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 7449#L314-15 assume !(1 == ~t4_pc~0); 7494#L314-17 is_transmit4_triggered_~__retres1~4#1 := 0; 7515#L325-5 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 7516#is_transmit4_triggered_returnLabel#6 activate_threads_#t~ret14#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 7627#L647-15 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 7445#L647-17 havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 7395#L555-3 assume 1 == ~M_E~0;~M_E~0 := 2; 7396#L555-5 assume !(1 == ~T1_E~0); 7320#L560-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 7321#L565-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 7628#L570-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 7617#L575-3 assume !(1 == ~E_1~0); 7530#L580-3 assume 1 == ~E_2~0;~E_2~0 := 2; 7531#L585-3 assume 1 == ~E_3~0;~E_3~0 := 2; 7571#L590-3 assume 1 == ~E_4~0;~E_4~0 := 2; 7572#L595-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 7497#L374-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 7274#L401-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 7374#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret16#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret16#1;havoc start_simulation_#t~ret16#1; 7416#L795 assume !(0 == start_simulation_~tmp~3#1); 7417#L795-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret15#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 8340#L374-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 8333#L401-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 8330#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret15#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret15#1;havoc stop_simulation_#t~ret15#1; 8327#L750 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 8324#L757 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 8321#stop_simulation_returnLabel#1 start_simulation_#t~ret17#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret15#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret17#1;havoc start_simulation_#t~ret17#1; 7613#L808 assume !(0 != start_simulation_~tmp___0~1#1); 7288#L776-2 [2023-11-12 02:12:01,879 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-12 02:12:01,880 INFO L85 PathProgramCache]: Analyzing trace with hash 1261932300, now seen corresponding path program 1 times [2023-11-12 02:12:01,880 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-12 02:12:01,880 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [857244380] [2023-11-12 02:12:01,880 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-12 02:12:01,881 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-12 02:12:01,893 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-12 02:12:01,948 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-12 02:12:01,949 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-12 02:12:01,950 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [857244380] [2023-11-12 02:12:01,951 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [857244380] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-12 02:12:01,951 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-12 02:12:01,951 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2023-11-12 02:12:01,956 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [602054606] [2023-11-12 02:12:01,956 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-12 02:12:01,957 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-12 02:12:01,962 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-12 02:12:01,962 INFO L85 PathProgramCache]: Analyzing trace with hash -1423265206, now seen corresponding path program 1 times [2023-11-12 02:12:01,962 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-12 02:12:01,964 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2090827771] [2023-11-12 02:12:01,965 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-12 02:12:01,965 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-12 02:12:01,977 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-12 02:12:02,008 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-12 02:12:02,009 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-12 02:12:02,009 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2090827771] [2023-11-12 02:12:02,011 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2090827771] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-12 02:12:02,012 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-12 02:12:02,012 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-12 02:12:02,012 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [618829804] [2023-11-12 02:12:02,012 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-12 02:12:02,013 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-12 02:12:02,013 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-12 02:12:02,014 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2023-11-12 02:12:02,014 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2023-11-12 02:12:02,014 INFO L87 Difference]: Start difference. First operand 1183 states and 1713 transitions. cyclomatic complexity: 532 Second operand has 5 states, 5 states have (on average 12.0) internal successors, (60), 5 states have internal predecessors, (60), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-12 02:12:02,263 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-12 02:12:02,263 INFO L93 Difference]: Finished difference Result 2586 states and 3698 transitions. [2023-11-12 02:12:02,263 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2586 states and 3698 transitions. [2023-11-12 02:12:02,287 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 2476 [2023-11-12 02:12:02,312 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2586 states to 2586 states and 3698 transitions. [2023-11-12 02:12:02,312 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2586 [2023-11-12 02:12:02,315 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2586 [2023-11-12 02:12:02,315 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2586 states and 3698 transitions. [2023-11-12 02:12:02,319 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-12 02:12:02,319 INFO L218 hiAutomatonCegarLoop]: Abstraction has 2586 states and 3698 transitions. [2023-11-12 02:12:02,323 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2586 states and 3698 transitions. [2023-11-12 02:12:02,348 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2586 to 1246. [2023-11-12 02:12:02,351 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1246 states, 1246 states have (on average 1.4253611556982344) internal successors, (1776), 1245 states have internal predecessors, (1776), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-12 02:12:02,356 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1246 states to 1246 states and 1776 transitions. [2023-11-12 02:12:02,356 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1246 states and 1776 transitions. [2023-11-12 02:12:02,356 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2023-11-12 02:12:02,361 INFO L428 stractBuchiCegarLoop]: Abstraction has 1246 states and 1776 transitions. [2023-11-12 02:12:02,361 INFO L335 stractBuchiCegarLoop]: ======== Iteration 9 ============ [2023-11-12 02:12:02,361 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1246 states and 1776 transitions. [2023-11-12 02:12:02,369 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 1178 [2023-11-12 02:12:02,369 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-12 02:12:02,370 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-12 02:12:02,371 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-12 02:12:02,371 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-12 02:12:02,371 INFO L748 eck$LassoCheckResult]: Stem: 11230#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2; 11231#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~6#1;havoc main_~__retres1~6#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 11303#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret16#1, start_simulation_#t~ret17#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 11304#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 11127#L341 assume 1 == ~m_i~0;~m_st~0 := 0; 11128#L341-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 11339#L346-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 11228#L351-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 11060#L356-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 11061#L361-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 11080#L502 assume !(0 == ~M_E~0); 11081#L502-2 assume !(0 == ~T1_E~0); 11046#L507-1 assume !(0 == ~T2_E~0); 11047#L512-1 assume !(0 == ~T3_E~0); 11129#L517-1 assume !(0 == ~T4_E~0); 11034#L522-1 assume !(0 == ~E_1~0); 11035#L527-1 assume !(0 == ~E_2~0); 11233#L532-1 assume !(0 == ~E_3~0); 11234#L537-1 assume !(0 == ~E_4~0); 11252#L542-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 11226#L238 assume !(1 == ~m_pc~0); 11227#L238-2 is_master_triggered_~__retres1~0#1 := 0; 11276#L249 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 11207#is_master_triggered_returnLabel#1 activate_threads_#t~ret10#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 11205#L615 assume !(0 != activate_threads_~tmp~1#1); 11206#L615-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 11187#L257 assume !(1 == ~t1_pc~0); 11188#L257-2 is_transmit1_triggered_~__retres1~1#1 := 0; 11224#L268 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 11078#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret11#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 11079#L623 assume !(0 != activate_threads_~tmp___0~0#1); 11062#L623-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 11063#L276 assume !(1 == ~t2_pc~0); 11310#L276-2 is_transmit2_triggered_~__retres1~2#1 := 0; 11405#L287 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 12261#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 11438#L631 assume !(0 != activate_threads_~tmp___1~0#1); 11439#L631-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 11204#L295 assume 1 == ~t3_pc~0; 11092#L296 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 11068#L306 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 11029#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 11030#L639 assume !(0 != activate_threads_~tmp___2~0#1); 11427#L639-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 11428#L314 assume !(1 == ~t4_pc~0); 11086#L314-2 is_transmit4_triggered_~__retres1~4#1 := 0; 11085#L325 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 11119#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 11120#L647 assume !(0 != activate_threads_~tmp___3~0#1); 11186#L647-2 havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 11401#L555 assume !(1 == ~M_E~0); 11095#L555-2 assume !(1 == ~T1_E~0); 11096#L560-1 assume !(1 == ~T2_E~0); 11036#L565-1 assume !(1 == ~T3_E~0); 11037#L570-1 assume !(1 == ~T4_E~0); 11193#L575-1 assume !(1 == ~E_1~0); 11345#L580-1 assume !(1 == ~E_2~0); 11244#L585-1 assume 1 == ~E_3~0;~E_3~0 := 2; 11075#L590-1 assume !(1 == ~E_4~0); 11069#L595-1 assume { :end_inline_reset_delta_events } true; 11070#L776-2 [2023-11-12 02:12:02,372 INFO L750 eck$LassoCheckResult]: Loop: 11070#L776-2 assume !false; 11051#L777 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 11052#L477-1 assume !false; 11363#L412 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 11364#L374 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 11174#L401 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 11317#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 11321#L416 assume !(0 != eval_~tmp~0#1); 11123#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 11124#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 11165#L502-3 assume 0 == ~M_E~0;~M_E~0 := 1; 11166#L502-5 assume !(0 == ~T1_E~0); 11418#L507-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 11125#L512-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 11126#L517-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 11113#L522-3 assume 0 == ~E_1~0;~E_1~0 := 1; 11114#L527-3 assume 0 == ~E_2~0;~E_2~0 := 1; 11189#L532-3 assume !(0 == ~E_3~0); 11260#L537-3 assume 0 == ~E_4~0;~E_4~0 := 1; 11133#L542-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 11134#L238-15 assume !(1 == ~m_pc~0); 11181#L238-17 is_master_triggered_~__retres1~0#1 := 0; 12191#L249-5 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 12190#is_master_triggered_returnLabel#6 activate_threads_#t~ret10#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 12189#L615-15 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 12188#L615-17 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 11337#L257-15 assume !(1 == ~t1_pc~0); 11338#L257-17 is_transmit1_triggered_~__retres1~1#1 := 0; 12141#L268-5 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 12138#is_transmit1_triggered_returnLabel#6 activate_threads_#t~ret11#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 12134#L623-15 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 12129#L623-17 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 12128#L276-15 assume !(1 == ~t2_pc~0); 12125#L276-17 is_transmit2_triggered_~__retres1~2#1 := 0; 12124#L287-5 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 12123#is_transmit2_triggered_returnLabel#6 activate_threads_#t~ret12#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 12122#L631-15 assume !(0 != activate_threads_~tmp___1~0#1); 12119#L631-17 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 12117#L295-15 assume 1 == ~t3_pc~0; 12114#L296-5 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 12111#L306-5 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 12109#is_transmit3_triggered_returnLabel#6 activate_threads_#t~ret13#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 12107#L639-15 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 12103#L639-17 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 12093#L314-15 assume !(1 == ~t4_pc~0); 12091#L314-17 is_transmit4_triggered_~__retres1~4#1 := 0; 12090#L325-5 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 11420#is_transmit4_triggered_returnLabel#6 activate_threads_#t~ret14#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 11421#L647-15 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 11232#L647-17 havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 11179#L555-3 assume 1 == ~M_E~0;~M_E~0 := 2; 11180#L555-5 assume !(1 == ~T1_E~0); 11102#L560-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 11103#L565-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 11422#L570-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 11409#L575-3 assume !(1 == ~E_1~0); 11313#L580-3 assume 1 == ~E_2~0;~E_2~0 := 2; 11314#L585-3 assume 1 == ~E_3~0;~E_3~0 := 2; 11359#L590-3 assume 1 == ~E_4~0;~E_4~0 := 2; 11360#L595-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 11280#L374-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 11056#L401-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 11157#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret16#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret16#1;havoc start_simulation_#t~ret16#1; 11201#L795 assume !(0 == start_simulation_~tmp~3#1); 11203#L795-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret15#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 11220#L374-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 11221#L401-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 11076#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret15#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret15#1;havoc stop_simulation_#t~ret15#1; 11077#L750 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 11097#L757 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 11098#stop_simulation_returnLabel#1 start_simulation_#t~ret17#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret15#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret17#1;havoc start_simulation_#t~ret17#1; 11404#L808 assume !(0 != start_simulation_~tmp___0~1#1); 11070#L776-2 [2023-11-12 02:12:02,373 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-12 02:12:02,373 INFO L85 PathProgramCache]: Analyzing trace with hash 1127918794, now seen corresponding path program 1 times [2023-11-12 02:12:02,373 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-12 02:12:02,374 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1670274481] [2023-11-12 02:12:02,374 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-12 02:12:02,374 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-12 02:12:02,388 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-12 02:12:02,466 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-12 02:12:02,466 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-12 02:12:02,466 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1670274481] [2023-11-12 02:12:02,466 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1670274481] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-12 02:12:02,467 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-12 02:12:02,467 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-12 02:12:02,467 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1232845680] [2023-11-12 02:12:02,467 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-12 02:12:02,468 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-12 02:12:02,468 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-12 02:12:02,468 INFO L85 PathProgramCache]: Analyzing trace with hash -1417640793, now seen corresponding path program 1 times [2023-11-12 02:12:02,468 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-12 02:12:02,469 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1280304663] [2023-11-12 02:12:02,469 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-12 02:12:02,469 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-12 02:12:02,478 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-12 02:12:02,507 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-12 02:12:02,507 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-12 02:12:02,507 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1280304663] [2023-11-12 02:12:02,507 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1280304663] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-12 02:12:02,508 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-12 02:12:02,508 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-12 02:12:02,508 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [643380518] [2023-11-12 02:12:02,508 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-12 02:12:02,509 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-12 02:12:02,509 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-12 02:12:02,510 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2023-11-12 02:12:02,510 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2023-11-12 02:12:02,510 INFO L87 Difference]: Start difference. First operand 1246 states and 1776 transitions. cyclomatic complexity: 532 Second operand has 4 states, 4 states have (on average 15.0) internal successors, (60), 3 states have internal predecessors, (60), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-12 02:12:02,707 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-12 02:12:02,707 INFO L93 Difference]: Finished difference Result 2834 states and 3998 transitions. [2023-11-12 02:12:02,707 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2834 states and 3998 transitions. [2023-11-12 02:12:02,731 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 2674 [2023-11-12 02:12:02,755 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2834 states to 2834 states and 3998 transitions. [2023-11-12 02:12:02,755 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2834 [2023-11-12 02:12:02,758 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2834 [2023-11-12 02:12:02,759 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2834 states and 3998 transitions. [2023-11-12 02:12:02,763 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-12 02:12:02,763 INFO L218 hiAutomatonCegarLoop]: Abstraction has 2834 states and 3998 transitions. [2023-11-12 02:12:02,766 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2834 states and 3998 transitions. [2023-11-12 02:12:02,804 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2834 to 2241. [2023-11-12 02:12:02,810 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2241 states, 2241 states have (on average 1.4203480589022757) internal successors, (3183), 2240 states have internal predecessors, (3183), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-12 02:12:02,819 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2241 states to 2241 states and 3183 transitions. [2023-11-12 02:12:02,819 INFO L240 hiAutomatonCegarLoop]: Abstraction has 2241 states and 3183 transitions. [2023-11-12 02:12:02,820 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2023-11-12 02:12:02,821 INFO L428 stractBuchiCegarLoop]: Abstraction has 2241 states and 3183 transitions. [2023-11-12 02:12:02,822 INFO L335 stractBuchiCegarLoop]: ======== Iteration 10 ============ [2023-11-12 02:12:02,822 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2241 states and 3183 transitions. [2023-11-12 02:12:02,837 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 2172 [2023-11-12 02:12:02,837 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-12 02:12:02,837 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-12 02:12:02,839 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-12 02:12:02,839 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-12 02:12:02,839 INFO L748 eck$LassoCheckResult]: Stem: 15315#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2; 15316#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~6#1;havoc main_~__retres1~6#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 15398#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret16#1, start_simulation_#t~ret17#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 15399#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 15213#L341 assume 1 == ~m_i~0;~m_st~0 := 0; 15214#L341-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 15435#L346-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 15312#L351-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 15150#L356-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 15151#L361-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 15169#L502 assume !(0 == ~M_E~0); 15170#L502-2 assume !(0 == ~T1_E~0); 15139#L507-1 assume !(0 == ~T2_E~0); 15140#L512-1 assume !(0 == ~T3_E~0); 15216#L517-1 assume !(0 == ~T4_E~0); 15128#L522-1 assume !(0 == ~E_1~0); 15129#L527-1 assume !(0 == ~E_2~0); 15318#L532-1 assume !(0 == ~E_3~0); 15319#L537-1 assume !(0 == ~E_4~0); 15338#L542-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 15310#L238 assume !(1 == ~m_pc~0); 15311#L238-2 is_master_triggered_~__retres1~0#1 := 0; 15367#L249 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 15292#is_master_triggered_returnLabel#1 activate_threads_#t~ret10#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 15290#L615 assume !(0 != activate_threads_~tmp~1#1); 15291#L615-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 15273#L257 assume !(1 == ~t1_pc~0); 15274#L257-2 is_transmit1_triggered_~__retres1~1#1 := 0; 15307#L268 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 15167#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret11#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 15168#L623 assume !(0 != activate_threads_~tmp___0~0#1); 15152#L623-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 15153#L276 assume !(1 == ~t2_pc~0); 15408#L276-2 is_transmit2_triggered_~__retres1~2#1 := 0; 15507#L287 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 15406#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 15407#L631 assume !(0 != activate_threads_~tmp___1~0#1); 15544#L631-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 15289#L295 assume !(1 == ~t3_pc~0); 15156#L295-2 is_transmit3_triggered_~__retres1~3#1 := 0; 15157#L306 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 15119#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 15120#L639 assume !(0 != activate_threads_~tmp___2~0#1); 15532#L639-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 15533#L314 assume !(1 == ~t4_pc~0); 15175#L314-2 is_transmit4_triggered_~__retres1~4#1 := 0; 15174#L325 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 15205#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 15206#L647 assume !(0 != activate_threads_~tmp___3~0#1); 15272#L647-2 havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 15503#L555 assume !(1 == ~M_E~0); 15183#L555-2 assume !(1 == ~T1_E~0); 15184#L560-1 assume !(1 == ~T2_E~0); 15124#L565-1 assume !(1 == ~T3_E~0); 15125#L570-1 assume !(1 == ~T4_E~0); 15279#L575-1 assume !(1 == ~E_1~0); 15443#L580-1 assume !(1 == ~E_2~0); 15331#L585-1 assume 1 == ~E_3~0;~E_3~0 := 2; 15164#L590-1 assume !(1 == ~E_4~0); 15158#L595-1 assume { :end_inline_reset_delta_events } true; 15159#L776-2 [2023-11-12 02:12:02,840 INFO L750 eck$LassoCheckResult]: Loop: 15159#L776-2 assume !false; 17251#L777 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 17250#L477-1 assume !false; 17249#L412 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 15519#L374 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 15260#L401 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 15416#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 15420#L416 assume !(0 != eval_~tmp~0#1); 15209#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 15210#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 15252#L502-3 assume 0 == ~M_E~0;~M_E~0 := 1; 15253#L502-5 assume !(0 == ~T1_E~0); 15521#L507-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 15211#L512-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 15212#L517-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 15199#L522-3 assume 0 == ~E_1~0;~E_1~0 := 1; 15200#L527-3 assume 0 == ~E_2~0;~E_2~0 := 1; 15275#L532-3 assume !(0 == ~E_3~0); 15346#L537-3 assume 0 == ~E_4~0;~E_4~0 := 1; 15219#L542-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 15220#L238-15 assume !(1 == ~m_pc~0); 15267#L238-17 is_master_triggered_~__retres1~0#1 := 0; 15308#L249-5 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 15201#is_master_triggered_returnLabel#6 activate_threads_#t~ret10#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 15202#L615-15 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 15361#L615-17 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 15362#L257-15 assume !(1 == ~t1_pc~0); 15244#L257-17 is_transmit1_triggered_~__retres1~1#1 := 0; 15245#L268-5 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 15472#is_transmit1_triggered_returnLabel#6 activate_threads_#t~ret11#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 15473#L623-15 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 15525#L623-17 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 15530#L276-15 assume 1 == ~t2_pc~0; 15486#L277-5 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 15488#L287-5 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 17286#is_transmit2_triggered_returnLabel#6 activate_threads_#t~ret12#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 17285#L631-15 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 15391#L631-17 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 15154#L295-15 assume !(1 == ~t3_pc~0); 15155#L295-17 is_transmit3_triggered_~__retres1~3#1 := 0; 15383#L306-5 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 17283#is_transmit3_triggered_returnLabel#6 activate_threads_#t~ret13#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 17282#L639-15 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 17281#L639-17 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 17280#L314-15 assume !(1 == ~t4_pc~0); 17278#L314-17 is_transmit4_triggered_~__retres1~4#1 := 0; 17277#L325-5 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 17276#is_transmit4_triggered_returnLabel#6 activate_threads_#t~ret14#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 17275#L647-15 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 15317#L647-17 havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 15265#L555-3 assume 1 == ~M_E~0;~M_E~0 := 2; 15266#L555-5 assume !(1 == ~T1_E~0); 15190#L560-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 15191#L565-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 15527#L570-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 15511#L575-3 assume !(1 == ~E_1~0); 15411#L580-3 assume 1 == ~E_2~0;~E_2~0 := 2; 15412#L585-3 assume 1 == ~E_3~0;~E_3~0 := 2; 15459#L590-3 assume 1 == ~E_4~0;~E_4~0 := 2; 15460#L595-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 15371#L374-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 15146#L401-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 15243#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret16#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret16#1;havoc start_simulation_#t~ret16#1; 15287#L795 assume !(0 == start_simulation_~tmp~3#1); 15288#L795-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret15#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 17269#L374-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 17264#L401-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 17263#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret15#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret15#1;havoc stop_simulation_#t~ret15#1; 17262#L750 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 17261#L757 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 17260#stop_simulation_returnLabel#1 start_simulation_#t~ret17#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret15#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret17#1;havoc start_simulation_#t~ret17#1; 17258#L808 assume !(0 != start_simulation_~tmp___0~1#1); 15159#L776-2 [2023-11-12 02:12:02,841 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-12 02:12:02,841 INFO L85 PathProgramCache]: Analyzing trace with hash 1014532137, now seen corresponding path program 1 times [2023-11-12 02:12:02,841 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-12 02:12:02,841 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1682892278] [2023-11-12 02:12:02,842 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-12 02:12:02,842 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-12 02:12:02,854 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-12 02:12:02,901 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-12 02:12:02,901 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-12 02:12:02,901 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1682892278] [2023-11-12 02:12:02,907 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1682892278] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-12 02:12:02,907 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-12 02:12:02,907 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-12 02:12:02,907 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1654127093] [2023-11-12 02:12:02,908 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-12 02:12:02,909 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-12 02:12:02,909 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-12 02:12:02,910 INFO L85 PathProgramCache]: Analyzing trace with hash 1243051817, now seen corresponding path program 1 times [2023-11-12 02:12:02,910 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-12 02:12:02,910 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [909724634] [2023-11-12 02:12:02,910 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-12 02:12:02,910 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-12 02:12:02,920 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-12 02:12:02,946 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-12 02:12:02,946 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-12 02:12:02,947 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [909724634] [2023-11-12 02:12:02,947 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [909724634] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-12 02:12:02,947 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-12 02:12:02,947 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-12 02:12:02,947 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1345045141] [2023-11-12 02:12:02,948 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-12 02:12:02,948 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-12 02:12:02,948 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-12 02:12:02,949 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2023-11-12 02:12:02,949 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2023-11-12 02:12:02,949 INFO L87 Difference]: Start difference. First operand 2241 states and 3183 transitions. cyclomatic complexity: 944 Second operand has 4 states, 4 states have (on average 15.0) internal successors, (60), 3 states have internal predecessors, (60), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-12 02:12:03,122 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-12 02:12:03,122 INFO L93 Difference]: Finished difference Result 4630 states and 6525 transitions. [2023-11-12 02:12:03,123 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 4630 states and 6525 transitions. [2023-11-12 02:12:03,163 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 4452 [2023-11-12 02:12:03,206 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 4630 states to 4630 states and 6525 transitions. [2023-11-12 02:12:03,206 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 4630 [2023-11-12 02:12:03,215 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 4630 [2023-11-12 02:12:03,215 INFO L73 IsDeterministic]: Start isDeterministic. Operand 4630 states and 6525 transitions. [2023-11-12 02:12:03,222 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-12 02:12:03,222 INFO L218 hiAutomatonCegarLoop]: Abstraction has 4630 states and 6525 transitions. [2023-11-12 02:12:03,229 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 4630 states and 6525 transitions. [2023-11-12 02:12:03,311 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 4630 to 4574. [2023-11-12 02:12:03,321 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 4574 states, 4574 states have (on average 1.410800174901618) internal successors, (6453), 4573 states have internal predecessors, (6453), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-12 02:12:03,337 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 4574 states to 4574 states and 6453 transitions. [2023-11-12 02:12:03,337 INFO L240 hiAutomatonCegarLoop]: Abstraction has 4574 states and 6453 transitions. [2023-11-12 02:12:03,337 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2023-11-12 02:12:03,338 INFO L428 stractBuchiCegarLoop]: Abstraction has 4574 states and 6453 transitions. [2023-11-12 02:12:03,338 INFO L335 stractBuchiCegarLoop]: ======== Iteration 11 ============ [2023-11-12 02:12:03,338 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 4574 states and 6453 transitions. [2023-11-12 02:12:03,360 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 4404 [2023-11-12 02:12:03,360 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-12 02:12:03,360 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-12 02:12:03,362 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-12 02:12:03,362 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-12 02:12:03,363 INFO L748 eck$LassoCheckResult]: Stem: 22194#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2; 22195#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~6#1;havoc main_~__retres1~6#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 22276#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret16#1, start_simulation_#t~ret17#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 22277#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 22095#L341 assume 1 == ~m_i~0;~m_st~0 := 0; 22096#L341-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 22321#L346-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 22192#L351-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 22032#L356-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 22033#L361-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 22051#L502 assume !(0 == ~M_E~0); 22052#L502-2 assume !(0 == ~T1_E~0); 22017#L507-1 assume 0 == ~T2_E~0;~T2_E~0 := 1; 22018#L512-1 assume !(0 == ~T3_E~0); 22097#L517-1 assume !(0 == ~T4_E~0); 22005#L522-1 assume !(0 == ~E_1~0); 22006#L527-1 assume !(0 == ~E_2~0); 22197#L532-1 assume 0 == ~E_3~0;~E_3~0 := 1; 22198#L537-1 assume !(0 == ~E_4~0); 22497#L542-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 22496#L238 assume !(1 == ~m_pc~0); 22495#L238-2 is_master_triggered_~__retres1~0#1 := 0; 22494#L249 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 22493#is_master_triggered_returnLabel#1 activate_threads_#t~ret10#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 22492#L615 assume !(0 != activate_threads_~tmp~1#1); 22491#L615-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 22490#L257 assume !(1 == ~t1_pc~0); 22489#L257-2 is_transmit1_triggered_~__retres1~1#1 := 0; 22488#L268 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 22487#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret11#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 22486#L623 assume !(0 != activate_threads_~tmp___0~0#1); 22485#L623-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 22484#L276 assume !(1 == ~t2_pc~0); 22483#L276-2 is_transmit2_triggered_~__retres1~2#1 := 0; 22499#L287 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 22498#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 22478#L631 assume !(0 != activate_threads_~tmp___1~0#1); 22477#L631-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 22476#L295 assume !(1 == ~t3_pc~0); 22475#L295-2 is_transmit3_triggered_~__retres1~3#1 := 0; 22474#L306 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 22473#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 22472#L639 assume !(0 != activate_threads_~tmp___2~0#1); 22471#L639-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 22470#L314 assume !(1 == ~t4_pc~0); 22469#L314-2 is_transmit4_triggered_~__retres1~4#1 := 0; 22467#L325 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 22466#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 22465#L647 assume !(0 != activate_threads_~tmp___3~0#1); 22464#L647-2 havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 22463#L555 assume !(1 == ~M_E~0); 22462#L555-2 assume !(1 == ~T1_E~0); 22461#L560-1 assume !(1 == ~T2_E~0); 22460#L565-1 assume !(1 == ~T3_E~0); 22459#L570-1 assume !(1 == ~T4_E~0); 22458#L575-1 assume !(1 == ~E_1~0); 22457#L580-1 assume !(1 == ~E_2~0); 22455#L585-1 assume 1 == ~E_3~0;~E_3~0 := 2; 22456#L590-1 assume !(1 == ~E_4~0); 24736#L595-1 assume { :end_inline_reset_delta_events } true; 24733#L776-2 [2023-11-12 02:12:03,363 INFO L750 eck$LassoCheckResult]: Loop: 24733#L776-2 assume !false; 24711#L777 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 24710#L477-1 assume !false; 24709#L412 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 24703#L374 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 24699#L401 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 24696#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 24694#L416 assume !(0 != eval_~tmp~0#1); 22091#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 22092#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 22397#L502-3 assume 0 == ~M_E~0;~M_E~0 := 1; 24941#L502-5 assume !(0 == ~T1_E~0); 24939#L507-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 24937#L512-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 24935#L517-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 24934#L522-3 assume 0 == ~E_1~0;~E_1~0 := 1; 24928#L527-3 assume 0 == ~E_2~0;~E_2~0 := 1; 24925#L532-3 assume 0 == ~E_3~0;~E_3~0 := 1; 24923#L537-3 assume 0 == ~E_4~0;~E_4~0 := 1; 24921#L542-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 24919#L238-15 assume !(1 == ~m_pc~0); 24917#L238-17 is_master_triggered_~__retres1~0#1 := 0; 24915#L249-5 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 24913#is_master_triggered_returnLabel#6 activate_threads_#t~ret10#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 24912#L615-15 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 24911#L615-17 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 24910#L257-15 assume !(1 == ~t1_pc~0); 24615#L257-17 is_transmit1_triggered_~__retres1~1#1 := 0; 24909#L268-5 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 24908#is_transmit1_triggered_returnLabel#6 activate_threads_#t~ret11#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 24906#L623-15 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 24905#L623-17 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 24904#L276-15 assume !(1 == ~t2_pc~0); 24901#L276-17 is_transmit2_triggered_~__retres1~2#1 := 0; 24900#L287-5 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 24899#is_transmit2_triggered_returnLabel#6 activate_threads_#t~ret12#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 24897#L631-15 assume !(0 != activate_threads_~tmp___1~0#1); 24894#L631-17 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 24892#L295-15 assume !(1 == ~t3_pc~0); 23502#L295-17 is_transmit3_triggered_~__retres1~3#1 := 0; 24891#L306-5 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 24888#is_transmit3_triggered_returnLabel#6 activate_threads_#t~ret13#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 24887#L639-15 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 24886#L639-17 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 24885#L314-15 assume !(1 == ~t4_pc~0); 24883#L314-17 is_transmit4_triggered_~__retres1~4#1 := 0; 24882#L325-5 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 24881#is_transmit4_triggered_returnLabel#6 activate_threads_#t~ret14#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 24880#L647-15 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 24879#L647-17 havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 24878#L555-3 assume 1 == ~M_E~0;~M_E~0 := 2; 24877#L555-5 assume !(1 == ~T1_E~0); 24876#L560-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 24875#L565-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 24874#L570-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 24873#L575-3 assume !(1 == ~E_1~0); 24872#L580-3 assume 1 == ~E_2~0;~E_2~0 := 2; 24811#L585-3 assume 1 == ~E_3~0;~E_3~0 := 2; 24809#L590-3 assume 1 == ~E_4~0;~E_4~0 := 2; 24807#L595-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 24802#L374-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 24797#L401-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 24795#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret16#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret16#1;havoc start_simulation_#t~ret16#1; 24793#L795 assume !(0 == start_simulation_~tmp~3#1); 24791#L795-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret15#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 24790#L374-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 24785#L401-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 24783#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret15#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret15#1;havoc stop_simulation_#t~ret15#1; 24782#L750 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 24780#L757 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 24779#stop_simulation_returnLabel#1 start_simulation_#t~ret17#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret15#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret17#1;havoc start_simulation_#t~ret17#1; 24735#L808 assume !(0 != start_simulation_~tmp___0~1#1); 24733#L776-2 [2023-11-12 02:12:03,364 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-12 02:12:03,364 INFO L85 PathProgramCache]: Analyzing trace with hash -27236631, now seen corresponding path program 1 times [2023-11-12 02:12:03,364 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-12 02:12:03,364 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1369560280] [2023-11-12 02:12:03,365 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-12 02:12:03,365 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-12 02:12:03,372 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-12 02:12:03,399 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-12 02:12:03,400 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-12 02:12:03,400 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1369560280] [2023-11-12 02:12:03,400 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1369560280] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-12 02:12:03,400 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-12 02:12:03,400 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2023-11-12 02:12:03,401 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [901810726] [2023-11-12 02:12:03,401 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-12 02:12:03,401 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-12 02:12:03,402 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-12 02:12:03,402 INFO L85 PathProgramCache]: Analyzing trace with hash -138109180, now seen corresponding path program 1 times [2023-11-12 02:12:03,402 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-12 02:12:03,402 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1450264738] [2023-11-12 02:12:03,402 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-12 02:12:03,403 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-12 02:12:03,411 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-12 02:12:03,472 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-12 02:12:03,472 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-12 02:12:03,472 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1450264738] [2023-11-12 02:12:03,472 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1450264738] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-12 02:12:03,472 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-12 02:12:03,473 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-12 02:12:03,473 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [393034222] [2023-11-12 02:12:03,473 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-12 02:12:03,473 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-12 02:12:03,473 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-12 02:12:03,474 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-12 02:12:03,474 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-12 02:12:03,474 INFO L87 Difference]: Start difference. First operand 4574 states and 6453 transitions. cyclomatic complexity: 1883 Second operand has 3 states, 3 states have (on average 20.0) internal successors, (60), 2 states have internal predecessors, (60), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-12 02:12:03,516 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-12 02:12:03,516 INFO L93 Difference]: Finished difference Result 4524 states and 6340 transitions. [2023-11-12 02:12:03,516 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 4524 states and 6340 transitions. [2023-11-12 02:12:03,549 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 4404 [2023-11-12 02:12:03,592 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 4524 states to 4524 states and 6340 transitions. [2023-11-12 02:12:03,592 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 4524 [2023-11-12 02:12:03,598 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 4524 [2023-11-12 02:12:03,598 INFO L73 IsDeterministic]: Start isDeterministic. Operand 4524 states and 6340 transitions. [2023-11-12 02:12:03,605 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-12 02:12:03,605 INFO L218 hiAutomatonCegarLoop]: Abstraction has 4524 states and 6340 transitions. [2023-11-12 02:12:03,611 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 4524 states and 6340 transitions. [2023-11-12 02:12:03,664 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 4524 to 2654. [2023-11-12 02:12:03,670 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2654 states, 2654 states have (on average 1.3960060286360212) internal successors, (3705), 2653 states have internal predecessors, (3705), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-12 02:12:03,678 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2654 states to 2654 states and 3705 transitions. [2023-11-12 02:12:03,678 INFO L240 hiAutomatonCegarLoop]: Abstraction has 2654 states and 3705 transitions. [2023-11-12 02:12:03,679 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-12 02:12:03,680 INFO L428 stractBuchiCegarLoop]: Abstraction has 2654 states and 3705 transitions. [2023-11-12 02:12:03,680 INFO L335 stractBuchiCegarLoop]: ======== Iteration 12 ============ [2023-11-12 02:12:03,680 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2654 states and 3705 transitions. [2023-11-12 02:12:03,692 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 2540 [2023-11-12 02:12:03,693 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-12 02:12:03,693 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-12 02:12:03,695 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-12 02:12:03,695 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-12 02:12:03,695 INFO L748 eck$LassoCheckResult]: Stem: 31306#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2; 31307#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~6#1;havoc main_~__retres1~6#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 31392#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret16#1, start_simulation_#t~ret17#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 31393#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 31199#L341 assume 1 == ~m_i~0;~m_st~0 := 0; 31200#L341-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 31435#L346-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 31304#L351-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 31136#L356-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 31137#L361-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 31155#L502 assume !(0 == ~M_E~0); 31156#L502-2 assume !(0 == ~T1_E~0); 31122#L507-1 assume !(0 == ~T2_E~0); 31123#L512-1 assume !(0 == ~T3_E~0); 31201#L517-1 assume !(0 == ~T4_E~0); 31110#L522-1 assume !(0 == ~E_1~0); 31111#L527-1 assume !(0 == ~E_2~0); 31310#L532-1 assume 0 == ~E_3~0;~E_3~0 := 1; 31311#L537-1 assume !(0 == ~E_4~0); 31331#L542-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 31332#L238 assume !(1 == ~m_pc~0); 31361#L238-2 is_master_triggered_~__retres1~0#1 := 0; 31362#L249 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 31282#is_master_triggered_returnLabel#1 activate_threads_#t~ret10#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 31283#L615 assume !(0 != activate_threads_~tmp~1#1); 31419#L615-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 31420#L257 assume !(1 == ~t1_pc~0); 31452#L257-2 is_transmit1_triggered_~__retres1~1#1 := 0; 31453#L268 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 31153#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret11#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 31154#L623 assume !(0 != activate_threads_~tmp___0~0#1); 31138#L623-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 31139#L276 assume !(1 == ~t2_pc~0); 31503#L276-2 is_transmit2_triggered_~__retres1~2#1 := 0; 31504#L287 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 31399#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 31400#L631 assume !(0 != activate_threads_~tmp___1~0#1); 31555#L631-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 31556#L295 assume !(1 == ~t3_pc~0); 31142#L295-2 is_transmit3_triggered_~__retres1~3#1 := 0; 31143#L306 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 31105#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 31106#L639 assume !(0 != activate_threads_~tmp___2~0#1); 31534#L639-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 31535#L314 assume !(1 == ~t4_pc~0); 31161#L314-2 is_transmit4_triggered_~__retres1~4#1 := 0; 31160#L325 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 31191#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 31192#L647 assume !(0 != activate_threads_~tmp___3~0#1); 31498#L647-2 havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 31499#L555 assume !(1 == ~M_E~0); 31169#L555-2 assume !(1 == ~T1_E~0); 31170#L560-1 assume !(1 == ~T2_E~0); 31112#L565-1 assume !(1 == ~T3_E~0); 31113#L570-1 assume !(1 == ~T4_E~0); 31441#L575-1 assume !(1 == ~E_1~0); 31442#L580-1 assume !(1 == ~E_2~0); 31577#L585-1 assume 1 == ~E_3~0;~E_3~0 := 2; 31150#L590-1 assume !(1 == ~E_4~0); 31144#L595-1 assume { :end_inline_reset_delta_events } true; 31145#L776-2 [2023-11-12 02:12:03,696 INFO L750 eck$LassoCheckResult]: Loop: 31145#L776-2 assume !false; 31127#L777 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 31128#L477-1 assume !false; 31464#L412 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 31465#L374 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 31245#L401 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 31415#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 31421#L416 assume !(0 != eval_~tmp~0#1); 31195#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 31196#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 31237#L502-3 assume 0 == ~M_E~0;~M_E~0 := 1; 31238#L502-5 assume !(0 == ~T1_E~0); 31521#L507-3 assume !(0 == ~T2_E~0); 31197#L512-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 31198#L517-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 31185#L522-3 assume 0 == ~E_1~0;~E_1~0 := 1; 31186#L527-3 assume 0 == ~E_2~0;~E_2~0 := 1; 31262#L532-3 assume !(0 == ~E_3~0); 31340#L537-3 assume 0 == ~E_4~0;~E_4~0 := 1; 33721#L542-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 31251#L238-15 assume !(1 == ~m_pc~0); 31252#L238-17 is_master_triggered_~__retres1~0#1 := 0; 31300#L249-5 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 33710#is_master_triggered_returnLabel#6 activate_threads_#t~ret10#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 33709#L615-15 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 33708#L615-17 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 31434#L257-15 assume !(1 == ~t1_pc~0); 31230#L257-17 is_transmit1_triggered_~__retres1~1#1 := 0; 31231#L268-5 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 31469#is_transmit1_triggered_returnLabel#6 activate_threads_#t~ret11#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 31470#L623-15 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 31525#L623-17 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 31531#L276-15 assume 1 == ~t2_pc~0; 31483#L277-5 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 31485#L287-5 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 33745#is_transmit2_triggered_returnLabel#6 activate_threads_#t~ret12#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 33744#L631-15 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 31385#L631-17 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 31140#L295-15 assume !(1 == ~t3_pc~0); 31141#L295-17 is_transmit3_triggered_~__retres1~3#1 := 0; 31377#L306-5 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 31542#is_transmit3_triggered_returnLabel#6 activate_threads_#t~ret13#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 31365#L639-15 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 31313#L639-17 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 31314#L314-15 assume !(1 == ~t4_pc~0); 31363#L314-17 is_transmit4_triggered_~__retres1~4#1 := 0; 31386#L325-5 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 31387#is_transmit4_triggered_returnLabel#6 activate_threads_#t~ret14#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 31532#L647-15 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 31533#L647-17 havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 31249#L555-3 assume 1 == ~M_E~0;~M_E~0 := 2; 31250#L555-5 assume !(1 == ~T1_E~0); 33720#L560-3 assume !(1 == ~T2_E~0); 33719#L565-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 33718#L570-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 33665#L575-3 assume !(1 == ~E_1~0); 33611#L580-3 assume 1 == ~E_2~0;~E_2~0 := 2; 33572#L585-3 assume !(1 == ~E_3~0); 33570#L590-3 assume 1 == ~E_4~0;~E_4~0 := 2; 33569#L595-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 33563#L374-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 31228#L401-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 31229#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret16#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret16#1;havoc start_simulation_#t~ret16#1; 31276#L795 assume !(0 == start_simulation_~tmp~3#1); 31277#L795-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret15#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 31294#L374-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 31295#L401-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 31151#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret15#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret15#1;havoc stop_simulation_#t~ret15#1; 31152#L750 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 31171#L757 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 31172#stop_simulation_returnLabel#1 start_simulation_#t~ret17#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret15#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret17#1;havoc start_simulation_#t~ret17#1; 31502#L808 assume !(0 != start_simulation_~tmp___0~1#1); 31145#L776-2 [2023-11-12 02:12:03,696 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-12 02:12:03,697 INFO L85 PathProgramCache]: Analyzing trace with hash 1911925415, now seen corresponding path program 1 times [2023-11-12 02:12:03,697 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-12 02:12:03,699 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2027189224] [2023-11-12 02:12:03,699 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-12 02:12:03,700 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-12 02:12:03,716 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-12 02:12:03,759 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-12 02:12:03,759 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-12 02:12:03,759 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2027189224] [2023-11-12 02:12:03,759 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2027189224] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-12 02:12:03,760 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-12 02:12:03,760 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-12 02:12:03,761 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1436486276] [2023-11-12 02:12:03,761 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-12 02:12:03,762 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-12 02:12:03,762 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-12 02:12:03,762 INFO L85 PathProgramCache]: Analyzing trace with hash -652636377, now seen corresponding path program 1 times [2023-11-12 02:12:03,763 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-12 02:12:03,763 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1329531550] [2023-11-12 02:12:03,763 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-12 02:12:03,763 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-12 02:12:03,784 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-12 02:12:03,817 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-12 02:12:03,818 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-12 02:12:03,818 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1329531550] [2023-11-12 02:12:03,818 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1329531550] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-12 02:12:03,818 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-12 02:12:03,818 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-12 02:12:03,819 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [193694440] [2023-11-12 02:12:03,819 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-12 02:12:03,819 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-12 02:12:03,819 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-12 02:12:03,820 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2023-11-12 02:12:03,820 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2023-11-12 02:12:03,820 INFO L87 Difference]: Start difference. First operand 2654 states and 3705 transitions. cyclomatic complexity: 1053 Second operand has 4 states, 4 states have (on average 15.0) internal successors, (60), 3 states have internal predecessors, (60), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-12 02:12:03,920 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-12 02:12:03,920 INFO L93 Difference]: Finished difference Result 4117 states and 5747 transitions. [2023-11-12 02:12:03,920 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 4117 states and 5747 transitions. [2023-11-12 02:12:03,941 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 4036 [2023-11-12 02:12:03,963 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 4117 states to 4117 states and 5747 transitions. [2023-11-12 02:12:03,964 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 4117 [2023-11-12 02:12:03,968 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 4117 [2023-11-12 02:12:03,968 INFO L73 IsDeterministic]: Start isDeterministic. Operand 4117 states and 5747 transitions. [2023-11-12 02:12:03,974 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-12 02:12:03,975 INFO L218 hiAutomatonCegarLoop]: Abstraction has 4117 states and 5747 transitions. [2023-11-12 02:12:03,981 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 4117 states and 5747 transitions. [2023-11-12 02:12:04,028 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 4117 to 2241. [2023-11-12 02:12:04,033 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2241 states, 2241 states have (on average 1.390004462293619) internal successors, (3115), 2240 states have internal predecessors, (3115), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-12 02:12:04,039 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2241 states to 2241 states and 3115 transitions. [2023-11-12 02:12:04,039 INFO L240 hiAutomatonCegarLoop]: Abstraction has 2241 states and 3115 transitions. [2023-11-12 02:12:04,040 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2023-11-12 02:12:04,040 INFO L428 stractBuchiCegarLoop]: Abstraction has 2241 states and 3115 transitions. [2023-11-12 02:12:04,041 INFO L335 stractBuchiCegarLoop]: ======== Iteration 13 ============ [2023-11-12 02:12:04,041 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2241 states and 3115 transitions. [2023-11-12 02:12:04,049 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 2172 [2023-11-12 02:12:04,049 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-12 02:12:04,050 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-12 02:12:04,051 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-12 02:12:04,051 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-12 02:12:04,052 INFO L748 eck$LassoCheckResult]: Stem: 38081#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2; 38082#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~6#1;havoc main_~__retres1~6#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 38165#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret16#1, start_simulation_#t~ret17#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 38166#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 37981#L341 assume 1 == ~m_i~0;~m_st~0 := 0; 37982#L341-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 38202#L346-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 38079#L351-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 37917#L356-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 37918#L361-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 37936#L502 assume !(0 == ~M_E~0); 37937#L502-2 assume !(0 == ~T1_E~0); 37903#L507-1 assume !(0 == ~T2_E~0); 37904#L512-1 assume !(0 == ~T3_E~0); 37983#L517-1 assume !(0 == ~T4_E~0); 37891#L522-1 assume !(0 == ~E_1~0); 37892#L527-1 assume !(0 == ~E_2~0); 38084#L532-1 assume !(0 == ~E_3~0); 38085#L537-1 assume !(0 == ~E_4~0); 38105#L542-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 38077#L238 assume !(1 == ~m_pc~0); 38078#L238-2 is_master_triggered_~__retres1~0#1 := 0; 38133#L249 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 38059#is_master_triggered_returnLabel#1 activate_threads_#t~ret10#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 38057#L615 assume !(0 != activate_threads_~tmp~1#1); 38058#L615-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 38039#L257 assume !(1 == ~t1_pc~0); 38040#L257-2 is_transmit1_triggered_~__retres1~1#1 := 0; 38074#L268 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 37934#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret11#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 37935#L623 assume !(0 != activate_threads_~tmp___0~0#1); 37919#L623-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 37920#L276 assume !(1 == ~t2_pc~0); 38174#L276-2 is_transmit2_triggered_~__retres1~2#1 := 0; 38270#L287 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 38172#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 38173#L631 assume !(0 != activate_threads_~tmp___1~0#1); 38309#L631-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 38056#L295 assume !(1 == ~t3_pc~0); 37923#L295-2 is_transmit3_triggered_~__retres1~3#1 := 0; 37924#L306 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 37886#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 37887#L639 assume !(0 != activate_threads_~tmp___2~0#1); 38296#L639-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 38297#L314 assume !(1 == ~t4_pc~0); 37942#L314-2 is_transmit4_triggered_~__retres1~4#1 := 0; 37941#L325 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 37973#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 37974#L647 assume !(0 != activate_threads_~tmp___3~0#1); 38038#L647-2 havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 38266#L555 assume !(1 == ~M_E~0); 37950#L555-2 assume !(1 == ~T1_E~0); 37951#L560-1 assume !(1 == ~T2_E~0); 37893#L565-1 assume !(1 == ~T3_E~0); 37894#L570-1 assume !(1 == ~T4_E~0); 38045#L575-1 assume !(1 == ~E_1~0); 38208#L580-1 assume !(1 == ~E_2~0); 38097#L585-1 assume !(1 == ~E_3~0); 37931#L590-1 assume !(1 == ~E_4~0); 37925#L595-1 assume { :end_inline_reset_delta_events } true; 37926#L776-2 [2023-11-12 02:12:04,052 INFO L750 eck$LassoCheckResult]: Loop: 37926#L776-2 assume !false; 39291#L777 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 39289#L477-1 assume !false; 39287#L412 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 39281#L374 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 39276#L401 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 39274#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 39272#L416 assume !(0 != eval_~tmp~0#1); 37977#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 37978#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 38018#L502-3 assume 0 == ~M_E~0;~M_E~0 := 1; 38019#L502-5 assume !(0 == ~T1_E~0); 38287#L507-3 assume !(0 == ~T2_E~0); 37979#L512-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 37980#L517-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 37967#L522-3 assume 0 == ~E_1~0;~E_1~0 := 1; 37968#L527-3 assume 0 == ~E_2~0;~E_2~0 := 1; 38041#L532-3 assume !(0 == ~E_3~0); 40102#L537-3 assume 0 == ~E_4~0;~E_4~0 := 1; 40100#L542-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 40098#L238-15 assume !(1 == ~m_pc~0); 40097#L238-17 is_master_triggered_~__retres1~0#1 := 0; 40096#L249-5 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 40095#is_master_triggered_returnLabel#6 activate_threads_#t~ret10#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 40093#L615-15 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 40088#L615-17 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 38200#L257-15 assume !(1 == ~t1_pc~0); 38201#L257-17 is_transmit1_triggered_~__retres1~1#1 := 0; 39877#L268-5 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 39875#is_transmit1_triggered_returnLabel#6 activate_threads_#t~ret11#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 39871#L623-15 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 39869#L623-17 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 39867#L276-15 assume !(1 == ~t2_pc~0); 39863#L276-17 is_transmit2_triggered_~__retres1~2#1 := 0; 39860#L287-5 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 39858#is_transmit2_triggered_returnLabel#6 activate_threads_#t~ret12#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 39856#L631-15 assume !(0 != activate_threads_~tmp___1~0#1); 39854#L631-17 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 37921#L295-15 assume !(1 == ~t3_pc~0); 37922#L295-17 is_transmit3_triggered_~__retres1~3#1 := 0; 39558#L306-5 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 39555#is_transmit3_triggered_returnLabel#6 activate_threads_#t~ret13#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 39553#L639-15 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 39551#L639-17 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 39549#L314-15 assume !(1 == ~t4_pc~0); 39546#L314-17 is_transmit4_triggered_~__retres1~4#1 := 0; 39544#L325-5 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 39542#is_transmit4_triggered_returnLabel#6 activate_threads_#t~ret14#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 39540#L647-15 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 39538#L647-17 havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 39536#L555-3 assume 1 == ~M_E~0;~M_E~0 := 2; 39535#L555-5 assume !(1 == ~T1_E~0); 39534#L560-3 assume !(1 == ~T2_E~0); 39533#L565-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 39532#L570-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 39517#L575-3 assume !(1 == ~E_1~0); 39515#L580-3 assume 1 == ~E_2~0;~E_2~0 := 2; 39514#L585-3 assume !(1 == ~E_3~0); 39513#L590-3 assume 1 == ~E_4~0;~E_4~0 := 2; 39511#L595-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 39504#L374-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 39495#L401-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 39488#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret16#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret16#1;havoc start_simulation_#t~ret16#1; 39448#L795 assume !(0 == start_simulation_~tmp~3#1); 39444#L795-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret15#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 39340#L374-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 39334#L401-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 39332#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret15#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret15#1;havoc stop_simulation_#t~ret15#1; 39331#L750 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 39330#L757 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 39329#stop_simulation_returnLabel#1 start_simulation_#t~ret17#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret15#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret17#1;havoc start_simulation_#t~ret17#1; 39323#L808 assume !(0 != start_simulation_~tmp___0~1#1); 37926#L776-2 [2023-11-12 02:12:04,053 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-12 02:12:04,053 INFO L85 PathProgramCache]: Analyzing trace with hash 1014534059, now seen corresponding path program 1 times [2023-11-12 02:12:04,053 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-12 02:12:04,053 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1016534818] [2023-11-12 02:12:04,053 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-12 02:12:04,054 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-12 02:12:04,066 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-12 02:12:04,066 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-12 02:12:04,075 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-12 02:12:04,111 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-12 02:12:04,112 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-12 02:12:04,113 INFO L85 PathProgramCache]: Analyzing trace with hash -647011964, now seen corresponding path program 1 times [2023-11-12 02:12:04,113 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-12 02:12:04,113 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [479662245] [2023-11-12 02:12:04,113 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-12 02:12:04,113 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-12 02:12:04,124 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-12 02:12:04,150 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-12 02:12:04,150 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-12 02:12:04,150 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [479662245] [2023-11-12 02:12:04,150 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [479662245] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-12 02:12:04,151 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-12 02:12:04,151 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-12 02:12:04,151 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [880747327] [2023-11-12 02:12:04,151 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-12 02:12:04,152 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-12 02:12:04,152 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-12 02:12:04,152 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-12 02:12:04,152 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-12 02:12:04,153 INFO L87 Difference]: Start difference. First operand 2241 states and 3115 transitions. cyclomatic complexity: 876 Second operand has 3 states, 3 states have (on average 24.0) internal successors, (72), 3 states have internal predecessors, (72), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-12 02:12:04,262 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-12 02:12:04,262 INFO L93 Difference]: Finished difference Result 3840 states and 5292 transitions. [2023-11-12 02:12:04,263 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 3840 states and 5292 transitions. [2023-11-12 02:12:04,286 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 3722 [2023-11-12 02:12:04,318 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 3840 states to 3840 states and 5292 transitions. [2023-11-12 02:12:04,318 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 3840 [2023-11-12 02:12:04,323 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 3840 [2023-11-12 02:12:04,323 INFO L73 IsDeterministic]: Start isDeterministic. Operand 3840 states and 5292 transitions. [2023-11-12 02:12:04,329 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-12 02:12:04,329 INFO L218 hiAutomatonCegarLoop]: Abstraction has 3840 states and 5292 transitions. [2023-11-12 02:12:04,335 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3840 states and 5292 transitions. [2023-11-12 02:12:04,406 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3840 to 3820. [2023-11-12 02:12:04,415 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 3820 states, 3820 states have (on average 1.3801047120418848) internal successors, (5272), 3819 states have internal predecessors, (5272), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-12 02:12:04,428 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3820 states to 3820 states and 5272 transitions. [2023-11-12 02:12:04,428 INFO L240 hiAutomatonCegarLoop]: Abstraction has 3820 states and 5272 transitions. [2023-11-12 02:12:04,429 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-12 02:12:04,430 INFO L428 stractBuchiCegarLoop]: Abstraction has 3820 states and 5272 transitions. [2023-11-12 02:12:04,430 INFO L335 stractBuchiCegarLoop]: ======== Iteration 14 ============ [2023-11-12 02:12:04,430 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 3820 states and 5272 transitions. [2023-11-12 02:12:04,448 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 3706 [2023-11-12 02:12:04,448 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-12 02:12:04,449 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-12 02:12:04,451 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-12 02:12:04,451 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-12 02:12:04,451 INFO L748 eck$LassoCheckResult]: Stem: 44170#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2; 44171#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~6#1;havoc main_~__retres1~6#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 44258#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret16#1, start_simulation_#t~ret17#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 44259#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 44070#L341 assume 1 == ~m_i~0;~m_st~0 := 0; 44071#L341-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 44302#L346-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 44168#L351-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 44004#L356-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 44005#L361-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 44023#L502 assume !(0 == ~M_E~0); 44024#L502-2 assume !(0 == ~T1_E~0); 43993#L507-1 assume !(0 == ~T2_E~0); 43994#L512-1 assume !(0 == ~T3_E~0); 44073#L517-1 assume !(0 == ~T4_E~0); 43979#L522-1 assume 0 == ~E_1~0;~E_1~0 := 1; 43980#L527-1 assume !(0 == ~E_2~0); 44174#L532-1 assume !(0 == ~E_3~0); 44175#L537-1 assume !(0 == ~E_4~0); 44192#L542-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 44166#L238 assume !(1 == ~m_pc~0); 44167#L238-2 is_master_triggered_~__retres1~0#1 := 0; 44278#L249 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 44149#is_master_triggered_returnLabel#1 activate_threads_#t~ret10#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 44147#L615 assume !(0 != activate_threads_~tmp~1#1); 44148#L615-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 44289#L257 assume !(1 == ~t1_pc~0); 44463#L257-2 is_transmit1_triggered_~__retres1~1#1 := 0; 44462#L268 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 44461#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret11#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 44460#L623 assume !(0 != activate_threads_~tmp___0~0#1); 44006#L623-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 44007#L276 assume !(1 == ~t2_pc~0); 44269#L276-2 is_transmit2_triggered_~__retres1~2#1 := 0; 44452#L287 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 44450#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 44409#L631 assume !(0 != activate_threads_~tmp___1~0#1); 44410#L631-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 44449#L295 assume !(1 == ~t3_pc~0); 44448#L295-2 is_transmit3_triggered_~__retres1~3#1 := 0; 44447#L306 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 44446#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 44399#L639 assume !(0 != activate_threads_~tmp___2~0#1); 44400#L639-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 44445#L314 assume !(1 == ~t4_pc~0); 44029#L314-2 is_transmit4_triggered_~__retres1~4#1 := 0; 44028#L325 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 44444#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 44126#L647 assume !(0 != activate_threads_~tmp___3~0#1); 44127#L647-2 havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 44443#L555 assume !(1 == ~M_E~0); 44037#L555-2 assume !(1 == ~T1_E~0); 44038#L560-1 assume !(1 == ~T2_E~0); 44422#L565-1 assume !(1 == ~T3_E~0); 44133#L570-1 assume !(1 == ~T4_E~0); 44134#L575-1 assume 1 == ~E_1~0;~E_1~0 := 2; 44308#L580-1 assume !(1 == ~E_2~0); 44184#L585-1 assume !(1 == ~E_3~0); 44020#L590-1 assume !(1 == ~E_4~0); 44012#L595-1 assume { :end_inline_reset_delta_events } true; 44013#L776-2 [2023-11-12 02:12:04,452 INFO L750 eck$LassoCheckResult]: Loop: 44013#L776-2 assume !false; 45993#L777 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 45986#L477-1 assume !false; 45929#L412 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 45922#L374 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 45918#L401 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 45916#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 45911#L416 assume !(0 != eval_~tmp~0#1); 45912#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 46298#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 46296#L502-3 assume 0 == ~M_E~0;~M_E~0 := 1; 46294#L502-5 assume !(0 == ~T1_E~0); 46292#L507-3 assume !(0 == ~T2_E~0); 46290#L512-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 46288#L517-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 46286#L522-3 assume !(0 == ~E_1~0); 46284#L527-3 assume 0 == ~E_2~0;~E_2~0 := 1; 46282#L532-3 assume !(0 == ~E_3~0); 46280#L537-3 assume 0 == ~E_4~0;~E_4~0 := 1; 46278#L542-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 46276#L238-15 assume !(1 == ~m_pc~0); 46272#L238-17 is_master_triggered_~__retres1~0#1 := 0; 46270#L249-5 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 46268#is_master_triggered_returnLabel#6 activate_threads_#t~ret10#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 46266#L615-15 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 46263#L615-17 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 46260#L257-15 assume !(1 == ~t1_pc~0); 45654#L257-17 is_transmit1_triggered_~__retres1~1#1 := 0; 46256#L268-5 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 46253#is_transmit1_triggered_returnLabel#6 activate_threads_#t~ret11#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 46250#L623-15 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 46247#L623-17 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 46245#L276-15 assume 1 == ~t2_pc~0; 46240#L277-5 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 46235#L287-5 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 46230#is_transmit2_triggered_returnLabel#6 activate_threads_#t~ret12#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 46225#L631-15 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 46222#L631-17 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 46218#L295-15 assume !(1 == ~t3_pc~0); 44689#L295-17 is_transmit3_triggered_~__retres1~3#1 := 0; 46210#L306-5 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 46205#is_transmit3_triggered_returnLabel#6 activate_threads_#t~ret13#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 46201#L639-15 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 46197#L639-17 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 46194#L314-15 assume !(1 == ~t4_pc~0); 46188#L314-17 is_transmit4_triggered_~__retres1~4#1 := 0; 46185#L325-5 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 46181#is_transmit4_triggered_returnLabel#6 activate_threads_#t~ret14#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 46177#L647-15 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 46173#L647-17 havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 46168#L555-3 assume 1 == ~M_E~0;~M_E~0 := 2; 46164#L555-5 assume !(1 == ~T1_E~0); 46159#L560-3 assume !(1 == ~T2_E~0); 46153#L565-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 46147#L570-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 46141#L575-3 assume !(1 == ~E_1~0); 46137#L580-3 assume 1 == ~E_2~0;~E_2~0 := 2; 46133#L585-3 assume !(1 == ~E_3~0); 46130#L590-3 assume 1 == ~E_4~0;~E_4~0 := 2; 46126#L595-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 46122#L374-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 46115#L401-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 46111#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret16#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret16#1;havoc start_simulation_#t~ret16#1; 46105#L795 assume !(0 == start_simulation_~tmp~3#1); 46099#L795-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret15#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 46062#L374-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 46051#L401-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 46045#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret15#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret15#1;havoc stop_simulation_#t~ret15#1; 46041#L750 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 46037#L757 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 46034#stop_simulation_returnLabel#1 start_simulation_#t~ret17#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret15#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret17#1;havoc start_simulation_#t~ret17#1; 46030#L808 assume !(0 != start_simulation_~tmp___0~1#1); 44013#L776-2 [2023-11-12 02:12:04,452 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-12 02:12:04,452 INFO L85 PathProgramCache]: Analyzing trace with hash 119200679, now seen corresponding path program 1 times [2023-11-12 02:12:04,453 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-12 02:12:04,453 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [299234487] [2023-11-12 02:12:04,453 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-12 02:12:04,453 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-12 02:12:04,464 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-12 02:12:04,504 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-12 02:12:04,504 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-12 02:12:04,504 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [299234487] [2023-11-12 02:12:04,504 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [299234487] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-12 02:12:04,505 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-12 02:12:04,505 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-12 02:12:04,505 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1028294710] [2023-11-12 02:12:04,505 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-12 02:12:04,507 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-12 02:12:04,508 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-12 02:12:04,508 INFO L85 PathProgramCache]: Analyzing trace with hash 608280873, now seen corresponding path program 1 times [2023-11-12 02:12:04,508 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-12 02:12:04,508 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1939137820] [2023-11-12 02:12:04,508 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-12 02:12:04,508 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-12 02:12:04,520 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-12 02:12:04,592 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-12 02:12:04,593 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-12 02:12:04,594 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1939137820] [2023-11-12 02:12:04,594 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1939137820] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-12 02:12:04,594 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-12 02:12:04,594 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2023-11-12 02:12:04,594 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [349820862] [2023-11-12 02:12:04,595 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-12 02:12:04,595 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-12 02:12:04,595 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-12 02:12:04,596 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2023-11-12 02:12:04,596 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2023-11-12 02:12:04,596 INFO L87 Difference]: Start difference. First operand 3820 states and 5272 transitions. cyclomatic complexity: 1454 Second operand has 4 states, 4 states have (on average 15.0) internal successors, (60), 3 states have internal predecessors, (60), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-12 02:12:04,704 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-12 02:12:04,704 INFO L93 Difference]: Finished difference Result 5525 states and 7600 transitions. [2023-11-12 02:12:04,705 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 5525 states and 7600 transitions. [2023-11-12 02:12:04,733 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 5159 [2023-11-12 02:12:04,760 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 5525 states to 5525 states and 7600 transitions. [2023-11-12 02:12:04,760 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 5525 [2023-11-12 02:12:04,765 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 5525 [2023-11-12 02:12:04,766 INFO L73 IsDeterministic]: Start isDeterministic. Operand 5525 states and 7600 transitions. [2023-11-12 02:12:04,773 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-12 02:12:04,774 INFO L218 hiAutomatonCegarLoop]: Abstraction has 5525 states and 7600 transitions. [2023-11-12 02:12:04,781 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 5525 states and 7600 transitions. [2023-11-12 02:12:04,852 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 5525 to 3775. [2023-11-12 02:12:04,869 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 3775 states, 3775 states have (on average 1.3785430463576158) internal successors, (5204), 3774 states have internal predecessors, (5204), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-12 02:12:04,879 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3775 states to 3775 states and 5204 transitions. [2023-11-12 02:12:04,880 INFO L240 hiAutomatonCegarLoop]: Abstraction has 3775 states and 5204 transitions. [2023-11-12 02:12:04,888 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2023-11-12 02:12:04,889 INFO L428 stractBuchiCegarLoop]: Abstraction has 3775 states and 5204 transitions. [2023-11-12 02:12:04,889 INFO L335 stractBuchiCegarLoop]: ======== Iteration 15 ============ [2023-11-12 02:12:04,890 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 3775 states and 5204 transitions. [2023-11-12 02:12:04,904 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 3706 [2023-11-12 02:12:04,904 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-12 02:12:04,905 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-12 02:12:04,906 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-12 02:12:04,906 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-12 02:12:04,907 INFO L748 eck$LassoCheckResult]: Stem: 53524#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2; 53525#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~6#1;havoc main_~__retres1~6#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 53614#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret16#1, start_simulation_#t~ret17#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 53615#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 53425#L341 assume 1 == ~m_i~0;~m_st~0 := 0; 53426#L341-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 53653#L346-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 53522#L351-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 53360#L356-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 53361#L361-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 53379#L502 assume !(0 == ~M_E~0); 53380#L502-2 assume !(0 == ~T1_E~0); 53349#L507-1 assume !(0 == ~T2_E~0); 53350#L512-1 assume !(0 == ~T3_E~0); 53428#L517-1 assume !(0 == ~T4_E~0); 53336#L522-1 assume !(0 == ~E_1~0); 53337#L527-1 assume !(0 == ~E_2~0); 53527#L532-1 assume !(0 == ~E_3~0); 53528#L537-1 assume !(0 == ~E_4~0); 53550#L542-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 53520#L238 assume !(1 == ~m_pc~0); 53521#L238-2 is_master_triggered_~__retres1~0#1 := 0; 53581#L249 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 53503#is_master_triggered_returnLabel#1 activate_threads_#t~ret10#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 53501#L615 assume !(0 != activate_threads_~tmp~1#1); 53502#L615-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 53484#L257 assume !(1 == ~t1_pc~0); 53485#L257-2 is_transmit1_triggered_~__retres1~1#1 := 0; 53519#L268 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 53377#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret11#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 53378#L623 assume !(0 != activate_threads_~tmp___0~0#1); 53362#L623-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 53363#L276 assume !(1 == ~t2_pc~0); 53623#L276-2 is_transmit2_triggered_~__retres1~2#1 := 0; 53726#L287 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 53621#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 53622#L631 assume !(0 != activate_threads_~tmp___1~0#1); 53777#L631-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 53500#L295 assume !(1 == ~t3_pc~0); 53366#L295-2 is_transmit3_triggered_~__retres1~3#1 := 0; 53367#L306 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 53329#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 53330#L639 assume !(0 != activate_threads_~tmp___2~0#1); 53758#L639-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 53759#L314 assume !(1 == ~t4_pc~0); 53385#L314-2 is_transmit4_triggered_~__retres1~4#1 := 0; 53384#L325 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 53418#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 53419#L647 assume !(0 != activate_threads_~tmp___3~0#1); 53483#L647-2 havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 53720#L555 assume !(1 == ~M_E~0); 53393#L555-2 assume !(1 == ~T1_E~0); 53394#L560-1 assume !(1 == ~T2_E~0); 53338#L565-1 assume !(1 == ~T3_E~0); 53339#L570-1 assume !(1 == ~T4_E~0); 53490#L575-1 assume !(1 == ~E_1~0); 53659#L580-1 assume !(1 == ~E_2~0); 53542#L585-1 assume !(1 == ~E_3~0); 53376#L590-1 assume !(1 == ~E_4~0); 53368#L595-1 assume { :end_inline_reset_delta_events } true; 53369#L776-2 [2023-11-12 02:12:04,907 INFO L750 eck$LassoCheckResult]: Loop: 53369#L776-2 assume !false; 55744#L777 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 55738#L477-1 assume !false; 55737#L412 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 55731#L374 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 55720#L401 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 55717#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 55713#L416 assume !(0 != eval_~tmp~0#1); 55714#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 57053#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 57051#L502-3 assume 0 == ~M_E~0;~M_E~0 := 1; 57050#L502-5 assume !(0 == ~T1_E~0); 57048#L507-3 assume !(0 == ~T2_E~0); 57047#L512-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 57046#L517-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 57045#L522-3 assume !(0 == ~E_1~0); 57044#L527-3 assume 0 == ~E_2~0;~E_2~0 := 1; 57042#L532-3 assume !(0 == ~E_3~0); 57040#L537-3 assume 0 == ~E_4~0;~E_4~0 := 1; 57038#L542-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 57036#L238-15 assume !(1 == ~m_pc~0); 57028#L238-17 is_master_triggered_~__retres1~0#1 := 0; 56984#L249-5 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 56924#is_master_triggered_returnLabel#6 activate_threads_#t~ret10#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 56922#L615-15 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 56921#L615-17 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 56920#L257-15 assume !(1 == ~t1_pc~0); 56897#L257-17 is_transmit1_triggered_~__retres1~1#1 := 0; 56898#L268-5 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 55868#is_transmit1_triggered_returnLabel#6 activate_threads_#t~ret11#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 55869#L623-15 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 55858#L623-17 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 55859#L276-15 assume 1 == ~t2_pc~0; 55852#L277-5 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 53693#L287-5 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 53694#is_transmit2_triggered_returnLabel#6 activate_threads_#t~ret12#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 53789#L631-15 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 55837#L631-17 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 55832#L295-15 assume !(1 == ~t3_pc~0); 55830#L295-17 is_transmit3_triggered_~__retres1~3#1 := 0; 55828#L306-5 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 55826#is_transmit3_triggered_returnLabel#6 activate_threads_#t~ret13#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 55824#L639-15 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 55821#L639-17 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 55818#L314-15 assume !(1 == ~t4_pc~0); 55813#L314-17 is_transmit4_triggered_~__retres1~4#1 := 0; 55810#L325-5 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 55807#is_transmit4_triggered_returnLabel#6 activate_threads_#t~ret14#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 55804#L647-15 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 55801#L647-17 havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 55797#L555-3 assume 1 == ~M_E~0;~M_E~0 := 2; 55794#L555-5 assume !(1 == ~T1_E~0); 55791#L560-3 assume !(1 == ~T2_E~0); 55788#L565-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 55785#L570-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 55782#L575-3 assume !(1 == ~E_1~0); 55780#L580-3 assume 1 == ~E_2~0;~E_2~0 := 2; 55778#L585-3 assume !(1 == ~E_3~0); 55776#L590-3 assume 1 == ~E_4~0;~E_4~0 := 2; 55774#L595-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 55771#L374-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 55766#L401-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 55764#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret16#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret16#1;havoc start_simulation_#t~ret16#1; 55761#L795 assume !(0 == start_simulation_~tmp~3#1); 55759#L795-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret15#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 55758#L374-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 55753#L401-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 55752#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret15#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret15#1;havoc stop_simulation_#t~ret15#1; 55751#L750 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 55750#L757 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 55749#stop_simulation_returnLabel#1 start_simulation_#t~ret17#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret15#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret17#1;havoc start_simulation_#t~ret17#1; 55748#L808 assume !(0 != start_simulation_~tmp___0~1#1); 53369#L776-2 [2023-11-12 02:12:04,907 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-12 02:12:04,908 INFO L85 PathProgramCache]: Analyzing trace with hash 1014534059, now seen corresponding path program 2 times [2023-11-12 02:12:04,908 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-12 02:12:04,908 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [16937619] [2023-11-12 02:12:04,908 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-12 02:12:04,908 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-12 02:12:04,925 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-12 02:12:04,925 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-12 02:12:04,938 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-12 02:12:04,965 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-12 02:12:04,966 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-12 02:12:04,967 INFO L85 PathProgramCache]: Analyzing trace with hash 608280873, now seen corresponding path program 2 times [2023-11-12 02:12:04,967 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-12 02:12:04,967 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [384343589] [2023-11-12 02:12:04,967 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-12 02:12:04,967 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-12 02:12:04,977 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-12 02:12:05,024 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-12 02:12:05,024 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-12 02:12:05,024 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [384343589] [2023-11-12 02:12:05,025 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [384343589] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-12 02:12:05,025 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-12 02:12:05,025 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2023-11-12 02:12:05,025 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1484183606] [2023-11-12 02:12:05,025 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-12 02:12:05,026 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-12 02:12:05,026 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-12 02:12:05,026 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2023-11-12 02:12:05,026 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2023-11-12 02:12:05,027 INFO L87 Difference]: Start difference. First operand 3775 states and 5204 transitions. cyclomatic complexity: 1431 Second operand has 5 states, 5 states have (on average 14.4) internal successors, (72), 5 states have internal predecessors, (72), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-12 02:12:05,188 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-12 02:12:05,189 INFO L93 Difference]: Finished difference Result 6585 states and 8994 transitions. [2023-11-12 02:12:05,189 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 6585 states and 8994 transitions. [2023-11-12 02:12:05,220 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 6512 [2023-11-12 02:12:05,245 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 6585 states to 6585 states and 8994 transitions. [2023-11-12 02:12:05,245 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 6585 [2023-11-12 02:12:05,252 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 6585 [2023-11-12 02:12:05,252 INFO L73 IsDeterministic]: Start isDeterministic. Operand 6585 states and 8994 transitions. [2023-11-12 02:12:05,259 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-12 02:12:05,259 INFO L218 hiAutomatonCegarLoop]: Abstraction has 6585 states and 8994 transitions. [2023-11-12 02:12:05,267 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 6585 states and 8994 transitions. [2023-11-12 02:12:05,332 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 6585 to 3823. [2023-11-12 02:12:05,338 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 3823 states, 3823 states have (on average 1.373790217106984) internal successors, (5252), 3822 states have internal predecessors, (5252), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-12 02:12:05,350 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3823 states to 3823 states and 5252 transitions. [2023-11-12 02:12:05,350 INFO L240 hiAutomatonCegarLoop]: Abstraction has 3823 states and 5252 transitions. [2023-11-12 02:12:05,351 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 9 states. [2023-11-12 02:12:05,352 INFO L428 stractBuchiCegarLoop]: Abstraction has 3823 states and 5252 transitions. [2023-11-12 02:12:05,352 INFO L335 stractBuchiCegarLoop]: ======== Iteration 16 ============ [2023-11-12 02:12:05,352 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 3823 states and 5252 transitions. [2023-11-12 02:12:05,367 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 3754 [2023-11-12 02:12:05,368 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-12 02:12:05,368 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-12 02:12:05,370 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-12 02:12:05,370 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-12 02:12:05,371 INFO L748 eck$LassoCheckResult]: Stem: 63901#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2; 63902#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~6#1;havoc main_~__retres1~6#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 63989#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret16#1, start_simulation_#t~ret17#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 63990#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 63802#L341 assume 1 == ~m_i~0;~m_st~0 := 0; 63803#L341-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 64029#L346-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 63899#L351-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 63737#L356-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 63738#L361-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 63756#L502 assume !(0 == ~M_E~0); 63757#L502-2 assume !(0 == ~T1_E~0); 63723#L507-1 assume !(0 == ~T2_E~0); 63724#L512-1 assume !(0 == ~T3_E~0); 63804#L517-1 assume !(0 == ~T4_E~0); 63711#L522-1 assume !(0 == ~E_1~0); 63712#L527-1 assume !(0 == ~E_2~0); 63905#L532-1 assume !(0 == ~E_3~0); 63906#L537-1 assume !(0 == ~E_4~0); 63925#L542-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 63897#L238 assume !(1 == ~m_pc~0); 63898#L238-2 is_master_triggered_~__retres1~0#1 := 0; 63956#L249 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 63880#is_master_triggered_returnLabel#1 activate_threads_#t~ret10#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 63878#L615 assume !(0 != activate_threads_~tmp~1#1); 63879#L615-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 63862#L257 assume !(1 == ~t1_pc~0); 63863#L257-2 is_transmit1_triggered_~__retres1~1#1 := 0; 63895#L268 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 63754#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret11#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 63755#L623 assume !(0 != activate_threads_~tmp___0~0#1); 63739#L623-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 63740#L276 assume !(1 == ~t2_pc~0); 63998#L276-2 is_transmit2_triggered_~__retres1~2#1 := 0; 64099#L287 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 63996#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 63997#L631 assume !(0 != activate_threads_~tmp___1~0#1); 64153#L631-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 63877#L295 assume !(1 == ~t3_pc~0); 63743#L295-2 is_transmit3_triggered_~__retres1~3#1 := 0; 63744#L306 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 63706#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 63707#L639 assume !(0 != activate_threads_~tmp___2~0#1); 64137#L639-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 64138#L314 assume !(1 == ~t4_pc~0); 63762#L314-2 is_transmit4_triggered_~__retres1~4#1 := 0; 63761#L325 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 63794#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 63795#L647 assume !(0 != activate_threads_~tmp___3~0#1); 63861#L647-2 havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 64094#L555 assume !(1 == ~M_E~0); 63770#L555-2 assume !(1 == ~T1_E~0); 63771#L560-1 assume !(1 == ~T2_E~0); 63713#L565-1 assume !(1 == ~T3_E~0); 63714#L570-1 assume !(1 == ~T4_E~0); 63867#L575-1 assume !(1 == ~E_1~0); 64035#L580-1 assume !(1 == ~E_2~0); 63917#L585-1 assume !(1 == ~E_3~0); 63751#L590-1 assume !(1 == ~E_4~0); 63745#L595-1 assume { :end_inline_reset_delta_events } true; 63746#L776-2 [2023-11-12 02:12:05,371 INFO L750 eck$LassoCheckResult]: Loop: 63746#L776-2 assume !false; 66041#L777 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 65900#L477-1 assume !false; 65823#L412 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 65818#L374 assume !(0 == ~m_st~0); 65819#L378 assume !(0 == ~t1_st~0); 65821#L382 assume !(0 == ~t2_st~0); 65816#L386 assume !(0 == ~t3_st~0); 65817#L390 assume !(0 == ~t4_st~0);exists_runnable_thread_~__retres1~5#1 := 0; 65820#L401 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 64898#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 64899#L416 assume !(0 != eval_~tmp~0#1); 65790#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 66269#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 66266#L502-3 assume 0 == ~M_E~0;~M_E~0 := 1; 66263#L502-5 assume !(0 == ~T1_E~0); 66260#L507-3 assume !(0 == ~T2_E~0); 66257#L512-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 66254#L517-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 66251#L522-3 assume !(0 == ~E_1~0); 66248#L527-3 assume 0 == ~E_2~0;~E_2~0 := 1; 66245#L532-3 assume !(0 == ~E_3~0); 66242#L537-3 assume 0 == ~E_4~0;~E_4~0 := 1; 66239#L542-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 66237#L238-15 assume !(1 == ~m_pc~0); 66233#L238-17 is_master_triggered_~__retres1~0#1 := 0; 66227#L249-5 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 66221#is_master_triggered_returnLabel#6 activate_threads_#t~ret10#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 66215#L615-15 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 66209#L615-17 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 66202#L257-15 assume !(1 == ~t1_pc~0); 66200#L257-17 is_transmit1_triggered_~__retres1~1#1 := 0; 66196#L268-5 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 66192#is_transmit1_triggered_returnLabel#6 activate_threads_#t~ret11#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 66188#L623-15 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 66184#L623-17 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 66180#L276-15 assume !(1 == ~t2_pc~0); 66173#L276-17 is_transmit2_triggered_~__retres1~2#1 := 0; 66165#L287-5 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 66157#is_transmit2_triggered_returnLabel#6 activate_threads_#t~ret12#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 66149#L631-15 assume !(0 != activate_threads_~tmp___1~0#1); 66144#L631-17 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 66138#L295-15 assume !(1 == ~t3_pc~0); 66136#L295-17 is_transmit3_triggered_~__retres1~3#1 := 0; 66134#L306-5 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 66132#is_transmit3_triggered_returnLabel#6 activate_threads_#t~ret13#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 66130#L639-15 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 66128#L639-17 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 66126#L314-15 assume 1 == ~t4_pc~0; 66123#L315-5 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 66120#L325-5 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 66118#is_transmit4_triggered_returnLabel#6 activate_threads_#t~ret14#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 66116#L647-15 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 66114#L647-17 havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 66112#L555-3 assume 1 == ~M_E~0;~M_E~0 := 2; 66110#L555-5 assume !(1 == ~T1_E~0); 66108#L560-3 assume !(1 == ~T2_E~0); 66106#L565-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 66104#L570-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 66102#L575-3 assume !(1 == ~E_1~0); 66101#L580-3 assume 1 == ~E_2~0;~E_2~0 := 2; 66100#L585-3 assume !(1 == ~E_3~0); 66099#L590-3 assume 1 == ~E_4~0;~E_4~0 := 2; 66098#L595-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 66096#L374-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 66090#L401-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 66086#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret16#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret16#1;havoc start_simulation_#t~ret16#1; 66082#L795 assume !(0 == start_simulation_~tmp~3#1); 66079#L795-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret15#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 66078#L374-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 66072#L401-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 66070#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret15#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret15#1;havoc stop_simulation_#t~ret15#1; 66066#L750 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 66064#L757 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 66062#stop_simulation_returnLabel#1 start_simulation_#t~ret17#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret15#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret17#1;havoc start_simulation_#t~ret17#1; 66057#L808 assume !(0 != start_simulation_~tmp___0~1#1); 63746#L776-2 [2023-11-12 02:12:05,372 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-12 02:12:05,372 INFO L85 PathProgramCache]: Analyzing trace with hash 1014534059, now seen corresponding path program 3 times [2023-11-12 02:12:05,372 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-12 02:12:05,373 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [970745372] [2023-11-12 02:12:05,373 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-12 02:12:05,373 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-12 02:12:05,385 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-12 02:12:05,385 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-12 02:12:05,392 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-12 02:12:05,407 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-12 02:12:05,407 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-12 02:12:05,408 INFO L85 PathProgramCache]: Analyzing trace with hash -1321180837, now seen corresponding path program 1 times [2023-11-12 02:12:05,408 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-12 02:12:05,408 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2074791067] [2023-11-12 02:12:05,408 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-12 02:12:05,409 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-12 02:12:05,422 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-12 02:12:05,490 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-12 02:12:05,491 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-12 02:12:05,491 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2074791067] [2023-11-12 02:12:05,491 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2074791067] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-12 02:12:05,491 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-12 02:12:05,491 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2023-11-12 02:12:05,492 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2043967473] [2023-11-12 02:12:05,492 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-12 02:12:05,492 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-12 02:12:05,492 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-12 02:12:05,493 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2023-11-12 02:12:05,493 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2023-11-12 02:12:05,493 INFO L87 Difference]: Start difference. First operand 3823 states and 5252 transitions. cyclomatic complexity: 1431 Second operand has 5 states, 5 states have (on average 15.2) internal successors, (76), 5 states have internal predecessors, (76), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-12 02:12:05,673 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-12 02:12:05,673 INFO L93 Difference]: Finished difference Result 6763 states and 9153 transitions. [2023-11-12 02:12:05,673 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 6763 states and 9153 transitions. [2023-11-12 02:12:05,708 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 6694 [2023-11-12 02:12:05,736 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 6763 states to 6763 states and 9153 transitions. [2023-11-12 02:12:05,736 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 6763 [2023-11-12 02:12:05,743 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 6763 [2023-11-12 02:12:05,744 INFO L73 IsDeterministic]: Start isDeterministic. Operand 6763 states and 9153 transitions. [2023-11-12 02:12:05,750 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-12 02:12:05,751 INFO L218 hiAutomatonCegarLoop]: Abstraction has 6763 states and 9153 transitions. [2023-11-12 02:12:05,760 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 6763 states and 9153 transitions. [2023-11-12 02:12:05,824 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 6763 to 3919. [2023-11-12 02:12:05,831 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 3919 states, 3919 states have (on average 1.357233988262312) internal successors, (5319), 3918 states have internal predecessors, (5319), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-12 02:12:05,841 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3919 states to 3919 states and 5319 transitions. [2023-11-12 02:12:05,842 INFO L240 hiAutomatonCegarLoop]: Abstraction has 3919 states and 5319 transitions. [2023-11-12 02:12:05,842 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2023-11-12 02:12:05,843 INFO L428 stractBuchiCegarLoop]: Abstraction has 3919 states and 5319 transitions. [2023-11-12 02:12:05,843 INFO L335 stractBuchiCegarLoop]: ======== Iteration 17 ============ [2023-11-12 02:12:05,843 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 3919 states and 5319 transitions. [2023-11-12 02:12:05,857 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 3850 [2023-11-12 02:12:05,858 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-12 02:12:05,858 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-12 02:12:05,860 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-12 02:12:05,860 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-12 02:12:05,860 INFO L748 eck$LassoCheckResult]: Stem: 74502#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2; 74503#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~6#1;havoc main_~__retres1~6#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 74594#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret16#1, start_simulation_#t~ret17#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 74595#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 74399#L341 assume 1 == ~m_i~0;~m_st~0 := 0; 74400#L341-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 74635#L346-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 74499#L351-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 74335#L356-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 74336#L361-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 74354#L502 assume !(0 == ~M_E~0); 74355#L502-2 assume !(0 == ~T1_E~0); 74321#L507-1 assume !(0 == ~T2_E~0); 74322#L512-1 assume !(0 == ~T3_E~0); 74401#L517-1 assume !(0 == ~T4_E~0); 74309#L522-1 assume !(0 == ~E_1~0); 74310#L527-1 assume !(0 == ~E_2~0); 74505#L532-1 assume !(0 == ~E_3~0); 74506#L537-1 assume !(0 == ~E_4~0); 74527#L542-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 74497#L238 assume !(1 == ~m_pc~0); 74498#L238-2 is_master_triggered_~__retres1~0#1 := 0; 74559#L249 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 74479#is_master_triggered_returnLabel#1 activate_threads_#t~ret10#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 74477#L615 assume !(0 != activate_threads_~tmp~1#1); 74478#L615-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 74460#L257 assume !(1 == ~t1_pc~0); 74461#L257-2 is_transmit1_triggered_~__retres1~1#1 := 0; 74494#L268 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 74352#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret11#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 74353#L623 assume !(0 != activate_threads_~tmp___0~0#1); 74337#L623-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 74338#L276 assume !(1 == ~t2_pc~0); 74604#L276-2 is_transmit2_triggered_~__retres1~2#1 := 0; 74705#L287 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 74602#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 74603#L631 assume !(0 != activate_threads_~tmp___1~0#1); 74751#L631-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 74476#L295 assume !(1 == ~t3_pc~0); 74341#L295-2 is_transmit3_triggered_~__retres1~3#1 := 0; 74342#L306 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 74304#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 74305#L639 assume !(0 != activate_threads_~tmp___2~0#1); 74735#L639-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 74736#L314 assume !(1 == ~t4_pc~0); 74360#L314-2 is_transmit4_triggered_~__retres1~4#1 := 0; 74359#L325 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 74391#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 74392#L647 assume !(0 != activate_threads_~tmp___3~0#1); 74459#L647-2 havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 74701#L555 assume !(1 == ~M_E~0); 74368#L555-2 assume !(1 == ~T1_E~0); 74369#L560-1 assume !(1 == ~T2_E~0); 74311#L565-1 assume !(1 == ~T3_E~0); 74312#L570-1 assume !(1 == ~T4_E~0); 74466#L575-1 assume !(1 == ~E_1~0); 74641#L580-1 assume !(1 == ~E_2~0); 74519#L585-1 assume !(1 == ~E_3~0); 74349#L590-1 assume !(1 == ~E_4~0); 74343#L595-1 assume { :end_inline_reset_delta_events } true; 74344#L776-2 [2023-11-12 02:12:05,861 INFO L750 eck$LassoCheckResult]: Loop: 74344#L776-2 assume !false; 75183#L777 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 75175#L477-1 assume !false; 75167#L412 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 75159#L374 assume !(0 == ~m_st~0); 75151#L378 assume !(0 == ~t1_st~0); 75143#L382 assume !(0 == ~t2_st~0); 75129#L386 assume !(0 == ~t3_st~0); 75119#L390 assume !(0 == ~t4_st~0);exists_runnable_thread_~__retres1~5#1 := 0; 75111#L401 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 75097#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 75087#L416 assume !(0 != eval_~tmp~0#1); 75079#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 75071#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 75063#L502-3 assume 0 == ~M_E~0;~M_E~0 := 1; 75055#L502-5 assume !(0 == ~T1_E~0); 75047#L507-3 assume !(0 == ~T2_E~0); 75039#L512-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 75031#L517-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 75023#L522-3 assume !(0 == ~E_1~0); 75015#L527-3 assume 0 == ~E_2~0;~E_2~0 := 1; 75007#L532-3 assume !(0 == ~E_3~0); 74999#L537-3 assume 0 == ~E_4~0;~E_4~0 := 1; 74991#L542-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 74983#L238-15 assume !(1 == ~m_pc~0); 74975#L238-17 is_master_triggered_~__retres1~0#1 := 0; 74967#L249-5 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 74959#is_master_triggered_returnLabel#6 activate_threads_#t~ret10#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 74951#L615-15 assume !(0 != activate_threads_~tmp~1#1); 74944#L615-17 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 74934#L257-15 assume !(1 == ~t1_pc~0); 74926#L257-17 is_transmit1_triggered_~__retres1~1#1 := 0; 74927#L268-5 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 74915#is_transmit1_triggered_returnLabel#6 activate_threads_#t~ret11#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 74916#L623-15 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 74904#L623-17 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 74905#L276-15 assume !(1 == ~t2_pc~0); 74885#L276-17 is_transmit2_triggered_~__retres1~2#1 := 0; 74887#L287-5 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 76194#is_transmit2_triggered_returnLabel#6 activate_threads_#t~ret12#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 76192#L631-15 assume !(0 != activate_threads_~tmp___1~0#1); 76190#L631-17 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 76188#L295-15 assume !(1 == ~t3_pc~0); 76078#L295-17 is_transmit3_triggered_~__retres1~3#1 := 0; 76185#L306-5 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 76170#is_transmit3_triggered_returnLabel#6 activate_threads_#t~ret13#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 76158#L639-15 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 76152#L639-17 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 76146#L314-15 assume 1 == ~t4_pc~0; 76141#L315-5 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 76135#L325-5 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 76129#is_transmit4_triggered_returnLabel#6 activate_threads_#t~ret14#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 75717#L647-15 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 75715#L647-17 havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 75713#L555-3 assume 1 == ~M_E~0;~M_E~0 := 2; 75711#L555-5 assume !(1 == ~T1_E~0); 75710#L560-3 assume !(1 == ~T2_E~0); 75709#L565-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 75708#L570-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 75706#L575-3 assume !(1 == ~E_1~0); 75703#L580-3 assume 1 == ~E_2~0;~E_2~0 := 2; 75701#L585-3 assume !(1 == ~E_3~0); 75699#L590-3 assume 1 == ~E_4~0;~E_4~0 := 2; 75697#L595-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 75690#L374-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 75685#L401-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 75683#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret16#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret16#1;havoc start_simulation_#t~ret16#1; 75392#L795 assume !(0 == start_simulation_~tmp~3#1); 75388#L795-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret15#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 75232#L374-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 75227#L401-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 75225#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret15#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret15#1;havoc stop_simulation_#t~ret15#1; 75223#L750 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 75221#L757 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 75220#stop_simulation_returnLabel#1 start_simulation_#t~ret17#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret15#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret17#1;havoc start_simulation_#t~ret17#1; 75217#L808 assume !(0 != start_simulation_~tmp___0~1#1); 74344#L776-2 [2023-11-12 02:12:05,861 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-12 02:12:05,861 INFO L85 PathProgramCache]: Analyzing trace with hash 1014534059, now seen corresponding path program 4 times [2023-11-12 02:12:05,862 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-12 02:12:05,862 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1854859308] [2023-11-12 02:12:05,862 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-12 02:12:05,862 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-12 02:12:05,872 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-12 02:12:05,872 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-12 02:12:05,878 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-12 02:12:05,887 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-12 02:12:05,888 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-12 02:12:05,888 INFO L85 PathProgramCache]: Analyzing trace with hash 617981209, now seen corresponding path program 1 times [2023-11-12 02:12:05,888 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-12 02:12:05,889 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1950129806] [2023-11-12 02:12:05,889 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-12 02:12:05,889 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-12 02:12:05,898 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-12 02:12:05,948 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-12 02:12:05,949 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-12 02:12:05,949 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1950129806] [2023-11-12 02:12:05,949 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1950129806] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-12 02:12:05,949 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-12 02:12:05,950 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-12 02:12:05,950 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [562706418] [2023-11-12 02:12:05,950 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-12 02:12:05,950 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-12 02:12:05,950 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-12 02:12:05,951 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-12 02:12:05,951 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-12 02:12:05,951 INFO L87 Difference]: Start difference. First operand 3919 states and 5319 transitions. cyclomatic complexity: 1402 Second operand has 3 states, 3 states have (on average 25.333333333333332) internal successors, (76), 3 states have internal predecessors, (76), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-12 02:12:06,014 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-12 02:12:06,014 INFO L93 Difference]: Finished difference Result 6558 states and 8787 transitions. [2023-11-12 02:12:06,014 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 6558 states and 8787 transitions. [2023-11-12 02:12:06,047 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 6487 [2023-11-12 02:12:06,072 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 6558 states to 6558 states and 8787 transitions. [2023-11-12 02:12:06,073 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 6558 [2023-11-12 02:12:06,080 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 6558 [2023-11-12 02:12:06,080 INFO L73 IsDeterministic]: Start isDeterministic. Operand 6558 states and 8787 transitions. [2023-11-12 02:12:06,087 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-12 02:12:06,087 INFO L218 hiAutomatonCegarLoop]: Abstraction has 6558 states and 8787 transitions. [2023-11-12 02:12:06,096 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 6558 states and 8787 transitions. [2023-11-12 02:12:06,176 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 6558 to 6424. [2023-11-12 02:12:06,185 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 6424 states, 6424 states have (on average 1.341376089663761) internal successors, (8617), 6423 states have internal predecessors, (8617), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-12 02:12:06,203 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 6424 states to 6424 states and 8617 transitions. [2023-11-12 02:12:06,204 INFO L240 hiAutomatonCegarLoop]: Abstraction has 6424 states and 8617 transitions. [2023-11-12 02:12:06,204 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-12 02:12:06,205 INFO L428 stractBuchiCegarLoop]: Abstraction has 6424 states and 8617 transitions. [2023-11-12 02:12:06,205 INFO L335 stractBuchiCegarLoop]: ======== Iteration 18 ============ [2023-11-12 02:12:06,205 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 6424 states and 8617 transitions. [2023-11-12 02:12:06,230 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 6353 [2023-11-12 02:12:06,230 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-12 02:12:06,230 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-12 02:12:06,231 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-12 02:12:06,231 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-12 02:12:06,231 INFO L748 eck$LassoCheckResult]: Stem: 84982#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2; 84983#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~6#1;havoc main_~__retres1~6#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 85070#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret16#1, start_simulation_#t~ret17#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 85071#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 84882#L341 assume 1 == ~m_i~0;~m_st~0 := 0; 84883#L341-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 85108#L346-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 84980#L351-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 84818#L356-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 84819#L361-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 84837#L502 assume !(0 == ~M_E~0); 84838#L502-2 assume !(0 == ~T1_E~0); 84807#L507-1 assume !(0 == ~T2_E~0); 84808#L512-1 assume !(0 == ~T3_E~0); 84885#L517-1 assume !(0 == ~T4_E~0); 84792#L522-1 assume !(0 == ~E_1~0); 84793#L527-1 assume !(0 == ~E_2~0); 84985#L532-1 assume !(0 == ~E_3~0); 84986#L537-1 assume !(0 == ~E_4~0); 85006#L542-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 84978#L238 assume !(1 == ~m_pc~0); 84979#L238-2 is_master_triggered_~__retres1~0#1 := 0; 85039#L249 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 84959#is_master_triggered_returnLabel#1 activate_threads_#t~ret10#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 84957#L615 assume !(0 != activate_threads_~tmp~1#1); 84958#L615-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 84940#L257 assume !(1 == ~t1_pc~0); 84941#L257-2 is_transmit1_triggered_~__retres1~1#1 := 0; 84977#L268 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 84835#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret11#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 84836#L623 assume !(0 != activate_threads_~tmp___0~0#1); 84820#L623-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 84821#L276 assume !(1 == ~t2_pc~0); 85080#L276-2 is_transmit2_triggered_~__retres1~2#1 := 0; 85182#L287 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 85078#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 85079#L631 assume !(0 != activate_threads_~tmp___1~0#1); 85226#L631-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 84956#L295 assume !(1 == ~t3_pc~0); 84824#L295-2 is_transmit3_triggered_~__retres1~3#1 := 0; 84825#L306 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 84787#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 84788#L639 assume !(0 != activate_threads_~tmp___2~0#1); 85212#L639-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 85213#L314 assume !(1 == ~t4_pc~0); 84843#L314-2 is_transmit4_triggered_~__retres1~4#1 := 0; 84842#L325 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 84875#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 84876#L647 assume !(0 != activate_threads_~tmp___3~0#1); 84939#L647-2 havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 85178#L555 assume !(1 == ~M_E~0); 84851#L555-2 assume !(1 == ~T1_E~0); 84852#L560-1 assume !(1 == ~T2_E~0); 84794#L565-1 assume !(1 == ~T3_E~0); 84795#L570-1 assume !(1 == ~T4_E~0); 84946#L575-1 assume !(1 == ~E_1~0); 85115#L580-1 assume !(1 == ~E_2~0); 84999#L585-1 assume !(1 == ~E_3~0); 84834#L590-1 assume !(1 == ~E_4~0); 84826#L595-1 assume { :end_inline_reset_delta_events } true; 84827#L776-2 assume !false; 85326#L777 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 85324#L477-1 [2023-11-12 02:12:06,232 INFO L750 eck$LassoCheckResult]: Loop: 85324#L477-1 assume !false; 85322#L412 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 85318#L374 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 85314#L401 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 85315#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 88752#L416 assume 0 != eval_~tmp~0#1; 89512#L416-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;havoc eval_#t~nondet5#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet5#1;havoc eval_#t~nondet5#1; 85295#L424 assume !(0 != eval_~tmp_ndt_1~0#1); 85165#L424-2 havoc eval_~tmp_ndt_1~0#1; 85166#L421-1 assume !(0 == ~t1_st~0); 90076#L435-1 assume !(0 == ~t2_st~0); 90073#L449-1 assume !(0 == ~t3_st~0); 85170#L463-1 assume !(0 == ~t4_st~0); 85324#L477-1 [2023-11-12 02:12:06,232 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-12 02:12:06,232 INFO L85 PathProgramCache]: Analyzing trace with hash 9663309, now seen corresponding path program 1 times [2023-11-12 02:12:06,233 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-12 02:12:06,233 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [150448562] [2023-11-12 02:12:06,233 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-12 02:12:06,233 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-12 02:12:06,243 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-12 02:12:06,243 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-12 02:12:06,250 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-12 02:12:06,260 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-12 02:12:06,261 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-12 02:12:06,261 INFO L85 PathProgramCache]: Analyzing trace with hash 105152312, now seen corresponding path program 1 times [2023-11-12 02:12:06,261 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-12 02:12:06,261 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [739871960] [2023-11-12 02:12:06,262 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-12 02:12:06,262 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-12 02:12:06,266 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-12 02:12:06,266 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-12 02:12:06,268 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-12 02:12:06,270 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-12 02:12:06,271 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-12 02:12:06,271 INFO L85 PathProgramCache]: Analyzing trace with hash 2080098156, now seen corresponding path program 1 times [2023-11-12 02:12:06,271 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-12 02:12:06,271 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1416208256] [2023-11-12 02:12:06,272 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-12 02:12:06,272 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-12 02:12:06,282 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-12 02:12:06,314 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-12 02:12:06,314 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-12 02:12:06,314 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1416208256] [2023-11-12 02:12:06,314 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1416208256] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-12 02:12:06,314 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-12 02:12:06,315 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-12 02:12:06,315 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [123192714] [2023-11-12 02:12:06,315 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-12 02:12:06,404 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-12 02:12:06,405 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-12 02:12:06,405 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-12 02:12:06,405 INFO L87 Difference]: Start difference. First operand 6424 states and 8617 transitions. cyclomatic complexity: 2197 Second operand has 3 states, 3 states have (on average 25.0) internal successors, (75), 3 states have internal predecessors, (75), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-12 02:12:06,488 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-12 02:12:06,488 INFO L93 Difference]: Finished difference Result 11876 states and 15795 transitions. [2023-11-12 02:12:06,488 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 11876 states and 15795 transitions. [2023-11-12 02:12:06,543 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 11740 [2023-11-12 02:12:06,586 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 11876 states to 11876 states and 15795 transitions. [2023-11-12 02:12:06,586 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 11876 [2023-11-12 02:12:06,599 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 11876 [2023-11-12 02:12:06,599 INFO L73 IsDeterministic]: Start isDeterministic. Operand 11876 states and 15795 transitions. [2023-11-12 02:12:06,610 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-12 02:12:06,610 INFO L218 hiAutomatonCegarLoop]: Abstraction has 11876 states and 15795 transitions. [2023-11-12 02:12:06,624 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 11876 states and 15795 transitions. [2023-11-12 02:12:06,936 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 11876 to 11436. [2023-11-12 02:12:06,952 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 11436 states, 11436 states have (on average 1.3321965722280518) internal successors, (15235), 11435 states have internal predecessors, (15235), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-12 02:12:06,990 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 11436 states to 11436 states and 15235 transitions. [2023-11-12 02:12:06,990 INFO L240 hiAutomatonCegarLoop]: Abstraction has 11436 states and 15235 transitions. [2023-11-12 02:12:06,991 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-12 02:12:06,992 INFO L428 stractBuchiCegarLoop]: Abstraction has 11436 states and 15235 transitions. [2023-11-12 02:12:06,992 INFO L335 stractBuchiCegarLoop]: ======== Iteration 19 ============ [2023-11-12 02:12:06,992 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 11436 states and 15235 transitions. [2023-11-12 02:12:07,044 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 11300 [2023-11-12 02:12:07,044 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-12 02:12:07,045 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-12 02:12:07,046 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-12 02:12:07,046 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-12 02:12:07,046 INFO L748 eck$LassoCheckResult]: Stem: 103293#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2; 103294#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~6#1;havoc main_~__retres1~6#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 103386#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret16#1, start_simulation_#t~ret17#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 103387#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 103191#L341 assume 1 == ~m_i~0;~m_st~0 := 0; 103192#L341-2 assume !(1 == ~t1_i~0);~t1_st~0 := 2; 103427#L346-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 103291#L351-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 103126#L356-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 103127#L361-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 103146#L502 assume !(0 == ~M_E~0); 103147#L502-2 assume !(0 == ~T1_E~0); 103115#L507-1 assume !(0 == ~T2_E~0); 103116#L512-1 assume !(0 == ~T3_E~0); 103194#L517-1 assume !(0 == ~T4_E~0); 103100#L522-1 assume !(0 == ~E_1~0); 103101#L527-1 assume !(0 == ~E_2~0); 103297#L532-1 assume !(0 == ~E_3~0); 103298#L537-1 assume !(0 == ~E_4~0); 103322#L542-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 103289#L238 assume !(1 == ~m_pc~0); 103290#L238-2 is_master_triggered_~__retres1~0#1 := 0; 103354#L249 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 103271#is_master_triggered_returnLabel#1 activate_threads_#t~ret10#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 103269#L615 assume !(0 != activate_threads_~tmp~1#1); 103270#L615-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 103251#L257 assume !(1 == ~t1_pc~0); 103252#L257-2 is_transmit1_triggered_~__retres1~1#1 := 0; 103288#L268 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 103144#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret11#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 103145#L623 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 103398#L623-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 110132#L276 assume !(1 == ~t2_pc~0); 103502#L276-2 is_transmit2_triggered_~__retres1~2#1 := 0; 103503#L287 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 103394#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 103395#L631 assume !(0 != activate_threads_~tmp___1~0#1); 103561#L631-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 103268#L295 assume !(1 == ~t3_pc~0); 103132#L295-2 is_transmit3_triggered_~__retres1~3#1 := 0; 103133#L306 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 103095#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 103096#L639 assume !(0 != activate_threads_~tmp___2~0#1); 103544#L639-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 110100#L314 assume !(1 == ~t4_pc~0); 103152#L314-2 is_transmit4_triggered_~__retres1~4#1 := 0; 103151#L325 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 103184#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 103185#L647 assume !(0 != activate_threads_~tmp___3~0#1); 103250#L647-2 havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 103498#L555 assume !(1 == ~M_E~0); 103160#L555-2 assume !(1 == ~T1_E~0); 103161#L560-1 assume !(1 == ~T2_E~0); 103102#L565-1 assume !(1 == ~T3_E~0); 103103#L570-1 assume !(1 == ~T4_E~0); 103258#L575-1 assume !(1 == ~E_1~0); 103517#L580-1 assume !(1 == ~E_2~0); 103518#L585-1 assume !(1 == ~E_3~0); 103142#L590-1 assume !(1 == ~E_4~0); 103143#L595-1 assume { :end_inline_reset_delta_events } true; 110063#L776-2 assume !false; 108330#L777 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 108331#L477-1 [2023-11-12 02:12:07,047 INFO L750 eck$LassoCheckResult]: Loop: 108331#L477-1 assume !false; 108324#L412 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 108325#L374 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 108303#L401 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 108304#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 108292#L416 assume 0 != eval_~tmp~0#1; 108293#L416-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;havoc eval_#t~nondet5#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet5#1;havoc eval_#t~nondet5#1; 108207#L424 assume !(0 != eval_~tmp_ndt_1~0#1); 108208#L424-2 havoc eval_~tmp_ndt_1~0#1; 108350#L421-1 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0#1;havoc eval_#t~nondet6#1;eval_~tmp_ndt_2~0#1 := eval_#t~nondet6#1;havoc eval_#t~nondet6#1; 108351#L438 assume !(0 != eval_~tmp_ndt_2~0#1); 108346#L438-2 havoc eval_~tmp_ndt_2~0#1; 108347#L435-1 assume !(0 == ~t2_st~0); 108338#L449-1 assume !(0 == ~t3_st~0); 108333#L463-1 assume !(0 == ~t4_st~0); 108331#L477-1 [2023-11-12 02:12:07,047 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-12 02:12:07,048 INFO L85 PathProgramCache]: Analyzing trace with hash 995820945, now seen corresponding path program 1 times [2023-11-12 02:12:07,048 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-12 02:12:07,048 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [39873920] [2023-11-12 02:12:07,048 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-12 02:12:07,049 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-12 02:12:07,059 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-12 02:12:07,083 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-12 02:12:07,083 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-12 02:12:07,083 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [39873920] [2023-11-12 02:12:07,084 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [39873920] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-12 02:12:07,084 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-12 02:12:07,084 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-12 02:12:07,084 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [140506112] [2023-11-12 02:12:07,085 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-12 02:12:07,085 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-12 02:12:07,086 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-12 02:12:07,086 INFO L85 PathProgramCache]: Analyzing trace with hash 1964339025, now seen corresponding path program 1 times [2023-11-12 02:12:07,086 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-12 02:12:07,086 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [829777951] [2023-11-12 02:12:07,087 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-12 02:12:07,087 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-12 02:12:07,091 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-12 02:12:07,092 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-12 02:12:07,095 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-12 02:12:07,097 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-12 02:12:07,198 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-12 02:12:07,198 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-12 02:12:07,198 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-12 02:12:07,199 INFO L87 Difference]: Start difference. First operand 11436 states and 15235 transitions. cyclomatic complexity: 3803 Second operand has 3 states, 3 states have (on average 20.666666666666668) internal successors, (62), 3 states have internal predecessors, (62), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-12 02:12:07,265 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-12 02:12:07,265 INFO L93 Difference]: Finished difference Result 11375 states and 15154 transitions. [2023-11-12 02:12:07,265 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 11375 states and 15154 transitions. [2023-11-12 02:12:07,336 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 11300 [2023-11-12 02:12:07,386 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 11375 states to 11375 states and 15154 transitions. [2023-11-12 02:12:07,386 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 11375 [2023-11-12 02:12:07,398 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 11375 [2023-11-12 02:12:07,398 INFO L73 IsDeterministic]: Start isDeterministic. Operand 11375 states and 15154 transitions. [2023-11-12 02:12:07,410 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-12 02:12:07,410 INFO L218 hiAutomatonCegarLoop]: Abstraction has 11375 states and 15154 transitions. [2023-11-12 02:12:07,422 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 11375 states and 15154 transitions. [2023-11-12 02:12:07,655 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 11375 to 11375. [2023-11-12 02:12:07,674 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 11375 states, 11375 states have (on average 1.3322197802197802) internal successors, (15154), 11374 states have internal predecessors, (15154), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-12 02:12:07,708 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 11375 states to 11375 states and 15154 transitions. [2023-11-12 02:12:07,709 INFO L240 hiAutomatonCegarLoop]: Abstraction has 11375 states and 15154 transitions. [2023-11-12 02:12:07,709 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-12 02:12:07,710 INFO L428 stractBuchiCegarLoop]: Abstraction has 11375 states and 15154 transitions. [2023-11-12 02:12:07,710 INFO L335 stractBuchiCegarLoop]: ======== Iteration 20 ============ [2023-11-12 02:12:07,710 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 11375 states and 15154 transitions. [2023-11-12 02:12:07,839 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 11300 [2023-11-12 02:12:07,839 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-12 02:12:07,839 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-12 02:12:07,840 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-12 02:12:07,840 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-12 02:12:07,840 INFO L748 eck$LassoCheckResult]: Stem: 126106#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2; 126107#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~6#1;havoc main_~__retres1~6#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 126199#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret16#1, start_simulation_#t~ret17#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 126200#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 126007#L341 assume 1 == ~m_i~0;~m_st~0 := 0; 126008#L341-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 126241#L346-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 126104#L351-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 125943#L356-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 125944#L361-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 125962#L502 assume !(0 == ~M_E~0); 125963#L502-2 assume !(0 == ~T1_E~0); 125932#L507-1 assume !(0 == ~T2_E~0); 125933#L512-1 assume !(0 == ~T3_E~0); 126010#L517-1 assume !(0 == ~T4_E~0); 125919#L522-1 assume !(0 == ~E_1~0); 125920#L527-1 assume !(0 == ~E_2~0); 126109#L532-1 assume !(0 == ~E_3~0); 126110#L537-1 assume !(0 == ~E_4~0); 126131#L542-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 126102#L238 assume !(1 == ~m_pc~0); 126103#L238-2 is_master_triggered_~__retres1~0#1 := 0; 126163#L249 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 126086#is_master_triggered_returnLabel#1 activate_threads_#t~ret10#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 126084#L615 assume !(0 != activate_threads_~tmp~1#1); 126085#L615-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 126066#L257 assume !(1 == ~t1_pc~0); 126067#L257-2 is_transmit1_triggered_~__retres1~1#1 := 0; 126101#L268 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 125960#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret11#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 125961#L623 assume !(0 != activate_threads_~tmp___0~0#1); 125945#L623-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 125946#L276 assume !(1 == ~t2_pc~0); 126210#L276-2 is_transmit2_triggered_~__retres1~2#1 := 0; 126316#L287 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 126208#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 126209#L631 assume !(0 != activate_threads_~tmp___1~0#1); 126359#L631-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 126083#L295 assume !(1 == ~t3_pc~0); 125949#L295-2 is_transmit3_triggered_~__retres1~3#1 := 0; 125950#L306 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 125912#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 125913#L639 assume !(0 != activate_threads_~tmp___2~0#1); 126346#L639-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 126347#L314 assume !(1 == ~t4_pc~0); 125968#L314-2 is_transmit4_triggered_~__retres1~4#1 := 0; 125967#L325 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 126000#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 126001#L647 assume !(0 != activate_threads_~tmp___3~0#1); 126065#L647-2 havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 126311#L555 assume !(1 == ~M_E~0); 125976#L555-2 assume !(1 == ~T1_E~0); 125977#L560-1 assume !(1 == ~T2_E~0); 125921#L565-1 assume !(1 == ~T3_E~0); 125922#L570-1 assume !(1 == ~T4_E~0); 126072#L575-1 assume !(1 == ~E_1~0); 126247#L580-1 assume !(1 == ~E_2~0); 126124#L585-1 assume !(1 == ~E_3~0); 125959#L590-1 assume !(1 == ~E_4~0); 125951#L595-1 assume { :end_inline_reset_delta_events } true; 125952#L776-2 assume !false; 132351#L777 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 132352#L477-1 [2023-11-12 02:12:07,840 INFO L750 eck$LassoCheckResult]: Loop: 132352#L477-1 assume !false; 134075#L412 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 134073#L374 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 134072#L401 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 134071#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 134070#L416 assume 0 != eval_~tmp~0#1; 134068#L416-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;havoc eval_#t~nondet5#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet5#1;havoc eval_#t~nondet5#1; 134067#L424 assume !(0 != eval_~tmp_ndt_1~0#1); 132371#L424-2 havoc eval_~tmp_ndt_1~0#1; 132369#L421-1 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0#1;havoc eval_#t~nondet6#1;eval_~tmp_ndt_2~0#1 := eval_#t~nondet6#1;havoc eval_#t~nondet6#1; 131961#L438 assume !(0 != eval_~tmp_ndt_2~0#1); 134062#L438-2 havoc eval_~tmp_ndt_2~0#1; 134083#L435-1 assume !(0 == ~t2_st~0); 134080#L449-1 assume !(0 == ~t3_st~0); 134077#L463-1 assume !(0 == ~t4_st~0); 132352#L477-1 [2023-11-12 02:12:07,841 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-12 02:12:07,841 INFO L85 PathProgramCache]: Analyzing trace with hash 9663309, now seen corresponding path program 2 times [2023-11-12 02:12:07,841 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-12 02:12:07,841 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [647226433] [2023-11-12 02:12:07,842 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-12 02:12:07,842 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-12 02:12:07,852 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-12 02:12:07,852 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-12 02:12:07,864 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-12 02:12:07,878 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-12 02:12:07,878 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-12 02:12:07,879 INFO L85 PathProgramCache]: Analyzing trace with hash 1964339025, now seen corresponding path program 2 times [2023-11-12 02:12:07,879 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-12 02:12:07,879 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [227563249] [2023-11-12 02:12:07,879 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-12 02:12:07,880 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-12 02:12:07,884 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-12 02:12:07,885 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-12 02:12:07,887 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-12 02:12:07,888 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-12 02:12:07,889 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-12 02:12:07,889 INFO L85 PathProgramCache]: Analyzing trace with hash 1511750277, now seen corresponding path program 1 times [2023-11-12 02:12:07,889 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-12 02:12:07,890 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [796506745] [2023-11-12 02:12:07,890 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-12 02:12:07,890 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-12 02:12:07,905 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-12 02:12:07,936 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-12 02:12:07,936 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-12 02:12:07,936 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [796506745] [2023-11-12 02:12:07,937 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [796506745] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-12 02:12:07,937 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-12 02:12:07,937 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-12 02:12:07,937 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [284132677] [2023-11-12 02:12:07,937 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-12 02:12:08,021 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-12 02:12:08,021 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-12 02:12:08,021 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-12 02:12:08,022 INFO L87 Difference]: Start difference. First operand 11375 states and 15154 transitions. cyclomatic complexity: 3783 Second operand has 3 states, 3 states have (on average 25.666666666666668) internal successors, (77), 3 states have internal predecessors, (77), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-12 02:12:08,125 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-12 02:12:08,125 INFO L93 Difference]: Finished difference Result 19829 states and 26310 transitions. [2023-11-12 02:12:08,125 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 19829 states and 26310 transitions. [2023-11-12 02:12:08,345 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 19746 [2023-11-12 02:12:08,414 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 19829 states to 19829 states and 26310 transitions. [2023-11-12 02:12:08,414 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 19829 [2023-11-12 02:12:08,432 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 19829 [2023-11-12 02:12:08,432 INFO L73 IsDeterministic]: Start isDeterministic. Operand 19829 states and 26310 transitions. [2023-11-12 02:12:08,447 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-12 02:12:08,448 INFO L218 hiAutomatonCegarLoop]: Abstraction has 19829 states and 26310 transitions. [2023-11-12 02:12:08,467 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 19829 states and 26310 transitions. [2023-11-12 02:12:08,731 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 19829 to 18709. [2023-11-12 02:12:08,758 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 18709 states, 18709 states have (on average 1.3293067507616656) internal successors, (24870), 18708 states have internal predecessors, (24870), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-12 02:12:08,815 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 18709 states to 18709 states and 24870 transitions. [2023-11-12 02:12:08,815 INFO L240 hiAutomatonCegarLoop]: Abstraction has 18709 states and 24870 transitions. [2023-11-12 02:12:08,816 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-12 02:12:08,816 INFO L428 stractBuchiCegarLoop]: Abstraction has 18709 states and 24870 transitions. [2023-11-12 02:12:08,816 INFO L335 stractBuchiCegarLoop]: ======== Iteration 21 ============ [2023-11-12 02:12:08,817 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 18709 states and 24870 transitions. [2023-11-12 02:12:08,892 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 18626 [2023-11-12 02:12:08,892 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-12 02:12:08,893 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-12 02:12:08,894 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-12 02:12:08,894 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-12 02:12:08,894 INFO L748 eck$LassoCheckResult]: Stem: 157320#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2; 157321#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~6#1;havoc main_~__retres1~6#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 157423#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret16#1, start_simulation_#t~ret17#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 157424#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 157218#L341 assume 1 == ~m_i~0;~m_st~0 := 0; 157219#L341-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 157467#L346-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 157318#L351-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 157154#L356-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 157155#L361-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 157173#L502 assume !(0 == ~M_E~0); 157174#L502-2 assume !(0 == ~T1_E~0); 157141#L507-1 assume !(0 == ~T2_E~0); 157142#L512-1 assume !(0 == ~T3_E~0); 157220#L517-1 assume !(0 == ~T4_E~0); 157129#L522-1 assume !(0 == ~E_1~0); 157130#L527-1 assume !(0 == ~E_2~0); 157324#L532-1 assume !(0 == ~E_3~0); 157325#L537-1 assume !(0 == ~E_4~0); 157348#L542-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 157316#L238 assume !(1 == ~m_pc~0); 157317#L238-2 is_master_triggered_~__retres1~0#1 := 0; 157384#L249 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 157298#is_master_triggered_returnLabel#1 activate_threads_#t~ret10#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 157296#L615 assume !(0 != activate_threads_~tmp~1#1); 157297#L615-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 157278#L257 assume !(1 == ~t1_pc~0); 157279#L257-2 is_transmit1_triggered_~__retres1~1#1 := 0; 157312#L268 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 157171#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret11#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 157172#L623 assume !(0 != activate_threads_~tmp___0~0#1); 157156#L623-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 157157#L276 assume !(1 == ~t2_pc~0); 157431#L276-2 is_transmit2_triggered_~__retres1~2#1 := 0; 157544#L287 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 157429#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 157430#L631 assume !(0 != activate_threads_~tmp___1~0#1); 157604#L631-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 157295#L295 assume !(1 == ~t3_pc~0); 157160#L295-2 is_transmit3_triggered_~__retres1~3#1 := 0; 157161#L306 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 157124#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 157125#L639 assume !(0 != activate_threads_~tmp___2~0#1); 157579#L639-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 157580#L314 assume !(1 == ~t4_pc~0); 157179#L314-2 is_transmit4_triggered_~__retres1~4#1 := 0; 157178#L325 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 157210#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 157211#L647 assume !(0 != activate_threads_~tmp___3~0#1); 157277#L647-2 havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 157537#L555 assume !(1 == ~M_E~0); 157187#L555-2 assume !(1 == ~T1_E~0); 157188#L560-1 assume !(1 == ~T2_E~0); 157131#L565-1 assume !(1 == ~T3_E~0); 157132#L570-1 assume !(1 == ~T4_E~0); 157284#L575-1 assume !(1 == ~E_1~0); 157474#L580-1 assume !(1 == ~E_2~0); 157340#L585-1 assume !(1 == ~E_3~0); 157168#L590-1 assume !(1 == ~E_4~0); 157162#L595-1 assume { :end_inline_reset_delta_events } true; 157163#L776-2 assume !false; 167997#L777 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 167996#L477-1 [2023-11-12 02:12:08,895 INFO L750 eck$LassoCheckResult]: Loop: 167996#L477-1 assume !false; 167995#L412 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 167993#L374 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 167989#L401 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 167987#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 167985#L416 assume 0 != eval_~tmp~0#1; 167983#L416-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;havoc eval_#t~nondet5#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet5#1;havoc eval_#t~nondet5#1; 167980#L424 assume !(0 != eval_~tmp_ndt_1~0#1); 167978#L424-2 havoc eval_~tmp_ndt_1~0#1; 167976#L421-1 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0#1;havoc eval_#t~nondet6#1;eval_~tmp_ndt_2~0#1 := eval_#t~nondet6#1;havoc eval_#t~nondet6#1; 167971#L438 assume !(0 != eval_~tmp_ndt_2~0#1); 167969#L438-2 havoc eval_~tmp_ndt_2~0#1; 167966#L435-1 assume 0 == ~t2_st~0;havoc eval_~tmp_ndt_3~0#1;havoc eval_#t~nondet7#1;eval_~tmp_ndt_3~0#1 := eval_#t~nondet7#1;havoc eval_#t~nondet7#1; 167961#L452 assume !(0 != eval_~tmp_ndt_3~0#1); 167960#L452-2 havoc eval_~tmp_ndt_3~0#1; 167955#L449-1 assume !(0 == ~t3_st~0); 167956#L463-1 assume !(0 == ~t4_st~0); 167996#L477-1 [2023-11-12 02:12:08,895 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-12 02:12:08,895 INFO L85 PathProgramCache]: Analyzing trace with hash 9663309, now seen corresponding path program 3 times [2023-11-12 02:12:08,895 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-12 02:12:08,896 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1912272192] [2023-11-12 02:12:08,896 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-12 02:12:08,897 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-12 02:12:08,910 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-12 02:12:08,911 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-12 02:12:08,918 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-12 02:12:08,930 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-12 02:12:08,931 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-12 02:12:08,931 INFO L85 PathProgramCache]: Analyzing trace with hash 2090989624, now seen corresponding path program 1 times [2023-11-12 02:12:08,931 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-12 02:12:08,931 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1960427354] [2023-11-12 02:12:08,931 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-12 02:12:08,932 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-12 02:12:08,936 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-12 02:12:08,937 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-12 02:12:08,939 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-12 02:12:08,941 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-12 02:12:08,942 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-12 02:12:08,942 INFO L85 PathProgramCache]: Analyzing trace with hash 944899692, now seen corresponding path program 1 times [2023-11-12 02:12:08,942 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-12 02:12:08,943 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1003084236] [2023-11-12 02:12:08,943 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-12 02:12:08,943 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-12 02:12:08,958 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-12 02:12:08,999 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-12 02:12:08,999 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-12 02:12:09,000 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1003084236] [2023-11-12 02:12:09,000 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1003084236] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-12 02:12:09,000 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-12 02:12:09,000 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-12 02:12:09,001 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1003297076] [2023-11-12 02:12:09,001 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-12 02:12:09,098 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-12 02:12:09,099 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-12 02:12:09,099 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-12 02:12:09,099 INFO L87 Difference]: Start difference. First operand 18709 states and 24870 transitions. cyclomatic complexity: 6165 Second operand has 3 states, 3 states have (on average 26.333333333333332) internal successors, (79), 3 states have internal predecessors, (79), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-12 02:12:09,342 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-12 02:12:09,342 INFO L93 Difference]: Finished difference Result 33201 states and 44014 transitions. [2023-11-12 02:12:09,343 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 33201 states and 44014 transitions. [2023-11-12 02:12:09,490 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 33102 [2023-11-12 02:12:09,716 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 33201 states to 33201 states and 44014 transitions. [2023-11-12 02:12:09,716 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 33201 [2023-11-12 02:12:09,735 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 33201 [2023-11-12 02:12:09,735 INFO L73 IsDeterministic]: Start isDeterministic. Operand 33201 states and 44014 transitions. [2023-11-12 02:12:09,759 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-12 02:12:09,759 INFO L218 hiAutomatonCegarLoop]: Abstraction has 33201 states and 44014 transitions. [2023-11-12 02:12:09,779 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 33201 states and 44014 transitions. [2023-11-12 02:12:10,184 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 33201 to 32497. [2023-11-12 02:12:10,259 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 32497 states, 32497 states have (on average 1.3268301689386712) internal successors, (43118), 32496 states have internal predecessors, (43118), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-12 02:12:10,347 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 32497 states to 32497 states and 43118 transitions. [2023-11-12 02:12:10,347 INFO L240 hiAutomatonCegarLoop]: Abstraction has 32497 states and 43118 transitions. [2023-11-12 02:12:10,348 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-12 02:12:10,349 INFO L428 stractBuchiCegarLoop]: Abstraction has 32497 states and 43118 transitions. [2023-11-12 02:12:10,349 INFO L335 stractBuchiCegarLoop]: ======== Iteration 22 ============ [2023-11-12 02:12:10,349 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 32497 states and 43118 transitions. [2023-11-12 02:12:10,611 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 32398 [2023-11-12 02:12:10,612 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-12 02:12:10,612 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-12 02:12:10,614 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-12 02:12:10,614 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-12 02:12:10,614 INFO L748 eck$LassoCheckResult]: Stem: 209236#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2; 209237#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~6#1;havoc main_~__retres1~6#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 209336#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret16#1, start_simulation_#t~ret17#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 209337#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 209137#L341 assume 1 == ~m_i~0;~m_st~0 := 0; 209138#L341-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 209377#L346-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 209234#L351-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 209072#L356-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 209073#L361-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 209091#L502 assume !(0 == ~M_E~0); 209092#L502-2 assume !(0 == ~T1_E~0); 209062#L507-1 assume !(0 == ~T2_E~0); 209063#L512-1 assume !(0 == ~T3_E~0); 209140#L517-1 assume !(0 == ~T4_E~0); 209047#L522-1 assume !(0 == ~E_1~0); 209048#L527-1 assume !(0 == ~E_2~0); 209240#L532-1 assume !(0 == ~E_3~0); 209241#L537-1 assume !(0 == ~E_4~0); 209264#L542-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 209232#L238 assume !(1 == ~m_pc~0); 209233#L238-2 is_master_triggered_~__retres1~0#1 := 0; 209297#L249 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 209216#is_master_triggered_returnLabel#1 activate_threads_#t~ret10#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 209214#L615 assume !(0 != activate_threads_~tmp~1#1); 209215#L615-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 209196#L257 assume !(1 == ~t1_pc~0); 209197#L257-2 is_transmit1_triggered_~__retres1~1#1 := 0; 209231#L268 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 209089#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret11#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 209090#L623 assume !(0 != activate_threads_~tmp___0~0#1); 209074#L623-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 209075#L276 assume !(1 == ~t2_pc~0); 209346#L276-2 is_transmit2_triggered_~__retres1~2#1 := 0; 209452#L287 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 209344#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 209345#L631 assume !(0 != activate_threads_~tmp___1~0#1); 209504#L631-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 209213#L295 assume !(1 == ~t3_pc~0); 209078#L295-2 is_transmit3_triggered_~__retres1~3#1 := 0; 209079#L306 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 209042#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 209043#L639 assume !(0 != activate_threads_~tmp___2~0#1); 209490#L639-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 209491#L314 assume !(1 == ~t4_pc~0); 209097#L314-2 is_transmit4_triggered_~__retres1~4#1 := 0; 209096#L325 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 209129#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 209130#L647 assume !(0 != activate_threads_~tmp___3~0#1); 209195#L647-2 havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 209448#L555 assume !(1 == ~M_E~0); 209105#L555-2 assume !(1 == ~T1_E~0); 209106#L560-1 assume !(1 == ~T2_E~0); 209049#L565-1 assume !(1 == ~T3_E~0); 209050#L570-1 assume !(1 == ~T4_E~0); 209203#L575-1 assume !(1 == ~E_1~0); 209384#L580-1 assume !(1 == ~E_2~0); 209256#L585-1 assume !(1 == ~E_3~0); 209088#L590-1 assume !(1 == ~E_4~0); 209080#L595-1 assume { :end_inline_reset_delta_events } true; 209081#L776-2 assume !false; 231561#L777 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 231558#L477-1 [2023-11-12 02:12:10,615 INFO L750 eck$LassoCheckResult]: Loop: 231558#L477-1 assume !false; 231556#L412 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 231554#L374 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 231550#L401 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 231548#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 231546#L416 assume 0 != eval_~tmp~0#1; 231543#L416-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;havoc eval_#t~nondet5#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet5#1;havoc eval_#t~nondet5#1; 231539#L424 assume !(0 != eval_~tmp_ndt_1~0#1); 231537#L424-2 havoc eval_~tmp_ndt_1~0#1; 228824#L421-1 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0#1;havoc eval_#t~nondet6#1;eval_~tmp_ndt_2~0#1 := eval_#t~nondet6#1;havoc eval_#t~nondet6#1; 228821#L438 assume !(0 != eval_~tmp_ndt_2~0#1); 228817#L438-2 havoc eval_~tmp_ndt_2~0#1; 228815#L435-1 assume 0 == ~t2_st~0;havoc eval_~tmp_ndt_3~0#1;havoc eval_#t~nondet7#1;eval_~tmp_ndt_3~0#1 := eval_#t~nondet7#1;havoc eval_#t~nondet7#1; 228607#L452 assume !(0 != eval_~tmp_ndt_3~0#1); 228786#L452-2 havoc eval_~tmp_ndt_3~0#1; 231567#L449-1 assume 0 == ~t3_st~0;havoc eval_~tmp_ndt_4~0#1;havoc eval_#t~nondet8#1;eval_~tmp_ndt_4~0#1 := eval_#t~nondet8#1;havoc eval_#t~nondet8#1; 231016#L466 assume !(0 != eval_~tmp_ndt_4~0#1); 231566#L466-2 havoc eval_~tmp_ndt_4~0#1; 231563#L463-1 assume !(0 == ~t4_st~0); 231558#L477-1 [2023-11-12 02:12:10,615 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-12 02:12:10,616 INFO L85 PathProgramCache]: Analyzing trace with hash 9663309, now seen corresponding path program 4 times [2023-11-12 02:12:10,616 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-12 02:12:10,616 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [933410708] [2023-11-12 02:12:10,616 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-12 02:12:10,617 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-12 02:12:10,629 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-12 02:12:10,629 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-12 02:12:10,637 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-12 02:12:10,655 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-12 02:12:10,655 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-12 02:12:10,656 INFO L85 PathProgramCache]: Analyzing trace with hash -608301423, now seen corresponding path program 1 times [2023-11-12 02:12:10,656 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-12 02:12:10,656 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1403446781] [2023-11-12 02:12:10,656 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-12 02:12:10,656 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-12 02:12:10,662 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-12 02:12:10,663 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-12 02:12:10,667 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-12 02:12:10,669 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-12 02:12:10,670 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-12 02:12:10,670 INFO L85 PathProgramCache]: Analyzing trace with hash 1805868997, now seen corresponding path program 1 times [2023-11-12 02:12:10,671 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-12 02:12:10,671 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [403453581] [2023-11-12 02:12:10,671 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-12 02:12:10,671 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-12 02:12:10,686 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-12 02:12:10,727 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-12 02:12:10,728 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-12 02:12:10,728 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [403453581] [2023-11-12 02:12:10,728 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [403453581] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-12 02:12:10,728 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-12 02:12:10,729 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2023-11-12 02:12:10,729 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2005301465] [2023-11-12 02:12:10,729 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-12 02:12:10,831 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-12 02:12:10,832 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-12 02:12:10,832 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-12 02:12:10,832 INFO L87 Difference]: Start difference. First operand 32497 states and 43118 transitions. cyclomatic complexity: 10625 Second operand has 3 states, 2 states have (on average 40.5) internal successors, (81), 3 states have internal predecessors, (81), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-12 02:12:11,229 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-12 02:12:11,229 INFO L93 Difference]: Finished difference Result 60393 states and 79790 transitions. [2023-11-12 02:12:11,230 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 60393 states and 79790 transitions. [2023-11-12 02:12:11,754 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 60262 [2023-11-12 02:12:12,000 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 60393 states to 60393 states and 79790 transitions. [2023-11-12 02:12:12,001 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 60393 [2023-11-12 02:12:12,035 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 60393 [2023-11-12 02:12:12,035 INFO L73 IsDeterministic]: Start isDeterministic. Operand 60393 states and 79790 transitions. [2023-11-12 02:12:12,210 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-12 02:12:12,211 INFO L218 hiAutomatonCegarLoop]: Abstraction has 60393 states and 79790 transitions. [2023-11-12 02:12:12,283 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 60393 states and 79790 transitions. [2023-11-12 02:12:13,020 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 60393 to 60393. [2023-11-12 02:12:13,083 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 60393 states, 60393 states have (on average 1.3211796069080854) internal successors, (79790), 60392 states have internal predecessors, (79790), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-12 02:12:13,310 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 60393 states to 60393 states and 79790 transitions. [2023-11-12 02:12:13,310 INFO L240 hiAutomatonCegarLoop]: Abstraction has 60393 states and 79790 transitions. [2023-11-12 02:12:13,311 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-12 02:12:13,312 INFO L428 stractBuchiCegarLoop]: Abstraction has 60393 states and 79790 transitions. [2023-11-12 02:12:13,312 INFO L335 stractBuchiCegarLoop]: ======== Iteration 23 ============ [2023-11-12 02:12:13,312 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 60393 states and 79790 transitions. [2023-11-12 02:12:13,776 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 60262 [2023-11-12 02:12:13,776 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-12 02:12:13,776 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-12 02:12:13,777 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-12 02:12:13,777 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-12 02:12:13,778 INFO L748 eck$LassoCheckResult]: Stem: 302133#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2; 302134#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~6#1;havoc main_~__retres1~6#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 302231#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret16#1, start_simulation_#t~ret17#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 302232#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 302035#L341 assume 1 == ~m_i~0;~m_st~0 := 0; 302036#L341-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 302273#L346-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 302131#L351-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 301971#L356-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 301972#L361-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 301990#L502 assume !(0 == ~M_E~0); 301991#L502-2 assume !(0 == ~T1_E~0); 301961#L507-1 assume !(0 == ~T2_E~0); 301962#L512-1 assume !(0 == ~T3_E~0); 302038#L517-1 assume !(0 == ~T4_E~0); 301948#L522-1 assume !(0 == ~E_1~0); 301949#L527-1 assume !(0 == ~E_2~0); 302136#L532-1 assume !(0 == ~E_3~0); 302137#L537-1 assume !(0 == ~E_4~0); 302159#L542-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 302129#L238 assume !(1 == ~m_pc~0); 302130#L238-2 is_master_triggered_~__retres1~0#1 := 0; 302194#L249 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 302112#is_master_triggered_returnLabel#1 activate_threads_#t~ret10#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 302110#L615 assume !(0 != activate_threads_~tmp~1#1); 302111#L615-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 302092#L257 assume !(1 == ~t1_pc~0); 302093#L257-2 is_transmit1_triggered_~__retres1~1#1 := 0; 302128#L268 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 301988#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret11#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 301989#L623 assume !(0 != activate_threads_~tmp___0~0#1); 301973#L623-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 301974#L276 assume !(1 == ~t2_pc~0); 302241#L276-2 is_transmit2_triggered_~__retres1~2#1 := 0; 302351#L287 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 302239#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 302240#L631 assume !(0 != activate_threads_~tmp___1~0#1); 302400#L631-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 302109#L295 assume !(1 == ~t3_pc~0); 301977#L295-2 is_transmit3_triggered_~__retres1~3#1 := 0; 301978#L306 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 301941#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 301942#L639 assume !(0 != activate_threads_~tmp___2~0#1); 302387#L639-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 302388#L314 assume !(1 == ~t4_pc~0); 301996#L314-2 is_transmit4_triggered_~__retres1~4#1 := 0; 301995#L325 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 302028#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 302029#L647 assume !(0 != activate_threads_~tmp___3~0#1); 302091#L647-2 havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 302346#L555 assume !(1 == ~M_E~0); 302004#L555-2 assume !(1 == ~T1_E~0); 302005#L560-1 assume !(1 == ~T2_E~0); 301950#L565-1 assume !(1 == ~T3_E~0); 301951#L570-1 assume !(1 == ~T4_E~0); 302099#L575-1 assume !(1 == ~E_1~0); 302281#L580-1 assume !(1 == ~E_2~0); 302151#L585-1 assume !(1 == ~E_3~0); 301987#L590-1 assume !(1 == ~E_4~0); 301979#L595-1 assume { :end_inline_reset_delta_events } true; 301980#L776-2 assume !false; 338824#L777 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 338825#L477-1 [2023-11-12 02:12:13,778 INFO L750 eck$LassoCheckResult]: Loop: 338825#L477-1 assume !false; 345917#L412 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 338800#L374 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 338795#L401 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 338787#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 338780#L416 assume 0 != eval_~tmp~0#1; 338772#L416-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;havoc eval_#t~nondet5#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet5#1;havoc eval_#t~nondet5#1; 338764#L424 assume !(0 != eval_~tmp_ndt_1~0#1); 338765#L424-2 havoc eval_~tmp_ndt_1~0#1; 337751#L421-1 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0#1;havoc eval_#t~nondet6#1;eval_~tmp_ndt_2~0#1 := eval_#t~nondet6#1;havoc eval_#t~nondet6#1; 337748#L438 assume !(0 != eval_~tmp_ndt_2~0#1); 337745#L438-2 havoc eval_~tmp_ndt_2~0#1; 337743#L435-1 assume 0 == ~t2_st~0;havoc eval_~tmp_ndt_3~0#1;havoc eval_#t~nondet7#1;eval_~tmp_ndt_3~0#1 := eval_#t~nondet7#1;havoc eval_#t~nondet7#1; 337733#L452 assume !(0 != eval_~tmp_ndt_3~0#1); 337741#L452-2 havoc eval_~tmp_ndt_3~0#1; 344533#L449-1 assume 0 == ~t3_st~0;havoc eval_~tmp_ndt_4~0#1;havoc eval_#t~nondet8#1;eval_~tmp_ndt_4~0#1 := eval_#t~nondet8#1;havoc eval_#t~nondet8#1; 333552#L466 assume !(0 != eval_~tmp_ndt_4~0#1); 337726#L466-2 havoc eval_~tmp_ndt_4~0#1; 337725#L463-1 assume 0 == ~t4_st~0;havoc eval_~tmp_ndt_5~0#1;havoc eval_#t~nondet9#1;eval_~tmp_ndt_5~0#1 := eval_#t~nondet9#1;havoc eval_#t~nondet9#1; 337634#L480 assume !(0 != eval_~tmp_ndt_5~0#1); 337723#L480-2 havoc eval_~tmp_ndt_5~0#1; 338825#L477-1 [2023-11-12 02:12:13,779 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-12 02:12:13,779 INFO L85 PathProgramCache]: Analyzing trace with hash 9663309, now seen corresponding path program 5 times [2023-11-12 02:12:13,779 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-12 02:12:13,780 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [547589380] [2023-11-12 02:12:13,780 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-12 02:12:13,780 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-12 02:12:13,791 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-12 02:12:13,792 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-12 02:12:13,799 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-12 02:12:13,809 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-12 02:12:13,810 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-12 02:12:13,810 INFO L85 PathProgramCache]: Analyzing trace with hash -462124120, now seen corresponding path program 1 times [2023-11-12 02:12:13,810 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-12 02:12:13,811 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [558569240] [2023-11-12 02:12:13,811 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-12 02:12:13,811 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-12 02:12:13,815 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-12 02:12:13,815 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-12 02:12:13,818 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-12 02:12:13,820 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-12 02:12:13,821 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-12 02:12:13,821 INFO L85 PathProgramCache]: Analyzing trace with hash 273309660, now seen corresponding path program 1 times [2023-11-12 02:12:13,821 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-12 02:12:13,821 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [964794467] [2023-11-12 02:12:13,821 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-12 02:12:13,822 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-12 02:12:13,833 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-12 02:12:13,833 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-12 02:12:13,840 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-12 02:12:13,853 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-12 02:12:15,557 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-12 02:12:15,558 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-12 02:12:15,581 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-12 02:12:15,758 INFO L201 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer CFG 12.11 02:12:15 BoogieIcfgContainer [2023-11-12 02:12:15,758 INFO L131 PluginConnector]: ------------------------ END BuchiAutomizer---------------------------- [2023-11-12 02:12:15,759 INFO L112 PluginConnector]: ------------------------Witness Printer---------------------------- [2023-11-12 02:12:15,759 INFO L270 PluginConnector]: Initializing Witness Printer... [2023-11-12 02:12:15,759 INFO L274 PluginConnector]: Witness Printer initialized [2023-11-12 02:12:15,760 INFO L184 PluginConnector]: Executing the observer RCFGCatcher from plugin Witness Printer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 12.11 02:11:59" (3/4) ... [2023-11-12 02:12:15,762 INFO L134 WitnessPrinter]: Generating witness for non-termination counterexample [2023-11-12 02:12:15,842 INFO L149 WitnessManager]: Wrote witness to /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_b9c4b66b-8a73-49ee-9f7b-92ffbd0a3c3e/bin/uautomizer-verify-uTZkv6EMXl/witness.graphml [2023-11-12 02:12:15,843 INFO L131 PluginConnector]: ------------------------ END Witness Printer---------------------------- [2023-11-12 02:12:15,843 INFO L158 Benchmark]: Toolchain (without parser) took 18555.12ms. Allocated memory was 165.7MB in the beginning and 4.8GB in the end (delta: 4.6GB). Free memory was 118.7MB in the beginning and 4.2GB in the end (delta: -4.1GB). Peak memory consumption was 544.2MB. Max. memory is 16.1GB. [2023-11-12 02:12:15,844 INFO L158 Benchmark]: CDTParser took 0.78ms. Allocated memory is still 165.7MB. Free memory is still 140.4MB. There was no memory consumed. Max. memory is 16.1GB. [2023-11-12 02:12:15,844 INFO L158 Benchmark]: CACSL2BoogieTranslator took 393.36ms. Allocated memory is still 165.7MB. Free memory was 118.4MB in the beginning and 103.4MB in the end (delta: 15.0MB). Peak memory consumption was 14.7MB. Max. memory is 16.1GB. [2023-11-12 02:12:15,845 INFO L158 Benchmark]: Boogie Procedure Inliner took 90.49ms. Allocated memory is still 165.7MB. Free memory was 103.4MB in the beginning and 99.3MB in the end (delta: 4.1MB). Peak memory consumption was 4.2MB. Max. memory is 16.1GB. [2023-11-12 02:12:15,845 INFO L158 Benchmark]: Boogie Preprocessor took 69.74ms. Allocated memory is still 165.7MB. Free memory was 99.3MB in the beginning and 95.7MB in the end (delta: 3.7MB). Peak memory consumption was 4.2MB. Max. memory is 16.1GB. [2023-11-12 02:12:15,845 INFO L158 Benchmark]: RCFGBuilder took 1356.35ms. Allocated memory is still 165.7MB. Free memory was 95.7MB in the beginning and 106.1MB in the end (delta: -10.4MB). Peak memory consumption was 27.4MB. Max. memory is 16.1GB. [2023-11-12 02:12:15,846 INFO L158 Benchmark]: BuchiAutomizer took 16555.25ms. Allocated memory was 165.7MB in the beginning and 4.8GB in the end (delta: 4.6GB). Free memory was 106.1MB in the beginning and 4.2GB in the end (delta: -4.1GB). Peak memory consumption was 523.1MB. Max. memory is 16.1GB. [2023-11-12 02:12:15,846 INFO L158 Benchmark]: Witness Printer took 83.92ms. Allocated memory is still 4.8GB. Free memory was 4.2GB in the beginning and 4.2GB in the end (delta: 7.3MB). Peak memory consumption was 6.3MB. Max. memory is 16.1GB. [2023-11-12 02:12:15,848 INFO L338 ainManager$Toolchain]: ####################### End [Toolchain 1] ####################### --- Results --- * Results from de.uni_freiburg.informatik.ultimate.core: - StatisticsResult: Toolchain Benchmarks Benchmark results are: * CDTParser took 0.78ms. Allocated memory is still 165.7MB. Free memory is still 140.4MB. There was no memory consumed. Max. memory is 16.1GB. * CACSL2BoogieTranslator took 393.36ms. Allocated memory is still 165.7MB. Free memory was 118.4MB in the beginning and 103.4MB in the end (delta: 15.0MB). Peak memory consumption was 14.7MB. Max. memory is 16.1GB. * Boogie Procedure Inliner took 90.49ms. Allocated memory is still 165.7MB. Free memory was 103.4MB in the beginning and 99.3MB in the end (delta: 4.1MB). Peak memory consumption was 4.2MB. Max. memory is 16.1GB. * Boogie Preprocessor took 69.74ms. Allocated memory is still 165.7MB. Free memory was 99.3MB in the beginning and 95.7MB in the end (delta: 3.7MB). Peak memory consumption was 4.2MB. Max. memory is 16.1GB. * RCFGBuilder took 1356.35ms. Allocated memory is still 165.7MB. Free memory was 95.7MB in the beginning and 106.1MB in the end (delta: -10.4MB). Peak memory consumption was 27.4MB. Max. memory is 16.1GB. * BuchiAutomizer took 16555.25ms. Allocated memory was 165.7MB in the beginning and 4.8GB in the end (delta: 4.6GB). Free memory was 106.1MB in the beginning and 4.2GB in the end (delta: -4.1GB). Peak memory consumption was 523.1MB. Max. memory is 16.1GB. * Witness Printer took 83.92ms. Allocated memory is still 4.8GB. Free memory was 4.2GB in the beginning and 4.2GB in the end (delta: 7.3MB). Peak memory consumption was 6.3MB. Max. memory is 16.1GB. * Results from de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction: - StatisticsResult: Constructed decomposition of program Your program was decomposed into 22 terminating modules (22 trivial, 0 deterministic, 0 nondeterministic) and one nonterminating remainder module.22 modules have a trivial ranking function, the largest among these consists of 5 locations. The remainder module has 60393 locations. - StatisticsResult: Timing statistics BüchiAutomizer plugin needed 16.3s and 23 iterations. TraceHistogramMax:1. Analysis of lassos took 5.4s. Construction of modules took 1.0s. Büchi inclusion checks took 8.4s. Highest rank in rank-based complementation 0. Minimization of det autom 22. Minimization of nondet autom 0. Automata minimization 3.8s AutomataMinimizationTime, 22 MinimizatonAttempts, 15877 StatesRemovedByMinimization, 15 NontrivialMinimizations. Non-live state removal took 2.3s Buchi closure took 0.1s. Biggest automaton had -1 states and ocurred in iteration -1. Nontrivial modules had stage [0, 0, 0, 0, 0]. InterpolantCoveringCapabilityFinite: 0/0 InterpolantCoveringCapabilityBuchi: 0/0 HoareTripleCheckerStatistics: 0 mSolverCounterUnknown, 15189 SdHoareTripleChecker+Valid, 1.4s IncrementalHoareTripleChecker+Time, 0 mSdLazyCounter, 15189 mSDsluCounter, 25981 SdHoareTripleChecker+Invalid, 1.1s Time, 0 mProtectedAction, 0 SdHoareTripleChecker+Unchecked, 0 IncrementalHoareTripleChecker+Unchecked, 12388 mSDsCounter, 264 IncrementalHoareTripleChecker+Valid, 0 mProtectedPredicate, 715 IncrementalHoareTripleChecker+Invalid, 979 SdHoareTripleChecker+Unknown, 0 mSolverCounterNotChecked, 264 mSolverCounterUnsat, 13593 mSDtfsCounter, 715 mSolverCounterSat, 0.2s SdHoareTripleChecker+Time, 0 IncrementalHoareTripleChecker+Unknown LassoAnalysisResults: nont1 unkn0 SFLI4 SFLT0 conc4 concLT0 SILN1 SILU0 SILI13 SILT0 lasso0 LassoPreprocessingBenchmarks: LassoTerminationAnalysisBenchmarks: not availableLassoTerminationAnalysisBenchmarks: LassoNonterminationAnalysisSatFixpoint: 0 LassoNonterminationAnalysisSatUnbounded: 0 LassoNonterminationAnalysisUnsat: 0 LassoNonterminationAnalysisUnknown: 0 LassoNonterminationAnalysisTime: 0.0s InitialAbstractionConstructionTime: 0.0s - TerminationAnalysisResult: Nontermination possible Buchi Automizer proved that your program is nonterminating for some inputs - LassoShapedNonTerminationArgument [Line: 411]: Nontermination argument in form of an infinite program execution. Nontermination argument in form of an infinite program execution. Stem: [L25] int m_pc = 0; [L26] int t1_pc = 0; [L27] int t2_pc = 0; [L28] int t3_pc = 0; [L29] int t4_pc = 0; [L30] int m_st ; [L31] int t1_st ; [L32] int t2_st ; [L33] int t3_st ; [L34] int t4_st ; [L35] int m_i ; [L36] int t1_i ; [L37] int t2_i ; [L38] int t3_i ; [L39] int t4_i ; [L40] int M_E = 2; [L41] int T1_E = 2; [L42] int T2_E = 2; [L43] int T3_E = 2; [L44] int T4_E = 2; [L45] int E_1 = 2; [L46] int E_2 = 2; [L47] int E_3 = 2; [L48] int E_4 = 2; VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, m_i=0, m_pc=0, m_st=0, t1_i=0, t1_pc=0, t1_st=0, t2_i=0, t2_pc=0, t2_st=0, t3_i=0, t3_pc=0, t3_st=0, t4_i=0, t4_pc=0, t4_st=0] [L821] int __retres1 ; [L825] CALL init_model() [L733] m_i = 1 [L734] t1_i = 1 [L735] t2_i = 1 [L736] t3_i = 1 [L737] t4_i = 1 VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0] [L825] RET init_model() [L826] CALL start_simulation() [L762] int kernel_st ; [L763] int tmp ; [L764] int tmp___0 ; [L768] kernel_st = 0 [L769] FCALL update_channels() [L770] CALL init_threads() [L341] COND TRUE m_i == 1 [L342] m_st = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0] [L346] COND TRUE t1_i == 1 [L347] t1_st = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0] [L351] COND TRUE t2_i == 1 [L352] t2_st = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0] [L356] COND TRUE t3_i == 1 [L357] t3_st = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0] [L361] COND TRUE t4_i == 1 [L362] t4_st = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0] [L770] RET init_threads() [L771] CALL fire_delta_events() [L502] COND FALSE !(M_E == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0] [L507] COND FALSE !(T1_E == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0] [L512] COND FALSE !(T2_E == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0] [L517] COND FALSE !(T3_E == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0] [L522] COND FALSE !(T4_E == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0] [L527] COND FALSE !(E_1 == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0] [L532] COND FALSE !(E_2 == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0] [L537] COND FALSE !(E_3 == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0] [L542] COND FALSE !(E_4 == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0] [L771] RET fire_delta_events() [L772] CALL activate_threads() [L605] int tmp ; [L606] int tmp___0 ; [L607] int tmp___1 ; [L608] int tmp___2 ; [L609] int tmp___3 ; [L613] CALL, EXPR is_master_triggered() [L235] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0] [L238] COND FALSE !(m_pc == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0] [L248] __retres1 = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, __retres1=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0] [L250] return (__retres1); VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, \result=0, __retres1=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0] [L613] RET, EXPR is_master_triggered() [L613] tmp = is_master_triggered() [L615] COND FALSE !(\read(tmp)) VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, tmp=0] [L621] CALL, EXPR is_transmit1_triggered() [L254] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0] [L257] COND FALSE !(t1_pc == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0] [L267] __retres1 = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, __retres1=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0] [L269] return (__retres1); VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, \result=0, __retres1=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0] [L621] RET, EXPR is_transmit1_triggered() [L621] tmp___0 = is_transmit1_triggered() [L623] COND FALSE !(\read(tmp___0)) VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, tmp=0, tmp___0=0] [L629] CALL, EXPR is_transmit2_triggered() [L273] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0] [L276] COND FALSE !(t2_pc == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0] [L286] __retres1 = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, __retres1=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0] [L288] return (__retres1); VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, \result=0, __retres1=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0] [L629] RET, EXPR is_transmit2_triggered() [L629] tmp___1 = is_transmit2_triggered() [L631] COND FALSE !(\read(tmp___1)) VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, tmp=0, tmp___0=0, tmp___1=0] [L637] CALL, EXPR is_transmit3_triggered() [L292] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0] [L295] COND FALSE !(t3_pc == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0] [L305] __retres1 = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, __retres1=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0] [L307] return (__retres1); VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, \result=0, __retres1=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0] [L637] RET, EXPR is_transmit3_triggered() [L637] tmp___2 = is_transmit3_triggered() [L639] COND FALSE !(\read(tmp___2)) VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, tmp=0, tmp___0=0, tmp___1=0, tmp___2=0] [L645] CALL, EXPR is_transmit4_triggered() [L311] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0] [L314] COND FALSE !(t4_pc == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0] [L324] __retres1 = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, __retres1=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0] [L326] return (__retres1); VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, \result=0, __retres1=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0] [L645] RET, EXPR is_transmit4_triggered() [L645] tmp___3 = is_transmit4_triggered() [L647] COND FALSE !(\read(tmp___3)) VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, tmp=0, tmp___0=0, tmp___1=0, tmp___2=0, tmp___3=0] [L772] RET activate_threads() [L773] CALL reset_delta_events() [L555] COND FALSE !(M_E == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0] [L560] COND FALSE !(T1_E == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0] [L565] COND FALSE !(T2_E == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0] [L570] COND FALSE !(T3_E == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0] [L575] COND FALSE !(T4_E == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0] [L580] COND FALSE !(E_1 == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0] [L585] COND FALSE !(E_2 == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0] [L590] COND FALSE !(E_3 == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0] [L595] COND FALSE !(E_4 == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0] [L773] RET reset_delta_events() [L776] COND TRUE 1 VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, kernel_st=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0] [L779] kernel_st = 1 [L780] CALL eval() [L407] int tmp ; VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0] Loop: [L411] COND TRUE 1 [L414] CALL, EXPR exists_runnable_thread() [L371] int __retres1 ; [L374] COND TRUE m_st == 0 [L375] __retres1 = 1 [L402] return (__retres1); [L414] RET, EXPR exists_runnable_thread() [L414] tmp = exists_runnable_thread() [L416] COND TRUE \read(tmp) [L421] COND TRUE m_st == 0 [L422] int tmp_ndt_1; [L423] EXPR tmp_ndt_1 = __VERIFIER_nondet_int() [L424] COND FALSE, EXPR !(\read(tmp_ndt_1)) [L421-L432] { int tmp_ndt_1; tmp_ndt_1 = __VERIFIER_nondet_int(); if (tmp_ndt_1) { { m_st = 1; master(); } } else { } } [L435] COND TRUE t1_st == 0 [L436] int tmp_ndt_2; [L437] EXPR tmp_ndt_2 = __VERIFIER_nondet_int() [L438] COND FALSE, EXPR !(\read(tmp_ndt_2)) [L435-L446] { int tmp_ndt_2; tmp_ndt_2 = __VERIFIER_nondet_int(); if (tmp_ndt_2) { { t1_st = 1; transmit1(); } } else { } } [L449] COND TRUE t2_st == 0 [L450] int tmp_ndt_3; [L451] EXPR tmp_ndt_3 = __VERIFIER_nondet_int() [L452] COND FALSE, EXPR !(\read(tmp_ndt_3)) [L449-L460] { int tmp_ndt_3; tmp_ndt_3 = __VERIFIER_nondet_int(); if (tmp_ndt_3) { { t2_st = 1; transmit2(); } } else { } } [L463] COND TRUE t3_st == 0 [L464] int tmp_ndt_4; [L465] EXPR tmp_ndt_4 = __VERIFIER_nondet_int() [L466] COND FALSE, EXPR !(\read(tmp_ndt_4)) [L463-L474] { int tmp_ndt_4; tmp_ndt_4 = __VERIFIER_nondet_int(); if (tmp_ndt_4) { { t3_st = 1; transmit3(); } } else { } } [L477] COND TRUE t4_st == 0 [L478] int tmp_ndt_5; [L479] EXPR tmp_ndt_5 = __VERIFIER_nondet_int() [L480] COND FALSE, EXPR !(\read(tmp_ndt_5)) [L477-L488] { int tmp_ndt_5; tmp_ndt_5 = __VERIFIER_nondet_int(); if (tmp_ndt_5) { { t4_st = 1; transmit4(); } } else { } } End of lasso representation. - StatisticsResult: NonterminationArgumentStatistics Fixpoint - NonterminatingLassoResult [Line: 411]: Nonterminating execution Found a nonterminating execution for the following lasso shaped sequence of statements. Stem: [L25] int m_pc = 0; [L26] int t1_pc = 0; [L27] int t2_pc = 0; [L28] int t3_pc = 0; [L29] int t4_pc = 0; [L30] int m_st ; [L31] int t1_st ; [L32] int t2_st ; [L33] int t3_st ; [L34] int t4_st ; [L35] int m_i ; [L36] int t1_i ; [L37] int t2_i ; [L38] int t3_i ; [L39] int t4_i ; [L40] int M_E = 2; [L41] int T1_E = 2; [L42] int T2_E = 2; [L43] int T3_E = 2; [L44] int T4_E = 2; [L45] int E_1 = 2; [L46] int E_2 = 2; [L47] int E_3 = 2; [L48] int E_4 = 2; VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, m_i=0, m_pc=0, m_st=0, t1_i=0, t1_pc=0, t1_st=0, t2_i=0, t2_pc=0, t2_st=0, t3_i=0, t3_pc=0, t3_st=0, t4_i=0, t4_pc=0, t4_st=0] [L821] int __retres1 ; [L825] CALL init_model() [L733] m_i = 1 [L734] t1_i = 1 [L735] t2_i = 1 [L736] t3_i = 1 [L737] t4_i = 1 VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0] [L825] RET init_model() [L826] CALL start_simulation() [L762] int kernel_st ; [L763] int tmp ; [L764] int tmp___0 ; [L768] kernel_st = 0 [L769] FCALL update_channels() [L770] CALL init_threads() [L341] COND TRUE m_i == 1 [L342] m_st = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0] [L346] COND TRUE t1_i == 1 [L347] t1_st = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0] [L351] COND TRUE t2_i == 1 [L352] t2_st = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0] [L356] COND TRUE t3_i == 1 [L357] t3_st = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0] [L361] COND TRUE t4_i == 1 [L362] t4_st = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0] [L770] RET init_threads() [L771] CALL fire_delta_events() [L502] COND FALSE !(M_E == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0] [L507] COND FALSE !(T1_E == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0] [L512] COND FALSE !(T2_E == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0] [L517] COND FALSE !(T3_E == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0] [L522] COND FALSE !(T4_E == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0] [L527] COND FALSE !(E_1 == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0] [L532] COND FALSE !(E_2 == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0] [L537] COND FALSE !(E_3 == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0] [L542] COND FALSE !(E_4 == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0] [L771] RET fire_delta_events() [L772] CALL activate_threads() [L605] int tmp ; [L606] int tmp___0 ; [L607] int tmp___1 ; [L608] int tmp___2 ; [L609] int tmp___3 ; [L613] CALL, EXPR is_master_triggered() [L235] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0] [L238] COND FALSE !(m_pc == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0] [L248] __retres1 = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, __retres1=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0] [L250] return (__retres1); VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, \result=0, __retres1=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0] [L613] RET, EXPR is_master_triggered() [L613] tmp = is_master_triggered() [L615] COND FALSE !(\read(tmp)) VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, tmp=0] [L621] CALL, EXPR is_transmit1_triggered() [L254] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0] [L257] COND FALSE !(t1_pc == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0] [L267] __retres1 = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, __retres1=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0] [L269] return (__retres1); VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, \result=0, __retres1=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0] [L621] RET, EXPR is_transmit1_triggered() [L621] tmp___0 = is_transmit1_triggered() [L623] COND FALSE !(\read(tmp___0)) VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, tmp=0, tmp___0=0] [L629] CALL, EXPR is_transmit2_triggered() [L273] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0] [L276] COND FALSE !(t2_pc == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0] [L286] __retres1 = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, __retres1=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0] [L288] return (__retres1); VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, \result=0, __retres1=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0] [L629] RET, EXPR is_transmit2_triggered() [L629] tmp___1 = is_transmit2_triggered() [L631] COND FALSE !(\read(tmp___1)) VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, tmp=0, tmp___0=0, tmp___1=0] [L637] CALL, EXPR is_transmit3_triggered() [L292] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0] [L295] COND FALSE !(t3_pc == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0] [L305] __retres1 = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, __retres1=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0] [L307] return (__retres1); VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, \result=0, __retres1=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0] [L637] RET, EXPR is_transmit3_triggered() [L637] tmp___2 = is_transmit3_triggered() [L639] COND FALSE !(\read(tmp___2)) VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, tmp=0, tmp___0=0, tmp___1=0, tmp___2=0] [L645] CALL, EXPR is_transmit4_triggered() [L311] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0] [L314] COND FALSE !(t4_pc == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0] [L324] __retres1 = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, __retres1=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0] [L326] return (__retres1); VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, \result=0, __retres1=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0] [L645] RET, EXPR is_transmit4_triggered() [L645] tmp___3 = is_transmit4_triggered() [L647] COND FALSE !(\read(tmp___3)) VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, tmp=0, tmp___0=0, tmp___1=0, tmp___2=0, tmp___3=0] [L772] RET activate_threads() [L773] CALL reset_delta_events() [L555] COND FALSE !(M_E == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0] [L560] COND FALSE !(T1_E == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0] [L565] COND FALSE !(T2_E == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0] [L570] COND FALSE !(T3_E == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0] [L575] COND FALSE !(T4_E == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0] [L580] COND FALSE !(E_1 == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0] [L585] COND FALSE !(E_2 == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0] [L590] COND FALSE !(E_3 == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0] [L595] COND FALSE !(E_4 == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0] [L773] RET reset_delta_events() [L776] COND TRUE 1 VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, kernel_st=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0] [L779] kernel_st = 1 [L780] CALL eval() [L407] int tmp ; VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0] Loop: [L411] COND TRUE 1 [L414] CALL, EXPR exists_runnable_thread() [L371] int __retres1 ; [L374] COND TRUE m_st == 0 [L375] __retres1 = 1 [L402] return (__retres1); [L414] RET, EXPR exists_runnable_thread() [L414] tmp = exists_runnable_thread() [L416] COND TRUE \read(tmp) [L421] COND TRUE m_st == 0 [L422] int tmp_ndt_1; [L423] EXPR tmp_ndt_1 = __VERIFIER_nondet_int() [L424] COND FALSE, EXPR !(\read(tmp_ndt_1)) [L421-L432] { int tmp_ndt_1; tmp_ndt_1 = __VERIFIER_nondet_int(); if (tmp_ndt_1) { { m_st = 1; master(); } } else { } } [L435] COND TRUE t1_st == 0 [L436] int tmp_ndt_2; [L437] EXPR tmp_ndt_2 = __VERIFIER_nondet_int() [L438] COND FALSE, EXPR !(\read(tmp_ndt_2)) [L435-L446] { int tmp_ndt_2; tmp_ndt_2 = __VERIFIER_nondet_int(); if (tmp_ndt_2) { { t1_st = 1; transmit1(); } } else { } } [L449] COND TRUE t2_st == 0 [L450] int tmp_ndt_3; [L451] EXPR tmp_ndt_3 = __VERIFIER_nondet_int() [L452] COND FALSE, EXPR !(\read(tmp_ndt_3)) [L449-L460] { int tmp_ndt_3; tmp_ndt_3 = __VERIFIER_nondet_int(); if (tmp_ndt_3) { { t2_st = 1; transmit2(); } } else { } } [L463] COND TRUE t3_st == 0 [L464] int tmp_ndt_4; [L465] EXPR tmp_ndt_4 = __VERIFIER_nondet_int() [L466] COND FALSE, EXPR !(\read(tmp_ndt_4)) [L463-L474] { int tmp_ndt_4; tmp_ndt_4 = __VERIFIER_nondet_int(); if (tmp_ndt_4) { { t3_st = 1; transmit3(); } } else { } } [L477] COND TRUE t4_st == 0 [L478] int tmp_ndt_5; [L479] EXPR tmp_ndt_5 = __VERIFIER_nondet_int() [L480] COND FALSE, EXPR !(\read(tmp_ndt_5)) [L477-L488] { int tmp_ndt_5; tmp_ndt_5 = __VERIFIER_nondet_int(); if (tmp_ndt_5) { { t4_st = 1; transmit4(); } } else { } } End of lasso representation. RESULT: Ultimate proved your program to be incorrect! [2023-11-12 02:12:15,956 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_b9c4b66b-8a73-49ee-9f7b-92ffbd0a3c3e/bin/uautomizer-verify-uTZkv6EMXl/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (1)] Forceful destruction successful, exit code 0 Received shutdown request... --- End real Ultimate output --- Execution finished normally Writing output log to file Ultimate.log Writing human readable error path to file UltimateCounterExample.errorpath Result: FALSE(TERM)