./Ultimate.py --spec ../../sv-benchmarks/c/properties/termination.prp --file ../../sv-benchmarks/c/systemc/transmitter.07.cil.c --full-output --architecture 32bit -------------------------------------------------------------------------------- Checking for termination Using default analysis Version cf1a7837 Calling Ultimate with: /usr/lib/jvm/java-1.11.0-openjdk-amd64/bin/java -Dosgi.configuration.area=/tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_59f24d8a-c2b1-4f81-becc-22ea5ac173f8/bin/uautomizer-verify-uTZkv6EMXl/data/config -Xmx15G -Xms4m -jar /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_59f24d8a-c2b1-4f81-becc-22ea5ac173f8/bin/uautomizer-verify-uTZkv6EMXl/plugins/org.eclipse.equinox.launcher_1.5.800.v20200727-1323.jar -data @noDefault -ultimatedata /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_59f24d8a-c2b1-4f81-becc-22ea5ac173f8/bin/uautomizer-verify-uTZkv6EMXl/data -tc /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_59f24d8a-c2b1-4f81-becc-22ea5ac173f8/bin/uautomizer-verify-uTZkv6EMXl/config/AutomizerTermination.xml -i ../../sv-benchmarks/c/systemc/transmitter.07.cil.c -s /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_59f24d8a-c2b1-4f81-becc-22ea5ac173f8/bin/uautomizer-verify-uTZkv6EMXl/config/svcomp-Termination-32bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_59f24d8a-c2b1-4f81-becc-22ea5ac173f8/bin/uautomizer-verify-uTZkv6EMXl --witnessprinter.witness.filename witness --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(F end) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 32bit --witnessprinter.graph.data.programhash 022987cd4c8c671e376c5c3e5a08e2f1b98444b4d5d48bc73787bff74aa0de0f --- Real Ultimate output --- This is Ultimate 0.2.3-dev-cf1a783 [2023-11-12 02:09:23,424 INFO L188 SettingsManager]: Resetting all preferences to default values... [2023-11-12 02:09:23,491 INFO L114 SettingsManager]: Loading settings from /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_59f24d8a-c2b1-4f81-becc-22ea5ac173f8/bin/uautomizer-verify-uTZkv6EMXl/config/svcomp-Termination-32bit-Automizer_Default.epf [2023-11-12 02:09:23,496 WARN L101 SettingsManager]: Preference file contains the following unknown settings: [2023-11-12 02:09:23,497 WARN L103 SettingsManager]: * de.uni_freiburg.informatik.ultimate.core.Log level for class [2023-11-12 02:09:23,523 INFO L130 SettingsManager]: Preferences different from defaults after loading the file: [2023-11-12 02:09:23,524 INFO L151 SettingsManager]: Preferences of UltimateCore differ from their defaults: [2023-11-12 02:09:23,525 INFO L153 SettingsManager]: * Log level for class=de.uni_freiburg.informatik.ultimate.lib.smtlibutils.quantifier.QuantifierPusher=ERROR; [2023-11-12 02:09:23,526 INFO L151 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2023-11-12 02:09:23,527 INFO L153 SettingsManager]: * Create parallel compositions if possible=false [2023-11-12 02:09:23,528 INFO L153 SettingsManager]: * Use SBE=true [2023-11-12 02:09:23,528 INFO L151 SettingsManager]: Preferences of BuchiAutomizer differ from their defaults: [2023-11-12 02:09:23,529 INFO L153 SettingsManager]: * NCSB implementation=INTSET_LAZY3 [2023-11-12 02:09:23,530 INFO L153 SettingsManager]: * Use old map elimination=false [2023-11-12 02:09:23,530 INFO L153 SettingsManager]: * Use external solver (rank synthesis)=false [2023-11-12 02:09:23,531 INFO L153 SettingsManager]: * Use only trivial implications for array writes=true [2023-11-12 02:09:23,531 INFO L153 SettingsManager]: * Rank analysis=LINEAR_WITH_GUESSES [2023-11-12 02:09:23,532 INFO L151 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2023-11-12 02:09:23,532 INFO L153 SettingsManager]: * Pointer base address is valid at dereference=ASSUME [2023-11-12 02:09:23,533 INFO L153 SettingsManager]: * sizeof long=4 [2023-11-12 02:09:23,534 INFO L153 SettingsManager]: * Overapproximate operations on floating types=true [2023-11-12 02:09:23,535 INFO L153 SettingsManager]: * sizeof POINTER=4 [2023-11-12 02:09:23,535 INFO L153 SettingsManager]: * Check division by zero=IGNORE [2023-11-12 02:09:23,536 INFO L153 SettingsManager]: * Pointer to allocated memory at dereference=ASSUME [2023-11-12 02:09:23,538 INFO L153 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=ASSUME [2023-11-12 02:09:23,538 INFO L153 SettingsManager]: * Check array bounds for arrays that are off heap=ASSUME [2023-11-12 02:09:23,539 INFO L153 SettingsManager]: * Check unreachability of reach_error function=false [2023-11-12 02:09:23,539 INFO L153 SettingsManager]: * sizeof long double=12 [2023-11-12 02:09:23,539 INFO L153 SettingsManager]: * Check if freed pointer was valid=false [2023-11-12 02:09:23,540 INFO L153 SettingsManager]: * Assume nondeterminstic values are in range=false [2023-11-12 02:09:23,541 INFO L153 SettingsManager]: * Use constant arrays=true [2023-11-12 02:09:23,542 INFO L151 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2023-11-12 02:09:23,542 INFO L153 SettingsManager]: * Size of a code block=SequenceOfStatements [2023-11-12 02:09:23,543 INFO L151 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2023-11-12 02:09:23,543 INFO L153 SettingsManager]: * Trace refinement strategy=CAMEL [2023-11-12 02:09:23,544 INFO L151 SettingsManager]: Preferences of IcfgTransformer differ from their defaults: [2023-11-12 02:09:23,545 INFO L153 SettingsManager]: * TransformationType=MODULO_NEIGHBOR WARNING: An illegal reflective access operation has occurred WARNING: Illegal reflective access by com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 (file:/tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_59f24d8a-c2b1-4f81-becc-22ea5ac173f8/bin/uautomizer-verify-uTZkv6EMXl/plugins/com.sun.xml.bind_2.2.0.v201505121915.jar) to method java.lang.ClassLoader.defineClass(java.lang.String,byte[],int,int) WARNING: Please consider reporting this to the maintainers of com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 WARNING: Use --illegal-access=warn to enable warnings of further illegal reflective access operations WARNING: All illegal access operations will be denied in a future release Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_59f24d8a-c2b1-4f81-becc-22ea5ac173f8/bin/uautomizer-verify-uTZkv6EMXl Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(F end) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 32bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> 022987cd4c8c671e376c5c3e5a08e2f1b98444b4d5d48bc73787bff74aa0de0f [2023-11-12 02:09:23,815 INFO L75 nceAwareModelManager]: Repository-Root is: /tmp [2023-11-12 02:09:23,839 INFO L261 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2023-11-12 02:09:23,842 INFO L217 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2023-11-12 02:09:23,843 INFO L270 PluginConnector]: Initializing CDTParser... [2023-11-12 02:09:23,844 INFO L274 PluginConnector]: CDTParser initialized [2023-11-12 02:09:23,845 INFO L431 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_59f24d8a-c2b1-4f81-becc-22ea5ac173f8/bin/uautomizer-verify-uTZkv6EMXl/../../sv-benchmarks/c/systemc/transmitter.07.cil.c [2023-11-12 02:09:27,062 INFO L533 CDTParser]: Created temporary CDT project at NULL [2023-11-12 02:09:27,432 INFO L384 CDTParser]: Found 1 translation units. [2023-11-12 02:09:27,433 INFO L180 CDTParser]: Scanning /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_59f24d8a-c2b1-4f81-becc-22ea5ac173f8/sv-benchmarks/c/systemc/transmitter.07.cil.c [2023-11-12 02:09:27,458 INFO L427 CDTParser]: About to delete temporary CDT project at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_59f24d8a-c2b1-4f81-becc-22ea5ac173f8/bin/uautomizer-verify-uTZkv6EMXl/data/9e3163223/4bcff5ee85c544b5b34e881ae8f326d5/FLAG1a6d52c5d [2023-11-12 02:09:27,474 INFO L435 CDTParser]: Successfully deleted /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_59f24d8a-c2b1-4f81-becc-22ea5ac173f8/bin/uautomizer-verify-uTZkv6EMXl/data/9e3163223/4bcff5ee85c544b5b34e881ae8f326d5 [2023-11-12 02:09:27,477 INFO L299 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2023-11-12 02:09:27,479 INFO L133 ToolchainWalker]: Walking toolchain with 6 elements. [2023-11-12 02:09:27,480 INFO L112 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2023-11-12 02:09:27,480 INFO L270 PluginConnector]: Initializing CACSL2BoogieTranslator... [2023-11-12 02:09:27,486 INFO L274 PluginConnector]: CACSL2BoogieTranslator initialized [2023-11-12 02:09:27,487 INFO L184 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 12.11 02:09:27" (1/1) ... [2023-11-12 02:09:27,488 INFO L204 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@23517097 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 12.11 02:09:27, skipping insertion in model container [2023-11-12 02:09:27,488 INFO L184 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 12.11 02:09:27" (1/1) ... [2023-11-12 02:09:27,558 INFO L177 MainTranslator]: Built tables and reachable declarations [2023-11-12 02:09:27,820 INFO L209 PostProcessor]: Analyzing one entry point: main [2023-11-12 02:09:27,842 INFO L202 MainTranslator]: Completed pre-run [2023-11-12 02:09:27,920 INFO L209 PostProcessor]: Analyzing one entry point: main [2023-11-12 02:09:27,941 INFO L206 MainTranslator]: Completed translation [2023-11-12 02:09:27,942 INFO L201 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 12.11 02:09:27 WrapperNode [2023-11-12 02:09:27,942 INFO L131 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2023-11-12 02:09:27,943 INFO L112 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2023-11-12 02:09:27,943 INFO L270 PluginConnector]: Initializing Boogie Procedure Inliner... [2023-11-12 02:09:27,943 INFO L274 PluginConnector]: Boogie Procedure Inliner initialized [2023-11-12 02:09:27,951 INFO L184 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 12.11 02:09:27" (1/1) ... [2023-11-12 02:09:27,965 INFO L184 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 12.11 02:09:27" (1/1) ... [2023-11-12 02:09:28,073 INFO L138 Inliner]: procedures = 42, calls = 52, calls flagged for inlining = 47, calls inlined = 125, statements flattened = 1861 [2023-11-12 02:09:28,074 INFO L131 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2023-11-12 02:09:28,075 INFO L112 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2023-11-12 02:09:28,075 INFO L270 PluginConnector]: Initializing Boogie Preprocessor... [2023-11-12 02:09:28,075 INFO L274 PluginConnector]: Boogie Preprocessor initialized [2023-11-12 02:09:28,087 INFO L184 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 12.11 02:09:27" (1/1) ... [2023-11-12 02:09:28,088 INFO L184 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 12.11 02:09:27" (1/1) ... [2023-11-12 02:09:28,108 INFO L184 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 12.11 02:09:27" (1/1) ... [2023-11-12 02:09:28,108 INFO L184 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 12.11 02:09:27" (1/1) ... [2023-11-12 02:09:28,169 INFO L184 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 12.11 02:09:27" (1/1) ... [2023-11-12 02:09:28,199 INFO L184 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 12.11 02:09:27" (1/1) ... [2023-11-12 02:09:28,204 INFO L184 PluginConnector]: Executing the observer LTLStepAnnotator from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 12.11 02:09:27" (1/1) ... [2023-11-12 02:09:28,211 INFO L184 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 12.11 02:09:27" (1/1) ... [2023-11-12 02:09:28,221 INFO L131 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2023-11-12 02:09:28,222 INFO L112 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2023-11-12 02:09:28,223 INFO L270 PluginConnector]: Initializing RCFGBuilder... [2023-11-12 02:09:28,223 INFO L274 PluginConnector]: RCFGBuilder initialized [2023-11-12 02:09:28,224 INFO L184 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 12.11 02:09:27" (1/1) ... [2023-11-12 02:09:28,231 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2023-11-12 02:09:28,244 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_59f24d8a-c2b1-4f81-becc-22ea5ac173f8/bin/uautomizer-verify-uTZkv6EMXl/z3 [2023-11-12 02:09:28,264 INFO L229 MonitoredProcess]: Starting monitored process 1 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_59f24d8a-c2b1-4f81-becc-22ea5ac173f8/bin/uautomizer-verify-uTZkv6EMXl/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2023-11-12 02:09:28,292 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_59f24d8a-c2b1-4f81-becc-22ea5ac173f8/bin/uautomizer-verify-uTZkv6EMXl/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (1)] Waiting until timeout for monitored process [2023-11-12 02:09:28,349 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocInit [2023-11-12 02:09:28,349 INFO L130 BoogieDeclarations]: Found specification of procedure write~init~int [2023-11-12 02:09:28,349 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2023-11-12 02:09:28,349 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2023-11-12 02:09:28,519 INFO L236 CfgBuilder]: Building ICFG [2023-11-12 02:09:28,522 INFO L262 CfgBuilder]: Building CFG for each procedure with an implementation [2023-11-12 02:09:30,093 INFO L277 CfgBuilder]: Performing block encoding [2023-11-12 02:09:30,110 INFO L297 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2023-11-12 02:09:30,110 INFO L302 CfgBuilder]: Removed 11 assume(true) statements. [2023-11-12 02:09:30,114 INFO L201 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 12.11 02:09:30 BoogieIcfgContainer [2023-11-12 02:09:30,114 INFO L131 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2023-11-12 02:09:30,116 INFO L112 PluginConnector]: ------------------------BuchiAutomizer---------------------------- [2023-11-12 02:09:30,116 INFO L270 PluginConnector]: Initializing BuchiAutomizer... [2023-11-12 02:09:30,121 INFO L274 PluginConnector]: BuchiAutomizer initialized [2023-11-12 02:09:30,122 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2023-11-12 02:09:30,122 INFO L184 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "CDTParser AST 12.11 02:09:27" (1/3) ... [2023-11-12 02:09:30,123 INFO L204 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@1a8f825b and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 12.11 02:09:30, skipping insertion in model container [2023-11-12 02:09:30,124 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2023-11-12 02:09:30,124 INFO L184 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 12.11 02:09:27" (2/3) ... [2023-11-12 02:09:30,125 INFO L204 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@1a8f825b and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 12.11 02:09:30, skipping insertion in model container [2023-11-12 02:09:30,125 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2023-11-12 02:09:30,125 INFO L184 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 12.11 02:09:30" (3/3) ... [2023-11-12 02:09:30,127 INFO L332 chiAutomizerObserver]: Analyzing ICFG transmitter.07.cil.c [2023-11-12 02:09:30,215 INFO L303 stractBuchiCegarLoop]: Interprodecural is true [2023-11-12 02:09:30,216 INFO L304 stractBuchiCegarLoop]: Hoare is false [2023-11-12 02:09:30,216 INFO L305 stractBuchiCegarLoop]: Compute interpolants for ForwardPredicates [2023-11-12 02:09:30,216 INFO L306 stractBuchiCegarLoop]: Backedges is STRAIGHT_LINE [2023-11-12 02:09:30,217 INFO L307 stractBuchiCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2023-11-12 02:09:30,217 INFO L308 stractBuchiCegarLoop]: Difference is false [2023-11-12 02:09:30,217 INFO L309 stractBuchiCegarLoop]: Minimize is MINIMIZE_SEVPA [2023-11-12 02:09:30,217 INFO L313 stractBuchiCegarLoop]: ======== Iteration 0 == of CEGAR loop == BuchiAutomatonCegarLoop ======== [2023-11-12 02:09:30,227 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 784 states, 783 states have (on average 1.5172413793103448) internal successors, (1188), 783 states have internal predecessors, (1188), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-12 02:09:30,299 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 679 [2023-11-12 02:09:30,299 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-12 02:09:30,300 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-12 02:09:30,317 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-12 02:09:30,318 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-12 02:09:30,318 INFO L335 stractBuchiCegarLoop]: ======== Iteration 1 ============ [2023-11-12 02:09:30,326 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 784 states, 783 states have (on average 1.5172413793103448) internal successors, (1188), 783 states have internal predecessors, (1188), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-12 02:09:30,353 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 679 [2023-11-12 02:09:30,354 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-12 02:09:30,354 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-12 02:09:30,366 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-12 02:09:30,366 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-12 02:09:30,377 INFO L748 eck$LassoCheckResult]: Stem: 107#$Ultimate##0true assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2; 718#L-1true assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~9#1;havoc main_~__retres1~9#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 570#init_model_returnLabel#1true assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret22#1, start_simulation_#t~ret23#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 715#update_channels_returnLabel#1true assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 650#L521true assume !(1 == ~m_i~0);~m_st~0 := 2; 612#L521-2true assume 1 == ~t1_i~0;~t1_st~0 := 0; 643#L526-1true assume !(1 == ~t2_i~0);~t2_st~0 := 2; 193#L531-1true assume !(1 == ~t3_i~0);~t3_st~0 := 2; 549#L536-1true assume !(1 == ~t4_i~0);~t4_st~0 := 2; 240#L541-1true assume !(1 == ~t5_i~0);~t5_st~0 := 2; 138#L546-1true assume !(1 == ~t6_i~0);~t6_st~0 := 2; 601#L551-1true assume !(1 == ~t7_i~0);~t7_st~0 := 2; 122#L556-1true assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 689#L754true assume !(0 == ~M_E~0); 737#L754-2true assume !(0 == ~T1_E~0); 509#L759-1true assume !(0 == ~T2_E~0); 376#L764-1true assume !(0 == ~T3_E~0); 339#L769-1true assume !(0 == ~T4_E~0); 377#L774-1true assume !(0 == ~T5_E~0); 636#L779-1true assume 0 == ~T6_E~0;~T6_E~0 := 1; 519#L784-1true assume !(0 == ~T7_E~0); 337#L789-1true assume !(0 == ~E_1~0); 424#L794-1true assume !(0 == ~E_2~0); 765#L799-1true assume !(0 == ~E_3~0); 346#L804-1true assume !(0 == ~E_4~0); 372#L809-1true assume !(0 == ~E_5~0); 550#L814-1true assume !(0 == ~E_6~0); 9#L819-1true assume 0 == ~E_7~0;~E_7~0 := 1; 171#L824-1true assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 137#L361true assume 1 == ~m_pc~0; 676#L362true assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 712#L372true is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 499#is_master_triggered_returnLabel#1true activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 633#L930true assume !(0 != activate_threads_~tmp~1#1); 272#L930-2true assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 134#L380true assume !(1 == ~t1_pc~0); 766#L380-2true is_transmit1_triggered_~__retres1~1#1 := 0; 644#L391true is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 20#is_transmit1_triggered_returnLabel#1true activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 770#L938true assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 460#L938-2true assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 438#L399true assume 1 == ~t2_pc~0; 638#L400true assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 654#L410true is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 179#is_transmit2_triggered_returnLabel#1true activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 175#L946true assume !(0 != activate_threads_~tmp___1~0#1); 414#L946-2true assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 13#L418true assume !(1 == ~t3_pc~0); 698#L418-2true is_transmit3_triggered_~__retres1~3#1 := 0; 552#L429true is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 8#is_transmit3_triggered_returnLabel#1true activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 777#L954true assume !(0 != activate_threads_~tmp___2~0#1); 361#L954-2true assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 691#L437true assume 1 == ~t4_pc~0; 755#L438true assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 494#L448true is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 47#is_transmit4_triggered_returnLabel#1true activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 209#L962true assume !(0 != activate_threads_~tmp___3~0#1); 592#L962-2true assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 478#L456true assume !(1 == ~t5_pc~0); 330#L456-2true is_transmit5_triggered_~__retres1~5#1 := 0; 681#L467true is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 502#is_transmit5_triggered_returnLabel#1true activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 410#L970true assume !(0 != activate_threads_~tmp___4~0#1); 734#L970-2true assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 45#L475true assume 1 == ~t6_pc~0; 221#L476true assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 66#L486true is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 169#is_transmit6_triggered_returnLabel#1true activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 402#L978true assume !(0 != activate_threads_~tmp___5~0#1); 351#L978-2true assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 547#L494true assume 1 == ~t7_pc~0; 304#L495true assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 316#L505true is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 731#is_transmit7_triggered_returnLabel#1true activate_threads_#t~ret20#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 378#L986true assume !(0 != activate_threads_~tmp___6~0#1); 761#L986-2true havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 668#L837true assume !(1 == ~M_E~0); 569#L837-2true assume !(1 == ~T1_E~0); 433#L842-1true assume !(1 == ~T2_E~0); 216#L847-1true assume !(1 == ~T3_E~0); 265#L852-1true assume !(1 == ~T4_E~0); 781#L857-1true assume 1 == ~T5_E~0;~T5_E~0 := 2; 182#L862-1true assume !(1 == ~T6_E~0); 189#L867-1true assume !(1 == ~T7_E~0); 239#L872-1true assume !(1 == ~E_1~0); 391#L877-1true assume !(1 == ~E_2~0); 578#L882-1true assume !(1 == ~E_3~0); 707#L887-1true assume !(1 == ~E_4~0); 454#L892-1true assume !(1 == ~E_5~0); 660#L897-1true assume 1 == ~E_6~0;~E_6~0 := 2; 199#L902-1true assume !(1 == ~E_7~0); 477#L907-1true assume { :end_inline_reset_delta_events } true; 230#L1148-2true [2023-11-12 02:09:30,380 INFO L750 eck$LassoCheckResult]: Loop: 230#L1148-2true assume !false; 10#L1149true start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 422#L729-1true assume false; 455#eval_returnLabel#1true havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 271#update_channels_returnLabel#2true assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 146#L754-3true assume 0 == ~M_E~0;~M_E~0 := 1; 16#L754-5true assume 0 == ~T1_E~0;~T1_E~0 := 1; 530#L759-3true assume !(0 == ~T2_E~0); 225#L764-3true assume 0 == ~T3_E~0;~T3_E~0 := 1; 616#L769-3true assume 0 == ~T4_E~0;~T4_E~0 := 1; 362#L774-3true assume 0 == ~T5_E~0;~T5_E~0 := 1; 94#L779-3true assume 0 == ~T6_E~0;~T6_E~0 := 1; 14#L784-3true assume 0 == ~T7_E~0;~T7_E~0 := 1; 774#L789-3true assume 0 == ~E_1~0;~E_1~0 := 1; 11#L794-3true assume 0 == ~E_2~0;~E_2~0 := 1; 35#L799-3true assume !(0 == ~E_3~0); 150#L804-3true assume 0 == ~E_4~0;~E_4~0 := 1; 293#L809-3true assume 0 == ~E_5~0;~E_5~0 := 1; 33#L814-3true assume 0 == ~E_6~0;~E_6~0 := 1; 526#L819-3true assume 0 == ~E_7~0;~E_7~0 := 1; 487#L824-3true assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 236#L361-24true assume !(1 == ~m_pc~0); 532#L361-26true is_master_triggered_~__retres1~0#1 := 0; 301#L372-8true is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 59#is_master_triggered_returnLabel#9true activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 553#L930-24true assume !(0 != activate_threads_~tmp~1#1); 584#L930-26true assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 343#L380-24true assume 1 == ~t1_pc~0; 585#L381-8true assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 625#L391-8true is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 297#is_transmit1_triggered_returnLabel#9true activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 144#L938-24true assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 439#L938-26true assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 505#L399-24true assume !(1 == ~t2_pc~0); 154#L399-26true is_transmit2_triggered_~__retres1~2#1 := 0; 110#L410-8true is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 381#is_transmit2_triggered_returnLabel#9true activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 264#L946-24true assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 142#L946-26true assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 624#L418-24true assume 1 == ~t3_pc~0; 551#L419-8true assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 185#L429-8true is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 591#is_transmit3_triggered_returnLabel#9true activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 96#L954-24true assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 412#L954-26true assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 556#L437-24true assume !(1 == ~t4_pc~0); 784#L437-26true is_transmit4_triggered_~__retres1~4#1 := 0; 740#L448-8true is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 263#is_transmit4_triggered_returnLabel#9true activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 88#L962-24true assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 350#L962-26true assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 645#L456-24true assume !(1 == ~t5_pc~0); 738#L456-26true is_transmit5_triggered_~__retres1~5#1 := 0; 307#L467-8true is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 533#is_transmit5_triggered_returnLabel#9true activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 574#L970-24true assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 273#L970-26true assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 769#L475-24true assume 1 == ~t6_pc~0; 15#L476-8true assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 315#L486-8true is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 85#is_transmit6_triggered_returnLabel#9true activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 347#L978-24true assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 6#L978-26true assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 309#L494-24true assume 1 == ~t7_pc~0; 248#L495-8true assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 174#L505-8true is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 257#is_transmit7_triggered_returnLabel#9true activate_threads_#t~ret20#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 140#L986-24true assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 490#L986-26true havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 515#L837-3true assume 1 == ~M_E~0;~M_E~0 := 2; 670#L837-5true assume !(1 == ~T1_E~0); 269#L842-3true assume 1 == ~T2_E~0;~T2_E~0 := 2; 608#L847-3true assume 1 == ~T3_E~0;~T3_E~0 := 2; 408#L852-3true assume 1 == ~T4_E~0;~T4_E~0 := 2; 313#L857-3true assume 1 == ~T5_E~0;~T5_E~0 := 2; 746#L862-3true assume 1 == ~T6_E~0;~T6_E~0 := 2; 703#L867-3true assume 1 == ~T7_E~0;~T7_E~0 := 2; 247#L872-3true assume 1 == ~E_1~0;~E_1~0 := 2; 306#L877-3true assume !(1 == ~E_2~0); 728#L882-3true assume 1 == ~E_3~0;~E_3~0 := 2; 354#L887-3true assume 1 == ~E_4~0;~E_4~0 := 2; 104#L892-3true assume 1 == ~E_5~0;~E_5~0 := 2; 514#L897-3true assume 1 == ~E_6~0;~E_6~0 := 2; 773#L902-3true assume 1 == ~E_7~0;~E_7~0 := 2; 196#L907-3true assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 581#L569-1true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 365#L611-1true exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 155#exists_runnable_thread_returnLabel#2true start_simulation_#t~ret22#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret22#1;havoc start_simulation_#t~ret22#1; 686#L1167true assume !(0 == start_simulation_~tmp~3#1); 233#L1167-2true assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret21#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 745#L569-2true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 254#L611-2true exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 19#exists_runnable_thread_returnLabel#3true stop_simulation_#t~ret21#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret21#1;havoc stop_simulation_#t~ret21#1; 308#L1122true assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 222#L1129true stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 282#stop_simulation_returnLabel#1true start_simulation_#t~ret23#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret21#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret23#1;havoc start_simulation_#t~ret23#1; 121#L1180true assume !(0 != start_simulation_~tmp___0~1#1); 230#L1148-2true [2023-11-12 02:09:30,389 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-12 02:09:30,389 INFO L85 PathProgramCache]: Analyzing trace with hash -171938705, now seen corresponding path program 1 times [2023-11-12 02:09:30,405 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-12 02:09:30,407 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [425422675] [2023-11-12 02:09:30,407 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-12 02:09:30,409 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-12 02:09:30,584 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-12 02:09:30,847 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-12 02:09:30,848 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-12 02:09:30,850 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [425422675] [2023-11-12 02:09:30,851 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [425422675] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-12 02:09:30,851 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-12 02:09:30,852 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-12 02:09:30,854 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [930401496] [2023-11-12 02:09:30,855 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-12 02:09:30,861 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-12 02:09:30,863 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-12 02:09:30,864 INFO L85 PathProgramCache]: Analyzing trace with hash 661713836, now seen corresponding path program 1 times [2023-11-12 02:09:30,864 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-12 02:09:30,864 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1211085301] [2023-11-12 02:09:30,864 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-12 02:09:30,865 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-12 02:09:30,900 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-12 02:09:30,962 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-12 02:09:30,962 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-12 02:09:30,962 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1211085301] [2023-11-12 02:09:30,963 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1211085301] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-12 02:09:30,963 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-12 02:09:30,963 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2023-11-12 02:09:30,963 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1269448001] [2023-11-12 02:09:30,964 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-12 02:09:30,967 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-12 02:09:30,968 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-12 02:09:31,012 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-12 02:09:31,013 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-12 02:09:31,017 INFO L87 Difference]: Start difference. First operand has 784 states, 783 states have (on average 1.5172413793103448) internal successors, (1188), 783 states have internal predecessors, (1188), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand has 3 states, 3 states have (on average 31.0) internal successors, (93), 3 states have internal predecessors, (93), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-12 02:09:31,115 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-12 02:09:31,116 INFO L93 Difference]: Finished difference Result 782 states and 1162 transitions. [2023-11-12 02:09:31,118 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 782 states and 1162 transitions. [2023-11-12 02:09:31,131 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 675 [2023-11-12 02:09:31,178 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 782 states to 776 states and 1156 transitions. [2023-11-12 02:09:31,179 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 776 [2023-11-12 02:09:31,180 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 776 [2023-11-12 02:09:31,181 INFO L73 IsDeterministic]: Start isDeterministic. Operand 776 states and 1156 transitions. [2023-11-12 02:09:31,191 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-12 02:09:31,191 INFO L218 hiAutomatonCegarLoop]: Abstraction has 776 states and 1156 transitions. [2023-11-12 02:09:31,217 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 776 states and 1156 transitions. [2023-11-12 02:09:31,285 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 776 to 776. [2023-11-12 02:09:31,288 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 776 states, 776 states have (on average 1.4896907216494846) internal successors, (1156), 775 states have internal predecessors, (1156), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-12 02:09:31,292 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 776 states to 776 states and 1156 transitions. [2023-11-12 02:09:31,293 INFO L240 hiAutomatonCegarLoop]: Abstraction has 776 states and 1156 transitions. [2023-11-12 02:09:31,294 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-12 02:09:31,299 INFO L428 stractBuchiCegarLoop]: Abstraction has 776 states and 1156 transitions. [2023-11-12 02:09:31,299 INFO L335 stractBuchiCegarLoop]: ======== Iteration 2 ============ [2023-11-12 02:09:31,299 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 776 states and 1156 transitions. [2023-11-12 02:09:31,305 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 675 [2023-11-12 02:09:31,305 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-12 02:09:31,306 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-12 02:09:31,309 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-12 02:09:31,309 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-12 02:09:31,310 INFO L748 eck$LassoCheckResult]: Stem: 1790#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2; 1791#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~9#1;havoc main_~__retres1~9#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 2318#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret22#1, start_simulation_#t~ret23#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 2319#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 2338#L521 assume 1 == ~m_i~0;~m_st~0 := 0; 2330#L521-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 2331#L526-1 assume !(1 == ~t2_i~0);~t2_st~0 := 2; 1939#L531-1 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 1940#L536-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 2009#L541-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 1853#L546-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 1854#L551-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 1820#L556-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 1821#L754 assume !(0 == ~M_E~0); 2346#L754-2 assume !(0 == ~T1_E~0); 2288#L759-1 assume !(0 == ~T2_E~0); 2170#L764-1 assume !(0 == ~T3_E~0); 2135#L769-1 assume !(0 == ~T4_E~0); 2136#L774-1 assume !(0 == ~T5_E~0); 2171#L779-1 assume 0 == ~T6_E~0;~T6_E~0 := 1; 2293#L784-1 assume !(0 == ~T7_E~0); 2132#L789-1 assume !(0 == ~E_1~0); 2133#L794-1 assume !(0 == ~E_2~0); 2207#L799-1 assume !(0 == ~E_3~0); 2143#L804-1 assume !(0 == ~E_4~0); 2144#L809-1 assume !(0 == ~E_5~0); 2165#L814-1 assume !(0 == ~E_6~0); 1591#L819-1 assume 0 == ~E_7~0;~E_7~0 := 1; 1592#L824-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1850#L361 assume 1 == ~m_pc~0; 1851#L362 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 2314#L372 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 2274#is_master_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 2275#L930 assume !(0 != activate_threads_~tmp~1#1); 2052#L930-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1844#L380 assume !(1 == ~t1_pc~0); 1845#L380-2 is_transmit1_triggered_~__retres1~1#1 := 0; 2213#L391 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1613#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 1614#L938 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 2233#L938-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 2214#L399 assume 1 == ~t2_pc~0; 2215#L400 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 1762#L410 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1922#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 1915#L946 assume !(0 != activate_threads_~tmp___1~0#1); 1916#L946-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1599#L418 assume !(1 == ~t3_pc~0); 1578#L418-2 is_transmit3_triggered_~__retres1~3#1 := 0; 1579#L429 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1589#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 1590#L954 assume !(0 != activate_threads_~tmp___2~0#1); 2155#L954-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 2156#L437 assume 1 == ~t4_pc~0; 2347#L438 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 2269#L448 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1672#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 1673#L962 assume !(0 != activate_threads_~tmp___3~0#1); 1968#L962-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 2251#L456 assume !(1 == ~t5_pc~0); 1776#L456-2 is_transmit5_triggered_~__retres1~5#1 := 0; 1775#L467 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 2278#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 2196#L970 assume !(0 != activate_threads_~tmp___4~0#1); 2197#L970-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1666#L475 assume 1 == ~t6_pc~0; 1667#L476 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 1708#L486 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1709#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1908#L978 assume !(0 != activate_threads_~tmp___5~0#1); 2148#L978-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 2149#L494 assume 1 == ~t7_pc~0; 2097#L495 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 1893#L505 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 2108#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 2172#L986 assume !(0 != activate_threads_~tmp___6~0#1); 2173#L986-2 havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 2343#L837 assume !(1 == ~M_E~0); 2317#L837-2 assume !(1 == ~T1_E~0); 2210#L842-1 assume !(1 == ~T2_E~0); 1975#L847-1 assume !(1 == ~T3_E~0); 1976#L852-1 assume !(1 == ~T4_E~0); 2042#L857-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 1928#L862-1 assume !(1 == ~T6_E~0); 1929#L867-1 assume !(1 == ~T7_E~0); 1935#L872-1 assume !(1 == ~E_1~0); 2008#L877-1 assume !(1 == ~E_2~0); 2185#L882-1 assume !(1 == ~E_3~0); 2322#L887-1 assume !(1 == ~E_4~0); 2229#L892-1 assume !(1 == ~E_5~0); 2230#L897-1 assume 1 == ~E_6~0;~E_6~0 := 2; 1951#L902-1 assume !(1 == ~E_7~0); 1952#L907-1 assume { :end_inline_reset_delta_events } true; 1819#L1148-2 [2023-11-12 02:09:31,310 INFO L750 eck$LassoCheckResult]: Loop: 1819#L1148-2 assume !false; 1593#L1149 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 1594#L729-1 assume !false; 2205#L622 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 1792#L569 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 1793#L611 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 1941#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 1837#L626 assume !(0 != eval_~tmp~0#1); 1838#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 2051#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 1866#L754-3 assume 0 == ~M_E~0;~M_E~0 := 1; 1605#L754-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 1606#L759-3 assume !(0 == ~T2_E~0); 1987#L764-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 1988#L769-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 2157#L774-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 1765#L779-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 1600#L784-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 1601#L789-3 assume 0 == ~E_1~0;~E_1~0 := 1; 1595#L794-3 assume 0 == ~E_2~0;~E_2~0 := 1; 1596#L799-3 assume !(0 == ~E_3~0); 1647#L804-3 assume 0 == ~E_4~0;~E_4~0 := 1; 1873#L809-3 assume 0 == ~E_5~0;~E_5~0 := 1; 1643#L814-3 assume 0 == ~E_6~0;~E_6~0 := 1; 1644#L819-3 assume 0 == ~E_7~0;~E_7~0 := 1; 2261#L824-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 2005#L361-24 assume 1 == ~m_pc~0; 1749#L362-8 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 1750#L372-8 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1695#is_master_triggered_returnLabel#9 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 1696#L930-24 assume !(0 != activate_threads_~tmp~1#1); 2306#L930-26 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 2140#L380-24 assume 1 == ~t1_pc~0; 2141#L381-8 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 1678#L391-8 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 2087#is_transmit1_triggered_returnLabel#9 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 1862#L938-24 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 1863#L938-26 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 2216#L399-24 assume !(1 == ~t2_pc~0); 1881#L399-26 is_transmit2_triggered_~__retres1~2#1 := 0; 1797#L410-8 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1798#is_transmit2_triggered_returnLabel#9 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 2041#L946-24 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 1859#L946-26 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1860#L418-24 assume 1 == ~t3_pc~0; 2305#L419-8 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 1642#L429-8 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1932#is_transmit3_triggered_returnLabel#9 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 1768#L954-24 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 1769#L954-26 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 2199#L437-24 assume 1 == ~t4_pc~0; 2265#L438-8 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 2267#L448-8 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 2040#is_transmit4_triggered_returnLabel#9 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 1752#L962-24 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 1753#L962-26 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 2147#L456-24 assume 1 == ~t5_pc~0; 2121#L457-8 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 2101#L467-8 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 2102#is_transmit5_triggered_returnLabel#9 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 2300#L970-24 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 2053#L970-26 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 2054#L475-24 assume 1 == ~t6_pc~0; 1602#L476-8 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 1603#L486-8 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1745#is_transmit6_triggered_returnLabel#9 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1746#L978-24 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 1584#L978-26 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1585#L494-24 assume 1 == ~t7_pc~0; 2024#L495-8 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 1913#L505-8 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1914#is_transmit7_triggered_returnLabel#9 activate_threads_#t~ret20#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1856#L986-24 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 1857#L986-26 havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 2264#L837-3 assume 1 == ~M_E~0;~M_E~0 := 2; 2291#L837-5 assume !(1 == ~T1_E~0); 2048#L842-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 2049#L847-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 2195#L852-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 2105#L857-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 2106#L862-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 2348#L867-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 2022#L872-3 assume 1 == ~E_1~0;~E_1~0 := 2; 2023#L877-3 assume !(1 == ~E_2~0); 2100#L882-3 assume 1 == ~E_3~0;~E_3~0 := 2; 2151#L887-3 assume 1 == ~E_4~0;~E_4~0 := 2; 1784#L892-3 assume 1 == ~E_5~0;~E_5~0 := 2; 1785#L897-3 assume 1 == ~E_6~0;~E_6~0 := 2; 2290#L902-3 assume 1 == ~E_7~0;~E_7~0 := 2; 1945#L907-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 1946#L569-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 1598#L611-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 1882#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret22#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret22#1;havoc start_simulation_#t~ret22#1; 1883#L1167 assume !(0 == start_simulation_~tmp~3#1); 2000#L1167-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret21#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 2001#L569-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 1806#L611-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 1611#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret21#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret21#1;havoc stop_simulation_#t~ret21#1; 1612#L1122 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 1982#L1129 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 1983#stop_simulation_returnLabel#1 start_simulation_#t~ret23#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret21#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret23#1;havoc start_simulation_#t~ret23#1; 1818#L1180 assume !(0 != start_simulation_~tmp___0~1#1); 1819#L1148-2 [2023-11-12 02:09:31,312 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-12 02:09:31,312 INFO L85 PathProgramCache]: Analyzing trace with hash 598794861, now seen corresponding path program 1 times [2023-11-12 02:09:31,312 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-12 02:09:31,312 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [183440072] [2023-11-12 02:09:31,313 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-12 02:09:31,313 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-12 02:09:31,347 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-12 02:09:31,474 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-12 02:09:31,474 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-12 02:09:31,474 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [183440072] [2023-11-12 02:09:31,475 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [183440072] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-12 02:09:31,475 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-12 02:09:31,479 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-12 02:09:31,479 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1968559427] [2023-11-12 02:09:31,479 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-12 02:09:31,480 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-12 02:09:31,480 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-12 02:09:31,481 INFO L85 PathProgramCache]: Analyzing trace with hash -716299096, now seen corresponding path program 1 times [2023-11-12 02:09:31,481 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-12 02:09:31,481 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1832472240] [2023-11-12 02:09:31,481 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-12 02:09:31,482 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-12 02:09:31,512 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-12 02:09:31,582 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-12 02:09:31,582 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-12 02:09:31,583 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1832472240] [2023-11-12 02:09:31,583 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1832472240] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-12 02:09:31,583 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-12 02:09:31,583 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-12 02:09:31,584 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1265013091] [2023-11-12 02:09:31,584 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-12 02:09:31,584 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-12 02:09:31,585 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-12 02:09:31,585 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-12 02:09:31,585 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-12 02:09:31,586 INFO L87 Difference]: Start difference. First operand 776 states and 1156 transitions. cyclomatic complexity: 381 Second operand has 3 states, 3 states have (on average 31.0) internal successors, (93), 3 states have internal predecessors, (93), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-12 02:09:31,614 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-12 02:09:31,614 INFO L93 Difference]: Finished difference Result 776 states and 1155 transitions. [2023-11-12 02:09:31,614 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 776 states and 1155 transitions. [2023-11-12 02:09:31,625 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 675 [2023-11-12 02:09:31,633 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 776 states to 776 states and 1155 transitions. [2023-11-12 02:09:31,634 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 776 [2023-11-12 02:09:31,635 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 776 [2023-11-12 02:09:31,635 INFO L73 IsDeterministic]: Start isDeterministic. Operand 776 states and 1155 transitions. [2023-11-12 02:09:31,637 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-12 02:09:31,637 INFO L218 hiAutomatonCegarLoop]: Abstraction has 776 states and 1155 transitions. [2023-11-12 02:09:31,639 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 776 states and 1155 transitions. [2023-11-12 02:09:31,656 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 776 to 776. [2023-11-12 02:09:31,658 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 776 states, 776 states have (on average 1.4884020618556701) internal successors, (1155), 775 states have internal predecessors, (1155), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-12 02:09:31,662 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 776 states to 776 states and 1155 transitions. [2023-11-12 02:09:31,663 INFO L240 hiAutomatonCegarLoop]: Abstraction has 776 states and 1155 transitions. [2023-11-12 02:09:31,663 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-12 02:09:31,664 INFO L428 stractBuchiCegarLoop]: Abstraction has 776 states and 1155 transitions. [2023-11-12 02:09:31,664 INFO L335 stractBuchiCegarLoop]: ======== Iteration 3 ============ [2023-11-12 02:09:31,665 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 776 states and 1155 transitions. [2023-11-12 02:09:31,671 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 675 [2023-11-12 02:09:31,671 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-12 02:09:31,671 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-12 02:09:31,674 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-12 02:09:31,675 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-12 02:09:31,675 INFO L748 eck$LassoCheckResult]: Stem: 3349#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2; 3350#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~9#1;havoc main_~__retres1~9#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 3877#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret22#1, start_simulation_#t~ret23#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 3878#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 3897#L521 assume 1 == ~m_i~0;~m_st~0 := 0; 3889#L521-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 3890#L526-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 3498#L531-1 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 3499#L536-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 3568#L541-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 3412#L546-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 3413#L551-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 3379#L556-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 3380#L754 assume !(0 == ~M_E~0); 3905#L754-2 assume !(0 == ~T1_E~0); 3847#L759-1 assume !(0 == ~T2_E~0); 3729#L764-1 assume !(0 == ~T3_E~0); 3694#L769-1 assume !(0 == ~T4_E~0); 3695#L774-1 assume !(0 == ~T5_E~0); 3730#L779-1 assume 0 == ~T6_E~0;~T6_E~0 := 1; 3852#L784-1 assume !(0 == ~T7_E~0); 3691#L789-1 assume !(0 == ~E_1~0); 3692#L794-1 assume !(0 == ~E_2~0); 3766#L799-1 assume !(0 == ~E_3~0); 3702#L804-1 assume !(0 == ~E_4~0); 3703#L809-1 assume !(0 == ~E_5~0); 3724#L814-1 assume !(0 == ~E_6~0); 3150#L819-1 assume 0 == ~E_7~0;~E_7~0 := 1; 3151#L824-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 3409#L361 assume 1 == ~m_pc~0; 3410#L362 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 3873#L372 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 3833#is_master_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 3834#L930 assume !(0 != activate_threads_~tmp~1#1); 3611#L930-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 3403#L380 assume !(1 == ~t1_pc~0); 3404#L380-2 is_transmit1_triggered_~__retres1~1#1 := 0; 3772#L391 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 3172#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 3173#L938 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 3792#L938-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 3773#L399 assume 1 == ~t2_pc~0; 3774#L400 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 3321#L410 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 3481#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 3474#L946 assume !(0 != activate_threads_~tmp___1~0#1); 3475#L946-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 3158#L418 assume !(1 == ~t3_pc~0); 3137#L418-2 is_transmit3_triggered_~__retres1~3#1 := 0; 3138#L429 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 3148#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 3149#L954 assume !(0 != activate_threads_~tmp___2~0#1); 3714#L954-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 3715#L437 assume 1 == ~t4_pc~0; 3906#L438 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 3828#L448 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 3231#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 3232#L962 assume !(0 != activate_threads_~tmp___3~0#1); 3527#L962-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 3810#L456 assume !(1 == ~t5_pc~0); 3335#L456-2 is_transmit5_triggered_~__retres1~5#1 := 0; 3334#L467 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 3837#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 3755#L970 assume !(0 != activate_threads_~tmp___4~0#1); 3756#L970-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 3225#L475 assume 1 == ~t6_pc~0; 3226#L476 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 3267#L486 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 3268#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 3467#L978 assume !(0 != activate_threads_~tmp___5~0#1); 3707#L978-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 3708#L494 assume 1 == ~t7_pc~0; 3656#L495 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 3452#L505 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 3667#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 3731#L986 assume !(0 != activate_threads_~tmp___6~0#1); 3732#L986-2 havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 3902#L837 assume !(1 == ~M_E~0); 3876#L837-2 assume !(1 == ~T1_E~0); 3769#L842-1 assume !(1 == ~T2_E~0); 3534#L847-1 assume !(1 == ~T3_E~0); 3535#L852-1 assume !(1 == ~T4_E~0); 3601#L857-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 3487#L862-1 assume !(1 == ~T6_E~0); 3488#L867-1 assume !(1 == ~T7_E~0); 3494#L872-1 assume !(1 == ~E_1~0); 3567#L877-1 assume !(1 == ~E_2~0); 3744#L882-1 assume !(1 == ~E_3~0); 3881#L887-1 assume !(1 == ~E_4~0); 3788#L892-1 assume !(1 == ~E_5~0); 3789#L897-1 assume 1 == ~E_6~0;~E_6~0 := 2; 3510#L902-1 assume !(1 == ~E_7~0); 3511#L907-1 assume { :end_inline_reset_delta_events } true; 3378#L1148-2 [2023-11-12 02:09:31,676 INFO L750 eck$LassoCheckResult]: Loop: 3378#L1148-2 assume !false; 3152#L1149 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 3153#L729-1 assume !false; 3764#L622 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 3351#L569 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 3352#L611 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 3500#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 3396#L626 assume !(0 != eval_~tmp~0#1); 3397#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 3610#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 3425#L754-3 assume 0 == ~M_E~0;~M_E~0 := 1; 3164#L754-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 3165#L759-3 assume !(0 == ~T2_E~0); 3546#L764-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 3547#L769-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 3716#L774-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 3324#L779-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 3159#L784-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 3160#L789-3 assume 0 == ~E_1~0;~E_1~0 := 1; 3154#L794-3 assume 0 == ~E_2~0;~E_2~0 := 1; 3155#L799-3 assume !(0 == ~E_3~0); 3206#L804-3 assume 0 == ~E_4~0;~E_4~0 := 1; 3432#L809-3 assume 0 == ~E_5~0;~E_5~0 := 1; 3202#L814-3 assume 0 == ~E_6~0;~E_6~0 := 1; 3203#L819-3 assume 0 == ~E_7~0;~E_7~0 := 1; 3820#L824-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 3564#L361-24 assume 1 == ~m_pc~0; 3308#L362-8 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 3309#L372-8 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 3254#is_master_triggered_returnLabel#9 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 3255#L930-24 assume !(0 != activate_threads_~tmp~1#1); 3865#L930-26 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 3699#L380-24 assume 1 == ~t1_pc~0; 3700#L381-8 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 3237#L391-8 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 3646#is_transmit1_triggered_returnLabel#9 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 3421#L938-24 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 3422#L938-26 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 3775#L399-24 assume !(1 == ~t2_pc~0); 3440#L399-26 is_transmit2_triggered_~__retres1~2#1 := 0; 3356#L410-8 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 3357#is_transmit2_triggered_returnLabel#9 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 3600#L946-24 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 3418#L946-26 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 3419#L418-24 assume !(1 == ~t3_pc~0); 3200#L418-26 is_transmit3_triggered_~__retres1~3#1 := 0; 3201#L429-8 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 3491#is_transmit3_triggered_returnLabel#9 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 3327#L954-24 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 3328#L954-26 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 3758#L437-24 assume 1 == ~t4_pc~0; 3824#L438-8 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 3826#L448-8 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 3599#is_transmit4_triggered_returnLabel#9 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 3311#L962-24 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 3312#L962-26 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 3706#L456-24 assume 1 == ~t5_pc~0; 3680#L457-8 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 3660#L467-8 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 3661#is_transmit5_triggered_returnLabel#9 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 3859#L970-24 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 3612#L970-26 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 3613#L475-24 assume 1 == ~t6_pc~0; 3161#L476-8 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 3162#L486-8 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 3304#is_transmit6_triggered_returnLabel#9 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 3305#L978-24 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 3143#L978-26 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 3144#L494-24 assume !(1 == ~t7_pc~0); 3492#L494-26 is_transmit7_triggered_~__retres1~7#1 := 0; 3472#L505-8 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 3473#is_transmit7_triggered_returnLabel#9 activate_threads_#t~ret20#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 3415#L986-24 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 3416#L986-26 havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 3823#L837-3 assume 1 == ~M_E~0;~M_E~0 := 2; 3850#L837-5 assume !(1 == ~T1_E~0); 3607#L842-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 3608#L847-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 3754#L852-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 3664#L857-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 3665#L862-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 3907#L867-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 3581#L872-3 assume 1 == ~E_1~0;~E_1~0 := 2; 3582#L877-3 assume !(1 == ~E_2~0); 3659#L882-3 assume 1 == ~E_3~0;~E_3~0 := 2; 3710#L887-3 assume 1 == ~E_4~0;~E_4~0 := 2; 3343#L892-3 assume 1 == ~E_5~0;~E_5~0 := 2; 3344#L897-3 assume 1 == ~E_6~0;~E_6~0 := 2; 3849#L902-3 assume 1 == ~E_7~0;~E_7~0 := 2; 3504#L907-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 3505#L569-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 3157#L611-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 3441#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret22#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret22#1;havoc start_simulation_#t~ret22#1; 3442#L1167 assume !(0 == start_simulation_~tmp~3#1); 3559#L1167-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret21#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 3560#L569-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 3365#L611-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 3170#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret21#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret21#1;havoc stop_simulation_#t~ret21#1; 3171#L1122 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 3541#L1129 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 3542#stop_simulation_returnLabel#1 start_simulation_#t~ret23#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret21#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret23#1;havoc start_simulation_#t~ret23#1; 3377#L1180 assume !(0 != start_simulation_~tmp___0~1#1); 3378#L1148-2 [2023-11-12 02:09:31,677 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-12 02:09:31,677 INFO L85 PathProgramCache]: Analyzing trace with hash 1185071083, now seen corresponding path program 1 times [2023-11-12 02:09:31,677 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-12 02:09:31,677 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1045691799] [2023-11-12 02:09:31,677 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-12 02:09:31,678 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-12 02:09:31,695 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-12 02:09:31,733 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-12 02:09:31,733 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-12 02:09:31,733 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1045691799] [2023-11-12 02:09:31,734 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1045691799] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-12 02:09:31,734 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-12 02:09:31,734 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-12 02:09:31,734 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1145171233] [2023-11-12 02:09:31,735 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-12 02:09:31,735 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-12 02:09:31,736 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-12 02:09:31,736 INFO L85 PathProgramCache]: Analyzing trace with hash 808370534, now seen corresponding path program 1 times [2023-11-12 02:09:31,736 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-12 02:09:31,737 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1931518189] [2023-11-12 02:09:31,737 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-12 02:09:31,737 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-12 02:09:31,756 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-12 02:09:31,861 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-12 02:09:31,866 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-12 02:09:31,866 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1931518189] [2023-11-12 02:09:31,867 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1931518189] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-12 02:09:31,867 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-12 02:09:31,867 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-12 02:09:31,867 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [937500703] [2023-11-12 02:09:31,867 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-12 02:09:31,868 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-12 02:09:31,868 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-12 02:09:31,869 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-12 02:09:31,869 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-12 02:09:31,869 INFO L87 Difference]: Start difference. First operand 776 states and 1155 transitions. cyclomatic complexity: 380 Second operand has 3 states, 3 states have (on average 31.0) internal successors, (93), 3 states have internal predecessors, (93), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-12 02:09:31,916 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-12 02:09:31,917 INFO L93 Difference]: Finished difference Result 776 states and 1154 transitions. [2023-11-12 02:09:31,917 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 776 states and 1154 transitions. [2023-11-12 02:09:31,925 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 675 [2023-11-12 02:09:31,932 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 776 states to 776 states and 1154 transitions. [2023-11-12 02:09:31,933 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 776 [2023-11-12 02:09:31,934 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 776 [2023-11-12 02:09:31,934 INFO L73 IsDeterministic]: Start isDeterministic. Operand 776 states and 1154 transitions. [2023-11-12 02:09:31,936 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-12 02:09:31,936 INFO L218 hiAutomatonCegarLoop]: Abstraction has 776 states and 1154 transitions. [2023-11-12 02:09:31,938 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 776 states and 1154 transitions. [2023-11-12 02:09:31,951 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 776 to 776. [2023-11-12 02:09:31,953 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 776 states, 776 states have (on average 1.4871134020618557) internal successors, (1154), 775 states have internal predecessors, (1154), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-12 02:09:31,957 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 776 states to 776 states and 1154 transitions. [2023-11-12 02:09:31,957 INFO L240 hiAutomatonCegarLoop]: Abstraction has 776 states and 1154 transitions. [2023-11-12 02:09:31,958 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-12 02:09:31,959 INFO L428 stractBuchiCegarLoop]: Abstraction has 776 states and 1154 transitions. [2023-11-12 02:09:31,959 INFO L335 stractBuchiCegarLoop]: ======== Iteration 4 ============ [2023-11-12 02:09:31,960 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 776 states and 1154 transitions. [2023-11-12 02:09:31,966 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 675 [2023-11-12 02:09:31,966 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-12 02:09:31,967 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-12 02:09:31,969 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-12 02:09:31,969 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-12 02:09:31,970 INFO L748 eck$LassoCheckResult]: Stem: 4908#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2; 4909#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~9#1;havoc main_~__retres1~9#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 5436#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret22#1, start_simulation_#t~ret23#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 5437#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 5456#L521 assume 1 == ~m_i~0;~m_st~0 := 0; 5448#L521-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 5449#L526-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 5057#L531-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 5058#L536-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 5127#L541-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 4971#L546-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 4972#L551-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 4938#L556-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 4939#L754 assume !(0 == ~M_E~0); 5464#L754-2 assume !(0 == ~T1_E~0); 5406#L759-1 assume !(0 == ~T2_E~0); 5288#L764-1 assume !(0 == ~T3_E~0); 5254#L769-1 assume !(0 == ~T4_E~0); 5255#L774-1 assume !(0 == ~T5_E~0); 5289#L779-1 assume 0 == ~T6_E~0;~T6_E~0 := 1; 5411#L784-1 assume !(0 == ~T7_E~0); 5251#L789-1 assume !(0 == ~E_1~0); 5252#L794-1 assume !(0 == ~E_2~0); 5325#L799-1 assume !(0 == ~E_3~0); 5261#L804-1 assume !(0 == ~E_4~0); 5262#L809-1 assume !(0 == ~E_5~0); 5283#L814-1 assume !(0 == ~E_6~0); 4711#L819-1 assume 0 == ~E_7~0;~E_7~0 := 1; 4712#L824-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 4968#L361 assume 1 == ~m_pc~0; 4969#L362 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 5432#L372 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 5392#is_master_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 5393#L930 assume !(0 != activate_threads_~tmp~1#1); 5170#L930-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 4962#L380 assume !(1 == ~t1_pc~0); 4963#L380-2 is_transmit1_triggered_~__retres1~1#1 := 0; 5331#L391 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 4731#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 4732#L938 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 5351#L938-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 5332#L399 assume 1 == ~t2_pc~0; 5333#L400 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 4880#L410 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 5040#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 5033#L946 assume !(0 != activate_threads_~tmp___1~0#1); 5034#L946-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 4717#L418 assume !(1 == ~t3_pc~0); 4696#L418-2 is_transmit3_triggered_~__retres1~3#1 := 0; 4697#L429 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 4707#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 4708#L954 assume !(0 != activate_threads_~tmp___2~0#1); 5273#L954-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 5274#L437 assume 1 == ~t4_pc~0; 5465#L438 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 5388#L448 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 4791#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 4792#L962 assume !(0 != activate_threads_~tmp___3~0#1); 5086#L962-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 5374#L456 assume !(1 == ~t5_pc~0); 4894#L456-2 is_transmit5_triggered_~__retres1~5#1 := 0; 4893#L467 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 5396#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 5315#L970 assume !(0 != activate_threads_~tmp___4~0#1); 5316#L970-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 4784#L475 assume 1 == ~t6_pc~0; 4785#L476 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 4826#L486 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 4827#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 5026#L978 assume !(0 != activate_threads_~tmp___5~0#1); 5266#L978-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 5267#L494 assume 1 == ~t7_pc~0; 5215#L495 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 5011#L505 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 5226#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 5290#L986 assume !(0 != activate_threads_~tmp___6~0#1); 5291#L986-2 havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 5461#L837 assume !(1 == ~M_E~0); 5435#L837-2 assume !(1 == ~T1_E~0); 5328#L842-1 assume !(1 == ~T2_E~0); 5093#L847-1 assume !(1 == ~T3_E~0); 5094#L852-1 assume !(1 == ~T4_E~0); 5160#L857-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 5046#L862-1 assume !(1 == ~T6_E~0); 5047#L867-1 assume !(1 == ~T7_E~0); 5053#L872-1 assume !(1 == ~E_1~0); 5126#L877-1 assume !(1 == ~E_2~0); 5304#L882-1 assume !(1 == ~E_3~0); 5440#L887-1 assume !(1 == ~E_4~0); 5347#L892-1 assume !(1 == ~E_5~0); 5348#L897-1 assume 1 == ~E_6~0;~E_6~0 := 2; 5069#L902-1 assume !(1 == ~E_7~0); 5070#L907-1 assume { :end_inline_reset_delta_events } true; 4937#L1148-2 [2023-11-12 02:09:31,971 INFO L750 eck$LassoCheckResult]: Loop: 4937#L1148-2 assume !false; 4713#L1149 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 4714#L729-1 assume !false; 5323#L622 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 4910#L569 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 4911#L611 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 5064#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 4957#L626 assume !(0 != eval_~tmp~0#1); 4958#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 5169#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 4984#L754-3 assume 0 == ~M_E~0;~M_E~0 := 1; 4723#L754-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 4724#L759-3 assume !(0 == ~T2_E~0); 5106#L764-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 5107#L769-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 5275#L774-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 4883#L779-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 4718#L784-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 4719#L789-3 assume 0 == ~E_1~0;~E_1~0 := 1; 4709#L794-3 assume 0 == ~E_2~0;~E_2~0 := 1; 4710#L799-3 assume !(0 == ~E_3~0); 4765#L804-3 assume 0 == ~E_4~0;~E_4~0 := 1; 4991#L809-3 assume 0 == ~E_5~0;~E_5~0 := 1; 4761#L814-3 assume 0 == ~E_6~0;~E_6~0 := 1; 4762#L819-3 assume 0 == ~E_7~0;~E_7~0 := 1; 5379#L824-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 5123#L361-24 assume 1 == ~m_pc~0; 4867#L362-8 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 4868#L372-8 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 4813#is_master_triggered_returnLabel#9 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 4814#L930-24 assume !(0 != activate_threads_~tmp~1#1); 5424#L930-26 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 5258#L380-24 assume 1 == ~t1_pc~0; 5259#L381-8 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 4796#L391-8 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 5205#is_transmit1_triggered_returnLabel#9 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 4980#L938-24 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 4981#L938-26 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 5334#L399-24 assume !(1 == ~t2_pc~0); 4999#L399-26 is_transmit2_triggered_~__retres1~2#1 := 0; 4915#L410-8 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 4916#is_transmit2_triggered_returnLabel#9 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 5159#L946-24 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 4977#L946-26 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 4978#L418-24 assume !(1 == ~t3_pc~0); 4759#L418-26 is_transmit3_triggered_~__retres1~3#1 := 0; 4760#L429-8 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 5050#is_transmit3_triggered_returnLabel#9 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 4886#L954-24 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 4887#L954-26 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 5317#L437-24 assume 1 == ~t4_pc~0; 5383#L438-8 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 5385#L448-8 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 5158#is_transmit4_triggered_returnLabel#9 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 4870#L962-24 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 4871#L962-26 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 5265#L456-24 assume 1 == ~t5_pc~0; 5239#L457-8 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 5219#L467-8 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 5220#is_transmit5_triggered_returnLabel#9 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 5418#L970-24 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 5171#L970-26 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 5172#L475-24 assume 1 == ~t6_pc~0; 4720#L476-8 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 4721#L486-8 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 4863#is_transmit6_triggered_returnLabel#9 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 4864#L978-24 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 4702#L978-26 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 4703#L494-24 assume 1 == ~t7_pc~0; 5142#L495-8 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 5031#L505-8 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 5032#is_transmit7_triggered_returnLabel#9 activate_threads_#t~ret20#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 4974#L986-24 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 4975#L986-26 havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 5382#L837-3 assume 1 == ~M_E~0;~M_E~0 := 2; 5409#L837-5 assume !(1 == ~T1_E~0); 5166#L842-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 5167#L847-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 5313#L852-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 5223#L857-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 5224#L862-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 5466#L867-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 5137#L872-3 assume 1 == ~E_1~0;~E_1~0 := 2; 5138#L877-3 assume !(1 == ~E_2~0); 5218#L882-3 assume 1 == ~E_3~0;~E_3~0 := 2; 5269#L887-3 assume 1 == ~E_4~0;~E_4~0 := 2; 4902#L892-3 assume 1 == ~E_5~0;~E_5~0 := 2; 4903#L897-3 assume 1 == ~E_6~0;~E_6~0 := 2; 5408#L902-3 assume 1 == ~E_7~0;~E_7~0 := 2; 5062#L907-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 5063#L569-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 4716#L611-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 5000#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret22#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret22#1;havoc start_simulation_#t~ret22#1; 5001#L1167 assume !(0 == start_simulation_~tmp~3#1); 5118#L1167-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret21#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 5119#L569-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 4924#L611-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 4729#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret21#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret21#1;havoc stop_simulation_#t~ret21#1; 4730#L1122 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 5100#L1129 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 5101#stop_simulation_returnLabel#1 start_simulation_#t~ret23#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret21#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret23#1;havoc start_simulation_#t~ret23#1; 4936#L1180 assume !(0 != start_simulation_~tmp___0~1#1); 4937#L1148-2 [2023-11-12 02:09:31,972 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-12 02:09:31,972 INFO L85 PathProgramCache]: Analyzing trace with hash -1151321427, now seen corresponding path program 1 times [2023-11-12 02:09:31,972 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-12 02:09:31,973 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [507255285] [2023-11-12 02:09:31,973 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-12 02:09:31,973 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-12 02:09:31,989 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-12 02:09:32,021 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-12 02:09:32,021 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-12 02:09:32,022 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [507255285] [2023-11-12 02:09:32,022 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [507255285] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-12 02:09:32,022 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-12 02:09:32,022 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-12 02:09:32,023 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [432852648] [2023-11-12 02:09:32,023 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-12 02:09:32,023 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-12 02:09:32,024 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-12 02:09:32,024 INFO L85 PathProgramCache]: Analyzing trace with hash -1857946489, now seen corresponding path program 1 times [2023-11-12 02:09:32,024 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-12 02:09:32,025 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1999266586] [2023-11-12 02:09:32,025 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-12 02:09:32,025 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-12 02:09:32,045 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-12 02:09:32,089 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-12 02:09:32,089 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-12 02:09:32,090 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1999266586] [2023-11-12 02:09:32,090 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1999266586] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-12 02:09:32,090 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-12 02:09:32,090 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-12 02:09:32,091 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [198732698] [2023-11-12 02:09:32,091 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-12 02:09:32,091 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-12 02:09:32,092 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-12 02:09:32,092 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-12 02:09:32,092 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-12 02:09:32,093 INFO L87 Difference]: Start difference. First operand 776 states and 1154 transitions. cyclomatic complexity: 379 Second operand has 3 states, 3 states have (on average 31.0) internal successors, (93), 3 states have internal predecessors, (93), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-12 02:09:32,117 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-12 02:09:32,117 INFO L93 Difference]: Finished difference Result 776 states and 1153 transitions. [2023-11-12 02:09:32,117 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 776 states and 1153 transitions. [2023-11-12 02:09:32,126 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 675 [2023-11-12 02:09:32,134 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 776 states to 776 states and 1153 transitions. [2023-11-12 02:09:32,134 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 776 [2023-11-12 02:09:32,135 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 776 [2023-11-12 02:09:32,136 INFO L73 IsDeterministic]: Start isDeterministic. Operand 776 states and 1153 transitions. [2023-11-12 02:09:32,137 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-12 02:09:32,138 INFO L218 hiAutomatonCegarLoop]: Abstraction has 776 states and 1153 transitions. [2023-11-12 02:09:32,139 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 776 states and 1153 transitions. [2023-11-12 02:09:32,153 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 776 to 776. [2023-11-12 02:09:32,156 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 776 states, 776 states have (on average 1.4858247422680413) internal successors, (1153), 775 states have internal predecessors, (1153), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-12 02:09:32,160 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 776 states to 776 states and 1153 transitions. [2023-11-12 02:09:32,160 INFO L240 hiAutomatonCegarLoop]: Abstraction has 776 states and 1153 transitions. [2023-11-12 02:09:32,161 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-12 02:09:32,162 INFO L428 stractBuchiCegarLoop]: Abstraction has 776 states and 1153 transitions. [2023-11-12 02:09:32,162 INFO L335 stractBuchiCegarLoop]: ======== Iteration 5 ============ [2023-11-12 02:09:32,162 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 776 states and 1153 transitions. [2023-11-12 02:09:32,169 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 675 [2023-11-12 02:09:32,169 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-12 02:09:32,170 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-12 02:09:32,172 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-12 02:09:32,172 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-12 02:09:32,173 INFO L748 eck$LassoCheckResult]: Stem: 6467#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2; 6468#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~9#1;havoc main_~__retres1~9#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 6995#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret22#1, start_simulation_#t~ret23#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 6996#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 7015#L521 assume 1 == ~m_i~0;~m_st~0 := 0; 7007#L521-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 7008#L526-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 6616#L531-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 6617#L536-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 6686#L541-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 6530#L546-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 6531#L551-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 6497#L556-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 6498#L754 assume !(0 == ~M_E~0); 7023#L754-2 assume !(0 == ~T1_E~0); 6965#L759-1 assume !(0 == ~T2_E~0); 6847#L764-1 assume !(0 == ~T3_E~0); 6812#L769-1 assume !(0 == ~T4_E~0); 6813#L774-1 assume !(0 == ~T5_E~0); 6848#L779-1 assume 0 == ~T6_E~0;~T6_E~0 := 1; 6970#L784-1 assume !(0 == ~T7_E~0); 6809#L789-1 assume !(0 == ~E_1~0); 6810#L794-1 assume !(0 == ~E_2~0); 6884#L799-1 assume !(0 == ~E_3~0); 6820#L804-1 assume !(0 == ~E_4~0); 6821#L809-1 assume !(0 == ~E_5~0); 6842#L814-1 assume !(0 == ~E_6~0); 6268#L819-1 assume 0 == ~E_7~0;~E_7~0 := 1; 6269#L824-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 6527#L361 assume 1 == ~m_pc~0; 6528#L362 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 6991#L372 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 6951#is_master_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 6952#L930 assume !(0 != activate_threads_~tmp~1#1); 6729#L930-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 6521#L380 assume !(1 == ~t1_pc~0); 6522#L380-2 is_transmit1_triggered_~__retres1~1#1 := 0; 6890#L391 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 6290#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 6291#L938 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 6910#L938-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 6891#L399 assume 1 == ~t2_pc~0; 6892#L400 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 6439#L410 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 6599#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 6592#L946 assume !(0 != activate_threads_~tmp___1~0#1); 6593#L946-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 6276#L418 assume !(1 == ~t3_pc~0); 6255#L418-2 is_transmit3_triggered_~__retres1~3#1 := 0; 6256#L429 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 6266#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 6267#L954 assume !(0 != activate_threads_~tmp___2~0#1); 6832#L954-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 6833#L437 assume 1 == ~t4_pc~0; 7024#L438 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 6946#L448 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 6349#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 6350#L962 assume !(0 != activate_threads_~tmp___3~0#1); 6645#L962-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 6930#L456 assume !(1 == ~t5_pc~0); 6453#L456-2 is_transmit5_triggered_~__retres1~5#1 := 0; 6452#L467 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 6955#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 6874#L970 assume !(0 != activate_threads_~tmp___4~0#1); 6875#L970-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 6343#L475 assume 1 == ~t6_pc~0; 6344#L476 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 6385#L486 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 6386#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 6585#L978 assume !(0 != activate_threads_~tmp___5~0#1); 6825#L978-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 6826#L494 assume 1 == ~t7_pc~0; 6774#L495 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 6570#L505 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 6785#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 6849#L986 assume !(0 != activate_threads_~tmp___6~0#1); 6850#L986-2 havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 7020#L837 assume !(1 == ~M_E~0); 6994#L837-2 assume !(1 == ~T1_E~0); 6887#L842-1 assume !(1 == ~T2_E~0); 6652#L847-1 assume !(1 == ~T3_E~0); 6653#L852-1 assume !(1 == ~T4_E~0); 6719#L857-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 6605#L862-1 assume !(1 == ~T6_E~0); 6606#L867-1 assume !(1 == ~T7_E~0); 6612#L872-1 assume !(1 == ~E_1~0); 6685#L877-1 assume !(1 == ~E_2~0); 6862#L882-1 assume !(1 == ~E_3~0); 6999#L887-1 assume !(1 == ~E_4~0); 6906#L892-1 assume !(1 == ~E_5~0); 6907#L897-1 assume 1 == ~E_6~0;~E_6~0 := 2; 6628#L902-1 assume !(1 == ~E_7~0); 6629#L907-1 assume { :end_inline_reset_delta_events } true; 6496#L1148-2 [2023-11-12 02:09:32,174 INFO L750 eck$LassoCheckResult]: Loop: 6496#L1148-2 assume !false; 6270#L1149 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 6271#L729-1 assume !false; 6882#L622 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 6469#L569 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 6470#L611 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 6620#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 6514#L626 assume !(0 != eval_~tmp~0#1); 6515#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 6728#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 6543#L754-3 assume 0 == ~M_E~0;~M_E~0 := 1; 6282#L754-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 6283#L759-3 assume !(0 == ~T2_E~0); 6664#L764-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 6665#L769-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 6834#L774-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 6442#L779-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 6277#L784-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 6278#L789-3 assume 0 == ~E_1~0;~E_1~0 := 1; 6272#L794-3 assume 0 == ~E_2~0;~E_2~0 := 1; 6273#L799-3 assume !(0 == ~E_3~0); 6324#L804-3 assume 0 == ~E_4~0;~E_4~0 := 1; 6550#L809-3 assume 0 == ~E_5~0;~E_5~0 := 1; 6320#L814-3 assume 0 == ~E_6~0;~E_6~0 := 1; 6321#L819-3 assume 0 == ~E_7~0;~E_7~0 := 1; 6938#L824-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 6682#L361-24 assume 1 == ~m_pc~0; 6426#L362-8 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 6427#L372-8 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 6372#is_master_triggered_returnLabel#9 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 6373#L930-24 assume !(0 != activate_threads_~tmp~1#1); 6983#L930-26 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 6817#L380-24 assume 1 == ~t1_pc~0; 6818#L381-8 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 6355#L391-8 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 6764#is_transmit1_triggered_returnLabel#9 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 6539#L938-24 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 6540#L938-26 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 6893#L399-24 assume !(1 == ~t2_pc~0); 6558#L399-26 is_transmit2_triggered_~__retres1~2#1 := 0; 6474#L410-8 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 6475#is_transmit2_triggered_returnLabel#9 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 6718#L946-24 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 6536#L946-26 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 6537#L418-24 assume 1 == ~t3_pc~0; 6982#L419-8 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 6319#L429-8 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 6609#is_transmit3_triggered_returnLabel#9 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 6445#L954-24 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 6446#L954-26 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 6876#L437-24 assume 1 == ~t4_pc~0; 6942#L438-8 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 6944#L448-8 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 6717#is_transmit4_triggered_returnLabel#9 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 6429#L962-24 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 6430#L962-26 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 6824#L456-24 assume 1 == ~t5_pc~0; 6798#L457-8 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 6778#L467-8 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 6779#is_transmit5_triggered_returnLabel#9 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 6977#L970-24 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 6730#L970-26 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 6731#L475-24 assume 1 == ~t6_pc~0; 6279#L476-8 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 6280#L486-8 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 6422#is_transmit6_triggered_returnLabel#9 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 6423#L978-24 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 6261#L978-26 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 6262#L494-24 assume !(1 == ~t7_pc~0); 6610#L494-26 is_transmit7_triggered_~__retres1~7#1 := 0; 6590#L505-8 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 6591#is_transmit7_triggered_returnLabel#9 activate_threads_#t~ret20#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 6533#L986-24 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 6534#L986-26 havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 6941#L837-3 assume 1 == ~M_E~0;~M_E~0 := 2; 6968#L837-5 assume !(1 == ~T1_E~0); 6725#L842-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 6726#L847-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 6872#L852-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 6782#L857-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 6783#L862-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 7025#L867-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 6696#L872-3 assume 1 == ~E_1~0;~E_1~0 := 2; 6697#L877-3 assume !(1 == ~E_2~0); 6777#L882-3 assume 1 == ~E_3~0;~E_3~0 := 2; 6828#L887-3 assume 1 == ~E_4~0;~E_4~0 := 2; 6461#L892-3 assume 1 == ~E_5~0;~E_5~0 := 2; 6462#L897-3 assume 1 == ~E_6~0;~E_6~0 := 2; 6967#L902-3 assume 1 == ~E_7~0;~E_7~0 := 2; 6618#L907-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 6619#L569-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 6275#L611-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 6559#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret22#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret22#1;havoc start_simulation_#t~ret22#1; 6560#L1167 assume !(0 == start_simulation_~tmp~3#1); 6677#L1167-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret21#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 6678#L569-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 6480#L611-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 6288#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret21#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret21#1;havoc stop_simulation_#t~ret21#1; 6289#L1122 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 6659#L1129 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 6660#stop_simulation_returnLabel#1 start_simulation_#t~ret23#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret21#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret23#1;havoc start_simulation_#t~ret23#1; 6495#L1180 assume !(0 != start_simulation_~tmp___0~1#1); 6496#L1148-2 [2023-11-12 02:09:32,175 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-12 02:09:32,175 INFO L85 PathProgramCache]: Analyzing trace with hash 1267163051, now seen corresponding path program 1 times [2023-11-12 02:09:32,175 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-12 02:09:32,176 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [817104026] [2023-11-12 02:09:32,176 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-12 02:09:32,176 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-12 02:09:32,189 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-12 02:09:32,218 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-12 02:09:32,219 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-12 02:09:32,219 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [817104026] [2023-11-12 02:09:32,219 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [817104026] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-12 02:09:32,220 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-12 02:09:32,220 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-12 02:09:32,220 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1759146810] [2023-11-12 02:09:32,220 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-12 02:09:32,221 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-12 02:09:32,221 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-12 02:09:32,222 INFO L85 PathProgramCache]: Analyzing trace with hash 1950017927, now seen corresponding path program 1 times [2023-11-12 02:09:32,233 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-12 02:09:32,233 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2137923238] [2023-11-12 02:09:32,233 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-12 02:09:32,233 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-12 02:09:32,252 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-12 02:09:32,324 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-12 02:09:32,324 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-12 02:09:32,325 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2137923238] [2023-11-12 02:09:32,325 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2137923238] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-12 02:09:32,325 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-12 02:09:32,325 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-12 02:09:32,326 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1227240860] [2023-11-12 02:09:32,326 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-12 02:09:32,326 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-12 02:09:32,326 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-12 02:09:32,327 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-12 02:09:32,327 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-12 02:09:32,328 INFO L87 Difference]: Start difference. First operand 776 states and 1153 transitions. cyclomatic complexity: 378 Second operand has 3 states, 3 states have (on average 31.0) internal successors, (93), 3 states have internal predecessors, (93), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-12 02:09:32,358 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-12 02:09:32,358 INFO L93 Difference]: Finished difference Result 776 states and 1152 transitions. [2023-11-12 02:09:32,360 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 776 states and 1152 transitions. [2023-11-12 02:09:32,402 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 675 [2023-11-12 02:09:32,412 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 776 states to 776 states and 1152 transitions. [2023-11-12 02:09:32,413 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 776 [2023-11-12 02:09:32,414 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 776 [2023-11-12 02:09:32,414 INFO L73 IsDeterministic]: Start isDeterministic. Operand 776 states and 1152 transitions. [2023-11-12 02:09:32,416 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-12 02:09:32,416 INFO L218 hiAutomatonCegarLoop]: Abstraction has 776 states and 1152 transitions. [2023-11-12 02:09:32,418 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 776 states and 1152 transitions. [2023-11-12 02:09:32,434 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 776 to 776. [2023-11-12 02:09:32,437 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 776 states, 776 states have (on average 1.4845360824742269) internal successors, (1152), 775 states have internal predecessors, (1152), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-12 02:09:32,441 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 776 states to 776 states and 1152 transitions. [2023-11-12 02:09:32,442 INFO L240 hiAutomatonCegarLoop]: Abstraction has 776 states and 1152 transitions. [2023-11-12 02:09:32,442 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-12 02:09:32,445 INFO L428 stractBuchiCegarLoop]: Abstraction has 776 states and 1152 transitions. [2023-11-12 02:09:32,446 INFO L335 stractBuchiCegarLoop]: ======== Iteration 6 ============ [2023-11-12 02:09:32,446 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 776 states and 1152 transitions. [2023-11-12 02:09:32,454 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 675 [2023-11-12 02:09:32,454 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-12 02:09:32,454 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-12 02:09:32,456 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-12 02:09:32,457 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-12 02:09:32,458 INFO L748 eck$LassoCheckResult]: Stem: 8026#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2; 8027#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~9#1;havoc main_~__retres1~9#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 8554#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret22#1, start_simulation_#t~ret23#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 8555#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 8574#L521 assume 1 == ~m_i~0;~m_st~0 := 0; 8566#L521-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 8567#L526-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 8175#L531-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 8176#L536-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 8245#L541-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 8089#L546-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 8090#L551-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 8056#L556-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 8057#L754 assume !(0 == ~M_E~0); 8582#L754-2 assume !(0 == ~T1_E~0); 8524#L759-1 assume !(0 == ~T2_E~0); 8406#L764-1 assume !(0 == ~T3_E~0); 8371#L769-1 assume !(0 == ~T4_E~0); 8372#L774-1 assume !(0 == ~T5_E~0); 8407#L779-1 assume 0 == ~T6_E~0;~T6_E~0 := 1; 8529#L784-1 assume !(0 == ~T7_E~0); 8368#L789-1 assume !(0 == ~E_1~0); 8369#L794-1 assume !(0 == ~E_2~0); 8443#L799-1 assume !(0 == ~E_3~0); 8379#L804-1 assume !(0 == ~E_4~0); 8380#L809-1 assume !(0 == ~E_5~0); 8401#L814-1 assume !(0 == ~E_6~0); 7827#L819-1 assume 0 == ~E_7~0;~E_7~0 := 1; 7828#L824-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 8086#L361 assume 1 == ~m_pc~0; 8087#L362 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 8550#L372 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 8510#is_master_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 8511#L930 assume !(0 != activate_threads_~tmp~1#1); 8288#L930-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 8080#L380 assume !(1 == ~t1_pc~0); 8081#L380-2 is_transmit1_triggered_~__retres1~1#1 := 0; 8449#L391 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 7849#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 7850#L938 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 8469#L938-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 8450#L399 assume 1 == ~t2_pc~0; 8451#L400 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 7998#L410 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 8158#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 8151#L946 assume !(0 != activate_threads_~tmp___1~0#1); 8152#L946-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 7835#L418 assume !(1 == ~t3_pc~0); 7814#L418-2 is_transmit3_triggered_~__retres1~3#1 := 0; 7815#L429 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 7825#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 7826#L954 assume !(0 != activate_threads_~tmp___2~0#1); 8391#L954-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 8392#L437 assume 1 == ~t4_pc~0; 8583#L438 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 8505#L448 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 7908#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 7909#L962 assume !(0 != activate_threads_~tmp___3~0#1); 8204#L962-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 8487#L456 assume !(1 == ~t5_pc~0); 8012#L456-2 is_transmit5_triggered_~__retres1~5#1 := 0; 8011#L467 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 8514#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 8432#L970 assume !(0 != activate_threads_~tmp___4~0#1); 8433#L970-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 7902#L475 assume 1 == ~t6_pc~0; 7903#L476 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 7944#L486 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 7945#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 8144#L978 assume !(0 != activate_threads_~tmp___5~0#1); 8384#L978-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 8385#L494 assume 1 == ~t7_pc~0; 8333#L495 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 8129#L505 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 8344#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 8408#L986 assume !(0 != activate_threads_~tmp___6~0#1); 8409#L986-2 havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 8579#L837 assume !(1 == ~M_E~0); 8553#L837-2 assume !(1 == ~T1_E~0); 8446#L842-1 assume !(1 == ~T2_E~0); 8211#L847-1 assume !(1 == ~T3_E~0); 8212#L852-1 assume !(1 == ~T4_E~0); 8278#L857-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 8164#L862-1 assume !(1 == ~T6_E~0); 8165#L867-1 assume !(1 == ~T7_E~0); 8171#L872-1 assume !(1 == ~E_1~0); 8244#L877-1 assume !(1 == ~E_2~0); 8421#L882-1 assume !(1 == ~E_3~0); 8558#L887-1 assume !(1 == ~E_4~0); 8465#L892-1 assume !(1 == ~E_5~0); 8466#L897-1 assume 1 == ~E_6~0;~E_6~0 := 2; 8187#L902-1 assume !(1 == ~E_7~0); 8188#L907-1 assume { :end_inline_reset_delta_events } true; 8055#L1148-2 [2023-11-12 02:09:32,459 INFO L750 eck$LassoCheckResult]: Loop: 8055#L1148-2 assume !false; 7829#L1149 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 7830#L729-1 assume !false; 8441#L622 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 8028#L569 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 8029#L611 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 8177#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 8073#L626 assume !(0 != eval_~tmp~0#1); 8074#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 8287#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 8102#L754-3 assume 0 == ~M_E~0;~M_E~0 := 1; 7841#L754-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 7842#L759-3 assume !(0 == ~T2_E~0); 8223#L764-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 8224#L769-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 8393#L774-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 8001#L779-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 7836#L784-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 7837#L789-3 assume 0 == ~E_1~0;~E_1~0 := 1; 7831#L794-3 assume 0 == ~E_2~0;~E_2~0 := 1; 7832#L799-3 assume !(0 == ~E_3~0); 7883#L804-3 assume 0 == ~E_4~0;~E_4~0 := 1; 8109#L809-3 assume 0 == ~E_5~0;~E_5~0 := 1; 7879#L814-3 assume 0 == ~E_6~0;~E_6~0 := 1; 7880#L819-3 assume 0 == ~E_7~0;~E_7~0 := 1; 8497#L824-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 8241#L361-24 assume 1 == ~m_pc~0; 7985#L362-8 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 7986#L372-8 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 7931#is_master_triggered_returnLabel#9 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 7932#L930-24 assume !(0 != activate_threads_~tmp~1#1); 8542#L930-26 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 8376#L380-24 assume 1 == ~t1_pc~0; 8377#L381-8 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 7914#L391-8 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 8323#is_transmit1_triggered_returnLabel#9 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 8098#L938-24 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 8099#L938-26 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 8452#L399-24 assume !(1 == ~t2_pc~0); 8117#L399-26 is_transmit2_triggered_~__retres1~2#1 := 0; 8033#L410-8 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 8034#is_transmit2_triggered_returnLabel#9 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 8277#L946-24 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 8095#L946-26 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 8096#L418-24 assume !(1 == ~t3_pc~0); 7877#L418-26 is_transmit3_triggered_~__retres1~3#1 := 0; 7878#L429-8 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 8168#is_transmit3_triggered_returnLabel#9 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 8004#L954-24 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 8005#L954-26 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 8435#L437-24 assume 1 == ~t4_pc~0; 8501#L438-8 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 8503#L448-8 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 8276#is_transmit4_triggered_returnLabel#9 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 7988#L962-24 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 7989#L962-26 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 8383#L456-24 assume 1 == ~t5_pc~0; 8357#L457-8 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 8337#L467-8 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 8338#is_transmit5_triggered_returnLabel#9 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 8536#L970-24 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 8289#L970-26 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 8290#L475-24 assume !(1 == ~t6_pc~0); 7840#L475-26 is_transmit6_triggered_~__retres1~6#1 := 0; 7839#L486-8 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 7981#is_transmit6_triggered_returnLabel#9 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 7982#L978-24 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 7820#L978-26 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 7821#L494-24 assume 1 == ~t7_pc~0; 8260#L495-8 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 8149#L505-8 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 8150#is_transmit7_triggered_returnLabel#9 activate_threads_#t~ret20#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 8092#L986-24 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 8093#L986-26 havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 8500#L837-3 assume 1 == ~M_E~0;~M_E~0 := 2; 8527#L837-5 assume !(1 == ~T1_E~0); 8284#L842-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 8285#L847-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 8431#L852-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 8341#L857-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 8342#L862-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 8584#L867-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 8258#L872-3 assume 1 == ~E_1~0;~E_1~0 := 2; 8259#L877-3 assume !(1 == ~E_2~0); 8336#L882-3 assume 1 == ~E_3~0;~E_3~0 := 2; 8387#L887-3 assume 1 == ~E_4~0;~E_4~0 := 2; 8020#L892-3 assume 1 == ~E_5~0;~E_5~0 := 2; 8021#L897-3 assume 1 == ~E_6~0;~E_6~0 := 2; 8526#L902-3 assume 1 == ~E_7~0;~E_7~0 := 2; 8181#L907-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 8182#L569-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 7834#L611-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 8118#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret22#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret22#1;havoc start_simulation_#t~ret22#1; 8119#L1167 assume !(0 == start_simulation_~tmp~3#1); 8236#L1167-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret21#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 8237#L569-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 8042#L611-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 7847#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret21#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret21#1;havoc stop_simulation_#t~ret21#1; 7848#L1122 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 8218#L1129 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 8219#stop_simulation_returnLabel#1 start_simulation_#t~ret23#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret21#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret23#1;havoc start_simulation_#t~ret23#1; 8054#L1180 assume !(0 != start_simulation_~tmp___0~1#1); 8055#L1148-2 [2023-11-12 02:09:32,460 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-12 02:09:32,460 INFO L85 PathProgramCache]: Analyzing trace with hash -1148673299, now seen corresponding path program 1 times [2023-11-12 02:09:32,461 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-12 02:09:32,462 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1055577780] [2023-11-12 02:09:32,462 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-12 02:09:32,462 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-12 02:09:32,484 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-12 02:09:32,527 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-12 02:09:32,527 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-12 02:09:32,527 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1055577780] [2023-11-12 02:09:32,528 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1055577780] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-12 02:09:32,528 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-12 02:09:32,529 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-12 02:09:32,529 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [551164450] [2023-11-12 02:09:32,529 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-12 02:09:32,530 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-12 02:09:32,542 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-12 02:09:32,543 INFO L85 PathProgramCache]: Analyzing trace with hash -1457955290, now seen corresponding path program 1 times [2023-11-12 02:09:32,543 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-12 02:09:32,544 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1556756111] [2023-11-12 02:09:32,549 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-12 02:09:32,549 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-12 02:09:32,570 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-12 02:09:32,622 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-12 02:09:32,622 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-12 02:09:32,623 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1556756111] [2023-11-12 02:09:32,623 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1556756111] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-12 02:09:32,623 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-12 02:09:32,624 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-12 02:09:32,624 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1759502457] [2023-11-12 02:09:32,624 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-12 02:09:32,625 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-12 02:09:32,625 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-12 02:09:32,625 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-12 02:09:32,626 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-12 02:09:32,626 INFO L87 Difference]: Start difference. First operand 776 states and 1152 transitions. cyclomatic complexity: 377 Second operand has 3 states, 3 states have (on average 31.0) internal successors, (93), 3 states have internal predecessors, (93), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-12 02:09:32,657 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-12 02:09:32,657 INFO L93 Difference]: Finished difference Result 776 states and 1151 transitions. [2023-11-12 02:09:32,657 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 776 states and 1151 transitions. [2023-11-12 02:09:32,668 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 675 [2023-11-12 02:09:32,677 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 776 states to 776 states and 1151 transitions. [2023-11-12 02:09:32,677 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 776 [2023-11-12 02:09:32,678 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 776 [2023-11-12 02:09:32,679 INFO L73 IsDeterministic]: Start isDeterministic. Operand 776 states and 1151 transitions. [2023-11-12 02:09:32,680 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-12 02:09:32,681 INFO L218 hiAutomatonCegarLoop]: Abstraction has 776 states and 1151 transitions. [2023-11-12 02:09:32,683 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 776 states and 1151 transitions. [2023-11-12 02:09:32,697 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 776 to 776. [2023-11-12 02:09:32,700 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 776 states, 776 states have (on average 1.4832474226804124) internal successors, (1151), 775 states have internal predecessors, (1151), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-12 02:09:32,704 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 776 states to 776 states and 1151 transitions. [2023-11-12 02:09:32,704 INFO L240 hiAutomatonCegarLoop]: Abstraction has 776 states and 1151 transitions. [2023-11-12 02:09:32,705 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-12 02:09:32,706 INFO L428 stractBuchiCegarLoop]: Abstraction has 776 states and 1151 transitions. [2023-11-12 02:09:32,706 INFO L335 stractBuchiCegarLoop]: ======== Iteration 7 ============ [2023-11-12 02:09:32,706 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 776 states and 1151 transitions. [2023-11-12 02:09:32,713 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 675 [2023-11-12 02:09:32,713 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-12 02:09:32,713 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-12 02:09:32,715 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-12 02:09:32,715 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-12 02:09:32,716 INFO L748 eck$LassoCheckResult]: Stem: 9585#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2; 9586#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~9#1;havoc main_~__retres1~9#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 10113#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret22#1, start_simulation_#t~ret23#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 10114#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 10133#L521 assume 1 == ~m_i~0;~m_st~0 := 0; 10125#L521-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 10126#L526-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 9734#L531-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 9735#L536-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 9804#L541-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 9648#L546-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 9649#L551-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 9615#L556-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 9616#L754 assume !(0 == ~M_E~0); 10141#L754-2 assume !(0 == ~T1_E~0); 10083#L759-1 assume !(0 == ~T2_E~0); 9965#L764-1 assume !(0 == ~T3_E~0); 9930#L769-1 assume !(0 == ~T4_E~0); 9931#L774-1 assume !(0 == ~T5_E~0); 9966#L779-1 assume 0 == ~T6_E~0;~T6_E~0 := 1; 10088#L784-1 assume !(0 == ~T7_E~0); 9927#L789-1 assume !(0 == ~E_1~0); 9928#L794-1 assume !(0 == ~E_2~0); 10002#L799-1 assume !(0 == ~E_3~0); 9938#L804-1 assume !(0 == ~E_4~0); 9939#L809-1 assume !(0 == ~E_5~0); 9960#L814-1 assume !(0 == ~E_6~0); 9386#L819-1 assume 0 == ~E_7~0;~E_7~0 := 1; 9387#L824-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 9645#L361 assume 1 == ~m_pc~0; 9646#L362 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 10109#L372 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 10069#is_master_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 10070#L930 assume !(0 != activate_threads_~tmp~1#1); 9847#L930-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 9639#L380 assume !(1 == ~t1_pc~0); 9640#L380-2 is_transmit1_triggered_~__retres1~1#1 := 0; 10008#L391 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 9408#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 9409#L938 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 10028#L938-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 10009#L399 assume 1 == ~t2_pc~0; 10010#L400 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 9557#L410 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 9717#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 9710#L946 assume !(0 != activate_threads_~tmp___1~0#1); 9711#L946-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 9394#L418 assume !(1 == ~t3_pc~0); 9373#L418-2 is_transmit3_triggered_~__retres1~3#1 := 0; 9374#L429 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 9384#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 9385#L954 assume !(0 != activate_threads_~tmp___2~0#1); 9950#L954-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 9951#L437 assume 1 == ~t4_pc~0; 10142#L438 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 10064#L448 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 9467#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 9468#L962 assume !(0 != activate_threads_~tmp___3~0#1); 9763#L962-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 10046#L456 assume !(1 == ~t5_pc~0); 9571#L456-2 is_transmit5_triggered_~__retres1~5#1 := 0; 9570#L467 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 10073#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 9991#L970 assume !(0 != activate_threads_~tmp___4~0#1); 9992#L970-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 9461#L475 assume 1 == ~t6_pc~0; 9462#L476 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 9503#L486 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 9504#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 9703#L978 assume !(0 != activate_threads_~tmp___5~0#1); 9943#L978-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 9944#L494 assume 1 == ~t7_pc~0; 9892#L495 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 9688#L505 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 9903#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 9967#L986 assume !(0 != activate_threads_~tmp___6~0#1); 9968#L986-2 havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 10138#L837 assume !(1 == ~M_E~0); 10112#L837-2 assume !(1 == ~T1_E~0); 10005#L842-1 assume !(1 == ~T2_E~0); 9770#L847-1 assume !(1 == ~T3_E~0); 9771#L852-1 assume !(1 == ~T4_E~0); 9837#L857-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 9723#L862-1 assume !(1 == ~T6_E~0); 9724#L867-1 assume !(1 == ~T7_E~0); 9730#L872-1 assume !(1 == ~E_1~0); 9803#L877-1 assume !(1 == ~E_2~0); 9980#L882-1 assume !(1 == ~E_3~0); 10117#L887-1 assume !(1 == ~E_4~0); 10024#L892-1 assume !(1 == ~E_5~0); 10025#L897-1 assume 1 == ~E_6~0;~E_6~0 := 2; 9746#L902-1 assume !(1 == ~E_7~0); 9747#L907-1 assume { :end_inline_reset_delta_events } true; 9614#L1148-2 [2023-11-12 02:09:32,717 INFO L750 eck$LassoCheckResult]: Loop: 9614#L1148-2 assume !false; 9388#L1149 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 9389#L729-1 assume !false; 10000#L622 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 9587#L569 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 9588#L611 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 9736#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 9632#L626 assume !(0 != eval_~tmp~0#1); 9633#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 9846#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 9661#L754-3 assume 0 == ~M_E~0;~M_E~0 := 1; 9400#L754-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 9401#L759-3 assume !(0 == ~T2_E~0); 9782#L764-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 9783#L769-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 9952#L774-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 9560#L779-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 9395#L784-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 9396#L789-3 assume 0 == ~E_1~0;~E_1~0 := 1; 9390#L794-3 assume 0 == ~E_2~0;~E_2~0 := 1; 9391#L799-3 assume !(0 == ~E_3~0); 9442#L804-3 assume 0 == ~E_4~0;~E_4~0 := 1; 9668#L809-3 assume 0 == ~E_5~0;~E_5~0 := 1; 9438#L814-3 assume 0 == ~E_6~0;~E_6~0 := 1; 9439#L819-3 assume 0 == ~E_7~0;~E_7~0 := 1; 10056#L824-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 9800#L361-24 assume 1 == ~m_pc~0; 9544#L362-8 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 9545#L372-8 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 9490#is_master_triggered_returnLabel#9 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 9491#L930-24 assume !(0 != activate_threads_~tmp~1#1); 10101#L930-26 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 9935#L380-24 assume 1 == ~t1_pc~0; 9936#L381-8 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 9473#L391-8 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 9882#is_transmit1_triggered_returnLabel#9 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 9657#L938-24 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 9658#L938-26 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 10011#L399-24 assume !(1 == ~t2_pc~0); 9676#L399-26 is_transmit2_triggered_~__retres1~2#1 := 0; 9592#L410-8 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 9593#is_transmit2_triggered_returnLabel#9 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 9836#L946-24 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 9654#L946-26 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 9655#L418-24 assume 1 == ~t3_pc~0; 10100#L419-8 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 9437#L429-8 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 9727#is_transmit3_triggered_returnLabel#9 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 9563#L954-24 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 9564#L954-26 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 9994#L437-24 assume 1 == ~t4_pc~0; 10060#L438-8 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 10062#L448-8 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 9835#is_transmit4_triggered_returnLabel#9 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 9547#L962-24 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 9548#L962-26 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 9942#L456-24 assume 1 == ~t5_pc~0; 9916#L457-8 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 9896#L467-8 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 9897#is_transmit5_triggered_returnLabel#9 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 10095#L970-24 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 9848#L970-26 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 9849#L475-24 assume 1 == ~t6_pc~0; 9397#L476-8 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 9398#L486-8 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 9540#is_transmit6_triggered_returnLabel#9 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 9541#L978-24 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 9379#L978-26 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 9380#L494-24 assume !(1 == ~t7_pc~0); 9728#L494-26 is_transmit7_triggered_~__retres1~7#1 := 0; 9708#L505-8 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 9709#is_transmit7_triggered_returnLabel#9 activate_threads_#t~ret20#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 9651#L986-24 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 9652#L986-26 havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 10059#L837-3 assume 1 == ~M_E~0;~M_E~0 := 2; 10086#L837-5 assume !(1 == ~T1_E~0); 9843#L842-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 9844#L847-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 9990#L852-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 9900#L857-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 9901#L862-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 10143#L867-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 9817#L872-3 assume 1 == ~E_1~0;~E_1~0 := 2; 9818#L877-3 assume !(1 == ~E_2~0); 9895#L882-3 assume 1 == ~E_3~0;~E_3~0 := 2; 9946#L887-3 assume 1 == ~E_4~0;~E_4~0 := 2; 9579#L892-3 assume 1 == ~E_5~0;~E_5~0 := 2; 9580#L897-3 assume 1 == ~E_6~0;~E_6~0 := 2; 10085#L902-3 assume 1 == ~E_7~0;~E_7~0 := 2; 9740#L907-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 9741#L569-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 9393#L611-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 9677#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret22#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret22#1;havoc start_simulation_#t~ret22#1; 9678#L1167 assume !(0 == start_simulation_~tmp~3#1); 9795#L1167-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret21#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 9796#L569-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 9601#L611-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 9406#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret21#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret21#1;havoc stop_simulation_#t~ret21#1; 9407#L1122 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 9777#L1129 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 9778#stop_simulation_returnLabel#1 start_simulation_#t~ret23#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret21#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret23#1;havoc start_simulation_#t~ret23#1; 9613#L1180 assume !(0 != start_simulation_~tmp___0~1#1); 9614#L1148-2 [2023-11-12 02:09:32,718 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-12 02:09:32,718 INFO L85 PathProgramCache]: Analyzing trace with hash 1821437803, now seen corresponding path program 1 times [2023-11-12 02:09:32,718 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-12 02:09:32,719 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1847796375] [2023-11-12 02:09:32,719 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-12 02:09:32,719 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-12 02:09:32,731 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-12 02:09:32,762 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-12 02:09:32,763 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-12 02:09:32,763 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1847796375] [2023-11-12 02:09:32,763 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1847796375] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-12 02:09:32,763 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-12 02:09:32,764 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-12 02:09:32,764 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [438533558] [2023-11-12 02:09:32,764 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-12 02:09:32,765 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-12 02:09:32,765 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-12 02:09:32,765 INFO L85 PathProgramCache]: Analyzing trace with hash 1950017927, now seen corresponding path program 2 times [2023-11-12 02:09:32,766 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-12 02:09:32,766 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1576394387] [2023-11-12 02:09:32,766 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-12 02:09:32,766 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-12 02:09:32,782 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-12 02:09:32,821 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-12 02:09:32,821 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-12 02:09:32,821 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1576394387] [2023-11-12 02:09:32,821 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1576394387] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-12 02:09:32,822 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-12 02:09:32,822 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-12 02:09:32,822 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [70633189] [2023-11-12 02:09:32,822 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-12 02:09:32,823 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-12 02:09:32,823 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-12 02:09:32,823 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-12 02:09:32,823 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-12 02:09:32,824 INFO L87 Difference]: Start difference. First operand 776 states and 1151 transitions. cyclomatic complexity: 376 Second operand has 3 states, 3 states have (on average 31.0) internal successors, (93), 3 states have internal predecessors, (93), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-12 02:09:32,845 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-12 02:09:32,846 INFO L93 Difference]: Finished difference Result 776 states and 1150 transitions. [2023-11-12 02:09:32,846 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 776 states and 1150 transitions. [2023-11-12 02:09:32,854 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 675 [2023-11-12 02:09:32,861 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 776 states to 776 states and 1150 transitions. [2023-11-12 02:09:32,861 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 776 [2023-11-12 02:09:32,862 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 776 [2023-11-12 02:09:32,862 INFO L73 IsDeterministic]: Start isDeterministic. Operand 776 states and 1150 transitions. [2023-11-12 02:09:32,863 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-12 02:09:32,863 INFO L218 hiAutomatonCegarLoop]: Abstraction has 776 states and 1150 transitions. [2023-11-12 02:09:32,865 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 776 states and 1150 transitions. [2023-11-12 02:09:32,878 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 776 to 776. [2023-11-12 02:09:32,880 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 776 states, 776 states have (on average 1.481958762886598) internal successors, (1150), 775 states have internal predecessors, (1150), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-12 02:09:32,884 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 776 states to 776 states and 1150 transitions. [2023-11-12 02:09:32,884 INFO L240 hiAutomatonCegarLoop]: Abstraction has 776 states and 1150 transitions. [2023-11-12 02:09:32,884 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-12 02:09:32,885 INFO L428 stractBuchiCegarLoop]: Abstraction has 776 states and 1150 transitions. [2023-11-12 02:09:32,885 INFO L335 stractBuchiCegarLoop]: ======== Iteration 8 ============ [2023-11-12 02:09:32,886 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 776 states and 1150 transitions. [2023-11-12 02:09:32,891 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 675 [2023-11-12 02:09:32,892 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-12 02:09:32,892 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-12 02:09:32,893 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-12 02:09:32,894 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-12 02:09:32,894 INFO L748 eck$LassoCheckResult]: Stem: 11144#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2; 11145#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~9#1;havoc main_~__retres1~9#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 11672#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret22#1, start_simulation_#t~ret23#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 11673#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 11692#L521 assume 1 == ~m_i~0;~m_st~0 := 0; 11684#L521-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 11685#L526-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 11293#L531-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 11294#L536-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 11363#L541-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 11208#L546-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 11209#L551-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 11174#L556-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 11175#L754 assume !(0 == ~M_E~0); 11700#L754-2 assume !(0 == ~T1_E~0); 11642#L759-1 assume !(0 == ~T2_E~0); 11524#L764-1 assume !(0 == ~T3_E~0); 11490#L769-1 assume !(0 == ~T4_E~0); 11491#L774-1 assume !(0 == ~T5_E~0); 11525#L779-1 assume 0 == ~T6_E~0;~T6_E~0 := 1; 11647#L784-1 assume !(0 == ~T7_E~0); 11487#L789-1 assume !(0 == ~E_1~0); 11488#L794-1 assume !(0 == ~E_2~0); 11561#L799-1 assume !(0 == ~E_3~0); 11497#L804-1 assume !(0 == ~E_4~0); 11498#L809-1 assume !(0 == ~E_5~0); 11519#L814-1 assume !(0 == ~E_6~0); 10949#L819-1 assume 0 == ~E_7~0;~E_7~0 := 1; 10950#L824-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 11204#L361 assume 1 == ~m_pc~0; 11205#L362 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 11668#L372 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 11628#is_master_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 11629#L930 assume !(0 != activate_threads_~tmp~1#1); 11406#L930-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 11198#L380 assume !(1 == ~t1_pc~0); 11199#L380-2 is_transmit1_triggered_~__retres1~1#1 := 0; 11567#L391 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 10967#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 10968#L938 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 11587#L938-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 11568#L399 assume 1 == ~t2_pc~0; 11569#L400 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 11116#L410 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 11276#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 11269#L946 assume !(0 != activate_threads_~tmp___1~0#1); 11270#L946-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 10953#L418 assume !(1 == ~t3_pc~0); 10932#L418-2 is_transmit3_triggered_~__retres1~3#1 := 0; 10933#L429 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 10943#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 10944#L954 assume !(0 != activate_threads_~tmp___2~0#1); 11509#L954-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 11510#L437 assume 1 == ~t4_pc~0; 11701#L438 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 11624#L448 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 11027#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 11028#L962 assume !(0 != activate_threads_~tmp___3~0#1); 11322#L962-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 11610#L456 assume !(1 == ~t5_pc~0); 11130#L456-2 is_transmit5_triggered_~__retres1~5#1 := 0; 11129#L467 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 11632#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 11551#L970 assume !(0 != activate_threads_~tmp___4~0#1); 11552#L970-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 11020#L475 assume 1 == ~t6_pc~0; 11021#L476 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 11062#L486 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 11063#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 11262#L978 assume !(0 != activate_threads_~tmp___5~0#1); 11502#L978-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 11503#L494 assume 1 == ~t7_pc~0; 11451#L495 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 11247#L505 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 11462#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 11526#L986 assume !(0 != activate_threads_~tmp___6~0#1); 11527#L986-2 havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 11697#L837 assume !(1 == ~M_E~0); 11671#L837-2 assume !(1 == ~T1_E~0); 11564#L842-1 assume !(1 == ~T2_E~0); 11329#L847-1 assume !(1 == ~T3_E~0); 11330#L852-1 assume !(1 == ~T4_E~0); 11396#L857-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 11282#L862-1 assume !(1 == ~T6_E~0); 11283#L867-1 assume !(1 == ~T7_E~0); 11289#L872-1 assume !(1 == ~E_1~0); 11362#L877-1 assume !(1 == ~E_2~0); 11539#L882-1 assume !(1 == ~E_3~0); 11676#L887-1 assume !(1 == ~E_4~0); 11583#L892-1 assume !(1 == ~E_5~0); 11584#L897-1 assume 1 == ~E_6~0;~E_6~0 := 2; 11305#L902-1 assume !(1 == ~E_7~0); 11306#L907-1 assume { :end_inline_reset_delta_events } true; 11173#L1148-2 [2023-11-12 02:09:32,895 INFO L750 eck$LassoCheckResult]: Loop: 11173#L1148-2 assume !false; 10945#L1149 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 10946#L729-1 assume !false; 11559#L622 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 11146#L569 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 11147#L611 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 11295#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 11191#L626 assume !(0 != eval_~tmp~0#1); 11192#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 11405#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 11220#L754-3 assume 0 == ~M_E~0;~M_E~0 := 1; 10959#L754-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 10960#L759-3 assume !(0 == ~T2_E~0); 11341#L764-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 11342#L769-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 11511#L774-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 11119#L779-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 10954#L784-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 10955#L789-3 assume 0 == ~E_1~0;~E_1~0 := 1; 10947#L794-3 assume 0 == ~E_2~0;~E_2~0 := 1; 10948#L799-3 assume !(0 == ~E_3~0); 11001#L804-3 assume 0 == ~E_4~0;~E_4~0 := 1; 11227#L809-3 assume 0 == ~E_5~0;~E_5~0 := 1; 10997#L814-3 assume 0 == ~E_6~0;~E_6~0 := 1; 10998#L819-3 assume 0 == ~E_7~0;~E_7~0 := 1; 11615#L824-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 11359#L361-24 assume !(1 == ~m_pc~0); 11105#L361-26 is_master_triggered_~__retres1~0#1 := 0; 11104#L372-8 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 11049#is_master_triggered_returnLabel#9 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 11050#L930-24 assume !(0 != activate_threads_~tmp~1#1); 11660#L930-26 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 11494#L380-24 assume 1 == ~t1_pc~0; 11495#L381-8 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 11032#L391-8 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 11441#is_transmit1_triggered_returnLabel#9 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 11216#L938-24 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 11217#L938-26 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 11570#L399-24 assume !(1 == ~t2_pc~0); 11235#L399-26 is_transmit2_triggered_~__retres1~2#1 := 0; 11151#L410-8 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 11152#is_transmit2_triggered_returnLabel#9 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 11395#L946-24 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 11213#L946-26 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 11214#L418-24 assume !(1 == ~t3_pc~0); 10995#L418-26 is_transmit3_triggered_~__retres1~3#1 := 0; 10996#L429-8 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 11286#is_transmit3_triggered_returnLabel#9 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 11122#L954-24 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 11123#L954-26 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 11553#L437-24 assume 1 == ~t4_pc~0; 11619#L438-8 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 11621#L448-8 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 11394#is_transmit4_triggered_returnLabel#9 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 11106#L962-24 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 11107#L962-26 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 11501#L456-24 assume 1 == ~t5_pc~0; 11475#L457-8 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 11455#L467-8 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 11456#is_transmit5_triggered_returnLabel#9 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 11654#L970-24 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 11407#L970-26 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 11408#L475-24 assume 1 == ~t6_pc~0; 10956#L476-8 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 10957#L486-8 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 11099#is_transmit6_triggered_returnLabel#9 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 11100#L978-24 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 10938#L978-26 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 10939#L494-24 assume 1 == ~t7_pc~0; 11378#L495-8 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 11267#L505-8 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 11268#is_transmit7_triggered_returnLabel#9 activate_threads_#t~ret20#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 11210#L986-24 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 11211#L986-26 havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 11618#L837-3 assume 1 == ~M_E~0;~M_E~0 := 2; 11645#L837-5 assume !(1 == ~T1_E~0); 11402#L842-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 11403#L847-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 11549#L852-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 11459#L857-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 11460#L862-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 11702#L867-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 11376#L872-3 assume 1 == ~E_1~0;~E_1~0 := 2; 11377#L877-3 assume !(1 == ~E_2~0); 11454#L882-3 assume 1 == ~E_3~0;~E_3~0 := 2; 11505#L887-3 assume 1 == ~E_4~0;~E_4~0 := 2; 11138#L892-3 assume 1 == ~E_5~0;~E_5~0 := 2; 11139#L897-3 assume 1 == ~E_6~0;~E_6~0 := 2; 11644#L902-3 assume 1 == ~E_7~0;~E_7~0 := 2; 11299#L907-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 11300#L569-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 10952#L611-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 11236#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret22#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret22#1;havoc start_simulation_#t~ret22#1; 11237#L1167 assume !(0 == start_simulation_~tmp~3#1); 11354#L1167-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret21#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 11355#L569-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 11160#L611-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 10965#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret21#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret21#1;havoc stop_simulation_#t~ret21#1; 10966#L1122 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 11336#L1129 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 11337#stop_simulation_returnLabel#1 start_simulation_#t~ret23#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret21#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret23#1;havoc start_simulation_#t~ret23#1; 11172#L1180 assume !(0 != start_simulation_~tmp___0~1#1); 11173#L1148-2 [2023-11-12 02:09:32,896 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-12 02:09:32,896 INFO L85 PathProgramCache]: Analyzing trace with hash 254679853, now seen corresponding path program 1 times [2023-11-12 02:09:32,896 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-12 02:09:32,896 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1206302582] [2023-11-12 02:09:32,896 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-12 02:09:32,897 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-12 02:09:32,911 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-12 02:09:32,979 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-12 02:09:32,979 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-12 02:09:32,980 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1206302582] [2023-11-12 02:09:32,980 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1206302582] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-12 02:09:32,980 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-12 02:09:32,980 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-12 02:09:32,980 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1459447161] [2023-11-12 02:09:32,981 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-12 02:09:32,981 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-12 02:09:32,981 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-12 02:09:32,982 INFO L85 PathProgramCache]: Analyzing trace with hash -1778828634, now seen corresponding path program 1 times [2023-11-12 02:09:32,982 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-12 02:09:32,982 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1974551921] [2023-11-12 02:09:32,983 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-12 02:09:32,983 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-12 02:09:32,998 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-12 02:09:33,038 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-12 02:09:33,039 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-12 02:09:33,039 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1974551921] [2023-11-12 02:09:33,039 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1974551921] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-12 02:09:33,040 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-12 02:09:33,040 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-12 02:09:33,040 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [813683445] [2023-11-12 02:09:33,040 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-12 02:09:33,041 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-12 02:09:33,041 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-12 02:09:33,041 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2023-11-12 02:09:33,042 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2023-11-12 02:09:33,042 INFO L87 Difference]: Start difference. First operand 776 states and 1150 transitions. cyclomatic complexity: 375 Second operand has 4 states, 4 states have (on average 23.25) internal successors, (93), 3 states have internal predecessors, (93), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-12 02:09:33,224 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-12 02:09:33,224 INFO L93 Difference]: Finished difference Result 1464 states and 2164 transitions. [2023-11-12 02:09:33,224 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1464 states and 2164 transitions. [2023-11-12 02:09:33,240 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 1350 [2023-11-12 02:09:33,254 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1464 states to 1464 states and 2164 transitions. [2023-11-12 02:09:33,254 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1464 [2023-11-12 02:09:33,256 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1464 [2023-11-12 02:09:33,256 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1464 states and 2164 transitions. [2023-11-12 02:09:33,259 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-12 02:09:33,259 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1464 states and 2164 transitions. [2023-11-12 02:09:33,262 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1464 states and 2164 transitions. [2023-11-12 02:09:33,294 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1464 to 1464. [2023-11-12 02:09:33,298 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1464 states, 1464 states have (on average 1.4781420765027322) internal successors, (2164), 1463 states have internal predecessors, (2164), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-12 02:09:33,305 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1464 states to 1464 states and 2164 transitions. [2023-11-12 02:09:33,306 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1464 states and 2164 transitions. [2023-11-12 02:09:33,306 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2023-11-12 02:09:33,307 INFO L428 stractBuchiCegarLoop]: Abstraction has 1464 states and 2164 transitions. [2023-11-12 02:09:33,307 INFO L335 stractBuchiCegarLoop]: ======== Iteration 9 ============ [2023-11-12 02:09:33,308 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1464 states and 2164 transitions. [2023-11-12 02:09:33,320 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 1350 [2023-11-12 02:09:33,320 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-12 02:09:33,320 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-12 02:09:33,322 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-12 02:09:33,322 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-12 02:09:33,323 INFO L748 eck$LassoCheckResult]: Stem: 13395#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2; 13396#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~9#1;havoc main_~__retres1~9#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 13972#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret22#1, start_simulation_#t~ret23#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 13973#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 14004#L521 assume 1 == ~m_i~0;~m_st~0 := 0; 13990#L521-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 13991#L526-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 13547#L531-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 13548#L536-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 13625#L541-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 13459#L546-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 13460#L551-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 13425#L556-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 13426#L754 assume !(0 == ~M_E~0); 14022#L754-2 assume !(0 == ~T1_E~0); 13932#L759-1 assume !(0 == ~T2_E~0); 13799#L764-1 assume !(0 == ~T3_E~0); 13762#L769-1 assume !(0 == ~T4_E~0); 13763#L774-1 assume !(0 == ~T5_E~0); 13800#L779-1 assume !(0 == ~T6_E~0); 13940#L784-1 assume !(0 == ~T7_E~0); 13759#L789-1 assume !(0 == ~E_1~0); 13760#L794-1 assume !(0 == ~E_2~0); 13839#L799-1 assume !(0 == ~E_3~0); 13769#L804-1 assume !(0 == ~E_4~0); 13770#L809-1 assume !(0 == ~E_5~0); 13794#L814-1 assume !(0 == ~E_6~0); 13195#L819-1 assume 0 == ~E_7~0;~E_7~0 := 1; 13196#L824-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 13456#L361 assume 1 == ~m_pc~0; 13457#L362 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 13966#L372 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 13917#is_master_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 13918#L930 assume !(0 != activate_threads_~tmp~1#1); 13671#L930-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 13450#L380 assume !(1 == ~t1_pc~0); 13451#L380-2 is_transmit1_triggered_~__retres1~1#1 := 0; 13848#L391 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 13217#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 13218#L938 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 13873#L938-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 13849#L399 assume 1 == ~t2_pc~0; 13850#L400 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 13367#L410 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 13529#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 13522#L946 assume !(0 != activate_threads_~tmp___1~0#1); 13523#L946-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 13203#L418 assume !(1 == ~t3_pc~0); 13182#L418-2 is_transmit3_triggered_~__retres1~3#1 := 0; 13183#L429 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 13193#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 13194#L954 assume !(0 != activate_threads_~tmp___2~0#1); 13782#L954-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 13783#L437 assume 1 == ~t4_pc~0; 14023#L438 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 13912#L448 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 13276#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 13277#L962 assume !(0 != activate_threads_~tmp___3~0#1); 13576#L962-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 13897#L456 assume !(1 == ~t5_pc~0); 13381#L456-2 is_transmit5_triggered_~__retres1~5#1 := 0; 13380#L467 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 13921#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 13828#L970 assume !(0 != activate_threads_~tmp___4~0#1); 13829#L970-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 13270#L475 assume 1 == ~t6_pc~0; 13271#L476 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 13312#L486 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 13313#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 13515#L978 assume !(0 != activate_threads_~tmp___5~0#1); 13775#L978-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 13776#L494 assume 1 == ~t7_pc~0; 13720#L495 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 13500#L505 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 13734#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 13801#L986 assume !(0 != activate_threads_~tmp___6~0#1); 13802#L986-2 havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 14012#L837 assume !(1 == ~M_E~0); 13971#L837-2 assume !(1 == ~T1_E~0); 13844#L842-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 13845#L847-1 assume !(1 == ~T3_E~0); 14069#L852-1 assume !(1 == ~T4_E~0); 14067#L857-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 14066#L862-1 assume !(1 == ~T6_E~0); 13536#L867-1 assume !(1 == ~T7_E~0); 13623#L872-1 assume !(1 == ~E_1~0); 13624#L877-1 assume !(1 == ~E_2~0); 13816#L882-1 assume !(1 == ~E_3~0); 13977#L887-1 assume !(1 == ~E_4~0); 14026#L892-1 assume !(1 == ~E_5~0); 14007#L897-1 assume 1 == ~E_6~0;~E_6~0 := 2; 13559#L902-1 assume !(1 == ~E_7~0); 13560#L907-1 assume { :end_inline_reset_delta_events } true; 13424#L1148-2 [2023-11-12 02:09:33,324 INFO L750 eck$LassoCheckResult]: Loop: 13424#L1148-2 assume !false; 13197#L1149 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 13198#L729-1 assume !false; 14049#L622 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 14045#L569 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 13946#L611 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 13554#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 13445#L626 assume !(0 != eval_~tmp~0#1); 13446#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 13670#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 13472#L754-3 assume 0 == ~M_E~0;~M_E~0 := 1; 13209#L754-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 13210#L759-3 assume !(0 == ~T2_E~0); 14036#L764-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 14213#L769-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 14212#L774-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 14211#L779-3 assume !(0 == ~T6_E~0); 14210#L784-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 14209#L789-3 assume 0 == ~E_1~0;~E_1~0 := 1; 14208#L794-3 assume 0 == ~E_2~0;~E_2~0 := 1; 14207#L799-3 assume !(0 == ~E_3~0); 14206#L804-3 assume 0 == ~E_4~0;~E_4~0 := 1; 14205#L809-3 assume 0 == ~E_5~0;~E_5~0 := 1; 14204#L814-3 assume 0 == ~E_6~0;~E_6~0 := 1; 14203#L819-3 assume 0 == ~E_7~0;~E_7~0 := 1; 14202#L824-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 14201#L361-24 assume 1 == ~m_pc~0; 13353#L362-8 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 13354#L372-8 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 13299#is_master_triggered_returnLabel#9 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 13300#L930-24 assume !(0 != activate_threads_~tmp~1#1); 13957#L930-26 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 13766#L380-24 assume !(1 == ~t1_pc~0); 13281#L380-26 is_transmit1_triggered_~__retres1~1#1 := 0; 13282#L391-8 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 13710#is_transmit1_triggered_returnLabel#9 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 13468#L938-24 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 13469#L938-26 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 13851#L399-24 assume !(1 == ~t2_pc~0); 13924#L399-26 is_transmit2_triggered_~__retres1~2#1 := 0; 14188#L410-8 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 14187#is_transmit2_triggered_returnLabel#9 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 14186#L946-24 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 13465#L946-26 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 13466#L418-24 assume 1 == ~t3_pc~0; 14184#L419-8 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 14183#L429-8 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 14182#is_transmit3_triggered_returnLabel#9 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 14181#L954-24 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 14180#L954-26 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 14179#L437-24 assume !(1 == ~t4_pc~0); 14177#L437-26 is_transmit4_triggered_~__retres1~4#1 := 0; 14176#L448-8 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 14175#is_transmit4_triggered_returnLabel#9 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 14174#L962-24 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 14173#L962-26 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 14172#L456-24 assume 1 == ~t5_pc~0; 14170#L457-8 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 14169#L467-8 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 14168#is_transmit5_triggered_returnLabel#9 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 14167#L970-24 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 13672#L970-26 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 13673#L475-24 assume !(1 == ~t6_pc~0); 14034#L475-26 is_transmit6_triggered_~__retres1~6#1 := 0; 13733#L486-8 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 13349#is_transmit6_triggered_returnLabel#9 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 13350#L978-24 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 13771#L978-26 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 14127#L494-24 assume !(1 == ~t7_pc~0); 13541#L494-26 is_transmit7_triggered_~__retres1~7#1 := 0; 13519#L505-8 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 13520#is_transmit7_triggered_returnLabel#9 activate_threads_#t~ret20#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 14118#L986-24 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 13906#L986-26 havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 13907#L837-3 assume 1 == ~M_E~0;~M_E~0 := 2; 13937#L837-5 assume !(1 == ~T1_E~0); 13667#L842-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 13668#L847-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 14110#L852-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 14108#L857-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 14107#L862-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 14031#L867-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 14105#L872-3 assume 1 == ~E_1~0;~E_1~0 := 2; 14104#L877-3 assume !(1 == ~E_2~0); 14101#L882-3 assume 1 == ~E_3~0;~E_3~0 := 2; 14100#L887-3 assume 1 == ~E_4~0;~E_4~0 := 2; 14099#L892-3 assume 1 == ~E_5~0;~E_5~0 := 2; 13935#L897-3 assume 1 == ~E_6~0;~E_6~0 := 2; 13936#L902-3 assume 1 == ~E_7~0;~E_7~0 := 2; 13552#L907-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 13553#L569-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 14084#L611-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 13489#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret22#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret22#1;havoc start_simulation_#t~ret22#1; 13490#L1167 assume !(0 == start_simulation_~tmp~3#1); 14082#L1167-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret21#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 14081#L569-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 14073#L611-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 14072#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret21#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret21#1;havoc stop_simulation_#t~ret21#1; 14071#L1122 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 14070#L1129 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 14068#stop_simulation_returnLabel#1 start_simulation_#t~ret23#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret21#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret23#1;havoc start_simulation_#t~ret23#1; 13423#L1180 assume !(0 != start_simulation_~tmp___0~1#1); 13424#L1148-2 [2023-11-12 02:09:33,324 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-12 02:09:33,325 INFO L85 PathProgramCache]: Analyzing trace with hash -2141947347, now seen corresponding path program 1 times [2023-11-12 02:09:33,325 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-12 02:09:33,325 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [951910168] [2023-11-12 02:09:33,325 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-12 02:09:33,326 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-12 02:09:33,339 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-12 02:09:33,386 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-12 02:09:33,386 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-12 02:09:33,386 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [951910168] [2023-11-12 02:09:33,387 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [951910168] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-12 02:09:33,387 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-12 02:09:33,387 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2023-11-12 02:09:33,387 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1947191246] [2023-11-12 02:09:33,387 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-12 02:09:33,388 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-12 02:09:33,388 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-12 02:09:33,389 INFO L85 PathProgramCache]: Analyzing trace with hash 596622562, now seen corresponding path program 1 times [2023-11-12 02:09:33,389 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-12 02:09:33,389 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1764487285] [2023-11-12 02:09:33,389 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-12 02:09:33,390 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-12 02:09:33,405 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-12 02:09:33,444 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-12 02:09:33,444 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-12 02:09:33,445 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1764487285] [2023-11-12 02:09:33,445 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1764487285] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-12 02:09:33,445 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-12 02:09:33,445 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-12 02:09:33,446 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [269988240] [2023-11-12 02:09:33,446 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-12 02:09:33,446 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-12 02:09:33,447 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-12 02:09:33,447 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-12 02:09:33,447 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-12 02:09:33,448 INFO L87 Difference]: Start difference. First operand 1464 states and 2164 transitions. cyclomatic complexity: 702 Second operand has 3 states, 3 states have (on average 31.0) internal successors, (93), 2 states have internal predecessors, (93), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-12 02:09:33,514 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-12 02:09:33,514 INFO L93 Difference]: Finished difference Result 1464 states and 2138 transitions. [2023-11-12 02:09:33,515 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1464 states and 2138 transitions. [2023-11-12 02:09:33,529 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 1350 [2023-11-12 02:09:33,542 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1464 states to 1464 states and 2138 transitions. [2023-11-12 02:09:33,543 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1464 [2023-11-12 02:09:33,544 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1464 [2023-11-12 02:09:33,544 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1464 states and 2138 transitions. [2023-11-12 02:09:33,547 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-12 02:09:33,547 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1464 states and 2138 transitions. [2023-11-12 02:09:33,550 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1464 states and 2138 transitions. [2023-11-12 02:09:33,580 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1464 to 1464. [2023-11-12 02:09:33,583 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1464 states, 1464 states have (on average 1.460382513661202) internal successors, (2138), 1463 states have internal predecessors, (2138), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-12 02:09:33,591 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1464 states to 1464 states and 2138 transitions. [2023-11-12 02:09:33,591 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1464 states and 2138 transitions. [2023-11-12 02:09:33,591 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-12 02:09:33,592 INFO L428 stractBuchiCegarLoop]: Abstraction has 1464 states and 2138 transitions. [2023-11-12 02:09:33,592 INFO L335 stractBuchiCegarLoop]: ======== Iteration 10 ============ [2023-11-12 02:09:33,593 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1464 states and 2138 transitions. [2023-11-12 02:09:33,603 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 1350 [2023-11-12 02:09:33,604 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-12 02:09:33,604 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-12 02:09:33,606 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-12 02:09:33,606 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-12 02:09:33,606 INFO L748 eck$LassoCheckResult]: Stem: 16327#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2; 16328#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~9#1;havoc main_~__retres1~9#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 16893#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret22#1, start_simulation_#t~ret23#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 16894#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 16922#L521 assume 1 == ~m_i~0;~m_st~0 := 0; 16911#L521-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 16912#L526-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 16480#L531-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 16481#L536-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 16552#L541-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 16390#L546-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 16391#L551-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 16357#L556-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 16358#L754 assume !(0 == ~M_E~0); 16934#L754-2 assume !(0 == ~T1_E~0); 16860#L759-1 assume !(0 == ~T2_E~0); 16721#L764-1 assume !(0 == ~T3_E~0); 16681#L769-1 assume !(0 == ~T4_E~0); 16682#L774-1 assume !(0 == ~T5_E~0); 16722#L779-1 assume !(0 == ~T6_E~0); 16865#L784-1 assume !(0 == ~T7_E~0); 16678#L789-1 assume !(0 == ~E_1~0); 16679#L794-1 assume !(0 == ~E_2~0); 16764#L799-1 assume !(0 == ~E_3~0); 16689#L804-1 assume !(0 == ~E_4~0); 16690#L809-1 assume !(0 == ~E_5~0); 16716#L814-1 assume !(0 == ~E_6~0); 16130#L819-1 assume !(0 == ~E_7~0); 16131#L824-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 16387#L361 assume 1 == ~m_pc~0; 16388#L362 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 16888#L372 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 16846#is_master_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 16847#L930 assume !(0 != activate_threads_~tmp~1#1); 16597#L930-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 16381#L380 assume !(1 == ~t1_pc~0); 16382#L380-2 is_transmit1_triggered_~__retres1~1#1 := 0; 16773#L391 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 16152#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 16153#L938 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 16800#L938-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 16774#L399 assume 1 == ~t2_pc~0; 16775#L400 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 16299#L410 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 16463#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 16456#L946 assume !(0 != activate_threads_~tmp___1~0#1); 16457#L946-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 16138#L418 assume !(1 == ~t3_pc~0); 16117#L418-2 is_transmit3_triggered_~__retres1~3#1 := 0; 16118#L429 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 16128#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 16129#L954 assume !(0 != activate_threads_~tmp___2~0#1); 16702#L954-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 16703#L437 assume 1 == ~t4_pc~0; 16935#L438 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 16841#L448 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 16211#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 16212#L962 assume !(0 != activate_threads_~tmp___3~0#1); 16510#L962-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 16820#L456 assume !(1 == ~t5_pc~0); 16313#L456-2 is_transmit5_triggered_~__retres1~5#1 := 0; 16312#L467 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 16850#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 16752#L970 assume !(0 != activate_threads_~tmp___4~0#1); 16753#L970-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 16205#L475 assume 1 == ~t6_pc~0; 16206#L476 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 16247#L486 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 16248#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 16449#L978 assume !(0 != activate_threads_~tmp___5~0#1); 16694#L978-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 16695#L494 assume !(1 == ~t7_pc~0); 16433#L494-2 is_transmit7_triggered_~__retres1~7#1 := 0; 16434#L505 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 16653#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 16723#L986 assume !(0 != activate_threads_~tmp___6~0#1); 16724#L986-2 havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 16928#L837 assume !(1 == ~M_E~0); 16892#L837-2 assume !(1 == ~T1_E~0); 16769#L842-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 16517#L847-1 assume !(1 == ~T3_E~0); 16518#L852-1 assume !(1 == ~T4_E~0); 16586#L857-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 16469#L862-1 assume !(1 == ~T6_E~0); 16470#L867-1 assume !(1 == ~T7_E~0); 16476#L872-1 assume !(1 == ~E_1~0); 16551#L877-1 assume !(1 == ~E_2~0); 16738#L882-1 assume !(1 == ~E_3~0); 16985#L887-1 assume !(1 == ~E_4~0); 16792#L892-1 assume !(1 == ~E_5~0); 16793#L897-1 assume 1 == ~E_6~0;~E_6~0 := 2; 16493#L902-1 assume !(1 == ~E_7~0); 16494#L907-1 assume { :end_inline_reset_delta_events } true; 16538#L1148-2 [2023-11-12 02:09:33,607 INFO L750 eck$LassoCheckResult]: Loop: 16538#L1148-2 assume !false; 16539#L1149 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 16761#L729-1 assume !false; 16762#L622 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 16329#L569 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 16330#L611 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 16948#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 16374#L626 assume !(0 != eval_~tmp~0#1); 16375#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 16596#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 16405#L754-3 assume 0 == ~M_E~0;~M_E~0 := 1; 16144#L754-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 16145#L759-3 assume !(0 == ~T2_E~0); 16945#L764-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 17451#L769-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 17450#L774-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 17449#L779-3 assume !(0 == ~T6_E~0); 17448#L784-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 17447#L789-3 assume 0 == ~E_1~0;~E_1~0 := 1; 17446#L794-3 assume 0 == ~E_2~0;~E_2~0 := 1; 17445#L799-3 assume !(0 == ~E_3~0); 17444#L804-3 assume 0 == ~E_4~0;~E_4~0 := 1; 17443#L809-3 assume 0 == ~E_5~0;~E_5~0 := 1; 17442#L814-3 assume 0 == ~E_6~0;~E_6~0 := 1; 17441#L819-3 assume !(0 == ~E_7~0); 17440#L824-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 17439#L361-24 assume 1 == ~m_pc~0; 17437#L362-8 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 17436#L372-8 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 17435#is_master_triggered_returnLabel#9 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 17434#L930-24 assume !(0 != activate_threads_~tmp~1#1); 17433#L930-26 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 17432#L380-24 assume 1 == ~t1_pc~0; 17430#L381-8 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 17429#L391-8 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 17428#is_transmit1_triggered_returnLabel#9 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 17427#L938-24 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 17426#L938-26 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 17425#L399-24 assume !(1 == ~t2_pc~0); 17424#L399-26 is_transmit2_triggered_~__retres1~2#1 := 0; 17422#L410-8 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 17421#is_transmit2_triggered_returnLabel#9 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 17420#L946-24 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 17419#L946-26 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 17418#L418-24 assume 1 == ~t3_pc~0; 17416#L419-8 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 17415#L429-8 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 17414#is_transmit3_triggered_returnLabel#9 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 17413#L954-24 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 17412#L954-26 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 17411#L437-24 assume !(1 == ~t4_pc~0); 17409#L437-26 is_transmit4_triggered_~__retres1~4#1 := 0; 17408#L448-8 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 17407#is_transmit4_triggered_returnLabel#9 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 17406#L962-24 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 17405#L962-26 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 17404#L456-24 assume 1 == ~t5_pc~0; 17402#L457-8 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 17401#L467-8 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 17400#is_transmit5_triggered_returnLabel#9 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 17399#L970-24 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 17398#L970-26 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 17397#L475-24 assume !(1 == ~t6_pc~0); 17395#L475-26 is_transmit6_triggered_~__retres1~6#1 := 0; 17394#L486-8 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 17393#is_transmit6_triggered_returnLabel#9 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 17392#L978-24 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 17391#L978-26 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 17390#L494-24 assume !(1 == ~t7_pc~0); 17388#L494-26 is_transmit7_triggered_~__retres1~7#1 := 0; 17387#L505-8 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 17386#is_transmit7_triggered_returnLabel#9 activate_threads_#t~ret20#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 17385#L986-24 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 17384#L986-26 havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 17383#L837-3 assume 1 == ~M_E~0;~M_E~0 := 2; 17382#L837-5 assume !(1 == ~T1_E~0); 17381#L842-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 16593#L847-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 17380#L852-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 17379#L857-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 17378#L862-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 16942#L867-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 16565#L872-3 assume 1 == ~E_1~0;~E_1~0 := 2; 16566#L877-3 assume !(1 == ~E_2~0); 16645#L882-3 assume 1 == ~E_3~0;~E_3~0 := 2; 16697#L887-3 assume 1 == ~E_4~0;~E_4~0 := 2; 16321#L892-3 assume 1 == ~E_5~0;~E_5~0 := 2; 16322#L897-3 assume 1 == ~E_6~0;~E_6~0 := 2; 16862#L902-3 assume !(1 == ~E_7~0); 16487#L907-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 16488#L569-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 16137#L611-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 16422#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret22#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret22#1;havoc start_simulation_#t~ret22#1; 16423#L1167 assume !(0 == start_simulation_~tmp~3#1); 16543#L1167-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret21#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 16544#L569-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 16343#L611-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 16982#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret21#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret21#1;havoc stop_simulation_#t~ret21#1; 16981#L1122 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 16979#L1129 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 16977#stop_simulation_returnLabel#1 start_simulation_#t~ret23#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret21#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret23#1;havoc start_simulation_#t~ret23#1; 16961#L1180 assume !(0 != start_simulation_~tmp___0~1#1); 16538#L1148-2 [2023-11-12 02:09:33,607 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-12 02:09:33,608 INFO L85 PathProgramCache]: Analyzing trace with hash 1307665866, now seen corresponding path program 1 times [2023-11-12 02:09:33,608 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-12 02:09:33,608 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [353580560] [2023-11-12 02:09:33,608 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-12 02:09:33,608 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-12 02:09:33,620 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-12 02:09:33,667 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-12 02:09:33,667 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-12 02:09:33,667 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [353580560] [2023-11-12 02:09:33,668 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [353580560] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-12 02:09:33,668 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-12 02:09:33,668 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2023-11-12 02:09:33,668 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [455404054] [2023-11-12 02:09:33,668 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-12 02:09:33,669 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-12 02:09:33,669 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-12 02:09:33,669 INFO L85 PathProgramCache]: Analyzing trace with hash -482217473, now seen corresponding path program 1 times [2023-11-12 02:09:33,670 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-12 02:09:33,670 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1615700414] [2023-11-12 02:09:33,670 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-12 02:09:33,670 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-12 02:09:33,683 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-12 02:09:33,718 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-12 02:09:33,719 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-12 02:09:33,719 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1615700414] [2023-11-12 02:09:33,719 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1615700414] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-12 02:09:33,719 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-12 02:09:33,719 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-12 02:09:33,720 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1770730596] [2023-11-12 02:09:33,720 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-12 02:09:33,720 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-12 02:09:33,720 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-12 02:09:33,721 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-12 02:09:33,721 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-12 02:09:33,721 INFO L87 Difference]: Start difference. First operand 1464 states and 2138 transitions. cyclomatic complexity: 676 Second operand has 3 states, 3 states have (on average 31.0) internal successors, (93), 2 states have internal predecessors, (93), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-12 02:09:33,866 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-12 02:09:33,867 INFO L93 Difference]: Finished difference Result 2791 states and 4036 transitions. [2023-11-12 02:09:33,867 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2791 states and 4036 transitions. [2023-11-12 02:09:33,891 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 2676 [2023-11-12 02:09:33,919 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2791 states to 2791 states and 4036 transitions. [2023-11-12 02:09:33,919 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2791 [2023-11-12 02:09:33,922 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2791 [2023-11-12 02:09:33,923 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2791 states and 4036 transitions. [2023-11-12 02:09:33,927 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-12 02:09:33,927 INFO L218 hiAutomatonCegarLoop]: Abstraction has 2791 states and 4036 transitions. [2023-11-12 02:09:33,932 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2791 states and 4036 transitions. [2023-11-12 02:09:33,984 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2791 to 2677. [2023-11-12 02:09:33,991 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2677 states, 2677 states have (on average 1.4493836384011953) internal successors, (3880), 2676 states have internal predecessors, (3880), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-12 02:09:34,003 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2677 states to 2677 states and 3880 transitions. [2023-11-12 02:09:34,003 INFO L240 hiAutomatonCegarLoop]: Abstraction has 2677 states and 3880 transitions. [2023-11-12 02:09:34,004 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-12 02:09:34,005 INFO L428 stractBuchiCegarLoop]: Abstraction has 2677 states and 3880 transitions. [2023-11-12 02:09:34,005 INFO L335 stractBuchiCegarLoop]: ======== Iteration 11 ============ [2023-11-12 02:09:34,005 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2677 states and 3880 transitions. [2023-11-12 02:09:34,020 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 2562 [2023-11-12 02:09:34,020 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-12 02:09:34,021 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-12 02:09:34,022 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-12 02:09:34,023 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-12 02:09:34,023 INFO L748 eck$LassoCheckResult]: Stem: 20589#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2; 20590#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~9#1;havoc main_~__retres1~9#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 21199#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret22#1, start_simulation_#t~ret23#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 21200#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 21244#L521 assume 1 == ~m_i~0;~m_st~0 := 0; 21229#L521-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 21230#L526-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 20742#L531-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 20743#L536-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 20815#L541-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 20651#L546-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 20652#L551-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 20619#L556-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 20620#L754 assume !(0 == ~M_E~0); 21261#L754-2 assume !(0 == ~T1_E~0); 21155#L759-1 assume !(0 == ~T2_E~0); 21002#L764-1 assume !(0 == ~T3_E~0); 20958#L769-1 assume !(0 == ~T4_E~0); 20959#L774-1 assume !(0 == ~T5_E~0); 21003#L779-1 assume !(0 == ~T6_E~0); 21164#L784-1 assume !(0 == ~T7_E~0); 20955#L789-1 assume !(0 == ~E_1~0); 20956#L794-1 assume !(0 == ~E_2~0); 21057#L799-1 assume !(0 == ~E_3~0); 20967#L804-1 assume !(0 == ~E_4~0); 20968#L809-1 assume !(0 == ~E_5~0); 20996#L814-1 assume !(0 == ~E_6~0); 20392#L819-1 assume !(0 == ~E_7~0); 20393#L824-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 20649#L361 assume !(1 == ~m_pc~0); 20650#L361-2 is_master_triggered_~__retres1~0#1 := 0; 21193#L372 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 21142#is_master_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 21143#L930 assume !(0 != activate_threads_~tmp~1#1); 20862#L930-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 20643#L380 assume !(1 == ~t1_pc~0); 20644#L380-2 is_transmit1_triggered_~__retres1~1#1 := 0; 21067#L391 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 20414#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 20415#L938 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 21092#L938-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 21068#L399 assume 1 == ~t2_pc~0; 21069#L400 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 20561#L410 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 20724#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 20717#L946 assume !(0 != activate_threads_~tmp___1~0#1); 20718#L946-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 20400#L418 assume !(1 == ~t3_pc~0); 20379#L418-2 is_transmit3_triggered_~__retres1~3#1 := 0; 20380#L429 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 20390#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 20391#L954 assume !(0 != activate_threads_~tmp___2~0#1); 20985#L954-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 20986#L437 assume 1 == ~t4_pc~0; 21265#L438 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 21137#L448 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 20473#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 20474#L962 assume !(0 != activate_threads_~tmp___3~0#1); 20772#L962-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 21114#L456 assume !(1 == ~t5_pc~0); 20575#L456-2 is_transmit5_triggered_~__retres1~5#1 := 0; 20574#L467 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 21146#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 21041#L970 assume !(0 != activate_threads_~tmp___4~0#1); 21042#L970-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 20467#L475 assume 1 == ~t6_pc~0; 20468#L476 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 20509#L486 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 20510#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 20710#L978 assume !(0 != activate_threads_~tmp___5~0#1); 20974#L978-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 20975#L494 assume !(1 == ~t7_pc~0); 20694#L494-2 is_transmit7_triggered_~__retres1~7#1 := 0; 20695#L505 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 20927#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 21004#L986 assume !(0 != activate_threads_~tmp___6~0#1); 21005#L986-2 havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 21253#L837 assume !(1 == ~M_E~0); 21198#L837-2 assume !(1 == ~T1_E~0); 21063#L842-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 20779#L847-1 assume !(1 == ~T3_E~0); 20780#L852-1 assume !(1 == ~T4_E~0); 20850#L857-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 20730#L862-1 assume !(1 == ~T6_E~0); 20731#L867-1 assume !(1 == ~T7_E~0); 20738#L872-1 assume !(1 == ~E_1~0); 20814#L877-1 assume !(1 == ~E_2~0); 21020#L882-1 assume !(1 == ~E_3~0); 21205#L887-1 assume !(1 == ~E_4~0); 22533#L892-1 assume !(1 == ~E_5~0); 21250#L897-1 assume 1 == ~E_6~0;~E_6~0 := 2; 20755#L902-1 assume !(1 == ~E_7~0); 20756#L907-1 assume { :end_inline_reset_delta_events } true; 20618#L1148-2 [2023-11-12 02:09:34,024 INFO L750 eck$LassoCheckResult]: Loop: 20618#L1148-2 assume !false; 22518#L1149 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 21054#L729-1 assume !false; 21055#L622 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 20591#L569 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 20592#L611 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 20744#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 20745#L626 assume !(0 != eval_~tmp~0#1); 21087#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 21088#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 20665#L754-3 assume 0 == ~M_E~0;~M_E~0 := 1; 20406#L754-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 20407#L759-3 assume !(0 == ~T2_E~0); 22507#L764-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 22980#L769-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 22979#L774-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 22978#L779-3 assume !(0 == ~T6_E~0); 22977#L784-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 22976#L789-3 assume 0 == ~E_1~0;~E_1~0 := 1; 22975#L794-3 assume 0 == ~E_2~0;~E_2~0 := 1; 22974#L799-3 assume !(0 == ~E_3~0); 22973#L804-3 assume 0 == ~E_4~0;~E_4~0 := 1; 22972#L809-3 assume 0 == ~E_5~0;~E_5~0 := 1; 22971#L814-3 assume 0 == ~E_6~0;~E_6~0 := 1; 22970#L819-3 assume !(0 == ~E_7~0); 22969#L824-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 22968#L361-24 assume !(1 == ~m_pc~0); 22967#L361-26 is_master_triggered_~__retres1~0#1 := 0; 22966#L372-8 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 22965#is_master_triggered_returnLabel#9 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 22964#L930-24 assume !(0 != activate_threads_~tmp~1#1); 22963#L930-26 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 22962#L380-24 assume 1 == ~t1_pc~0; 22960#L381-8 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 22959#L391-8 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 22958#is_transmit1_triggered_returnLabel#9 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 22957#L938-24 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 22956#L938-26 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 22955#L399-24 assume 1 == ~t2_pc~0; 22953#L400-8 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 22952#L410-8 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 22951#is_transmit2_triggered_returnLabel#9 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 22950#L946-24 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 22949#L946-26 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 21238#L418-24 assume !(1 == ~t3_pc~0); 20442#L418-26 is_transmit3_triggered_~__retres1~3#1 := 0; 20443#L429-8 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 22932#is_transmit3_triggered_returnLabel#9 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 22931#L954-24 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 22930#L954-26 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 22929#L437-24 assume 1 == ~t4_pc~0; 21133#L438-8 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 21135#L448-8 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 20848#is_transmit4_triggered_returnLabel#9 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 20552#L962-24 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 20553#L962-26 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 20973#L456-24 assume !(1 == ~t5_pc~0); 20945#L456-26 is_transmit5_triggered_~__retres1~5#1 := 0; 20944#L467-8 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 22917#is_transmit5_triggered_returnLabel#9 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 21202#L970-24 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 20863#L970-26 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 20864#L475-24 assume 1 == ~t6_pc~0; 20403#L476-8 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 20404#L486-8 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 20545#is_transmit6_triggered_returnLabel#9 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 20546#L978-24 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 20969#L978-26 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 20917#L494-24 assume !(1 == ~t7_pc~0); 20736#L494-26 is_transmit7_triggered_~__retres1~7#1 := 0; 20715#L505-8 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 20716#is_transmit7_triggered_returnLabel#9 activate_threads_#t~ret20#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 20655#L986-24 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 20656#L986-26 havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 21132#L837-3 assume 1 == ~M_E~0;~M_E~0 := 2; 21160#L837-5 assume !(1 == ~T1_E~0); 20856#L842-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 20857#L847-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 21037#L852-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 21038#L857-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 21282#L862-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 21267#L867-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 21268#L872-3 assume 1 == ~E_1~0;~E_1~0 := 2; 20913#L877-3 assume !(1 == ~E_2~0); 20914#L882-3 assume 1 == ~E_3~0;~E_3~0 := 2; 20980#L887-3 assume 1 == ~E_4~0;~E_4~0 := 2; 20583#L892-3 assume 1 == ~E_5~0;~E_5~0 := 2; 20584#L897-3 assume 1 == ~E_6~0;~E_6~0 := 2; 21159#L902-3 assume !(1 == ~E_7~0); 20749#L907-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 20750#L569-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 22868#L611-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 22866#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret22#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret22#1;havoc start_simulation_#t~ret22#1; 22865#L1167 assume !(0 == start_simulation_~tmp~3#1); 22863#L1167-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret21#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 21281#L569-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 20605#L611-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 20412#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret21#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret21#1;havoc stop_simulation_#t~ret21#1; 20413#L1122 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 20785#L1129 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 20786#stop_simulation_returnLabel#1 start_simulation_#t~ret23#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret21#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret23#1;havoc start_simulation_#t~ret23#1; 20617#L1180 assume !(0 != start_simulation_~tmp___0~1#1); 20618#L1148-2 [2023-11-12 02:09:34,024 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-12 02:09:34,024 INFO L85 PathProgramCache]: Analyzing trace with hash 2012584553, now seen corresponding path program 1 times [2023-11-12 02:09:34,025 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-12 02:09:34,025 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [61374099] [2023-11-12 02:09:34,025 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-12 02:09:34,025 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-12 02:09:34,037 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-12 02:09:34,095 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-12 02:09:34,095 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-12 02:09:34,096 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [61374099] [2023-11-12 02:09:34,096 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [61374099] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-12 02:09:34,096 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-12 02:09:34,096 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2023-11-12 02:09:34,096 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [536261220] [2023-11-12 02:09:34,097 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-12 02:09:34,097 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-12 02:09:34,097 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-12 02:09:34,098 INFO L85 PathProgramCache]: Analyzing trace with hash 1038873855, now seen corresponding path program 1 times [2023-11-12 02:09:34,098 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-12 02:09:34,098 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1989996508] [2023-11-12 02:09:34,098 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-12 02:09:34,099 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-12 02:09:34,112 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-12 02:09:34,150 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-12 02:09:34,151 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-12 02:09:34,151 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1989996508] [2023-11-12 02:09:34,151 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1989996508] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-12 02:09:34,151 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-12 02:09:34,152 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-12 02:09:34,152 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1683255409] [2023-11-12 02:09:34,152 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-12 02:09:34,153 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-12 02:09:34,153 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-12 02:09:34,153 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2023-11-12 02:09:34,153 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2023-11-12 02:09:34,154 INFO L87 Difference]: Start difference. First operand 2677 states and 3880 transitions. cyclomatic complexity: 1207 Second operand has 5 states, 5 states have (on average 18.6) internal successors, (93), 5 states have internal predecessors, (93), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-12 02:09:34,503 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-12 02:09:34,503 INFO L93 Difference]: Finished difference Result 6719 states and 9605 transitions. [2023-11-12 02:09:34,504 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 6719 states and 9605 transitions. [2023-11-12 02:09:34,615 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 6484 [2023-11-12 02:09:34,676 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 6719 states to 6719 states and 9605 transitions. [2023-11-12 02:09:34,676 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 6719 [2023-11-12 02:09:34,683 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 6719 [2023-11-12 02:09:34,684 INFO L73 IsDeterministic]: Start isDeterministic. Operand 6719 states and 9605 transitions. [2023-11-12 02:09:34,694 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-12 02:09:34,694 INFO L218 hiAutomatonCegarLoop]: Abstraction has 6719 states and 9605 transitions. [2023-11-12 02:09:34,703 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 6719 states and 9605 transitions. [2023-11-12 02:09:34,769 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 6719 to 2782. [2023-11-12 02:09:34,777 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2782 states, 2782 states have (on average 1.4324227174694464) internal successors, (3985), 2781 states have internal predecessors, (3985), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-12 02:09:34,787 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2782 states to 2782 states and 3985 transitions. [2023-11-12 02:09:34,787 INFO L240 hiAutomatonCegarLoop]: Abstraction has 2782 states and 3985 transitions. [2023-11-12 02:09:34,788 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2023-11-12 02:09:34,788 INFO L428 stractBuchiCegarLoop]: Abstraction has 2782 states and 3985 transitions. [2023-11-12 02:09:34,788 INFO L335 stractBuchiCegarLoop]: ======== Iteration 12 ============ [2023-11-12 02:09:34,788 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2782 states and 3985 transitions. [2023-11-12 02:09:34,804 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 2664 [2023-11-12 02:09:34,804 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-12 02:09:34,804 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-12 02:09:34,806 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-12 02:09:34,806 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-12 02:09:34,806 INFO L748 eck$LassoCheckResult]: Stem: 29998#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2; 29999#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~9#1;havoc main_~__retres1~9#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 30585#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret22#1, start_simulation_#t~ret23#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 30586#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 30632#L521 assume 1 == ~m_i~0;~m_st~0 := 0; 30615#L521-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 30616#L526-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 30153#L531-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 30154#L536-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 30226#L541-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 30060#L546-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 30061#L551-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 30028#L556-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 30029#L754 assume !(0 == ~M_E~0); 30651#L754-2 assume !(0 == ~T1_E~0); 30541#L759-1 assume !(0 == ~T2_E~0); 30402#L764-1 assume !(0 == ~T3_E~0); 30358#L769-1 assume !(0 == ~T4_E~0); 30359#L774-1 assume !(0 == ~T5_E~0); 30403#L779-1 assume !(0 == ~T6_E~0); 30549#L784-1 assume !(0 == ~T7_E~0); 30355#L789-1 assume !(0 == ~E_1~0); 30356#L794-1 assume !(0 == ~E_2~0); 30449#L799-1 assume !(0 == ~E_3~0); 30367#L804-1 assume !(0 == ~E_4~0); 30368#L809-1 assume !(0 == ~E_5~0); 30397#L814-1 assume !(0 == ~E_6~0); 29801#L819-1 assume !(0 == ~E_7~0); 29802#L824-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 30058#L361 assume !(1 == ~m_pc~0); 30059#L361-2 is_master_triggered_~__retres1~0#1 := 0; 30578#L372 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 30528#is_master_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 30529#L930 assume !(0 != activate_threads_~tmp~1#1); 30271#L930-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 30052#L380 assume !(1 == ~t1_pc~0); 30053#L380-2 is_transmit1_triggered_~__retres1~1#1 := 0; 30629#L391 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 30630#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 30670#L938 assume !(0 != activate_threads_~tmp___0~0#1); 30482#L938-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 30461#L399 assume 1 == ~t2_pc~0; 30462#L400 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 29970#L410 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 30132#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 30125#L946 assume !(0 != activate_threads_~tmp___1~0#1); 30126#L946-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 29809#L418 assume !(1 == ~t3_pc~0); 29788#L418-2 is_transmit3_triggered_~__retres1~3#1 := 0; 29789#L429 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 29799#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 29800#L954 assume !(0 != activate_threads_~tmp___2~0#1); 30386#L954-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 30387#L437 assume 1 == ~t4_pc~0; 30652#L438 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 30521#L448 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 29882#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 29883#L962 assume !(0 != activate_threads_~tmp___3~0#1); 30182#L962-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 30502#L456 assume !(1 == ~t5_pc~0); 29984#L456-2 is_transmit5_triggered_~__retres1~5#1 := 0; 29983#L467 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 30532#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 30435#L970 assume !(0 != activate_threads_~tmp___4~0#1); 30436#L970-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 29876#L475 assume 1 == ~t6_pc~0; 29877#L476 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 29918#L486 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 29919#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 30118#L978 assume !(0 != activate_threads_~tmp___5~0#1); 30373#L978-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 30374#L494 assume !(1 == ~t7_pc~0); 30102#L494-2 is_transmit7_triggered_~__retres1~7#1 := 0; 30103#L505 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 30329#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 30404#L986 assume !(0 != activate_threads_~tmp___6~0#1); 30405#L986-2 havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 30641#L837 assume !(1 == ~M_E~0); 30584#L837-2 assume !(1 == ~T1_E~0); 30456#L842-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 30457#L847-1 assume !(1 == ~T3_E~0); 30260#L852-1 assume !(1 == ~T4_E~0); 30261#L857-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 30138#L862-1 assume !(1 == ~T6_E~0); 30139#L867-1 assume !(1 == ~T7_E~0); 30147#L872-1 assume !(1 == ~E_1~0); 30225#L877-1 assume !(1 == ~E_2~0); 30418#L882-1 assume !(1 == ~E_3~0); 31762#L887-1 assume !(1 == ~E_4~0); 31760#L892-1 assume !(1 == ~E_5~0); 31758#L897-1 assume 1 == ~E_6~0;~E_6~0 := 2; 31756#L902-1 assume !(1 == ~E_7~0); 31738#L907-1 assume { :end_inline_reset_delta_events } true; 31728#L1148-2 [2023-11-12 02:09:34,807 INFO L750 eck$LassoCheckResult]: Loop: 31728#L1148-2 assume !false; 31723#L1149 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 31721#L729-1 assume !false; 31720#L622 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 31716#L569 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 30739#L611 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 30740#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 30727#L626 assume !(0 != eval_~tmp~0#1); 30728#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 32504#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 32503#L754-3 assume 0 == ~M_E~0;~M_E~0 := 1; 32502#L754-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 32501#L759-3 assume !(0 == ~T2_E~0); 32500#L764-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 32499#L769-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 32498#L774-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 32497#L779-3 assume !(0 == ~T6_E~0); 32496#L784-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 32495#L789-3 assume 0 == ~E_1~0;~E_1~0 := 1; 32494#L794-3 assume 0 == ~E_2~0;~E_2~0 := 1; 32493#L799-3 assume !(0 == ~E_3~0); 32492#L804-3 assume 0 == ~E_4~0;~E_4~0 := 1; 32491#L809-3 assume 0 == ~E_5~0;~E_5~0 := 1; 32490#L814-3 assume 0 == ~E_6~0;~E_6~0 := 1; 32489#L819-3 assume !(0 == ~E_7~0); 32488#L824-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 32485#L361-24 assume !(1 == ~m_pc~0); 32484#L361-26 is_master_triggered_~__retres1~0#1 := 0; 32483#L372-8 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 32482#is_master_triggered_returnLabel#9 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 32481#L930-24 assume !(0 != activate_threads_~tmp~1#1); 32480#L930-26 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 30363#L380-24 assume 1 == ~t1_pc~0; 30364#L381-8 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 32478#L391-8 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 32476#is_transmit1_triggered_returnLabel#9 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 32474#L938-24 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 32472#L938-26 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 32470#L399-24 assume 1 == ~t2_pc~0; 32467#L400-8 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 32465#L410-8 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 32464#is_transmit2_triggered_returnLabel#9 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 32463#L946-24 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 30067#L946-26 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 30068#L418-24 assume 1 == ~t3_pc~0; 30568#L419-8 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 29852#L429-8 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 30144#is_transmit3_triggered_returnLabel#9 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 29976#L954-24 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 29977#L954-26 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 30439#L437-24 assume 1 == ~t4_pc~0; 30517#L438-8 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 30519#L448-8 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 30257#is_transmit4_triggered_returnLabel#9 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 29961#L962-24 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 29962#L962-26 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 30372#L456-24 assume 1 == ~t5_pc~0; 30343#L457-8 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 30322#L467-8 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 30323#is_transmit5_triggered_returnLabel#9 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 30561#L970-24 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 30272#L970-26 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 30273#L475-24 assume 1 == ~t6_pc~0; 29812#L476-8 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 29813#L486-8 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 29954#is_transmit6_triggered_returnLabel#9 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 29955#L978-24 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 29794#L978-26 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 29795#L494-24 assume !(1 == ~t7_pc~0); 30145#L494-26 is_transmit7_triggered_~__retres1~7#1 := 0; 30123#L505-8 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 30124#is_transmit7_triggered_returnLabel#9 activate_threads_#t~ret20#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 30064#L986-24 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 30065#L986-26 havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 30516#L837-3 assume 1 == ~M_E~0;~M_E~0 := 2; 30546#L837-5 assume !(1 == ~T1_E~0); 30267#L842-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 30268#L847-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 30434#L852-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 30326#L857-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 30327#L862-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 30657#L867-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 30239#L872-3 assume 1 == ~E_1~0;~E_1~0 := 2; 30240#L877-3 assume !(1 == ~E_2~0); 30321#L882-3 assume 1 == ~E_3~0;~E_3~0 := 2; 30377#L887-3 assume 1 == ~E_4~0;~E_4~0 := 2; 29992#L892-3 assume 1 == ~E_5~0;~E_5~0 := 2; 29993#L897-3 assume 1 == ~E_6~0;~E_6~0 := 2; 30545#L902-3 assume !(1 == ~E_7~0); 30159#L907-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 30160#L569-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 29808#L611-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 30090#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret22#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret22#1;havoc start_simulation_#t~ret22#1; 30091#L1167 assume !(0 == start_simulation_~tmp~3#1); 30612#L1167-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret21#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 31818#L569-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 31755#L611-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 31751#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret21#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret21#1;havoc stop_simulation_#t~ret21#1; 31749#L1122 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 31747#L1129 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 31745#stop_simulation_returnLabel#1 start_simulation_#t~ret23#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret21#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret23#1;havoc start_simulation_#t~ret23#1; 31737#L1180 assume !(0 != start_simulation_~tmp___0~1#1); 31728#L1148-2 [2023-11-12 02:09:34,807 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-12 02:09:34,808 INFO L85 PathProgramCache]: Analyzing trace with hash -1406363737, now seen corresponding path program 1 times [2023-11-12 02:09:34,808 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-12 02:09:34,808 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1447422420] [2023-11-12 02:09:34,808 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-12 02:09:34,808 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-12 02:09:34,820 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-12 02:09:34,877 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-12 02:09:34,877 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-12 02:09:34,878 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1447422420] [2023-11-12 02:09:34,878 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1447422420] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-12 02:09:34,878 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-12 02:09:34,878 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-12 02:09:34,879 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1526762149] [2023-11-12 02:09:34,879 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-12 02:09:34,879 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-12 02:09:34,880 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-12 02:09:34,880 INFO L85 PathProgramCache]: Analyzing trace with hash -806441279, now seen corresponding path program 1 times [2023-11-12 02:09:34,880 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-12 02:09:34,880 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [476479487] [2023-11-12 02:09:34,880 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-12 02:09:34,881 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-12 02:09:34,894 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-12 02:09:34,930 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-12 02:09:34,930 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-12 02:09:34,930 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [476479487] [2023-11-12 02:09:34,930 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [476479487] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-12 02:09:34,931 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-12 02:09:34,931 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-12 02:09:34,931 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [771800100] [2023-11-12 02:09:34,931 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-12 02:09:34,932 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-12 02:09:34,932 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-12 02:09:34,932 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2023-11-12 02:09:34,932 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2023-11-12 02:09:34,933 INFO L87 Difference]: Start difference. First operand 2782 states and 3985 transitions. cyclomatic complexity: 1207 Second operand has 4 states, 4 states have (on average 23.25) internal successors, (93), 3 states have internal predecessors, (93), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-12 02:09:35,213 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-12 02:09:35,213 INFO L93 Difference]: Finished difference Result 6579 states and 9329 transitions. [2023-11-12 02:09:35,214 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 6579 states and 9329 transitions. [2023-11-12 02:09:35,326 INFO L131 ngComponentsAnalysis]: Automaton has 6 accepting balls. 6326 [2023-11-12 02:09:35,377 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 6579 states to 6579 states and 9329 transitions. [2023-11-12 02:09:35,377 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 6579 [2023-11-12 02:09:35,385 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 6579 [2023-11-12 02:09:35,385 INFO L73 IsDeterministic]: Start isDeterministic. Operand 6579 states and 9329 transitions. [2023-11-12 02:09:35,396 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-12 02:09:35,396 INFO L218 hiAutomatonCegarLoop]: Abstraction has 6579 states and 9329 transitions. [2023-11-12 02:09:35,405 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 6579 states and 9329 transitions. [2023-11-12 02:09:35,532 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 6579 to 5163. [2023-11-12 02:09:35,545 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 5163 states, 5163 states have (on average 1.4247530505520047) internal successors, (7356), 5162 states have internal predecessors, (7356), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-12 02:09:35,566 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 5163 states to 5163 states and 7356 transitions. [2023-11-12 02:09:35,567 INFO L240 hiAutomatonCegarLoop]: Abstraction has 5163 states and 7356 transitions. [2023-11-12 02:09:35,568 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2023-11-12 02:09:35,569 INFO L428 stractBuchiCegarLoop]: Abstraction has 5163 states and 7356 transitions. [2023-11-12 02:09:35,569 INFO L335 stractBuchiCegarLoop]: ======== Iteration 13 ============ [2023-11-12 02:09:35,570 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 5163 states and 7356 transitions. [2023-11-12 02:09:35,601 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 5044 [2023-11-12 02:09:35,601 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-12 02:09:35,602 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-12 02:09:35,604 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-12 02:09:35,604 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-12 02:09:35,605 INFO L748 eck$LassoCheckResult]: Stem: 39372#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2; 39373#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~9#1;havoc main_~__retres1~9#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 39936#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret22#1, start_simulation_#t~ret23#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 39937#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 39970#L521 assume 1 == ~m_i~0;~m_st~0 := 0; 39959#L521-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 39960#L526-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 39525#L531-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 39526#L536-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 39599#L541-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 39437#L546-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 39438#L551-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 39403#L556-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 39404#L754 assume !(0 == ~M_E~0); 39985#L754-2 assume !(0 == ~T1_E~0); 39898#L759-1 assume !(0 == ~T2_E~0); 39768#L764-1 assume !(0 == ~T3_E~0); 39732#L769-1 assume !(0 == ~T4_E~0); 39733#L774-1 assume !(0 == ~T5_E~0); 39769#L779-1 assume !(0 == ~T6_E~0); 39908#L784-1 assume !(0 == ~T7_E~0); 39729#L789-1 assume !(0 == ~E_1~0); 39730#L794-1 assume !(0 == ~E_2~0); 39814#L799-1 assume !(0 == ~E_3~0); 39739#L804-1 assume !(0 == ~E_4~0); 39740#L809-1 assume !(0 == ~E_5~0); 39763#L814-1 assume !(0 == ~E_6~0); 39176#L819-1 assume !(0 == ~E_7~0); 39177#L824-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 39433#L361 assume !(1 == ~m_pc~0); 39434#L361-2 is_master_triggered_~__retres1~0#1 := 0; 39932#L372 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 39886#is_master_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 39887#L930 assume !(0 != activate_threads_~tmp~1#1); 39645#L930-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 39427#L380 assume !(1 == ~t1_pc~0); 39428#L380-2 is_transmit1_triggered_~__retres1~1#1 := 0; 40006#L391 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 39194#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 39195#L938 assume !(0 != activate_threads_~tmp___0~0#1); 39845#L938-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 39827#L399 assume !(1 == ~t2_pc~0); 39343#L399-2 is_transmit2_triggered_~__retres1~2#1 := 0; 39344#L410 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 39506#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 39499#L946 assume !(0 != activate_threads_~tmp___1~0#1); 39500#L946-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 39180#L418 assume !(1 == ~t3_pc~0); 39159#L418-2 is_transmit3_triggered_~__retres1~3#1 := 0; 39160#L429 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 39170#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 39171#L954 assume !(0 != activate_threads_~tmp___2~0#1); 39752#L954-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 39753#L437 assume 1 == ~t4_pc~0; 39986#L438 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 39882#L448 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 39255#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 39256#L962 assume !(0 != activate_threads_~tmp___3~0#1); 39555#L962-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 39868#L456 assume !(1 == ~t5_pc~0); 39358#L456-2 is_transmit5_triggered_~__retres1~5#1 := 0; 39357#L467 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 39890#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 39803#L970 assume !(0 != activate_threads_~tmp___4~0#1); 39804#L970-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 39247#L475 assume 1 == ~t6_pc~0; 39248#L476 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 39290#L486 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 39291#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 39492#L978 assume !(0 != activate_threads_~tmp___5~0#1); 39744#L978-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 39745#L494 assume !(1 == ~t7_pc~0); 39476#L494-2 is_transmit7_triggered_~__retres1~7#1 := 0; 39477#L505 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 39700#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 39770#L986 assume !(0 != activate_threads_~tmp___6~0#1); 39771#L986-2 havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 39981#L837 assume !(1 == ~M_E~0); 39935#L837-2 assume !(1 == ~T1_E~0); 39822#L842-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 39823#L847-1 assume !(1 == ~T3_E~0); 39633#L852-1 assume !(1 == ~T4_E~0); 39634#L857-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 39512#L862-1 assume !(1 == ~T6_E~0); 39513#L867-1 assume !(1 == ~T7_E~0); 39597#L872-1 assume !(1 == ~E_1~0); 39598#L877-1 assume !(1 == ~E_2~0); 39942#L882-1 assume !(1 == ~E_3~0); 39943#L887-1 assume !(1 == ~E_4~0); 39841#L892-1 assume !(1 == ~E_5~0); 39842#L897-1 assume 1 == ~E_6~0;~E_6~0 := 2; 39539#L902-1 assume !(1 == ~E_7~0); 39540#L907-1 assume { :end_inline_reset_delta_events } true; 43615#L1148-2 [2023-11-12 02:09:35,605 INFO L750 eck$LassoCheckResult]: Loop: 43615#L1148-2 assume !false; 43609#L1149 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 43605#L729-1 assume !false; 43602#L622 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 43595#L569 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 43586#L611 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 43581#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 43575#L626 assume !(0 != eval_~tmp~0#1); 43576#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 44003#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 44000#L754-3 assume 0 == ~M_E~0;~M_E~0 := 1; 43998#L754-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 43996#L759-3 assume !(0 == ~T2_E~0); 43995#L764-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 43994#L769-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 43993#L774-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 43992#L779-3 assume !(0 == ~T6_E~0); 43991#L784-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 43990#L789-3 assume 0 == ~E_1~0;~E_1~0 := 1; 43989#L794-3 assume 0 == ~E_2~0;~E_2~0 := 1; 43985#L799-3 assume !(0 == ~E_3~0); 43984#L804-3 assume 0 == ~E_4~0;~E_4~0 := 1; 43983#L809-3 assume 0 == ~E_5~0;~E_5~0 := 1; 43982#L814-3 assume 0 == ~E_6~0;~E_6~0 := 1; 43981#L819-3 assume !(0 == ~E_7~0); 43980#L824-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 43979#L361-24 assume !(1 == ~m_pc~0); 43978#L361-26 is_master_triggered_~__retres1~0#1 := 0; 43977#L372-8 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 43976#is_master_triggered_returnLabel#9 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 43975#L930-24 assume !(0 != activate_threads_~tmp~1#1); 43974#L930-26 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 43973#L380-24 assume !(1 == ~t1_pc~0); 43969#L380-26 is_transmit1_triggered_~__retres1~1#1 := 0; 43968#L391-8 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 43967#is_transmit1_triggered_returnLabel#9 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 43965#L938-24 assume !(0 != activate_threads_~tmp___0~0#1); 43963#L938-26 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 43962#L399-24 assume !(1 == ~t2_pc~0); 41681#L399-26 is_transmit2_triggered_~__retres1~2#1 := 0; 43961#L410-8 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 43959#is_transmit2_triggered_returnLabel#9 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 43957#L946-24 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 43955#L946-26 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 43953#L418-24 assume 1 == ~t3_pc~0; 43950#L419-8 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 43948#L429-8 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 43944#is_transmit3_triggered_returnLabel#9 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 43942#L954-24 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 43940#L954-26 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 43938#L437-24 assume !(1 == ~t4_pc~0); 43934#L437-26 is_transmit4_triggered_~__retres1~4#1 := 0; 43932#L448-8 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 43930#is_transmit4_triggered_returnLabel#9 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 43929#L962-24 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 43927#L962-26 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 43925#L456-24 assume 1 == ~t5_pc~0; 43922#L457-8 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 43920#L467-8 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 43918#is_transmit5_triggered_returnLabel#9 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 43915#L970-24 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 43913#L970-26 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 43911#L475-24 assume !(1 == ~t6_pc~0); 43908#L475-26 is_transmit6_triggered_~__retres1~6#1 := 0; 43906#L486-8 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 43904#is_transmit6_triggered_returnLabel#9 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 43901#L978-24 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 43899#L978-26 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 43897#L494-24 assume !(1 == ~t7_pc~0); 43894#L494-26 is_transmit7_triggered_~__retres1~7#1 := 0; 43892#L505-8 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 43890#is_transmit7_triggered_returnLabel#9 activate_threads_#t~ret20#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 43887#L986-24 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 43885#L986-26 havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 43883#L837-3 assume 1 == ~M_E~0;~M_E~0 := 2; 43881#L837-5 assume !(1 == ~T1_E~0); 43879#L842-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 39641#L847-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 43875#L852-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 43873#L857-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 43871#L862-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 40000#L867-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 43868#L872-3 assume 1 == ~E_1~0;~E_1~0 := 2; 43865#L877-3 assume !(1 == ~E_2~0); 43863#L882-3 assume 1 == ~E_3~0;~E_3~0 := 2; 43861#L887-3 assume 1 == ~E_4~0;~E_4~0 := 2; 43859#L892-3 assume 1 == ~E_5~0;~E_5~0 := 2; 43857#L897-3 assume 1 == ~E_6~0;~E_6~0 := 2; 43855#L902-3 assume !(1 == ~E_7~0); 43853#L907-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 43716#L569-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 43710#L611-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 43708#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret22#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret22#1;havoc start_simulation_#t~ret22#1; 43683#L1167 assume !(0 == start_simulation_~tmp~3#1); 43680#L1167-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret21#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 43678#L569-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 43666#L611-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 43644#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret21#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret21#1;havoc stop_simulation_#t~ret21#1; 43640#L1122 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 43635#L1129 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 43630#stop_simulation_returnLabel#1 start_simulation_#t~ret23#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret21#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret23#1;havoc start_simulation_#t~ret23#1; 43624#L1180 assume !(0 != start_simulation_~tmp___0~1#1); 43615#L1148-2 [2023-11-12 02:09:35,606 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-12 02:09:35,606 INFO L85 PathProgramCache]: Analyzing trace with hash -2107931962, now seen corresponding path program 1 times [2023-11-12 02:09:35,606 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-12 02:09:35,607 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [709183451] [2023-11-12 02:09:35,607 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-12 02:09:35,607 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-12 02:09:35,621 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-12 02:09:35,675 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-12 02:09:35,676 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-12 02:09:35,676 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [709183451] [2023-11-12 02:09:35,676 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [709183451] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-12 02:09:35,676 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-12 02:09:35,677 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2023-11-12 02:09:35,677 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [358478680] [2023-11-12 02:09:35,677 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-12 02:09:35,678 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-12 02:09:35,679 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-12 02:09:35,679 INFO L85 PathProgramCache]: Analyzing trace with hash -228310597, now seen corresponding path program 1 times [2023-11-12 02:09:35,679 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-12 02:09:35,679 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2007510857] [2023-11-12 02:09:35,680 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-12 02:09:35,680 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-12 02:09:35,695 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-12 02:09:35,735 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-12 02:09:35,735 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-12 02:09:35,736 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2007510857] [2023-11-12 02:09:35,736 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2007510857] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-12 02:09:35,736 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-12 02:09:35,736 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-12 02:09:35,736 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1472812392] [2023-11-12 02:09:35,737 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-12 02:09:35,737 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-12 02:09:35,738 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-12 02:09:35,738 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-12 02:09:35,739 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-12 02:09:35,739 INFO L87 Difference]: Start difference. First operand 5163 states and 7356 transitions. cyclomatic complexity: 2197 Second operand has 3 states, 3 states have (on average 31.0) internal successors, (93), 2 states have internal predecessors, (93), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-12 02:09:35,868 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-12 02:09:35,868 INFO L93 Difference]: Finished difference Result 9666 states and 13705 transitions. [2023-11-12 02:09:35,868 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 9666 states and 13705 transitions. [2023-11-12 02:09:35,927 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 9528 [2023-11-12 02:09:36,083 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 9666 states to 9666 states and 13705 transitions. [2023-11-12 02:09:36,083 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 9666 [2023-11-12 02:09:36,092 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 9666 [2023-11-12 02:09:36,092 INFO L73 IsDeterministic]: Start isDeterministic. Operand 9666 states and 13705 transitions. [2023-11-12 02:09:36,104 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-12 02:09:36,104 INFO L218 hiAutomatonCegarLoop]: Abstraction has 9666 states and 13705 transitions. [2023-11-12 02:09:36,118 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 9666 states and 13705 transitions. [2023-11-12 02:09:36,279 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 9666 to 9650. [2023-11-12 02:09:36,307 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 9650 states, 9650 states have (on average 1.4185492227979275) internal successors, (13689), 9649 states have internal predecessors, (13689), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-12 02:09:36,345 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 9650 states to 9650 states and 13689 transitions. [2023-11-12 02:09:36,345 INFO L240 hiAutomatonCegarLoop]: Abstraction has 9650 states and 13689 transitions. [2023-11-12 02:09:36,345 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-12 02:09:36,346 INFO L428 stractBuchiCegarLoop]: Abstraction has 9650 states and 13689 transitions. [2023-11-12 02:09:36,347 INFO L335 stractBuchiCegarLoop]: ======== Iteration 14 ============ [2023-11-12 02:09:36,347 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 9650 states and 13689 transitions. [2023-11-12 02:09:36,395 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 9512 [2023-11-12 02:09:36,395 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-12 02:09:36,395 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-12 02:09:36,397 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-12 02:09:36,397 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-12 02:09:36,397 INFO L748 eck$LassoCheckResult]: Stem: 54210#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2; 54211#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~9#1;havoc main_~__retres1~9#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 54785#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret22#1, start_simulation_#t~ret23#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 54786#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 54826#L521 assume 1 == ~m_i~0;~m_st~0 := 0; 54811#L521-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 54812#L526-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 54364#L531-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 54365#L536-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 54434#L541-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 54276#L546-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 54277#L551-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 54241#L556-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 54242#L754 assume !(0 == ~M_E~0); 54843#L754-2 assume !(0 == ~T1_E~0); 54742#L759-1 assume !(0 == ~T2_E~0); 54604#L764-1 assume !(0 == ~T3_E~0); 54565#L769-1 assume !(0 == ~T4_E~0); 54566#L774-1 assume !(0 == ~T5_E~0); 54605#L779-1 assume !(0 == ~T6_E~0); 54750#L784-1 assume !(0 == ~T7_E~0); 54562#L789-1 assume !(0 == ~E_1~0); 54563#L794-1 assume !(0 == ~E_2~0); 54648#L799-1 assume !(0 == ~E_3~0); 54572#L804-1 assume !(0 == ~E_4~0); 54573#L809-1 assume !(0 == ~E_5~0); 54599#L814-1 assume !(0 == ~E_6~0); 54011#L819-1 assume !(0 == ~E_7~0); 54012#L824-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 54272#L361 assume !(1 == ~m_pc~0); 54273#L361-2 is_master_triggered_~__retres1~0#1 := 0; 54781#L372 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 54729#is_master_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 54730#L930 assume !(0 != activate_threads_~tmp~1#1); 54477#L930-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 54265#L380 assume !(1 == ~t1_pc~0); 54266#L380-2 is_transmit1_triggered_~__retres1~1#1 := 0; 54869#L391 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 54029#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 54030#L938 assume !(0 != activate_threads_~tmp___0~0#1); 54685#L938-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 54660#L399 assume !(1 == ~t2_pc~0); 54179#L399-2 is_transmit2_triggered_~__retres1~2#1 := 0; 54180#L410 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 54343#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 54336#L946 assume !(0 != activate_threads_~tmp___1~0#1); 54337#L946-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 54015#L418 assume !(1 == ~t3_pc~0); 53995#L418-2 is_transmit3_triggered_~__retres1~3#1 := 0; 53996#L429 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 54005#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 54006#L954 assume !(0 != activate_threads_~tmp___2~0#1); 54586#L954-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 54587#L437 assume !(1 == ~t4_pc~0); 54813#L437-2 is_transmit4_triggered_~__retres1~4#1 := 0; 54725#L448 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 54090#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 54091#L962 assume !(0 != activate_threads_~tmp___3~0#1); 54392#L962-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 54708#L456 assume !(1 == ~t5_pc~0); 54193#L456-2 is_transmit5_triggered_~__retres1~5#1 := 0; 54192#L467 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 54733#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 54636#L970 assume !(0 != activate_threads_~tmp___4~0#1); 54637#L970-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 54082#L475 assume 1 == ~t6_pc~0; 54083#L476 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 54125#L486 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 54126#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 54329#L978 assume !(0 != activate_threads_~tmp___5~0#1); 54577#L978-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 54578#L494 assume !(1 == ~t7_pc~0); 54313#L494-2 is_transmit7_triggered_~__retres1~7#1 := 0; 54314#L505 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 54533#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 54606#L986 assume !(0 != activate_threads_~tmp___6~0#1); 54607#L986-2 havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 54834#L837 assume !(1 == ~M_E~0); 54784#L837-2 assume !(1 == ~T1_E~0); 54655#L842-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 54656#L847-1 assume !(1 == ~T3_E~0); 62178#L852-1 assume !(1 == ~T4_E~0); 62176#L857-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 62174#L862-1 assume !(1 == ~T6_E~0); 54350#L867-1 assume !(1 == ~T7_E~0); 62171#L872-1 assume !(1 == ~E_1~0); 62168#L877-1 assume !(1 == ~E_2~0); 62166#L882-1 assume !(1 == ~E_3~0); 62164#L887-1 assume !(1 == ~E_4~0); 62162#L892-1 assume !(1 == ~E_5~0); 62160#L897-1 assume 1 == ~E_6~0;~E_6~0 := 2; 62158#L902-1 assume !(1 == ~E_7~0); 62155#L907-1 assume { :end_inline_reset_delta_events } true; 62152#L1148-2 [2023-11-12 02:09:36,398 INFO L750 eck$LassoCheckResult]: Loop: 62152#L1148-2 assume !false; 61819#L1149 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 61816#L729-1 assume !false; 61814#L622 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 61802#L569 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 61796#L611 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 61794#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 61793#L626 assume !(0 != eval_~tmp~0#1); 54681#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 54476#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 54288#L754-3 assume 0 == ~M_E~0;~M_E~0 := 1; 54021#L754-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 54022#L759-3 assume !(0 == ~T2_E~0); 54410#L764-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 54411#L769-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 54588#L774-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 54589#L779-3 assume !(0 == ~T6_E~0); 63564#L784-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 54873#L789-3 assume 0 == ~E_1~0;~E_1~0 := 1; 54007#L794-3 assume 0 == ~E_2~0;~E_2~0 := 1; 54008#L799-3 assume !(0 == ~E_3~0); 54063#L804-3 assume 0 == ~E_4~0;~E_4~0 := 1; 54295#L809-3 assume 0 == ~E_5~0;~E_5~0 := 1; 54059#L814-3 assume 0 == ~E_6~0;~E_6~0 := 1; 54060#L819-3 assume !(0 == ~E_7~0); 54716#L824-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 54429#L361-24 assume !(1 == ~m_pc~0); 54430#L361-26 is_master_triggered_~__retres1~0#1 := 0; 54518#L372-8 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 54112#is_master_triggered_returnLabel#9 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 54113#L930-24 assume !(0 != activate_threads_~tmp~1#1); 54771#L930-26 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 54569#L380-24 assume 1 == ~t1_pc~0; 54570#L381-8 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 54794#L391-8 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 63467#is_transmit1_triggered_returnLabel#9 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 63464#L938-24 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 54285#L938-26 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 62357#L399-24 assume !(1 == ~t2_pc~0); 62355#L399-26 is_transmit2_triggered_~__retres1~2#1 := 0; 62353#L410-8 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 62351#is_transmit2_triggered_returnLabel#9 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 62349#L946-24 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 62347#L946-26 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 62344#L418-24 assume 1 == ~t3_pc~0; 62341#L419-8 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 62339#L429-8 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 62337#is_transmit3_triggered_returnLabel#9 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 62335#L954-24 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 62333#L954-26 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 62331#L437-24 assume !(1 == ~t4_pc~0); 62329#L437-26 is_transmit4_triggered_~__retres1~4#1 := 0; 62327#L448-8 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 62325#is_transmit4_triggered_returnLabel#9 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 62323#L962-24 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 62321#L962-26 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 62318#L456-24 assume 1 == ~t5_pc~0; 62315#L457-8 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 62313#L467-8 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 62311#is_transmit5_triggered_returnLabel#9 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 62309#L970-24 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 62307#L970-26 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 62304#L475-24 assume !(1 == ~t6_pc~0); 62301#L475-26 is_transmit6_triggered_~__retres1~6#1 := 0; 62299#L486-8 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 62297#is_transmit6_triggered_returnLabel#9 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 62295#L978-24 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 62292#L978-26 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 62290#L494-24 assume !(1 == ~t7_pc~0); 62287#L494-26 is_transmit7_triggered_~__retres1~7#1 := 0; 62285#L505-8 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 62283#is_transmit7_triggered_returnLabel#9 activate_threads_#t~ret20#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 62281#L986-24 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 62279#L986-26 havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 62277#L837-3 assume 1 == ~M_E~0;~M_E~0 := 2; 62273#L837-5 assume !(1 == ~T1_E~0); 62271#L842-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 62267#L847-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 62265#L852-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 62262#L857-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 62260#L862-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 62257#L867-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 62255#L872-3 assume 1 == ~E_1~0;~E_1~0 := 2; 62253#L877-3 assume !(1 == ~E_2~0); 62251#L882-3 assume 1 == ~E_3~0;~E_3~0 := 2; 62249#L887-3 assume 1 == ~E_4~0;~E_4~0 := 2; 62247#L892-3 assume 1 == ~E_5~0;~E_5~0 := 2; 62245#L897-3 assume 1 == ~E_6~0;~E_6~0 := 2; 62244#L902-3 assume !(1 == ~E_7~0); 62243#L907-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 62236#L569-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 62230#L611-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 62228#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret22#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret22#1;havoc start_simulation_#t~ret22#1; 62225#L1167 assume !(0 == start_simulation_~tmp~3#1); 62220#L1167-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret21#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 62218#L569-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 62209#L611-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 62207#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret21#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret21#1;havoc stop_simulation_#t~ret21#1; 62204#L1122 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 62202#L1129 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 62200#stop_simulation_returnLabel#1 start_simulation_#t~ret23#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret21#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret23#1;havoc start_simulation_#t~ret23#1; 62154#L1180 assume !(0 != start_simulation_~tmp___0~1#1); 62152#L1148-2 [2023-11-12 02:09:36,398 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-12 02:09:36,399 INFO L85 PathProgramCache]: Analyzing trace with hash -1707940763, now seen corresponding path program 1 times [2023-11-12 02:09:36,399 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-12 02:09:36,399 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1661546903] [2023-11-12 02:09:36,400 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-12 02:09:36,400 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-12 02:09:36,414 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-12 02:09:36,466 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-12 02:09:36,466 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-12 02:09:36,467 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1661546903] [2023-11-12 02:09:36,468 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1661546903] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-12 02:09:36,468 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-12 02:09:36,468 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-12 02:09:36,468 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1680704096] [2023-11-12 02:09:36,468 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-12 02:09:36,470 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-12 02:09:36,471 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-12 02:09:36,471 INFO L85 PathProgramCache]: Analyzing trace with hash -403099618, now seen corresponding path program 1 times [2023-11-12 02:09:36,471 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-12 02:09:36,471 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [353945654] [2023-11-12 02:09:36,472 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-12 02:09:36,472 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-12 02:09:36,486 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-12 02:09:36,518 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-12 02:09:36,519 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-12 02:09:36,519 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [353945654] [2023-11-12 02:09:36,519 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [353945654] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-12 02:09:36,519 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-12 02:09:36,519 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-12 02:09:36,520 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1648253392] [2023-11-12 02:09:36,520 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-12 02:09:36,520 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-12 02:09:36,521 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-12 02:09:36,521 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2023-11-12 02:09:36,521 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2023-11-12 02:09:36,522 INFO L87 Difference]: Start difference. First operand 9650 states and 13689 transitions. cyclomatic complexity: 4047 Second operand has 4 states, 4 states have (on average 23.25) internal successors, (93), 3 states have internal predecessors, (93), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-12 02:09:36,898 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-12 02:09:36,898 INFO L93 Difference]: Finished difference Result 22749 states and 31990 transitions. [2023-11-12 02:09:36,898 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 22749 states and 31990 transitions. [2023-11-12 02:09:37,034 INFO L131 ngComponentsAnalysis]: Automaton has 12 accepting balls. 22052 [2023-11-12 02:09:37,128 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 22749 states to 22749 states and 31990 transitions. [2023-11-12 02:09:37,128 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 22749 [2023-11-12 02:09:37,153 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 22749 [2023-11-12 02:09:37,153 INFO L73 IsDeterministic]: Start isDeterministic. Operand 22749 states and 31990 transitions. [2023-11-12 02:09:37,285 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-12 02:09:37,285 INFO L218 hiAutomatonCegarLoop]: Abstraction has 22749 states and 31990 transitions. [2023-11-12 02:09:37,329 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 22749 states and 31990 transitions. [2023-11-12 02:09:37,775 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 22749 to 18081. [2023-11-12 02:09:37,808 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 18081 states, 18081 states have (on average 1.412643106022897) internal successors, (25542), 18080 states have internal predecessors, (25542), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-12 02:09:37,882 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 18081 states to 18081 states and 25542 transitions. [2023-11-12 02:09:37,882 INFO L240 hiAutomatonCegarLoop]: Abstraction has 18081 states and 25542 transitions. [2023-11-12 02:09:37,883 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2023-11-12 02:09:37,884 INFO L428 stractBuchiCegarLoop]: Abstraction has 18081 states and 25542 transitions. [2023-11-12 02:09:37,884 INFO L335 stractBuchiCegarLoop]: ======== Iteration 15 ============ [2023-11-12 02:09:37,884 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 18081 states and 25542 transitions. [2023-11-12 02:09:37,993 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 17920 [2023-11-12 02:09:37,993 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-12 02:09:37,993 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-12 02:09:37,996 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-12 02:09:37,997 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-12 02:09:37,997 INFO L748 eck$LassoCheckResult]: Stem: 86613#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2; 86614#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~9#1;havoc main_~__retres1~9#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 87255#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret22#1, start_simulation_#t~ret23#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 87256#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 87310#L521 assume 1 == ~m_i~0;~m_st~0 := 0; 87287#L521-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 87288#L526-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 86773#L531-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 86774#L536-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 86848#L541-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 86678#L546-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 86679#L551-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 86644#L556-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 86645#L754 assume !(0 == ~M_E~0); 87331#L754-2 assume !(0 == ~T1_E~0); 87209#L759-1 assume !(0 == ~T2_E~0); 87058#L764-1 assume !(0 == ~T3_E~0); 87006#L769-1 assume !(0 == ~T4_E~0); 87007#L774-1 assume !(0 == ~T5_E~0); 87059#L779-1 assume !(0 == ~T6_E~0); 87220#L784-1 assume !(0 == ~T7_E~0); 87002#L789-1 assume !(0 == ~E_1~0); 87003#L794-1 assume !(0 == ~E_2~0); 87112#L799-1 assume !(0 == ~E_3~0); 87015#L804-1 assume !(0 == ~E_4~0); 87016#L809-1 assume !(0 == ~E_5~0); 87052#L814-1 assume !(0 == ~E_6~0); 86421#L819-1 assume !(0 == ~E_7~0); 86422#L824-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 86674#L361 assume !(1 == ~m_pc~0); 86675#L361-2 is_master_triggered_~__retres1~0#1 := 0; 87249#L372 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 87196#is_master_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 87197#L930 assume !(0 != activate_threads_~tmp~1#1); 86902#L930-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 86668#L380 assume !(1 == ~t1_pc~0); 86669#L380-2 is_transmit1_triggered_~__retres1~1#1 := 0; 87367#L391 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 86439#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 86440#L938 assume !(0 != activate_threads_~tmp___0~0#1); 87148#L938-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 87125#L399 assume !(1 == ~t2_pc~0); 86584#L399-2 is_transmit2_triggered_~__retres1~2#1 := 0; 86585#L410 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 86751#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 86744#L946 assume !(0 != activate_threads_~tmp___1~0#1); 86745#L946-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 86425#L418 assume !(1 == ~t3_pc~0); 86404#L418-2 is_transmit3_triggered_~__retres1~3#1 := 0; 86405#L429 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 86415#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 86416#L954 assume !(0 != activate_threads_~tmp___2~0#1); 87036#L954-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 87037#L437 assume !(1 == ~t4_pc~0); 87289#L437-2 is_transmit4_triggered_~__retres1~4#1 := 0; 87191#L448 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 86498#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 86499#L962 assume !(0 != activate_threads_~tmp___3~0#1); 86803#L962-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 87174#L456 assume !(1 == ~t5_pc~0); 86599#L456-2 is_transmit5_triggered_~__retres1~5#1 := 0; 86598#L467 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 87200#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 87099#L970 assume !(0 != activate_threads_~tmp___4~0#1); 87100#L970-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 86491#L475 assume !(1 == ~t6_pc~0); 86492#L475-2 is_transmit6_triggered_~__retres1~6#1 := 0; 86533#L486 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 86534#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 86736#L978 assume !(0 != activate_threads_~tmp___5~0#1); 87023#L978-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 87024#L494 assume !(1 == ~t7_pc~0); 86720#L494-2 is_transmit7_triggered_~__retres1~7#1 := 0; 86721#L505 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 86970#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 87060#L986 assume !(0 != activate_threads_~tmp___6~0#1); 87061#L986-2 havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 87319#L837 assume !(1 == ~M_E~0); 87254#L837-2 assume !(1 == ~T1_E~0); 87119#L842-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 86810#L847-1 assume !(1 == ~T3_E~0); 86811#L852-1 assume !(1 == ~T4_E~0); 87374#L857-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 87375#L862-1 assume !(1 == ~T6_E~0); 86758#L867-1 assume !(1 == ~T7_E~0); 86769#L872-1 assume !(1 == ~E_1~0); 87077#L877-1 assume !(1 == ~E_2~0); 87078#L882-1 assume !(1 == ~E_3~0); 87342#L887-1 assume !(1 == ~E_4~0); 87343#L892-1 assume !(1 == ~E_5~0); 87315#L897-1 assume 1 == ~E_6~0;~E_6~0 := 2; 87316#L902-1 assume !(1 == ~E_7~0); 87167#L907-1 assume { :end_inline_reset_delta_events } true; 87168#L1148-2 [2023-11-12 02:09:37,998 INFO L750 eck$LassoCheckResult]: Loop: 87168#L1148-2 assume !false; 95662#L1149 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 95661#L729-1 assume !false; 95660#L622 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 95652#L569 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 95646#L611 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 95644#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 95641#L626 assume !(0 != eval_~tmp~0#1); 95642#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 99168#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 99167#L754-3 assume 0 == ~M_E~0;~M_E~0 := 1; 99166#L754-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 99165#L759-3 assume !(0 == ~T2_E~0); 99163#L764-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 99161#L769-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 99159#L774-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 99157#L779-3 assume !(0 == ~T6_E~0); 99155#L784-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 99153#L789-3 assume 0 == ~E_1~0;~E_1~0 := 1; 99151#L794-3 assume 0 == ~E_2~0;~E_2~0 := 1; 99149#L799-3 assume !(0 == ~E_3~0); 99147#L804-3 assume 0 == ~E_4~0;~E_4~0 := 1; 99145#L809-3 assume 0 == ~E_5~0;~E_5~0 := 1; 99143#L814-3 assume 0 == ~E_6~0;~E_6~0 := 1; 99141#L819-3 assume !(0 == ~E_7~0); 99139#L824-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 99137#L361-24 assume !(1 == ~m_pc~0); 99135#L361-26 is_master_triggered_~__retres1~0#1 := 0; 99133#L372-8 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 99131#is_master_triggered_returnLabel#9 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 99129#L930-24 assume !(0 != activate_threads_~tmp~1#1); 99127#L930-26 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 99125#L380-24 assume !(1 == ~t1_pc~0); 99121#L380-26 is_transmit1_triggered_~__retres1~1#1 := 0; 99119#L391-8 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 99117#is_transmit1_triggered_returnLabel#9 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 99113#L938-24 assume !(0 != activate_threads_~tmp___0~0#1); 99110#L938-26 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 95817#L399-24 assume !(1 == ~t2_pc~0); 95814#L399-26 is_transmit2_triggered_~__retres1~2#1 := 0; 95813#L410-8 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 95812#is_transmit2_triggered_returnLabel#9 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 95811#L946-24 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 95810#L946-26 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 95809#L418-24 assume 1 == ~t3_pc~0; 95799#L419-8 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 95797#L429-8 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 95795#is_transmit3_triggered_returnLabel#9 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 95792#L954-24 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 95791#L954-26 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 95789#L437-24 assume !(1 == ~t4_pc~0); 95785#L437-26 is_transmit4_triggered_~__retres1~4#1 := 0; 95781#L448-8 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 95777#is_transmit4_triggered_returnLabel#9 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 95773#L962-24 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 95770#L962-26 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 95767#L456-24 assume !(1 == ~t5_pc~0); 95765#L456-26 is_transmit5_triggered_~__retres1~5#1 := 0; 95761#L467-8 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 95759#is_transmit5_triggered_returnLabel#9 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 95757#L970-24 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 95755#L970-26 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 95753#L475-24 assume !(1 == ~t6_pc~0); 91631#L475-26 is_transmit6_triggered_~__retres1~6#1 := 0; 95750#L486-8 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 95748#is_transmit6_triggered_returnLabel#9 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 95744#L978-24 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 95742#L978-26 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 95739#L494-24 assume !(1 == ~t7_pc~0); 95735#L494-26 is_transmit7_triggered_~__retres1~7#1 := 0; 95732#L505-8 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 95729#is_transmit7_triggered_returnLabel#9 activate_threads_#t~ret20#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 95725#L986-24 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 95723#L986-26 havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 95721#L837-3 assume 1 == ~M_E~0;~M_E~0 := 2; 95719#L837-5 assume !(1 == ~T1_E~0); 95717#L842-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 94183#L847-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 95714#L852-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 95713#L857-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 95712#L862-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 94154#L867-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 95711#L872-3 assume 1 == ~E_1~0;~E_1~0 := 2; 95710#L877-3 assume !(1 == ~E_2~0); 95709#L882-3 assume 1 == ~E_3~0;~E_3~0 := 2; 95708#L887-3 assume 1 == ~E_4~0;~E_4~0 := 2; 95707#L892-3 assume 1 == ~E_5~0;~E_5~0 := 2; 95706#L897-3 assume 1 == ~E_6~0;~E_6~0 := 2; 95705#L902-3 assume !(1 == ~E_7~0); 95704#L907-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 95698#L569-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 95692#L611-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 95690#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret22#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret22#1;havoc start_simulation_#t~ret22#1; 95688#L1167 assume !(0 == start_simulation_~tmp~3#1); 95686#L1167-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret21#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 95684#L569-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 95676#L611-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 95675#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret21#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret21#1;havoc stop_simulation_#t~ret21#1; 95674#L1122 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 95672#L1129 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 95670#stop_simulation_returnLabel#1 start_simulation_#t~ret23#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret21#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret23#1;havoc start_simulation_#t~ret23#1; 95668#L1180 assume !(0 != start_simulation_~tmp___0~1#1); 87168#L1148-2 [2023-11-12 02:09:37,999 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-12 02:09:37,999 INFO L85 PathProgramCache]: Analyzing trace with hash -2016379772, now seen corresponding path program 1 times [2023-11-12 02:09:37,999 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-12 02:09:37,999 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [934636803] [2023-11-12 02:09:38,000 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-12 02:09:38,000 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-12 02:09:38,017 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-12 02:09:38,114 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-12 02:09:38,115 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-12 02:09:38,115 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [934636803] [2023-11-12 02:09:38,115 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [934636803] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-12 02:09:38,115 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-12 02:09:38,116 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2023-11-12 02:09:38,116 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [976001335] [2023-11-12 02:09:38,116 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-12 02:09:38,116 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-12 02:09:38,117 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-12 02:09:38,117 INFO L85 PathProgramCache]: Analyzing trace with hash -1536315366, now seen corresponding path program 1 times [2023-11-12 02:09:38,117 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-12 02:09:38,118 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [350899040] [2023-11-12 02:09:38,118 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-12 02:09:38,118 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-12 02:09:38,134 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-12 02:09:38,175 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-12 02:09:38,175 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-12 02:09:38,176 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [350899040] [2023-11-12 02:09:38,176 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [350899040] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-12 02:09:38,176 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-12 02:09:38,176 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-12 02:09:38,177 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1842681457] [2023-11-12 02:09:38,177 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-12 02:09:38,177 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-12 02:09:38,177 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-12 02:09:38,178 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-12 02:09:38,178 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-12 02:09:38,178 INFO L87 Difference]: Start difference. First operand 18081 states and 25542 transitions. cyclomatic complexity: 7469 Second operand has 3 states, 3 states have (on average 31.0) internal successors, (93), 2 states have internal predecessors, (93), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-12 02:09:38,420 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-12 02:09:38,420 INFO L93 Difference]: Finished difference Result 18077 states and 25453 transitions. [2023-11-12 02:09:38,421 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 18077 states and 25453 transitions. [2023-11-12 02:09:38,532 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 17920 [2023-11-12 02:09:38,616 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 18077 states to 18077 states and 25453 transitions. [2023-11-12 02:09:38,617 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 18077 [2023-11-12 02:09:38,638 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 18077 [2023-11-12 02:09:38,639 INFO L73 IsDeterministic]: Start isDeterministic. Operand 18077 states and 25453 transitions. [2023-11-12 02:09:38,661 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-12 02:09:38,661 INFO L218 hiAutomatonCegarLoop]: Abstraction has 18077 states and 25453 transitions. [2023-11-12 02:09:38,683 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 18077 states and 25453 transitions. [2023-11-12 02:09:38,941 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 18077 to 9084. [2023-11-12 02:09:38,957 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 9084 states, 9084 states have (on average 1.4078599735799207) internal successors, (12789), 9083 states have internal predecessors, (12789), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-12 02:09:38,988 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 9084 states to 9084 states and 12789 transitions. [2023-11-12 02:09:38,988 INFO L240 hiAutomatonCegarLoop]: Abstraction has 9084 states and 12789 transitions. [2023-11-12 02:09:38,989 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-12 02:09:38,989 INFO L428 stractBuchiCegarLoop]: Abstraction has 9084 states and 12789 transitions. [2023-11-12 02:09:38,990 INFO L335 stractBuchiCegarLoop]: ======== Iteration 16 ============ [2023-11-12 02:09:38,990 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 9084 states and 12789 transitions. [2023-11-12 02:09:39,029 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 8960 [2023-11-12 02:09:39,030 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-12 02:09:39,030 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-12 02:09:39,032 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-12 02:09:39,033 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-12 02:09:39,033 INFO L748 eck$LassoCheckResult]: Stem: 122782#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2; 122783#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~9#1;havoc main_~__retres1~9#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 123377#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret22#1, start_simulation_#t~ret23#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 123378#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 123415#L521 assume 1 == ~m_i~0;~m_st~0 := 0; 123399#L521-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 123400#L526-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 122937#L531-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 122938#L536-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 123009#L541-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 122846#L546-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 122847#L551-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 122814#L556-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 122815#L754 assume !(0 == ~M_E~0); 123429#L754-2 assume !(0 == ~T1_E~0); 123333#L759-1 assume !(0 == ~T2_E~0); 123191#L764-1 assume !(0 == ~T3_E~0); 123148#L769-1 assume !(0 == ~T4_E~0); 123149#L774-1 assume !(0 == ~T5_E~0); 123192#L779-1 assume !(0 == ~T6_E~0); 123342#L784-1 assume !(0 == ~T7_E~0); 123145#L789-1 assume !(0 == ~E_1~0); 123146#L794-1 assume !(0 == ~E_2~0); 123238#L799-1 assume !(0 == ~E_3~0); 123157#L804-1 assume !(0 == ~E_4~0); 123158#L809-1 assume !(0 == ~E_5~0); 123185#L814-1 assume !(0 == ~E_6~0); 122582#L819-1 assume !(0 == ~E_7~0); 122583#L824-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 122844#L361 assume !(1 == ~m_pc~0); 122845#L361-2 is_master_triggered_~__retres1~0#1 := 0; 123373#L372 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 123317#is_master_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 123318#L930 assume !(0 != activate_threads_~tmp~1#1); 123056#L930-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 122838#L380 assume !(1 == ~t1_pc~0); 122839#L380-2 is_transmit1_triggered_~__retres1~1#1 := 0; 123452#L391 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 122604#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 122605#L938 assume !(0 != activate_threads_~tmp___0~0#1); 123270#L938-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 123249#L399 assume !(1 == ~t2_pc~0); 122751#L399-2 is_transmit2_triggered_~__retres1~2#1 := 0; 122752#L410 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 122917#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 122910#L946 assume !(0 != activate_threads_~tmp___1~0#1); 122911#L946-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 122590#L418 assume !(1 == ~t3_pc~0); 122569#L418-2 is_transmit3_triggered_~__retres1~3#1 := 0; 122570#L429 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 122580#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 122581#L954 assume !(0 != activate_threads_~tmp___2~0#1); 123171#L954-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 123172#L437 assume !(1 == ~t4_pc~0); 123401#L437-2 is_transmit4_triggered_~__retres1~4#1 := 0; 123311#L448 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 122662#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 122663#L962 assume !(0 != activate_threads_~tmp___3~0#1); 122965#L962-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 123292#L456 assume !(1 == ~t5_pc~0); 122766#L456-2 is_transmit5_triggered_~__retres1~5#1 := 0; 122765#L467 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 123322#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 123223#L970 assume !(0 != activate_threads_~tmp___4~0#1); 123224#L970-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 122657#L475 assume !(1 == ~t6_pc~0); 122658#L475-2 is_transmit6_triggered_~__retres1~6#1 := 0; 122698#L486 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 122699#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 122903#L978 assume !(0 != activate_threads_~tmp___5~0#1); 123163#L978-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 123164#L494 assume !(1 == ~t7_pc~0); 122887#L494-2 is_transmit7_triggered_~__retres1~7#1 := 0; 122888#L505 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 123115#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 123193#L986 assume !(0 != activate_threads_~tmp___6~0#1); 123194#L986-2 havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 123421#L837 assume !(1 == ~M_E~0); 123376#L837-2 assume !(1 == ~T1_E~0); 123245#L842-1 assume !(1 == ~T2_E~0); 122974#L847-1 assume !(1 == ~T3_E~0); 122975#L852-1 assume !(1 == ~T4_E~0); 123046#L857-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 122923#L862-1 assume !(1 == ~T6_E~0); 122924#L867-1 assume !(1 == ~T7_E~0); 122933#L872-1 assume !(1 == ~E_1~0); 123008#L877-1 assume !(1 == ~E_2~0); 123208#L882-1 assume !(1 == ~E_3~0); 123382#L887-1 assume !(1 == ~E_4~0); 123264#L892-1 assume !(1 == ~E_5~0); 123265#L897-1 assume 1 == ~E_6~0;~E_6~0 := 2; 122948#L902-1 assume !(1 == ~E_7~0); 122949#L907-1 assume { :end_inline_reset_delta_events } true; 123291#L1148-2 [2023-11-12 02:09:39,034 INFO L750 eck$LassoCheckResult]: Loop: 123291#L1148-2 assume !false; 125210#L1149 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 125206#L729-1 assume !false; 125202#L622 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 125167#L569 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 125159#L611 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 125153#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 125148#L626 assume !(0 != eval_~tmp~0#1); 123266#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 123055#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 122860#L754-3 assume 0 == ~M_E~0;~M_E~0 := 1; 122596#L754-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 122597#L759-3 assume !(0 == ~T2_E~0); 122984#L764-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 122985#L769-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 123173#L774-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 122755#L779-3 assume !(0 == ~T6_E~0); 122591#L784-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 122592#L789-3 assume 0 == ~E_1~0;~E_1~0 := 1; 122586#L794-3 assume 0 == ~E_2~0;~E_2~0 := 1; 122587#L799-3 assume !(0 == ~E_3~0); 131592#L804-3 assume 0 == ~E_4~0;~E_4~0 := 1; 131588#L809-3 assume 0 == ~E_5~0;~E_5~0 := 1; 131586#L814-3 assume 0 == ~E_6~0;~E_6~0 := 1; 131584#L819-3 assume !(0 == ~E_7~0); 131582#L824-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 131579#L361-24 assume !(1 == ~m_pc~0); 131577#L361-26 is_master_triggered_~__retres1~0#1 := 0; 131515#L372-8 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 122685#is_master_triggered_returnLabel#9 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 122686#L930-24 assume !(0 != activate_threads_~tmp~1#1); 123362#L930-26 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 123385#L380-24 assume 1 == ~t1_pc~0; 131508#L381-8 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 131328#L391-8 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 131329#is_transmit1_triggered_returnLabel#9 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 131325#L938-24 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 122857#L938-26 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 125446#L399-24 assume !(1 == ~t2_pc~0); 125445#L399-26 is_transmit2_triggered_~__retres1~2#1 := 0; 125444#L410-8 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 125443#is_transmit2_triggered_returnLabel#9 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 125442#L946-24 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 125441#L946-26 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 125440#L418-24 assume !(1 == ~t3_pc~0); 125439#L418-26 is_transmit3_triggered_~__retres1~3#1 := 0; 125437#L429-8 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 125436#is_transmit3_triggered_returnLabel#9 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 125435#L954-24 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 125434#L954-26 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 125433#L437-24 assume !(1 == ~t4_pc~0); 125432#L437-26 is_transmit4_triggered_~__retres1~4#1 := 0; 125431#L448-8 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 125430#is_transmit4_triggered_returnLabel#9 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 125429#L962-24 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 125428#L962-26 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 125427#L456-24 assume 1 == ~t5_pc~0; 125425#L457-8 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 125424#L467-8 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 125422#is_transmit5_triggered_returnLabel#9 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 125420#L970-24 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 125418#L970-26 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 125416#L475-24 assume !(1 == ~t6_pc~0); 125245#L475-26 is_transmit6_triggered_~__retres1~6#1 := 0; 125413#L486-8 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 125411#is_transmit6_triggered_returnLabel#9 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 125408#L978-24 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 125406#L978-26 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 125404#L494-24 assume !(1 == ~t7_pc~0); 125401#L494-26 is_transmit7_triggered_~__retres1~7#1 := 0; 125399#L505-8 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 125397#is_transmit7_triggered_returnLabel#9 activate_threads_#t~ret20#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 125395#L986-24 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 125393#L986-26 havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 125391#L837-3 assume 1 == ~M_E~0;~M_E~0 := 2; 125389#L837-5 assume !(1 == ~T1_E~0); 125387#L842-3 assume !(1 == ~T2_E~0); 125385#L847-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 125382#L852-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 125380#L857-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 125378#L862-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 125376#L867-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 125374#L872-3 assume 1 == ~E_1~0;~E_1~0 := 2; 125372#L877-3 assume !(1 == ~E_2~0); 125371#L882-3 assume 1 == ~E_3~0;~E_3~0 := 2; 125369#L887-3 assume 1 == ~E_4~0;~E_4~0 := 2; 125367#L892-3 assume 1 == ~E_5~0;~E_5~0 := 2; 125365#L897-3 assume 1 == ~E_6~0;~E_6~0 := 2; 125363#L902-3 assume !(1 == ~E_7~0); 125361#L907-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 125318#L569-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 125310#L611-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 125305#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret22#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret22#1;havoc start_simulation_#t~ret22#1; 125264#L1167 assume !(0 == start_simulation_~tmp~3#1); 125261#L1167-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret21#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 125259#L569-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 125248#L611-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 125243#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret21#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret21#1;havoc stop_simulation_#t~ret21#1; 125239#L1122 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 125234#L1129 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 125228#stop_simulation_returnLabel#1 start_simulation_#t~ret23#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret21#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret23#1;havoc start_simulation_#t~ret23#1; 125223#L1180 assume !(0 != start_simulation_~tmp___0~1#1); 123291#L1148-2 [2023-11-12 02:09:39,034 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-12 02:09:39,035 INFO L85 PathProgramCache]: Analyzing trace with hash 1267470274, now seen corresponding path program 1 times [2023-11-12 02:09:39,035 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-12 02:09:39,035 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1836721774] [2023-11-12 02:09:39,035 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-12 02:09:39,035 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-12 02:09:39,050 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-12 02:09:39,109 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-12 02:09:39,110 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-12 02:09:39,110 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1836721774] [2023-11-12 02:09:39,112 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1836721774] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-12 02:09:39,113 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-12 02:09:39,113 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2023-11-12 02:09:39,113 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1437277121] [2023-11-12 02:09:39,113 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-12 02:09:39,114 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-12 02:09:39,114 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-12 02:09:39,114 INFO L85 PathProgramCache]: Analyzing trace with hash -1482707397, now seen corresponding path program 1 times [2023-11-12 02:09:39,115 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-12 02:09:39,115 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [997468165] [2023-11-12 02:09:39,115 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-12 02:09:39,117 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-12 02:09:39,136 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-12 02:09:39,174 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-12 02:09:39,175 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-12 02:09:39,175 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [997468165] [2023-11-12 02:09:39,175 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [997468165] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-12 02:09:39,175 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-12 02:09:39,175 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-12 02:09:39,176 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [977740749] [2023-11-12 02:09:39,176 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-12 02:09:39,176 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-12 02:09:39,177 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-12 02:09:39,177 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-12 02:09:39,177 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-12 02:09:39,177 INFO L87 Difference]: Start difference. First operand 9084 states and 12789 transitions. cyclomatic complexity: 3709 Second operand has 3 states, 3 states have (on average 31.0) internal successors, (93), 2 states have internal predecessors, (93), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-12 02:09:39,247 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-12 02:09:39,247 INFO L93 Difference]: Finished difference Result 9084 states and 12739 transitions. [2023-11-12 02:09:39,248 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 9084 states and 12739 transitions. [2023-11-12 02:09:39,296 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 8960 [2023-11-12 02:09:39,438 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 9084 states to 9084 states and 12739 transitions. [2023-11-12 02:09:39,439 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 9084 [2023-11-12 02:09:39,445 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 9084 [2023-11-12 02:09:39,445 INFO L73 IsDeterministic]: Start isDeterministic. Operand 9084 states and 12739 transitions. [2023-11-12 02:09:39,449 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-12 02:09:39,450 INFO L218 hiAutomatonCegarLoop]: Abstraction has 9084 states and 12739 transitions. [2023-11-12 02:09:39,459 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 9084 states and 12739 transitions. [2023-11-12 02:09:39,564 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 9084 to 9084. [2023-11-12 02:09:39,579 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 9084 states, 9084 states have (on average 1.4023557904007045) internal successors, (12739), 9083 states have internal predecessors, (12739), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-12 02:09:39,610 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 9084 states to 9084 states and 12739 transitions. [2023-11-12 02:09:39,611 INFO L240 hiAutomatonCegarLoop]: Abstraction has 9084 states and 12739 transitions. [2023-11-12 02:09:39,611 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-12 02:09:39,612 INFO L428 stractBuchiCegarLoop]: Abstraction has 9084 states and 12739 transitions. [2023-11-12 02:09:39,613 INFO L335 stractBuchiCegarLoop]: ======== Iteration 17 ============ [2023-11-12 02:09:39,613 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 9084 states and 12739 transitions. [2023-11-12 02:09:39,650 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 8960 [2023-11-12 02:09:39,651 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-12 02:09:39,651 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-12 02:09:39,653 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-12 02:09:39,653 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-12 02:09:39,654 INFO L748 eck$LassoCheckResult]: Stem: 140957#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2; 140958#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~9#1;havoc main_~__retres1~9#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 141544#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret22#1, start_simulation_#t~ret23#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 141545#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 141577#L521 assume 1 == ~m_i~0;~m_st~0 := 0; 141561#L521-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 141562#L526-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 141109#L531-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 141110#L536-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 141182#L541-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 141020#L546-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 141021#L551-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 140988#L556-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 140989#L754 assume !(0 == ~M_E~0); 141591#L754-2 assume !(0 == ~T1_E~0); 141506#L759-1 assume !(0 == ~T2_E~0); 141367#L764-1 assume !(0 == ~T3_E~0); 141320#L769-1 assume !(0 == ~T4_E~0); 141321#L774-1 assume !(0 == ~T5_E~0); 141368#L779-1 assume !(0 == ~T6_E~0); 141514#L784-1 assume !(0 == ~T7_E~0); 141317#L789-1 assume !(0 == ~E_1~0); 141318#L794-1 assume !(0 == ~E_2~0); 141417#L799-1 assume !(0 == ~E_3~0); 141328#L804-1 assume !(0 == ~E_4~0); 141329#L809-1 assume !(0 == ~E_5~0); 141361#L814-1 assume !(0 == ~E_6~0); 140756#L819-1 assume !(0 == ~E_7~0); 140757#L824-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 141018#L361 assume !(1 == ~m_pc~0); 141019#L361-2 is_master_triggered_~__retres1~0#1 := 0; 141540#L372 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 141491#is_master_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 141492#L930 assume !(0 != activate_threads_~tmp~1#1); 141228#L930-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 141012#L380 assume !(1 == ~t1_pc~0); 141013#L380-2 is_transmit1_triggered_~__retres1~1#1 := 0; 141573#L391 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 141574#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 141623#L938 assume !(0 != activate_threads_~tmp___0~0#1); 141447#L938-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 141426#L399 assume !(1 == ~t2_pc~0); 140926#L399-2 is_transmit2_triggered_~__retres1~2#1 := 0; 140927#L410 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 141089#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 141082#L946 assume !(0 != activate_threads_~tmp___1~0#1); 141083#L946-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 140764#L418 assume !(1 == ~t3_pc~0); 140744#L418-2 is_transmit3_triggered_~__retres1~3#1 := 0; 140745#L429 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 140754#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 140755#L954 assume !(0 != activate_threads_~tmp___2~0#1); 141346#L954-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 141347#L437 assume !(1 == ~t4_pc~0); 141563#L437-2 is_transmit4_triggered_~__retres1~4#1 := 0; 141486#L448 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 140835#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 140836#L962 assume !(0 != activate_threads_~tmp___3~0#1); 141138#L962-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 141468#L456 assume !(1 == ~t5_pc~0); 140940#L456-2 is_transmit5_triggered_~__retres1~5#1 := 0; 140939#L467 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 141495#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 141402#L970 assume !(0 != activate_threads_~tmp___4~0#1); 141403#L970-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 140830#L475 assume !(1 == ~t6_pc~0); 140831#L475-2 is_transmit6_triggered_~__retres1~6#1 := 0; 140873#L486 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 140874#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 141075#L978 assume !(0 != activate_threads_~tmp___5~0#1); 141333#L978-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 141334#L494 assume !(1 == ~t7_pc~0); 141059#L494-2 is_transmit7_triggered_~__retres1~7#1 := 0; 141060#L505 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 141287#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 141369#L986 assume !(0 != activate_threads_~tmp___6~0#1); 141370#L986-2 havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 141583#L837 assume !(1 == ~M_E~0); 141543#L837-2 assume !(1 == ~T1_E~0); 141422#L842-1 assume !(1 == ~T2_E~0); 141147#L847-1 assume !(1 == ~T3_E~0); 141148#L852-1 assume !(1 == ~T4_E~0); 141218#L857-1 assume !(1 == ~T5_E~0); 141095#L862-1 assume !(1 == ~T6_E~0); 141096#L867-1 assume !(1 == ~T7_E~0); 141105#L872-1 assume !(1 == ~E_1~0); 141181#L877-1 assume !(1 == ~E_2~0); 141384#L882-1 assume !(1 == ~E_3~0); 141549#L887-1 assume !(1 == ~E_4~0); 141442#L892-1 assume !(1 == ~E_5~0); 141443#L897-1 assume 1 == ~E_6~0;~E_6~0 := 2; 141120#L902-1 assume !(1 == ~E_7~0); 141121#L907-1 assume { :end_inline_reset_delta_events } true; 141467#L1148-2 [2023-11-12 02:09:39,654 INFO L750 eck$LassoCheckResult]: Loop: 141467#L1148-2 assume !false; 145058#L1149 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 145056#L729-1 assume !false; 145055#L622 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 144144#L569 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 144138#L611 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 144135#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 144132#L626 assume !(0 != eval_~tmp~0#1); 144133#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 145873#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 145872#L754-3 assume 0 == ~M_E~0;~M_E~0 := 1; 145871#L754-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 145870#L759-3 assume !(0 == ~T2_E~0); 145869#L764-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 145868#L769-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 145867#L774-3 assume !(0 == ~T5_E~0); 145866#L779-3 assume !(0 == ~T6_E~0); 145864#L784-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 145861#L789-3 assume 0 == ~E_1~0;~E_1~0 := 1; 145858#L794-3 assume 0 == ~E_2~0;~E_2~0 := 1; 145854#L799-3 assume !(0 == ~E_3~0); 145850#L804-3 assume 0 == ~E_4~0;~E_4~0 := 1; 145846#L809-3 assume 0 == ~E_5~0;~E_5~0 := 1; 145842#L814-3 assume 0 == ~E_6~0;~E_6~0 := 1; 145837#L819-3 assume !(0 == ~E_7~0); 145830#L824-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 145823#L361-24 assume !(1 == ~m_pc~0); 145816#L361-26 is_master_triggered_~__retres1~0#1 := 0; 145810#L372-8 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 145806#is_master_triggered_returnLabel#9 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 145803#L930-24 assume !(0 != activate_threads_~tmp~1#1); 145801#L930-26 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 145797#L380-24 assume 1 == ~t1_pc~0; 145792#L381-8 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 145787#L391-8 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 145782#is_transmit1_triggered_returnLabel#9 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 145776#L938-24 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 145770#L938-26 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 145766#L399-24 assume !(1 == ~t2_pc~0); 145611#L399-26 is_transmit2_triggered_~__retres1~2#1 := 0; 145759#L410-8 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 145755#is_transmit2_triggered_returnLabel#9 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 145750#L946-24 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 145744#L946-26 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 145740#L418-24 assume 1 == ~t3_pc~0; 145735#L419-8 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 145731#L429-8 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 145727#is_transmit3_triggered_returnLabel#9 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 145722#L954-24 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 145716#L954-26 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 145712#L437-24 assume !(1 == ~t4_pc~0); 145708#L437-26 is_transmit4_triggered_~__retres1~4#1 := 0; 145704#L448-8 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 145428#is_transmit4_triggered_returnLabel#9 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 145420#L962-24 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 145372#L962-26 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 145366#L456-24 assume !(1 == ~t5_pc~0); 145360#L456-26 is_transmit5_triggered_~__retres1~5#1 := 0; 145269#L467-8 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 145265#is_transmit5_triggered_returnLabel#9 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 145263#L970-24 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 145261#L970-26 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 145259#L475-24 assume !(1 == ~t6_pc~0); 143621#L475-26 is_transmit6_triggered_~__retres1~6#1 := 0; 145199#L486-8 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 145198#is_transmit6_triggered_returnLabel#9 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 145197#L978-24 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 145196#L978-26 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 145195#L494-24 assume !(1 == ~t7_pc~0); 145193#L494-26 is_transmit7_triggered_~__retres1~7#1 := 0; 145192#L505-8 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 145191#is_transmit7_triggered_returnLabel#9 activate_threads_#t~ret20#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 145190#L986-24 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 145189#L986-26 havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 145188#L837-3 assume 1 == ~M_E~0;~M_E~0 := 2; 145187#L837-5 assume !(1 == ~T1_E~0); 145186#L842-3 assume !(1 == ~T2_E~0); 145184#L847-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 145182#L852-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 145180#L857-3 assume !(1 == ~T5_E~0); 145178#L862-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 145176#L867-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 145174#L872-3 assume 1 == ~E_1~0;~E_1~0 := 2; 145172#L877-3 assume !(1 == ~E_2~0); 145169#L882-3 assume 1 == ~E_3~0;~E_3~0 := 2; 145167#L887-3 assume 1 == ~E_4~0;~E_4~0 := 2; 145165#L892-3 assume 1 == ~E_5~0;~E_5~0 := 2; 145163#L897-3 assume 1 == ~E_6~0;~E_6~0 := 2; 145161#L902-3 assume !(1 == ~E_7~0); 145159#L907-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 145092#L569-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 145086#L611-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 145084#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret22#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret22#1;havoc start_simulation_#t~ret22#1; 145082#L1167 assume !(0 == start_simulation_~tmp~3#1); 145080#L1167-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret21#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 145079#L569-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 145071#L611-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 145070#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret21#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret21#1;havoc stop_simulation_#t~ret21#1; 145069#L1122 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 145067#L1129 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 145065#stop_simulation_returnLabel#1 start_simulation_#t~ret23#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret21#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret23#1;havoc start_simulation_#t~ret23#1; 145063#L1180 assume !(0 != start_simulation_~tmp___0~1#1); 141467#L1148-2 [2023-11-12 02:09:39,655 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-12 02:09:39,655 INFO L85 PathProgramCache]: Analyzing trace with hash 1968534852, now seen corresponding path program 1 times [2023-11-12 02:09:39,656 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-12 02:09:39,656 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [541357561] [2023-11-12 02:09:39,656 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-12 02:09:39,656 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-12 02:09:39,671 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-12 02:09:39,734 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-12 02:09:39,735 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-12 02:09:39,735 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [541357561] [2023-11-12 02:09:39,735 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [541357561] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-12 02:09:39,735 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-12 02:09:39,735 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-12 02:09:39,736 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [177621719] [2023-11-12 02:09:39,736 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-12 02:09:39,736 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-12 02:09:39,737 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-12 02:09:39,737 INFO L85 PathProgramCache]: Analyzing trace with hash 254187967, now seen corresponding path program 1 times [2023-11-12 02:09:39,737 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-12 02:09:39,737 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [593250366] [2023-11-12 02:09:39,737 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-12 02:09:39,738 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-12 02:09:39,754 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-12 02:09:39,791 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-12 02:09:39,792 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-12 02:09:39,792 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [593250366] [2023-11-12 02:09:39,792 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [593250366] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-12 02:09:39,792 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-12 02:09:39,793 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-12 02:09:39,793 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [601970432] [2023-11-12 02:09:39,793 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-12 02:09:39,793 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-12 02:09:39,794 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-12 02:09:39,794 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2023-11-12 02:09:39,794 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2023-11-12 02:09:39,794 INFO L87 Difference]: Start difference. First operand 9084 states and 12739 transitions. cyclomatic complexity: 3659 Second operand has 4 states, 4 states have (on average 23.25) internal successors, (93), 3 states have internal predecessors, (93), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-12 02:09:40,141 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-12 02:09:40,141 INFO L93 Difference]: Finished difference Result 18469 states and 25814 transitions. [2023-11-12 02:09:40,141 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 18469 states and 25814 transitions. [2023-11-12 02:09:40,272 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 18232 [2023-11-12 02:09:40,362 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 18469 states to 18469 states and 25814 transitions. [2023-11-12 02:09:40,362 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 18469 [2023-11-12 02:09:40,382 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 18469 [2023-11-12 02:09:40,382 INFO L73 IsDeterministic]: Start isDeterministic. Operand 18469 states and 25814 transitions. [2023-11-12 02:09:40,403 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-12 02:09:40,403 INFO L218 hiAutomatonCegarLoop]: Abstraction has 18469 states and 25814 transitions. [2023-11-12 02:09:40,425 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 18469 states and 25814 transitions. [2023-11-12 02:09:40,607 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 18469 to 10315. [2023-11-12 02:09:40,626 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 10315 states, 10315 states have (on average 1.3968007755695588) internal successors, (14408), 10314 states have internal predecessors, (14408), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-12 02:09:40,667 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 10315 states to 10315 states and 14408 transitions. [2023-11-12 02:09:40,667 INFO L240 hiAutomatonCegarLoop]: Abstraction has 10315 states and 14408 transitions. [2023-11-12 02:09:40,668 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2023-11-12 02:09:40,668 INFO L428 stractBuchiCegarLoop]: Abstraction has 10315 states and 14408 transitions. [2023-11-12 02:09:40,668 INFO L335 stractBuchiCegarLoop]: ======== Iteration 18 ============ [2023-11-12 02:09:40,669 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 10315 states and 14408 transitions. [2023-11-12 02:09:40,837 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 10120 [2023-11-12 02:09:40,838 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-12 02:09:40,838 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-12 02:09:40,840 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-12 02:09:40,841 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-12 02:09:40,841 INFO L748 eck$LassoCheckResult]: Stem: 168517#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2; 168518#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~9#1;havoc main_~__retres1~9#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 169131#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret22#1, start_simulation_#t~ret23#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 169132#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 169175#L521 assume 1 == ~m_i~0;~m_st~0 := 0; 169156#L521-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 169157#L526-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 168677#L531-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 168678#L536-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 168748#L541-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 168580#L546-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 168581#L551-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 168548#L556-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 168549#L754 assume !(0 == ~M_E~0); 169194#L754-2 assume !(0 == ~T1_E~0); 169079#L759-1 assume !(0 == ~T2_E~0); 168933#L764-1 assume !(0 == ~T3_E~0); 168891#L769-1 assume !(0 == ~T4_E~0); 168892#L774-1 assume !(0 == ~T5_E~0); 168934#L779-1 assume !(0 == ~T6_E~0); 169089#L784-1 assume !(0 == ~T7_E~0); 168888#L789-1 assume !(0 == ~E_1~0); 168889#L794-1 assume !(0 == ~E_2~0); 168987#L799-1 assume !(0 == ~E_3~0); 168898#L804-1 assume !(0 == ~E_4~0); 168899#L809-1 assume !(0 == ~E_5~0); 168927#L814-1 assume 0 == ~E_6~0;~E_6~0 := 1; 168321#L819-1 assume !(0 == ~E_7~0); 168322#L824-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 168578#L361 assume !(1 == ~m_pc~0); 168579#L361-2 is_master_triggered_~__retres1~0#1 := 0; 169203#L372 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 169204#is_master_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 169166#L930 assume !(0 != activate_threads_~tmp~1#1); 169167#L930-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 168572#L380 assume !(1 == ~t1_pc~0); 168573#L380-2 is_transmit1_triggered_~__retres1~1#1 := 0; 169255#L391 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 169253#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 169229#L938 assume !(0 != activate_threads_~tmp___0~0#1); 169018#L938-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 168997#L399 assume !(1 == ~t2_pc~0); 168998#L399-2 is_transmit2_triggered_~__retres1~2#1 := 0; 169176#L410 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 169177#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 168647#L946 assume !(0 != activate_threads_~tmp___1~0#1); 168648#L946-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 169248#L418 assume !(1 == ~t3_pc~0); 168307#L418-2 is_transmit3_triggered_~__retres1~3#1 := 0; 168308#L429 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 169247#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 169233#L954 assume !(0 != activate_threads_~tmp___2~0#1); 169234#L954-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 169197#L437 assume !(1 == ~t4_pc~0); 169198#L437-2 is_transmit4_triggered_~__retres1~4#1 := 0; 169246#L448 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 168399#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 168400#L962 assume !(0 != activate_threads_~tmp___3~0#1); 169142#L962-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 169043#L456 assume !(1 == ~t5_pc~0); 169044#L456-2 is_transmit5_triggered_~__retres1~5#1 := 0; 169190#L467 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 169069#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 168972#L970 assume !(0 != activate_threads_~tmp___4~0#1); 168973#L970-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 168394#L475 assume !(1 == ~t6_pc~0); 168395#L475-2 is_transmit6_triggered_~__retres1~6#1 := 0; 168434#L486 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 168435#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 168963#L978 assume !(0 != activate_threads_~tmp___5~0#1); 168964#L978-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 169110#L494 assume !(1 == ~t7_pc~0); 168840#L494-2 is_transmit7_triggered_~__retres1~7#1 := 0; 168855#L505 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 168856#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 168935#L986 assume !(0 != activate_threads_~tmp___6~0#1); 168936#L986-2 havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 169186#L837 assume !(1 == ~M_E~0); 169187#L837-2 assume !(1 == ~T1_E~0); 169241#L842-1 assume !(1 == ~T2_E~0); 169240#L847-1 assume !(1 == ~T3_E~0); 168781#L852-1 assume !(1 == ~T4_E~0); 168782#L857-1 assume !(1 == ~T5_E~0); 168661#L862-1 assume !(1 == ~T6_E~0); 168662#L867-1 assume !(1 == ~T7_E~0); 169239#L872-1 assume !(1 == ~E_1~0); 168950#L877-1 assume !(1 == ~E_2~0); 168951#L882-1 assume !(1 == ~E_3~0); 169202#L887-1 assume !(1 == ~E_4~0); 169013#L892-1 assume !(1 == ~E_5~0); 169014#L897-1 assume 1 == ~E_6~0;~E_6~0 := 2; 168688#L902-1 assume !(1 == ~E_7~0); 168689#L907-1 assume { :end_inline_reset_delta_events } true; 169037#L1148-2 [2023-11-12 02:09:40,842 INFO L750 eck$LassoCheckResult]: Loop: 169037#L1148-2 assume !false; 176088#L1149 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 175968#L729-1 assume !false; 175966#L622 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 175872#L569 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 175861#L611 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 175856#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 175850#L626 assume !(0 != eval_~tmp~0#1); 175851#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 177795#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 177793#L754-3 assume 0 == ~M_E~0;~M_E~0 := 1; 177784#L754-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 177783#L759-3 assume !(0 == ~T2_E~0); 177782#L764-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 177781#L769-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 177780#L774-3 assume !(0 == ~T5_E~0); 177779#L779-3 assume !(0 == ~T6_E~0); 177778#L784-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 177777#L789-3 assume 0 == ~E_1~0;~E_1~0 := 1; 177776#L794-3 assume 0 == ~E_2~0;~E_2~0 := 1; 177775#L799-3 assume !(0 == ~E_3~0); 177774#L804-3 assume 0 == ~E_4~0;~E_4~0 := 1; 177773#L809-3 assume 0 == ~E_5~0;~E_5~0 := 1; 177771#L814-3 assume 0 == ~E_6~0;~E_6~0 := 1; 176664#L819-3 assume !(0 == ~E_7~0); 176665#L824-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 176658#L361-24 assume !(1 == ~m_pc~0); 176659#L361-26 is_master_triggered_~__retres1~0#1 := 0; 176652#L372-8 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 176653#is_master_triggered_returnLabel#9 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 176646#L930-24 assume !(0 != activate_threads_~tmp~1#1); 176647#L930-26 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 176638#L380-24 assume !(1 == ~t1_pc~0); 176640#L380-26 is_transmit1_triggered_~__retres1~1#1 := 0; 176630#L391-8 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 176631#is_transmit1_triggered_returnLabel#9 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 176625#L938-24 assume !(0 != activate_threads_~tmp___0~0#1); 176624#L938-26 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 176486#L399-24 assume !(1 == ~t2_pc~0); 176485#L399-26 is_transmit2_triggered_~__retres1~2#1 := 0; 176484#L410-8 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 176483#is_transmit2_triggered_returnLabel#9 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 176482#L946-24 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 176481#L946-26 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 176480#L418-24 assume 1 == ~t3_pc~0; 176478#L419-8 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 176477#L429-8 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 176476#is_transmit3_triggered_returnLabel#9 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 176475#L954-24 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 176474#L954-26 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 176473#L437-24 assume !(1 == ~t4_pc~0); 176472#L437-26 is_transmit4_triggered_~__retres1~4#1 := 0; 176471#L448-8 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 176470#is_transmit4_triggered_returnLabel#9 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 176469#L962-24 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 176468#L962-26 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 176467#L456-24 assume !(1 == ~t5_pc~0); 176466#L456-26 is_transmit5_triggered_~__retres1~5#1 := 0; 176464#L467-8 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 176463#is_transmit5_triggered_returnLabel#9 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 176462#L970-24 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 176461#L970-26 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 176460#L475-24 assume !(1 == ~t6_pc~0); 175523#L475-26 is_transmit6_triggered_~__retres1~6#1 := 0; 176459#L486-8 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 176458#is_transmit6_triggered_returnLabel#9 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 176457#L978-24 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 176456#L978-26 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 176455#L494-24 assume !(1 == ~t7_pc~0); 176453#L494-26 is_transmit7_triggered_~__retres1~7#1 := 0; 176452#L505-8 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 176451#is_transmit7_triggered_returnLabel#9 activate_threads_#t~ret20#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 176450#L986-24 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 176449#L986-26 havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 176448#L837-3 assume 1 == ~M_E~0;~M_E~0 := 2; 176447#L837-5 assume !(1 == ~T1_E~0); 176446#L842-3 assume !(1 == ~T2_E~0); 176445#L847-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 176444#L852-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 176443#L857-3 assume !(1 == ~T5_E~0); 176442#L862-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 176441#L867-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 176440#L872-3 assume 1 == ~E_1~0;~E_1~0 := 2; 176439#L877-3 assume !(1 == ~E_2~0); 176438#L882-3 assume 1 == ~E_3~0;~E_3~0 := 2; 176437#L887-3 assume 1 == ~E_4~0;~E_4~0 := 2; 176436#L892-3 assume 1 == ~E_5~0;~E_5~0 := 2; 176434#L897-3 assume 1 == ~E_6~0;~E_6~0 := 2; 176420#L902-3 assume !(1 == ~E_7~0); 176419#L907-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 176414#L569-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 176408#L611-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 176406#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret22#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret22#1;havoc start_simulation_#t~ret22#1; 176404#L1167 assume !(0 == start_simulation_~tmp~3#1); 176402#L1167-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret21#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 176400#L569-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 176392#L611-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 176391#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret21#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret21#1;havoc stop_simulation_#t~ret21#1; 176390#L1122 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 176389#L1129 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 176150#stop_simulation_returnLabel#1 start_simulation_#t~ret23#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret21#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret23#1;havoc start_simulation_#t~ret23#1; 176110#L1180 assume !(0 != start_simulation_~tmp___0~1#1); 169037#L1148-2 [2023-11-12 02:09:40,842 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-12 02:09:40,842 INFO L85 PathProgramCache]: Analyzing trace with hash -1110278718, now seen corresponding path program 1 times [2023-11-12 02:09:40,843 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-12 02:09:40,843 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1963469156] [2023-11-12 02:09:40,843 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-12 02:09:40,843 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-12 02:09:40,854 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-12 02:09:40,905 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-12 02:09:40,905 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-12 02:09:40,905 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1963469156] [2023-11-12 02:09:40,906 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1963469156] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-12 02:09:40,906 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-12 02:09:40,906 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-12 02:09:40,906 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [771865801] [2023-11-12 02:09:40,906 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-12 02:09:40,907 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-12 02:09:40,907 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-12 02:09:40,907 INFO L85 PathProgramCache]: Analyzing trace with hash 428976988, now seen corresponding path program 1 times [2023-11-12 02:09:40,907 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-12 02:09:40,908 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [202032157] [2023-11-12 02:09:40,908 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-12 02:09:40,908 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-12 02:09:40,923 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-12 02:09:40,964 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-12 02:09:40,964 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-12 02:09:40,964 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [202032157] [2023-11-12 02:09:40,964 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [202032157] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-12 02:09:40,964 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-12 02:09:40,965 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-12 02:09:40,965 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [892883241] [2023-11-12 02:09:40,965 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-12 02:09:40,966 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-12 02:09:40,966 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-12 02:09:40,966 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2023-11-12 02:09:40,967 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2023-11-12 02:09:40,967 INFO L87 Difference]: Start difference. First operand 10315 states and 14408 transitions. cyclomatic complexity: 4097 Second operand has 4 states, 4 states have (on average 23.25) internal successors, (93), 3 states have internal predecessors, (93), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-12 02:09:41,150 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-12 02:09:41,150 INFO L93 Difference]: Finished difference Result 17140 states and 23905 transitions. [2023-11-12 02:09:41,150 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 17140 states and 23905 transitions. [2023-11-12 02:09:41,251 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 16976 [2023-11-12 02:09:41,324 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 17140 states to 17140 states and 23905 transitions. [2023-11-12 02:09:41,325 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 17140 [2023-11-12 02:09:41,342 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 17140 [2023-11-12 02:09:41,342 INFO L73 IsDeterministic]: Start isDeterministic. Operand 17140 states and 23905 transitions. [2023-11-12 02:09:41,358 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-12 02:09:41,358 INFO L218 hiAutomatonCegarLoop]: Abstraction has 17140 states and 23905 transitions. [2023-11-12 02:09:41,377 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 17140 states and 23905 transitions. [2023-11-12 02:09:41,655 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 17140 to 9084. [2023-11-12 02:09:41,669 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 9084 states, 9084 states have (on average 1.3911272567151034) internal successors, (12637), 9083 states have internal predecessors, (12637), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-12 02:09:41,698 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 9084 states to 9084 states and 12637 transitions. [2023-11-12 02:09:41,698 INFO L240 hiAutomatonCegarLoop]: Abstraction has 9084 states and 12637 transitions. [2023-11-12 02:09:41,699 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2023-11-12 02:09:41,699 INFO L428 stractBuchiCegarLoop]: Abstraction has 9084 states and 12637 transitions. [2023-11-12 02:09:41,699 INFO L335 stractBuchiCegarLoop]: ======== Iteration 19 ============ [2023-11-12 02:09:41,700 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 9084 states and 12637 transitions. [2023-11-12 02:09:41,808 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 8960 [2023-11-12 02:09:41,809 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-12 02:09:41,809 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-12 02:09:41,811 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-12 02:09:41,811 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-12 02:09:41,812 INFO L748 eck$LassoCheckResult]: Stem: 195980#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2; 195981#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~9#1;havoc main_~__retres1~9#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 196570#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret22#1, start_simulation_#t~ret23#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 196571#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 196610#L521 assume 1 == ~m_i~0;~m_st~0 := 0; 196596#L521-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 196597#L526-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 196132#L531-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 196133#L536-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 196203#L541-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 196043#L546-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 196044#L551-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 196011#L556-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 196012#L754 assume !(0 == ~M_E~0); 196634#L754-2 assume !(0 == ~T1_E~0); 196524#L759-1 assume !(0 == ~T2_E~0); 196382#L764-1 assume !(0 == ~T3_E~0); 196339#L769-1 assume !(0 == ~T4_E~0); 196340#L774-1 assume !(0 == ~T5_E~0); 196383#L779-1 assume !(0 == ~T6_E~0); 196534#L784-1 assume !(0 == ~T7_E~0); 196336#L789-1 assume !(0 == ~E_1~0); 196337#L794-1 assume !(0 == ~E_2~0); 196434#L799-1 assume !(0 == ~E_3~0); 196347#L804-1 assume !(0 == ~E_4~0); 196348#L809-1 assume !(0 == ~E_5~0); 196376#L814-1 assume !(0 == ~E_6~0); 195784#L819-1 assume !(0 == ~E_7~0); 195785#L824-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 196041#L361 assume !(1 == ~m_pc~0); 196042#L361-2 is_master_triggered_~__retres1~0#1 := 0; 196565#L372 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 196512#is_master_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 196513#L930 assume !(0 != activate_threads_~tmp~1#1); 196247#L930-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 196035#L380 assume !(1 == ~t1_pc~0); 196036#L380-2 is_transmit1_triggered_~__retres1~1#1 := 0; 196606#L391 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 196607#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 196666#L938 assume !(0 != activate_threads_~tmp___0~0#1); 196466#L938-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 196444#L399 assume !(1 == ~t2_pc~0); 195948#L399-2 is_transmit2_triggered_~__retres1~2#1 := 0; 195949#L410 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 196112#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 196105#L946 assume !(0 != activate_threads_~tmp___1~0#1); 196106#L946-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 195792#L418 assume !(1 == ~t3_pc~0); 195772#L418-2 is_transmit3_triggered_~__retres1~3#1 := 0; 195773#L429 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 195782#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 195783#L954 assume !(0 != activate_threads_~tmp___2~0#1); 196362#L954-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 196363#L437 assume !(1 == ~t4_pc~0); 196598#L437-2 is_transmit4_triggered_~__retres1~4#1 := 0; 196506#L448 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 195861#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 195862#L962 assume !(0 != activate_threads_~tmp___3~0#1); 196160#L962-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 196487#L456 assume !(1 == ~t5_pc~0); 195963#L456-2 is_transmit5_triggered_~__retres1~5#1 := 0; 195962#L467 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 196516#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 196417#L970 assume !(0 != activate_threads_~tmp___4~0#1); 196418#L970-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 195856#L475 assume !(1 == ~t6_pc~0); 195857#L475-2 is_transmit6_triggered_~__retres1~6#1 := 0; 195897#L486 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 195898#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 196098#L978 assume !(0 != activate_threads_~tmp___5~0#1); 196352#L978-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 196353#L494 assume !(1 == ~t7_pc~0); 196082#L494-2 is_transmit7_triggered_~__retres1~7#1 := 0; 196083#L505 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 196306#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 196384#L986 assume !(0 != activate_threads_~tmp___6~0#1); 196385#L986-2 havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 196622#L837 assume !(1 == ~M_E~0); 196569#L837-2 assume !(1 == ~T1_E~0); 196440#L842-1 assume !(1 == ~T2_E~0); 196169#L847-1 assume !(1 == ~T3_E~0); 196170#L852-1 assume !(1 == ~T4_E~0); 196237#L857-1 assume !(1 == ~T5_E~0); 196118#L862-1 assume !(1 == ~T6_E~0); 196119#L867-1 assume !(1 == ~T7_E~0); 196128#L872-1 assume !(1 == ~E_1~0); 196202#L877-1 assume !(1 == ~E_2~0); 196399#L882-1 assume !(1 == ~E_3~0); 196576#L887-1 assume !(1 == ~E_4~0); 196459#L892-1 assume !(1 == ~E_5~0); 196460#L897-1 assume !(1 == ~E_6~0); 196143#L902-1 assume !(1 == ~E_7~0); 196144#L907-1 assume { :end_inline_reset_delta_events } true; 196486#L1148-2 [2023-11-12 02:09:41,812 INFO L750 eck$LassoCheckResult]: Loop: 196486#L1148-2 assume !false; 201579#L1149 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 201573#L729-1 assume !false; 201571#L622 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 201446#L569 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 201436#L611 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 201431#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 201423#L626 assume !(0 != eval_~tmp~0#1); 201424#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 202038#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 202034#L754-3 assume 0 == ~M_E~0;~M_E~0 := 1; 202030#L754-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 202025#L759-3 assume !(0 == ~T2_E~0); 202020#L764-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 202015#L769-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 202010#L774-3 assume !(0 == ~T5_E~0); 202005#L779-3 assume !(0 == ~T6_E~0); 202001#L784-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 201996#L789-3 assume 0 == ~E_1~0;~E_1~0 := 1; 201991#L794-3 assume 0 == ~E_2~0;~E_2~0 := 1; 201985#L799-3 assume !(0 == ~E_3~0); 201980#L804-3 assume 0 == ~E_4~0;~E_4~0 := 1; 201975#L809-3 assume 0 == ~E_5~0;~E_5~0 := 1; 201970#L814-3 assume !(0 == ~E_6~0); 201964#L819-3 assume !(0 == ~E_7~0); 201959#L824-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 201953#L361-24 assume !(1 == ~m_pc~0); 201948#L361-26 is_master_triggered_~__retres1~0#1 := 0; 201942#L372-8 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 201937#is_master_triggered_returnLabel#9 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 201932#L930-24 assume !(0 != activate_threads_~tmp~1#1); 201927#L930-26 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 201921#L380-24 assume 1 == ~t1_pc~0; 201915#L381-8 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 201909#L391-8 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 201903#is_transmit1_triggered_returnLabel#9 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 201896#L938-24 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 201891#L938-26 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 201885#L399-24 assume !(1 == ~t2_pc~0); 199584#L399-26 is_transmit2_triggered_~__retres1~2#1 := 0; 201876#L410-8 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 201870#is_transmit2_triggered_returnLabel#9 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 201865#L946-24 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 201861#L946-26 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 201858#L418-24 assume !(1 == ~t3_pc~0); 201854#L418-26 is_transmit3_triggered_~__retres1~3#1 := 0; 201849#L429-8 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 201845#is_transmit3_triggered_returnLabel#9 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 201841#L954-24 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 201838#L954-26 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 201837#L437-24 assume !(1 == ~t4_pc~0); 201836#L437-26 is_transmit4_triggered_~__retres1~4#1 := 0; 201835#L448-8 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 201834#is_transmit4_triggered_returnLabel#9 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 201833#L962-24 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 201831#L962-26 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 201830#L456-24 assume !(1 == ~t5_pc~0); 201829#L456-26 is_transmit5_triggered_~__retres1~5#1 := 0; 201827#L467-8 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 201826#is_transmit5_triggered_returnLabel#9 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 201825#L970-24 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 201824#L970-26 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 201822#L475-24 assume !(1 == ~t6_pc~0); 201067#L475-26 is_transmit6_triggered_~__retres1~6#1 := 0; 201818#L486-8 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 201816#is_transmit6_triggered_returnLabel#9 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 201814#L978-24 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 201812#L978-26 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 201808#L494-24 assume !(1 == ~t7_pc~0); 201805#L494-26 is_transmit7_triggered_~__retres1~7#1 := 0; 201803#L505-8 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 201801#is_transmit7_triggered_returnLabel#9 activate_threads_#t~ret20#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 201798#L986-24 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 201796#L986-26 havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 201794#L837-3 assume 1 == ~M_E~0;~M_E~0 := 2; 201793#L837-5 assume !(1 == ~T1_E~0); 201791#L842-3 assume !(1 == ~T2_E~0); 201789#L847-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 201787#L852-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 201785#L857-3 assume !(1 == ~T5_E~0); 201783#L862-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 201780#L867-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 201778#L872-3 assume 1 == ~E_1~0;~E_1~0 := 2; 201776#L877-3 assume !(1 == ~E_2~0); 201774#L882-3 assume 1 == ~E_3~0;~E_3~0 := 2; 201772#L887-3 assume 1 == ~E_4~0;~E_4~0 := 2; 201753#L892-3 assume 1 == ~E_5~0;~E_5~0 := 2; 201747#L897-3 assume !(1 == ~E_6~0); 201741#L902-3 assume !(1 == ~E_7~0); 201733#L907-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 201719#L569-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 201713#L611-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 201711#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret22#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret22#1;havoc start_simulation_#t~ret22#1; 201668#L1167 assume !(0 == start_simulation_~tmp~3#1); 201663#L1167-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret21#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 201617#L569-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 201608#L611-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 201606#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret21#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret21#1;havoc stop_simulation_#t~ret21#1; 201604#L1122 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 201602#L1129 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 201599#stop_simulation_returnLabel#1 start_simulation_#t~ret23#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret21#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret23#1;havoc start_simulation_#t~ret23#1; 201597#L1180 assume !(0 != start_simulation_~tmp___0~1#1); 196486#L1148-2 [2023-11-12 02:09:41,814 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-12 02:09:41,814 INFO L85 PathProgramCache]: Analyzing trace with hash 1968536774, now seen corresponding path program 1 times [2023-11-12 02:09:41,814 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-12 02:09:41,814 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2146836289] [2023-11-12 02:09:41,814 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-12 02:09:41,815 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-12 02:09:41,829 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-12 02:09:41,830 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-12 02:09:41,842 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-12 02:09:41,914 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-12 02:09:41,915 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-12 02:09:41,915 INFO L85 PathProgramCache]: Analyzing trace with hash -1927083358, now seen corresponding path program 1 times [2023-11-12 02:09:41,916 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-12 02:09:41,916 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1371391724] [2023-11-12 02:09:41,916 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-12 02:09:41,916 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-12 02:09:41,934 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-12 02:09:41,968 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-12 02:09:41,969 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-12 02:09:41,969 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1371391724] [2023-11-12 02:09:41,969 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1371391724] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-12 02:09:41,969 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-12 02:09:41,969 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-12 02:09:41,971 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [374915234] [2023-11-12 02:09:41,971 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-12 02:09:41,972 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-12 02:09:41,972 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-12 02:09:41,973 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-12 02:09:41,973 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-12 02:09:41,973 INFO L87 Difference]: Start difference. First operand 9084 states and 12637 transitions. cyclomatic complexity: 3557 Second operand has 3 states, 3 states have (on average 34.0) internal successors, (102), 3 states have internal predecessors, (102), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-12 02:09:42,045 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-12 02:09:42,045 INFO L93 Difference]: Finished difference Result 10323 states and 14340 transitions. [2023-11-12 02:09:42,045 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 10323 states and 14340 transitions. [2023-11-12 02:09:42,195 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 10128 [2023-11-12 02:09:42,239 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 10323 states to 10323 states and 14340 transitions. [2023-11-12 02:09:42,240 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 10323 [2023-11-12 02:09:42,258 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 10323 [2023-11-12 02:09:42,258 INFO L73 IsDeterministic]: Start isDeterministic. Operand 10323 states and 14340 transitions. [2023-11-12 02:09:42,269 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-12 02:09:42,270 INFO L218 hiAutomatonCegarLoop]: Abstraction has 10323 states and 14340 transitions. [2023-11-12 02:09:42,278 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 10323 states and 14340 transitions. [2023-11-12 02:09:42,403 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 10323 to 10323. [2023-11-12 02:09:42,420 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 10323 states, 10323 states have (on average 1.3891310665504213) internal successors, (14340), 10322 states have internal predecessors, (14340), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-12 02:09:42,455 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 10323 states to 10323 states and 14340 transitions. [2023-11-12 02:09:42,456 INFO L240 hiAutomatonCegarLoop]: Abstraction has 10323 states and 14340 transitions. [2023-11-12 02:09:42,456 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-12 02:09:42,457 INFO L428 stractBuchiCegarLoop]: Abstraction has 10323 states and 14340 transitions. [2023-11-12 02:09:42,457 INFO L335 stractBuchiCegarLoop]: ======== Iteration 20 ============ [2023-11-12 02:09:42,457 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 10323 states and 14340 transitions. [2023-11-12 02:09:42,505 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 10128 [2023-11-12 02:09:42,505 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-12 02:09:42,506 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-12 02:09:42,509 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-12 02:09:42,509 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-12 02:09:42,510 INFO L748 eck$LassoCheckResult]: Stem: 215398#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2; 215399#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~9#1;havoc main_~__retres1~9#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 216003#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret22#1, start_simulation_#t~ret23#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 216004#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 216047#L521 assume 1 == ~m_i~0;~m_st~0 := 0; 216030#L521-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 216031#L526-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 215554#L531-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 215555#L536-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 215624#L541-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 215462#L546-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 215463#L551-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 215429#L556-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 215430#L754 assume !(0 == ~M_E~0); 216067#L754-2 assume 0 == ~T1_E~0;~T1_E~0 := 1; 215953#L759-1 assume !(0 == ~T2_E~0); 215954#L764-1 assume !(0 == ~T3_E~0); 215759#L769-1 assume !(0 == ~T4_E~0); 215760#L774-1 assume !(0 == ~T5_E~0); 216039#L779-1 assume !(0 == ~T6_E~0); 216040#L784-1 assume !(0 == ~T7_E~0); 215756#L789-1 assume !(0 == ~E_1~0); 215757#L794-1 assume !(0 == ~E_2~0); 216092#L799-1 assume !(0 == ~E_3~0); 216093#L804-1 assume !(0 == ~E_4~0); 215797#L809-1 assume !(0 == ~E_5~0); 215798#L814-1 assume !(0 == ~E_6~0); 215200#L819-1 assume !(0 == ~E_7~0); 215201#L824-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 215460#L361 assume !(1 == ~m_pc~0); 215461#L361-2 is_master_triggered_~__retres1~0#1 := 0; 216077#L372 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 215939#is_master_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 215940#L930 assume !(0 != activate_threads_~tmp~1#1); 215669#L930-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 215670#L380 assume !(1 == ~t1_pc~0); 215871#L380-2 is_transmit1_triggered_~__retres1~1#1 := 0; 216044#L391 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 215222#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 215223#L938 assume !(0 != activate_threads_~tmp___0~0#1); 215894#L938-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 215872#L399 assume !(1 == ~t2_pc~0); 215873#L399-2 is_transmit2_triggered_~__retres1~2#1 := 0; 216048#L410 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 216049#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 215528#L946 assume !(0 != activate_threads_~tmp___1~0#1); 215529#L946-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 215206#L418 assume !(1 == ~t3_pc~0); 215207#L418-2 is_transmit3_triggered_~__retres1~3#1 := 0; 215988#L429 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 215196#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 215197#L954 assume !(0 != activate_threads_~tmp___2~0#1); 216098#L954-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 216070#L437 assume !(1 == ~t4_pc~0); 216071#L437-2 is_transmit4_triggered_~__retres1~4#1 := 0; 216116#L448 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 215278#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 215279#L962 assume !(0 != activate_threads_~tmp___3~0#1); 215583#L962-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 216114#L456 assume !(1 == ~t5_pc~0); 215384#L456-2 is_transmit5_triggered_~__retres1~5#1 := 0; 215383#L467 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 216113#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 216112#L970 assume !(0 != activate_threads_~tmp___4~0#1); 216085#L970-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 215273#L475 assume !(1 == ~t6_pc~0); 215274#L475-2 is_transmit6_triggered_~__retres1~6#1 := 0; 216110#L486 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 215518#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 215519#L978 assume !(0 != activate_threads_~tmp___5~0#1); 215772#L978-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 215773#L494 assume !(1 == ~t7_pc~0); 215502#L494-2 is_transmit7_triggered_~__retres1~7#1 := 0; 215503#L505 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 215727#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 215808#L986 assume !(0 != activate_threads_~tmp___6~0#1); 215809#L986-2 havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 216056#L837 assume !(1 == ~M_E~0); 216002#L837-2 assume 1 == ~T1_E~0;~T1_E~0 := 2; 215866#L842-1 assume !(1 == ~T2_E~0); 215590#L847-1 assume !(1 == ~T3_E~0); 215591#L852-1 assume !(1 == ~T4_E~0); 215659#L857-1 assume !(1 == ~T5_E~0); 215542#L862-1 assume !(1 == ~T6_E~0); 215543#L867-1 assume !(1 == ~T7_E~0); 215550#L872-1 assume !(1 == ~E_1~0); 215623#L877-1 assume !(1 == ~E_2~0); 215823#L882-1 assume !(1 == ~E_3~0); 216010#L887-1 assume !(1 == ~E_4~0); 215888#L892-1 assume !(1 == ~E_5~0); 215889#L897-1 assume !(1 == ~E_6~0); 215565#L902-1 assume !(1 == ~E_7~0); 215566#L907-1 assume { :end_inline_reset_delta_events } true; 215911#L1148-2 [2023-11-12 02:09:42,511 INFO L750 eck$LassoCheckResult]: Loop: 215911#L1148-2 assume !false; 219490#L1149 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 219487#L729-1 assume !false; 219483#L622 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 219473#L569 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 219466#L611 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 219462#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 219457#L626 assume !(0 != eval_~tmp~0#1); 219458#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 219815#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 219813#L754-3 assume 0 == ~M_E~0;~M_E~0 := 1; 219810#L754-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 219811#L759-3 assume !(0 == ~T2_E~0); 221969#L764-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 221967#L769-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 221965#L774-3 assume !(0 == ~T5_E~0); 221963#L779-3 assume !(0 == ~T6_E~0); 221961#L784-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 221959#L789-3 assume 0 == ~E_1~0;~E_1~0 := 1; 221957#L794-3 assume 0 == ~E_2~0;~E_2~0 := 1; 221955#L799-3 assume !(0 == ~E_3~0); 221953#L804-3 assume 0 == ~E_4~0;~E_4~0 := 1; 221951#L809-3 assume 0 == ~E_5~0;~E_5~0 := 1; 221949#L814-3 assume !(0 == ~E_6~0); 221947#L819-3 assume !(0 == ~E_7~0); 221945#L824-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 221941#L361-24 assume !(1 == ~m_pc~0); 221939#L361-26 is_master_triggered_~__retres1~0#1 := 0; 221937#L372-8 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 221935#is_master_triggered_returnLabel#9 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 221932#L930-24 assume !(0 != activate_threads_~tmp~1#1); 221930#L930-26 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 221928#L380-24 assume 1 == ~t1_pc~0; 221926#L381-8 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 221927#L391-8 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 221978#is_transmit1_triggered_returnLabel#9 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 221918#L938-24 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 221916#L938-26 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 221914#L399-24 assume !(1 == ~t2_pc~0); 220401#L399-26 is_transmit2_triggered_~__retres1~2#1 := 0; 221910#L410-8 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 221909#is_transmit2_triggered_returnLabel#9 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 221908#L946-24 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 221907#L946-26 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 221906#L418-24 assume !(1 == ~t3_pc~0); 221904#L418-26 is_transmit3_triggered_~__retres1~3#1 := 0; 221900#L429-8 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 220397#is_transmit3_triggered_returnLabel#9 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 220398#L954-24 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 220391#L954-26 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 220392#L437-24 assume !(1 == ~t4_pc~0); 220387#L437-26 is_transmit4_triggered_~__retres1~4#1 := 0; 220388#L448-8 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 220381#is_transmit4_triggered_returnLabel#9 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 220382#L962-24 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 220377#L962-26 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 220378#L456-24 assume 1 == ~t5_pc~0; 220370#L457-8 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 220371#L467-8 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 220365#is_transmit5_triggered_returnLabel#9 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 220364#L970-24 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 220362#L970-26 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 219655#L475-24 assume !(1 == ~t6_pc~0); 219652#L475-26 is_transmit6_triggered_~__retres1~6#1 := 0; 219650#L486-8 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 219648#is_transmit6_triggered_returnLabel#9 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 219646#L978-24 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 219644#L978-26 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 219642#L494-24 assume !(1 == ~t7_pc~0); 219639#L494-26 is_transmit7_triggered_~__retres1~7#1 := 0; 219637#L505-8 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 219635#is_transmit7_triggered_returnLabel#9 activate_threads_#t~ret20#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 219633#L986-24 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 219631#L986-26 havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 219629#L837-3 assume 1 == ~M_E~0;~M_E~0 := 2; 219627#L837-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 219624#L842-3 assume !(1 == ~T2_E~0); 219622#L847-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 219620#L852-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 219618#L857-3 assume !(1 == ~T5_E~0); 219616#L862-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 219614#L867-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 219612#L872-3 assume 1 == ~E_1~0;~E_1~0 := 2; 219610#L877-3 assume !(1 == ~E_2~0); 219609#L882-3 assume 1 == ~E_3~0;~E_3~0 := 2; 219608#L887-3 assume 1 == ~E_4~0;~E_4~0 := 2; 219607#L892-3 assume 1 == ~E_5~0;~E_5~0 := 2; 219606#L897-3 assume !(1 == ~E_6~0); 219605#L902-3 assume !(1 == ~E_7~0); 219603#L907-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 219580#L569-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 219573#L611-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 219571#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret22#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret22#1;havoc start_simulation_#t~ret22#1; 219568#L1167 assume !(0 == start_simulation_~tmp~3#1); 219565#L1167-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret21#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 219563#L569-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 219549#L611-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 219540#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret21#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret21#1;havoc stop_simulation_#t~ret21#1; 219534#L1122 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 219527#L1129 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 219514#stop_simulation_returnLabel#1 start_simulation_#t~ret23#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret21#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret23#1;havoc start_simulation_#t~ret23#1; 219505#L1180 assume !(0 != start_simulation_~tmp___0~1#1); 215911#L1148-2 [2023-11-12 02:09:42,514 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-12 02:09:42,515 INFO L85 PathProgramCache]: Analyzing trace with hash -1286806590, now seen corresponding path program 1 times [2023-11-12 02:09:42,515 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-12 02:09:42,515 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1725230133] [2023-11-12 02:09:42,516 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-12 02:09:42,516 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-12 02:09:42,531 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-12 02:09:42,579 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-12 02:09:42,580 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-12 02:09:42,580 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1725230133] [2023-11-12 02:09:42,580 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1725230133] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-12 02:09:42,581 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-12 02:09:42,581 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2023-11-12 02:09:42,581 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [272945498] [2023-11-12 02:09:42,581 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-12 02:09:42,582 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-12 02:09:42,582 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-12 02:09:42,582 INFO L85 PathProgramCache]: Analyzing trace with hash 1752660673, now seen corresponding path program 1 times [2023-11-12 02:09:42,583 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-12 02:09:42,583 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1948368574] [2023-11-12 02:09:42,583 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-12 02:09:42,583 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-12 02:09:42,602 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-12 02:09:42,644 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-12 02:09:42,645 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-12 02:09:42,645 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1948368574] [2023-11-12 02:09:42,645 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1948368574] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-12 02:09:42,645 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-12 02:09:42,645 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-12 02:09:42,646 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [239530471] [2023-11-12 02:09:42,646 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-12 02:09:42,646 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-12 02:09:42,647 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-12 02:09:42,647 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-12 02:09:42,647 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-12 02:09:42,648 INFO L87 Difference]: Start difference. First operand 10323 states and 14340 transitions. cyclomatic complexity: 4021 Second operand has 3 states, 3 states have (on average 31.0) internal successors, (93), 2 states have internal predecessors, (93), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-12 02:09:42,726 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-12 02:09:42,727 INFO L93 Difference]: Finished difference Result 9084 states and 12587 transitions. [2023-11-12 02:09:42,727 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 9084 states and 12587 transitions. [2023-11-12 02:09:42,884 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 8960 [2023-11-12 02:09:42,932 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 9084 states to 9084 states and 12587 transitions. [2023-11-12 02:09:42,932 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 9084 [2023-11-12 02:09:42,938 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 9084 [2023-11-12 02:09:42,939 INFO L73 IsDeterministic]: Start isDeterministic. Operand 9084 states and 12587 transitions. [2023-11-12 02:09:42,947 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-12 02:09:42,948 INFO L218 hiAutomatonCegarLoop]: Abstraction has 9084 states and 12587 transitions. [2023-11-12 02:09:42,955 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 9084 states and 12587 transitions. [2023-11-12 02:09:43,041 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 9084 to 9084. [2023-11-12 02:09:43,052 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 9084 states, 9084 states have (on average 1.3856230735358872) internal successors, (12587), 9083 states have internal predecessors, (12587), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-12 02:09:43,077 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 9084 states to 9084 states and 12587 transitions. [2023-11-12 02:09:43,077 INFO L240 hiAutomatonCegarLoop]: Abstraction has 9084 states and 12587 transitions. [2023-11-12 02:09:43,078 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-12 02:09:43,078 INFO L428 stractBuchiCegarLoop]: Abstraction has 9084 states and 12587 transitions. [2023-11-12 02:09:43,078 INFO L335 stractBuchiCegarLoop]: ======== Iteration 21 ============ [2023-11-12 02:09:43,079 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 9084 states and 12587 transitions. [2023-11-12 02:09:43,112 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 8960 [2023-11-12 02:09:43,112 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-12 02:09:43,112 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-12 02:09:43,115 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-12 02:09:43,115 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-12 02:09:43,115 INFO L748 eck$LassoCheckResult]: Stem: 234808#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2; 234809#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~9#1;havoc main_~__retres1~9#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 235388#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret22#1, start_simulation_#t~ret23#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 235389#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 235427#L521 assume 1 == ~m_i~0;~m_st~0 := 0; 235413#L521-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 235414#L526-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 234963#L531-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 234964#L536-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 235033#L541-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 234876#L546-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 234877#L551-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 234840#L556-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 234841#L754 assume !(0 == ~M_E~0); 235441#L754-2 assume !(0 == ~T1_E~0); 235346#L759-1 assume !(0 == ~T2_E~0); 235215#L764-1 assume !(0 == ~T3_E~0); 235168#L769-1 assume !(0 == ~T4_E~0); 235169#L774-1 assume !(0 == ~T5_E~0); 235216#L779-1 assume !(0 == ~T6_E~0); 235357#L784-1 assume !(0 == ~T7_E~0); 235165#L789-1 assume !(0 == ~E_1~0); 235166#L794-1 assume !(0 == ~E_2~0); 235263#L799-1 assume !(0 == ~E_3~0); 235176#L804-1 assume !(0 == ~E_4~0); 235177#L809-1 assume !(0 == ~E_5~0); 235210#L814-1 assume !(0 == ~E_6~0); 234616#L819-1 assume !(0 == ~E_7~0); 234617#L824-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 234872#L361 assume !(1 == ~m_pc~0); 234873#L361-2 is_master_triggered_~__retres1~0#1 := 0; 235382#L372 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 235333#is_master_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 235334#L930 assume !(0 != activate_threads_~tmp~1#1); 235080#L930-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 234865#L380 assume !(1 == ~t1_pc~0); 234866#L380-2 is_transmit1_triggered_~__retres1~1#1 := 0; 235424#L391 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 235425#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 235468#L938 assume !(0 != activate_threads_~tmp___0~0#1); 235292#L938-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 235273#L399 assume !(1 == ~t2_pc~0); 234779#L399-2 is_transmit2_triggered_~__retres1~2#1 := 0; 234780#L410 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 234943#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 234936#L946 assume !(0 != activate_threads_~tmp___1~0#1); 234937#L946-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 234620#L418 assume !(1 == ~t3_pc~0); 234599#L418-2 is_transmit3_triggered_~__retres1~3#1 := 0; 234600#L429 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 234610#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 234611#L954 assume !(0 != activate_threads_~tmp___2~0#1); 235193#L954-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 235194#L437 assume !(1 == ~t4_pc~0); 235415#L437-2 is_transmit4_triggered_~__retres1~4#1 := 0; 235329#L448 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 234692#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 234693#L962 assume !(0 != activate_threads_~tmp___3~0#1); 234991#L962-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 235314#L456 assume !(1 == ~t5_pc~0); 234794#L456-2 is_transmit5_triggered_~__retres1~5#1 := 0; 234793#L467 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 235337#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 235250#L970 assume !(0 != activate_threads_~tmp___4~0#1); 235251#L970-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 234685#L475 assume !(1 == ~t6_pc~0); 234686#L475-2 is_transmit6_triggered_~__retres1~6#1 := 0; 234726#L486 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 234727#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 234929#L978 assume !(0 != activate_threads_~tmp___5~0#1); 235182#L978-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 235183#L494 assume !(1 == ~t7_pc~0); 234913#L494-2 is_transmit7_triggered_~__retres1~7#1 := 0; 234914#L505 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 235138#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 235217#L986 assume !(0 != activate_threads_~tmp___6~0#1); 235218#L986-2 havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 235433#L837 assume !(1 == ~M_E~0); 235387#L837-2 assume !(1 == ~T1_E~0); 235269#L842-1 assume !(1 == ~T2_E~0); 234998#L847-1 assume !(1 == ~T3_E~0); 234999#L852-1 assume !(1 == ~T4_E~0); 235070#L857-1 assume !(1 == ~T5_E~0); 234949#L862-1 assume !(1 == ~T6_E~0); 234950#L867-1 assume !(1 == ~T7_E~0); 234959#L872-1 assume !(1 == ~E_1~0); 235032#L877-1 assume !(1 == ~E_2~0); 235234#L882-1 assume !(1 == ~E_3~0); 235393#L887-1 assume !(1 == ~E_4~0); 235287#L892-1 assume !(1 == ~E_5~0); 235288#L897-1 assume !(1 == ~E_6~0); 234975#L902-1 assume !(1 == ~E_7~0); 234976#L907-1 assume { :end_inline_reset_delta_events } true; 235308#L1148-2 [2023-11-12 02:09:43,116 INFO L750 eck$LassoCheckResult]: Loop: 235308#L1148-2 assume !false; 237883#L1149 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 237881#L729-1 assume !false; 237879#L622 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 237774#L569 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 237767#L611 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 237765#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 237762#L626 assume !(0 != eval_~tmp~0#1); 237763#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 239644#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 239642#L754-3 assume 0 == ~M_E~0;~M_E~0 := 1; 239640#L754-5 assume !(0 == ~T1_E~0); 239638#L759-3 assume !(0 == ~T2_E~0); 239636#L764-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 239633#L769-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 239630#L774-3 assume !(0 == ~T5_E~0); 239627#L779-3 assume !(0 == ~T6_E~0); 239624#L784-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 239622#L789-3 assume 0 == ~E_1~0;~E_1~0 := 1; 239620#L794-3 assume 0 == ~E_2~0;~E_2~0 := 1; 239619#L799-3 assume !(0 == ~E_3~0); 239617#L804-3 assume 0 == ~E_4~0;~E_4~0 := 1; 239615#L809-3 assume 0 == ~E_5~0;~E_5~0 := 1; 239613#L814-3 assume !(0 == ~E_6~0); 239611#L819-3 assume !(0 == ~E_7~0); 239609#L824-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 239606#L361-24 assume !(1 == ~m_pc~0); 239604#L361-26 is_master_triggered_~__retres1~0#1 := 0; 239602#L372-8 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 239600#is_master_triggered_returnLabel#9 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 239598#L930-24 assume !(0 != activate_threads_~tmp~1#1); 239596#L930-26 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 239594#L380-24 assume 1 == ~t1_pc~0; 239591#L381-8 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 239588#L391-8 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 239585#is_transmit1_triggered_returnLabel#9 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 239582#L938-24 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 239580#L938-26 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 239577#L399-24 assume !(1 == ~t2_pc~0); 239505#L399-26 is_transmit2_triggered_~__retres1~2#1 := 0; 239574#L410-8 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 239571#is_transmit2_triggered_returnLabel#9 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 239570#L946-24 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 239569#L946-26 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 239568#L418-24 assume !(1 == ~t3_pc~0); 239566#L418-26 is_transmit3_triggered_~__retres1~3#1 := 0; 239563#L429-8 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 239561#is_transmit3_triggered_returnLabel#9 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 239559#L954-24 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 239557#L954-26 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 239555#L437-24 assume !(1 == ~t4_pc~0); 239553#L437-26 is_transmit4_triggered_~__retres1~4#1 := 0; 239551#L448-8 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 239549#is_transmit4_triggered_returnLabel#9 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 239547#L962-24 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 239545#L962-26 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 239543#L456-24 assume !(1 == ~t5_pc~0); 239541#L456-26 is_transmit5_triggered_~__retres1~5#1 := 0; 239538#L467-8 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 239536#is_transmit5_triggered_returnLabel#9 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 239534#L970-24 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 239532#L970-26 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 238735#L475-24 assume !(1 == ~t6_pc~0); 238730#L475-26 is_transmit6_triggered_~__retres1~6#1 := 0; 238725#L486-8 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 238722#is_transmit6_triggered_returnLabel#9 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 238719#L978-24 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 238715#L978-26 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 238711#L494-24 assume !(1 == ~t7_pc~0); 238706#L494-26 is_transmit7_triggered_~__retres1~7#1 := 0; 238701#L505-8 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 238697#is_transmit7_triggered_returnLabel#9 activate_threads_#t~ret20#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 238693#L986-24 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 238689#L986-26 havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 238684#L837-3 assume 1 == ~M_E~0;~M_E~0 := 2; 238679#L837-5 assume !(1 == ~T1_E~0); 238674#L842-3 assume !(1 == ~T2_E~0); 238669#L847-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 238665#L852-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 238660#L857-3 assume !(1 == ~T5_E~0); 238655#L862-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 238651#L867-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 238647#L872-3 assume 1 == ~E_1~0;~E_1~0 := 2; 238643#L877-3 assume !(1 == ~E_2~0); 238407#L882-3 assume 1 == ~E_3~0;~E_3~0 := 2; 238405#L887-3 assume 1 == ~E_4~0;~E_4~0 := 2; 238404#L892-3 assume 1 == ~E_5~0;~E_5~0 := 2; 238403#L897-3 assume !(1 == ~E_6~0); 238400#L902-3 assume !(1 == ~E_7~0); 238398#L907-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 238306#L569-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 238296#L611-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 238290#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret22#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret22#1;havoc start_simulation_#t~ret22#1; 238282#L1167 assume !(0 == start_simulation_~tmp~3#1); 238275#L1167-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret21#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 238258#L569-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 238250#L611-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 238249#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret21#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret21#1;havoc stop_simulation_#t~ret21#1; 238248#L1122 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 238236#L1129 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 238232#stop_simulation_returnLabel#1 start_simulation_#t~ret23#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret21#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret23#1;havoc start_simulation_#t~ret23#1; 238227#L1180 assume !(0 != start_simulation_~tmp___0~1#1); 235308#L1148-2 [2023-11-12 02:09:43,117 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-12 02:09:43,117 INFO L85 PathProgramCache]: Analyzing trace with hash 1968536774, now seen corresponding path program 2 times [2023-11-12 02:09:43,117 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-12 02:09:43,117 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1471728458] [2023-11-12 02:09:43,118 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-12 02:09:43,118 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-12 02:09:43,133 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-12 02:09:43,133 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-12 02:09:43,143 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-12 02:09:43,188 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-12 02:09:43,188 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-12 02:09:43,189 INFO L85 PathProgramCache]: Analyzing trace with hash 427301924, now seen corresponding path program 1 times [2023-11-12 02:09:43,189 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-12 02:09:43,189 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [535508847] [2023-11-12 02:09:43,191 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-12 02:09:43,191 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-12 02:09:43,214 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-12 02:09:43,248 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-12 02:09:43,248 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-12 02:09:43,249 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [535508847] [2023-11-12 02:09:43,249 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [535508847] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-12 02:09:43,249 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-12 02:09:43,249 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-12 02:09:43,249 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2040827230] [2023-11-12 02:09:43,250 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-12 02:09:43,250 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-12 02:09:43,250 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-12 02:09:43,250 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-12 02:09:43,251 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-12 02:09:43,251 INFO L87 Difference]: Start difference. First operand 9084 states and 12587 transitions. cyclomatic complexity: 3507 Second operand has 3 states, 3 states have (on average 34.0) internal successors, (102), 3 states have internal predecessors, (102), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-12 02:09:43,422 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-12 02:09:43,422 INFO L93 Difference]: Finished difference Result 15823 states and 21794 transitions. [2023-11-12 02:09:43,423 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 15823 states and 21794 transitions. [2023-11-12 02:09:43,645 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 15604 [2023-11-12 02:09:43,713 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 15823 states to 15823 states and 21794 transitions. [2023-11-12 02:09:43,713 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 15823 [2023-11-12 02:09:43,725 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 15823 [2023-11-12 02:09:43,725 INFO L73 IsDeterministic]: Start isDeterministic. Operand 15823 states and 21794 transitions. [2023-11-12 02:09:43,741 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-12 02:09:43,741 INFO L218 hiAutomatonCegarLoop]: Abstraction has 15823 states and 21794 transitions. [2023-11-12 02:09:43,756 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 15823 states and 21794 transitions. [2023-11-12 02:09:43,907 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 15823 to 15807. [2023-11-12 02:09:43,925 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 15807 states, 15807 states have (on average 1.3777440374517618) internal successors, (21778), 15806 states have internal predecessors, (21778), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-12 02:09:43,967 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 15807 states to 15807 states and 21778 transitions. [2023-11-12 02:09:43,968 INFO L240 hiAutomatonCegarLoop]: Abstraction has 15807 states and 21778 transitions. [2023-11-12 02:09:43,968 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-12 02:09:43,969 INFO L428 stractBuchiCegarLoop]: Abstraction has 15807 states and 21778 transitions. [2023-11-12 02:09:43,969 INFO L335 stractBuchiCegarLoop]: ======== Iteration 22 ============ [2023-11-12 02:09:43,969 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 15807 states and 21778 transitions. [2023-11-12 02:09:44,127 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 15588 [2023-11-12 02:09:44,128 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-12 02:09:44,128 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-12 02:09:44,131 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-12 02:09:44,131 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-12 02:09:44,131 INFO L748 eck$LassoCheckResult]: Stem: 259723#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2; 259724#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~9#1;havoc main_~__retres1~9#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 260332#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret22#1, start_simulation_#t~ret23#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 260333#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 260373#L521 assume 1 == ~m_i~0;~m_st~0 := 0; 260358#L521-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 260359#L526-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 259879#L531-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 259880#L536-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 259951#L541-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 259784#L546-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 259785#L551-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 259753#L556-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 259754#L754 assume !(0 == ~M_E~0); 260391#L754-2 assume !(0 == ~T1_E~0); 260278#L759-1 assume !(0 == ~T2_E~0); 260136#L764-1 assume !(0 == ~T3_E~0); 260090#L769-1 assume !(0 == ~T4_E~0); 260091#L774-1 assume !(0 == ~T5_E~0); 260137#L779-1 assume !(0 == ~T6_E~0); 260289#L784-1 assume !(0 == ~T7_E~0); 260087#L789-1 assume !(0 == ~E_1~0); 260088#L794-1 assume 0 == ~E_2~0;~E_2~0 := 1; 260183#L799-1 assume !(0 == ~E_3~0); 260100#L804-1 assume !(0 == ~E_4~0); 260101#L809-1 assume !(0 == ~E_5~0); 260313#L814-1 assume !(0 == ~E_6~0); 260314#L819-1 assume !(0 == ~E_7~0); 259846#L824-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 259847#L361 assume !(1 == ~m_pc~0); 260325#L361-2 is_master_triggered_~__retres1~0#1 := 0; 260326#L372 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 260264#is_master_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 260265#L930 assume !(0 != activate_threads_~tmp~1#1); 259997#L930-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 259998#L380 assume !(1 == ~t1_pc~0); 260197#L380-2 is_transmit1_triggered_~__retres1~1#1 := 0; 260421#L391 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 260459#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 260456#L938 assume !(0 != activate_threads_~tmp___0~0#1); 260455#L938-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 260454#L399 assume !(1 == ~t2_pc~0); 259694#L399-2 is_transmit2_triggered_~__retres1~2#1 := 0; 259695#L410 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 259859#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 259860#L946 assume !(0 != activate_threads_~tmp___1~0#1); 260453#L946-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 260452#L418 assume !(1 == ~t3_pc~0); 259512#L418-2 is_transmit3_triggered_~__retres1~3#1 := 0; 259513#L429 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 260451#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 260427#L954 assume !(0 != activate_threads_~tmp___2~0#1); 260428#L954-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 260392#L437 assume !(1 == ~t4_pc~0); 260393#L437-2 is_transmit4_triggered_~__retres1~4#1 := 0; 260450#L448 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 259604#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 259605#L962 assume !(0 != activate_threads_~tmp___3~0#1); 259908#L962-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 260448#L456 assume !(1 == ~t5_pc~0); 259709#L456-2 is_transmit5_triggered_~__retres1~5#1 := 0; 259708#L467 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 260447#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 260446#L970 assume !(0 != activate_threads_~tmp___4~0#1); 260409#L970-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 260410#L475 assume !(1 == ~t6_pc~0); 260050#L475-2 is_transmit6_triggered_~__retres1~6#1 := 0; 260051#L486 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 259842#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 259843#L978 assume !(0 != activate_threads_~tmp___5~0#1); 260164#L978-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 260311#L494 assume !(1 == ~t7_pc~0); 260044#L494-2 is_transmit7_triggered_~__retres1~7#1 := 0; 260443#L505 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 260442#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 260441#L986 assume !(0 != activate_threads_~tmp___6~0#1); 260440#L986-2 havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 260439#L837 assume !(1 == ~M_E~0); 260438#L837-2 assume !(1 == ~T1_E~0); 260437#L842-1 assume !(1 == ~T2_E~0); 260436#L847-1 assume !(1 == ~T3_E~0); 259986#L852-1 assume !(1 == ~T4_E~0); 259987#L857-1 assume !(1 == ~T5_E~0); 259866#L862-1 assume !(1 == ~T6_E~0); 259867#L867-1 assume !(1 == ~T7_E~0); 259875#L872-1 assume !(1 == ~E_1~0); 259950#L877-1 assume 1 == ~E_2~0;~E_2~0 := 2; 260153#L882-1 assume !(1 == ~E_3~0); 260338#L887-1 assume !(1 == ~E_4~0); 260213#L892-1 assume !(1 == ~E_5~0); 260214#L897-1 assume !(1 == ~E_6~0); 259890#L902-1 assume !(1 == ~E_7~0); 259891#L907-1 assume { :end_inline_reset_delta_events } true; 260237#L1148-2 [2023-11-12 02:09:44,132 INFO L750 eck$LassoCheckResult]: Loop: 260237#L1148-2 assume !false; 267355#L1149 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 267352#L729-1 assume !false; 267350#L622 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 267331#L569 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 267325#L611 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 267324#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 267321#L626 assume !(0 != eval_~tmp~0#1); 267322#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 268845#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 268840#L754-3 assume 0 == ~M_E~0;~M_E~0 := 1; 268835#L754-5 assume !(0 == ~T1_E~0); 268830#L759-3 assume !(0 == ~T2_E~0); 268825#L764-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 268821#L769-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 268817#L774-3 assume !(0 == ~T5_E~0); 268815#L779-3 assume !(0 == ~T6_E~0); 268811#L784-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 268807#L789-3 assume 0 == ~E_1~0;~E_1~0 := 1; 268802#L794-3 assume 0 == ~E_2~0;~E_2~0 := 1; 268803#L799-3 assume !(0 == ~E_3~0); 274724#L804-3 assume 0 == ~E_4~0;~E_4~0 := 1; 274723#L809-3 assume 0 == ~E_5~0;~E_5~0 := 1; 274722#L814-3 assume !(0 == ~E_6~0); 274721#L819-3 assume !(0 == ~E_7~0); 274719#L824-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 274718#L361-24 assume !(1 == ~m_pc~0); 274717#L361-26 is_master_triggered_~__retres1~0#1 := 0; 274716#L372-8 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 274715#is_master_triggered_returnLabel#9 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 274714#L930-24 assume !(0 != activate_threads_~tmp~1#1); 274713#L930-26 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 274712#L380-24 assume !(1 == ~t1_pc~0); 274710#L380-26 is_transmit1_triggered_~__retres1~1#1 := 0; 274708#L391-8 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 274706#is_transmit1_triggered_returnLabel#9 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 274705#L938-24 assume !(0 != activate_threads_~tmp___0~0#1); 274703#L938-26 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 260271#L399-24 assume !(1 == ~t2_pc~0); 260272#L399-26 is_transmit2_triggered_~__retres1~2#1 := 0; 274921#L410-8 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 274919#is_transmit2_triggered_returnLabel#9 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 273564#L946-24 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 273563#L946-26 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 273562#L418-24 assume 1 == ~t3_pc~0; 273560#L419-8 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 273558#L429-8 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 273556#is_transmit3_triggered_returnLabel#9 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 273554#L954-24 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 273552#L954-26 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 273550#L437-24 assume !(1 == ~t4_pc~0); 273548#L437-26 is_transmit4_triggered_~__retres1~4#1 := 0; 273546#L448-8 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 273543#is_transmit4_triggered_returnLabel#9 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 273541#L962-24 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 273539#L962-26 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 273538#L456-24 assume 1 == ~t5_pc~0; 273533#L457-8 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 273530#L467-8 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 273528#is_transmit5_triggered_returnLabel#9 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 273527#L970-24 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 273522#L970-26 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 267963#L475-24 assume !(1 == ~t6_pc~0); 267961#L475-26 is_transmit6_triggered_~__retres1~6#1 := 0; 267958#L486-8 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 267956#is_transmit6_triggered_returnLabel#9 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 267953#L978-24 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 267951#L978-26 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 267950#L494-24 assume !(1 == ~t7_pc~0); 267947#L494-26 is_transmit7_triggered_~__retres1~7#1 := 0; 267945#L505-8 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 267943#is_transmit7_triggered_returnLabel#9 activate_threads_#t~ret20#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 267941#L986-24 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 267940#L986-26 havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 267937#L837-3 assume 1 == ~M_E~0;~M_E~0 := 2; 267935#L837-5 assume !(1 == ~T1_E~0); 267933#L842-3 assume !(1 == ~T2_E~0); 267931#L847-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 267929#L852-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 267927#L857-3 assume !(1 == ~T5_E~0); 267925#L862-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 267923#L867-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 267921#L872-3 assume 1 == ~E_1~0;~E_1~0 := 2; 267674#L877-3 assume 1 == ~E_2~0;~E_2~0 := 2; 267671#L882-3 assume 1 == ~E_3~0;~E_3~0 := 2; 267669#L887-3 assume 1 == ~E_4~0;~E_4~0 := 2; 267666#L892-3 assume 1 == ~E_5~0;~E_5~0 := 2; 267664#L897-3 assume !(1 == ~E_6~0); 267662#L902-3 assume !(1 == ~E_7~0); 267598#L907-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 267454#L569-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 267448#L611-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 267446#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret22#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret22#1;havoc start_simulation_#t~ret22#1; 267444#L1167 assume !(0 == start_simulation_~tmp~3#1); 267442#L1167-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret21#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 267441#L569-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 267433#L611-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 267432#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret21#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret21#1;havoc stop_simulation_#t~ret21#1; 267431#L1122 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 267430#L1129 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 267429#stop_simulation_returnLabel#1 start_simulation_#t~ret23#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret21#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret23#1;havoc start_simulation_#t~ret23#1; 267427#L1180 assume !(0 != start_simulation_~tmp___0~1#1); 260237#L1148-2 [2023-11-12 02:09:44,132 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-12 02:09:44,133 INFO L85 PathProgramCache]: Analyzing trace with hash 1160880066, now seen corresponding path program 1 times [2023-11-12 02:09:44,133 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-12 02:09:44,133 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [17329154] [2023-11-12 02:09:44,133 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-12 02:09:44,134 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-12 02:09:44,145 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-12 02:09:44,186 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-12 02:09:44,186 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-12 02:09:44,186 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [17329154] [2023-11-12 02:09:44,187 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [17329154] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-12 02:09:44,187 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-12 02:09:44,187 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2023-11-12 02:09:44,187 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1755195914] [2023-11-12 02:09:44,187 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-12 02:09:44,188 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-12 02:09:44,188 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-12 02:09:44,189 INFO L85 PathProgramCache]: Analyzing trace with hash 445719553, now seen corresponding path program 1 times [2023-11-12 02:09:44,189 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-12 02:09:44,189 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1166056716] [2023-11-12 02:09:44,189 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-12 02:09:44,189 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-12 02:09:44,206 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-12 02:09:44,263 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-12 02:09:44,264 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-12 02:09:44,265 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1166056716] [2023-11-12 02:09:44,266 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1166056716] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-12 02:09:44,266 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-12 02:09:44,266 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2023-11-12 02:09:44,266 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [215052669] [2023-11-12 02:09:44,266 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-12 02:09:44,267 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-12 02:09:44,267 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-12 02:09:44,268 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-12 02:09:44,268 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-12 02:09:44,268 INFO L87 Difference]: Start difference. First operand 15807 states and 21778 transitions. cyclomatic complexity: 5975 Second operand has 3 states, 3 states have (on average 31.0) internal successors, (93), 2 states have internal predecessors, (93), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-12 02:09:44,362 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-12 02:09:44,362 INFO L93 Difference]: Finished difference Result 9076 states and 12469 transitions. [2023-11-12 02:09:44,362 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 9076 states and 12469 transitions. [2023-11-12 02:09:44,414 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 8952 [2023-11-12 02:09:44,454 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 9076 states to 9076 states and 12469 transitions. [2023-11-12 02:09:44,454 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 9076 [2023-11-12 02:09:44,462 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 9076 [2023-11-12 02:09:44,462 INFO L73 IsDeterministic]: Start isDeterministic. Operand 9076 states and 12469 transitions. [2023-11-12 02:09:44,472 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-12 02:09:44,472 INFO L218 hiAutomatonCegarLoop]: Abstraction has 9076 states and 12469 transitions. [2023-11-12 02:09:44,480 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 9076 states and 12469 transitions. [2023-11-12 02:09:44,561 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 9076 to 9076. [2023-11-12 02:09:44,571 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 9076 states, 9076 states have (on average 1.373843102688409) internal successors, (12469), 9075 states have internal predecessors, (12469), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-12 02:09:44,594 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 9076 states to 9076 states and 12469 transitions. [2023-11-12 02:09:44,595 INFO L240 hiAutomatonCegarLoop]: Abstraction has 9076 states and 12469 transitions. [2023-11-12 02:09:44,595 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-12 02:09:44,596 INFO L428 stractBuchiCegarLoop]: Abstraction has 9076 states and 12469 transitions. [2023-11-12 02:09:44,596 INFO L335 stractBuchiCegarLoop]: ======== Iteration 23 ============ [2023-11-12 02:09:44,596 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 9076 states and 12469 transitions. [2023-11-12 02:09:44,748 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 8952 [2023-11-12 02:09:44,749 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-12 02:09:44,749 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-12 02:09:44,751 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-12 02:09:44,752 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-12 02:09:44,752 INFO L748 eck$LassoCheckResult]: Stem: 284613#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2; 284614#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~9#1;havoc main_~__retres1~9#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 285193#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret22#1, start_simulation_#t~ret23#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 285194#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 285227#L521 assume 1 == ~m_i~0;~m_st~0 := 0; 285213#L521-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 285214#L526-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 284764#L531-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 284765#L536-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 284835#L541-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 284676#L546-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 284677#L551-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 284643#L556-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 284644#L754 assume !(0 == ~M_E~0); 285239#L754-2 assume !(0 == ~T1_E~0); 285149#L759-1 assume !(0 == ~T2_E~0); 285013#L764-1 assume !(0 == ~T3_E~0); 284970#L769-1 assume !(0 == ~T4_E~0); 284971#L774-1 assume !(0 == ~T5_E~0); 285014#L779-1 assume !(0 == ~T6_E~0); 285157#L784-1 assume !(0 == ~T7_E~0); 284967#L789-1 assume !(0 == ~E_1~0); 284968#L794-1 assume !(0 == ~E_2~0); 285060#L799-1 assume !(0 == ~E_3~0); 284977#L804-1 assume !(0 == ~E_4~0); 284978#L809-1 assume !(0 == ~E_5~0); 285007#L814-1 assume !(0 == ~E_6~0); 284420#L819-1 assume !(0 == ~E_7~0); 284421#L824-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 284672#L361 assume !(1 == ~m_pc~0); 284673#L361-2 is_master_triggered_~__retres1~0#1 := 0; 285188#L372 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 285135#is_master_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 285136#L930 assume !(0 != activate_threads_~tmp~1#1); 284878#L930-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 284666#L380 assume !(1 == ~t1_pc~0); 284667#L380-2 is_transmit1_triggered_~__retres1~1#1 := 0; 285224#L391 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 285225#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 285262#L938 assume !(0 != activate_threads_~tmp___0~0#1); 285091#L938-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 285070#L399 assume !(1 == ~t2_pc~0); 284582#L399-2 is_transmit2_triggered_~__retres1~2#1 := 0; 284583#L410 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 284746#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 284739#L946 assume !(0 != activate_threads_~tmp___1~0#1); 284740#L946-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 284424#L418 assume !(1 == ~t3_pc~0); 284404#L418-2 is_transmit3_triggered_~__retres1~3#1 := 0; 284405#L429 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 284414#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 284415#L954 assume !(0 != activate_threads_~tmp___2~0#1); 284993#L954-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 284994#L437 assume !(1 == ~t4_pc~0); 285215#L437-2 is_transmit4_triggered_~__retres1~4#1 := 0; 285130#L448 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 284497#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 284498#L962 assume !(0 != activate_threads_~tmp___3~0#1); 284792#L962-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 285116#L456 assume !(1 == ~t5_pc~0); 284597#L456-2 is_transmit5_triggered_~__retres1~5#1 := 0; 284596#L467 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 285139#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 285048#L970 assume !(0 != activate_threads_~tmp___4~0#1); 285049#L970-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 284489#L475 assume !(1 == ~t6_pc~0); 284490#L475-2 is_transmit6_triggered_~__retres1~6#1 := 0; 284531#L486 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 284532#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 284732#L978 assume !(0 != activate_threads_~tmp___5~0#1); 284983#L978-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 284984#L494 assume !(1 == ~t7_pc~0); 284716#L494-2 is_transmit7_triggered_~__retres1~7#1 := 0; 284717#L505 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 284936#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 285015#L986 assume !(0 != activate_threads_~tmp___6~0#1); 285016#L986-2 havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 285234#L837 assume !(1 == ~M_E~0); 285192#L837-2 assume !(1 == ~T1_E~0); 285066#L842-1 assume !(1 == ~T2_E~0); 284801#L847-1 assume !(1 == ~T3_E~0); 284802#L852-1 assume !(1 == ~T4_E~0); 284868#L857-1 assume !(1 == ~T5_E~0); 284752#L862-1 assume !(1 == ~T6_E~0); 284753#L867-1 assume !(1 == ~T7_E~0); 284760#L872-1 assume !(1 == ~E_1~0); 284834#L877-1 assume !(1 == ~E_2~0); 285030#L882-1 assume !(1 == ~E_3~0); 285199#L887-1 assume !(1 == ~E_4~0); 285086#L892-1 assume !(1 == ~E_5~0); 285087#L897-1 assume !(1 == ~E_6~0); 284776#L902-1 assume !(1 == ~E_7~0); 284777#L907-1 assume { :end_inline_reset_delta_events } true; 285110#L1148-2 [2023-11-12 02:09:44,753 INFO L750 eck$LassoCheckResult]: Loop: 285110#L1148-2 assume !false; 289976#L1149 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 289974#L729-1 assume !false; 289972#L622 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 289959#L569 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 289953#L611 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 289951#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 289948#L626 assume !(0 != eval_~tmp~0#1); 289949#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 291001#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 290999#L754-3 assume 0 == ~M_E~0;~M_E~0 := 1; 290997#L754-5 assume !(0 == ~T1_E~0); 290994#L759-3 assume !(0 == ~T2_E~0); 290992#L764-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 290990#L769-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 290989#L774-3 assume !(0 == ~T5_E~0); 290987#L779-3 assume !(0 == ~T6_E~0); 290985#L784-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 290983#L789-3 assume 0 == ~E_1~0;~E_1~0 := 1; 290981#L794-3 assume !(0 == ~E_2~0); 290979#L799-3 assume !(0 == ~E_3~0); 290976#L804-3 assume 0 == ~E_4~0;~E_4~0 := 1; 290974#L809-3 assume 0 == ~E_5~0;~E_5~0 := 1; 290972#L814-3 assume !(0 == ~E_6~0); 290970#L819-3 assume !(0 == ~E_7~0); 290968#L824-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 290966#L361-24 assume !(1 == ~m_pc~0); 290964#L361-26 is_master_triggered_~__retres1~0#1 := 0; 290962#L372-8 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 290960#is_master_triggered_returnLabel#9 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 290958#L930-24 assume !(0 != activate_threads_~tmp~1#1); 290956#L930-26 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 290954#L380-24 assume !(1 == ~t1_pc~0); 290949#L380-26 is_transmit1_triggered_~__retres1~1#1 := 0; 290947#L391-8 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 290945#is_transmit1_triggered_returnLabel#9 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 290943#L938-24 assume !(0 != activate_threads_~tmp___0~0#1); 290940#L938-26 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 290938#L399-24 assume !(1 == ~t2_pc~0); 288938#L399-26 is_transmit2_triggered_~__retres1~2#1 := 0; 290936#L410-8 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 290934#is_transmit2_triggered_returnLabel#9 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 290932#L946-24 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 290930#L946-26 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 290927#L418-24 assume 1 == ~t3_pc~0; 290924#L419-8 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 290922#L429-8 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 290920#is_transmit3_triggered_returnLabel#9 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 290918#L954-24 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 290916#L954-26 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 290914#L437-24 assume !(1 == ~t4_pc~0); 290912#L437-26 is_transmit4_triggered_~__retres1~4#1 := 0; 290910#L448-8 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 290908#is_transmit4_triggered_returnLabel#9 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 290906#L962-24 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 290904#L962-26 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 290902#L456-24 assume !(1 == ~t5_pc~0); 290900#L456-26 is_transmit5_triggered_~__retres1~5#1 := 0; 290897#L467-8 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 290895#is_transmit5_triggered_returnLabel#9 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 290893#L970-24 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 290891#L970-26 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 290889#L475-24 assume !(1 == ~t6_pc~0); 289692#L475-26 is_transmit6_triggered_~__retres1~6#1 := 0; 290886#L486-8 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 290885#is_transmit6_triggered_returnLabel#9 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 290884#L978-24 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 290883#L978-26 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 290882#L494-24 assume !(1 == ~t7_pc~0); 290880#L494-26 is_transmit7_triggered_~__retres1~7#1 := 0; 290879#L505-8 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 290877#is_transmit7_triggered_returnLabel#9 activate_threads_#t~ret20#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 290876#L986-24 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 290875#L986-26 havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 290874#L837-3 assume 1 == ~M_E~0;~M_E~0 := 2; 290872#L837-5 assume !(1 == ~T1_E~0); 290870#L842-3 assume !(1 == ~T2_E~0); 290868#L847-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 290866#L852-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 290864#L857-3 assume !(1 == ~T5_E~0); 290862#L862-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 290860#L867-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 290858#L872-3 assume 1 == ~E_1~0;~E_1~0 := 2; 290854#L877-3 assume !(1 == ~E_2~0); 290852#L882-3 assume 1 == ~E_3~0;~E_3~0 := 2; 290850#L887-3 assume 1 == ~E_4~0;~E_4~0 := 2; 290848#L892-3 assume 1 == ~E_5~0;~E_5~0 := 2; 290845#L897-3 assume !(1 == ~E_6~0); 290843#L902-3 assume !(1 == ~E_7~0); 290840#L907-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 290828#L569-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 290822#L611-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 290820#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret22#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret22#1;havoc start_simulation_#t~ret22#1; 290817#L1167 assume !(0 == start_simulation_~tmp~3#1); 290814#L1167-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret21#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 290052#L569-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 290043#L611-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 290041#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret21#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret21#1;havoc stop_simulation_#t~ret21#1; 290038#L1122 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 290036#L1129 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 290034#stop_simulation_returnLabel#1 start_simulation_#t~ret23#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret21#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret23#1;havoc start_simulation_#t~ret23#1; 290032#L1180 assume !(0 != start_simulation_~tmp___0~1#1); 285110#L1148-2 [2023-11-12 02:09:44,754 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-12 02:09:44,754 INFO L85 PathProgramCache]: Analyzing trace with hash 1968536774, now seen corresponding path program 3 times [2023-11-12 02:09:44,754 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-12 02:09:44,756 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1065118876] [2023-11-12 02:09:44,756 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-12 02:09:44,757 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-12 02:09:44,774 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-12 02:09:44,774 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-12 02:09:44,792 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-12 02:09:44,829 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-12 02:09:44,830 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-12 02:09:44,830 INFO L85 PathProgramCache]: Analyzing trace with hash -1226372764, now seen corresponding path program 1 times [2023-11-12 02:09:44,831 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-12 02:09:44,831 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [126813498] [2023-11-12 02:09:44,831 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-12 02:09:44,831 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-12 02:09:44,850 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-12 02:09:44,931 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-12 02:09:44,931 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-12 02:09:44,932 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [126813498] [2023-11-12 02:09:44,932 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [126813498] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-12 02:09:44,932 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-12 02:09:44,932 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2023-11-12 02:09:44,933 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1643052908] [2023-11-12 02:09:44,933 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-12 02:09:44,933 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-12 02:09:44,934 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-12 02:09:44,934 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2023-11-12 02:09:44,934 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2023-11-12 02:09:44,935 INFO L87 Difference]: Start difference. First operand 9076 states and 12469 transitions. cyclomatic complexity: 3397 Second operand has 5 states, 5 states have (on average 20.4) internal successors, (102), 5 states have internal predecessors, (102), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-12 02:09:45,207 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-12 02:09:45,208 INFO L93 Difference]: Finished difference Result 16436 states and 22357 transitions. [2023-11-12 02:09:45,208 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 16436 states and 22357 transitions. [2023-11-12 02:09:45,314 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 16288 [2023-11-12 02:09:45,383 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 16436 states to 16436 states and 22357 transitions. [2023-11-12 02:09:45,384 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 16436 [2023-11-12 02:09:45,396 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 16436 [2023-11-12 02:09:45,396 INFO L73 IsDeterministic]: Start isDeterministic. Operand 16436 states and 22357 transitions. [2023-11-12 02:09:45,413 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-12 02:09:45,413 INFO L218 hiAutomatonCegarLoop]: Abstraction has 16436 states and 22357 transitions. [2023-11-12 02:09:45,429 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 16436 states and 22357 transitions. [2023-11-12 02:09:45,576 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 16436 to 9124. [2023-11-12 02:09:45,588 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 9124 states, 9124 states have (on average 1.3718763700131522) internal successors, (12517), 9123 states have internal predecessors, (12517), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-12 02:09:45,617 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 9124 states to 9124 states and 12517 transitions. [2023-11-12 02:09:45,618 INFO L240 hiAutomatonCegarLoop]: Abstraction has 9124 states and 12517 transitions. [2023-11-12 02:09:45,618 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 9 states. [2023-11-12 02:09:45,619 INFO L428 stractBuchiCegarLoop]: Abstraction has 9124 states and 12517 transitions. [2023-11-12 02:09:45,620 INFO L335 stractBuchiCegarLoop]: ======== Iteration 24 ============ [2023-11-12 02:09:45,620 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 9124 states and 12517 transitions. [2023-11-12 02:09:45,661 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 9000 [2023-11-12 02:09:45,662 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-12 02:09:45,662 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-12 02:09:45,665 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-12 02:09:45,665 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-12 02:09:45,666 INFO L748 eck$LassoCheckResult]: Stem: 310145#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2; 310146#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~9#1;havoc main_~__retres1~9#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 310743#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret22#1, start_simulation_#t~ret23#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 310744#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 310786#L521 assume 1 == ~m_i~0;~m_st~0 := 0; 310769#L521-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 310770#L526-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 310299#L531-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 310300#L536-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 310371#L541-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 310210#L546-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 310211#L551-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 310178#L556-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 310179#L754 assume !(0 == ~M_E~0); 310797#L754-2 assume !(0 == ~T1_E~0); 310693#L759-1 assume !(0 == ~T2_E~0); 310552#L764-1 assume !(0 == ~T3_E~0); 310507#L769-1 assume !(0 == ~T4_E~0); 310508#L774-1 assume !(0 == ~T5_E~0); 310553#L779-1 assume !(0 == ~T6_E~0); 310702#L784-1 assume !(0 == ~T7_E~0); 310504#L789-1 assume !(0 == ~E_1~0); 310505#L794-1 assume !(0 == ~E_2~0); 310602#L799-1 assume !(0 == ~E_3~0); 310516#L804-1 assume !(0 == ~E_4~0); 310517#L809-1 assume !(0 == ~E_5~0); 310546#L814-1 assume !(0 == ~E_6~0); 309950#L819-1 assume !(0 == ~E_7~0); 309951#L824-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 310206#L361 assume !(1 == ~m_pc~0); 310207#L361-2 is_master_triggered_~__retres1~0#1 := 0; 310738#L372 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 310679#is_master_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 310680#L930 assume !(0 != activate_threads_~tmp~1#1); 310417#L930-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 310200#L380 assume !(1 == ~t1_pc~0); 310201#L380-2 is_transmit1_triggered_~__retres1~1#1 := 0; 310783#L391 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 310784#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 310819#L938 assume !(0 != activate_threads_~tmp___0~0#1); 310633#L938-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 310613#L399 assume !(1 == ~t2_pc~0); 310114#L399-2 is_transmit2_triggered_~__retres1~2#1 := 0; 310115#L410 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 310279#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 310272#L946 assume !(0 != activate_threads_~tmp___1~0#1); 310273#L946-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 309954#L418 assume !(1 == ~t3_pc~0); 309933#L418-2 is_transmit3_triggered_~__retres1~3#1 := 0; 309934#L429 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 309944#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 309945#L954 assume !(0 != activate_threads_~tmp___2~0#1); 310531#L954-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 310532#L437 assume !(1 == ~t4_pc~0); 310771#L437-2 is_transmit4_triggered_~__retres1~4#1 := 0; 310674#L448 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 310026#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 310027#L962 assume !(0 != activate_threads_~tmp___3~0#1); 310328#L962-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 310659#L456 assume !(1 == ~t5_pc~0); 310128#L456-2 is_transmit5_triggered_~__retres1~5#1 := 0; 310127#L467 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 310683#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 310590#L970 assume !(0 != activate_threads_~tmp___4~0#1); 310591#L970-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 310019#L475 assume !(1 == ~t6_pc~0); 310020#L475-2 is_transmit6_triggered_~__retres1~6#1 := 0; 310060#L486 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 310061#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 310265#L978 assume !(0 != activate_threads_~tmp___5~0#1); 310521#L978-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 310522#L494 assume !(1 == ~t7_pc~0); 310249#L494-2 is_transmit7_triggered_~__retres1~7#1 := 0; 310250#L505 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 310475#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 310554#L986 assume !(0 != activate_threads_~tmp___6~0#1); 310555#L986-2 havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 310791#L837 assume !(1 == ~M_E~0); 310742#L837-2 assume !(1 == ~T1_E~0); 310608#L842-1 assume !(1 == ~T2_E~0); 310337#L847-1 assume !(1 == ~T3_E~0); 310338#L852-1 assume !(1 == ~T4_E~0); 310406#L857-1 assume !(1 == ~T5_E~0); 310285#L862-1 assume !(1 == ~T6_E~0); 310286#L867-1 assume !(1 == ~T7_E~0); 310295#L872-1 assume !(1 == ~E_1~0); 310370#L877-1 assume !(1 == ~E_2~0); 310571#L882-1 assume !(1 == ~E_3~0); 310750#L887-1 assume !(1 == ~E_4~0); 310627#L892-1 assume !(1 == ~E_5~0); 310628#L897-1 assume !(1 == ~E_6~0); 310312#L902-1 assume !(1 == ~E_7~0); 310313#L907-1 assume { :end_inline_reset_delta_events } true; 310653#L1148-2 [2023-11-12 02:09:45,667 INFO L750 eck$LassoCheckResult]: Loop: 310653#L1148-2 assume !false; 314575#L1149 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 314574#L729-1 assume !false; 314572#L622 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 314560#L569 assume !(0 == ~m_st~0); 314561#L573 assume !(0 == ~t1_st~0); 314563#L577 assume !(0 == ~t2_st~0); 314558#L581 assume !(0 == ~t3_st~0); 314559#L585 assume !(0 == ~t4_st~0); 314562#L589 assume !(0 == ~t5_st~0); 314555#L593 assume !(0 == ~t6_st~0); 314557#L597 assume !(0 == ~t7_st~0);exists_runnable_thread_~__retres1~8#1 := 0; 314553#L611 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 314550#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 314551#L626 assume !(0 != eval_~tmp~0#1); 316033#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 316032#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 316031#L754-3 assume 0 == ~M_E~0;~M_E~0 := 1; 316030#L754-5 assume !(0 == ~T1_E~0); 316029#L759-3 assume !(0 == ~T2_E~0); 316028#L764-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 316027#L769-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 316026#L774-3 assume !(0 == ~T5_E~0); 316025#L779-3 assume !(0 == ~T6_E~0); 316024#L784-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 316023#L789-3 assume 0 == ~E_1~0;~E_1~0 := 1; 316022#L794-3 assume !(0 == ~E_2~0); 316021#L799-3 assume !(0 == ~E_3~0); 316020#L804-3 assume 0 == ~E_4~0;~E_4~0 := 1; 316018#L809-3 assume 0 == ~E_5~0;~E_5~0 := 1; 316016#L814-3 assume !(0 == ~E_6~0); 316014#L819-3 assume !(0 == ~E_7~0); 316012#L824-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 316010#L361-24 assume !(1 == ~m_pc~0); 316008#L361-26 is_master_triggered_~__retres1~0#1 := 0; 316006#L372-8 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 316004#is_master_triggered_returnLabel#9 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 316002#L930-24 assume !(0 != activate_threads_~tmp~1#1); 316000#L930-26 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 315998#L380-24 assume !(1 == ~t1_pc~0); 315996#L380-26 is_transmit1_triggered_~__retres1~1#1 := 0; 315993#L391-8 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 315990#is_transmit1_triggered_returnLabel#9 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 315987#L938-24 assume !(0 != activate_threads_~tmp___0~0#1); 315984#L938-26 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 314737#L399-24 assume !(1 == ~t2_pc~0); 314738#L399-26 is_transmit2_triggered_~__retres1~2#1 := 0; 314731#L410-8 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 314732#is_transmit2_triggered_returnLabel#9 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 314724#L946-24 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 314725#L946-26 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 314717#L418-24 assume 1 == ~t3_pc~0; 314718#L419-8 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 314710#L429-8 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 314711#is_transmit3_triggered_returnLabel#9 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 314704#L954-24 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 314705#L954-26 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 314698#L437-24 assume !(1 == ~t4_pc~0); 314699#L437-26 is_transmit4_triggered_~__retres1~4#1 := 0; 314692#L448-8 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 314693#is_transmit4_triggered_returnLabel#9 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 314686#L962-24 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 314687#L962-26 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 314679#L456-24 assume 1 == ~t5_pc~0; 314680#L457-8 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 314672#L467-8 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 314673#is_transmit5_triggered_returnLabel#9 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 314666#L970-24 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 314667#L970-26 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 314662#L475-24 assume !(1 == ~t6_pc~0); 314661#L475-26 is_transmit6_triggered_~__retres1~6#1 := 0; 314660#L486-8 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 314659#is_transmit6_triggered_returnLabel#9 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 314658#L978-24 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 314657#L978-26 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 314656#L494-24 assume !(1 == ~t7_pc~0); 314654#L494-26 is_transmit7_triggered_~__retres1~7#1 := 0; 314653#L505-8 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 314652#is_transmit7_triggered_returnLabel#9 activate_threads_#t~ret20#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 314651#L986-24 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 314650#L986-26 havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 314649#L837-3 assume 1 == ~M_E~0;~M_E~0 := 2; 314648#L837-5 assume !(1 == ~T1_E~0); 314647#L842-3 assume !(1 == ~T2_E~0); 314646#L847-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 314645#L852-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 314644#L857-3 assume !(1 == ~T5_E~0); 314643#L862-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 314642#L867-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 314641#L872-3 assume 1 == ~E_1~0;~E_1~0 := 2; 314640#L877-3 assume !(1 == ~E_2~0); 314639#L882-3 assume 1 == ~E_3~0;~E_3~0 := 2; 314638#L887-3 assume 1 == ~E_4~0;~E_4~0 := 2; 314637#L892-3 assume 1 == ~E_5~0;~E_5~0 := 2; 314636#L897-3 assume !(1 == ~E_6~0); 314635#L902-3 assume !(1 == ~E_7~0); 314634#L907-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 314630#L569-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 314624#L611-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 314622#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret22#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret22#1;havoc start_simulation_#t~ret22#1; 314619#L1167 assume !(0 == start_simulation_~tmp~3#1); 314617#L1167-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret21#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 314616#L569-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 314606#L611-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 314604#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret21#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret21#1;havoc stop_simulation_#t~ret21#1; 314602#L1122 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 314600#L1129 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 314598#stop_simulation_returnLabel#1 start_simulation_#t~ret23#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret21#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret23#1;havoc start_simulation_#t~ret23#1; 314596#L1180 assume !(0 != start_simulation_~tmp___0~1#1); 310653#L1148-2 [2023-11-12 02:09:45,668 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-12 02:09:45,668 INFO L85 PathProgramCache]: Analyzing trace with hash 1968536774, now seen corresponding path program 4 times [2023-11-12 02:09:45,668 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-12 02:09:45,668 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1672417400] [2023-11-12 02:09:45,669 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-12 02:09:45,669 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-12 02:09:45,687 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-12 02:09:45,687 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-12 02:09:45,699 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-12 02:09:45,739 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-12 02:09:45,740 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-12 02:09:45,740 INFO L85 PathProgramCache]: Analyzing trace with hash 769276425, now seen corresponding path program 1 times [2023-11-12 02:09:45,740 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-12 02:09:45,740 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [671774436] [2023-11-12 02:09:45,741 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-12 02:09:45,741 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-12 02:09:45,757 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-12 02:09:45,801 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-12 02:09:45,802 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-12 02:09:45,802 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [671774436] [2023-11-12 02:09:45,802 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [671774436] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-12 02:09:45,803 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-12 02:09:45,803 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-12 02:09:45,803 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1918906569] [2023-11-12 02:09:45,803 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-12 02:09:45,804 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-12 02:09:45,804 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-12 02:09:45,804 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-12 02:09:45,804 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-12 02:09:45,805 INFO L87 Difference]: Start difference. First operand 9124 states and 12517 transitions. cyclomatic complexity: 3397 Second operand has 3 states, 3 states have (on average 36.333333333333336) internal successors, (109), 3 states have internal predecessors, (109), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-12 02:09:45,965 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-12 02:09:45,966 INFO L93 Difference]: Finished difference Result 17244 states and 23365 transitions. [2023-11-12 02:09:45,966 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 17244 states and 23365 transitions. [2023-11-12 02:09:46,063 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 17104 [2023-11-12 02:09:46,127 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 17244 states to 17244 states and 23365 transitions. [2023-11-12 02:09:46,128 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 17244 [2023-11-12 02:09:46,140 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 17244 [2023-11-12 02:09:46,140 INFO L73 IsDeterministic]: Start isDeterministic. Operand 17244 states and 23365 transitions. [2023-11-12 02:09:46,260 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-12 02:09:46,260 INFO L218 hiAutomatonCegarLoop]: Abstraction has 17244 states and 23365 transitions. [2023-11-12 02:09:46,273 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 17244 states and 23365 transitions. [2023-11-12 02:09:46,407 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 17244 to 16808. [2023-11-12 02:09:46,423 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 16808 states, 16808 states have (on average 1.3565564017134697) internal successors, (22801), 16807 states have internal predecessors, (22801), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-12 02:09:46,459 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 16808 states to 16808 states and 22801 transitions. [2023-11-12 02:09:46,460 INFO L240 hiAutomatonCegarLoop]: Abstraction has 16808 states and 22801 transitions. [2023-11-12 02:09:46,460 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-12 02:09:46,460 INFO L428 stractBuchiCegarLoop]: Abstraction has 16808 states and 22801 transitions. [2023-11-12 02:09:46,461 INFO L335 stractBuchiCegarLoop]: ======== Iteration 25 ============ [2023-11-12 02:09:46,461 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 16808 states and 22801 transitions. [2023-11-12 02:09:46,517 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 16668 [2023-11-12 02:09:46,517 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-12 02:09:46,517 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-12 02:09:46,520 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-12 02:09:46,520 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-12 02:09:46,520 INFO L748 eck$LassoCheckResult]: Stem: 336512#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2; 336513#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~9#1;havoc main_~__retres1~9#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 337113#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret22#1, start_simulation_#t~ret23#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 337114#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 337161#L521 assume 1 == ~m_i~0;~m_st~0 := 0; 337146#L521-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 337147#L526-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 336667#L531-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 336668#L536-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 336739#L541-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 336577#L546-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 336578#L551-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 336543#L556-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 336544#L754 assume !(0 == ~M_E~0); 337178#L754-2 assume !(0 == ~T1_E~0); 337062#L759-1 assume !(0 == ~T2_E~0); 336917#L764-1 assume !(0 == ~T3_E~0); 336874#L769-1 assume !(0 == ~T4_E~0); 336875#L774-1 assume !(0 == ~T5_E~0); 336918#L779-1 assume !(0 == ~T6_E~0); 337072#L784-1 assume !(0 == ~T7_E~0); 336871#L789-1 assume !(0 == ~E_1~0); 336872#L794-1 assume !(0 == ~E_2~0); 336968#L799-1 assume !(0 == ~E_3~0); 336881#L804-1 assume !(0 == ~E_4~0); 336882#L809-1 assume !(0 == ~E_5~0); 336912#L814-1 assume !(0 == ~E_6~0); 336323#L819-1 assume !(0 == ~E_7~0); 336324#L824-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 336573#L361 assume !(1 == ~m_pc~0); 336574#L361-2 is_master_triggered_~__retres1~0#1 := 0; 337106#L372 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 337050#is_master_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 337051#L930 assume !(0 != activate_threads_~tmp~1#1); 336784#L930-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 336566#L380 assume !(1 == ~t1_pc~0); 336567#L380-2 is_transmit1_triggered_~__retres1~1#1 := 0; 337158#L391 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 337159#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 337209#L938 assume !(0 != activate_threads_~tmp___0~0#1); 337000#L938-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 336978#L399 assume !(1 == ~t2_pc~0); 336483#L399-2 is_transmit2_triggered_~__retres1~2#1 := 0; 336484#L410 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 336647#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 336640#L946 assume !(0 != activate_threads_~tmp___1~0#1); 336641#L946-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 336327#L418 assume !(1 == ~t3_pc~0); 336307#L418-2 is_transmit3_triggered_~__retres1~3#1 := 0; 336308#L429 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 336317#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 336318#L954 assume !(0 != activate_threads_~tmp___2~0#1); 336896#L954-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 336897#L437 assume !(1 == ~t4_pc~0); 337148#L437-2 is_transmit4_triggered_~__retres1~4#1 := 0; 337045#L448 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 336398#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 336399#L962 assume !(0 != activate_threads_~tmp___3~0#1); 336697#L962-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 337025#L456 assume !(1 == ~t5_pc~0); 336498#L456-2 is_transmit5_triggered_~__retres1~5#1 := 0; 336497#L467 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 337054#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 336953#L970 assume !(0 != activate_threads_~tmp___4~0#1); 336954#L970-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 336391#L475 assume !(1 == ~t6_pc~0); 336392#L475-2 is_transmit6_triggered_~__retres1~6#1 := 0; 336432#L486 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 336433#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 336632#L978 assume !(0 != activate_threads_~tmp___5~0#1); 336886#L978-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 336887#L494 assume !(1 == ~t7_pc~0); 336616#L494-2 is_transmit7_triggered_~__retres1~7#1 := 0; 336617#L505 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 336842#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 336919#L986 assume !(0 != activate_threads_~tmp___6~0#1); 336920#L986-2 havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 337170#L837 assume !(1 == ~M_E~0); 337112#L837-2 assume !(1 == ~T1_E~0); 336974#L842-1 assume !(1 == ~T2_E~0); 336705#L847-1 assume !(1 == ~T3_E~0); 336706#L852-1 assume !(1 == ~T4_E~0); 336774#L857-1 assume !(1 == ~T5_E~0); 336653#L862-1 assume !(1 == ~T6_E~0); 336654#L867-1 assume !(1 == ~T7_E~0); 336662#L872-1 assume !(1 == ~E_1~0); 336738#L877-1 assume !(1 == ~E_2~0); 336936#L882-1 assume !(1 == ~E_3~0); 337121#L887-1 assume !(1 == ~E_4~0); 336994#L892-1 assume !(1 == ~E_5~0); 336995#L897-1 assume !(1 == ~E_6~0); 336681#L902-1 assume !(1 == ~E_7~0); 336682#L907-1 assume { :end_inline_reset_delta_events } true; 337019#L1148-2 [2023-11-12 02:09:46,521 INFO L750 eck$LassoCheckResult]: Loop: 337019#L1148-2 assume !false; 352976#L1149 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 352975#L729-1 assume !false; 352974#L622 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 352973#L569 assume !(0 == ~m_st~0); 336515#L573 assume !(0 == ~t1_st~0); 336549#L577 assume !(0 == ~t2_st~0); 336551#L581 assume !(0 == ~t3_st~0); 337117#L585 assume !(0 == ~t4_st~0); 337052#L589 assume !(0 == ~t5_st~0); 337053#L593 assume !(0 == ~t6_st~0); 337156#L597 assume !(0 == ~t7_st~0);exists_runnable_thread_~__retres1~8#1 := 0; 337169#L611 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 352092#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 352069#L626 assume !(0 != eval_~tmp~0#1); 336996#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 336783#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 336589#L754-3 assume 0 == ~M_E~0;~M_E~0 := 1; 336332#L754-5 assume !(0 == ~T1_E~0); 336333#L759-3 assume !(0 == ~T2_E~0); 336715#L764-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 336716#L769-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 336898#L774-3 assume !(0 == ~T5_E~0); 336487#L779-3 assume !(0 == ~T6_E~0); 336328#L784-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 336329#L789-3 assume 0 == ~E_1~0;~E_1~0 := 1; 336319#L794-3 assume !(0 == ~E_2~0); 336320#L799-3 assume !(0 == ~E_3~0); 336372#L804-3 assume 0 == ~E_4~0;~E_4~0 := 1; 336596#L809-3 assume 0 == ~E_5~0;~E_5~0 := 1; 336368#L814-3 assume !(0 == ~E_6~0); 336369#L819-3 assume !(0 == ~E_7~0); 337034#L824-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 336734#L361-24 assume !(1 == ~m_pc~0); 336735#L361-26 is_master_triggered_~__retres1~0#1 := 0; 336824#L372-8 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 336419#is_master_triggered_returnLabel#9 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 336420#L930-24 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 337096#L930-26 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 337123#L380-24 assume !(1 == ~t1_pc~0); 352573#L380-26 is_transmit1_triggered_~__retres1~1#1 := 0; 352571#L391-8 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 352568#is_transmit1_triggered_returnLabel#9 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 352566#L938-24 assume !(0 != activate_threads_~tmp___0~0#1); 352563#L938-26 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 352561#L399-24 assume !(1 == ~t2_pc~0); 351868#L399-26 is_transmit2_triggered_~__retres1~2#1 := 0; 352558#L410-8 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 352556#is_transmit2_triggered_returnLabel#9 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 352554#L946-24 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 352552#L946-26 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 352550#L418-24 assume !(1 == ~t3_pc~0); 352548#L418-26 is_transmit3_triggered_~__retres1~3#1 := 0; 352545#L429-8 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 352543#is_transmit3_triggered_returnLabel#9 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 352541#L954-24 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 352539#L954-26 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 352537#L437-24 assume !(1 == ~t4_pc~0); 352535#L437-26 is_transmit4_triggered_~__retres1~4#1 := 0; 352533#L448-8 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 352531#is_transmit4_triggered_returnLabel#9 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 352529#L962-24 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 352527#L962-26 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 352526#L456-24 assume !(1 == ~t5_pc~0); 352525#L456-26 is_transmit5_triggered_~__retres1~5#1 := 0; 352523#L467-8 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 352522#is_transmit5_triggered_returnLabel#9 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 352521#L970-24 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 352520#L970-26 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 352519#L475-24 assume !(1 == ~t6_pc~0); 348386#L475-26 is_transmit6_triggered_~__retres1~6#1 := 0; 352518#L486-8 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 352517#is_transmit6_triggered_returnLabel#9 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 352516#L978-24 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 352515#L978-26 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 352514#L494-24 assume !(1 == ~t7_pc~0); 352512#L494-26 is_transmit7_triggered_~__retres1~7#1 := 0; 352511#L505-8 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 352510#is_transmit7_triggered_returnLabel#9 activate_threads_#t~ret20#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 352509#L986-24 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 352508#L986-26 havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 352507#L837-3 assume 1 == ~M_E~0;~M_E~0 := 2; 352506#L837-5 assume !(1 == ~T1_E~0); 352505#L842-3 assume !(1 == ~T2_E~0); 352504#L847-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 352503#L852-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 352502#L857-3 assume !(1 == ~T5_E~0); 352501#L862-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 337184#L867-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 336752#L872-3 assume 1 == ~E_1~0;~E_1~0 := 2; 336753#L877-3 assume !(1 == ~E_2~0); 336832#L882-3 assume 1 == ~E_3~0;~E_3~0 := 2; 336889#L887-3 assume 1 == ~E_4~0;~E_4~0 := 2; 336506#L892-3 assume 1 == ~E_5~0;~E_5~0 := 2; 336507#L897-3 assume !(1 == ~E_6~0); 337067#L902-3 assume !(1 == ~E_7~0); 336669#L907-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 336670#L569-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 352454#L611-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 352452#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret22#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret22#1;havoc start_simulation_#t~ret22#1; 352449#L1167 assume !(0 == start_simulation_~tmp~3#1); 352446#L1167-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret21#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 352442#L569-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 352444#L611-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 352988#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret21#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret21#1;havoc stop_simulation_#t~ret21#1; 352987#L1122 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 352986#L1129 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 352985#stop_simulation_returnLabel#1 start_simulation_#t~ret23#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret21#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret23#1;havoc start_simulation_#t~ret23#1; 352984#L1180 assume !(0 != start_simulation_~tmp___0~1#1); 337019#L1148-2 [2023-11-12 02:09:46,521 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-12 02:09:46,522 INFO L85 PathProgramCache]: Analyzing trace with hash 1968536774, now seen corresponding path program 5 times [2023-11-12 02:09:46,522 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-12 02:09:46,522 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [40811088] [2023-11-12 02:09:46,522 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-12 02:09:46,522 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-12 02:09:46,535 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-12 02:09:46,535 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-12 02:09:46,542 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-12 02:09:46,565 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-12 02:09:46,566 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-12 02:09:46,566 INFO L85 PathProgramCache]: Analyzing trace with hash -1757276535, now seen corresponding path program 1 times [2023-11-12 02:09:46,566 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-12 02:09:46,566 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [246859665] [2023-11-12 02:09:46,566 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-12 02:09:46,567 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-12 02:09:46,581 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-12 02:09:46,644 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-12 02:09:46,644 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-12 02:09:46,644 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [246859665] [2023-11-12 02:09:46,644 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [246859665] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-12 02:09:46,644 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-12 02:09:46,645 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2023-11-12 02:09:46,645 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1676910878] [2023-11-12 02:09:46,645 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-12 02:09:46,645 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-12 02:09:46,646 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-12 02:09:46,646 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2023-11-12 02:09:46,646 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2023-11-12 02:09:46,646 INFO L87 Difference]: Start difference. First operand 16808 states and 22801 transitions. cyclomatic complexity: 5997 Second operand has 5 states, 5 states have (on average 21.8) internal successors, (109), 5 states have internal predecessors, (109), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-12 02:09:46,948 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-12 02:09:46,948 INFO L93 Difference]: Finished difference Result 26026 states and 34970 transitions. [2023-11-12 02:09:46,948 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 26026 states and 34970 transitions. [2023-11-12 02:09:47,076 INFO L131 ngComponentsAnalysis]: Automaton has 6 accepting balls. 25868 [2023-11-12 02:09:47,154 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 26026 states to 26026 states and 34970 transitions. [2023-11-12 02:09:47,155 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 26026 [2023-11-12 02:09:47,171 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 26026 [2023-11-12 02:09:47,172 INFO L73 IsDeterministic]: Start isDeterministic. Operand 26026 states and 34970 transitions. [2023-11-12 02:09:47,403 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-12 02:09:47,403 INFO L218 hiAutomatonCegarLoop]: Abstraction has 26026 states and 34970 transitions. [2023-11-12 02:09:47,427 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 26026 states and 34970 transitions. [2023-11-12 02:09:47,588 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 26026 to 15882. [2023-11-12 02:09:47,604 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 15882 states, 15882 states have (on average 1.3440372749024052) internal successors, (21346), 15881 states have internal predecessors, (21346), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-12 02:09:47,639 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 15882 states to 15882 states and 21346 transitions. [2023-11-12 02:09:47,640 INFO L240 hiAutomatonCegarLoop]: Abstraction has 15882 states and 21346 transitions. [2023-11-12 02:09:47,640 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2023-11-12 02:09:47,641 INFO L428 stractBuchiCegarLoop]: Abstraction has 15882 states and 21346 transitions. [2023-11-12 02:09:47,641 INFO L335 stractBuchiCegarLoop]: ======== Iteration 26 ============ [2023-11-12 02:09:47,641 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 15882 states and 21346 transitions. [2023-11-12 02:09:47,694 INFO L131 ngComponentsAnalysis]: Automaton has 6 accepting balls. 15740 [2023-11-12 02:09:47,694 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-12 02:09:47,695 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-12 02:09:47,696 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-12 02:09:47,696 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-12 02:09:47,697 INFO L748 eck$LassoCheckResult]: Stem: 379364#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2; 379365#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~9#1;havoc main_~__retres1~9#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 379970#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret22#1, start_simulation_#t~ret23#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 379971#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 380003#L521 assume 1 == ~m_i~0;~m_st~0 := 0; 379989#L521-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 379990#L526-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 379514#L531-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 379515#L536-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 379587#L541-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 379425#L546-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 379426#L551-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 379393#L556-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 379394#L754 assume !(0 == ~M_E~0); 380022#L754-2 assume !(0 == ~T1_E~0); 379925#L759-1 assume !(0 == ~T2_E~0); 379773#L764-1 assume !(0 == ~T3_E~0); 379728#L769-1 assume !(0 == ~T4_E~0); 379729#L774-1 assume !(0 == ~T5_E~0); 379774#L779-1 assume !(0 == ~T6_E~0); 379937#L784-1 assume !(0 == ~T7_E~0); 379725#L789-1 assume !(0 == ~E_1~0); 379726#L794-1 assume !(0 == ~E_2~0); 379825#L799-1 assume !(0 == ~E_3~0); 379737#L804-1 assume !(0 == ~E_4~0); 379738#L809-1 assume !(0 == ~E_5~0); 379767#L814-1 assume !(0 == ~E_6~0); 379166#L819-1 assume !(0 == ~E_7~0); 379167#L824-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 379423#L361 assume !(1 == ~m_pc~0); 379424#L361-2 is_master_triggered_~__retres1~0#1 := 0; 379966#L372 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 379912#is_master_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 379913#L930 assume !(0 != activate_threads_~tmp~1#1); 379635#L930-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 379416#L380 assume !(1 == ~t1_pc~0); 379417#L380-2 is_transmit1_triggered_~__retres1~1#1 := 0; 380000#L391 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 380001#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 380048#L938 assume !(0 != activate_threads_~tmp___0~0#1); 379862#L938-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 379837#L399 assume !(1 == ~t2_pc~0); 379334#L399-2 is_transmit2_triggered_~__retres1~2#1 := 0; 379335#L410 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 379495#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 379488#L946 assume !(0 != activate_threads_~tmp___1~0#1); 379489#L946-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 379174#L418 assume !(1 == ~t3_pc~0); 379153#L418-2 is_transmit3_triggered_~__retres1~3#1 := 0; 379154#L429 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 379164#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 379165#L954 assume !(0 != activate_threads_~tmp___2~0#1); 379752#L954-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 379753#L437 assume !(1 == ~t4_pc~0); 379991#L437-2 is_transmit4_triggered_~__retres1~4#1 := 0; 379906#L448 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 379243#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 379244#L962 assume !(0 != activate_threads_~tmp___3~0#1); 379543#L962-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 379884#L456 assume !(1 == ~t5_pc~0); 379348#L456-2 is_transmit5_triggered_~__retres1~5#1 := 0; 379347#L467 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 379916#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 379806#L970 assume !(0 != activate_threads_~tmp___4~0#1); 379807#L970-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 379238#L475 assume !(1 == ~t6_pc~0); 379239#L475-2 is_transmit6_triggered_~__retres1~6#1 := 0; 379281#L486 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 379282#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 379481#L978 assume !(0 != activate_threads_~tmp___5~0#1); 379742#L978-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 379743#L494 assume !(1 == ~t7_pc~0); 379465#L494-2 is_transmit7_triggered_~__retres1~7#1 := 0; 379466#L505 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 379695#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 379775#L986 assume !(0 != activate_threads_~tmp___6~0#1); 379776#L986-2 havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 380012#L837 assume !(1 == ~M_E~0); 379969#L837-2 assume !(1 == ~T1_E~0); 379832#L842-1 assume !(1 == ~T2_E~0); 379552#L847-1 assume !(1 == ~T3_E~0); 379553#L852-1 assume !(1 == ~T4_E~0); 379624#L857-1 assume !(1 == ~T5_E~0); 379501#L862-1 assume !(1 == ~T6_E~0); 379502#L867-1 assume !(1 == ~T7_E~0); 379510#L872-1 assume !(1 == ~E_1~0); 379586#L877-1 assume !(1 == ~E_2~0); 379791#L882-1 assume !(1 == ~E_3~0); 379974#L887-1 assume !(1 == ~E_4~0); 379857#L892-1 assume !(1 == ~E_5~0); 379858#L897-1 assume !(1 == ~E_6~0); 379525#L902-1 assume !(1 == ~E_7~0); 379526#L907-1 assume { :end_inline_reset_delta_events } true; 379883#L1148-2 assume !false; 383756#L1149 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 383754#L729-1 [2023-11-12 02:09:47,698 INFO L750 eck$LassoCheckResult]: Loop: 383754#L729-1 assume !false; 383752#L622 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 383741#L569 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 383735#L611 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 383728#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 383720#L626 assume 0 != eval_~tmp~0#1; 383321#L626-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;havoc eval_#t~nondet5#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet5#1;havoc eval_#t~nondet5#1; 383316#L634 assume !(0 != eval_~tmp_ndt_1~0#1); 383314#L634-2 havoc eval_~tmp_ndt_1~0#1; 383311#L631-1 assume !(0 == ~t1_st~0); 383306#L645-1 assume !(0 == ~t2_st~0); 383303#L659-1 assume !(0 == ~t3_st~0); 383299#L673-1 assume !(0 == ~t4_st~0); 382276#L687-1 assume !(0 == ~t5_st~0); 381994#L701-1 assume !(0 == ~t6_st~0); 381995#L715-1 assume !(0 == ~t7_st~0); 383754#L729-1 [2023-11-12 02:09:47,698 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-12 02:09:47,698 INFO L85 PathProgramCache]: Analyzing trace with hash 1978243464, now seen corresponding path program 1 times [2023-11-12 02:09:47,699 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-12 02:09:47,699 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [927022099] [2023-11-12 02:09:47,699 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-12 02:09:47,699 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-12 02:09:47,714 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-12 02:09:47,715 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-12 02:09:47,723 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-12 02:09:47,747 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-12 02:09:47,748 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-12 02:09:47,748 INFO L85 PathProgramCache]: Analyzing trace with hash -1739844173, now seen corresponding path program 1 times [2023-11-12 02:09:47,748 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-12 02:09:47,749 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1648301260] [2023-11-12 02:09:47,749 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-12 02:09:47,749 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-12 02:09:47,754 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-12 02:09:47,754 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-12 02:09:47,757 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-12 02:09:47,759 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-12 02:09:47,760 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-12 02:09:47,760 INFO L85 PathProgramCache]: Analyzing trace with hash 729268538, now seen corresponding path program 1 times [2023-11-12 02:09:47,760 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-12 02:09:47,760 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2078731758] [2023-11-12 02:09:47,760 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-12 02:09:47,760 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-12 02:09:47,774 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-12 02:09:47,810 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-12 02:09:47,810 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-12 02:09:47,811 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2078731758] [2023-11-12 02:09:47,811 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2078731758] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-12 02:09:47,811 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-12 02:09:47,811 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-12 02:09:47,811 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1553742256] [2023-11-12 02:09:47,812 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-12 02:09:47,974 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-12 02:09:47,974 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-12 02:09:47,975 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-12 02:09:47,975 INFO L87 Difference]: Start difference. First operand 15882 states and 21346 transitions. cyclomatic complexity: 5470 Second operand has 3 states, 3 states have (on average 37.0) internal successors, (111), 3 states have internal predecessors, (111), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-12 02:09:48,125 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-12 02:09:48,125 INFO L93 Difference]: Finished difference Result 30078 states and 40157 transitions. [2023-11-12 02:09:48,125 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 30078 states and 40157 transitions. [2023-11-12 02:09:48,264 INFO L131 ngComponentsAnalysis]: Automaton has 6 accepting balls. 29800 [2023-11-12 02:09:48,351 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 30078 states to 30078 states and 40157 transitions. [2023-11-12 02:09:48,351 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 30078 [2023-11-12 02:09:48,370 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 30078 [2023-11-12 02:09:48,370 INFO L73 IsDeterministic]: Start isDeterministic. Operand 30078 states and 40157 transitions. [2023-11-12 02:09:48,600 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-12 02:09:48,620 INFO L218 hiAutomatonCegarLoop]: Abstraction has 30078 states and 40157 transitions. [2023-11-12 02:09:48,649 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 30078 states and 40157 transitions. [2023-11-12 02:09:48,888 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 30078 to 28670. [2023-11-12 02:09:48,914 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 28670 states, 28670 states have (on average 1.3370422043948378) internal successors, (38333), 28669 states have internal predecessors, (38333), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-12 02:09:48,983 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 28670 states to 28670 states and 38333 transitions. [2023-11-12 02:09:48,984 INFO L240 hiAutomatonCegarLoop]: Abstraction has 28670 states and 38333 transitions. [2023-11-12 02:09:48,985 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-12 02:09:48,985 INFO L428 stractBuchiCegarLoop]: Abstraction has 28670 states and 38333 transitions. [2023-11-12 02:09:48,985 INFO L335 stractBuchiCegarLoop]: ======== Iteration 27 ============ [2023-11-12 02:09:48,986 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 28670 states and 38333 transitions. [2023-11-12 02:09:49,079 INFO L131 ngComponentsAnalysis]: Automaton has 6 accepting balls. 28392 [2023-11-12 02:09:49,079 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-12 02:09:49,080 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-12 02:09:49,081 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-12 02:09:49,081 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-12 02:09:49,081 INFO L748 eck$LassoCheckResult]: Stem: 425332#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2; 425333#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~9#1;havoc main_~__retres1~9#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 426005#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret22#1, start_simulation_#t~ret23#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 426006#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 426068#L521 assume 1 == ~m_i~0;~m_st~0 := 0; 426039#L521-2 assume !(1 == ~t1_i~0);~t1_st~0 := 2; 426040#L526-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 426061#L531-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 425978#L536-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 425979#L541-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 425394#L546-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 425395#L551-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 425363#L556-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 425364#L754 assume !(0 == ~M_E~0); 426120#L754-2 assume !(0 == ~T1_E~0); 426121#L759-1 assume !(0 == ~T2_E~0); 425768#L764-1 assume !(0 == ~T3_E~0); 425769#L769-1 assume !(0 == ~T4_E~0); 425770#L774-1 assume !(0 == ~T5_E~0); 425771#L779-1 assume !(0 == ~T6_E~0); 425953#L784-1 assume !(0 == ~T7_E~0); 425954#L789-1 assume !(0 == ~E_1~0); 425831#L794-1 assume !(0 == ~E_2~0); 425832#L799-1 assume !(0 == ~E_3~0); 425726#L804-1 assume !(0 == ~E_4~0); 425727#L809-1 assume !(0 == ~E_5~0); 425980#L814-1 assume !(0 == ~E_6~0); 425981#L819-1 assume !(0 == ~E_7~0); 425456#L824-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 425457#L361 assume !(1 == ~m_pc~0); 425997#L361-2 is_master_triggered_~__retres1~0#1 := 0; 425998#L372 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 425924#is_master_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 425925#L930 assume !(0 != activate_threads_~tmp~1#1); 425615#L930-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 425616#L380 assume !(1 == ~t1_pc~0); 425844#L380-2 is_transmit1_triggered_~__retres1~1#1 := 0; 426142#L391 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 426157#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 426158#L938 assume !(0 != activate_threads_~tmp___0~0#1); 425870#L938-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 425871#L399 assume !(1 == ~t2_pc~0); 425301#L399-2 is_transmit2_triggered_~__retres1~2#1 := 0; 425302#L410 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 425469#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 425470#L946 assume !(0 != activate_threads_~tmp___1~0#1); 425820#L946-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 425821#L418 assume !(1 == ~t3_pc~0); 425121#L418-2 is_transmit3_triggered_~__retres1~3#1 := 0; 425122#L429 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 425131#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 425132#L954 assume !(0 != activate_threads_~tmp___2~0#1); 425745#L954-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 425746#L437 assume !(1 == ~t4_pc~0); 426042#L437-2 is_transmit4_triggered_~__retres1~4#1 := 0; 426043#L448 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 425213#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 425214#L962 assume !(0 != activate_threads_~tmp___3~0#1); 426021#L962-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 426022#L456 assume !(1 == ~t5_pc~0); 425316#L456-2 is_transmit5_triggered_~__retres1~5#1 := 0; 425315#L467 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 425928#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 425929#L970 assume !(0 != activate_threads_~tmp___4~0#1); 426118#L970-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 426119#L475 assume !(1 == ~t6_pc~0); 425674#L475-2 is_transmit6_triggered_~__retres1~6#1 := 0; 425675#L486 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 425452#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 425453#L978 assume !(0 != activate_threads_~tmp___5~0#1); 425732#L978-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 425733#L494 assume !(1 == ~t7_pc~0); 425436#L494-2 is_transmit7_triggered_~__retres1~7#1 := 0; 425437#L505 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 426113#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 426114#L986 assume !(0 != activate_threads_~tmp___6~0#1); 426138#L986-2 havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 426139#L837 assume !(1 == ~M_E~0); 426003#L837-2 assume !(1 == ~T1_E~0); 426004#L842-1 assume !(1 == ~T2_E~0); 425532#L847-1 assume !(1 == ~T3_E~0); 425533#L852-1 assume !(1 == ~T4_E~0); 426153#L857-1 assume !(1 == ~T5_E~0); 426154#L862-1 assume !(1 == ~T6_E~0); 425486#L867-1 assume !(1 == ~T7_E~0); 425487#L872-1 assume !(1 == ~E_1~0); 425567#L877-1 assume !(1 == ~E_2~0); 425788#L882-1 assume !(1 == ~E_3~0); 426013#L887-1 assume !(1 == ~E_4~0); 425864#L892-1 assume !(1 == ~E_5~0); 425865#L897-1 assume !(1 == ~E_6~0); 425503#L902-1 assume !(1 == ~E_7~0); 425504#L907-1 assume { :end_inline_reset_delta_events } true; 434089#L1148-2 assume !false; 434082#L1149 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 434078#L729-1 [2023-11-12 02:09:49,082 INFO L750 eck$LassoCheckResult]: Loop: 434078#L729-1 assume !false; 434074#L622 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 434070#L569 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 434066#L611 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 434062#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 434057#L626 assume 0 != eval_~tmp~0#1; 434050#L626-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;havoc eval_#t~nondet5#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet5#1;havoc eval_#t~nondet5#1; 434044#L634 assume !(0 != eval_~tmp_ndt_1~0#1); 434045#L634-2 havoc eval_~tmp_ndt_1~0#1; 434130#L631-1 assume !(0 == ~t1_st~0); 434122#L645-1 assume !(0 == ~t2_st~0); 434115#L659-1 assume !(0 == ~t3_st~0); 434107#L673-1 assume !(0 == ~t4_st~0); 434100#L687-1 assume !(0 == ~t5_st~0); 434093#L701-1 assume !(0 == ~t6_st~0); 434084#L715-1 assume !(0 == ~t7_st~0); 434078#L729-1 [2023-11-12 02:09:49,082 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-12 02:09:49,082 INFO L85 PathProgramCache]: Analyzing trace with hash -439660602, now seen corresponding path program 1 times [2023-11-12 02:09:49,083 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-12 02:09:49,083 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [639053338] [2023-11-12 02:09:49,083 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-12 02:09:49,083 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-12 02:09:49,092 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-12 02:09:49,116 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-12 02:09:49,116 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-12 02:09:49,116 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [639053338] [2023-11-12 02:09:49,116 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [639053338] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-12 02:09:49,116 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-12 02:09:49,117 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-12 02:09:49,117 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2029213413] [2023-11-12 02:09:49,117 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-12 02:09:49,118 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-12 02:09:49,118 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-12 02:09:49,118 INFO L85 PathProgramCache]: Analyzing trace with hash -1739844173, now seen corresponding path program 2 times [2023-11-12 02:09:49,118 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-12 02:09:49,118 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1654126000] [2023-11-12 02:09:49,118 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-12 02:09:49,119 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-12 02:09:49,122 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-12 02:09:49,122 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-12 02:09:49,126 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-12 02:09:49,128 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-12 02:09:49,227 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-12 02:09:49,228 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-12 02:09:49,228 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-12 02:09:49,229 INFO L87 Difference]: Start difference. First operand 28670 states and 38333 transitions. cyclomatic complexity: 9669 Second operand has 3 states, 3 states have (on average 31.666666666666668) internal successors, (95), 3 states have internal predecessors, (95), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-12 02:09:49,324 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-12 02:09:49,324 INFO L93 Difference]: Finished difference Result 28574 states and 38205 transitions. [2023-11-12 02:09:49,324 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 28574 states and 38205 transitions. [2023-11-12 02:09:49,734 INFO L131 ngComponentsAnalysis]: Automaton has 6 accepting balls. 28392 [2023-11-12 02:09:49,812 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 28574 states to 28574 states and 38205 transitions. [2023-11-12 02:09:49,812 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 28574 [2023-11-12 02:09:49,827 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 28574 [2023-11-12 02:09:49,827 INFO L73 IsDeterministic]: Start isDeterministic. Operand 28574 states and 38205 transitions. [2023-11-12 02:09:49,841 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-12 02:09:49,841 INFO L218 hiAutomatonCegarLoop]: Abstraction has 28574 states and 38205 transitions. [2023-11-12 02:09:49,866 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 28574 states and 38205 transitions. [2023-11-12 02:09:50,183 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 28574 to 28574. [2023-11-12 02:09:50,205 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 28574 states, 28574 states have (on average 1.3370546650801427) internal successors, (38205), 28573 states have internal predecessors, (38205), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-12 02:09:50,297 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 28574 states to 28574 states and 38205 transitions. [2023-11-12 02:09:50,298 INFO L240 hiAutomatonCegarLoop]: Abstraction has 28574 states and 38205 transitions. [2023-11-12 02:09:50,298 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-12 02:09:50,299 INFO L428 stractBuchiCegarLoop]: Abstraction has 28574 states and 38205 transitions. [2023-11-12 02:09:50,299 INFO L335 stractBuchiCegarLoop]: ======== Iteration 28 ============ [2023-11-12 02:09:50,299 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 28574 states and 38205 transitions. [2023-11-12 02:09:50,468 INFO L131 ngComponentsAnalysis]: Automaton has 6 accepting balls. 28392 [2023-11-12 02:09:50,468 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-12 02:09:50,468 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-12 02:09:50,469 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-12 02:09:50,469 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-12 02:09:50,470 INFO L748 eck$LassoCheckResult]: Stem: 482581#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2; 482582#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~9#1;havoc main_~__retres1~9#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 483185#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret22#1, start_simulation_#t~ret23#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 483186#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 483224#L521 assume 1 == ~m_i~0;~m_st~0 := 0; 483207#L521-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 483208#L526-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 482733#L531-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 482734#L536-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 482806#L541-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 482644#L546-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 482645#L551-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 482610#L556-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 482611#L754 assume !(0 == ~M_E~0); 483238#L754-2 assume !(0 == ~T1_E~0); 483138#L759-1 assume !(0 == ~T2_E~0); 482992#L764-1 assume !(0 == ~T3_E~0); 482946#L769-1 assume !(0 == ~T4_E~0); 482947#L774-1 assume !(0 == ~T5_E~0); 482993#L779-1 assume !(0 == ~T6_E~0); 483149#L784-1 assume !(0 == ~T7_E~0); 482943#L789-1 assume !(0 == ~E_1~0); 482944#L794-1 assume !(0 == ~E_2~0); 483044#L799-1 assume !(0 == ~E_3~0); 482954#L804-1 assume !(0 == ~E_4~0); 482955#L809-1 assume !(0 == ~E_5~0); 482986#L814-1 assume !(0 == ~E_6~0); 482387#L819-1 assume !(0 == ~E_7~0); 482388#L824-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 482640#L361 assume !(1 == ~m_pc~0); 482641#L361-2 is_master_triggered_~__retres1~0#1 := 0; 483179#L372 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 483125#is_master_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 483126#L930 assume !(0 != activate_threads_~tmp~1#1); 482851#L930-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 482634#L380 assume !(1 == ~t1_pc~0); 482635#L380-2 is_transmit1_triggered_~__retres1~1#1 := 0; 483220#L391 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 483221#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 483277#L938 assume !(0 != activate_threads_~tmp___0~0#1); 483080#L938-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 483057#L399 assume !(1 == ~t2_pc~0); 482550#L399-2 is_transmit2_triggered_~__retres1~2#1 := 0; 482551#L410 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 482714#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 482707#L946 assume !(0 != activate_threads_~tmp___1~0#1); 482708#L946-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 482391#L418 assume !(1 == ~t3_pc~0); 482371#L418-2 is_transmit3_triggered_~__retres1~3#1 := 0; 482372#L429 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 482381#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 482382#L954 assume !(0 != activate_threads_~tmp___2~0#1); 482971#L954-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 482972#L437 assume !(1 == ~t4_pc~0); 483209#L437-2 is_transmit4_triggered_~__retres1~4#1 := 0; 483120#L448 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 482464#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 482465#L962 assume !(0 != activate_threads_~tmp___3~0#1); 482763#L962-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 483104#L456 assume !(1 == ~t5_pc~0); 482564#L456-2 is_transmit5_triggered_~__retres1~5#1 := 0; 482563#L467 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 483129#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 483029#L970 assume !(0 != activate_threads_~tmp___4~0#1); 483030#L970-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 482456#L475 assume !(1 == ~t6_pc~0); 482457#L475-2 is_transmit6_triggered_~__retres1~6#1 := 0; 482498#L486 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 482499#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 482700#L978 assume !(0 != activate_threads_~tmp___5~0#1); 482960#L978-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 482961#L494 assume !(1 == ~t7_pc~0); 482684#L494-2 is_transmit7_triggered_~__retres1~7#1 := 0; 482685#L505 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 482913#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 482994#L986 assume !(0 != activate_threads_~tmp___6~0#1); 482995#L986-2 havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 483232#L837 assume !(1 == ~M_E~0); 483184#L837-2 assume !(1 == ~T1_E~0); 483052#L842-1 assume !(1 == ~T2_E~0); 482772#L847-1 assume !(1 == ~T3_E~0); 482773#L852-1 assume !(1 == ~T4_E~0); 482841#L857-1 assume !(1 == ~T5_E~0); 482720#L862-1 assume !(1 == ~T6_E~0); 482721#L867-1 assume !(1 == ~T7_E~0); 482729#L872-1 assume !(1 == ~E_1~0); 482805#L877-1 assume !(1 == ~E_2~0); 483009#L882-1 assume !(1 == ~E_3~0); 483192#L887-1 assume !(1 == ~E_4~0); 483073#L892-1 assume !(1 == ~E_5~0); 483074#L897-1 assume !(1 == ~E_6~0); 482746#L902-1 assume !(1 == ~E_7~0); 482747#L907-1 assume { :end_inline_reset_delta_events } true; 483098#L1148-2 assume !false; 496265#L1149 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 496263#L729-1 [2023-11-12 02:09:50,470 INFO L750 eck$LassoCheckResult]: Loop: 496263#L729-1 assume !false; 496261#L622 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 496258#L569 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 496256#L611 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 496254#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 496252#L626 assume 0 != eval_~tmp~0#1; 496250#L626-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;havoc eval_#t~nondet5#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet5#1;havoc eval_#t~nondet5#1; 496247#L634 assume !(0 != eval_~tmp_ndt_1~0#1); 496245#L634-2 havoc eval_~tmp_ndt_1~0#1; 496243#L631-1 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0#1;havoc eval_#t~nondet6#1;eval_~tmp_ndt_2~0#1 := eval_#t~nondet6#1;havoc eval_#t~nondet6#1; 496226#L648 assume !(0 != eval_~tmp_ndt_2~0#1); 496241#L648-2 havoc eval_~tmp_ndt_2~0#1; 496290#L645-1 assume !(0 == ~t2_st~0); 496286#L659-1 assume !(0 == ~t3_st~0); 496278#L673-1 assume !(0 == ~t4_st~0); 496275#L687-1 assume !(0 == ~t5_st~0); 496271#L701-1 assume !(0 == ~t6_st~0); 496267#L715-1 assume !(0 == ~t7_st~0); 496263#L729-1 [2023-11-12 02:09:50,471 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-12 02:09:50,471 INFO L85 PathProgramCache]: Analyzing trace with hash 1978243464, now seen corresponding path program 2 times [2023-11-12 02:09:50,471 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-12 02:09:50,471 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [301933645] [2023-11-12 02:09:50,472 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-12 02:09:50,472 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-12 02:09:50,487 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-12 02:09:50,488 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-12 02:09:50,497 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-12 02:09:50,525 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-12 02:09:50,526 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-12 02:09:50,526 INFO L85 PathProgramCache]: Analyzing trace with hash 230138997, now seen corresponding path program 1 times [2023-11-12 02:09:50,526 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-12 02:09:50,526 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [469333000] [2023-11-12 02:09:50,526 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-12 02:09:50,527 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-12 02:09:50,531 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-12 02:09:50,532 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-12 02:09:50,534 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-12 02:09:50,537 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-12 02:09:50,538 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-12 02:09:50,538 INFO L85 PathProgramCache]: Analyzing trace with hash -2069460420, now seen corresponding path program 1 times [2023-11-12 02:09:50,538 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-12 02:09:50,538 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1471716806] [2023-11-12 02:09:50,539 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-12 02:09:50,539 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-12 02:09:50,555 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-12 02:09:50,599 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-12 02:09:50,600 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-12 02:09:50,600 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1471716806] [2023-11-12 02:09:50,600 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1471716806] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-12 02:09:50,600 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-12 02:09:50,601 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-12 02:09:50,601 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [733755287] [2023-11-12 02:09:50,601 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-12 02:09:50,726 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-12 02:09:50,726 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-12 02:09:50,727 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-12 02:09:50,727 INFO L87 Difference]: Start difference. First operand 28574 states and 38205 transitions. cyclomatic complexity: 9637 Second operand has 3 states, 3 states have (on average 37.666666666666664) internal successors, (113), 3 states have internal predecessors, (113), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-12 02:09:51,018 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-12 02:09:51,018 INFO L93 Difference]: Finished difference Result 54750 states and 72949 transitions. [2023-11-12 02:09:51,018 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 54750 states and 72949 transitions. [2023-11-12 02:09:51,636 INFO L131 ngComponentsAnalysis]: Automaton has 6 accepting balls. 54488 [2023-11-12 02:09:51,741 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 54750 states to 54750 states and 72949 transitions. [2023-11-12 02:09:51,741 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 54750 [2023-11-12 02:09:51,762 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 54750 [2023-11-12 02:09:51,763 INFO L73 IsDeterministic]: Start isDeterministic. Operand 54750 states and 72949 transitions. [2023-11-12 02:09:51,779 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-12 02:09:51,779 INFO L218 hiAutomatonCegarLoop]: Abstraction has 54750 states and 72949 transitions. [2023-11-12 02:09:51,813 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 54750 states and 72949 transitions. [2023-11-12 02:09:52,250 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 54750 to 53534. [2023-11-12 02:09:52,284 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 53534 states, 53534 states have (on average 1.3330780438599767) internal successors, (71365), 53533 states have internal predecessors, (71365), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-12 02:09:52,797 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 53534 states to 53534 states and 71365 transitions. [2023-11-12 02:09:52,797 INFO L240 hiAutomatonCegarLoop]: Abstraction has 53534 states and 71365 transitions. [2023-11-12 02:09:52,798 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-12 02:09:52,812 INFO L428 stractBuchiCegarLoop]: Abstraction has 53534 states and 71365 transitions. [2023-11-12 02:09:52,812 INFO L335 stractBuchiCegarLoop]: ======== Iteration 29 ============ [2023-11-12 02:09:52,813 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 53534 states and 71365 transitions. [2023-11-12 02:09:52,967 INFO L131 ngComponentsAnalysis]: Automaton has 6 accepting balls. 53272 [2023-11-12 02:09:52,968 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-12 02:09:52,968 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-12 02:09:52,969 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-12 02:09:52,969 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-12 02:09:52,969 INFO L748 eck$LassoCheckResult]: Stem: 565913#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2; 565914#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~9#1;havoc main_~__retres1~9#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 566553#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret22#1, start_simulation_#t~ret23#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 566554#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 566615#L521 assume 1 == ~m_i~0;~m_st~0 := 0; 566583#L521-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 566584#L526-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 566069#L531-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 566070#L536-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 566146#L541-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 565978#L546-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 565979#L551-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 565944#L556-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 565945#L754 assume !(0 == ~M_E~0); 566635#L754-2 assume !(0 == ~T1_E~0); 566499#L759-1 assume !(0 == ~T2_E~0); 566342#L764-1 assume !(0 == ~T3_E~0); 566294#L769-1 assume !(0 == ~T4_E~0); 566295#L774-1 assume !(0 == ~T5_E~0); 566343#L779-1 assume !(0 == ~T6_E~0); 566510#L784-1 assume !(0 == ~T7_E~0); 566291#L789-1 assume !(0 == ~E_1~0); 566292#L794-1 assume !(0 == ~E_2~0); 566396#L799-1 assume !(0 == ~E_3~0); 566302#L804-1 assume !(0 == ~E_4~0); 566303#L809-1 assume !(0 == ~E_5~0); 566336#L814-1 assume !(0 == ~E_6~0); 565719#L819-1 assume !(0 == ~E_7~0); 565720#L824-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 565974#L361 assume !(1 == ~m_pc~0); 565975#L361-2 is_master_triggered_~__retres1~0#1 := 0; 566548#L372 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 566484#is_master_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 566485#L930 assume !(0 != activate_threads_~tmp~1#1); 566199#L930-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 565967#L380 assume !(1 == ~t1_pc~0); 565968#L380-2 is_transmit1_triggered_~__retres1~1#1 := 0; 566609#L391 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 566610#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 566669#L938 assume !(0 != activate_threads_~tmp___0~0#1); 566435#L938-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 566411#L399 assume !(1 == ~t2_pc~0); 565882#L399-2 is_transmit2_triggered_~__retres1~2#1 := 0; 565883#L410 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 566047#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 566040#L946 assume !(0 != activate_threads_~tmp___1~0#1); 566041#L946-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 565723#L418 assume !(1 == ~t3_pc~0); 565703#L418-2 is_transmit3_triggered_~__retres1~3#1 := 0; 565704#L429 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 565713#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 565714#L954 assume !(0 != activate_threads_~tmp___2~0#1); 566320#L954-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 566321#L437 assume !(1 == ~t4_pc~0); 566585#L437-2 is_transmit4_triggered_~__retres1~4#1 := 0; 566480#L448 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 565796#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 565797#L962 assume !(0 != activate_threads_~tmp___3~0#1); 566100#L962-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 566462#L456 assume !(1 == ~t5_pc~0); 565896#L456-2 is_transmit5_triggered_~__retres1~5#1 := 0; 565895#L467 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 566490#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 566380#L970 assume !(0 != activate_threads_~tmp___4~0#1); 566381#L970-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 565789#L475 assume !(1 == ~t6_pc~0); 565790#L475-2 is_transmit6_triggered_~__retres1~6#1 := 0; 565831#L486 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 565832#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 566033#L978 assume !(0 != activate_threads_~tmp___5~0#1); 566308#L978-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 566309#L494 assume !(1 == ~t7_pc~0); 566017#L494-2 is_transmit7_triggered_~__retres1~7#1 := 0; 566018#L505 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 566260#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 566344#L986 assume !(0 != activate_threads_~tmp___6~0#1); 566345#L986-2 havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 566625#L837 assume !(1 == ~M_E~0); 566552#L837-2 assume !(1 == ~T1_E~0); 566406#L842-1 assume !(1 == ~T2_E~0); 566111#L847-1 assume !(1 == ~T3_E~0); 566112#L852-1 assume !(1 == ~T4_E~0); 566188#L857-1 assume !(1 == ~T5_E~0); 566054#L862-1 assume !(1 == ~T6_E~0); 566055#L867-1 assume !(1 == ~T7_E~0); 566065#L872-1 assume !(1 == ~E_1~0); 566145#L877-1 assume !(1 == ~E_2~0); 566359#L882-1 assume !(1 == ~E_3~0); 566560#L887-1 assume !(1 == ~E_4~0); 566429#L892-1 assume !(1 == ~E_5~0); 566430#L897-1 assume !(1 == ~E_6~0); 566083#L902-1 assume !(1 == ~E_7~0); 566084#L907-1 assume { :end_inline_reset_delta_events } true; 566456#L1148-2 assume !false; 593217#L1149 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 593215#L729-1 [2023-11-12 02:09:52,970 INFO L750 eck$LassoCheckResult]: Loop: 593215#L729-1 assume !false; 593213#L622 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 593210#L569 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 593207#L611 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 593205#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 593203#L626 assume 0 != eval_~tmp~0#1; 593201#L626-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;havoc eval_#t~nondet5#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet5#1;havoc eval_#t~nondet5#1; 593198#L634 assume !(0 != eval_~tmp_ndt_1~0#1); 593199#L634-2 havoc eval_~tmp_ndt_1~0#1; 589594#L631-1 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0#1;havoc eval_#t~nondet6#1;eval_~tmp_ndt_2~0#1 := eval_#t~nondet6#1;havoc eval_#t~nondet6#1; 589584#L648 assume !(0 != eval_~tmp_ndt_2~0#1); 585410#L648-2 havoc eval_~tmp_ndt_2~0#1; 584003#L645-1 assume 0 == ~t2_st~0;havoc eval_~tmp_ndt_3~0#1;havoc eval_#t~nondet7#1;eval_~tmp_ndt_3~0#1 := eval_#t~nondet7#1;havoc eval_#t~nondet7#1; 584001#L662 assume !(0 != eval_~tmp_ndt_3~0#1); 584002#L662-2 havoc eval_~tmp_ndt_3~0#1; 593407#L659-1 assume !(0 == ~t3_st~0); 593230#L673-1 assume !(0 == ~t4_st~0); 593227#L687-1 assume !(0 == ~t5_st~0); 593223#L701-1 assume !(0 == ~t6_st~0); 593219#L715-1 assume !(0 == ~t7_st~0); 593215#L729-1 [2023-11-12 02:09:52,970 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-12 02:09:52,970 INFO L85 PathProgramCache]: Analyzing trace with hash 1978243464, now seen corresponding path program 3 times [2023-11-12 02:09:52,971 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-12 02:09:52,971 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [412811585] [2023-11-12 02:09:52,971 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-12 02:09:52,972 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-12 02:09:52,985 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-12 02:09:52,985 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-12 02:09:52,992 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-12 02:09:53,017 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-12 02:09:53,017 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-12 02:09:53,017 INFO L85 PathProgramCache]: Analyzing trace with hash -2126794573, now seen corresponding path program 1 times [2023-11-12 02:09:53,018 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-12 02:09:53,018 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [871265382] [2023-11-12 02:09:53,018 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-12 02:09:53,018 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-12 02:09:53,021 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-12 02:09:53,022 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-12 02:09:53,024 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-12 02:09:53,026 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-12 02:09:53,027 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-12 02:09:53,027 INFO L85 PathProgramCache]: Analyzing trace with hash -133676870, now seen corresponding path program 1 times [2023-11-12 02:09:53,027 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-12 02:09:53,027 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [868872347] [2023-11-12 02:09:53,027 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-12 02:09:53,028 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-12 02:09:53,040 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-12 02:09:53,076 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-12 02:09:53,076 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-12 02:09:53,077 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [868872347] [2023-11-12 02:09:53,077 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [868872347] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-12 02:09:53,077 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-12 02:09:53,077 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-12 02:09:53,077 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1520031503] [2023-11-12 02:09:53,077 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-12 02:09:53,193 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-12 02:09:53,194 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-12 02:09:53,194 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-12 02:09:53,194 INFO L87 Difference]: Start difference. First operand 53534 states and 71365 transitions. cyclomatic complexity: 17837 Second operand has 3 states, 3 states have (on average 38.333333333333336) internal successors, (115), 3 states have internal predecessors, (115), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-12 02:09:53,565 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-12 02:09:53,565 INFO L93 Difference]: Finished difference Result 100558 states and 133685 transitions. [2023-11-12 02:09:53,565 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 100558 states and 133685 transitions. [2023-11-12 02:09:54,319 INFO L131 ngComponentsAnalysis]: Automaton has 6 accepting balls. 100136 [2023-11-12 02:09:54,550 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 100558 states to 100558 states and 133685 transitions. [2023-11-12 02:09:54,550 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 100558 [2023-11-12 02:09:54,599 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 100558 [2023-11-12 02:09:54,599 INFO L73 IsDeterministic]: Start isDeterministic. Operand 100558 states and 133685 transitions. [2023-11-12 02:09:54,637 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-12 02:09:54,637 INFO L218 hiAutomatonCegarLoop]: Abstraction has 100558 states and 133685 transitions. [2023-11-12 02:09:54,686 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 100558 states and 133685 transitions. [2023-11-12 02:09:55,678 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 100558 to 96590. [2023-11-12 02:09:55,736 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 96590 states, 96590 states have (on average 1.331701004244746) internal successors, (128629), 96589 states have internal predecessors, (128629), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-12 02:09:55,958 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 96590 states to 96590 states and 128629 transitions. [2023-11-12 02:09:55,958 INFO L240 hiAutomatonCegarLoop]: Abstraction has 96590 states and 128629 transitions. [2023-11-12 02:09:55,959 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-12 02:09:55,960 INFO L428 stractBuchiCegarLoop]: Abstraction has 96590 states and 128629 transitions. [2023-11-12 02:09:55,960 INFO L335 stractBuchiCegarLoop]: ======== Iteration 30 ============ [2023-11-12 02:09:55,960 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 96590 states and 128629 transitions. [2023-11-12 02:09:56,265 INFO L131 ngComponentsAnalysis]: Automaton has 6 accepting balls. 96168 [2023-11-12 02:09:56,265 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-12 02:09:56,266 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-12 02:09:56,267 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-12 02:09:56,267 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-12 02:09:56,268 INFO L748 eck$LassoCheckResult]: Stem: 720015#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2; 720016#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~9#1;havoc main_~__retres1~9#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 720672#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret22#1, start_simulation_#t~ret23#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 720673#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 720733#L521 assume 1 == ~m_i~0;~m_st~0 := 0; 720708#L521-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 720709#L526-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 720171#L531-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 720172#L536-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 720248#L541-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 720078#L546-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 720079#L551-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 720047#L556-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 720048#L754 assume !(0 == ~M_E~0); 720751#L754-2 assume !(0 == ~T1_E~0); 720615#L759-1 assume !(0 == ~T2_E~0); 720453#L764-1 assume !(0 == ~T3_E~0); 720404#L769-1 assume !(0 == ~T4_E~0); 720405#L774-1 assume !(0 == ~T5_E~0); 720454#L779-1 assume !(0 == ~T6_E~0); 720627#L784-1 assume !(0 == ~T7_E~0); 720401#L789-1 assume !(0 == ~E_1~0); 720402#L794-1 assume !(0 == ~E_2~0); 720511#L799-1 assume !(0 == ~E_3~0); 720414#L804-1 assume !(0 == ~E_4~0); 720415#L809-1 assume !(0 == ~E_5~0); 720447#L814-1 assume !(0 == ~E_6~0); 719816#L819-1 assume !(0 == ~E_7~0); 719817#L824-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 720076#L361 assume !(1 == ~m_pc~0); 720077#L361-2 is_master_triggered_~__retres1~0#1 := 0; 720665#L372 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 720599#is_master_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 720600#L930 assume !(0 != activate_threads_~tmp~1#1); 720297#L930-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 720070#L380 assume !(1 == ~t1_pc~0); 720071#L380-2 is_transmit1_triggered_~__retres1~1#1 := 0; 720728#L391 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 720729#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 720788#L938 assume !(0 != activate_threads_~tmp___0~0#1); 720550#L938-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 720526#L399 assume !(1 == ~t2_pc~0); 719984#L399-2 is_transmit2_triggered_~__retres1~2#1 := 0; 719985#L410 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 720153#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 720146#L946 assume !(0 != activate_threads_~tmp___1~0#1); 720147#L946-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 719824#L418 assume !(1 == ~t3_pc~0); 719803#L418-2 is_transmit3_triggered_~__retres1~3#1 := 0; 719804#L429 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 719814#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 719815#L954 assume !(0 != activate_threads_~tmp___2~0#1); 720430#L954-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 720431#L437 assume !(1 == ~t4_pc~0); 720710#L437-2 is_transmit4_triggered_~__retres1~4#1 := 0; 720593#L448 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 719895#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 719896#L962 assume !(0 != activate_threads_~tmp___3~0#1); 720202#L962-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 720571#L456 assume !(1 == ~t5_pc~0); 720001#L456-2 is_transmit5_triggered_~__retres1~5#1 := 0; 720000#L467 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 720606#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 720492#L970 assume !(0 != activate_threads_~tmp___4~0#1); 720493#L970-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 719890#L475 assume !(1 == ~t6_pc~0); 719891#L475-2 is_transmit6_triggered_~__retres1~6#1 := 0; 719933#L486 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 719934#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 720139#L978 assume !(0 != activate_threads_~tmp___5~0#1); 720419#L978-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 720420#L494 assume !(1 == ~t7_pc~0); 720123#L494-2 is_transmit7_triggered_~__retres1~7#1 := 0; 720124#L505 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 720371#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 720455#L986 assume !(0 != activate_threads_~tmp___6~0#1); 720456#L986-2 havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 720744#L837 assume !(1 == ~M_E~0); 720671#L837-2 assume !(1 == ~T1_E~0); 720519#L842-1 assume !(1 == ~T2_E~0); 720210#L847-1 assume !(1 == ~T3_E~0); 720211#L852-1 assume !(1 == ~T4_E~0); 720286#L857-1 assume !(1 == ~T5_E~0); 720159#L862-1 assume !(1 == ~T6_E~0); 720160#L867-1 assume !(1 == ~T7_E~0); 720167#L872-1 assume !(1 == ~E_1~0); 720247#L877-1 assume !(1 == ~E_2~0); 720472#L882-1 assume !(1 == ~E_3~0); 720679#L887-1 assume !(1 == ~E_4~0); 720543#L892-1 assume !(1 == ~E_5~0); 720544#L897-1 assume !(1 == ~E_6~0); 720183#L902-1 assume !(1 == ~E_7~0); 720184#L907-1 assume { :end_inline_reset_delta_events } true; 720570#L1148-2 assume !false; 732527#L1149 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 732519#L729-1 [2023-11-12 02:09:56,268 INFO L750 eck$LassoCheckResult]: Loop: 732519#L729-1 assume !false; 732520#L622 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 732502#L569 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 732503#L611 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 732480#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 732481#L626 assume 0 != eval_~tmp~0#1; 732462#L626-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;havoc eval_#t~nondet5#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet5#1;havoc eval_#t~nondet5#1; 732463#L634 assume !(0 != eval_~tmp_ndt_1~0#1); 736161#L634-2 havoc eval_~tmp_ndt_1~0#1; 732421#L631-1 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0#1;havoc eval_#t~nondet6#1;eval_~tmp_ndt_2~0#1 := eval_#t~nondet6#1;havoc eval_#t~nondet6#1; 732417#L648 assume !(0 != eval_~tmp_ndt_2~0#1); 732414#L648-2 havoc eval_~tmp_ndt_2~0#1; 732411#L645-1 assume 0 == ~t2_st~0;havoc eval_~tmp_ndt_3~0#1;havoc eval_#t~nondet7#1;eval_~tmp_ndt_3~0#1 := eval_#t~nondet7#1;havoc eval_#t~nondet7#1; 723003#L662 assume !(0 != eval_~tmp_ndt_3~0#1); 732405#L662-2 havoc eval_~tmp_ndt_3~0#1; 733396#L659-1 assume 0 == ~t3_st~0;havoc eval_~tmp_ndt_4~0#1;havoc eval_#t~nondet8#1;eval_~tmp_ndt_4~0#1 := eval_#t~nondet8#1;havoc eval_#t~nondet8#1; 733394#L676 assume !(0 != eval_~tmp_ndt_4~0#1); 732583#L676-2 havoc eval_~tmp_ndt_4~0#1; 732584#L673-1 assume !(0 == ~t4_st~0); 732556#L687-1 assume !(0 == ~t5_st~0); 732543#L701-1 assume !(0 == ~t6_st~0); 732542#L715-1 assume !(0 == ~t7_st~0); 732519#L729-1 [2023-11-12 02:09:56,269 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-12 02:09:56,269 INFO L85 PathProgramCache]: Analyzing trace with hash 1978243464, now seen corresponding path program 4 times [2023-11-12 02:09:56,270 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-12 02:09:56,270 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [879868595] [2023-11-12 02:09:56,270 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-12 02:09:56,270 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-12 02:09:56,286 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-12 02:09:56,286 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-12 02:09:56,296 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-12 02:09:56,323 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-12 02:09:56,324 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-12 02:09:56,324 INFO L85 PathProgramCache]: Analyzing trace with hash 833736693, now seen corresponding path program 1 times [2023-11-12 02:09:56,324 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-12 02:09:56,324 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1437767992] [2023-11-12 02:09:56,325 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-12 02:09:56,325 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-12 02:09:56,330 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-12 02:09:56,330 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-12 02:09:56,333 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-12 02:09:56,336 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-12 02:09:56,336 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-12 02:09:56,337 INFO L85 PathProgramCache]: Analyzing trace with hash 664435260, now seen corresponding path program 1 times [2023-11-12 02:09:56,337 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-12 02:09:56,337 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1021263580] [2023-11-12 02:09:56,337 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-12 02:09:56,338 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-12 02:09:56,354 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-12 02:09:56,396 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-12 02:09:56,397 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-12 02:09:56,397 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1021263580] [2023-11-12 02:09:56,397 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1021263580] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-12 02:09:56,397 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-12 02:09:56,398 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-12 02:09:56,398 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [62601429] [2023-11-12 02:09:56,398 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-12 02:09:56,514 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-12 02:09:56,515 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-12 02:09:56,515 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-12 02:09:56,515 INFO L87 Difference]: Start difference. First operand 96590 states and 128629 transitions. cyclomatic complexity: 32045 Second operand has 3 states, 3 states have (on average 39.0) internal successors, (117), 3 states have internal predecessors, (117), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-12 02:09:57,661 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-12 02:09:57,676 INFO L93 Difference]: Finished difference Result 128266 states and 170429 transitions. [2023-11-12 02:09:57,676 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 128266 states and 170429 transitions. [2023-11-12 02:09:58,161 INFO L131 ngComponentsAnalysis]: Automaton has 6 accepting balls. 127812 [2023-11-12 02:09:58,438 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 128266 states to 128266 states and 170429 transitions. [2023-11-12 02:09:58,438 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 128266 [2023-11-12 02:09:58,489 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 128266 [2023-11-12 02:09:58,489 INFO L73 IsDeterministic]: Start isDeterministic. Operand 128266 states and 170429 transitions. [2023-11-12 02:09:58,531 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-12 02:09:58,531 INFO L218 hiAutomatonCegarLoop]: Abstraction has 128266 states and 170429 transitions. [2023-11-12 02:09:58,589 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 128266 states and 170429 transitions. [2023-11-12 02:09:59,993 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 128266 to 125130. [2023-11-12 02:10:00,064 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 125130 states, 125130 states have (on average 1.3303044833373292) internal successors, (166461), 125129 states have internal predecessors, (166461), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-12 02:10:00,307 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 125130 states to 125130 states and 166461 transitions. [2023-11-12 02:10:00,307 INFO L240 hiAutomatonCegarLoop]: Abstraction has 125130 states and 166461 transitions. [2023-11-12 02:10:00,308 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-12 02:10:00,308 INFO L428 stractBuchiCegarLoop]: Abstraction has 125130 states and 166461 transitions. [2023-11-12 02:10:00,308 INFO L335 stractBuchiCegarLoop]: ======== Iteration 31 ============ [2023-11-12 02:10:00,308 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 125130 states and 166461 transitions. [2023-11-12 02:10:01,343 INFO L131 ngComponentsAnalysis]: Automaton has 6 accepting balls. 124676 [2023-11-12 02:10:01,344 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-12 02:10:01,344 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-12 02:10:01,345 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-12 02:10:01,345 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-12 02:10:01,345 INFO L748 eck$LassoCheckResult]: Stem: 944880#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2; 944881#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~9#1;havoc main_~__retres1~9#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 945524#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret22#1, start_simulation_#t~ret23#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 945525#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 945593#L521 assume 1 == ~m_i~0;~m_st~0 := 0; 945565#L521-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 945566#L526-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 945038#L531-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 945039#L536-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 945112#L541-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 944943#L546-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 944944#L551-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 944912#L556-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 944913#L754 assume !(0 == ~M_E~0); 945615#L754-2 assume !(0 == ~T1_E~0); 945467#L759-1 assume !(0 == ~T2_E~0); 945311#L764-1 assume !(0 == ~T3_E~0); 945260#L769-1 assume !(0 == ~T4_E~0); 945261#L774-1 assume !(0 == ~T5_E~0); 945312#L779-1 assume !(0 == ~T6_E~0); 945479#L784-1 assume !(0 == ~T7_E~0); 945257#L789-1 assume !(0 == ~E_1~0); 945258#L794-1 assume !(0 == ~E_2~0); 945367#L799-1 assume !(0 == ~E_3~0); 945269#L804-1 assume !(0 == ~E_4~0); 945270#L809-1 assume !(0 == ~E_5~0); 945305#L814-1 assume !(0 == ~E_6~0); 944679#L819-1 assume !(0 == ~E_7~0); 944680#L824-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 944941#L361 assume !(1 == ~m_pc~0); 944942#L361-2 is_master_triggered_~__retres1~0#1 := 0; 945518#L372 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 945452#is_master_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 945453#L930 assume !(0 != activate_threads_~tmp~1#1); 945162#L930-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 944935#L380 assume !(1 == ~t1_pc~0); 944936#L380-2 is_transmit1_triggered_~__retres1~1#1 := 0; 945586#L391 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 945587#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 945671#L938 assume !(0 != activate_threads_~tmp___0~0#1); 945406#L938-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 945381#L399 assume !(1 == ~t2_pc~0); 944847#L399-2 is_transmit2_triggered_~__retres1~2#1 := 0; 944848#L410 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 945018#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 945012#L946 assume !(0 != activate_threads_~tmp___1~0#1); 945013#L946-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 944687#L418 assume !(1 == ~t3_pc~0); 944667#L418-2 is_transmit3_triggered_~__retres1~3#1 := 0; 944668#L429 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 944677#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 944678#L954 assume !(0 != activate_threads_~tmp___2~0#1); 945289#L954-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 945290#L437 assume !(1 == ~t4_pc~0); 945567#L437-2 is_transmit4_triggered_~__retres1~4#1 := 0; 945447#L448 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 944758#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 944759#L962 assume !(0 != activate_threads_~tmp___3~0#1); 945066#L962-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 945427#L456 assume !(1 == ~t5_pc~0); 944863#L456-2 is_transmit5_triggered_~__retres1~5#1 := 0; 944862#L467 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 945457#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 945350#L970 assume !(0 != activate_threads_~tmp___4~0#1); 945351#L970-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 944753#L475 assume !(1 == ~t6_pc~0); 944754#L475-2 is_transmit6_triggered_~__retres1~6#1 := 0; 944796#L486 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 944797#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 945005#L978 assume !(0 != activate_threads_~tmp___5~0#1); 945275#L978-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 945276#L494 assume !(1 == ~t7_pc~0); 944989#L494-2 is_transmit7_triggered_~__retres1~7#1 := 0; 944990#L505 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 945227#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 945313#L986 assume !(0 != activate_threads_~tmp___6~0#1); 945314#L986-2 havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 945608#L837 assume !(1 == ~M_E~0); 945523#L837-2 assume !(1 == ~T1_E~0); 945378#L842-1 assume !(1 == ~T2_E~0); 945076#L847-1 assume !(1 == ~T3_E~0); 945077#L852-1 assume !(1 == ~T4_E~0); 945150#L857-1 assume !(1 == ~T5_E~0); 945025#L862-1 assume !(1 == ~T6_E~0); 945026#L867-1 assume !(1 == ~T7_E~0); 945034#L872-1 assume !(1 == ~E_1~0); 945111#L877-1 assume !(1 == ~E_2~0); 945329#L882-1 assume !(1 == ~E_3~0); 945534#L887-1 assume !(1 == ~E_4~0); 945398#L892-1 assume !(1 == ~E_5~0); 945399#L897-1 assume !(1 == ~E_6~0); 945049#L902-1 assume !(1 == ~E_7~0); 945050#L907-1 assume { :end_inline_reset_delta_events } true; 945426#L1148-2 assume !false; 968580#L1149 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 968578#L729-1 [2023-11-12 02:10:01,345 INFO L750 eck$LassoCheckResult]: Loop: 968578#L729-1 assume !false; 968576#L622 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 968573#L569 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 968567#L611 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 968562#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 968557#L626 assume 0 != eval_~tmp~0#1; 968553#L626-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;havoc eval_#t~nondet5#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet5#1;havoc eval_#t~nondet5#1; 968548#L634 assume !(0 != eval_~tmp_ndt_1~0#1); 968544#L634-2 havoc eval_~tmp_ndt_1~0#1; 968537#L631-1 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0#1;havoc eval_#t~nondet6#1;eval_~tmp_ndt_2~0#1 := eval_#t~nondet6#1;havoc eval_#t~nondet6#1; 964683#L648 assume !(0 != eval_~tmp_ndt_2~0#1); 965029#L648-2 havoc eval_~tmp_ndt_2~0#1; 971765#L645-1 assume 0 == ~t2_st~0;havoc eval_~tmp_ndt_3~0#1;havoc eval_#t~nondet7#1;eval_~tmp_ndt_3~0#1 := eval_#t~nondet7#1;havoc eval_#t~nondet7#1; 948771#L662 assume !(0 != eval_~tmp_ndt_3~0#1); 971762#L662-2 havoc eval_~tmp_ndt_3~0#1; 971760#L659-1 assume 0 == ~t3_st~0;havoc eval_~tmp_ndt_4~0#1;havoc eval_#t~nondet8#1;eval_~tmp_ndt_4~0#1 := eval_#t~nondet8#1;havoc eval_#t~nondet8#1; 971732#L676 assume !(0 != eval_~tmp_ndt_4~0#1); 971757#L676-2 havoc eval_~tmp_ndt_4~0#1; 971899#L673-1 assume 0 == ~t4_st~0;havoc eval_~tmp_ndt_5~0#1;havoc eval_#t~nondet9#1;eval_~tmp_ndt_5~0#1 := eval_#t~nondet9#1;havoc eval_#t~nondet9#1; 971893#L690 assume !(0 != eval_~tmp_ndt_5~0#1); 971888#L690-2 havoc eval_~tmp_ndt_5~0#1; 970223#L687-1 assume !(0 == ~t5_st~0); 968586#L701-1 assume !(0 == ~t6_st~0); 968582#L715-1 assume !(0 == ~t7_st~0); 968578#L729-1 [2023-11-12 02:10:01,345 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-12 02:10:01,346 INFO L85 PathProgramCache]: Analyzing trace with hash 1978243464, now seen corresponding path program 5 times [2023-11-12 02:10:01,346 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-12 02:10:01,346 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1264628832] [2023-11-12 02:10:01,346 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-12 02:10:01,346 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-12 02:10:01,358 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-12 02:10:01,359 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-12 02:10:01,366 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-12 02:10:01,389 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-12 02:10:01,389 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-12 02:10:01,390 INFO L85 PathProgramCache]: Analyzing trace with hash 10984371, now seen corresponding path program 1 times [2023-11-12 02:10:01,390 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-12 02:10:01,390 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1699112792] [2023-11-12 02:10:01,390 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-12 02:10:01,390 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-12 02:10:01,394 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-12 02:10:01,394 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-12 02:10:01,397 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-12 02:10:01,399 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-12 02:10:01,400 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-12 02:10:01,400 INFO L85 PathProgramCache]: Analyzing trace with hash 521064506, now seen corresponding path program 1 times [2023-11-12 02:10:01,400 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-12 02:10:01,400 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1241918975] [2023-11-12 02:10:01,400 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-12 02:10:01,401 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-12 02:10:01,413 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-12 02:10:01,446 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-12 02:10:01,447 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-12 02:10:01,447 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1241918975] [2023-11-12 02:10:01,447 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1241918975] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-12 02:10:01,447 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-12 02:10:01,447 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-12 02:10:01,447 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [774199023] [2023-11-12 02:10:01,448 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-12 02:10:01,582 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-12 02:10:01,583 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-12 02:10:01,583 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-12 02:10:01,583 INFO L87 Difference]: Start difference. First operand 125130 states and 166461 transitions. cyclomatic complexity: 41337 Second operand has 3 states, 3 states have (on average 39.666666666666664) internal successors, (119), 3 states have internal predecessors, (119), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-12 02:10:02,293 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-12 02:10:02,293 INFO L93 Difference]: Finished difference Result 228378 states and 302733 transitions. [2023-11-12 02:10:02,293 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 228378 states and 302733 transitions. [2023-11-12 02:10:04,158 INFO L131 ngComponentsAnalysis]: Automaton has 6 accepting balls. 227572 [2023-11-12 02:10:04,820 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 228378 states to 228378 states and 302733 transitions. [2023-11-12 02:10:04,820 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 228378 [2023-11-12 02:10:04,957 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 228378 [2023-11-12 02:10:04,957 INFO L73 IsDeterministic]: Start isDeterministic. Operand 228378 states and 302733 transitions. [2023-11-12 02:10:05,072 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-12 02:10:05,073 INFO L218 hiAutomatonCegarLoop]: Abstraction has 228378 states and 302733 transitions. [2023-11-12 02:10:05,195 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 228378 states and 302733 transitions. [2023-11-12 02:10:07,647 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 228378 to 221658. [2023-11-12 02:10:07,770 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 221658 states, 221658 states have (on average 1.328519611293073) internal successors, (294477), 221657 states have internal predecessors, (294477), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-12 02:10:08,234 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 221658 states to 221658 states and 294477 transitions. [2023-11-12 02:10:08,234 INFO L240 hiAutomatonCegarLoop]: Abstraction has 221658 states and 294477 transitions. [2023-11-12 02:10:08,234 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-12 02:10:08,235 INFO L428 stractBuchiCegarLoop]: Abstraction has 221658 states and 294477 transitions. [2023-11-12 02:10:08,235 INFO L335 stractBuchiCegarLoop]: ======== Iteration 32 ============ [2023-11-12 02:10:08,235 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 221658 states and 294477 transitions. [2023-11-12 02:10:09,822 INFO L131 ngComponentsAnalysis]: Automaton has 6 accepting balls. 220852 [2023-11-12 02:10:09,822 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-12 02:10:09,822 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-12 02:10:09,824 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-12 02:10:09,824 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-12 02:10:09,824 INFO L748 eck$LassoCheckResult]: Stem: 1298398#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2; 1298399#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~9#1;havoc main_~__retres1~9#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 1299074#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret22#1, start_simulation_#t~ret23#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 1299075#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 1299148#L521 assume 1 == ~m_i~0;~m_st~0 := 0; 1299112#L521-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 1299113#L526-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 1298561#L531-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 1298562#L536-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 1298636#L541-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 1298463#L546-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 1298464#L551-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 1298431#L556-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 1298432#L754 assume !(0 == ~M_E~0); 1299175#L754-2 assume !(0 == ~T1_E~0); 1299016#L759-1 assume !(0 == ~T2_E~0); 1298845#L764-1 assume !(0 == ~T3_E~0); 1298795#L769-1 assume !(0 == ~T4_E~0); 1298796#L774-1 assume !(0 == ~T5_E~0); 1298846#L779-1 assume !(0 == ~T6_E~0); 1299025#L784-1 assume !(0 == ~T7_E~0); 1298792#L789-1 assume !(0 == ~E_1~0); 1298793#L794-1 assume !(0 == ~E_2~0); 1298904#L799-1 assume !(0 == ~E_3~0); 1298806#L804-1 assume !(0 == ~E_4~0); 1298807#L809-1 assume !(0 == ~E_5~0); 1298838#L814-1 assume !(0 == ~E_6~0); 1298195#L819-1 assume !(0 == ~E_7~0); 1298196#L824-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1298461#L361 assume !(1 == ~m_pc~0); 1298462#L361-2 is_master_triggered_~__retres1~0#1 := 0; 1299064#L372 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1299002#is_master_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 1299003#L930 assume !(0 != activate_threads_~tmp~1#1); 1298686#L930-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1298454#L380 assume !(1 == ~t1_pc~0); 1298455#L380-2 is_transmit1_triggered_~__retres1~1#1 := 0; 1299142#L391 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1299143#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 1299227#L938 assume !(0 != activate_threads_~tmp___0~0#1); 1298944#L938-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1298918#L399 assume !(1 == ~t2_pc~0); 1298365#L399-2 is_transmit2_triggered_~__retres1~2#1 := 0; 1298366#L410 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1298539#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 1298532#L946 assume !(0 != activate_threads_~tmp___1~0#1); 1298533#L946-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1298203#L418 assume !(1 == ~t3_pc~0); 1298183#L418-2 is_transmit3_triggered_~__retres1~3#1 := 0; 1298184#L429 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1298193#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 1298194#L954 assume !(0 != activate_threads_~tmp___2~0#1); 1298823#L954-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1298824#L437 assume !(1 == ~t4_pc~0); 1299114#L437-2 is_transmit4_triggered_~__retres1~4#1 := 0; 1298994#L448 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1298275#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 1298276#L962 assume !(0 != activate_threads_~tmp___3~0#1); 1298592#L962-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1298968#L456 assume !(1 == ~t5_pc~0); 1298381#L456-2 is_transmit5_triggered_~__retres1~5#1 := 0; 1298380#L467 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1299007#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1298885#L970 assume !(0 != activate_threads_~tmp___4~0#1); 1298886#L970-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1298270#L475 assume !(1 == ~t6_pc~0); 1298271#L475-2 is_transmit6_triggered_~__retres1~6#1 := 0; 1298313#L486 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1298314#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1298523#L978 assume !(0 != activate_threads_~tmp___5~0#1); 1298812#L978-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1298813#L494 assume !(1 == ~t7_pc~0); 1298507#L494-2 is_transmit7_triggered_~__retres1~7#1 := 0; 1298508#L505 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1298755#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1298847#L986 assume !(0 != activate_threads_~tmp___6~0#1); 1298848#L986-2 havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1299165#L837 assume !(1 == ~M_E~0); 1299073#L837-2 assume !(1 == ~T1_E~0); 1298914#L842-1 assume !(1 == ~T2_E~0); 1298600#L847-1 assume !(1 == ~T3_E~0); 1298601#L852-1 assume !(1 == ~T4_E~0); 1298674#L857-1 assume !(1 == ~T5_E~0); 1298546#L862-1 assume !(1 == ~T6_E~0); 1298547#L867-1 assume !(1 == ~T7_E~0); 1298556#L872-1 assume !(1 == ~E_1~0); 1298635#L877-1 assume !(1 == ~E_2~0); 1298864#L882-1 assume !(1 == ~E_3~0); 1299085#L887-1 assume !(1 == ~E_4~0); 1298937#L892-1 assume !(1 == ~E_5~0); 1298938#L897-1 assume !(1 == ~E_6~0); 1298573#L902-1 assume !(1 == ~E_7~0); 1298574#L907-1 assume { :end_inline_reset_delta_events } true; 1298967#L1148-2 assume !false; 1369676#L1149 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 1369674#L729-1 [2023-11-12 02:10:09,824 INFO L750 eck$LassoCheckResult]: Loop: 1369674#L729-1 assume !false; 1369672#L622 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 1369668#L569 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 1369666#L611 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 1369664#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 1369662#L626 assume 0 != eval_~tmp~0#1; 1369660#L626-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;havoc eval_#t~nondet5#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet5#1;havoc eval_#t~nondet5#1; 1369657#L634 assume !(0 != eval_~tmp_ndt_1~0#1); 1369656#L634-2 havoc eval_~tmp_ndt_1~0#1; 1369655#L631-1 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0#1;havoc eval_#t~nondet6#1;eval_~tmp_ndt_2~0#1 := eval_#t~nondet6#1;havoc eval_#t~nondet6#1; 1352634#L648 assume !(0 != eval_~tmp_ndt_2~0#1); 1369652#L648-2 havoc eval_~tmp_ndt_2~0#1; 1369650#L645-1 assume 0 == ~t2_st~0;havoc eval_~tmp_ndt_3~0#1;havoc eval_#t~nondet7#1;eval_~tmp_ndt_3~0#1 := eval_#t~nondet7#1;havoc eval_#t~nondet7#1; 1344073#L662 assume !(0 != eval_~tmp_ndt_3~0#1); 1369646#L662-2 havoc eval_~tmp_ndt_3~0#1; 1369644#L659-1 assume 0 == ~t3_st~0;havoc eval_~tmp_ndt_4~0#1;havoc eval_#t~nondet8#1;eval_~tmp_ndt_4~0#1 := eval_#t~nondet8#1;havoc eval_#t~nondet8#1; 1369626#L676 assume !(0 != eval_~tmp_ndt_4~0#1); 1369642#L676-2 havoc eval_~tmp_ndt_4~0#1; 1369692#L673-1 assume 0 == ~t4_st~0;havoc eval_~tmp_ndt_5~0#1;havoc eval_#t~nondet9#1;eval_~tmp_ndt_5~0#1 := eval_#t~nondet9#1;havoc eval_#t~nondet9#1; 1369690#L690 assume !(0 != eval_~tmp_ndt_5~0#1); 1369688#L690-2 havoc eval_~tmp_ndt_5~0#1; 1369687#L687-1 assume 0 == ~t5_st~0;havoc eval_~tmp_ndt_6~0#1;havoc eval_#t~nondet10#1;eval_~tmp_ndt_6~0#1 := eval_#t~nondet10#1;havoc eval_#t~nondet10#1; 1355858#L704 assume !(0 != eval_~tmp_ndt_6~0#1); 1369685#L704-2 havoc eval_~tmp_ndt_6~0#1; 1369682#L701-1 assume !(0 == ~t6_st~0); 1369678#L715-1 assume !(0 == ~t7_st~0); 1369674#L729-1 [2023-11-12 02:10:09,825 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-12 02:10:09,825 INFO L85 PathProgramCache]: Analyzing trace with hash 1978243464, now seen corresponding path program 6 times [2023-11-12 02:10:09,825 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-12 02:10:09,825 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [246515849] [2023-11-12 02:10:09,826 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-12 02:10:09,826 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-12 02:10:09,837 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-12 02:10:09,838 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-12 02:10:09,845 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-12 02:10:09,868 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-12 02:10:09,869 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-12 02:10:09,869 INFO L85 PathProgramCache]: Analyzing trace with hash 1752066933, now seen corresponding path program 1 times [2023-11-12 02:10:09,869 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-12 02:10:09,869 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1552317347] [2023-11-12 02:10:09,869 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-12 02:10:09,870 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-12 02:10:09,874 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-12 02:10:09,874 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-12 02:10:09,876 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-12 02:10:09,879 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-12 02:10:09,879 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-12 02:10:09,879 INFO L85 PathProgramCache]: Analyzing trace with hash -1982162372, now seen corresponding path program 1 times [2023-11-12 02:10:09,879 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-12 02:10:09,880 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1765307689] [2023-11-12 02:10:09,880 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-12 02:10:09,880 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-12 02:10:09,892 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-12 02:10:09,927 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-12 02:10:09,928 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-12 02:10:09,928 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1765307689] [2023-11-12 02:10:09,928 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1765307689] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-12 02:10:09,928 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-12 02:10:09,928 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-12 02:10:09,929 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1424055688] [2023-11-12 02:10:09,929 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-12 02:10:10,061 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-12 02:10:10,062 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-12 02:10:10,062 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-12 02:10:10,062 INFO L87 Difference]: Start difference. First operand 221658 states and 294477 transitions. cyclomatic complexity: 72825 Second operand has 3 states, 3 states have (on average 40.333333333333336) internal successors, (121), 3 states have internal predecessors, (121), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0)