./Ultimate.py --spec ../../sv-benchmarks/c/properties/termination.prp --file ../../sv-benchmarks/c/systemc/transmitter.12.cil.c --full-output --architecture 32bit -------------------------------------------------------------------------------- Checking for termination Using default analysis Version cf1a7837 Calling Ultimate with: /usr/lib/jvm/java-1.11.0-openjdk-amd64/bin/java -Dosgi.configuration.area=/tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_abcd6f0e-11a0-4fc5-bc6f-77eabf5ba084/bin/uautomizer-verify-uTZkv6EMXl/data/config -Xmx15G -Xms4m -jar /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_abcd6f0e-11a0-4fc5-bc6f-77eabf5ba084/bin/uautomizer-verify-uTZkv6EMXl/plugins/org.eclipse.equinox.launcher_1.5.800.v20200727-1323.jar -data @noDefault -ultimatedata /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_abcd6f0e-11a0-4fc5-bc6f-77eabf5ba084/bin/uautomizer-verify-uTZkv6EMXl/data -tc /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_abcd6f0e-11a0-4fc5-bc6f-77eabf5ba084/bin/uautomizer-verify-uTZkv6EMXl/config/AutomizerTermination.xml -i ../../sv-benchmarks/c/systemc/transmitter.12.cil.c -s /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_abcd6f0e-11a0-4fc5-bc6f-77eabf5ba084/bin/uautomizer-verify-uTZkv6EMXl/config/svcomp-Termination-32bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_abcd6f0e-11a0-4fc5-bc6f-77eabf5ba084/bin/uautomizer-verify-uTZkv6EMXl --witnessprinter.witness.filename witness --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(F end) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 32bit --witnessprinter.graph.data.programhash 062c7418109a213aa13d25a99437d8241cca4f6492c123259890838dc94aff90 --- Real Ultimate output --- This is Ultimate 0.2.3-dev-cf1a783 [2023-11-12 02:13:32,011 INFO L188 SettingsManager]: Resetting all preferences to default values... [2023-11-12 02:13:32,126 INFO L114 SettingsManager]: Loading settings from /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_abcd6f0e-11a0-4fc5-bc6f-77eabf5ba084/bin/uautomizer-verify-uTZkv6EMXl/config/svcomp-Termination-32bit-Automizer_Default.epf [2023-11-12 02:13:32,138 WARN L101 SettingsManager]: Preference file contains the following unknown settings: [2023-11-12 02:13:32,139 WARN L103 SettingsManager]: * de.uni_freiburg.informatik.ultimate.core.Log level for class [2023-11-12 02:13:32,177 INFO L130 SettingsManager]: Preferences different from defaults after loading the file: [2023-11-12 02:13:32,179 INFO L151 SettingsManager]: Preferences of UltimateCore differ from their defaults: [2023-11-12 02:13:32,179 INFO L153 SettingsManager]: * Log level for class=de.uni_freiburg.informatik.ultimate.lib.smtlibutils.quantifier.QuantifierPusher=ERROR; [2023-11-12 02:13:32,181 INFO L151 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2023-11-12 02:13:32,185 INFO L153 SettingsManager]: * Create parallel compositions if possible=false [2023-11-12 02:13:32,187 INFO L153 SettingsManager]: * Use SBE=true [2023-11-12 02:13:32,187 INFO L151 SettingsManager]: Preferences of BuchiAutomizer differ from their defaults: [2023-11-12 02:13:32,188 INFO L153 SettingsManager]: * NCSB implementation=INTSET_LAZY3 [2023-11-12 02:13:32,189 INFO L153 SettingsManager]: * Use old map elimination=false [2023-11-12 02:13:32,190 INFO L153 SettingsManager]: * Use external solver (rank synthesis)=false [2023-11-12 02:13:32,190 INFO L153 SettingsManager]: * Use only trivial implications for array writes=true [2023-11-12 02:13:32,191 INFO L153 SettingsManager]: * Rank analysis=LINEAR_WITH_GUESSES [2023-11-12 02:13:32,191 INFO L151 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2023-11-12 02:13:32,192 INFO L153 SettingsManager]: * Pointer base address is valid at dereference=ASSUME [2023-11-12 02:13:32,193 INFO L153 SettingsManager]: * sizeof long=4 [2023-11-12 02:13:32,194 INFO L153 SettingsManager]: * Overapproximate operations on floating types=true [2023-11-12 02:13:32,195 INFO L153 SettingsManager]: * sizeof POINTER=4 [2023-11-12 02:13:32,195 INFO L153 SettingsManager]: * Check division by zero=IGNORE [2023-11-12 02:13:32,195 INFO L153 SettingsManager]: * Pointer to allocated memory at dereference=ASSUME [2023-11-12 02:13:32,196 INFO L153 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=ASSUME [2023-11-12 02:13:32,196 INFO L153 SettingsManager]: * Check array bounds for arrays that are off heap=ASSUME [2023-11-12 02:13:32,197 INFO L153 SettingsManager]: * Check unreachability of reach_error function=false [2023-11-12 02:13:32,197 INFO L153 SettingsManager]: * sizeof long double=12 [2023-11-12 02:13:32,197 INFO L153 SettingsManager]: * Check if freed pointer was valid=false [2023-11-12 02:13:32,198 INFO L153 SettingsManager]: * Assume nondeterminstic values are in range=false [2023-11-12 02:13:32,199 INFO L153 SettingsManager]: * Use constant arrays=true [2023-11-12 02:13:32,199 INFO L151 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2023-11-12 02:13:32,200 INFO L153 SettingsManager]: * Size of a code block=SequenceOfStatements [2023-11-12 02:13:32,200 INFO L151 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2023-11-12 02:13:32,200 INFO L153 SettingsManager]: * Trace refinement strategy=CAMEL [2023-11-12 02:13:32,201 INFO L151 SettingsManager]: Preferences of IcfgTransformer differ from their defaults: [2023-11-12 02:13:32,201 INFO L153 SettingsManager]: * TransformationType=MODULO_NEIGHBOR WARNING: An illegal reflective access operation has occurred WARNING: Illegal reflective access by com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 (file:/tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_abcd6f0e-11a0-4fc5-bc6f-77eabf5ba084/bin/uautomizer-verify-uTZkv6EMXl/plugins/com.sun.xml.bind_2.2.0.v201505121915.jar) to method java.lang.ClassLoader.defineClass(java.lang.String,byte[],int,int) WARNING: Please consider reporting this to the maintainers of com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 WARNING: Use --illegal-access=warn to enable warnings of further illegal reflective access operations WARNING: All illegal access operations will be denied in a future release Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_abcd6f0e-11a0-4fc5-bc6f-77eabf5ba084/bin/uautomizer-verify-uTZkv6EMXl Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(F end) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 32bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> 062c7418109a213aa13d25a99437d8241cca4f6492c123259890838dc94aff90 [2023-11-12 02:13:32,447 INFO L75 nceAwareModelManager]: Repository-Root is: /tmp [2023-11-12 02:13:32,474 INFO L261 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2023-11-12 02:13:32,476 INFO L217 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2023-11-12 02:13:32,478 INFO L270 PluginConnector]: Initializing CDTParser... [2023-11-12 02:13:32,479 INFO L274 PluginConnector]: CDTParser initialized [2023-11-12 02:13:32,480 INFO L431 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_abcd6f0e-11a0-4fc5-bc6f-77eabf5ba084/bin/uautomizer-verify-uTZkv6EMXl/../../sv-benchmarks/c/systemc/transmitter.12.cil.c [2023-11-12 02:13:35,664 INFO L533 CDTParser]: Created temporary CDT project at NULL [2023-11-12 02:13:35,909 INFO L384 CDTParser]: Found 1 translation units. [2023-11-12 02:13:35,910 INFO L180 CDTParser]: Scanning /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_abcd6f0e-11a0-4fc5-bc6f-77eabf5ba084/sv-benchmarks/c/systemc/transmitter.12.cil.c [2023-11-12 02:13:35,928 INFO L427 CDTParser]: About to delete temporary CDT project at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_abcd6f0e-11a0-4fc5-bc6f-77eabf5ba084/bin/uautomizer-verify-uTZkv6EMXl/data/4a172168a/44c4c45a9a7b4c5fb344fb6559772276/FLAGadc101dbd [2023-11-12 02:13:35,944 INFO L435 CDTParser]: Successfully deleted /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_abcd6f0e-11a0-4fc5-bc6f-77eabf5ba084/bin/uautomizer-verify-uTZkv6EMXl/data/4a172168a/44c4c45a9a7b4c5fb344fb6559772276 [2023-11-12 02:13:35,950 INFO L299 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2023-11-12 02:13:35,952 INFO L133 ToolchainWalker]: Walking toolchain with 6 elements. [2023-11-12 02:13:35,955 INFO L112 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2023-11-12 02:13:35,957 INFO L270 PluginConnector]: Initializing CACSL2BoogieTranslator... [2023-11-12 02:13:35,963 INFO L274 PluginConnector]: CACSL2BoogieTranslator initialized [2023-11-12 02:13:35,964 INFO L184 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 12.11 02:13:35" (1/1) ... [2023-11-12 02:13:35,965 INFO L204 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@26e8a452 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 12.11 02:13:35, skipping insertion in model container [2023-11-12 02:13:35,966 INFO L184 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 12.11 02:13:35" (1/1) ... [2023-11-12 02:13:36,045 INFO L177 MainTranslator]: Built tables and reachable declarations [2023-11-12 02:13:36,336 INFO L209 PostProcessor]: Analyzing one entry point: main [2023-11-12 02:13:36,362 INFO L202 MainTranslator]: Completed pre-run [2023-11-12 02:13:36,442 INFO L209 PostProcessor]: Analyzing one entry point: main [2023-11-12 02:13:36,479 INFO L206 MainTranslator]: Completed translation [2023-11-12 02:13:36,479 INFO L201 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 12.11 02:13:36 WrapperNode [2023-11-12 02:13:36,480 INFO L131 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2023-11-12 02:13:36,481 INFO L112 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2023-11-12 02:13:36,481 INFO L270 PluginConnector]: Initializing Boogie Procedure Inliner... [2023-11-12 02:13:36,481 INFO L274 PluginConnector]: Boogie Procedure Inliner initialized [2023-11-12 02:13:36,487 INFO L184 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 12.11 02:13:36" (1/1) ... [2023-11-12 02:13:36,501 INFO L184 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 12.11 02:13:36" (1/1) ... [2023-11-12 02:13:36,642 INFO L138 Inliner]: procedures = 52, calls = 67, calls flagged for inlining = 62, calls inlined = 255, statements flattened = 3936 [2023-11-12 02:13:36,643 INFO L131 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2023-11-12 02:13:36,643 INFO L112 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2023-11-12 02:13:36,644 INFO L270 PluginConnector]: Initializing Boogie Preprocessor... [2023-11-12 02:13:36,644 INFO L274 PluginConnector]: Boogie Preprocessor initialized [2023-11-12 02:13:36,654 INFO L184 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 12.11 02:13:36" (1/1) ... [2023-11-12 02:13:36,654 INFO L184 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 12.11 02:13:36" (1/1) ... [2023-11-12 02:13:36,667 INFO L184 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 12.11 02:13:36" (1/1) ... [2023-11-12 02:13:36,667 INFO L184 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 12.11 02:13:36" (1/1) ... [2023-11-12 02:13:36,721 INFO L184 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 12.11 02:13:36" (1/1) ... [2023-11-12 02:13:36,775 INFO L184 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 12.11 02:13:36" (1/1) ... [2023-11-12 02:13:36,787 INFO L184 PluginConnector]: Executing the observer LTLStepAnnotator from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 12.11 02:13:36" (1/1) ... [2023-11-12 02:13:36,801 INFO L184 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 12.11 02:13:36" (1/1) ... [2023-11-12 02:13:36,818 INFO L131 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2023-11-12 02:13:36,820 INFO L112 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2023-11-12 02:13:36,820 INFO L270 PluginConnector]: Initializing RCFGBuilder... [2023-11-12 02:13:36,820 INFO L274 PluginConnector]: RCFGBuilder initialized [2023-11-12 02:13:36,821 INFO L184 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 12.11 02:13:36" (1/1) ... [2023-11-12 02:13:36,828 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2023-11-12 02:13:36,840 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_abcd6f0e-11a0-4fc5-bc6f-77eabf5ba084/bin/uautomizer-verify-uTZkv6EMXl/z3 [2023-11-12 02:13:36,859 INFO L229 MonitoredProcess]: Starting monitored process 1 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_abcd6f0e-11a0-4fc5-bc6f-77eabf5ba084/bin/uautomizer-verify-uTZkv6EMXl/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2023-11-12 02:13:36,879 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_abcd6f0e-11a0-4fc5-bc6f-77eabf5ba084/bin/uautomizer-verify-uTZkv6EMXl/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (1)] Waiting until timeout for monitored process [2023-11-12 02:13:36,902 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocInit [2023-11-12 02:13:36,903 INFO L130 BoogieDeclarations]: Found specification of procedure write~init~int [2023-11-12 02:13:36,903 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2023-11-12 02:13:36,903 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2023-11-12 02:13:37,030 INFO L236 CfgBuilder]: Building ICFG [2023-11-12 02:13:37,032 INFO L262 CfgBuilder]: Building CFG for each procedure with an implementation [2023-11-12 02:13:39,480 INFO L277 CfgBuilder]: Performing block encoding [2023-11-12 02:13:39,508 INFO L297 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2023-11-12 02:13:39,509 INFO L302 CfgBuilder]: Removed 16 assume(true) statements. [2023-11-12 02:13:39,513 INFO L201 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 12.11 02:13:39 BoogieIcfgContainer [2023-11-12 02:13:39,513 INFO L131 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2023-11-12 02:13:39,515 INFO L112 PluginConnector]: ------------------------BuchiAutomizer---------------------------- [2023-11-12 02:13:39,515 INFO L270 PluginConnector]: Initializing BuchiAutomizer... [2023-11-12 02:13:39,519 INFO L274 PluginConnector]: BuchiAutomizer initialized [2023-11-12 02:13:39,519 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2023-11-12 02:13:39,520 INFO L184 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "CDTParser AST 12.11 02:13:35" (1/3) ... [2023-11-12 02:13:39,520 INFO L204 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@16eb01f5 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 12.11 02:13:39, skipping insertion in model container [2023-11-12 02:13:39,521 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2023-11-12 02:13:39,521 INFO L184 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 12.11 02:13:36" (2/3) ... [2023-11-12 02:13:39,523 INFO L204 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@16eb01f5 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 12.11 02:13:39, skipping insertion in model container [2023-11-12 02:13:39,523 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2023-11-12 02:13:39,523 INFO L184 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 12.11 02:13:39" (3/3) ... [2023-11-12 02:13:39,524 INFO L332 chiAutomizerObserver]: Analyzing ICFG transmitter.12.cil.c [2023-11-12 02:13:39,624 INFO L303 stractBuchiCegarLoop]: Interprodecural is true [2023-11-12 02:13:39,624 INFO L304 stractBuchiCegarLoop]: Hoare is false [2023-11-12 02:13:39,624 INFO L305 stractBuchiCegarLoop]: Compute interpolants for ForwardPredicates [2023-11-12 02:13:39,624 INFO L306 stractBuchiCegarLoop]: Backedges is STRAIGHT_LINE [2023-11-12 02:13:39,625 INFO L307 stractBuchiCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2023-11-12 02:13:39,625 INFO L308 stractBuchiCegarLoop]: Difference is false [2023-11-12 02:13:39,625 INFO L309 stractBuchiCegarLoop]: Minimize is MINIMIZE_SEVPA [2023-11-12 02:13:39,625 INFO L313 stractBuchiCegarLoop]: ======== Iteration 0 == of CEGAR loop == BuchiAutomatonCegarLoop ======== [2023-11-12 02:13:39,640 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 1709 states, 1708 states have (on average 1.4976580796252927) internal successors, (2558), 1708 states have internal predecessors, (2558), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-12 02:13:39,737 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1544 [2023-11-12 02:13:39,737 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-12 02:13:39,737 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-12 02:13:39,756 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-12 02:13:39,756 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-12 02:13:39,756 INFO L335 stractBuchiCegarLoop]: ======== Iteration 1 ============ [2023-11-12 02:13:39,761 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 1709 states, 1708 states have (on average 1.4976580796252927) internal successors, (2558), 1708 states have internal predecessors, (2558), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-12 02:13:39,786 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1544 [2023-11-12 02:13:39,786 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-12 02:13:39,786 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-12 02:13:39,793 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-12 02:13:39,793 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-12 02:13:39,804 INFO L748 eck$LassoCheckResult]: Stem: 130#$Ultimate##0true assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2; 1621#L-1true assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~14#1;havoc main_~__retres1~14#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1; 630#init_model_returnLabel#1true assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret32#1, start_simulation_#t~ret33#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 1617#update_channels_returnLabel#1true assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 524#L821true assume !(1 == ~m_i~0);~m_st~0 := 2; 599#L821-2true assume 1 == ~t1_i~0;~t1_st~0 := 0; 871#L826-1true assume !(1 == ~t2_i~0);~t2_st~0 := 2; 1186#L831-1true assume !(1 == ~t3_i~0);~t3_st~0 := 2; 1028#L836-1true assume !(1 == ~t4_i~0);~t4_st~0 := 2; 1334#L841-1true assume !(1 == ~t5_i~0);~t5_st~0 := 2; 119#L846-1true assume !(1 == ~t6_i~0);~t6_st~0 := 2; 1636#L851-1true assume !(1 == ~t7_i~0);~t7_st~0 := 2; 941#L856-1true assume !(1 == ~t8_i~0);~t8_st~0 := 2; 450#L861-1true assume 1 == ~t9_i~0;~t9_st~0 := 0; 477#L866-1true assume !(1 == ~t10_i~0);~t10_st~0 := 2; 392#L871-1true assume !(1 == ~t11_i~0);~t11_st~0 := 2; 706#L876-1true assume !(1 == ~t12_i~0);~t12_st~0 := 2; 701#L881-1true assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 240#L1174true assume !(0 == ~M_E~0); 1357#L1174-2true assume 0 == ~T1_E~0;~T1_E~0 := 1; 163#L1179-1true assume !(0 == ~T2_E~0); 117#L1184-1true assume !(0 == ~T3_E~0); 138#L1189-1true assume !(0 == ~T4_E~0); 184#L1194-1true assume !(0 == ~T5_E~0); 811#L1199-1true assume !(0 == ~T6_E~0); 977#L1204-1true assume !(0 == ~T7_E~0); 740#L1209-1true assume !(0 == ~T8_E~0); 1248#L1214-1true assume 0 == ~T9_E~0;~T9_E~0 := 1; 1651#L1219-1true assume !(0 == ~T10_E~0); 1571#L1224-1true assume !(0 == ~T11_E~0); 306#L1229-1true assume !(0 == ~T12_E~0); 84#L1234-1true assume !(0 == ~E_1~0); 489#L1239-1true assume !(0 == ~E_2~0); 98#L1244-1true assume !(0 == ~E_3~0); 1340#L1249-1true assume !(0 == ~E_4~0); 465#L1254-1true assume 0 == ~E_5~0;~E_5~0 := 1; 50#L1259-1true assume !(0 == ~E_6~0); 30#L1264-1true assume !(0 == ~E_7~0); 1702#L1269-1true assume !(0 == ~E_8~0); 1624#L1274-1true assume !(0 == ~E_9~0); 1328#L1279-1true assume !(0 == ~E_10~0); 140#L1284-1true assume !(0 == ~E_11~0); 1473#L1289-1true assume !(0 == ~E_12~0); 503#L1294-1true assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1344#L566true assume 1 == ~m_pc~0; 37#L567true assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 970#L577true is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 538#is_master_triggered_returnLabel#1true activate_threads_#t~ret18#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1193#L1455true assume !(0 != activate_threads_~tmp~1#1); 252#L1455-2true assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 783#L585true assume 1 == ~t1_pc~0; 83#L586true assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 1627#L596true is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 861#is_transmit1_triggered_returnLabel#1true activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1546#L1463true assume !(0 != activate_threads_~tmp___0~0#1); 1414#L1463-2true assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1405#L604true assume !(1 == ~t2_pc~0); 776#L604-2true is_transmit2_triggered_~__retres1~2#1 := 0; 1366#L615true is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 223#is_transmit2_triggered_returnLabel#1true activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1202#L1471true assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 984#L1471-2true assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1471#L623true assume 1 == ~t3_pc~0; 356#L624true assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 1676#L634true is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 836#is_transmit3_triggered_returnLabel#1true activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1021#L1479true assume !(0 != activate_threads_~tmp___2~0#1); 1246#L1479-2true assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 36#L642true assume !(1 == ~t4_pc~0); 670#L642-2true is_transmit4_triggered_~__retres1~4#1 := 0; 259#L653true is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 61#is_transmit4_triggered_returnLabel#1true activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 72#L1487true assume !(0 != activate_threads_~tmp___3~0#1); 787#L1487-2true assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1126#L661true assume 1 == ~t5_pc~0; 147#L662true assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 714#L672true is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1372#is_transmit5_triggered_returnLabel#1true activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 1103#L1495true assume !(0 != activate_threads_~tmp___4~0#1); 818#L1495-2true assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1703#L680true assume !(1 == ~t6_pc~0); 1705#L680-2true is_transmit6_triggered_~__retres1~6#1 := 0; 1500#L691true is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 218#is_transmit6_triggered_returnLabel#1true activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 1118#L1503true assume !(0 != activate_threads_~tmp___5~0#1); 1410#L1503-2true assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1401#L699true assume 1 == ~t7_pc~0; 682#L700true assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 890#L710true is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1637#is_transmit7_triggered_returnLabel#1true activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 588#L1511true assume !(0 != activate_threads_~tmp___6~0#1); 795#L1511-2true assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 504#L718true assume !(1 == ~t8_pc~0); 1254#L718-2true is_transmit8_triggered_~__retres1~8#1 := 0; 137#L729true is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 1322#is_transmit8_triggered_returnLabel#1true activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 155#L1519true assume !(0 != activate_threads_~tmp___7~0#1); 221#L1519-2true assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 849#L737true assume 1 == ~t9_pc~0; 1512#L738true assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 1291#L748true is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 244#is_transmit9_triggered_returnLabel#1true activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 1652#L1527true assume !(0 != activate_threads_~tmp___8~0#1); 405#L1527-2true assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 1097#L756true assume 1 == ~t10_pc~0; 882#L757true assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 806#L767true is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 1119#is_transmit10_triggered_returnLabel#1true activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 531#L1535true assume !(0 != activate_threads_~tmp___9~0#1); 284#L1535-2true assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 751#L775true assume !(1 == ~t11_pc~0); 446#L775-2true is_transmit11_triggered_~__retres1~11#1 := 0; 1269#L786true is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 1234#is_transmit11_triggered_returnLabel#1true activate_threads_#t~ret29#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 104#L1543true assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 842#L1543-2true assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 195#L794true assume 1 == ~t12_pc~0; 115#L795true assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 1104#L805true is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 38#is_transmit12_triggered_returnLabel#1true activate_threads_#t~ret30#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 177#L1551true assume !(0 != activate_threads_~tmp___11~0#1); 698#L1551-2true havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 454#L1307true assume !(1 == ~M_E~0); 535#L1307-2true assume !(1 == ~T1_E~0); 1452#L1312-1true assume !(1 == ~T2_E~0); 474#L1317-1true assume 1 == ~T3_E~0;~T3_E~0 := 2; 643#L1322-1true assume !(1 == ~T4_E~0); 291#L1327-1true assume !(1 == ~T5_E~0); 686#L1332-1true assume !(1 == ~T6_E~0); 1427#L1337-1true assume !(1 == ~T7_E~0); 638#L1342-1true assume !(1 == ~T8_E~0); 1326#L1347-1true assume !(1 == ~T9_E~0); 1065#L1352-1true assume !(1 == ~T10_E~0); 891#L1357-1true assume 1 == ~T11_E~0;~T11_E~0 := 2; 391#L1362-1true assume !(1 == ~T12_E~0); 1137#L1367-1true assume !(1 == ~E_1~0); 185#L1372-1true assume !(1 == ~E_2~0); 484#L1377-1true assume !(1 == ~E_3~0); 349#L1382-1true assume !(1 == ~E_4~0); 777#L1387-1true assume !(1 == ~E_5~0); 1264#L1392-1true assume !(1 == ~E_6~0); 360#L1397-1true assume 1 == ~E_7~0;~E_7~0 := 2; 1394#L1402-1true assume !(1 == ~E_8~0); 193#L1407-1true assume !(1 == ~E_9~0); 1529#L1412-1true assume !(1 == ~E_10~0); 973#L1417-1true assume !(1 == ~E_11~0); 1709#L1422-1true assume !(1 == ~E_12~0); 1390#L1427-1true assume { :end_inline_reset_delta_events } true; 96#L1768-2true [2023-11-12 02:13:39,809 INFO L750 eck$LassoCheckResult]: Loop: 96#L1768-2true assume !false; 520#L1769true start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 799#L1149-1true assume false; 498#eval_returnLabel#1true havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 318#update_channels_returnLabel#2true assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 997#L1174-3true assume 0 == ~M_E~0;~M_E~0 := 1; 989#L1174-5true assume 0 == ~T1_E~0;~T1_E~0 := 1; 722#L1179-3true assume 0 == ~T2_E~0;~T2_E~0 := 1; 1406#L1184-3true assume !(0 == ~T3_E~0); 892#L1189-3true assume 0 == ~T4_E~0;~T4_E~0 := 1; 576#L1194-3true assume 0 == ~T5_E~0;~T5_E~0 := 1; 173#L1199-3true assume 0 == ~T6_E~0;~T6_E~0 := 1; 815#L1204-3true assume 0 == ~T7_E~0;~T7_E~0 := 1; 302#L1209-3true assume 0 == ~T8_E~0;~T8_E~0 := 1; 11#L1214-3true assume 0 == ~T9_E~0;~T9_E~0 := 1; 628#L1219-3true assume 0 == ~T10_E~0;~T10_E~0 := 1; 414#L1224-3true assume !(0 == ~T11_E~0); 1707#L1229-3true assume 0 == ~T12_E~0;~T12_E~0 := 1; 425#L1234-3true assume 0 == ~E_1~0;~E_1~0 := 1; 101#L1239-3true assume 0 == ~E_2~0;~E_2~0 := 1; 336#L1244-3true assume 0 == ~E_3~0;~E_3~0 := 1; 668#L1249-3true assume 0 == ~E_4~0;~E_4~0 := 1; 1453#L1254-3true assume 0 == ~E_5~0;~E_5~0 := 1; 1241#L1259-3true assume 0 == ~E_6~0;~E_6~0 := 1; 763#L1264-3true assume !(0 == ~E_7~0); 103#L1269-3true assume 0 == ~E_8~0;~E_8~0 := 1; 1513#L1274-3true assume 0 == ~E_9~0;~E_9~0 := 1; 1325#L1279-3true assume 0 == ~E_10~0;~E_10~0 := 1; 412#L1284-3true assume 0 == ~E_11~0;~E_11~0 := 1; 1382#L1289-3true assume 0 == ~E_12~0;~E_12~0 := 1; 403#L1294-3true assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 213#L566-39true assume 1 == ~m_pc~0; 747#L567-13true assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 607#L577-13true is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 650#is_master_triggered_returnLabel#14true activate_threads_#t~ret18#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1255#L1455-39true assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 829#L1455-41true assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1301#L585-39true assume !(1 == ~t1_pc~0); 217#L585-41true is_transmit1_triggered_~__retres1~1#1 := 0; 332#L596-13true is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1487#is_transmit1_triggered_returnLabel#14true activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1229#L1463-39true assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 864#L1463-41true assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 592#L604-39true assume !(1 == ~t2_pc~0); 1224#L604-41true is_transmit2_triggered_~__retres1~2#1 := 0; 338#L615-13true is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 453#is_transmit2_triggered_returnLabel#14true activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 632#L1471-39true assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 1005#L1471-41true assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 324#L623-39true assume !(1 == ~t3_pc~0); 657#L623-41true is_transmit3_triggered_~__retres1~3#1 := 0; 845#L634-13true is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1682#is_transmit3_triggered_returnLabel#14true activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 241#L1479-39true assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 794#L1479-41true assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1307#L642-39true assume !(1 == ~t4_pc~0); 598#L642-41true is_transmit4_triggered_~__retres1~4#1 := 0; 750#L653-13true is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 573#is_transmit4_triggered_returnLabel#14true activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 1040#L1487-39true assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 1183#L1487-41true assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 199#L661-39true assume 1 == ~t5_pc~0; 1050#L662-13true assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 1641#L672-13true is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 596#is_transmit5_triggered_returnLabel#14true activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 1153#L1495-39true assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 847#L1495-41true assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1176#L680-39true assume !(1 == ~t6_pc~0); 975#L680-41true is_transmit6_triggered_~__retres1~6#1 := 0; 1146#L691-13true is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1576#is_transmit6_triggered_returnLabel#14true activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 283#L1503-39true assume !(0 != activate_threads_~tmp___5~0#1); 1501#L1503-41true assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1252#L699-39true assume 1 == ~t7_pc~0; 578#L700-13true assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 380#L710-13true is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 850#is_transmit7_triggered_returnLabel#14true activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 1275#L1511-39true assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 1143#L1511-41true assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 1141#L718-39true assume 1 == ~t8_pc~0; 507#L719-13true assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 1393#L729-13true is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 952#is_transmit8_triggered_returnLabel#14true activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 1155#L1519-39true assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 713#L1519-41true assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 692#L737-39true assume 1 == ~t9_pc~0; 270#L738-13true assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 451#L748-13true is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 66#is_transmit9_triggered_returnLabel#14true activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 1455#L1527-39true assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 1102#L1527-41true assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 1023#L756-39true assume 1 == ~t10_pc~0; 1379#L757-13true assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 1524#L767-13true is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 1228#is_transmit10_triggered_returnLabel#14true activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 436#L1535-39true assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 562#L1535-41true assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 77#L775-39true assume !(1 == ~t11_pc~0); 458#L775-41true is_transmit11_triggered_~__retres1~11#1 := 0; 432#L786-13true is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 616#is_transmit11_triggered_returnLabel#14true activate_threads_#t~ret29#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 1556#L1543-39true assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 757#L1543-41true assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 464#L794-39true assume 1 == ~t12_pc~0; 271#L795-13true assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 913#L805-13true is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 322#is_transmit12_triggered_returnLabel#14true activate_threads_#t~ret30#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 801#L1551-39true assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 48#L1551-41true havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1309#L1307-3true assume 1 == ~M_E~0;~M_E~0 := 2; 1203#L1307-5true assume 1 == ~T1_E~0;~T1_E~0 := 2; 1622#L1312-3true assume 1 == ~T2_E~0;~T2_E~0 := 2; 1614#L1317-3true assume 1 == ~T3_E~0;~T3_E~0 := 2; 819#L1322-3true assume 1 == ~T4_E~0;~T4_E~0 := 2; 1687#L1327-3true assume !(1 == ~T5_E~0); 110#L1332-3true assume 1 == ~T6_E~0;~T6_E~0 := 2; 99#L1337-3true assume 1 == ~T7_E~0;~T7_E~0 := 2; 528#L1342-3true assume 1 == ~T8_E~0;~T8_E~0 := 2; 954#L1347-3true assume 1 == ~T9_E~0;~T9_E~0 := 2; 634#L1352-3true assume 1 == ~T10_E~0;~T10_E~0 := 2; 1114#L1357-3true assume 1 == ~T11_E~0;~T11_E~0 := 2; 1697#L1362-3true assume 1 == ~T12_E~0;~T12_E~0 := 2; 1551#L1367-3true assume !(1 == ~E_1~0); 1518#L1372-3true assume 1 == ~E_2~0;~E_2~0 := 2; 17#L1377-3true assume 1 == ~E_3~0;~E_3~0 := 2; 428#L1382-3true assume 1 == ~E_4~0;~E_4~0 := 2; 340#L1387-3true assume 1 == ~E_5~0;~E_5~0 := 2; 926#L1392-3true assume 1 == ~E_6~0;~E_6~0 := 2; 1605#L1397-3true assume 1 == ~E_7~0;~E_7~0 := 2; 1376#L1402-3true assume 1 == ~E_8~0;~E_8~0 := 2; 606#L1407-3true assume !(1 == ~E_9~0); 153#L1412-3true assume 1 == ~E_10~0;~E_10~0 := 2; 1151#L1417-3true assume 1 == ~E_11~0;~E_11~0 := 2; 542#L1422-3true assume 1 == ~E_12~0;~E_12~0 := 2; 1107#L1427-3true assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 157#L894-1true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 1665#L961-1true exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 191#exists_runnable_thread_returnLabel#2true start_simulation_#t~ret32#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret32#1;havoc start_simulation_#t~ret32#1; 609#L1787true assume !(0 == start_simulation_~tmp~3#1); 1441#L1787-2true assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret31#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 1218#L894-2true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 1008#L961-2true exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 25#exists_runnable_thread_returnLabel#3true stop_simulation_#t~ret31#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret31#1;havoc stop_simulation_#t~ret31#1; 1320#L1742true assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 328#L1749true stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 1148#stop_simulation_returnLabel#1true start_simulation_#t~ret33#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret31#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret33#1;havoc start_simulation_#t~ret33#1; 1601#L1800true assume !(0 != start_simulation_~tmp___0~1#1); 96#L1768-2true [2023-11-12 02:13:39,817 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-12 02:13:39,818 INFO L85 PathProgramCache]: Analyzing trace with hash -1422298547, now seen corresponding path program 1 times [2023-11-12 02:13:39,828 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-12 02:13:39,829 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1937599216] [2023-11-12 02:13:39,829 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-12 02:13:39,829 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-12 02:13:39,951 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-12 02:13:40,207 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-12 02:13:40,207 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-12 02:13:40,208 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1937599216] [2023-11-12 02:13:40,208 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1937599216] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-12 02:13:40,209 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-12 02:13:40,209 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-12 02:13:40,211 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [784206982] [2023-11-12 02:13:40,211 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-12 02:13:40,216 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-12 02:13:40,217 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-12 02:13:40,217 INFO L85 PathProgramCache]: Analyzing trace with hash 1373381520, now seen corresponding path program 1 times [2023-11-12 02:13:40,218 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-12 02:13:40,218 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [112513703] [2023-11-12 02:13:40,218 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-12 02:13:40,219 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-12 02:13:40,239 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-12 02:13:40,369 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-12 02:13:40,369 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-12 02:13:40,370 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [112513703] [2023-11-12 02:13:40,370 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [112513703] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-12 02:13:40,370 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-12 02:13:40,370 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2023-11-12 02:13:40,370 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [325147762] [2023-11-12 02:13:40,371 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-12 02:13:40,372 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-12 02:13:40,373 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-12 02:13:40,428 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 2 interpolants. [2023-11-12 02:13:40,429 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=1, Invalid=1, Unknown=0, NotChecked=0, Total=2 [2023-11-12 02:13:40,435 INFO L87 Difference]: Start difference. First operand has 1709 states, 1708 states have (on average 1.4976580796252927) internal successors, (2558), 1708 states have internal predecessors, (2558), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand has 2 states, 2 states have (on average 73.5) internal successors, (147), 2 states have internal predecessors, (147), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-12 02:13:40,521 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-12 02:13:40,522 INFO L93 Difference]: Finished difference Result 1707 states and 2523 transitions. [2023-11-12 02:13:40,523 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1707 states and 2523 transitions. [2023-11-12 02:13:40,541 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1540 [2023-11-12 02:13:40,562 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1707 states to 1701 states and 2517 transitions. [2023-11-12 02:13:40,563 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1701 [2023-11-12 02:13:40,566 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1701 [2023-11-12 02:13:40,567 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1701 states and 2517 transitions. [2023-11-12 02:13:40,579 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-12 02:13:40,580 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1701 states and 2517 transitions. [2023-11-12 02:13:40,606 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1701 states and 2517 transitions. [2023-11-12 02:13:40,680 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1701 to 1701. [2023-11-12 02:13:40,685 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1701 states, 1701 states have (on average 1.4797178130511464) internal successors, (2517), 1700 states have internal predecessors, (2517), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-12 02:13:40,693 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1701 states to 1701 states and 2517 transitions. [2023-11-12 02:13:40,695 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1701 states and 2517 transitions. [2023-11-12 02:13:40,696 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 2 states. [2023-11-12 02:13:40,700 INFO L428 stractBuchiCegarLoop]: Abstraction has 1701 states and 2517 transitions. [2023-11-12 02:13:40,700 INFO L335 stractBuchiCegarLoop]: ======== Iteration 2 ============ [2023-11-12 02:13:40,700 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1701 states and 2517 transitions. [2023-11-12 02:13:40,712 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1540 [2023-11-12 02:13:40,713 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-12 02:13:40,713 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-12 02:13:40,717 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-12 02:13:40,717 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-12 02:13:40,718 INFO L748 eck$LassoCheckResult]: Stem: 3702#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2; 3703#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~14#1;havoc main_~__retres1~14#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1; 4495#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret32#1, start_simulation_#t~ret33#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 4496#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 4363#L821 assume !(1 == ~m_i~0);~m_st~0 := 2; 4364#L821-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 4457#L826-1 assume !(1 == ~t2_i~0);~t2_st~0 := 2; 4756#L831-1 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 4891#L836-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 4892#L841-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 3678#L846-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 3679#L851-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 4823#L856-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 4261#L861-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 4262#L866-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 4172#L871-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 4173#L876-1 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 4566#L881-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 3917#L1174 assume !(0 == ~M_E~0); 3918#L1174-2 assume 0 == ~T1_E~0;~T1_E~0 := 1; 3769#L1179-1 assume !(0 == ~T2_E~0); 3675#L1184-1 assume !(0 == ~T3_E~0); 3676#L1189-1 assume !(0 == ~T4_E~0); 3718#L1194-1 assume !(0 == ~T5_E~0); 3811#L1199-1 assume !(0 == ~T6_E~0); 4690#L1204-1 assume !(0 == ~T7_E~0); 4611#L1209-1 assume !(0 == ~T8_E~0); 4612#L1214-1 assume 0 == ~T9_E~0;~T9_E~0 := 1; 5035#L1219-1 assume !(0 == ~T10_E~0); 5120#L1224-1 assume !(0 == ~T11_E~0); 4034#L1229-1 assume !(0 == ~T12_E~0); 3605#L1234-1 assume !(0 == ~E_1~0); 3606#L1239-1 assume !(0 == ~E_2~0); 3638#L1244-1 assume !(0 == ~E_3~0); 3639#L1249-1 assume !(0 == ~E_4~0); 4281#L1254-1 assume 0 == ~E_5~0;~E_5~0 := 1; 3535#L1259-1 assume !(0 == ~E_6~0); 3488#L1264-1 assume !(0 == ~E_7~0); 3489#L1269-1 assume !(0 == ~E_8~0); 5123#L1274-1 assume !(0 == ~E_9~0); 5062#L1279-1 assume !(0 == ~E_10~0); 3722#L1284-1 assume !(0 == ~E_11~0); 3723#L1289-1 assume !(0 == ~E_12~0); 4333#L1294-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 4334#L566 assume 1 == ~m_pc~0; 3505#L567 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 3506#L577 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 4377#is_master_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 4378#L1455 assume !(0 != activate_threads_~tmp~1#1); 3944#L1455-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 3945#L585 assume 1 == ~t1_pc~0; 3602#L586 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 3603#L596 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 4746#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 4747#L1463 assume !(0 != activate_threads_~tmp___0~0#1); 5091#L1463-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 5087#L604 assume !(1 == ~t2_pc~0); 4652#L604-2 is_transmit2_triggered_~__retres1~2#1 := 0; 4653#L615 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 3887#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 3888#L1471 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 4851#L1471-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 4852#L623 assume 1 == ~t3_pc~0; 4118#L624 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 3464#L634 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 4721#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 4722#L1479 assume !(0 != activate_threads_~tmp___2~0#1); 4885#L1479-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 3502#L642 assume !(1 == ~t4_pc~0); 3503#L642-2 is_transmit4_triggered_~__retres1~4#1 := 0; 3955#L653 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 3557#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 3558#L1487 assume !(0 != activate_threads_~tmp___3~0#1); 3579#L1487-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 4665#L661 assume 1 == ~t5_pc~0; 3735#L662 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 3736#L672 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 4583#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 4950#L1495 assume !(0 != activate_threads_~tmp___4~0#1); 4697#L1495-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 4698#L680 assume !(1 == ~t6_pc~0); 4151#L680-2 is_transmit6_triggered_~__retres1~6#1 := 0; 4152#L691 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 3878#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 3879#L1503 assume !(0 != activate_threads_~tmp___5~0#1); 4960#L1503-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 5084#L699 assume 1 == ~t7_pc~0; 4546#L700 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 4547#L710 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 4779#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 4439#L1511 assume !(0 != activate_threads_~tmp___6~0#1); 4440#L1511-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 4335#L718 assume !(1 == ~t8_pc~0); 4336#L718-2 is_transmit8_triggered_~__retres1~8#1 := 0; 3716#L729 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 3717#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 3751#L1519 assume !(0 != activate_threads_~tmp___7~0#1); 3752#L1519-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 3884#L737 assume 1 == ~t9_pc~0; 4735#L738 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 4015#L748 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 3924#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 3925#L1527 assume !(0 != activate_threads_~tmp___8~0#1); 4192#L1527-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 4193#L756 assume 1 == ~t10_pc~0; 4769#L757 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 4430#L767 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 4685#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 4370#L1535 assume !(0 != activate_threads_~tmp___9~0#1); 3994#L1535-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 3995#L775 assume !(1 == ~t11_pc~0); 4253#L775-2 is_transmit11_triggered_~__retres1~11#1 := 0; 4254#L786 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 5028#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 3650#L1543 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 3651#L1543-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 3832#L794 assume 1 == ~t12_pc~0; 3673#L795 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 3653#L805 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 3508#is_transmit12_triggered_returnLabel#1 activate_threads_#t~ret30#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 3509#L1551 assume !(0 != activate_threads_~tmp___11~0#1); 3797#L1551-2 havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 4265#L1307 assume !(1 == ~M_E~0); 4266#L1307-2 assume !(1 == ~T1_E~0); 4374#L1312-1 assume !(1 == ~T2_E~0); 4294#L1317-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 4295#L1322-1 assume !(1 == ~T4_E~0); 4005#L1327-1 assume !(1 == ~T5_E~0); 4006#L1332-1 assume !(1 == ~T6_E~0); 4551#L1337-1 assume !(1 == ~T7_E~0); 4508#L1342-1 assume !(1 == ~T8_E~0); 4509#L1347-1 assume !(1 == ~T9_E~0); 4921#L1352-1 assume !(1 == ~T10_E~0); 4780#L1357-1 assume 1 == ~T11_E~0;~T11_E~0 := 2; 4170#L1362-1 assume !(1 == ~T12_E~0); 4171#L1367-1 assume !(1 == ~E_1~0); 3812#L1372-1 assume !(1 == ~E_2~0); 3813#L1377-1 assume !(1 == ~E_3~0); 4103#L1382-1 assume !(1 == ~E_4~0); 4104#L1387-1 assume !(1 == ~E_5~0); 4654#L1392-1 assume !(1 == ~E_6~0); 4121#L1397-1 assume 1 == ~E_7~0;~E_7~0 := 2; 4122#L1402-1 assume !(1 == ~E_8~0); 3827#L1407-1 assume !(1 == ~E_9~0); 3828#L1412-1 assume !(1 == ~E_10~0); 4846#L1417-1 assume !(1 == ~E_11~0); 4847#L1422-1 assume !(1 == ~E_12~0); 5081#L1427-1 assume { :end_inline_reset_delta_events } true; 3634#L1768-2 [2023-11-12 02:13:40,719 INFO L750 eck$LassoCheckResult]: Loop: 3634#L1768-2 assume !false; 3635#L1769 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 4298#L1149-1 assume !false; 4676#L972 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 4903#L894 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 4012#L961 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 4828#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 4898#L976 assume !(0 != eval_~tmp~0#1); 4326#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 4055#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 4056#L1174-3 assume 0 == ~M_E~0;~M_E~0 := 1; 4856#L1174-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 4594#L1179-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 4595#L1184-3 assume !(0 == ~T3_E~0); 4781#L1189-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 4425#L1194-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 3788#L1199-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 3789#L1204-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 4025#L1209-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 3448#L1214-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 3449#L1219-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 4205#L1224-3 assume !(0 == ~T11_E~0); 4206#L1229-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 4220#L1234-3 assume 0 == ~E_1~0;~E_1~0 := 1; 3644#L1239-3 assume 0 == ~E_2~0;~E_2~0 := 1; 3645#L1244-3 assume 0 == ~E_3~0;~E_3~0 := 1; 4080#L1249-3 assume 0 == ~E_4~0;~E_4~0 := 1; 4538#L1254-3 assume 0 == ~E_5~0;~E_5~0 := 1; 5031#L1259-3 assume 0 == ~E_6~0;~E_6~0 := 1; 4637#L1264-3 assume !(0 == ~E_7~0); 3648#L1269-3 assume 0 == ~E_8~0;~E_8~0 := 1; 3649#L1274-3 assume 0 == ~E_9~0;~E_9~0 := 1; 5061#L1279-3 assume 0 == ~E_10~0;~E_10~0 := 1; 4201#L1284-3 assume 0 == ~E_11~0;~E_11~0 := 1; 4202#L1289-3 assume 0 == ~E_12~0;~E_12~0 := 1; 4189#L1294-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 3868#L566-39 assume 1 == ~m_pc~0; 3869#L567-13 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 4468#L577-13 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 4469#is_master_triggered_returnLabel#14 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 4521#L1455-39 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 4712#L1455-41 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 4713#L585-39 assume !(1 == ~t1_pc~0); 3876#L585-41 is_transmit1_triggered_~__retres1~1#1 := 0; 3877#L596-13 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 4077#is_transmit1_triggered_returnLabel#14 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 5025#L1463-39 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 4750#L1463-41 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 4445#L604-39 assume 1 == ~t2_pc~0; 4446#L605-13 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 4084#L615-13 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 4085#is_transmit2_triggered_returnLabel#14 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 4264#L1471-39 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 4498#L1471-41 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 4066#L623-39 assume 1 == ~t3_pc~0; 3465#L624-13 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 3466#L634-13 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 4730#is_transmit3_triggered_returnLabel#14 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 3919#L1479-39 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 3920#L1479-41 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 4672#L642-39 assume !(1 == ~t4_pc~0); 4257#L642-41 is_transmit4_triggered_~__retres1~4#1 := 0; 4256#L653-13 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 4420#is_transmit4_triggered_returnLabel#14 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 4421#L1487-39 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 4902#L1487-41 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 3838#L661-39 assume !(1 == ~t5_pc~0); 3473#L661-41 is_transmit5_triggered_~__retres1~5#1 := 0; 3474#L672-13 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 4452#is_transmit5_triggered_returnLabel#14 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 4453#L1495-39 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 4732#L1495-41 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 4733#L680-39 assume 1 == ~t6_pc~0; 3540#L681-13 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 3541#L691-13 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 4981#is_transmit6_triggered_returnLabel#14 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 3992#L1503-39 assume !(0 != activate_threads_~tmp___5~0#1); 3993#L1503-41 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 5037#L699-39 assume 1 == ~t7_pc~0; 4427#L700-13 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 4154#L710-13 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 4155#is_transmit7_triggered_returnLabel#14 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 4737#L1511-39 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 4977#L1511-41 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 4974#L718-39 assume 1 == ~t8_pc~0; 4339#L719-13 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 4340#L729-13 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 4833#is_transmit8_triggered_returnLabel#14 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 4834#L1519-39 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 4582#L1519-41 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 4559#L737-39 assume 1 == ~t9_pc~0; 3973#L738-13 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 3974#L748-13 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 3568#is_transmit9_triggered_returnLabel#14 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 3569#L1527-39 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 4949#L1527-41 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 4886#L756-39 assume !(1 == ~t10_pc~0); 4353#L756-41 is_transmit10_triggered_~__retres1~10#1 := 0; 4354#L767-13 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 5024#is_transmit10_triggered_returnLabel#14 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 4238#L1535-39 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 4239#L1535-41 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 3589#L775-39 assume 1 == ~t11_pc~0; 3590#L776-13 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 4229#L786-13 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 4230#is_transmit11_triggered_returnLabel#14 activate_threads_#t~ret29#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 4479#L1543-39 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 4630#L1543-41 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 4280#L794-39 assume !(1 == ~t12_pc~0); 3969#L794-41 is_transmit12_triggered_~__retres1~12#1 := 0; 3970#L805-13 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 4063#is_transmit12_triggered_returnLabel#14 activate_threads_#t~ret30#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 4064#L1551-39 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 3531#L1551-41 havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 3532#L1307-3 assume 1 == ~M_E~0;~M_E~0 := 2; 5008#L1307-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 5009#L1312-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 5122#L1317-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 4699#L1322-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 4700#L1327-3 assume !(1 == ~T5_E~0); 3665#L1332-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 3640#L1337-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 3641#L1342-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 4368#L1347-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 4501#L1352-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 4502#L1357-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 4957#L1362-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 5117#L1367-3 assume !(1 == ~E_1~0); 5108#L1372-3 assume 1 == ~E_2~0;~E_2~0 := 2; 3461#L1377-3 assume 1 == ~E_3~0;~E_3~0 := 2; 3462#L1382-3 assume 1 == ~E_4~0;~E_4~0 := 2; 4087#L1387-3 assume 1 == ~E_5~0;~E_5~0 := 2; 4088#L1392-3 assume 1 == ~E_6~0;~E_6~0 := 2; 4807#L1397-3 assume 1 == ~E_7~0;~E_7~0 := 2; 5075#L1402-3 assume 1 == ~E_8~0;~E_8~0 := 2; 4467#L1407-3 assume !(1 == ~E_9~0); 3747#L1412-3 assume 1 == ~E_10~0;~E_10~0 := 2; 3748#L1417-3 assume 1 == ~E_11~0;~E_11~0 := 2; 4382#L1422-3 assume 1 == ~E_12~0;~E_12~0 := 2; 4383#L1427-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 3755#L894-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 3756#L961-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 3823#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret32#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret32#1;havoc start_simulation_#t~ret32#1; 3824#L1787 assume !(0 == start_simulation_~tmp~3#1); 4471#L1787-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret31#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 5017#L894-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 3732#L961-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 3480#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret31#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret31#1;havoc stop_simulation_#t~ret31#1; 3481#L1742 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 4073#L1749 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 4074#stop_simulation_returnLabel#1 start_simulation_#t~ret33#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret31#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret33#1;havoc start_simulation_#t~ret33#1; 4984#L1800 assume !(0 != start_simulation_~tmp___0~1#1); 3634#L1768-2 [2023-11-12 02:13:40,720 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-12 02:13:40,720 INFO L85 PathProgramCache]: Analyzing trace with hash -1422298547, now seen corresponding path program 2 times [2023-11-12 02:13:40,721 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-12 02:13:40,721 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [130390309] [2023-11-12 02:13:40,721 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-12 02:13:40,722 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-12 02:13:40,745 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-12 02:13:40,818 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-12 02:13:40,818 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-12 02:13:40,818 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [130390309] [2023-11-12 02:13:40,819 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [130390309] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-12 02:13:40,819 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-12 02:13:40,819 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-12 02:13:40,819 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1763689756] [2023-11-12 02:13:40,819 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-12 02:13:40,820 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-12 02:13:40,820 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-12 02:13:40,821 INFO L85 PathProgramCache]: Analyzing trace with hash -1137085798, now seen corresponding path program 1 times [2023-11-12 02:13:40,821 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-12 02:13:40,821 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [644286891] [2023-11-12 02:13:40,821 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-12 02:13:40,822 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-12 02:13:40,875 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-12 02:13:41,022 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-12 02:13:41,023 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-12 02:13:41,023 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [644286891] [2023-11-12 02:13:41,023 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [644286891] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-12 02:13:41,023 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-12 02:13:41,024 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-12 02:13:41,024 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [983041943] [2023-11-12 02:13:41,024 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-12 02:13:41,025 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-12 02:13:41,025 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-12 02:13:41,026 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-12 02:13:41,026 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-12 02:13:41,026 INFO L87 Difference]: Start difference. First operand 1701 states and 2517 transitions. cyclomatic complexity: 817 Second operand has 3 states, 3 states have (on average 49.333333333333336) internal successors, (148), 3 states have internal predecessors, (148), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-12 02:13:41,081 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-12 02:13:41,082 INFO L93 Difference]: Finished difference Result 1701 states and 2516 transitions. [2023-11-12 02:13:41,082 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1701 states and 2516 transitions. [2023-11-12 02:13:41,098 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1540 [2023-11-12 02:13:41,113 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1701 states to 1701 states and 2516 transitions. [2023-11-12 02:13:41,114 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1701 [2023-11-12 02:13:41,116 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1701 [2023-11-12 02:13:41,116 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1701 states and 2516 transitions. [2023-11-12 02:13:41,119 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-12 02:13:41,119 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1701 states and 2516 transitions. [2023-11-12 02:13:41,123 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1701 states and 2516 transitions. [2023-11-12 02:13:41,150 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1701 to 1701. [2023-11-12 02:13:41,154 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1701 states, 1701 states have (on average 1.479129923574368) internal successors, (2516), 1700 states have internal predecessors, (2516), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-12 02:13:41,162 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1701 states to 1701 states and 2516 transitions. [2023-11-12 02:13:41,163 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1701 states and 2516 transitions. [2023-11-12 02:13:41,165 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-12 02:13:41,166 INFO L428 stractBuchiCegarLoop]: Abstraction has 1701 states and 2516 transitions. [2023-11-12 02:13:41,166 INFO L335 stractBuchiCegarLoop]: ======== Iteration 3 ============ [2023-11-12 02:13:41,166 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1701 states and 2516 transitions. [2023-11-12 02:13:41,177 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1540 [2023-11-12 02:13:41,177 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-12 02:13:41,178 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-12 02:13:41,180 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-12 02:13:41,181 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-12 02:13:41,181 INFO L748 eck$LassoCheckResult]: Stem: 7111#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2; 7112#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~14#1;havoc main_~__retres1~14#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1; 7904#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret32#1, start_simulation_#t~ret33#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 7905#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 7772#L821 assume 1 == ~m_i~0;~m_st~0 := 0; 7773#L821-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 7866#L826-1 assume !(1 == ~t2_i~0);~t2_st~0 := 2; 8165#L831-1 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 8300#L836-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 8301#L841-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 7087#L846-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 7088#L851-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 8232#L856-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 7670#L861-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 7671#L866-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 7581#L871-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 7582#L876-1 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 7975#L881-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 7326#L1174 assume !(0 == ~M_E~0); 7327#L1174-2 assume 0 == ~T1_E~0;~T1_E~0 := 1; 7178#L1179-1 assume !(0 == ~T2_E~0); 7084#L1184-1 assume !(0 == ~T3_E~0); 7085#L1189-1 assume !(0 == ~T4_E~0); 7127#L1194-1 assume !(0 == ~T5_E~0); 7220#L1199-1 assume !(0 == ~T6_E~0); 8099#L1204-1 assume !(0 == ~T7_E~0); 8020#L1209-1 assume !(0 == ~T8_E~0); 8021#L1214-1 assume 0 == ~T9_E~0;~T9_E~0 := 1; 8444#L1219-1 assume !(0 == ~T10_E~0); 8529#L1224-1 assume !(0 == ~T11_E~0); 7443#L1229-1 assume !(0 == ~T12_E~0); 7014#L1234-1 assume !(0 == ~E_1~0); 7015#L1239-1 assume !(0 == ~E_2~0); 7047#L1244-1 assume !(0 == ~E_3~0); 7048#L1249-1 assume !(0 == ~E_4~0); 7690#L1254-1 assume 0 == ~E_5~0;~E_5~0 := 1; 6944#L1259-1 assume !(0 == ~E_6~0); 6897#L1264-1 assume !(0 == ~E_7~0); 6898#L1269-1 assume !(0 == ~E_8~0); 8532#L1274-1 assume !(0 == ~E_9~0); 8471#L1279-1 assume !(0 == ~E_10~0); 7131#L1284-1 assume !(0 == ~E_11~0); 7132#L1289-1 assume !(0 == ~E_12~0); 7742#L1294-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 7743#L566 assume 1 == ~m_pc~0; 6914#L567 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 6915#L577 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 7786#is_master_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 7787#L1455 assume !(0 != activate_threads_~tmp~1#1); 7353#L1455-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 7354#L585 assume 1 == ~t1_pc~0; 7011#L586 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 7012#L596 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 8155#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 8156#L1463 assume !(0 != activate_threads_~tmp___0~0#1); 8500#L1463-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 8496#L604 assume !(1 == ~t2_pc~0); 8061#L604-2 is_transmit2_triggered_~__retres1~2#1 := 0; 8062#L615 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 7296#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 7297#L1471 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 8260#L1471-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 8261#L623 assume 1 == ~t3_pc~0; 7527#L624 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 6873#L634 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 8130#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 8131#L1479 assume !(0 != activate_threads_~tmp___2~0#1); 8294#L1479-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 6911#L642 assume !(1 == ~t4_pc~0); 6912#L642-2 is_transmit4_triggered_~__retres1~4#1 := 0; 7364#L653 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 6966#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 6967#L1487 assume !(0 != activate_threads_~tmp___3~0#1); 6988#L1487-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 8074#L661 assume 1 == ~t5_pc~0; 7144#L662 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 7145#L672 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 7992#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 8359#L1495 assume !(0 != activate_threads_~tmp___4~0#1); 8106#L1495-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 8107#L680 assume !(1 == ~t6_pc~0); 7560#L680-2 is_transmit6_triggered_~__retres1~6#1 := 0; 7561#L691 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 7287#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 7288#L1503 assume !(0 != activate_threads_~tmp___5~0#1); 8369#L1503-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 8493#L699 assume 1 == ~t7_pc~0; 7955#L700 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 7956#L710 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 8188#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 7848#L1511 assume !(0 != activate_threads_~tmp___6~0#1); 7849#L1511-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 7744#L718 assume !(1 == ~t8_pc~0); 7745#L718-2 is_transmit8_triggered_~__retres1~8#1 := 0; 7125#L729 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 7126#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 7160#L1519 assume !(0 != activate_threads_~tmp___7~0#1); 7161#L1519-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 7293#L737 assume 1 == ~t9_pc~0; 8144#L738 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 7424#L748 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 7333#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 7334#L1527 assume !(0 != activate_threads_~tmp___8~0#1); 7601#L1527-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 7602#L756 assume 1 == ~t10_pc~0; 8178#L757 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 7839#L767 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 8094#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 7779#L1535 assume !(0 != activate_threads_~tmp___9~0#1); 7403#L1535-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 7404#L775 assume !(1 == ~t11_pc~0); 7662#L775-2 is_transmit11_triggered_~__retres1~11#1 := 0; 7663#L786 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 8437#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 7059#L1543 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 7060#L1543-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 7241#L794 assume 1 == ~t12_pc~0; 7082#L795 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 7062#L805 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 6917#is_transmit12_triggered_returnLabel#1 activate_threads_#t~ret30#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 6918#L1551 assume !(0 != activate_threads_~tmp___11~0#1); 7206#L1551-2 havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 7674#L1307 assume !(1 == ~M_E~0); 7675#L1307-2 assume !(1 == ~T1_E~0); 7783#L1312-1 assume !(1 == ~T2_E~0); 7703#L1317-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 7704#L1322-1 assume !(1 == ~T4_E~0); 7414#L1327-1 assume !(1 == ~T5_E~0); 7415#L1332-1 assume !(1 == ~T6_E~0); 7960#L1337-1 assume !(1 == ~T7_E~0); 7917#L1342-1 assume !(1 == ~T8_E~0); 7918#L1347-1 assume !(1 == ~T9_E~0); 8330#L1352-1 assume !(1 == ~T10_E~0); 8189#L1357-1 assume 1 == ~T11_E~0;~T11_E~0 := 2; 7579#L1362-1 assume !(1 == ~T12_E~0); 7580#L1367-1 assume !(1 == ~E_1~0); 7221#L1372-1 assume !(1 == ~E_2~0); 7222#L1377-1 assume !(1 == ~E_3~0); 7512#L1382-1 assume !(1 == ~E_4~0); 7513#L1387-1 assume !(1 == ~E_5~0); 8063#L1392-1 assume !(1 == ~E_6~0); 7530#L1397-1 assume 1 == ~E_7~0;~E_7~0 := 2; 7531#L1402-1 assume !(1 == ~E_8~0); 7236#L1407-1 assume !(1 == ~E_9~0); 7237#L1412-1 assume !(1 == ~E_10~0); 8255#L1417-1 assume !(1 == ~E_11~0); 8256#L1422-1 assume !(1 == ~E_12~0); 8490#L1427-1 assume { :end_inline_reset_delta_events } true; 7043#L1768-2 [2023-11-12 02:13:41,182 INFO L750 eck$LassoCheckResult]: Loop: 7043#L1768-2 assume !false; 7044#L1769 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 7707#L1149-1 assume !false; 8085#L972 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 8312#L894 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 7421#L961 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 8237#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 8307#L976 assume !(0 != eval_~tmp~0#1); 7735#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 7464#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 7465#L1174-3 assume 0 == ~M_E~0;~M_E~0 := 1; 8265#L1174-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 8003#L1179-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 8004#L1184-3 assume !(0 == ~T3_E~0); 8190#L1189-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 7834#L1194-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 7197#L1199-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 7198#L1204-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 7434#L1209-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 6857#L1214-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 6858#L1219-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 7614#L1224-3 assume !(0 == ~T11_E~0); 7615#L1229-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 7629#L1234-3 assume 0 == ~E_1~0;~E_1~0 := 1; 7053#L1239-3 assume 0 == ~E_2~0;~E_2~0 := 1; 7054#L1244-3 assume 0 == ~E_3~0;~E_3~0 := 1; 7489#L1249-3 assume 0 == ~E_4~0;~E_4~0 := 1; 7947#L1254-3 assume 0 == ~E_5~0;~E_5~0 := 1; 8440#L1259-3 assume 0 == ~E_6~0;~E_6~0 := 1; 8046#L1264-3 assume !(0 == ~E_7~0); 7057#L1269-3 assume 0 == ~E_8~0;~E_8~0 := 1; 7058#L1274-3 assume 0 == ~E_9~0;~E_9~0 := 1; 8470#L1279-3 assume 0 == ~E_10~0;~E_10~0 := 1; 7610#L1284-3 assume 0 == ~E_11~0;~E_11~0 := 1; 7611#L1289-3 assume 0 == ~E_12~0;~E_12~0 := 1; 7598#L1294-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 7277#L566-39 assume 1 == ~m_pc~0; 7278#L567-13 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 7877#L577-13 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 7878#is_master_triggered_returnLabel#14 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 7930#L1455-39 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 8121#L1455-41 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 8122#L585-39 assume !(1 == ~t1_pc~0); 7285#L585-41 is_transmit1_triggered_~__retres1~1#1 := 0; 7286#L596-13 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 7486#is_transmit1_triggered_returnLabel#14 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 8434#L1463-39 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 8159#L1463-41 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 7854#L604-39 assume !(1 == ~t2_pc~0); 7856#L604-41 is_transmit2_triggered_~__retres1~2#1 := 0; 7493#L615-13 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 7494#is_transmit2_triggered_returnLabel#14 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 7673#L1471-39 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 7907#L1471-41 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 7475#L623-39 assume 1 == ~t3_pc~0; 6874#L624-13 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 6875#L634-13 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 8139#is_transmit3_triggered_returnLabel#14 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 7328#L1479-39 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 7329#L1479-41 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 8081#L642-39 assume 1 == ~t4_pc~0; 7664#L643-13 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 7665#L653-13 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 7829#is_transmit4_triggered_returnLabel#14 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 7830#L1487-39 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 8311#L1487-41 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 7247#L661-39 assume 1 == ~t5_pc~0; 7248#L662-13 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 6883#L672-13 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 7861#is_transmit5_triggered_returnLabel#14 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 7862#L1495-39 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 8141#L1495-41 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 8142#L680-39 assume 1 == ~t6_pc~0; 6949#L681-13 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 6950#L691-13 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 8390#is_transmit6_triggered_returnLabel#14 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 7401#L1503-39 assume !(0 != activate_threads_~tmp___5~0#1); 7402#L1503-41 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 8446#L699-39 assume 1 == ~t7_pc~0; 7836#L700-13 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 7563#L710-13 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 7564#is_transmit7_triggered_returnLabel#14 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 8146#L1511-39 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 8386#L1511-41 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 8383#L718-39 assume 1 == ~t8_pc~0; 7748#L719-13 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 7749#L729-13 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 8242#is_transmit8_triggered_returnLabel#14 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 8243#L1519-39 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 7991#L1519-41 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 7968#L737-39 assume 1 == ~t9_pc~0; 7382#L738-13 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 7383#L748-13 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 6977#is_transmit9_triggered_returnLabel#14 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 6978#L1527-39 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 8358#L1527-41 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 8295#L756-39 assume !(1 == ~t10_pc~0); 7762#L756-41 is_transmit10_triggered_~__retres1~10#1 := 0; 7763#L767-13 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 8433#is_transmit10_triggered_returnLabel#14 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 7647#L1535-39 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 7648#L1535-41 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 6998#L775-39 assume 1 == ~t11_pc~0; 6999#L776-13 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 7638#L786-13 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 7639#is_transmit11_triggered_returnLabel#14 activate_threads_#t~ret29#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 7888#L1543-39 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 8039#L1543-41 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 7689#L794-39 assume !(1 == ~t12_pc~0); 7378#L794-41 is_transmit12_triggered_~__retres1~12#1 := 0; 7379#L805-13 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 7472#is_transmit12_triggered_returnLabel#14 activate_threads_#t~ret30#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 7473#L1551-39 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 6940#L1551-41 havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 6941#L1307-3 assume 1 == ~M_E~0;~M_E~0 := 2; 8417#L1307-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 8418#L1312-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 8531#L1317-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 8108#L1322-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 8109#L1327-3 assume !(1 == ~T5_E~0); 7074#L1332-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 7049#L1337-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 7050#L1342-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 7777#L1347-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 7910#L1352-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 7911#L1357-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 8366#L1362-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 8526#L1367-3 assume !(1 == ~E_1~0); 8517#L1372-3 assume 1 == ~E_2~0;~E_2~0 := 2; 6870#L1377-3 assume 1 == ~E_3~0;~E_3~0 := 2; 6871#L1382-3 assume 1 == ~E_4~0;~E_4~0 := 2; 7496#L1387-3 assume 1 == ~E_5~0;~E_5~0 := 2; 7497#L1392-3 assume 1 == ~E_6~0;~E_6~0 := 2; 8216#L1397-3 assume 1 == ~E_7~0;~E_7~0 := 2; 8484#L1402-3 assume 1 == ~E_8~0;~E_8~0 := 2; 7876#L1407-3 assume !(1 == ~E_9~0); 7156#L1412-3 assume 1 == ~E_10~0;~E_10~0 := 2; 7157#L1417-3 assume 1 == ~E_11~0;~E_11~0 := 2; 7791#L1422-3 assume 1 == ~E_12~0;~E_12~0 := 2; 7792#L1427-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 7164#L894-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 7165#L961-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 7232#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret32#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret32#1;havoc start_simulation_#t~ret32#1; 7233#L1787 assume !(0 == start_simulation_~tmp~3#1); 7880#L1787-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret31#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 8426#L894-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 7141#L961-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 6889#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret31#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret31#1;havoc stop_simulation_#t~ret31#1; 6890#L1742 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 7482#L1749 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 7483#stop_simulation_returnLabel#1 start_simulation_#t~ret33#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret31#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret33#1;havoc start_simulation_#t~ret33#1; 8393#L1800 assume !(0 != start_simulation_~tmp___0~1#1); 7043#L1768-2 [2023-11-12 02:13:41,182 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-12 02:13:41,182 INFO L85 PathProgramCache]: Analyzing trace with hash -1760586097, now seen corresponding path program 1 times [2023-11-12 02:13:41,183 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-12 02:13:41,183 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [936558529] [2023-11-12 02:13:41,183 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-12 02:13:41,183 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-12 02:13:41,218 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-12 02:13:41,289 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-12 02:13:41,289 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-12 02:13:41,290 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [936558529] [2023-11-12 02:13:41,290 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [936558529] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-12 02:13:41,290 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-12 02:13:41,290 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-12 02:13:41,291 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1300579325] [2023-11-12 02:13:41,291 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-12 02:13:41,291 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-12 02:13:41,292 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-12 02:13:41,292 INFO L85 PathProgramCache]: Analyzing trace with hash -1670129477, now seen corresponding path program 1 times [2023-11-12 02:13:41,292 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-12 02:13:41,292 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1724580230] [2023-11-12 02:13:41,293 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-12 02:13:41,293 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-12 02:13:41,313 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-12 02:13:41,402 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-12 02:13:41,402 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-12 02:13:41,402 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1724580230] [2023-11-12 02:13:41,402 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1724580230] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-12 02:13:41,403 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-12 02:13:41,403 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-12 02:13:41,403 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [126024506] [2023-11-12 02:13:41,403 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-12 02:13:41,404 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-12 02:13:41,404 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-12 02:13:41,405 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-12 02:13:41,405 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-12 02:13:41,405 INFO L87 Difference]: Start difference. First operand 1701 states and 2516 transitions. cyclomatic complexity: 816 Second operand has 3 states, 3 states have (on average 49.333333333333336) internal successors, (148), 3 states have internal predecessors, (148), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-12 02:13:41,461 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-12 02:13:41,462 INFO L93 Difference]: Finished difference Result 1701 states and 2515 transitions. [2023-11-12 02:13:41,462 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1701 states and 2515 transitions. [2023-11-12 02:13:41,479 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1540 [2023-11-12 02:13:41,495 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1701 states to 1701 states and 2515 transitions. [2023-11-12 02:13:41,495 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1701 [2023-11-12 02:13:41,497 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1701 [2023-11-12 02:13:41,498 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1701 states and 2515 transitions. [2023-11-12 02:13:41,501 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-12 02:13:41,501 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1701 states and 2515 transitions. [2023-11-12 02:13:41,505 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1701 states and 2515 transitions. [2023-11-12 02:13:41,538 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1701 to 1701. [2023-11-12 02:13:41,542 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1701 states, 1701 states have (on average 1.4785420340975897) internal successors, (2515), 1700 states have internal predecessors, (2515), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-12 02:13:41,551 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1701 states to 1701 states and 2515 transitions. [2023-11-12 02:13:41,551 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1701 states and 2515 transitions. [2023-11-12 02:13:41,552 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-12 02:13:41,553 INFO L428 stractBuchiCegarLoop]: Abstraction has 1701 states and 2515 transitions. [2023-11-12 02:13:41,553 INFO L335 stractBuchiCegarLoop]: ======== Iteration 4 ============ [2023-11-12 02:13:41,553 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1701 states and 2515 transitions. [2023-11-12 02:13:41,565 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1540 [2023-11-12 02:13:41,565 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-12 02:13:41,565 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-12 02:13:41,568 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-12 02:13:41,569 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-12 02:13:41,570 INFO L748 eck$LassoCheckResult]: Stem: 10520#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2; 10521#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~14#1;havoc main_~__retres1~14#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1; 11313#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret32#1, start_simulation_#t~ret33#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 11314#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 11181#L821 assume 1 == ~m_i~0;~m_st~0 := 0; 11182#L821-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 11275#L826-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 11574#L831-1 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 11709#L836-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 11710#L841-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 10496#L846-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 10497#L851-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 11641#L856-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 11079#L861-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 11080#L866-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 10990#L871-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 10991#L876-1 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 11384#L881-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 10735#L1174 assume !(0 == ~M_E~0); 10736#L1174-2 assume 0 == ~T1_E~0;~T1_E~0 := 1; 10587#L1179-1 assume !(0 == ~T2_E~0); 10493#L1184-1 assume !(0 == ~T3_E~0); 10494#L1189-1 assume !(0 == ~T4_E~0); 10536#L1194-1 assume !(0 == ~T5_E~0); 10629#L1199-1 assume !(0 == ~T6_E~0); 11508#L1204-1 assume !(0 == ~T7_E~0); 11429#L1209-1 assume !(0 == ~T8_E~0); 11430#L1214-1 assume 0 == ~T9_E~0;~T9_E~0 := 1; 11853#L1219-1 assume !(0 == ~T10_E~0); 11938#L1224-1 assume !(0 == ~T11_E~0); 10852#L1229-1 assume !(0 == ~T12_E~0); 10423#L1234-1 assume !(0 == ~E_1~0); 10424#L1239-1 assume !(0 == ~E_2~0); 10456#L1244-1 assume !(0 == ~E_3~0); 10457#L1249-1 assume !(0 == ~E_4~0); 11099#L1254-1 assume 0 == ~E_5~0;~E_5~0 := 1; 10353#L1259-1 assume !(0 == ~E_6~0); 10306#L1264-1 assume !(0 == ~E_7~0); 10307#L1269-1 assume !(0 == ~E_8~0); 11941#L1274-1 assume !(0 == ~E_9~0); 11880#L1279-1 assume !(0 == ~E_10~0); 10540#L1284-1 assume !(0 == ~E_11~0); 10541#L1289-1 assume !(0 == ~E_12~0); 11151#L1294-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 11152#L566 assume 1 == ~m_pc~0; 10323#L567 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 10324#L577 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 11195#is_master_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 11196#L1455 assume !(0 != activate_threads_~tmp~1#1); 10762#L1455-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 10763#L585 assume 1 == ~t1_pc~0; 10420#L586 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 10421#L596 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 11564#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 11565#L1463 assume !(0 != activate_threads_~tmp___0~0#1); 11909#L1463-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 11905#L604 assume !(1 == ~t2_pc~0); 11470#L604-2 is_transmit2_triggered_~__retres1~2#1 := 0; 11471#L615 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 10705#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 10706#L1471 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 11669#L1471-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 11670#L623 assume 1 == ~t3_pc~0; 10936#L624 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 10282#L634 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 11539#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 11540#L1479 assume !(0 != activate_threads_~tmp___2~0#1); 11703#L1479-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 10320#L642 assume !(1 == ~t4_pc~0); 10321#L642-2 is_transmit4_triggered_~__retres1~4#1 := 0; 10773#L653 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 10375#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 10376#L1487 assume !(0 != activate_threads_~tmp___3~0#1); 10397#L1487-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 11483#L661 assume 1 == ~t5_pc~0; 10553#L662 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 10554#L672 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 11401#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 11768#L1495 assume !(0 != activate_threads_~tmp___4~0#1); 11515#L1495-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 11516#L680 assume !(1 == ~t6_pc~0); 10969#L680-2 is_transmit6_triggered_~__retres1~6#1 := 0; 10970#L691 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 10696#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 10697#L1503 assume !(0 != activate_threads_~tmp___5~0#1); 11778#L1503-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 11902#L699 assume 1 == ~t7_pc~0; 11364#L700 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 11365#L710 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 11597#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 11257#L1511 assume !(0 != activate_threads_~tmp___6~0#1); 11258#L1511-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 11153#L718 assume !(1 == ~t8_pc~0); 11154#L718-2 is_transmit8_triggered_~__retres1~8#1 := 0; 10534#L729 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 10535#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 10569#L1519 assume !(0 != activate_threads_~tmp___7~0#1); 10570#L1519-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 10702#L737 assume 1 == ~t9_pc~0; 11553#L738 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 10833#L748 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 10742#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 10743#L1527 assume !(0 != activate_threads_~tmp___8~0#1); 11010#L1527-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 11011#L756 assume 1 == ~t10_pc~0; 11587#L757 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 11248#L767 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 11503#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 11188#L1535 assume !(0 != activate_threads_~tmp___9~0#1); 10812#L1535-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 10813#L775 assume !(1 == ~t11_pc~0); 11071#L775-2 is_transmit11_triggered_~__retres1~11#1 := 0; 11072#L786 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 11846#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 10468#L1543 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 10469#L1543-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 10650#L794 assume 1 == ~t12_pc~0; 10491#L795 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 10471#L805 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 10326#is_transmit12_triggered_returnLabel#1 activate_threads_#t~ret30#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 10327#L1551 assume !(0 != activate_threads_~tmp___11~0#1); 10615#L1551-2 havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 11083#L1307 assume !(1 == ~M_E~0); 11084#L1307-2 assume !(1 == ~T1_E~0); 11192#L1312-1 assume !(1 == ~T2_E~0); 11112#L1317-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 11113#L1322-1 assume !(1 == ~T4_E~0); 10823#L1327-1 assume !(1 == ~T5_E~0); 10824#L1332-1 assume !(1 == ~T6_E~0); 11369#L1337-1 assume !(1 == ~T7_E~0); 11326#L1342-1 assume !(1 == ~T8_E~0); 11327#L1347-1 assume !(1 == ~T9_E~0); 11739#L1352-1 assume !(1 == ~T10_E~0); 11598#L1357-1 assume 1 == ~T11_E~0;~T11_E~0 := 2; 10988#L1362-1 assume !(1 == ~T12_E~0); 10989#L1367-1 assume !(1 == ~E_1~0); 10630#L1372-1 assume !(1 == ~E_2~0); 10631#L1377-1 assume !(1 == ~E_3~0); 10921#L1382-1 assume !(1 == ~E_4~0); 10922#L1387-1 assume !(1 == ~E_5~0); 11472#L1392-1 assume !(1 == ~E_6~0); 10939#L1397-1 assume 1 == ~E_7~0;~E_7~0 := 2; 10940#L1402-1 assume !(1 == ~E_8~0); 10645#L1407-1 assume !(1 == ~E_9~0); 10646#L1412-1 assume !(1 == ~E_10~0); 11664#L1417-1 assume !(1 == ~E_11~0); 11665#L1422-1 assume !(1 == ~E_12~0); 11899#L1427-1 assume { :end_inline_reset_delta_events } true; 10452#L1768-2 [2023-11-12 02:13:41,571 INFO L750 eck$LassoCheckResult]: Loop: 10452#L1768-2 assume !false; 10453#L1769 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 11116#L1149-1 assume !false; 11494#L972 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 11721#L894 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 10830#L961 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 11646#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 11716#L976 assume !(0 != eval_~tmp~0#1); 11144#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 10873#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 10874#L1174-3 assume 0 == ~M_E~0;~M_E~0 := 1; 11674#L1174-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 11412#L1179-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 11413#L1184-3 assume !(0 == ~T3_E~0); 11599#L1189-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 11243#L1194-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 10606#L1199-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 10607#L1204-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 10843#L1209-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 10266#L1214-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 10267#L1219-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 11023#L1224-3 assume !(0 == ~T11_E~0); 11024#L1229-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 11038#L1234-3 assume 0 == ~E_1~0;~E_1~0 := 1; 10462#L1239-3 assume 0 == ~E_2~0;~E_2~0 := 1; 10463#L1244-3 assume 0 == ~E_3~0;~E_3~0 := 1; 10898#L1249-3 assume 0 == ~E_4~0;~E_4~0 := 1; 11356#L1254-3 assume 0 == ~E_5~0;~E_5~0 := 1; 11849#L1259-3 assume 0 == ~E_6~0;~E_6~0 := 1; 11455#L1264-3 assume !(0 == ~E_7~0); 10466#L1269-3 assume 0 == ~E_8~0;~E_8~0 := 1; 10467#L1274-3 assume 0 == ~E_9~0;~E_9~0 := 1; 11879#L1279-3 assume 0 == ~E_10~0;~E_10~0 := 1; 11019#L1284-3 assume 0 == ~E_11~0;~E_11~0 := 1; 11020#L1289-3 assume 0 == ~E_12~0;~E_12~0 := 1; 11007#L1294-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 10686#L566-39 assume !(1 == ~m_pc~0); 10688#L566-41 is_master_triggered_~__retres1~0#1 := 0; 11286#L577-13 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 11287#is_master_triggered_returnLabel#14 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 11339#L1455-39 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 11530#L1455-41 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 11531#L585-39 assume !(1 == ~t1_pc~0); 10694#L585-41 is_transmit1_triggered_~__retres1~1#1 := 0; 10695#L596-13 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 10895#is_transmit1_triggered_returnLabel#14 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 11843#L1463-39 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 11568#L1463-41 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 11263#L604-39 assume 1 == ~t2_pc~0; 11264#L605-13 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 10902#L615-13 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 10903#is_transmit2_triggered_returnLabel#14 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 11082#L1471-39 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 11316#L1471-41 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 10884#L623-39 assume 1 == ~t3_pc~0; 10283#L624-13 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 10284#L634-13 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 11548#is_transmit3_triggered_returnLabel#14 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 10737#L1479-39 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 10738#L1479-41 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 11490#L642-39 assume 1 == ~t4_pc~0; 11073#L643-13 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 11074#L653-13 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 11238#is_transmit4_triggered_returnLabel#14 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 11239#L1487-39 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 11720#L1487-41 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 10656#L661-39 assume 1 == ~t5_pc~0; 10657#L662-13 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 10292#L672-13 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 11270#is_transmit5_triggered_returnLabel#14 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 11271#L1495-39 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 11550#L1495-41 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 11551#L680-39 assume 1 == ~t6_pc~0; 10358#L681-13 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 10359#L691-13 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 11799#is_transmit6_triggered_returnLabel#14 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 10810#L1503-39 assume !(0 != activate_threads_~tmp___5~0#1); 10811#L1503-41 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 11855#L699-39 assume 1 == ~t7_pc~0; 11245#L700-13 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 10972#L710-13 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 10973#is_transmit7_triggered_returnLabel#14 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 11555#L1511-39 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 11795#L1511-41 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 11792#L718-39 assume 1 == ~t8_pc~0; 11157#L719-13 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 11158#L729-13 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 11651#is_transmit8_triggered_returnLabel#14 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 11652#L1519-39 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 11400#L1519-41 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 11377#L737-39 assume 1 == ~t9_pc~0; 10791#L738-13 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 10792#L748-13 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 10386#is_transmit9_triggered_returnLabel#14 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 10387#L1527-39 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 11767#L1527-41 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 11704#L756-39 assume !(1 == ~t10_pc~0); 11171#L756-41 is_transmit10_triggered_~__retres1~10#1 := 0; 11172#L767-13 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 11842#is_transmit10_triggered_returnLabel#14 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 11056#L1535-39 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 11057#L1535-41 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 10407#L775-39 assume 1 == ~t11_pc~0; 10408#L776-13 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 11047#L786-13 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 11048#is_transmit11_triggered_returnLabel#14 activate_threads_#t~ret29#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 11297#L1543-39 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 11448#L1543-41 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 11098#L794-39 assume !(1 == ~t12_pc~0); 10787#L794-41 is_transmit12_triggered_~__retres1~12#1 := 0; 10788#L805-13 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 10881#is_transmit12_triggered_returnLabel#14 activate_threads_#t~ret30#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 10882#L1551-39 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 10349#L1551-41 havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 10350#L1307-3 assume 1 == ~M_E~0;~M_E~0 := 2; 11826#L1307-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 11827#L1312-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 11940#L1317-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 11517#L1322-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 11518#L1327-3 assume !(1 == ~T5_E~0); 10483#L1332-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 10458#L1337-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 10459#L1342-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 11186#L1347-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 11319#L1352-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 11320#L1357-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 11775#L1362-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 11935#L1367-3 assume !(1 == ~E_1~0); 11926#L1372-3 assume 1 == ~E_2~0;~E_2~0 := 2; 10279#L1377-3 assume 1 == ~E_3~0;~E_3~0 := 2; 10280#L1382-3 assume 1 == ~E_4~0;~E_4~0 := 2; 10905#L1387-3 assume 1 == ~E_5~0;~E_5~0 := 2; 10906#L1392-3 assume 1 == ~E_6~0;~E_6~0 := 2; 11625#L1397-3 assume 1 == ~E_7~0;~E_7~0 := 2; 11893#L1402-3 assume 1 == ~E_8~0;~E_8~0 := 2; 11285#L1407-3 assume !(1 == ~E_9~0); 10565#L1412-3 assume 1 == ~E_10~0;~E_10~0 := 2; 10566#L1417-3 assume 1 == ~E_11~0;~E_11~0 := 2; 11200#L1422-3 assume 1 == ~E_12~0;~E_12~0 := 2; 11201#L1427-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 10573#L894-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 10574#L961-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 10641#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret32#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret32#1;havoc start_simulation_#t~ret32#1; 10642#L1787 assume !(0 == start_simulation_~tmp~3#1); 11289#L1787-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret31#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 11835#L894-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 10550#L961-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 10298#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret31#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret31#1;havoc stop_simulation_#t~ret31#1; 10299#L1742 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 10891#L1749 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 10892#stop_simulation_returnLabel#1 start_simulation_#t~ret33#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret31#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret33#1;havoc start_simulation_#t~ret33#1; 11802#L1800 assume !(0 != start_simulation_~tmp___0~1#1); 10452#L1768-2 [2023-11-12 02:13:41,574 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-12 02:13:41,575 INFO L85 PathProgramCache]: Analyzing trace with hash -1220156591, now seen corresponding path program 1 times [2023-11-12 02:13:41,575 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-12 02:13:41,575 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1171702967] [2023-11-12 02:13:41,575 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-12 02:13:41,576 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-12 02:13:41,600 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-12 02:13:41,653 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-12 02:13:41,653 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-12 02:13:41,654 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1171702967] [2023-11-12 02:13:41,654 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1171702967] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-12 02:13:41,655 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-12 02:13:41,655 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-12 02:13:41,655 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1497958086] [2023-11-12 02:13:41,655 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-12 02:13:41,656 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-12 02:13:41,656 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-12 02:13:41,656 INFO L85 PathProgramCache]: Analyzing trace with hash 2042585659, now seen corresponding path program 1 times [2023-11-12 02:13:41,657 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-12 02:13:41,661 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1610993407] [2023-11-12 02:13:41,662 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-12 02:13:41,662 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-12 02:13:41,692 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-12 02:13:41,770 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-12 02:13:41,770 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-12 02:13:41,770 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1610993407] [2023-11-12 02:13:41,770 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1610993407] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-12 02:13:41,770 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-12 02:13:41,771 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-12 02:13:41,771 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [61866070] [2023-11-12 02:13:41,771 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-12 02:13:41,772 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-12 02:13:41,772 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-12 02:13:41,772 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-12 02:13:41,773 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-12 02:13:41,773 INFO L87 Difference]: Start difference. First operand 1701 states and 2515 transitions. cyclomatic complexity: 815 Second operand has 3 states, 3 states have (on average 49.333333333333336) internal successors, (148), 3 states have internal predecessors, (148), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-12 02:13:41,826 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-12 02:13:41,827 INFO L93 Difference]: Finished difference Result 1701 states and 2514 transitions. [2023-11-12 02:13:41,827 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1701 states and 2514 transitions. [2023-11-12 02:13:41,841 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1540 [2023-11-12 02:13:41,855 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1701 states to 1701 states and 2514 transitions. [2023-11-12 02:13:41,855 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1701 [2023-11-12 02:13:41,857 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1701 [2023-11-12 02:13:41,857 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1701 states and 2514 transitions. [2023-11-12 02:13:41,861 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-12 02:13:41,862 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1701 states and 2514 transitions. [2023-11-12 02:13:41,866 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1701 states and 2514 transitions. [2023-11-12 02:13:41,937 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1701 to 1701. [2023-11-12 02:13:41,941 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1701 states, 1701 states have (on average 1.4779541446208113) internal successors, (2514), 1700 states have internal predecessors, (2514), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-12 02:13:41,948 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1701 states to 1701 states and 2514 transitions. [2023-11-12 02:13:41,948 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1701 states and 2514 transitions. [2023-11-12 02:13:41,949 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-12 02:13:41,951 INFO L428 stractBuchiCegarLoop]: Abstraction has 1701 states and 2514 transitions. [2023-11-12 02:13:41,951 INFO L335 stractBuchiCegarLoop]: ======== Iteration 5 ============ [2023-11-12 02:13:41,953 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1701 states and 2514 transitions. [2023-11-12 02:13:41,965 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1540 [2023-11-12 02:13:41,966 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-12 02:13:41,966 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-12 02:13:41,969 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-12 02:13:41,969 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-12 02:13:41,970 INFO L748 eck$LassoCheckResult]: Stem: 13929#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2; 13930#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~14#1;havoc main_~__retres1~14#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1; 14723#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret32#1, start_simulation_#t~ret33#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 14724#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 14590#L821 assume 1 == ~m_i~0;~m_st~0 := 0; 14591#L821-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 14684#L826-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 14988#L831-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 15118#L836-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 15119#L841-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 13905#L846-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 13906#L851-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 15050#L856-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 14488#L861-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 14489#L866-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 14401#L871-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 14402#L876-1 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 14793#L881-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 14144#L1174 assume !(0 == ~M_E~0); 14145#L1174-2 assume 0 == ~T1_E~0;~T1_E~0 := 1; 13998#L1179-1 assume !(0 == ~T2_E~0); 13902#L1184-1 assume !(0 == ~T3_E~0); 13903#L1189-1 assume !(0 == ~T4_E~0); 13945#L1194-1 assume !(0 == ~T5_E~0); 14040#L1199-1 assume !(0 == ~T6_E~0); 14917#L1204-1 assume !(0 == ~T7_E~0); 14838#L1209-1 assume !(0 == ~T8_E~0); 14839#L1214-1 assume 0 == ~T9_E~0;~T9_E~0 := 1; 15262#L1219-1 assume !(0 == ~T10_E~0); 15347#L1224-1 assume !(0 == ~T11_E~0); 14263#L1229-1 assume !(0 == ~T12_E~0); 13832#L1234-1 assume !(0 == ~E_1~0); 13833#L1239-1 assume !(0 == ~E_2~0); 13867#L1244-1 assume !(0 == ~E_3~0); 13868#L1249-1 assume !(0 == ~E_4~0); 14508#L1254-1 assume 0 == ~E_5~0;~E_5~0 := 1; 13762#L1259-1 assume !(0 == ~E_6~0); 13715#L1264-1 assume !(0 == ~E_7~0); 13716#L1269-1 assume !(0 == ~E_8~0); 15350#L1274-1 assume !(0 == ~E_9~0); 15290#L1279-1 assume !(0 == ~E_10~0); 13949#L1284-1 assume !(0 == ~E_11~0); 13950#L1289-1 assume !(0 == ~E_12~0); 14560#L1294-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 14561#L566 assume 1 == ~m_pc~0; 13732#L567 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 13733#L577 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 14604#is_master_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 14605#L1455 assume !(0 != activate_threads_~tmp~1#1); 14171#L1455-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 14172#L585 assume 1 == ~t1_pc~0; 13829#L586 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 13830#L596 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 14973#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 14974#L1463 assume !(0 != activate_threads_~tmp___0~0#1); 15318#L1463-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 15314#L604 assume !(1 == ~t2_pc~0); 14879#L604-2 is_transmit2_triggered_~__retres1~2#1 := 0; 14880#L615 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 14119#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 14120#L1471 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 15080#L1471-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 15081#L623 assume 1 == ~t3_pc~0; 14345#L624 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 13691#L634 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 14951#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 14952#L1479 assume !(0 != activate_threads_~tmp___2~0#1); 15112#L1479-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 13729#L642 assume !(1 == ~t4_pc~0); 13730#L642-2 is_transmit4_triggered_~__retres1~4#1 := 0; 14182#L653 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 13790#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 13791#L1487 assume !(0 != activate_threads_~tmp___3~0#1); 13806#L1487-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 14892#L661 assume 1 == ~t5_pc~0; 13962#L662 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 13963#L672 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 14810#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 15177#L1495 assume !(0 != activate_threads_~tmp___4~0#1); 14926#L1495-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 14927#L680 assume !(1 == ~t6_pc~0); 14378#L680-2 is_transmit6_triggered_~__retres1~6#1 := 0; 14379#L691 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 14108#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 14109#L1503 assume !(0 != activate_threads_~tmp___5~0#1); 15187#L1503-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 15312#L699 assume 1 == ~t7_pc~0; 14773#L700 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 14774#L710 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 15006#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 14666#L1511 assume !(0 != activate_threads_~tmp___6~0#1); 14667#L1511-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 14562#L718 assume !(1 == ~t8_pc~0); 14563#L718-2 is_transmit8_triggered_~__retres1~8#1 := 0; 13943#L729 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 13944#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 13980#L1519 assume !(0 != activate_threads_~tmp___7~0#1); 13981#L1519-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 14111#L737 assume 1 == ~t9_pc~0; 14964#L738 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 14244#L748 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 14151#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 14152#L1527 assume !(0 != activate_threads_~tmp___8~0#1); 14419#L1527-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 14420#L756 assume 1 == ~t10_pc~0; 14996#L757 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 14658#L767 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 14912#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 14597#L1535 assume !(0 != activate_threads_~tmp___9~0#1); 14221#L1535-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 14222#L775 assume !(1 == ~t11_pc~0); 14480#L775-2 is_transmit11_triggered_~__retres1~11#1 := 0; 14481#L786 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 15255#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 13877#L1543 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 13878#L1543-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 14059#L794 assume 1 == ~t12_pc~0; 13901#L795 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 13880#L805 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 13737#is_transmit12_triggered_returnLabel#1 activate_threads_#t~ret30#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 13738#L1551 assume !(0 != activate_threads_~tmp___11~0#1); 14026#L1551-2 havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 14492#L1307 assume !(1 == ~M_E~0); 14493#L1307-2 assume !(1 == ~T1_E~0); 14601#L1312-1 assume !(1 == ~T2_E~0); 14521#L1317-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 14522#L1322-1 assume !(1 == ~T4_E~0); 14232#L1327-1 assume !(1 == ~T5_E~0); 14233#L1332-1 assume !(1 == ~T6_E~0); 14778#L1337-1 assume !(1 == ~T7_E~0); 14736#L1342-1 assume !(1 == ~T8_E~0); 14737#L1347-1 assume !(1 == ~T9_E~0); 15148#L1352-1 assume !(1 == ~T10_E~0); 15007#L1357-1 assume 1 == ~T11_E~0;~T11_E~0 := 2; 14397#L1362-1 assume !(1 == ~T12_E~0); 14398#L1367-1 assume !(1 == ~E_1~0); 14041#L1372-1 assume !(1 == ~E_2~0); 14042#L1377-1 assume !(1 == ~E_3~0); 14330#L1382-1 assume !(1 == ~E_4~0); 14331#L1387-1 assume !(1 == ~E_5~0); 14881#L1392-1 assume !(1 == ~E_6~0); 14350#L1397-1 assume 1 == ~E_7~0;~E_7~0 := 2; 14351#L1402-1 assume !(1 == ~E_8~0); 14057#L1407-1 assume !(1 == ~E_9~0); 14058#L1412-1 assume !(1 == ~E_10~0); 15073#L1417-1 assume !(1 == ~E_11~0); 15074#L1422-1 assume !(1 == ~E_12~0); 15308#L1427-1 assume { :end_inline_reset_delta_events } true; 13861#L1768-2 [2023-11-12 02:13:41,970 INFO L750 eck$LassoCheckResult]: Loop: 13861#L1768-2 assume !false; 13862#L1769 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 14525#L1149-1 assume !false; 14905#L972 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 15130#L894 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 14239#L961 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 15055#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 15125#L976 assume !(0 != eval_~tmp~0#1); 14553#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 14282#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 14283#L1174-3 assume 0 == ~M_E~0;~M_E~0 := 1; 15083#L1174-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 14821#L1179-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 14822#L1184-3 assume !(0 == ~T3_E~0); 15009#L1189-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 14652#L1194-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 14018#L1199-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 14019#L1204-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 14252#L1209-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 13675#L1214-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 13676#L1219-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 14432#L1224-3 assume !(0 == ~T11_E~0); 14433#L1229-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 14447#L1234-3 assume 0 == ~E_1~0;~E_1~0 := 1; 13869#L1239-3 assume 0 == ~E_2~0;~E_2~0 := 1; 13870#L1244-3 assume 0 == ~E_3~0;~E_3~0 := 1; 14307#L1249-3 assume 0 == ~E_4~0;~E_4~0 := 1; 14765#L1254-3 assume 0 == ~E_5~0;~E_5~0 := 1; 15258#L1259-3 assume 0 == ~E_6~0;~E_6~0 := 1; 14864#L1264-3 assume !(0 == ~E_7~0); 13875#L1269-3 assume 0 == ~E_8~0;~E_8~0 := 1; 13876#L1274-3 assume 0 == ~E_9~0;~E_9~0 := 1; 15288#L1279-3 assume 0 == ~E_10~0;~E_10~0 := 1; 14428#L1284-3 assume 0 == ~E_11~0;~E_11~0 := 1; 14429#L1289-3 assume 0 == ~E_12~0;~E_12~0 := 1; 14416#L1294-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 14095#L566-39 assume 1 == ~m_pc~0; 14096#L567-13 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 14695#L577-13 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 14696#is_master_triggered_returnLabel#14 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 14748#L1455-39 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 14939#L1455-41 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 14940#L585-39 assume !(1 == ~t1_pc~0); 14103#L585-41 is_transmit1_triggered_~__retres1~1#1 := 0; 14104#L596-13 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 14304#is_transmit1_triggered_returnLabel#14 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 15252#L1463-39 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 14977#L1463-41 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 14672#L604-39 assume 1 == ~t2_pc~0; 14673#L605-13 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 14311#L615-13 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 14312#is_transmit2_triggered_returnLabel#14 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 14491#L1471-39 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 14725#L1471-41 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 14293#L623-39 assume 1 == ~t3_pc~0; 13692#L624-13 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 13693#L634-13 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 14957#is_transmit3_triggered_returnLabel#14 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 14146#L1479-39 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 14147#L1479-41 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 14899#L642-39 assume 1 == ~t4_pc~0; 14482#L643-13 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 14483#L653-13 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 14647#is_transmit4_triggered_returnLabel#14 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 14648#L1487-39 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 15129#L1487-41 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 14065#L661-39 assume 1 == ~t5_pc~0; 14066#L662-13 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 13701#L672-13 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 14679#is_transmit5_triggered_returnLabel#14 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 14680#L1495-39 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 14959#L1495-41 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 14960#L680-39 assume 1 == ~t6_pc~0; 13767#L681-13 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 13768#L691-13 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 15208#is_transmit6_triggered_returnLabel#14 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 14219#L1503-39 assume !(0 != activate_threads_~tmp___5~0#1); 14220#L1503-41 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 15264#L699-39 assume 1 == ~t7_pc~0; 14654#L700-13 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 14381#L710-13 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 14382#is_transmit7_triggered_returnLabel#14 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 14963#L1511-39 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 15204#L1511-41 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 15201#L718-39 assume 1 == ~t8_pc~0; 14566#L719-13 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 14567#L729-13 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 15060#is_transmit8_triggered_returnLabel#14 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 15061#L1519-39 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 14809#L1519-41 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 14786#L737-39 assume 1 == ~t9_pc~0; 14200#L738-13 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 14201#L748-13 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 13795#is_transmit9_triggered_returnLabel#14 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 13796#L1527-39 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 15176#L1527-41 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 15113#L756-39 assume !(1 == ~t10_pc~0); 14580#L756-41 is_transmit10_triggered_~__retres1~10#1 := 0; 14581#L767-13 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 15251#is_transmit10_triggered_returnLabel#14 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 14465#L1535-39 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 14466#L1535-41 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 13816#L775-39 assume 1 == ~t11_pc~0; 13817#L776-13 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 14456#L786-13 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 14457#is_transmit11_triggered_returnLabel#14 activate_threads_#t~ret29#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 14706#L1543-39 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 14857#L1543-41 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 14507#L794-39 assume !(1 == ~t12_pc~0); 14196#L794-41 is_transmit12_triggered_~__retres1~12#1 := 0; 14197#L805-13 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 14290#is_transmit12_triggered_returnLabel#14 activate_threads_#t~ret30#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 14291#L1551-39 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 13758#L1551-41 havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 13759#L1307-3 assume 1 == ~M_E~0;~M_E~0 := 2; 15235#L1307-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 15236#L1312-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 15349#L1317-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 14924#L1322-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 14925#L1327-3 assume !(1 == ~T5_E~0); 13892#L1332-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 13865#L1337-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 13866#L1342-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 14595#L1347-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 14728#L1352-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 14729#L1357-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 15184#L1362-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 15344#L1367-3 assume !(1 == ~E_1~0); 15335#L1372-3 assume 1 == ~E_2~0;~E_2~0 := 2; 13685#L1377-3 assume 1 == ~E_3~0;~E_3~0 := 2; 13686#L1382-3 assume 1 == ~E_4~0;~E_4~0 := 2; 14314#L1387-3 assume 1 == ~E_5~0;~E_5~0 := 2; 14315#L1392-3 assume 1 == ~E_6~0;~E_6~0 := 2; 15034#L1397-3 assume 1 == ~E_7~0;~E_7~0 := 2; 15302#L1402-3 assume 1 == ~E_8~0;~E_8~0 := 2; 14694#L1407-3 assume !(1 == ~E_9~0); 13974#L1412-3 assume 1 == ~E_10~0;~E_10~0 := 2; 13975#L1417-3 assume 1 == ~E_11~0;~E_11~0 := 2; 14609#L1422-3 assume 1 == ~E_12~0;~E_12~0 := 2; 14610#L1427-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 13982#L894-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 13983#L961-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 14050#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret32#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret32#1;havoc start_simulation_#t~ret32#1; 14051#L1787 assume !(0 == start_simulation_~tmp~3#1); 14697#L1787-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret31#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 15244#L894-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 13959#L961-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 13704#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret31#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret31#1;havoc stop_simulation_#t~ret31#1; 13705#L1742 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 14300#L1749 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 14301#stop_simulation_returnLabel#1 start_simulation_#t~ret33#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret31#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret33#1;havoc start_simulation_#t~ret33#1; 15211#L1800 assume !(0 != start_simulation_~tmp___0~1#1); 13861#L1768-2 [2023-11-12 02:13:41,972 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-12 02:13:41,976 INFO L85 PathProgramCache]: Analyzing trace with hash -1064176049, now seen corresponding path program 1 times [2023-11-12 02:13:41,976 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-12 02:13:41,977 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1901287223] [2023-11-12 02:13:41,977 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-12 02:13:41,977 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-12 02:13:41,997 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-12 02:13:42,041 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-12 02:13:42,041 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-12 02:13:42,042 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1901287223] [2023-11-12 02:13:42,042 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1901287223] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-12 02:13:42,042 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-12 02:13:42,043 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-12 02:13:42,043 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [956877974] [2023-11-12 02:13:42,043 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-12 02:13:42,043 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-12 02:13:42,044 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-12 02:13:42,044 INFO L85 PathProgramCache]: Analyzing trace with hash -432476388, now seen corresponding path program 1 times [2023-11-12 02:13:42,044 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-12 02:13:42,044 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1926264798] [2023-11-12 02:13:42,044 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-12 02:13:42,045 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-12 02:13:42,065 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-12 02:13:42,124 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-12 02:13:42,125 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-12 02:13:42,125 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1926264798] [2023-11-12 02:13:42,125 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1926264798] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-12 02:13:42,125 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-12 02:13:42,125 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-12 02:13:42,126 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1930453674] [2023-11-12 02:13:42,126 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-12 02:13:42,126 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-12 02:13:42,126 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-12 02:13:42,127 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-12 02:13:42,127 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-12 02:13:42,127 INFO L87 Difference]: Start difference. First operand 1701 states and 2514 transitions. cyclomatic complexity: 814 Second operand has 3 states, 3 states have (on average 49.333333333333336) internal successors, (148), 3 states have internal predecessors, (148), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-12 02:13:42,174 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-12 02:13:42,174 INFO L93 Difference]: Finished difference Result 1701 states and 2513 transitions. [2023-11-12 02:13:42,175 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1701 states and 2513 transitions. [2023-11-12 02:13:42,190 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1540 [2023-11-12 02:13:42,204 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1701 states to 1701 states and 2513 transitions. [2023-11-12 02:13:42,204 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1701 [2023-11-12 02:13:42,206 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1701 [2023-11-12 02:13:42,206 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1701 states and 2513 transitions. [2023-11-12 02:13:42,209 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-12 02:13:42,209 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1701 states and 2513 transitions. [2023-11-12 02:13:42,213 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1701 states and 2513 transitions. [2023-11-12 02:13:42,240 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1701 to 1701. [2023-11-12 02:13:42,244 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1701 states, 1701 states have (on average 1.477366255144033) internal successors, (2513), 1700 states have internal predecessors, (2513), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-12 02:13:42,251 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1701 states to 1701 states and 2513 transitions. [2023-11-12 02:13:42,251 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1701 states and 2513 transitions. [2023-11-12 02:13:42,252 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-12 02:13:42,254 INFO L428 stractBuchiCegarLoop]: Abstraction has 1701 states and 2513 transitions. [2023-11-12 02:13:42,255 INFO L335 stractBuchiCegarLoop]: ======== Iteration 6 ============ [2023-11-12 02:13:42,255 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1701 states and 2513 transitions. [2023-11-12 02:13:42,262 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1540 [2023-11-12 02:13:42,262 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-12 02:13:42,263 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-12 02:13:42,265 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-12 02:13:42,265 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-12 02:13:42,266 INFO L748 eck$LassoCheckResult]: Stem: 17338#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2; 17339#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~14#1;havoc main_~__retres1~14#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1; 18131#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret32#1, start_simulation_#t~ret33#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 18132#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 17999#L821 assume 1 == ~m_i~0;~m_st~0 := 0; 18000#L821-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 18093#L826-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 18394#L831-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 18527#L836-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 18528#L841-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 17314#L846-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 17315#L851-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 18459#L856-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 17897#L861-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 17898#L866-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 17808#L871-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 17809#L876-1 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 18202#L881-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 17553#L1174 assume !(0 == ~M_E~0); 17554#L1174-2 assume 0 == ~T1_E~0;~T1_E~0 := 1; 17407#L1179-1 assume !(0 == ~T2_E~0); 17311#L1184-1 assume !(0 == ~T3_E~0); 17312#L1189-1 assume !(0 == ~T4_E~0); 17354#L1194-1 assume !(0 == ~T5_E~0); 17449#L1199-1 assume !(0 == ~T6_E~0); 18326#L1204-1 assume !(0 == ~T7_E~0); 18247#L1209-1 assume !(0 == ~T8_E~0); 18248#L1214-1 assume 0 == ~T9_E~0;~T9_E~0 := 1; 18671#L1219-1 assume !(0 == ~T10_E~0); 18756#L1224-1 assume !(0 == ~T11_E~0); 17670#L1229-1 assume !(0 == ~T12_E~0); 17241#L1234-1 assume !(0 == ~E_1~0); 17242#L1239-1 assume !(0 == ~E_2~0); 17276#L1244-1 assume !(0 == ~E_3~0); 17277#L1249-1 assume !(0 == ~E_4~0); 17917#L1254-1 assume 0 == ~E_5~0;~E_5~0 := 1; 17171#L1259-1 assume !(0 == ~E_6~0); 17124#L1264-1 assume !(0 == ~E_7~0); 17125#L1269-1 assume !(0 == ~E_8~0); 18759#L1274-1 assume !(0 == ~E_9~0); 18699#L1279-1 assume !(0 == ~E_10~0); 17358#L1284-1 assume !(0 == ~E_11~0); 17359#L1289-1 assume !(0 == ~E_12~0); 17969#L1294-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 17970#L566 assume 1 == ~m_pc~0; 17141#L567 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 17142#L577 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 18013#is_master_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 18014#L1455 assume !(0 != activate_threads_~tmp~1#1); 17580#L1455-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 17581#L585 assume 1 == ~t1_pc~0; 17238#L586 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 17239#L596 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 18382#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 18383#L1463 assume !(0 != activate_threads_~tmp___0~0#1); 18727#L1463-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 18723#L604 assume !(1 == ~t2_pc~0); 18288#L604-2 is_transmit2_triggered_~__retres1~2#1 := 0; 18289#L615 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 17528#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 17529#L1471 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 18489#L1471-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 18490#L623 assume 1 == ~t3_pc~0; 17754#L624 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 17100#L634 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 18360#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 18361#L1479 assume !(0 != activate_threads_~tmp___2~0#1); 18521#L1479-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 17138#L642 assume !(1 == ~t4_pc~0); 17139#L642-2 is_transmit4_triggered_~__retres1~4#1 := 0; 17591#L653 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 17196#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 17197#L1487 assume !(0 != activate_threads_~tmp___3~0#1); 17215#L1487-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 18301#L661 assume 1 == ~t5_pc~0; 17371#L662 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 17372#L672 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 18219#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 18586#L1495 assume !(0 != activate_threads_~tmp___4~0#1); 18335#L1495-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 18336#L680 assume !(1 == ~t6_pc~0); 17787#L680-2 is_transmit6_triggered_~__retres1~6#1 := 0; 17788#L691 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 17514#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 17515#L1503 assume !(0 != activate_threads_~tmp___5~0#1); 18596#L1503-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 18721#L699 assume 1 == ~t7_pc~0; 18182#L700 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 18183#L710 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 18415#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 18075#L1511 assume !(0 != activate_threads_~tmp___6~0#1); 18076#L1511-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 17971#L718 assume !(1 == ~t8_pc~0); 17972#L718-2 is_transmit8_triggered_~__retres1~8#1 := 0; 17352#L729 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 17353#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 17387#L1519 assume !(0 != activate_threads_~tmp___7~0#1); 17388#L1519-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 17520#L737 assume 1 == ~t9_pc~0; 18373#L738 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 17651#L748 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 17560#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 17561#L1527 assume !(0 != activate_threads_~tmp___8~0#1); 17828#L1527-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 17829#L756 assume 1 == ~t10_pc~0; 18405#L757 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 18066#L767 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 18321#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 18006#L1535 assume !(0 != activate_threads_~tmp___9~0#1); 17630#L1535-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 17631#L775 assume !(1 == ~t11_pc~0); 17889#L775-2 is_transmit11_triggered_~__retres1~11#1 := 0; 17890#L786 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 18664#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 17286#L1543 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 17287#L1543-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 17468#L794 assume 1 == ~t12_pc~0; 17310#L795 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 17289#L805 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 17146#is_transmit12_triggered_returnLabel#1 activate_threads_#t~ret30#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 17147#L1551 assume !(0 != activate_threads_~tmp___11~0#1); 17435#L1551-2 havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 17901#L1307 assume !(1 == ~M_E~0); 17902#L1307-2 assume !(1 == ~T1_E~0); 18010#L1312-1 assume !(1 == ~T2_E~0); 17930#L1317-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 17931#L1322-1 assume !(1 == ~T4_E~0); 17641#L1327-1 assume !(1 == ~T5_E~0); 17642#L1332-1 assume !(1 == ~T6_E~0); 18187#L1337-1 assume !(1 == ~T7_E~0); 18144#L1342-1 assume !(1 == ~T8_E~0); 18145#L1347-1 assume !(1 == ~T9_E~0); 18557#L1352-1 assume !(1 == ~T10_E~0); 18416#L1357-1 assume 1 == ~T11_E~0;~T11_E~0 := 2; 17806#L1362-1 assume !(1 == ~T12_E~0); 17807#L1367-1 assume !(1 == ~E_1~0); 17450#L1372-1 assume !(1 == ~E_2~0); 17451#L1377-1 assume !(1 == ~E_3~0); 17739#L1382-1 assume !(1 == ~E_4~0); 17740#L1387-1 assume !(1 == ~E_5~0); 18290#L1392-1 assume !(1 == ~E_6~0); 17759#L1397-1 assume 1 == ~E_7~0;~E_7~0 := 2; 17760#L1402-1 assume !(1 == ~E_8~0); 17463#L1407-1 assume !(1 == ~E_9~0); 17464#L1412-1 assume !(1 == ~E_10~0); 18482#L1417-1 assume !(1 == ~E_11~0); 18483#L1422-1 assume !(1 == ~E_12~0); 18717#L1427-1 assume { :end_inline_reset_delta_events } true; 17270#L1768-2 [2023-11-12 02:13:42,267 INFO L750 eck$LassoCheckResult]: Loop: 17270#L1768-2 assume !false; 17271#L1769 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 17934#L1149-1 assume !false; 18314#L972 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 18539#L894 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 17648#L961 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 18464#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 18534#L976 assume !(0 != eval_~tmp~0#1); 17962#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 17691#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 17692#L1174-3 assume 0 == ~M_E~0;~M_E~0 := 1; 18492#L1174-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 18230#L1179-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 18231#L1184-3 assume !(0 == ~T3_E~0); 18417#L1189-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 18061#L1194-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 17427#L1199-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 17428#L1204-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 17661#L1209-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 17084#L1214-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 17085#L1219-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 17841#L1224-3 assume !(0 == ~T11_E~0); 17842#L1229-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 17856#L1234-3 assume 0 == ~E_1~0;~E_1~0 := 1; 17280#L1239-3 assume 0 == ~E_2~0;~E_2~0 := 1; 17281#L1244-3 assume 0 == ~E_3~0;~E_3~0 := 1; 17716#L1249-3 assume 0 == ~E_4~0;~E_4~0 := 1; 18174#L1254-3 assume 0 == ~E_5~0;~E_5~0 := 1; 18667#L1259-3 assume 0 == ~E_6~0;~E_6~0 := 1; 18273#L1264-3 assume !(0 == ~E_7~0); 17284#L1269-3 assume 0 == ~E_8~0;~E_8~0 := 1; 17285#L1274-3 assume 0 == ~E_9~0;~E_9~0 := 1; 18697#L1279-3 assume 0 == ~E_10~0;~E_10~0 := 1; 17837#L1284-3 assume 0 == ~E_11~0;~E_11~0 := 1; 17838#L1289-3 assume 0 == ~E_12~0;~E_12~0 := 1; 17825#L1294-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 17504#L566-39 assume 1 == ~m_pc~0; 17505#L567-13 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 18104#L577-13 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 18105#is_master_triggered_returnLabel#14 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 18157#L1455-39 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 18348#L1455-41 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 18349#L585-39 assume !(1 == ~t1_pc~0); 17512#L585-41 is_transmit1_triggered_~__retres1~1#1 := 0; 17513#L596-13 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 17713#is_transmit1_triggered_returnLabel#14 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 18661#L1463-39 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 18386#L1463-41 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 18083#L604-39 assume 1 == ~t2_pc~0; 18084#L605-13 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 17720#L615-13 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 17721#is_transmit2_triggered_returnLabel#14 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 17900#L1471-39 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 18138#L1471-41 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 17702#L623-39 assume !(1 == ~t3_pc~0); 17105#L623-41 is_transmit3_triggered_~__retres1~3#1 := 0; 17104#L634-13 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 18366#is_transmit3_triggered_returnLabel#14 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 17555#L1479-39 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 17556#L1479-41 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 18308#L642-39 assume 1 == ~t4_pc~0; 17893#L643-13 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 17894#L653-13 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 18056#is_transmit4_triggered_returnLabel#14 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 18057#L1487-39 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 18538#L1487-41 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 17473#L661-39 assume 1 == ~t5_pc~0; 17474#L662-13 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 17107#L672-13 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 18088#is_transmit5_triggered_returnLabel#14 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 18089#L1495-39 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 18368#L1495-41 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 18369#L680-39 assume 1 == ~t6_pc~0; 17176#L681-13 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 17177#L691-13 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 18617#is_transmit6_triggered_returnLabel#14 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 17628#L1503-39 assume !(0 != activate_threads_~tmp___5~0#1); 17629#L1503-41 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 18673#L699-39 assume !(1 == ~t7_pc~0); 18064#L699-41 is_transmit7_triggered_~__retres1~7#1 := 0; 17790#L710-13 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 17791#is_transmit7_triggered_returnLabel#14 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 18372#L1511-39 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 18611#L1511-41 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 18610#L718-39 assume 1 == ~t8_pc~0; 17975#L719-13 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 17976#L729-13 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 18468#is_transmit8_triggered_returnLabel#14 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 18469#L1519-39 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 18218#L1519-41 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 18195#L737-39 assume 1 == ~t9_pc~0; 17609#L738-13 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 17610#L748-13 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 17203#is_transmit9_triggered_returnLabel#14 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 17204#L1527-39 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 18585#L1527-41 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 18522#L756-39 assume !(1 == ~t10_pc~0); 17989#L756-41 is_transmit10_triggered_~__retres1~10#1 := 0; 17990#L767-13 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 18660#is_transmit10_triggered_returnLabel#14 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 17874#L1535-39 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 17875#L1535-41 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 17225#L775-39 assume 1 == ~t11_pc~0; 17226#L776-13 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 17865#L786-13 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 17866#is_transmit11_triggered_returnLabel#14 activate_threads_#t~ret29#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 18115#L1543-39 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 18266#L1543-41 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 17916#L794-39 assume !(1 == ~t12_pc~0); 17605#L794-41 is_transmit12_triggered_~__retres1~12#1 := 0; 17606#L805-13 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 17697#is_transmit12_triggered_returnLabel#14 activate_threads_#t~ret30#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 17698#L1551-39 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 17167#L1551-41 havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 17168#L1307-3 assume 1 == ~M_E~0;~M_E~0 := 2; 18644#L1307-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 18645#L1312-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 18758#L1317-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 18333#L1322-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 18334#L1327-3 assume !(1 == ~T5_E~0); 17299#L1332-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 17274#L1337-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 17275#L1342-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 18004#L1347-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 18136#L1352-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 18137#L1357-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 18593#L1362-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 18753#L1367-3 assume !(1 == ~E_1~0); 18744#L1372-3 assume 1 == ~E_2~0;~E_2~0 := 2; 17094#L1377-3 assume 1 == ~E_3~0;~E_3~0 := 2; 17095#L1382-3 assume 1 == ~E_4~0;~E_4~0 := 2; 17723#L1387-3 assume 1 == ~E_5~0;~E_5~0 := 2; 17724#L1392-3 assume 1 == ~E_6~0;~E_6~0 := 2; 18443#L1397-3 assume 1 == ~E_7~0;~E_7~0 := 2; 18711#L1402-3 assume 1 == ~E_8~0;~E_8~0 := 2; 18103#L1407-3 assume !(1 == ~E_9~0); 17383#L1412-3 assume 1 == ~E_10~0;~E_10~0 := 2; 17384#L1417-3 assume 1 == ~E_11~0;~E_11~0 := 2; 18017#L1422-3 assume 1 == ~E_12~0;~E_12~0 := 2; 18018#L1427-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 17391#L894-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 17392#L961-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 17459#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret32#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret32#1;havoc start_simulation_#t~ret32#1; 17460#L1787 assume !(0 == start_simulation_~tmp~3#1); 18106#L1787-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret31#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 18653#L894-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 17368#L961-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 17113#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret31#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret31#1;havoc stop_simulation_#t~ret31#1; 17114#L1742 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 17709#L1749 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 17710#stop_simulation_returnLabel#1 start_simulation_#t~ret33#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret31#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret33#1;havoc start_simulation_#t~ret33#1; 18620#L1800 assume !(0 != start_simulation_~tmp___0~1#1); 17270#L1768-2 [2023-11-12 02:13:42,268 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-12 02:13:42,268 INFO L85 PathProgramCache]: Analyzing trace with hash -1474786415, now seen corresponding path program 1 times [2023-11-12 02:13:42,268 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-12 02:13:42,268 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1533157872] [2023-11-12 02:13:42,269 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-12 02:13:42,269 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-12 02:13:42,299 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-12 02:13:42,345 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-12 02:13:42,345 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-12 02:13:42,345 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1533157872] [2023-11-12 02:13:42,345 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1533157872] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-12 02:13:42,345 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-12 02:13:42,346 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-12 02:13:42,346 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [748829234] [2023-11-12 02:13:42,346 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-12 02:13:42,346 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-12 02:13:42,347 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-12 02:13:42,347 INFO L85 PathProgramCache]: Analyzing trace with hash -634554918, now seen corresponding path program 1 times [2023-11-12 02:13:42,352 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-12 02:13:42,352 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [591635192] [2023-11-12 02:13:42,353 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-12 02:13:42,353 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-12 02:13:42,384 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-12 02:13:42,440 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-12 02:13:42,441 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-12 02:13:42,441 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [591635192] [2023-11-12 02:13:42,441 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [591635192] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-12 02:13:42,441 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-12 02:13:42,441 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-12 02:13:42,442 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1098511017] [2023-11-12 02:13:42,442 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-12 02:13:42,442 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-12 02:13:42,443 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-12 02:13:42,443 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-12 02:13:42,443 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-12 02:13:42,443 INFO L87 Difference]: Start difference. First operand 1701 states and 2513 transitions. cyclomatic complexity: 813 Second operand has 3 states, 3 states have (on average 49.333333333333336) internal successors, (148), 3 states have internal predecessors, (148), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-12 02:13:42,520 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-12 02:13:42,521 INFO L93 Difference]: Finished difference Result 1701 states and 2512 transitions. [2023-11-12 02:13:42,521 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1701 states and 2512 transitions. [2023-11-12 02:13:42,532 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1540 [2023-11-12 02:13:42,546 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1701 states to 1701 states and 2512 transitions. [2023-11-12 02:13:42,547 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1701 [2023-11-12 02:13:42,548 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1701 [2023-11-12 02:13:42,548 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1701 states and 2512 transitions. [2023-11-12 02:13:42,551 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-12 02:13:42,551 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1701 states and 2512 transitions. [2023-11-12 02:13:42,555 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1701 states and 2512 transitions. [2023-11-12 02:13:42,580 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1701 to 1701. [2023-11-12 02:13:42,584 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1701 states, 1701 states have (on average 1.4767783656672546) internal successors, (2512), 1700 states have internal predecessors, (2512), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-12 02:13:42,592 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1701 states to 1701 states and 2512 transitions. [2023-11-12 02:13:42,592 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1701 states and 2512 transitions. [2023-11-12 02:13:42,592 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-12 02:13:42,594 INFO L428 stractBuchiCegarLoop]: Abstraction has 1701 states and 2512 transitions. [2023-11-12 02:13:42,594 INFO L335 stractBuchiCegarLoop]: ======== Iteration 7 ============ [2023-11-12 02:13:42,594 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1701 states and 2512 transitions. [2023-11-12 02:13:42,602 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1540 [2023-11-12 02:13:42,602 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-12 02:13:42,604 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-12 02:13:42,607 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-12 02:13:42,607 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-12 02:13:42,607 INFO L748 eck$LassoCheckResult]: Stem: 20747#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2; 20748#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~14#1;havoc main_~__retres1~14#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1; 21540#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret32#1, start_simulation_#t~ret33#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 21541#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 21408#L821 assume 1 == ~m_i~0;~m_st~0 := 0; 21409#L821-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 21502#L826-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 21801#L831-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 21936#L836-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 21937#L841-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 20723#L846-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 20724#L851-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 21868#L856-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 21306#L861-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 21307#L866-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 21217#L871-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 21218#L876-1 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 21611#L881-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 20962#L1174 assume !(0 == ~M_E~0); 20963#L1174-2 assume 0 == ~T1_E~0;~T1_E~0 := 1; 20814#L1179-1 assume !(0 == ~T2_E~0); 20720#L1184-1 assume !(0 == ~T3_E~0); 20721#L1189-1 assume !(0 == ~T4_E~0); 20763#L1194-1 assume !(0 == ~T5_E~0); 20856#L1199-1 assume !(0 == ~T6_E~0); 21735#L1204-1 assume !(0 == ~T7_E~0); 21656#L1209-1 assume !(0 == ~T8_E~0); 21657#L1214-1 assume 0 == ~T9_E~0;~T9_E~0 := 1; 22080#L1219-1 assume !(0 == ~T10_E~0); 22165#L1224-1 assume !(0 == ~T11_E~0); 21079#L1229-1 assume !(0 == ~T12_E~0); 20650#L1234-1 assume !(0 == ~E_1~0); 20651#L1239-1 assume !(0 == ~E_2~0); 20683#L1244-1 assume !(0 == ~E_3~0); 20684#L1249-1 assume !(0 == ~E_4~0); 21326#L1254-1 assume 0 == ~E_5~0;~E_5~0 := 1; 20580#L1259-1 assume !(0 == ~E_6~0); 20533#L1264-1 assume !(0 == ~E_7~0); 20534#L1269-1 assume !(0 == ~E_8~0); 22168#L1274-1 assume !(0 == ~E_9~0); 22107#L1279-1 assume !(0 == ~E_10~0); 20767#L1284-1 assume !(0 == ~E_11~0); 20768#L1289-1 assume !(0 == ~E_12~0); 21378#L1294-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 21379#L566 assume 1 == ~m_pc~0; 20550#L567 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 20551#L577 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 21422#is_master_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 21423#L1455 assume !(0 != activate_threads_~tmp~1#1); 20989#L1455-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 20990#L585 assume 1 == ~t1_pc~0; 20647#L586 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 20648#L596 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 21791#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 21792#L1463 assume !(0 != activate_threads_~tmp___0~0#1); 22136#L1463-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 22132#L604 assume !(1 == ~t2_pc~0); 21697#L604-2 is_transmit2_triggered_~__retres1~2#1 := 0; 21698#L615 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 20932#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 20933#L1471 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 21896#L1471-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 21897#L623 assume 1 == ~t3_pc~0; 21163#L624 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 20509#L634 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 21766#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 21767#L1479 assume !(0 != activate_threads_~tmp___2~0#1); 21930#L1479-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 20547#L642 assume !(1 == ~t4_pc~0); 20548#L642-2 is_transmit4_triggered_~__retres1~4#1 := 0; 21000#L653 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 20602#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 20603#L1487 assume !(0 != activate_threads_~tmp___3~0#1); 20624#L1487-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 21710#L661 assume 1 == ~t5_pc~0; 20780#L662 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 20781#L672 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 21628#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 21995#L1495 assume !(0 != activate_threads_~tmp___4~0#1); 21742#L1495-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 21743#L680 assume !(1 == ~t6_pc~0); 21196#L680-2 is_transmit6_triggered_~__retres1~6#1 := 0; 21197#L691 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 20923#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 20924#L1503 assume !(0 != activate_threads_~tmp___5~0#1); 22005#L1503-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 22129#L699 assume 1 == ~t7_pc~0; 21591#L700 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 21592#L710 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 21824#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 21484#L1511 assume !(0 != activate_threads_~tmp___6~0#1); 21485#L1511-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 21380#L718 assume !(1 == ~t8_pc~0); 21381#L718-2 is_transmit8_triggered_~__retres1~8#1 := 0; 20761#L729 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 20762#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 20796#L1519 assume !(0 != activate_threads_~tmp___7~0#1); 20797#L1519-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 20929#L737 assume 1 == ~t9_pc~0; 21780#L738 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 21060#L748 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 20969#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 20970#L1527 assume !(0 != activate_threads_~tmp___8~0#1); 21237#L1527-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 21238#L756 assume 1 == ~t10_pc~0; 21814#L757 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 21475#L767 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 21730#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 21415#L1535 assume !(0 != activate_threads_~tmp___9~0#1); 21039#L1535-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 21040#L775 assume !(1 == ~t11_pc~0); 21298#L775-2 is_transmit11_triggered_~__retres1~11#1 := 0; 21299#L786 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 22073#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 20695#L1543 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 20696#L1543-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 20877#L794 assume 1 == ~t12_pc~0; 20718#L795 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 20698#L805 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 20553#is_transmit12_triggered_returnLabel#1 activate_threads_#t~ret30#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 20554#L1551 assume !(0 != activate_threads_~tmp___11~0#1); 20842#L1551-2 havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 21310#L1307 assume !(1 == ~M_E~0); 21311#L1307-2 assume !(1 == ~T1_E~0); 21419#L1312-1 assume !(1 == ~T2_E~0); 21339#L1317-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 21340#L1322-1 assume !(1 == ~T4_E~0); 21050#L1327-1 assume !(1 == ~T5_E~0); 21051#L1332-1 assume !(1 == ~T6_E~0); 21596#L1337-1 assume !(1 == ~T7_E~0); 21553#L1342-1 assume !(1 == ~T8_E~0); 21554#L1347-1 assume !(1 == ~T9_E~0); 21966#L1352-1 assume !(1 == ~T10_E~0); 21825#L1357-1 assume 1 == ~T11_E~0;~T11_E~0 := 2; 21215#L1362-1 assume !(1 == ~T12_E~0); 21216#L1367-1 assume !(1 == ~E_1~0); 20857#L1372-1 assume !(1 == ~E_2~0); 20858#L1377-1 assume !(1 == ~E_3~0); 21148#L1382-1 assume !(1 == ~E_4~0); 21149#L1387-1 assume !(1 == ~E_5~0); 21699#L1392-1 assume !(1 == ~E_6~0); 21166#L1397-1 assume 1 == ~E_7~0;~E_7~0 := 2; 21167#L1402-1 assume !(1 == ~E_8~0); 20872#L1407-1 assume !(1 == ~E_9~0); 20873#L1412-1 assume !(1 == ~E_10~0); 21891#L1417-1 assume !(1 == ~E_11~0); 21892#L1422-1 assume !(1 == ~E_12~0); 22126#L1427-1 assume { :end_inline_reset_delta_events } true; 20679#L1768-2 [2023-11-12 02:13:42,608 INFO L750 eck$LassoCheckResult]: Loop: 20679#L1768-2 assume !false; 20680#L1769 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 21343#L1149-1 assume !false; 21721#L972 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 21948#L894 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 21057#L961 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 21873#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 21943#L976 assume !(0 != eval_~tmp~0#1); 21371#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 21100#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 21101#L1174-3 assume 0 == ~M_E~0;~M_E~0 := 1; 21901#L1174-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 21639#L1179-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 21640#L1184-3 assume !(0 == ~T3_E~0); 21826#L1189-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 21470#L1194-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 20833#L1199-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 20834#L1204-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 21070#L1209-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 20493#L1214-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 20494#L1219-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 21250#L1224-3 assume !(0 == ~T11_E~0); 21251#L1229-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 21265#L1234-3 assume 0 == ~E_1~0;~E_1~0 := 1; 20689#L1239-3 assume 0 == ~E_2~0;~E_2~0 := 1; 20690#L1244-3 assume 0 == ~E_3~0;~E_3~0 := 1; 21125#L1249-3 assume 0 == ~E_4~0;~E_4~0 := 1; 21583#L1254-3 assume 0 == ~E_5~0;~E_5~0 := 1; 22076#L1259-3 assume 0 == ~E_6~0;~E_6~0 := 1; 21682#L1264-3 assume !(0 == ~E_7~0); 20693#L1269-3 assume 0 == ~E_8~0;~E_8~0 := 1; 20694#L1274-3 assume 0 == ~E_9~0;~E_9~0 := 1; 22106#L1279-3 assume 0 == ~E_10~0;~E_10~0 := 1; 21246#L1284-3 assume 0 == ~E_11~0;~E_11~0 := 1; 21247#L1289-3 assume 0 == ~E_12~0;~E_12~0 := 1; 21234#L1294-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 20913#L566-39 assume 1 == ~m_pc~0; 20914#L567-13 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 21513#L577-13 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 21514#is_master_triggered_returnLabel#14 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 21566#L1455-39 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 21757#L1455-41 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 21758#L585-39 assume !(1 == ~t1_pc~0); 20921#L585-41 is_transmit1_triggered_~__retres1~1#1 := 0; 20922#L596-13 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 21122#is_transmit1_triggered_returnLabel#14 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 22070#L1463-39 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 21795#L1463-41 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 21490#L604-39 assume 1 == ~t2_pc~0; 21491#L605-13 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 21129#L615-13 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 21130#is_transmit2_triggered_returnLabel#14 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 21309#L1471-39 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 21543#L1471-41 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 21111#L623-39 assume !(1 == ~t3_pc~0); 20512#L623-41 is_transmit3_triggered_~__retres1~3#1 := 0; 20511#L634-13 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 21775#is_transmit3_triggered_returnLabel#14 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 20964#L1479-39 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 20965#L1479-41 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 21717#L642-39 assume 1 == ~t4_pc~0; 21300#L643-13 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 21301#L653-13 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 21465#is_transmit4_triggered_returnLabel#14 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 21466#L1487-39 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 21947#L1487-41 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 20883#L661-39 assume 1 == ~t5_pc~0; 20884#L662-13 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 20519#L672-13 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 21497#is_transmit5_triggered_returnLabel#14 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 21498#L1495-39 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 21777#L1495-41 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 21778#L680-39 assume 1 == ~t6_pc~0; 20585#L681-13 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 20586#L691-13 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 22026#is_transmit6_triggered_returnLabel#14 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 21037#L1503-39 assume !(0 != activate_threads_~tmp___5~0#1); 21038#L1503-41 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 22082#L699-39 assume 1 == ~t7_pc~0; 21472#L700-13 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 21199#L710-13 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 21200#is_transmit7_triggered_returnLabel#14 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 21782#L1511-39 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 22022#L1511-41 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 22019#L718-39 assume 1 == ~t8_pc~0; 21384#L719-13 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 21385#L729-13 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 21878#is_transmit8_triggered_returnLabel#14 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 21879#L1519-39 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 21627#L1519-41 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 21604#L737-39 assume 1 == ~t9_pc~0; 21018#L738-13 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 21019#L748-13 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 20613#is_transmit9_triggered_returnLabel#14 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 20614#L1527-39 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 21994#L1527-41 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 21931#L756-39 assume !(1 == ~t10_pc~0); 21398#L756-41 is_transmit10_triggered_~__retres1~10#1 := 0; 21399#L767-13 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 22069#is_transmit10_triggered_returnLabel#14 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 21283#L1535-39 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 21284#L1535-41 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 20634#L775-39 assume 1 == ~t11_pc~0; 20635#L776-13 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 21274#L786-13 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 21275#is_transmit11_triggered_returnLabel#14 activate_threads_#t~ret29#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 21524#L1543-39 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 21675#L1543-41 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 21325#L794-39 assume !(1 == ~t12_pc~0); 21014#L794-41 is_transmit12_triggered_~__retres1~12#1 := 0; 21015#L805-13 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 21108#is_transmit12_triggered_returnLabel#14 activate_threads_#t~ret30#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 21109#L1551-39 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 20576#L1551-41 havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 20577#L1307-3 assume 1 == ~M_E~0;~M_E~0 := 2; 22053#L1307-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 22054#L1312-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 22167#L1317-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 21744#L1322-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 21745#L1327-3 assume !(1 == ~T5_E~0); 20710#L1332-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 20685#L1337-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 20686#L1342-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 21413#L1347-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 21546#L1352-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 21547#L1357-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 22002#L1362-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 22162#L1367-3 assume !(1 == ~E_1~0); 22153#L1372-3 assume 1 == ~E_2~0;~E_2~0 := 2; 20506#L1377-3 assume 1 == ~E_3~0;~E_3~0 := 2; 20507#L1382-3 assume 1 == ~E_4~0;~E_4~0 := 2; 21132#L1387-3 assume 1 == ~E_5~0;~E_5~0 := 2; 21133#L1392-3 assume 1 == ~E_6~0;~E_6~0 := 2; 21852#L1397-3 assume 1 == ~E_7~0;~E_7~0 := 2; 22120#L1402-3 assume 1 == ~E_8~0;~E_8~0 := 2; 21512#L1407-3 assume !(1 == ~E_9~0); 20792#L1412-3 assume 1 == ~E_10~0;~E_10~0 := 2; 20793#L1417-3 assume 1 == ~E_11~0;~E_11~0 := 2; 21427#L1422-3 assume 1 == ~E_12~0;~E_12~0 := 2; 21428#L1427-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 20800#L894-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 20801#L961-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 20868#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret32#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret32#1;havoc start_simulation_#t~ret32#1; 20869#L1787 assume !(0 == start_simulation_~tmp~3#1); 21516#L1787-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret31#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 22062#L894-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 20777#L961-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 20525#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret31#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret31#1;havoc stop_simulation_#t~ret31#1; 20526#L1742 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 21118#L1749 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 21119#stop_simulation_returnLabel#1 start_simulation_#t~ret33#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret31#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret33#1;havoc start_simulation_#t~ret33#1; 22029#L1800 assume !(0 != start_simulation_~tmp___0~1#1); 20679#L1768-2 [2023-11-12 02:13:42,609 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-12 02:13:42,609 INFO L85 PathProgramCache]: Analyzing trace with hash 313083407, now seen corresponding path program 1 times [2023-11-12 02:13:42,609 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-12 02:13:42,609 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [624352158] [2023-11-12 02:13:42,611 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-12 02:13:42,611 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-12 02:13:42,628 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-12 02:13:42,670 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-12 02:13:42,670 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-12 02:13:42,671 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [624352158] [2023-11-12 02:13:42,671 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [624352158] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-12 02:13:42,671 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-12 02:13:42,671 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-12 02:13:42,671 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [265426572] [2023-11-12 02:13:42,671 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-12 02:13:42,672 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-12 02:13:42,672 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-12 02:13:42,672 INFO L85 PathProgramCache]: Analyzing trace with hash 1993292795, now seen corresponding path program 1 times [2023-11-12 02:13:42,673 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-12 02:13:42,673 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2019737466] [2023-11-12 02:13:42,673 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-12 02:13:42,673 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-12 02:13:42,692 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-12 02:13:42,766 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-12 02:13:42,766 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-12 02:13:42,766 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2019737466] [2023-11-12 02:13:42,767 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2019737466] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-12 02:13:42,767 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-12 02:13:42,767 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-12 02:13:42,767 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1942140350] [2023-11-12 02:13:42,767 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-12 02:13:42,768 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-12 02:13:42,768 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-12 02:13:42,768 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-12 02:13:42,768 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-12 02:13:42,769 INFO L87 Difference]: Start difference. First operand 1701 states and 2512 transitions. cyclomatic complexity: 812 Second operand has 3 states, 3 states have (on average 49.333333333333336) internal successors, (148), 3 states have internal predecessors, (148), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-12 02:13:42,815 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-12 02:13:42,815 INFO L93 Difference]: Finished difference Result 1701 states and 2511 transitions. [2023-11-12 02:13:42,815 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1701 states and 2511 transitions. [2023-11-12 02:13:42,827 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1540 [2023-11-12 02:13:42,841 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1701 states to 1701 states and 2511 transitions. [2023-11-12 02:13:42,841 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1701 [2023-11-12 02:13:42,845 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1701 [2023-11-12 02:13:42,845 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1701 states and 2511 transitions. [2023-11-12 02:13:42,848 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-12 02:13:42,848 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1701 states and 2511 transitions. [2023-11-12 02:13:42,852 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1701 states and 2511 transitions. [2023-11-12 02:13:42,880 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1701 to 1701. [2023-11-12 02:13:42,884 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1701 states, 1701 states have (on average 1.4761904761904763) internal successors, (2511), 1700 states have internal predecessors, (2511), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-12 02:13:42,891 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1701 states to 1701 states and 2511 transitions. [2023-11-12 02:13:42,892 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1701 states and 2511 transitions. [2023-11-12 02:13:42,892 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-12 02:13:42,894 INFO L428 stractBuchiCegarLoop]: Abstraction has 1701 states and 2511 transitions. [2023-11-12 02:13:42,894 INFO L335 stractBuchiCegarLoop]: ======== Iteration 8 ============ [2023-11-12 02:13:42,895 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1701 states and 2511 transitions. [2023-11-12 02:13:42,902 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1540 [2023-11-12 02:13:42,902 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-12 02:13:42,902 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-12 02:13:42,905 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-12 02:13:42,905 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-12 02:13:42,905 INFO L748 eck$LassoCheckResult]: Stem: 24156#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2; 24157#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~14#1;havoc main_~__retres1~14#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1; 24949#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret32#1, start_simulation_#t~ret33#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 24950#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 24817#L821 assume 1 == ~m_i~0;~m_st~0 := 0; 24818#L821-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 24911#L826-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 25210#L831-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 25345#L836-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 25346#L841-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 24132#L846-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 24133#L851-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 25277#L856-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 24715#L861-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 24716#L866-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 24626#L871-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 24627#L876-1 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 25020#L881-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 24371#L1174 assume !(0 == ~M_E~0); 24372#L1174-2 assume 0 == ~T1_E~0;~T1_E~0 := 1; 24223#L1179-1 assume !(0 == ~T2_E~0); 24129#L1184-1 assume !(0 == ~T3_E~0); 24130#L1189-1 assume !(0 == ~T4_E~0); 24172#L1194-1 assume !(0 == ~T5_E~0); 24265#L1199-1 assume !(0 == ~T6_E~0); 25144#L1204-1 assume !(0 == ~T7_E~0); 25065#L1209-1 assume !(0 == ~T8_E~0); 25066#L1214-1 assume 0 == ~T9_E~0;~T9_E~0 := 1; 25489#L1219-1 assume !(0 == ~T10_E~0); 25574#L1224-1 assume !(0 == ~T11_E~0); 24488#L1229-1 assume !(0 == ~T12_E~0); 24059#L1234-1 assume !(0 == ~E_1~0); 24060#L1239-1 assume !(0 == ~E_2~0); 24092#L1244-1 assume !(0 == ~E_3~0); 24093#L1249-1 assume !(0 == ~E_4~0); 24735#L1254-1 assume 0 == ~E_5~0;~E_5~0 := 1; 23989#L1259-1 assume !(0 == ~E_6~0); 23942#L1264-1 assume !(0 == ~E_7~0); 23943#L1269-1 assume !(0 == ~E_8~0); 25577#L1274-1 assume !(0 == ~E_9~0); 25516#L1279-1 assume !(0 == ~E_10~0); 24176#L1284-1 assume !(0 == ~E_11~0); 24177#L1289-1 assume !(0 == ~E_12~0); 24787#L1294-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 24788#L566 assume 1 == ~m_pc~0; 23959#L567 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 23960#L577 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 24831#is_master_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 24832#L1455 assume !(0 != activate_threads_~tmp~1#1); 24398#L1455-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 24399#L585 assume 1 == ~t1_pc~0; 24056#L586 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 24057#L596 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 25200#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 25201#L1463 assume !(0 != activate_threads_~tmp___0~0#1); 25545#L1463-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 25541#L604 assume !(1 == ~t2_pc~0); 25106#L604-2 is_transmit2_triggered_~__retres1~2#1 := 0; 25107#L615 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 24341#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 24342#L1471 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 25305#L1471-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 25306#L623 assume 1 == ~t3_pc~0; 24572#L624 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 23918#L634 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 25175#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 25176#L1479 assume !(0 != activate_threads_~tmp___2~0#1); 25339#L1479-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 23956#L642 assume !(1 == ~t4_pc~0); 23957#L642-2 is_transmit4_triggered_~__retres1~4#1 := 0; 24409#L653 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 24011#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 24012#L1487 assume !(0 != activate_threads_~tmp___3~0#1); 24033#L1487-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 25119#L661 assume 1 == ~t5_pc~0; 24189#L662 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 24190#L672 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 25037#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 25404#L1495 assume !(0 != activate_threads_~tmp___4~0#1); 25151#L1495-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 25152#L680 assume !(1 == ~t6_pc~0); 24605#L680-2 is_transmit6_triggered_~__retres1~6#1 := 0; 24606#L691 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 24332#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 24333#L1503 assume !(0 != activate_threads_~tmp___5~0#1); 25414#L1503-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 25538#L699 assume 1 == ~t7_pc~0; 25000#L700 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 25001#L710 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 25233#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 24893#L1511 assume !(0 != activate_threads_~tmp___6~0#1); 24894#L1511-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 24789#L718 assume !(1 == ~t8_pc~0); 24790#L718-2 is_transmit8_triggered_~__retres1~8#1 := 0; 24170#L729 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 24171#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 24205#L1519 assume !(0 != activate_threads_~tmp___7~0#1); 24206#L1519-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 24338#L737 assume 1 == ~t9_pc~0; 25189#L738 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 24469#L748 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 24378#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 24379#L1527 assume !(0 != activate_threads_~tmp___8~0#1); 24646#L1527-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 24647#L756 assume 1 == ~t10_pc~0; 25223#L757 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 24884#L767 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 25139#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 24824#L1535 assume !(0 != activate_threads_~tmp___9~0#1); 24448#L1535-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 24449#L775 assume !(1 == ~t11_pc~0); 24707#L775-2 is_transmit11_triggered_~__retres1~11#1 := 0; 24708#L786 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 25482#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 24104#L1543 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 24105#L1543-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 24286#L794 assume 1 == ~t12_pc~0; 24127#L795 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 24107#L805 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 23962#is_transmit12_triggered_returnLabel#1 activate_threads_#t~ret30#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 23963#L1551 assume !(0 != activate_threads_~tmp___11~0#1); 24251#L1551-2 havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 24719#L1307 assume !(1 == ~M_E~0); 24720#L1307-2 assume !(1 == ~T1_E~0); 24828#L1312-1 assume !(1 == ~T2_E~0); 24748#L1317-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 24749#L1322-1 assume !(1 == ~T4_E~0); 24459#L1327-1 assume !(1 == ~T5_E~0); 24460#L1332-1 assume !(1 == ~T6_E~0); 25005#L1337-1 assume !(1 == ~T7_E~0); 24962#L1342-1 assume !(1 == ~T8_E~0); 24963#L1347-1 assume !(1 == ~T9_E~0); 25375#L1352-1 assume !(1 == ~T10_E~0); 25234#L1357-1 assume 1 == ~T11_E~0;~T11_E~0 := 2; 24624#L1362-1 assume !(1 == ~T12_E~0); 24625#L1367-1 assume !(1 == ~E_1~0); 24266#L1372-1 assume !(1 == ~E_2~0); 24267#L1377-1 assume !(1 == ~E_3~0); 24557#L1382-1 assume !(1 == ~E_4~0); 24558#L1387-1 assume !(1 == ~E_5~0); 25108#L1392-1 assume !(1 == ~E_6~0); 24575#L1397-1 assume 1 == ~E_7~0;~E_7~0 := 2; 24576#L1402-1 assume !(1 == ~E_8~0); 24281#L1407-1 assume !(1 == ~E_9~0); 24282#L1412-1 assume !(1 == ~E_10~0); 25300#L1417-1 assume !(1 == ~E_11~0); 25301#L1422-1 assume !(1 == ~E_12~0); 25535#L1427-1 assume { :end_inline_reset_delta_events } true; 24088#L1768-2 [2023-11-12 02:13:42,906 INFO L750 eck$LassoCheckResult]: Loop: 24088#L1768-2 assume !false; 24089#L1769 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 24752#L1149-1 assume !false; 25130#L972 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 25357#L894 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 24466#L961 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 25282#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 25352#L976 assume !(0 != eval_~tmp~0#1); 24780#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 24509#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 24510#L1174-3 assume 0 == ~M_E~0;~M_E~0 := 1; 25310#L1174-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 25048#L1179-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 25049#L1184-3 assume !(0 == ~T3_E~0); 25235#L1189-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 24879#L1194-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 24242#L1199-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 24243#L1204-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 24479#L1209-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 23902#L1214-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 23903#L1219-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 24659#L1224-3 assume !(0 == ~T11_E~0); 24660#L1229-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 24674#L1234-3 assume 0 == ~E_1~0;~E_1~0 := 1; 24098#L1239-3 assume 0 == ~E_2~0;~E_2~0 := 1; 24099#L1244-3 assume 0 == ~E_3~0;~E_3~0 := 1; 24534#L1249-3 assume 0 == ~E_4~0;~E_4~0 := 1; 24992#L1254-3 assume 0 == ~E_5~0;~E_5~0 := 1; 25485#L1259-3 assume 0 == ~E_6~0;~E_6~0 := 1; 25091#L1264-3 assume !(0 == ~E_7~0); 24102#L1269-3 assume 0 == ~E_8~0;~E_8~0 := 1; 24103#L1274-3 assume 0 == ~E_9~0;~E_9~0 := 1; 25515#L1279-3 assume 0 == ~E_10~0;~E_10~0 := 1; 24655#L1284-3 assume 0 == ~E_11~0;~E_11~0 := 1; 24656#L1289-3 assume 0 == ~E_12~0;~E_12~0 := 1; 24643#L1294-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 24322#L566-39 assume 1 == ~m_pc~0; 24323#L567-13 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 24922#L577-13 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 24923#is_master_triggered_returnLabel#14 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 24975#L1455-39 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 25166#L1455-41 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 25167#L585-39 assume 1 == ~t1_pc~0; 25296#L586-13 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 24331#L596-13 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 24531#is_transmit1_triggered_returnLabel#14 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 25479#L1463-39 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 25204#L1463-41 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 24899#L604-39 assume 1 == ~t2_pc~0; 24900#L605-13 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 24538#L615-13 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 24539#is_transmit2_triggered_returnLabel#14 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 24718#L1471-39 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 24952#L1471-41 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 24520#L623-39 assume !(1 == ~t3_pc~0); 23921#L623-41 is_transmit3_triggered_~__retres1~3#1 := 0; 23920#L634-13 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 25184#is_transmit3_triggered_returnLabel#14 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 24373#L1479-39 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 24374#L1479-41 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 25126#L642-39 assume 1 == ~t4_pc~0; 24709#L643-13 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 24710#L653-13 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 24874#is_transmit4_triggered_returnLabel#14 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 24875#L1487-39 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 25356#L1487-41 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 24292#L661-39 assume 1 == ~t5_pc~0; 24293#L662-13 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 23928#L672-13 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 24906#is_transmit5_triggered_returnLabel#14 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 24907#L1495-39 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 25186#L1495-41 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 25187#L680-39 assume 1 == ~t6_pc~0; 23994#L681-13 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 23995#L691-13 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 25435#is_transmit6_triggered_returnLabel#14 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 24446#L1503-39 assume !(0 != activate_threads_~tmp___5~0#1); 24447#L1503-41 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 25491#L699-39 assume 1 == ~t7_pc~0; 24881#L700-13 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 24608#L710-13 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 24609#is_transmit7_triggered_returnLabel#14 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 25191#L1511-39 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 25431#L1511-41 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 25428#L718-39 assume 1 == ~t8_pc~0; 24793#L719-13 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 24794#L729-13 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 25287#is_transmit8_triggered_returnLabel#14 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 25288#L1519-39 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 25036#L1519-41 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 25013#L737-39 assume 1 == ~t9_pc~0; 24427#L738-13 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 24428#L748-13 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 24022#is_transmit9_triggered_returnLabel#14 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 24023#L1527-39 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 25403#L1527-41 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 25340#L756-39 assume !(1 == ~t10_pc~0); 24807#L756-41 is_transmit10_triggered_~__retres1~10#1 := 0; 24808#L767-13 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 25478#is_transmit10_triggered_returnLabel#14 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 24692#L1535-39 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 24693#L1535-41 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 24043#L775-39 assume 1 == ~t11_pc~0; 24044#L776-13 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 24683#L786-13 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 24684#is_transmit11_triggered_returnLabel#14 activate_threads_#t~ret29#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 24933#L1543-39 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 25084#L1543-41 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 24734#L794-39 assume !(1 == ~t12_pc~0); 24423#L794-41 is_transmit12_triggered_~__retres1~12#1 := 0; 24424#L805-13 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 24517#is_transmit12_triggered_returnLabel#14 activate_threads_#t~ret30#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 24518#L1551-39 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 23985#L1551-41 havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 23986#L1307-3 assume 1 == ~M_E~0;~M_E~0 := 2; 25462#L1307-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 25463#L1312-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 25576#L1317-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 25153#L1322-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 25154#L1327-3 assume !(1 == ~T5_E~0); 24119#L1332-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 24094#L1337-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 24095#L1342-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 24822#L1347-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 24955#L1352-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 24956#L1357-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 25411#L1362-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 25571#L1367-3 assume !(1 == ~E_1~0); 25562#L1372-3 assume 1 == ~E_2~0;~E_2~0 := 2; 23915#L1377-3 assume 1 == ~E_3~0;~E_3~0 := 2; 23916#L1382-3 assume 1 == ~E_4~0;~E_4~0 := 2; 24541#L1387-3 assume 1 == ~E_5~0;~E_5~0 := 2; 24542#L1392-3 assume 1 == ~E_6~0;~E_6~0 := 2; 25261#L1397-3 assume 1 == ~E_7~0;~E_7~0 := 2; 25529#L1402-3 assume 1 == ~E_8~0;~E_8~0 := 2; 24921#L1407-3 assume !(1 == ~E_9~0); 24201#L1412-3 assume 1 == ~E_10~0;~E_10~0 := 2; 24202#L1417-3 assume 1 == ~E_11~0;~E_11~0 := 2; 24836#L1422-3 assume 1 == ~E_12~0;~E_12~0 := 2; 24837#L1427-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 24209#L894-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 24210#L961-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 24277#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret32#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret32#1;havoc start_simulation_#t~ret32#1; 24278#L1787 assume !(0 == start_simulation_~tmp~3#1); 24925#L1787-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret31#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 25471#L894-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 24186#L961-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 23934#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret31#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret31#1;havoc stop_simulation_#t~ret31#1; 23935#L1742 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 24527#L1749 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 24528#stop_simulation_returnLabel#1 start_simulation_#t~ret33#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret31#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret33#1;havoc start_simulation_#t~ret33#1; 25438#L1800 assume !(0 != start_simulation_~tmp___0~1#1); 24088#L1768-2 [2023-11-12 02:13:42,908 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-12 02:13:42,908 INFO L85 PathProgramCache]: Analyzing trace with hash -1846000687, now seen corresponding path program 1 times [2023-11-12 02:13:42,908 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-12 02:13:42,908 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [369222499] [2023-11-12 02:13:42,908 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-12 02:13:42,908 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-12 02:13:42,928 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-12 02:13:42,969 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-12 02:13:42,969 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-12 02:13:42,971 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [369222499] [2023-11-12 02:13:42,971 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [369222499] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-12 02:13:42,971 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-12 02:13:42,971 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-12 02:13:42,971 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [904401578] [2023-11-12 02:13:42,972 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-12 02:13:42,972 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-12 02:13:42,976 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-12 02:13:42,976 INFO L85 PathProgramCache]: Analyzing trace with hash 1831355804, now seen corresponding path program 1 times [2023-11-12 02:13:42,977 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-12 02:13:42,979 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1122148093] [2023-11-12 02:13:42,979 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-12 02:13:42,979 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-12 02:13:43,001 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-12 02:13:43,072 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-12 02:13:43,072 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-12 02:13:43,072 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1122148093] [2023-11-12 02:13:43,075 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1122148093] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-12 02:13:43,075 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-12 02:13:43,075 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-12 02:13:43,075 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [596504163] [2023-11-12 02:13:43,075 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-12 02:13:43,076 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-12 02:13:43,076 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-12 02:13:43,077 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-12 02:13:43,077 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-12 02:13:43,077 INFO L87 Difference]: Start difference. First operand 1701 states and 2511 transitions. cyclomatic complexity: 811 Second operand has 3 states, 3 states have (on average 49.333333333333336) internal successors, (148), 3 states have internal predecessors, (148), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-12 02:13:43,126 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-12 02:13:43,126 INFO L93 Difference]: Finished difference Result 1701 states and 2510 transitions. [2023-11-12 02:13:43,126 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1701 states and 2510 transitions. [2023-11-12 02:13:43,138 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1540 [2023-11-12 02:13:43,152 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1701 states to 1701 states and 2510 transitions. [2023-11-12 02:13:43,152 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1701 [2023-11-12 02:13:43,154 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1701 [2023-11-12 02:13:43,155 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1701 states and 2510 transitions. [2023-11-12 02:13:43,157 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-12 02:13:43,157 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1701 states and 2510 transitions. [2023-11-12 02:13:43,161 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1701 states and 2510 transitions. [2023-11-12 02:13:43,188 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1701 to 1701. [2023-11-12 02:13:43,192 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1701 states, 1701 states have (on average 1.475602586713698) internal successors, (2510), 1700 states have internal predecessors, (2510), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-12 02:13:43,200 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1701 states to 1701 states and 2510 transitions. [2023-11-12 02:13:43,200 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1701 states and 2510 transitions. [2023-11-12 02:13:43,200 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-12 02:13:43,202 INFO L428 stractBuchiCegarLoop]: Abstraction has 1701 states and 2510 transitions. [2023-11-12 02:13:43,202 INFO L335 stractBuchiCegarLoop]: ======== Iteration 9 ============ [2023-11-12 02:13:43,202 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1701 states and 2510 transitions. [2023-11-12 02:13:43,210 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1540 [2023-11-12 02:13:43,210 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-12 02:13:43,210 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-12 02:13:43,213 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-12 02:13:43,213 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-12 02:13:43,213 INFO L748 eck$LassoCheckResult]: Stem: 27565#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2; 27566#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~14#1;havoc main_~__retres1~14#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1; 28358#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret32#1, start_simulation_#t~ret33#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 28359#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 28226#L821 assume 1 == ~m_i~0;~m_st~0 := 0; 28227#L821-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 28320#L826-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 28619#L831-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 28754#L836-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 28755#L841-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 27541#L846-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 27542#L851-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 28686#L856-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 28124#L861-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 28125#L866-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 28035#L871-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 28036#L876-1 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 28429#L881-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 27780#L1174 assume !(0 == ~M_E~0); 27781#L1174-2 assume 0 == ~T1_E~0;~T1_E~0 := 1; 27632#L1179-1 assume !(0 == ~T2_E~0); 27538#L1184-1 assume !(0 == ~T3_E~0); 27539#L1189-1 assume !(0 == ~T4_E~0); 27581#L1194-1 assume !(0 == ~T5_E~0); 27674#L1199-1 assume !(0 == ~T6_E~0); 28553#L1204-1 assume !(0 == ~T7_E~0); 28474#L1209-1 assume !(0 == ~T8_E~0); 28475#L1214-1 assume 0 == ~T9_E~0;~T9_E~0 := 1; 28898#L1219-1 assume !(0 == ~T10_E~0); 28983#L1224-1 assume !(0 == ~T11_E~0); 27897#L1229-1 assume !(0 == ~T12_E~0); 27468#L1234-1 assume !(0 == ~E_1~0); 27469#L1239-1 assume !(0 == ~E_2~0); 27501#L1244-1 assume !(0 == ~E_3~0); 27502#L1249-1 assume !(0 == ~E_4~0); 28144#L1254-1 assume 0 == ~E_5~0;~E_5~0 := 1; 27398#L1259-1 assume !(0 == ~E_6~0); 27351#L1264-1 assume !(0 == ~E_7~0); 27352#L1269-1 assume !(0 == ~E_8~0); 28986#L1274-1 assume !(0 == ~E_9~0); 28925#L1279-1 assume !(0 == ~E_10~0); 27585#L1284-1 assume !(0 == ~E_11~0); 27586#L1289-1 assume !(0 == ~E_12~0); 28196#L1294-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 28197#L566 assume 1 == ~m_pc~0; 27368#L567 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 27369#L577 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 28240#is_master_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 28241#L1455 assume !(0 != activate_threads_~tmp~1#1); 27807#L1455-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 27808#L585 assume 1 == ~t1_pc~0; 27465#L586 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 27466#L596 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 28609#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 28610#L1463 assume !(0 != activate_threads_~tmp___0~0#1); 28954#L1463-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 28950#L604 assume !(1 == ~t2_pc~0); 28515#L604-2 is_transmit2_triggered_~__retres1~2#1 := 0; 28516#L615 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 27750#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 27751#L1471 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 28714#L1471-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 28715#L623 assume 1 == ~t3_pc~0; 27981#L624 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 27327#L634 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 28584#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 28585#L1479 assume !(0 != activate_threads_~tmp___2~0#1); 28748#L1479-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 27365#L642 assume !(1 == ~t4_pc~0); 27366#L642-2 is_transmit4_triggered_~__retres1~4#1 := 0; 27818#L653 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 27420#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 27421#L1487 assume !(0 != activate_threads_~tmp___3~0#1); 27442#L1487-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 28528#L661 assume 1 == ~t5_pc~0; 27598#L662 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 27599#L672 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 28446#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 28813#L1495 assume !(0 != activate_threads_~tmp___4~0#1); 28560#L1495-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 28561#L680 assume !(1 == ~t6_pc~0); 28014#L680-2 is_transmit6_triggered_~__retres1~6#1 := 0; 28015#L691 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 27741#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 27742#L1503 assume !(0 != activate_threads_~tmp___5~0#1); 28823#L1503-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 28947#L699 assume 1 == ~t7_pc~0; 28409#L700 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 28410#L710 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 28642#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 28302#L1511 assume !(0 != activate_threads_~tmp___6~0#1); 28303#L1511-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 28198#L718 assume !(1 == ~t8_pc~0); 28199#L718-2 is_transmit8_triggered_~__retres1~8#1 := 0; 27579#L729 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 27580#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 27614#L1519 assume !(0 != activate_threads_~tmp___7~0#1); 27615#L1519-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 27747#L737 assume 1 == ~t9_pc~0; 28598#L738 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 27878#L748 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 27787#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 27788#L1527 assume !(0 != activate_threads_~tmp___8~0#1); 28055#L1527-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 28056#L756 assume 1 == ~t10_pc~0; 28632#L757 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 28293#L767 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 28548#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 28233#L1535 assume !(0 != activate_threads_~tmp___9~0#1); 27857#L1535-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 27858#L775 assume !(1 == ~t11_pc~0); 28116#L775-2 is_transmit11_triggered_~__retres1~11#1 := 0; 28117#L786 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 28891#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 27513#L1543 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 27514#L1543-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 27695#L794 assume 1 == ~t12_pc~0; 27536#L795 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 27516#L805 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 27371#is_transmit12_triggered_returnLabel#1 activate_threads_#t~ret30#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 27372#L1551 assume !(0 != activate_threads_~tmp___11~0#1); 27660#L1551-2 havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 28128#L1307 assume !(1 == ~M_E~0); 28129#L1307-2 assume !(1 == ~T1_E~0); 28237#L1312-1 assume !(1 == ~T2_E~0); 28157#L1317-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 28158#L1322-1 assume !(1 == ~T4_E~0); 27868#L1327-1 assume !(1 == ~T5_E~0); 27869#L1332-1 assume !(1 == ~T6_E~0); 28414#L1337-1 assume !(1 == ~T7_E~0); 28371#L1342-1 assume !(1 == ~T8_E~0); 28372#L1347-1 assume !(1 == ~T9_E~0); 28784#L1352-1 assume !(1 == ~T10_E~0); 28643#L1357-1 assume 1 == ~T11_E~0;~T11_E~0 := 2; 28033#L1362-1 assume !(1 == ~T12_E~0); 28034#L1367-1 assume !(1 == ~E_1~0); 27675#L1372-1 assume !(1 == ~E_2~0); 27676#L1377-1 assume !(1 == ~E_3~0); 27966#L1382-1 assume !(1 == ~E_4~0); 27967#L1387-1 assume !(1 == ~E_5~0); 28517#L1392-1 assume !(1 == ~E_6~0); 27984#L1397-1 assume 1 == ~E_7~0;~E_7~0 := 2; 27985#L1402-1 assume !(1 == ~E_8~0); 27690#L1407-1 assume !(1 == ~E_9~0); 27691#L1412-1 assume !(1 == ~E_10~0); 28709#L1417-1 assume !(1 == ~E_11~0); 28710#L1422-1 assume !(1 == ~E_12~0); 28944#L1427-1 assume { :end_inline_reset_delta_events } true; 27497#L1768-2 [2023-11-12 02:13:43,214 INFO L750 eck$LassoCheckResult]: Loop: 27497#L1768-2 assume !false; 27498#L1769 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 28161#L1149-1 assume !false; 28539#L972 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 28766#L894 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 27875#L961 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 28691#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 28761#L976 assume !(0 != eval_~tmp~0#1); 28189#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 27918#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 27919#L1174-3 assume 0 == ~M_E~0;~M_E~0 := 1; 28719#L1174-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 28457#L1179-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 28458#L1184-3 assume !(0 == ~T3_E~0); 28644#L1189-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 28288#L1194-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 27651#L1199-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 27652#L1204-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 27888#L1209-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 27311#L1214-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 27312#L1219-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 28068#L1224-3 assume !(0 == ~T11_E~0); 28069#L1229-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 28083#L1234-3 assume 0 == ~E_1~0;~E_1~0 := 1; 27507#L1239-3 assume 0 == ~E_2~0;~E_2~0 := 1; 27508#L1244-3 assume 0 == ~E_3~0;~E_3~0 := 1; 27943#L1249-3 assume 0 == ~E_4~0;~E_4~0 := 1; 28401#L1254-3 assume 0 == ~E_5~0;~E_5~0 := 1; 28894#L1259-3 assume 0 == ~E_6~0;~E_6~0 := 1; 28500#L1264-3 assume !(0 == ~E_7~0); 27511#L1269-3 assume 0 == ~E_8~0;~E_8~0 := 1; 27512#L1274-3 assume 0 == ~E_9~0;~E_9~0 := 1; 28924#L1279-3 assume 0 == ~E_10~0;~E_10~0 := 1; 28064#L1284-3 assume 0 == ~E_11~0;~E_11~0 := 1; 28065#L1289-3 assume 0 == ~E_12~0;~E_12~0 := 1; 28052#L1294-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 27731#L566-39 assume 1 == ~m_pc~0; 27732#L567-13 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 28331#L577-13 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 28332#is_master_triggered_returnLabel#14 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 28384#L1455-39 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 28575#L1455-41 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 28576#L585-39 assume 1 == ~t1_pc~0; 28705#L586-13 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 27740#L596-13 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 27940#is_transmit1_triggered_returnLabel#14 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 28888#L1463-39 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 28613#L1463-41 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 28308#L604-39 assume 1 == ~t2_pc~0; 28309#L605-13 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 27947#L615-13 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 27948#is_transmit2_triggered_returnLabel#14 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 28127#L1471-39 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 28361#L1471-41 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 27929#L623-39 assume 1 == ~t3_pc~0; 27328#L624-13 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 27329#L634-13 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 28593#is_transmit3_triggered_returnLabel#14 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 27782#L1479-39 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 27783#L1479-41 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 28535#L642-39 assume 1 == ~t4_pc~0; 28118#L643-13 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 28119#L653-13 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 28283#is_transmit4_triggered_returnLabel#14 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 28284#L1487-39 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 28765#L1487-41 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 27701#L661-39 assume 1 == ~t5_pc~0; 27702#L662-13 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 27337#L672-13 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 28315#is_transmit5_triggered_returnLabel#14 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 28316#L1495-39 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 28595#L1495-41 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 28596#L680-39 assume 1 == ~t6_pc~0; 27403#L681-13 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 27404#L691-13 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 28844#is_transmit6_triggered_returnLabel#14 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 27855#L1503-39 assume !(0 != activate_threads_~tmp___5~0#1); 27856#L1503-41 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 28900#L699-39 assume 1 == ~t7_pc~0; 28290#L700-13 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 28017#L710-13 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 28018#is_transmit7_triggered_returnLabel#14 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 28600#L1511-39 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 28840#L1511-41 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 28837#L718-39 assume 1 == ~t8_pc~0; 28202#L719-13 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 28203#L729-13 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 28696#is_transmit8_triggered_returnLabel#14 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 28697#L1519-39 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 28445#L1519-41 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 28422#L737-39 assume 1 == ~t9_pc~0; 27836#L738-13 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 27837#L748-13 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 27431#is_transmit9_triggered_returnLabel#14 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 27432#L1527-39 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 28812#L1527-41 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 28749#L756-39 assume !(1 == ~t10_pc~0); 28216#L756-41 is_transmit10_triggered_~__retres1~10#1 := 0; 28217#L767-13 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 28887#is_transmit10_triggered_returnLabel#14 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 28101#L1535-39 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 28102#L1535-41 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 27452#L775-39 assume 1 == ~t11_pc~0; 27453#L776-13 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 28092#L786-13 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 28093#is_transmit11_triggered_returnLabel#14 activate_threads_#t~ret29#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 28342#L1543-39 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 28493#L1543-41 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 28143#L794-39 assume !(1 == ~t12_pc~0); 27832#L794-41 is_transmit12_triggered_~__retres1~12#1 := 0; 27833#L805-13 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 27926#is_transmit12_triggered_returnLabel#14 activate_threads_#t~ret30#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 27927#L1551-39 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 27394#L1551-41 havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 27395#L1307-3 assume 1 == ~M_E~0;~M_E~0 := 2; 28871#L1307-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 28872#L1312-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 28985#L1317-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 28562#L1322-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 28563#L1327-3 assume !(1 == ~T5_E~0); 27528#L1332-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 27503#L1337-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 27504#L1342-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 28231#L1347-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 28364#L1352-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 28365#L1357-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 28820#L1362-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 28980#L1367-3 assume !(1 == ~E_1~0); 28971#L1372-3 assume 1 == ~E_2~0;~E_2~0 := 2; 27324#L1377-3 assume 1 == ~E_3~0;~E_3~0 := 2; 27325#L1382-3 assume 1 == ~E_4~0;~E_4~0 := 2; 27950#L1387-3 assume 1 == ~E_5~0;~E_5~0 := 2; 27951#L1392-3 assume 1 == ~E_6~0;~E_6~0 := 2; 28670#L1397-3 assume 1 == ~E_7~0;~E_7~0 := 2; 28938#L1402-3 assume 1 == ~E_8~0;~E_8~0 := 2; 28330#L1407-3 assume !(1 == ~E_9~0); 27610#L1412-3 assume 1 == ~E_10~0;~E_10~0 := 2; 27611#L1417-3 assume 1 == ~E_11~0;~E_11~0 := 2; 28245#L1422-3 assume 1 == ~E_12~0;~E_12~0 := 2; 28246#L1427-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 27618#L894-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 27619#L961-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 27686#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret32#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret32#1;havoc start_simulation_#t~ret32#1; 27687#L1787 assume !(0 == start_simulation_~tmp~3#1); 28334#L1787-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret31#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 28880#L894-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 27595#L961-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 27343#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret31#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret31#1;havoc stop_simulation_#t~ret31#1; 27344#L1742 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 27936#L1749 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 27937#stop_simulation_returnLabel#1 start_simulation_#t~ret33#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret31#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret33#1;havoc start_simulation_#t~ret33#1; 28847#L1800 assume !(0 != start_simulation_~tmp___0~1#1); 27497#L1768-2 [2023-11-12 02:13:43,215 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-12 02:13:43,215 INFO L85 PathProgramCache]: Analyzing trace with hash -1915648561, now seen corresponding path program 1 times [2023-11-12 02:13:43,216 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-12 02:13:43,216 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [594184219] [2023-11-12 02:13:43,216 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-12 02:13:43,216 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-12 02:13:43,232 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-12 02:13:43,267 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-12 02:13:43,267 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-12 02:13:43,268 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [594184219] [2023-11-12 02:13:43,268 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [594184219] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-12 02:13:43,268 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-12 02:13:43,268 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-12 02:13:43,268 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [779252036] [2023-11-12 02:13:43,268 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-12 02:13:43,269 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-12 02:13:43,269 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-12 02:13:43,269 INFO L85 PathProgramCache]: Analyzing trace with hash -594413379, now seen corresponding path program 1 times [2023-11-12 02:13:43,270 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-12 02:13:43,270 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1476311761] [2023-11-12 02:13:43,270 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-12 02:13:43,270 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-12 02:13:43,290 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-12 02:13:43,341 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-12 02:13:43,342 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-12 02:13:43,342 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1476311761] [2023-11-12 02:13:43,342 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1476311761] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-12 02:13:43,342 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-12 02:13:43,342 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-12 02:13:43,343 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [998923707] [2023-11-12 02:13:43,343 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-12 02:13:43,343 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-12 02:13:43,343 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-12 02:13:43,344 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-12 02:13:43,344 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-12 02:13:43,344 INFO L87 Difference]: Start difference. First operand 1701 states and 2510 transitions. cyclomatic complexity: 810 Second operand has 3 states, 3 states have (on average 49.333333333333336) internal successors, (148), 3 states have internal predecessors, (148), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-12 02:13:43,394 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-12 02:13:43,394 INFO L93 Difference]: Finished difference Result 1701 states and 2509 transitions. [2023-11-12 02:13:43,394 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1701 states and 2509 transitions. [2023-11-12 02:13:43,413 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1540 [2023-11-12 02:13:43,426 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1701 states to 1701 states and 2509 transitions. [2023-11-12 02:13:43,427 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1701 [2023-11-12 02:13:43,429 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1701 [2023-11-12 02:13:43,429 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1701 states and 2509 transitions. [2023-11-12 02:13:43,431 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-12 02:13:43,432 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1701 states and 2509 transitions. [2023-11-12 02:13:43,435 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1701 states and 2509 transitions. [2023-11-12 02:13:43,461 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1701 to 1701. [2023-11-12 02:13:43,465 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1701 states, 1701 states have (on average 1.4750146972369194) internal successors, (2509), 1700 states have internal predecessors, (2509), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-12 02:13:43,471 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1701 states to 1701 states and 2509 transitions. [2023-11-12 02:13:43,471 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1701 states and 2509 transitions. [2023-11-12 02:13:43,471 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-12 02:13:43,473 INFO L428 stractBuchiCegarLoop]: Abstraction has 1701 states and 2509 transitions. [2023-11-12 02:13:43,473 INFO L335 stractBuchiCegarLoop]: ======== Iteration 10 ============ [2023-11-12 02:13:43,473 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1701 states and 2509 transitions. [2023-11-12 02:13:43,480 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1540 [2023-11-12 02:13:43,480 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-12 02:13:43,481 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-12 02:13:43,483 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-12 02:13:43,483 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-12 02:13:43,484 INFO L748 eck$LassoCheckResult]: Stem: 30974#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2; 30975#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~14#1;havoc main_~__retres1~14#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1; 31767#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret32#1, start_simulation_#t~ret33#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 31768#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 31635#L821 assume 1 == ~m_i~0;~m_st~0 := 0; 31636#L821-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 31729#L826-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 32028#L831-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 32163#L836-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 32164#L841-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 30950#L846-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 30951#L851-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 32095#L856-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 31533#L861-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 31534#L866-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 31444#L871-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 31445#L876-1 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 31838#L881-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 31189#L1174 assume !(0 == ~M_E~0); 31190#L1174-2 assume 0 == ~T1_E~0;~T1_E~0 := 1; 31041#L1179-1 assume !(0 == ~T2_E~0); 30947#L1184-1 assume !(0 == ~T3_E~0); 30948#L1189-1 assume !(0 == ~T4_E~0); 30990#L1194-1 assume !(0 == ~T5_E~0); 31083#L1199-1 assume !(0 == ~T6_E~0); 31962#L1204-1 assume !(0 == ~T7_E~0); 31883#L1209-1 assume !(0 == ~T8_E~0); 31884#L1214-1 assume 0 == ~T9_E~0;~T9_E~0 := 1; 32307#L1219-1 assume !(0 == ~T10_E~0); 32392#L1224-1 assume !(0 == ~T11_E~0); 31306#L1229-1 assume !(0 == ~T12_E~0); 30877#L1234-1 assume !(0 == ~E_1~0); 30878#L1239-1 assume !(0 == ~E_2~0); 30910#L1244-1 assume !(0 == ~E_3~0); 30911#L1249-1 assume !(0 == ~E_4~0); 31553#L1254-1 assume 0 == ~E_5~0;~E_5~0 := 1; 30807#L1259-1 assume !(0 == ~E_6~0); 30760#L1264-1 assume !(0 == ~E_7~0); 30761#L1269-1 assume !(0 == ~E_8~0); 32395#L1274-1 assume !(0 == ~E_9~0); 32334#L1279-1 assume !(0 == ~E_10~0); 30994#L1284-1 assume !(0 == ~E_11~0); 30995#L1289-1 assume !(0 == ~E_12~0); 31605#L1294-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 31606#L566 assume 1 == ~m_pc~0; 30777#L567 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 30778#L577 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 31649#is_master_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 31650#L1455 assume !(0 != activate_threads_~tmp~1#1); 31216#L1455-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 31217#L585 assume 1 == ~t1_pc~0; 30874#L586 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 30875#L596 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 32018#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 32019#L1463 assume !(0 != activate_threads_~tmp___0~0#1); 32363#L1463-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 32359#L604 assume !(1 == ~t2_pc~0); 31924#L604-2 is_transmit2_triggered_~__retres1~2#1 := 0; 31925#L615 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 31159#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 31160#L1471 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 32123#L1471-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 32124#L623 assume 1 == ~t3_pc~0; 31390#L624 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 30736#L634 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 31993#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 31994#L1479 assume !(0 != activate_threads_~tmp___2~0#1); 32157#L1479-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 30774#L642 assume !(1 == ~t4_pc~0); 30775#L642-2 is_transmit4_triggered_~__retres1~4#1 := 0; 31227#L653 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 30829#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 30830#L1487 assume !(0 != activate_threads_~tmp___3~0#1); 30851#L1487-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 31937#L661 assume 1 == ~t5_pc~0; 31007#L662 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 31008#L672 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 31855#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 32222#L1495 assume !(0 != activate_threads_~tmp___4~0#1); 31969#L1495-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 31970#L680 assume !(1 == ~t6_pc~0); 31423#L680-2 is_transmit6_triggered_~__retres1~6#1 := 0; 31424#L691 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 31150#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 31151#L1503 assume !(0 != activate_threads_~tmp___5~0#1); 32232#L1503-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 32356#L699 assume 1 == ~t7_pc~0; 31818#L700 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 31819#L710 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 32051#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 31711#L1511 assume !(0 != activate_threads_~tmp___6~0#1); 31712#L1511-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 31607#L718 assume !(1 == ~t8_pc~0); 31608#L718-2 is_transmit8_triggered_~__retres1~8#1 := 0; 30988#L729 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 30989#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 31023#L1519 assume !(0 != activate_threads_~tmp___7~0#1); 31024#L1519-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 31156#L737 assume 1 == ~t9_pc~0; 32007#L738 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 31287#L748 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 31196#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 31197#L1527 assume !(0 != activate_threads_~tmp___8~0#1); 31464#L1527-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 31465#L756 assume 1 == ~t10_pc~0; 32041#L757 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 31702#L767 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 31957#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 31642#L1535 assume !(0 != activate_threads_~tmp___9~0#1); 31266#L1535-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 31267#L775 assume !(1 == ~t11_pc~0); 31525#L775-2 is_transmit11_triggered_~__retres1~11#1 := 0; 31526#L786 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 32300#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 30922#L1543 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 30923#L1543-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 31104#L794 assume 1 == ~t12_pc~0; 30945#L795 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 30925#L805 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 30780#is_transmit12_triggered_returnLabel#1 activate_threads_#t~ret30#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 30781#L1551 assume !(0 != activate_threads_~tmp___11~0#1); 31069#L1551-2 havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 31537#L1307 assume !(1 == ~M_E~0); 31538#L1307-2 assume !(1 == ~T1_E~0); 31646#L1312-1 assume !(1 == ~T2_E~0); 31566#L1317-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 31567#L1322-1 assume !(1 == ~T4_E~0); 31277#L1327-1 assume !(1 == ~T5_E~0); 31278#L1332-1 assume !(1 == ~T6_E~0); 31823#L1337-1 assume !(1 == ~T7_E~0); 31780#L1342-1 assume !(1 == ~T8_E~0); 31781#L1347-1 assume !(1 == ~T9_E~0); 32193#L1352-1 assume !(1 == ~T10_E~0); 32052#L1357-1 assume 1 == ~T11_E~0;~T11_E~0 := 2; 31442#L1362-1 assume !(1 == ~T12_E~0); 31443#L1367-1 assume !(1 == ~E_1~0); 31084#L1372-1 assume !(1 == ~E_2~0); 31085#L1377-1 assume !(1 == ~E_3~0); 31375#L1382-1 assume !(1 == ~E_4~0); 31376#L1387-1 assume !(1 == ~E_5~0); 31926#L1392-1 assume !(1 == ~E_6~0); 31393#L1397-1 assume 1 == ~E_7~0;~E_7~0 := 2; 31394#L1402-1 assume !(1 == ~E_8~0); 31099#L1407-1 assume !(1 == ~E_9~0); 31100#L1412-1 assume !(1 == ~E_10~0); 32118#L1417-1 assume !(1 == ~E_11~0); 32119#L1422-1 assume !(1 == ~E_12~0); 32353#L1427-1 assume { :end_inline_reset_delta_events } true; 30906#L1768-2 [2023-11-12 02:13:43,485 INFO L750 eck$LassoCheckResult]: Loop: 30906#L1768-2 assume !false; 30907#L1769 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 31570#L1149-1 assume !false; 31948#L972 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 32175#L894 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 31284#L961 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 32100#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 32170#L976 assume !(0 != eval_~tmp~0#1); 31598#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 31327#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 31328#L1174-3 assume 0 == ~M_E~0;~M_E~0 := 1; 32128#L1174-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 31866#L1179-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 31867#L1184-3 assume !(0 == ~T3_E~0); 32053#L1189-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 31697#L1194-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 31060#L1199-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 31061#L1204-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 31297#L1209-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 30720#L1214-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 30721#L1219-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 31477#L1224-3 assume !(0 == ~T11_E~0); 31478#L1229-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 31492#L1234-3 assume 0 == ~E_1~0;~E_1~0 := 1; 30916#L1239-3 assume 0 == ~E_2~0;~E_2~0 := 1; 30917#L1244-3 assume 0 == ~E_3~0;~E_3~0 := 1; 31352#L1249-3 assume 0 == ~E_4~0;~E_4~0 := 1; 31810#L1254-3 assume 0 == ~E_5~0;~E_5~0 := 1; 32303#L1259-3 assume 0 == ~E_6~0;~E_6~0 := 1; 31909#L1264-3 assume !(0 == ~E_7~0); 30920#L1269-3 assume 0 == ~E_8~0;~E_8~0 := 1; 30921#L1274-3 assume 0 == ~E_9~0;~E_9~0 := 1; 32333#L1279-3 assume 0 == ~E_10~0;~E_10~0 := 1; 31473#L1284-3 assume 0 == ~E_11~0;~E_11~0 := 1; 31474#L1289-3 assume 0 == ~E_12~0;~E_12~0 := 1; 31461#L1294-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 31140#L566-39 assume 1 == ~m_pc~0; 31141#L567-13 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 31740#L577-13 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 31741#is_master_triggered_returnLabel#14 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 31793#L1455-39 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 31984#L1455-41 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 31985#L585-39 assume 1 == ~t1_pc~0; 32114#L586-13 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 31149#L596-13 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 31349#is_transmit1_triggered_returnLabel#14 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 32297#L1463-39 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 32022#L1463-41 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 31717#L604-39 assume 1 == ~t2_pc~0; 31718#L605-13 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 31356#L615-13 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 31357#is_transmit2_triggered_returnLabel#14 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 31536#L1471-39 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 31770#L1471-41 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 31338#L623-39 assume 1 == ~t3_pc~0; 30737#L624-13 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 30738#L634-13 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 32002#is_transmit3_triggered_returnLabel#14 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 31191#L1479-39 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 31192#L1479-41 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 31944#L642-39 assume 1 == ~t4_pc~0; 31527#L643-13 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 31528#L653-13 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 31692#is_transmit4_triggered_returnLabel#14 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 31693#L1487-39 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 32174#L1487-41 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 31110#L661-39 assume 1 == ~t5_pc~0; 31111#L662-13 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 30746#L672-13 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 31724#is_transmit5_triggered_returnLabel#14 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 31725#L1495-39 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 32004#L1495-41 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 32005#L680-39 assume 1 == ~t6_pc~0; 30812#L681-13 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 30813#L691-13 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 32253#is_transmit6_triggered_returnLabel#14 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 31264#L1503-39 assume !(0 != activate_threads_~tmp___5~0#1); 31265#L1503-41 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 32309#L699-39 assume 1 == ~t7_pc~0; 31699#L700-13 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 31426#L710-13 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 31427#is_transmit7_triggered_returnLabel#14 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 32009#L1511-39 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 32249#L1511-41 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 32246#L718-39 assume 1 == ~t8_pc~0; 31611#L719-13 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 31612#L729-13 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 32105#is_transmit8_triggered_returnLabel#14 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 32106#L1519-39 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 31854#L1519-41 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 31831#L737-39 assume 1 == ~t9_pc~0; 31245#L738-13 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 31246#L748-13 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 30840#is_transmit9_triggered_returnLabel#14 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 30841#L1527-39 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 32221#L1527-41 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 32158#L756-39 assume !(1 == ~t10_pc~0); 31625#L756-41 is_transmit10_triggered_~__retres1~10#1 := 0; 31626#L767-13 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 32296#is_transmit10_triggered_returnLabel#14 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 31510#L1535-39 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 31511#L1535-41 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 30861#L775-39 assume 1 == ~t11_pc~0; 30862#L776-13 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 31501#L786-13 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 31502#is_transmit11_triggered_returnLabel#14 activate_threads_#t~ret29#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 31751#L1543-39 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 31902#L1543-41 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 31552#L794-39 assume 1 == ~t12_pc~0; 31248#L795-13 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 31242#L805-13 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 31335#is_transmit12_triggered_returnLabel#14 activate_threads_#t~ret30#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 31336#L1551-39 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 30803#L1551-41 havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 30804#L1307-3 assume 1 == ~M_E~0;~M_E~0 := 2; 32280#L1307-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 32281#L1312-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 32394#L1317-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 31971#L1322-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 31972#L1327-3 assume !(1 == ~T5_E~0); 30937#L1332-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 30912#L1337-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 30913#L1342-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 31640#L1347-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 31773#L1352-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 31774#L1357-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 32229#L1362-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 32389#L1367-3 assume !(1 == ~E_1~0); 32380#L1372-3 assume 1 == ~E_2~0;~E_2~0 := 2; 30733#L1377-3 assume 1 == ~E_3~0;~E_3~0 := 2; 30734#L1382-3 assume 1 == ~E_4~0;~E_4~0 := 2; 31359#L1387-3 assume 1 == ~E_5~0;~E_5~0 := 2; 31360#L1392-3 assume 1 == ~E_6~0;~E_6~0 := 2; 32079#L1397-3 assume 1 == ~E_7~0;~E_7~0 := 2; 32347#L1402-3 assume 1 == ~E_8~0;~E_8~0 := 2; 31739#L1407-3 assume !(1 == ~E_9~0); 31019#L1412-3 assume 1 == ~E_10~0;~E_10~0 := 2; 31020#L1417-3 assume 1 == ~E_11~0;~E_11~0 := 2; 31654#L1422-3 assume 1 == ~E_12~0;~E_12~0 := 2; 31655#L1427-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 31027#L894-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 31028#L961-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 31095#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret32#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret32#1;havoc start_simulation_#t~ret32#1; 31096#L1787 assume !(0 == start_simulation_~tmp~3#1); 31743#L1787-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret31#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 32289#L894-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 31004#L961-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 30752#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret31#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret31#1;havoc stop_simulation_#t~ret31#1; 30753#L1742 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 31345#L1749 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 31346#stop_simulation_returnLabel#1 start_simulation_#t~ret33#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret31#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret33#1;havoc start_simulation_#t~ret33#1; 32256#L1800 assume !(0 != start_simulation_~tmp___0~1#1); 30906#L1768-2 [2023-11-12 02:13:43,486 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-12 02:13:43,486 INFO L85 PathProgramCache]: Analyzing trace with hash 1961430033, now seen corresponding path program 1 times [2023-11-12 02:13:43,486 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-12 02:13:43,486 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1722506471] [2023-11-12 02:13:43,486 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-12 02:13:43,487 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-12 02:13:43,504 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-12 02:13:43,542 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-12 02:13:43,543 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-12 02:13:43,543 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1722506471] [2023-11-12 02:13:43,543 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1722506471] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-12 02:13:43,543 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-12 02:13:43,543 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-12 02:13:43,543 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1556201016] [2023-11-12 02:13:43,543 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-12 02:13:43,545 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-12 02:13:43,545 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-12 02:13:43,545 INFO L85 PathProgramCache]: Analyzing trace with hash 680689310, now seen corresponding path program 1 times [2023-11-12 02:13:43,545 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-12 02:13:43,546 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [901839922] [2023-11-12 02:13:43,546 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-12 02:13:43,546 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-12 02:13:43,564 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-12 02:13:43,657 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-12 02:13:43,657 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-12 02:13:43,657 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [901839922] [2023-11-12 02:13:43,657 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [901839922] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-12 02:13:43,658 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-12 02:13:43,658 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-12 02:13:43,658 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1494182358] [2023-11-12 02:13:43,658 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-12 02:13:43,659 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-12 02:13:43,659 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-12 02:13:43,659 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-12 02:13:43,659 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-12 02:13:43,660 INFO L87 Difference]: Start difference. First operand 1701 states and 2509 transitions. cyclomatic complexity: 809 Second operand has 3 states, 3 states have (on average 49.333333333333336) internal successors, (148), 3 states have internal predecessors, (148), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-12 02:13:43,712 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-12 02:13:43,712 INFO L93 Difference]: Finished difference Result 1701 states and 2508 transitions. [2023-11-12 02:13:43,712 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1701 states and 2508 transitions. [2023-11-12 02:13:43,725 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1540 [2023-11-12 02:13:43,739 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1701 states to 1701 states and 2508 transitions. [2023-11-12 02:13:43,739 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1701 [2023-11-12 02:13:43,741 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1701 [2023-11-12 02:13:43,741 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1701 states and 2508 transitions. [2023-11-12 02:13:43,744 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-12 02:13:43,745 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1701 states and 2508 transitions. [2023-11-12 02:13:43,749 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1701 states and 2508 transitions. [2023-11-12 02:13:43,782 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1701 to 1701. [2023-11-12 02:13:43,786 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1701 states, 1701 states have (on average 1.474426807760141) internal successors, (2508), 1700 states have internal predecessors, (2508), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-12 02:13:43,793 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1701 states to 1701 states and 2508 transitions. [2023-11-12 02:13:43,794 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1701 states and 2508 transitions. [2023-11-12 02:13:43,794 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-12 02:13:43,795 INFO L428 stractBuchiCegarLoop]: Abstraction has 1701 states and 2508 transitions. [2023-11-12 02:13:43,795 INFO L335 stractBuchiCegarLoop]: ======== Iteration 11 ============ [2023-11-12 02:13:43,795 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1701 states and 2508 transitions. [2023-11-12 02:13:43,805 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1540 [2023-11-12 02:13:43,805 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-12 02:13:43,805 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-12 02:13:43,808 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-12 02:13:43,809 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-12 02:13:43,809 INFO L748 eck$LassoCheckResult]: Stem: 34383#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2; 34384#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~14#1;havoc main_~__retres1~14#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1; 35177#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret32#1, start_simulation_#t~ret33#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 35178#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 35044#L821 assume 1 == ~m_i~0;~m_st~0 := 0; 35045#L821-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 35138#L826-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 35442#L831-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 35572#L836-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 35573#L841-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 34359#L846-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 34360#L851-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 35504#L856-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 34942#L861-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 34943#L866-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 34855#L871-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 34856#L876-1 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 35247#L881-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 34598#L1174 assume !(0 == ~M_E~0); 34599#L1174-2 assume 0 == ~T1_E~0;~T1_E~0 := 1; 34452#L1179-1 assume !(0 == ~T2_E~0); 34356#L1184-1 assume !(0 == ~T3_E~0); 34357#L1189-1 assume !(0 == ~T4_E~0); 34399#L1194-1 assume !(0 == ~T5_E~0); 34494#L1199-1 assume !(0 == ~T6_E~0); 35371#L1204-1 assume !(0 == ~T7_E~0); 35292#L1209-1 assume !(0 == ~T8_E~0); 35293#L1214-1 assume 0 == ~T9_E~0;~T9_E~0 := 1; 35716#L1219-1 assume !(0 == ~T10_E~0); 35801#L1224-1 assume !(0 == ~T11_E~0); 34717#L1229-1 assume !(0 == ~T12_E~0); 34286#L1234-1 assume !(0 == ~E_1~0); 34287#L1239-1 assume !(0 == ~E_2~0); 34321#L1244-1 assume !(0 == ~E_3~0); 34322#L1249-1 assume !(0 == ~E_4~0); 34962#L1254-1 assume 0 == ~E_5~0;~E_5~0 := 1; 34216#L1259-1 assume !(0 == ~E_6~0); 34169#L1264-1 assume !(0 == ~E_7~0); 34170#L1269-1 assume !(0 == ~E_8~0); 35804#L1274-1 assume !(0 == ~E_9~0); 35744#L1279-1 assume !(0 == ~E_10~0); 34403#L1284-1 assume !(0 == ~E_11~0); 34404#L1289-1 assume !(0 == ~E_12~0); 35014#L1294-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 35015#L566 assume 1 == ~m_pc~0; 34186#L567 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 34187#L577 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 35058#is_master_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 35059#L1455 assume !(0 != activate_threads_~tmp~1#1); 34625#L1455-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 34626#L585 assume 1 == ~t1_pc~0; 34283#L586 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 34284#L596 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 35427#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 35428#L1463 assume !(0 != activate_threads_~tmp___0~0#1); 35772#L1463-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 35768#L604 assume !(1 == ~t2_pc~0); 35333#L604-2 is_transmit2_triggered_~__retres1~2#1 := 0; 35334#L615 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 34573#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 34574#L1471 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 35534#L1471-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 35535#L623 assume 1 == ~t3_pc~0; 34799#L624 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 34145#L634 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 35405#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 35406#L1479 assume !(0 != activate_threads_~tmp___2~0#1); 35566#L1479-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 34183#L642 assume !(1 == ~t4_pc~0); 34184#L642-2 is_transmit4_triggered_~__retres1~4#1 := 0; 34636#L653 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 34244#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 34245#L1487 assume !(0 != activate_threads_~tmp___3~0#1); 34260#L1487-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 35346#L661 assume 1 == ~t5_pc~0; 34416#L662 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 34417#L672 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 35264#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 35631#L1495 assume !(0 != activate_threads_~tmp___4~0#1); 35380#L1495-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 35381#L680 assume !(1 == ~t6_pc~0); 34832#L680-2 is_transmit6_triggered_~__retres1~6#1 := 0; 34833#L691 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 34562#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 34563#L1503 assume !(0 != activate_threads_~tmp___5~0#1); 35641#L1503-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 35766#L699 assume 1 == ~t7_pc~0; 35227#L700 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 35228#L710 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 35460#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 35120#L1511 assume !(0 != activate_threads_~tmp___6~0#1); 35121#L1511-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 35016#L718 assume !(1 == ~t8_pc~0); 35017#L718-2 is_transmit8_triggered_~__retres1~8#1 := 0; 34397#L729 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 34398#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 34434#L1519 assume !(0 != activate_threads_~tmp___7~0#1); 34435#L1519-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 34565#L737 assume 1 == ~t9_pc~0; 35418#L738 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 34698#L748 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 34605#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 34606#L1527 assume !(0 != activate_threads_~tmp___8~0#1); 34873#L1527-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 34874#L756 assume 1 == ~t10_pc~0; 35450#L757 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 35112#L767 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 35366#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 35051#L1535 assume !(0 != activate_threads_~tmp___9~0#1); 34675#L1535-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 34676#L775 assume !(1 == ~t11_pc~0); 34934#L775-2 is_transmit11_triggered_~__retres1~11#1 := 0; 34935#L786 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 35709#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 34331#L1543 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 34332#L1543-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 34513#L794 assume 1 == ~t12_pc~0; 34355#L795 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 34334#L805 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 34191#is_transmit12_triggered_returnLabel#1 activate_threads_#t~ret30#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 34192#L1551 assume !(0 != activate_threads_~tmp___11~0#1); 34480#L1551-2 havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 34946#L1307 assume !(1 == ~M_E~0); 34947#L1307-2 assume !(1 == ~T1_E~0); 35055#L1312-1 assume !(1 == ~T2_E~0); 34975#L1317-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 34976#L1322-1 assume !(1 == ~T4_E~0); 34686#L1327-1 assume !(1 == ~T5_E~0); 34687#L1332-1 assume !(1 == ~T6_E~0); 35232#L1337-1 assume !(1 == ~T7_E~0); 35190#L1342-1 assume !(1 == ~T8_E~0); 35191#L1347-1 assume !(1 == ~T9_E~0); 35602#L1352-1 assume !(1 == ~T10_E~0); 35461#L1357-1 assume 1 == ~T11_E~0;~T11_E~0 := 2; 34851#L1362-1 assume !(1 == ~T12_E~0); 34852#L1367-1 assume !(1 == ~E_1~0); 34495#L1372-1 assume !(1 == ~E_2~0); 34496#L1377-1 assume !(1 == ~E_3~0); 34784#L1382-1 assume !(1 == ~E_4~0); 34785#L1387-1 assume !(1 == ~E_5~0); 35335#L1392-1 assume !(1 == ~E_6~0); 34804#L1397-1 assume 1 == ~E_7~0;~E_7~0 := 2; 34805#L1402-1 assume !(1 == ~E_8~0); 34511#L1407-1 assume !(1 == ~E_9~0); 34512#L1412-1 assume !(1 == ~E_10~0); 35527#L1417-1 assume !(1 == ~E_11~0); 35528#L1422-1 assume !(1 == ~E_12~0); 35762#L1427-1 assume { :end_inline_reset_delta_events } true; 34315#L1768-2 [2023-11-12 02:13:43,810 INFO L750 eck$LassoCheckResult]: Loop: 34315#L1768-2 assume !false; 34316#L1769 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 34979#L1149-1 assume !false; 35359#L972 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 35584#L894 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 34693#L961 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 35509#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 35579#L976 assume !(0 != eval_~tmp~0#1); 35007#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 34736#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 34737#L1174-3 assume 0 == ~M_E~0;~M_E~0 := 1; 35537#L1174-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 35275#L1179-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 35276#L1184-3 assume !(0 == ~T3_E~0); 35463#L1189-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 35106#L1194-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 34472#L1199-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 34473#L1204-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 34706#L1209-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 34129#L1214-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 34130#L1219-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 34886#L1224-3 assume !(0 == ~T11_E~0); 34887#L1229-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 34901#L1234-3 assume 0 == ~E_1~0;~E_1~0 := 1; 34323#L1239-3 assume 0 == ~E_2~0;~E_2~0 := 1; 34324#L1244-3 assume 0 == ~E_3~0;~E_3~0 := 1; 34761#L1249-3 assume 0 == ~E_4~0;~E_4~0 := 1; 35219#L1254-3 assume 0 == ~E_5~0;~E_5~0 := 1; 35712#L1259-3 assume 0 == ~E_6~0;~E_6~0 := 1; 35318#L1264-3 assume !(0 == ~E_7~0); 34329#L1269-3 assume 0 == ~E_8~0;~E_8~0 := 1; 34330#L1274-3 assume 0 == ~E_9~0;~E_9~0 := 1; 35742#L1279-3 assume 0 == ~E_10~0;~E_10~0 := 1; 34882#L1284-3 assume 0 == ~E_11~0;~E_11~0 := 1; 34883#L1289-3 assume 0 == ~E_12~0;~E_12~0 := 1; 34870#L1294-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 34546#L566-39 assume 1 == ~m_pc~0; 34547#L567-13 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 35149#L577-13 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 35150#is_master_triggered_returnLabel#14 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 35202#L1455-39 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 35393#L1455-41 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 35394#L585-39 assume 1 == ~t1_pc~0; 35523#L586-13 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 34558#L596-13 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 34758#is_transmit1_triggered_returnLabel#14 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 35706#L1463-39 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 35431#L1463-41 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 35126#L604-39 assume 1 == ~t2_pc~0; 35127#L605-13 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 34765#L615-13 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 34766#is_transmit2_triggered_returnLabel#14 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 34945#L1471-39 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 35179#L1471-41 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 34747#L623-39 assume 1 == ~t3_pc~0; 34146#L624-13 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 34147#L634-13 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 35411#is_transmit3_triggered_returnLabel#14 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 34600#L1479-39 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 34601#L1479-41 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 35353#L642-39 assume 1 == ~t4_pc~0; 34936#L643-13 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 34937#L653-13 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 35101#is_transmit4_triggered_returnLabel#14 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 35102#L1487-39 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 35583#L1487-41 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 34519#L661-39 assume 1 == ~t5_pc~0; 34520#L662-13 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 34155#L672-13 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 35133#is_transmit5_triggered_returnLabel#14 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 35134#L1495-39 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 35413#L1495-41 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 35414#L680-39 assume 1 == ~t6_pc~0; 34221#L681-13 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 34222#L691-13 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 35662#is_transmit6_triggered_returnLabel#14 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 34673#L1503-39 assume !(0 != activate_threads_~tmp___5~0#1); 34674#L1503-41 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 35718#L699-39 assume 1 == ~t7_pc~0; 35108#L700-13 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 34835#L710-13 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 34836#is_transmit7_triggered_returnLabel#14 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 35417#L1511-39 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 35658#L1511-41 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 35655#L718-39 assume 1 == ~t8_pc~0; 35020#L719-13 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 35021#L729-13 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 35514#is_transmit8_triggered_returnLabel#14 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 35515#L1519-39 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 35263#L1519-41 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 35240#L737-39 assume !(1 == ~t9_pc~0); 34656#L737-41 is_transmit9_triggered_~__retres1~9#1 := 0; 34655#L748-13 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 34249#is_transmit9_triggered_returnLabel#14 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 34250#L1527-39 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 35630#L1527-41 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 35567#L756-39 assume 1 == ~t10_pc~0; 35568#L757-13 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 35035#L767-13 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 35705#is_transmit10_triggered_returnLabel#14 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 34919#L1535-39 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 34920#L1535-41 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 34270#L775-39 assume !(1 == ~t11_pc~0); 34272#L775-41 is_transmit11_triggered_~__retres1~11#1 := 0; 34910#L786-13 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 34911#is_transmit11_triggered_returnLabel#14 activate_threads_#t~ret29#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 35160#L1543-39 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 35311#L1543-41 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 34961#L794-39 assume 1 == ~t12_pc~0; 34657#L795-13 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 34651#L805-13 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 34744#is_transmit12_triggered_returnLabel#14 activate_threads_#t~ret30#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 34745#L1551-39 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 34212#L1551-41 havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 34213#L1307-3 assume 1 == ~M_E~0;~M_E~0 := 2; 35689#L1307-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 35690#L1312-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 35803#L1317-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 35378#L1322-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 35379#L1327-3 assume !(1 == ~T5_E~0); 34346#L1332-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 34319#L1337-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 34320#L1342-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 35049#L1347-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 35182#L1352-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 35183#L1357-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 35638#L1362-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 35798#L1367-3 assume !(1 == ~E_1~0); 35789#L1372-3 assume 1 == ~E_2~0;~E_2~0 := 2; 34139#L1377-3 assume 1 == ~E_3~0;~E_3~0 := 2; 34140#L1382-3 assume 1 == ~E_4~0;~E_4~0 := 2; 34768#L1387-3 assume 1 == ~E_5~0;~E_5~0 := 2; 34769#L1392-3 assume 1 == ~E_6~0;~E_6~0 := 2; 35488#L1397-3 assume 1 == ~E_7~0;~E_7~0 := 2; 35756#L1402-3 assume 1 == ~E_8~0;~E_8~0 := 2; 35148#L1407-3 assume !(1 == ~E_9~0); 34428#L1412-3 assume 1 == ~E_10~0;~E_10~0 := 2; 34429#L1417-3 assume 1 == ~E_11~0;~E_11~0 := 2; 35063#L1422-3 assume 1 == ~E_12~0;~E_12~0 := 2; 35064#L1427-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 34436#L894-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 34437#L961-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 34504#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret32#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret32#1;havoc start_simulation_#t~ret32#1; 34505#L1787 assume !(0 == start_simulation_~tmp~3#1); 35151#L1787-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret31#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 35698#L894-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 34413#L961-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 34158#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret31#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret31#1;havoc stop_simulation_#t~ret31#1; 34159#L1742 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 34754#L1749 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 34755#stop_simulation_returnLabel#1 start_simulation_#t~ret33#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret31#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret33#1;havoc start_simulation_#t~ret33#1; 35665#L1800 assume !(0 != start_simulation_~tmp___0~1#1); 34315#L1768-2 [2023-11-12 02:13:43,811 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-12 02:13:43,812 INFO L85 PathProgramCache]: Analyzing trace with hash -716096813, now seen corresponding path program 1 times [2023-11-12 02:13:43,812 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-12 02:13:43,812 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1421811081] [2023-11-12 02:13:43,812 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-12 02:13:43,812 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-12 02:13:43,835 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-12 02:13:43,882 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-12 02:13:43,882 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-12 02:13:43,882 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1421811081] [2023-11-12 02:13:43,882 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1421811081] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-12 02:13:43,882 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-12 02:13:43,883 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-12 02:13:43,883 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2115327691] [2023-11-12 02:13:43,883 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-12 02:13:43,883 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-12 02:13:43,884 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-12 02:13:43,884 INFO L85 PathProgramCache]: Analyzing trace with hash 762327613, now seen corresponding path program 1 times [2023-11-12 02:13:43,884 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-12 02:13:43,884 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1174273893] [2023-11-12 02:13:43,885 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-12 02:13:43,885 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-12 02:13:43,910 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-12 02:13:43,965 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-12 02:13:43,965 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-12 02:13:43,965 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1174273893] [2023-11-12 02:13:43,965 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1174273893] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-12 02:13:43,966 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-12 02:13:43,966 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-12 02:13:43,966 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1526620672] [2023-11-12 02:13:43,966 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-12 02:13:43,966 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-12 02:13:43,967 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-12 02:13:43,967 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-12 02:13:43,967 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-12 02:13:43,968 INFO L87 Difference]: Start difference. First operand 1701 states and 2508 transitions. cyclomatic complexity: 808 Second operand has 3 states, 3 states have (on average 49.333333333333336) internal successors, (148), 3 states have internal predecessors, (148), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-12 02:13:44,016 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-12 02:13:44,016 INFO L93 Difference]: Finished difference Result 1701 states and 2507 transitions. [2023-11-12 02:13:44,016 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1701 states and 2507 transitions. [2023-11-12 02:13:44,026 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1540 [2023-11-12 02:13:44,048 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1701 states to 1701 states and 2507 transitions. [2023-11-12 02:13:44,048 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1701 [2023-11-12 02:13:44,050 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1701 [2023-11-12 02:13:44,051 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1701 states and 2507 transitions. [2023-11-12 02:13:44,053 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-12 02:13:44,053 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1701 states and 2507 transitions. [2023-11-12 02:13:44,057 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1701 states and 2507 transitions. [2023-11-12 02:13:44,084 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1701 to 1701. [2023-11-12 02:13:44,097 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1701 states, 1701 states have (on average 1.4738389182833627) internal successors, (2507), 1700 states have internal predecessors, (2507), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-12 02:13:44,102 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1701 states to 1701 states and 2507 transitions. [2023-11-12 02:13:44,103 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1701 states and 2507 transitions. [2023-11-12 02:13:44,111 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-12 02:13:44,111 INFO L428 stractBuchiCegarLoop]: Abstraction has 1701 states and 2507 transitions. [2023-11-12 02:13:44,111 INFO L335 stractBuchiCegarLoop]: ======== Iteration 12 ============ [2023-11-12 02:13:44,112 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1701 states and 2507 transitions. [2023-11-12 02:13:44,118 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1540 [2023-11-12 02:13:44,119 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-12 02:13:44,119 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-12 02:13:44,121 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-12 02:13:44,121 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-12 02:13:44,122 INFO L748 eck$LassoCheckResult]: Stem: 37792#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2; 37793#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~14#1;havoc main_~__retres1~14#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1; 38585#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret32#1, start_simulation_#t~ret33#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 38586#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 38453#L821 assume 1 == ~m_i~0;~m_st~0 := 0; 38454#L821-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 38547#L826-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 38848#L831-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 38981#L836-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 38982#L841-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 37768#L846-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 37769#L851-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 38913#L856-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 38351#L861-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 38352#L866-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 38262#L871-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 38263#L876-1 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 38656#L881-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 38007#L1174 assume !(0 == ~M_E~0); 38008#L1174-2 assume 0 == ~T1_E~0;~T1_E~0 := 1; 37861#L1179-1 assume !(0 == ~T2_E~0); 37765#L1184-1 assume !(0 == ~T3_E~0); 37766#L1189-1 assume !(0 == ~T4_E~0); 37808#L1194-1 assume !(0 == ~T5_E~0); 37901#L1199-1 assume !(0 == ~T6_E~0); 38780#L1204-1 assume !(0 == ~T7_E~0); 38701#L1209-1 assume !(0 == ~T8_E~0); 38702#L1214-1 assume 0 == ~T9_E~0;~T9_E~0 := 1; 39125#L1219-1 assume !(0 == ~T10_E~0); 39210#L1224-1 assume !(0 == ~T11_E~0); 38124#L1229-1 assume !(0 == ~T12_E~0); 37695#L1234-1 assume !(0 == ~E_1~0); 37696#L1239-1 assume !(0 == ~E_2~0); 37730#L1244-1 assume !(0 == ~E_3~0); 37731#L1249-1 assume !(0 == ~E_4~0); 38371#L1254-1 assume 0 == ~E_5~0;~E_5~0 := 1; 37625#L1259-1 assume !(0 == ~E_6~0); 37578#L1264-1 assume !(0 == ~E_7~0); 37579#L1269-1 assume !(0 == ~E_8~0); 39213#L1274-1 assume !(0 == ~E_9~0); 39153#L1279-1 assume !(0 == ~E_10~0); 37812#L1284-1 assume !(0 == ~E_11~0); 37813#L1289-1 assume !(0 == ~E_12~0); 38423#L1294-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 38424#L566 assume 1 == ~m_pc~0; 37595#L567 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 37596#L577 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 38467#is_master_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 38468#L1455 assume !(0 != activate_threads_~tmp~1#1); 38034#L1455-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 38035#L585 assume 1 == ~t1_pc~0; 37692#L586 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 37693#L596 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 38836#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 38837#L1463 assume !(0 != activate_threads_~tmp___0~0#1); 39181#L1463-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 39177#L604 assume !(1 == ~t2_pc~0); 38742#L604-2 is_transmit2_triggered_~__retres1~2#1 := 0; 38743#L615 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 37982#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 37983#L1471 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 38943#L1471-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 38944#L623 assume 1 == ~t3_pc~0; 38208#L624 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 37554#L634 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 38814#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 38815#L1479 assume !(0 != activate_threads_~tmp___2~0#1); 38975#L1479-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 37592#L642 assume !(1 == ~t4_pc~0); 37593#L642-2 is_transmit4_triggered_~__retres1~4#1 := 0; 38045#L653 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 37650#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 37651#L1487 assume !(0 != activate_threads_~tmp___3~0#1); 37669#L1487-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 38755#L661 assume 1 == ~t5_pc~0; 37825#L662 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 37826#L672 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 38673#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 39040#L1495 assume !(0 != activate_threads_~tmp___4~0#1); 38789#L1495-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 38790#L680 assume !(1 == ~t6_pc~0); 38241#L680-2 is_transmit6_triggered_~__retres1~6#1 := 0; 38242#L691 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 37968#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 37969#L1503 assume !(0 != activate_threads_~tmp___5~0#1); 39050#L1503-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 39175#L699 assume 1 == ~t7_pc~0; 38636#L700 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 38637#L710 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 38869#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 38529#L1511 assume !(0 != activate_threads_~tmp___6~0#1); 38530#L1511-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 38425#L718 assume !(1 == ~t8_pc~0); 38426#L718-2 is_transmit8_triggered_~__retres1~8#1 := 0; 37806#L729 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 37807#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 37841#L1519 assume !(0 != activate_threads_~tmp___7~0#1); 37842#L1519-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 37974#L737 assume 1 == ~t9_pc~0; 38827#L738 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 38105#L748 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 38014#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 38015#L1527 assume !(0 != activate_threads_~tmp___8~0#1); 38282#L1527-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 38283#L756 assume 1 == ~t10_pc~0; 38859#L757 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 38520#L767 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 38775#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 38460#L1535 assume !(0 != activate_threads_~tmp___9~0#1); 38084#L1535-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 38085#L775 assume !(1 == ~t11_pc~0); 38343#L775-2 is_transmit11_triggered_~__retres1~11#1 := 0; 38344#L786 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 39118#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 37740#L1543 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 37741#L1543-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 37922#L794 assume 1 == ~t12_pc~0; 37764#L795 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 37743#L805 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 37600#is_transmit12_triggered_returnLabel#1 activate_threads_#t~ret30#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 37601#L1551 assume !(0 != activate_threads_~tmp___11~0#1); 37889#L1551-2 havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 38355#L1307 assume !(1 == ~M_E~0); 38356#L1307-2 assume !(1 == ~T1_E~0); 38464#L1312-1 assume !(1 == ~T2_E~0); 38384#L1317-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 38385#L1322-1 assume !(1 == ~T4_E~0); 38095#L1327-1 assume !(1 == ~T5_E~0); 38096#L1332-1 assume !(1 == ~T6_E~0); 38641#L1337-1 assume !(1 == ~T7_E~0); 38598#L1342-1 assume !(1 == ~T8_E~0); 38599#L1347-1 assume !(1 == ~T9_E~0); 39011#L1352-1 assume !(1 == ~T10_E~0); 38870#L1357-1 assume 1 == ~T11_E~0;~T11_E~0 := 2; 38260#L1362-1 assume !(1 == ~T12_E~0); 38261#L1367-1 assume !(1 == ~E_1~0); 37902#L1372-1 assume !(1 == ~E_2~0); 37903#L1377-1 assume !(1 == ~E_3~0); 38193#L1382-1 assume !(1 == ~E_4~0); 38194#L1387-1 assume !(1 == ~E_5~0); 38744#L1392-1 assume !(1 == ~E_6~0); 38213#L1397-1 assume 1 == ~E_7~0;~E_7~0 := 2; 38214#L1402-1 assume !(1 == ~E_8~0); 37917#L1407-1 assume !(1 == ~E_9~0); 37918#L1412-1 assume !(1 == ~E_10~0); 38936#L1417-1 assume !(1 == ~E_11~0); 38937#L1422-1 assume !(1 == ~E_12~0); 39171#L1427-1 assume { :end_inline_reset_delta_events } true; 37724#L1768-2 [2023-11-12 02:13:44,123 INFO L750 eck$LassoCheckResult]: Loop: 37724#L1768-2 assume !false; 37725#L1769 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 38388#L1149-1 assume !false; 38768#L972 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 38993#L894 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 38102#L961 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 38918#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 38988#L976 assume !(0 != eval_~tmp~0#1); 38416#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 38145#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 38146#L1174-3 assume 0 == ~M_E~0;~M_E~0 := 1; 38946#L1174-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 38684#L1179-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 38685#L1184-3 assume !(0 == ~T3_E~0); 38871#L1189-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 38515#L1194-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 37881#L1199-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 37882#L1204-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 38115#L1209-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 37538#L1214-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 37539#L1219-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 38295#L1224-3 assume !(0 == ~T11_E~0); 38296#L1229-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 38310#L1234-3 assume 0 == ~E_1~0;~E_1~0 := 1; 37734#L1239-3 assume 0 == ~E_2~0;~E_2~0 := 1; 37735#L1244-3 assume 0 == ~E_3~0;~E_3~0 := 1; 38170#L1249-3 assume 0 == ~E_4~0;~E_4~0 := 1; 38628#L1254-3 assume 0 == ~E_5~0;~E_5~0 := 1; 39121#L1259-3 assume 0 == ~E_6~0;~E_6~0 := 1; 38727#L1264-3 assume !(0 == ~E_7~0); 37738#L1269-3 assume 0 == ~E_8~0;~E_8~0 := 1; 37739#L1274-3 assume 0 == ~E_9~0;~E_9~0 := 1; 39151#L1279-3 assume 0 == ~E_10~0;~E_10~0 := 1; 38291#L1284-3 assume 0 == ~E_11~0;~E_11~0 := 1; 38292#L1289-3 assume 0 == ~E_12~0;~E_12~0 := 1; 38279#L1294-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 37958#L566-39 assume 1 == ~m_pc~0; 37959#L567-13 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 38558#L577-13 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 38559#is_master_triggered_returnLabel#14 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 38611#L1455-39 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 38802#L1455-41 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 38803#L585-39 assume 1 == ~t1_pc~0; 38932#L586-13 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 37967#L596-13 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 38167#is_transmit1_triggered_returnLabel#14 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 39115#L1463-39 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 38840#L1463-41 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 38535#L604-39 assume 1 == ~t2_pc~0; 38536#L605-13 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 38174#L615-13 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 38175#is_transmit2_triggered_returnLabel#14 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 38354#L1471-39 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 38592#L1471-41 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 38156#L623-39 assume 1 == ~t3_pc~0; 37557#L624-13 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 37558#L634-13 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 38820#is_transmit3_triggered_returnLabel#14 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 38009#L1479-39 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 38010#L1479-41 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 38762#L642-39 assume 1 == ~t4_pc~0; 38347#L643-13 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 38348#L653-13 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 38510#is_transmit4_triggered_returnLabel#14 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 38511#L1487-39 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 38992#L1487-41 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 37930#L661-39 assume !(1 == ~t5_pc~0); 37560#L661-41 is_transmit5_triggered_~__retres1~5#1 := 0; 37561#L672-13 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 38542#is_transmit5_triggered_returnLabel#14 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 38543#L1495-39 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 38822#L1495-41 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 38823#L680-39 assume !(1 == ~t6_pc~0); 37632#L680-41 is_transmit6_triggered_~__retres1~6#1 := 0; 37631#L691-13 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 39071#is_transmit6_triggered_returnLabel#14 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 38082#L1503-39 assume !(0 != activate_threads_~tmp___5~0#1); 38083#L1503-41 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 39127#L699-39 assume 1 == ~t7_pc~0; 38517#L700-13 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 38244#L710-13 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 38245#is_transmit7_triggered_returnLabel#14 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 38826#L1511-39 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 39065#L1511-41 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 39064#L718-39 assume 1 == ~t8_pc~0; 38429#L719-13 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 38430#L729-13 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 38922#is_transmit8_triggered_returnLabel#14 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 38923#L1519-39 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 38672#L1519-41 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 38649#L737-39 assume !(1 == ~t9_pc~0); 38065#L737-41 is_transmit9_triggered_~__retres1~9#1 := 0; 38064#L748-13 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 37657#is_transmit9_triggered_returnLabel#14 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 37658#L1527-39 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 39039#L1527-41 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 38976#L756-39 assume 1 == ~t10_pc~0; 38977#L757-13 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 38444#L767-13 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 39114#is_transmit10_triggered_returnLabel#14 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 38328#L1535-39 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 38329#L1535-41 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 37679#L775-39 assume 1 == ~t11_pc~0; 37680#L776-13 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 38319#L786-13 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 38320#is_transmit11_triggered_returnLabel#14 activate_threads_#t~ret29#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 38569#L1543-39 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 38720#L1543-41 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 38370#L794-39 assume 1 == ~t12_pc~0; 38066#L795-13 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 38060#L805-13 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 38151#is_transmit12_triggered_returnLabel#14 activate_threads_#t~ret30#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 38152#L1551-39 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 37621#L1551-41 havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 37622#L1307-3 assume 1 == ~M_E~0;~M_E~0 := 2; 39098#L1307-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 39099#L1312-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 39212#L1317-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 38787#L1322-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 38788#L1327-3 assume !(1 == ~T5_E~0); 37753#L1332-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 37728#L1337-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 37729#L1342-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 38458#L1347-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 38590#L1352-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 38591#L1357-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 39047#L1362-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 39207#L1367-3 assume !(1 == ~E_1~0); 39198#L1372-3 assume 1 == ~E_2~0;~E_2~0 := 2; 37548#L1377-3 assume 1 == ~E_3~0;~E_3~0 := 2; 37549#L1382-3 assume 1 == ~E_4~0;~E_4~0 := 2; 38177#L1387-3 assume 1 == ~E_5~0;~E_5~0 := 2; 38178#L1392-3 assume 1 == ~E_6~0;~E_6~0 := 2; 38897#L1397-3 assume 1 == ~E_7~0;~E_7~0 := 2; 39165#L1402-3 assume 1 == ~E_8~0;~E_8~0 := 2; 38557#L1407-3 assume !(1 == ~E_9~0); 37837#L1412-3 assume 1 == ~E_10~0;~E_10~0 := 2; 37838#L1417-3 assume 1 == ~E_11~0;~E_11~0 := 2; 38471#L1422-3 assume 1 == ~E_12~0;~E_12~0 := 2; 38472#L1427-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 37845#L894-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 37846#L961-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 37913#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret32#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret32#1;havoc start_simulation_#t~ret32#1; 37914#L1787 assume !(0 == start_simulation_~tmp~3#1); 38560#L1787-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret31#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 39107#L894-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 37822#L961-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 37567#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret31#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret31#1;havoc stop_simulation_#t~ret31#1; 37568#L1742 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 38163#L1749 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 38164#stop_simulation_returnLabel#1 start_simulation_#t~ret33#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret31#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret33#1;havoc start_simulation_#t~ret33#1; 39074#L1800 assume !(0 != start_simulation_~tmp___0~1#1); 37724#L1768-2 [2023-11-12 02:13:44,123 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-12 02:13:44,124 INFO L85 PathProgramCache]: Analyzing trace with hash -1079563311, now seen corresponding path program 1 times [2023-11-12 02:13:44,124 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-12 02:13:44,126 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [798257740] [2023-11-12 02:13:44,126 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-12 02:13:44,126 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-12 02:13:44,142 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-12 02:13:44,190 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-12 02:13:44,190 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-12 02:13:44,190 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [798257740] [2023-11-12 02:13:44,191 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [798257740] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-12 02:13:44,191 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-12 02:13:44,191 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-12 02:13:44,192 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1135948706] [2023-11-12 02:13:44,192 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-12 02:13:44,193 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-12 02:13:44,193 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-12 02:13:44,193 INFO L85 PathProgramCache]: Analyzing trace with hash 136545628, now seen corresponding path program 1 times [2023-11-12 02:13:44,193 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-12 02:13:44,194 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1188874352] [2023-11-12 02:13:44,194 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-12 02:13:44,194 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-12 02:13:44,212 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-12 02:13:44,292 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-12 02:13:44,292 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-12 02:13:44,292 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1188874352] [2023-11-12 02:13:44,292 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1188874352] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-12 02:13:44,292 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-12 02:13:44,293 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-12 02:13:44,293 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1108707800] [2023-11-12 02:13:44,293 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-12 02:13:44,294 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-12 02:13:44,294 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-12 02:13:44,294 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-12 02:13:44,294 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-12 02:13:44,295 INFO L87 Difference]: Start difference. First operand 1701 states and 2507 transitions. cyclomatic complexity: 807 Second operand has 3 states, 3 states have (on average 49.333333333333336) internal successors, (148), 3 states have internal predecessors, (148), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-12 02:13:44,340 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-12 02:13:44,341 INFO L93 Difference]: Finished difference Result 1701 states and 2506 transitions. [2023-11-12 02:13:44,341 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1701 states and 2506 transitions. [2023-11-12 02:13:44,351 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1540 [2023-11-12 02:13:44,361 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1701 states to 1701 states and 2506 transitions. [2023-11-12 02:13:44,361 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1701 [2023-11-12 02:13:44,364 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1701 [2023-11-12 02:13:44,364 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1701 states and 2506 transitions. [2023-11-12 02:13:44,366 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-12 02:13:44,367 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1701 states and 2506 transitions. [2023-11-12 02:13:44,370 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1701 states and 2506 transitions. [2023-11-12 02:13:44,397 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1701 to 1701. [2023-11-12 02:13:44,399 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1701 states, 1701 states have (on average 1.4732510288065843) internal successors, (2506), 1700 states have internal predecessors, (2506), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-12 02:13:44,405 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1701 states to 1701 states and 2506 transitions. [2023-11-12 02:13:44,405 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1701 states and 2506 transitions. [2023-11-12 02:13:44,406 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-12 02:13:44,406 INFO L428 stractBuchiCegarLoop]: Abstraction has 1701 states and 2506 transitions. [2023-11-12 02:13:44,407 INFO L335 stractBuchiCegarLoop]: ======== Iteration 13 ============ [2023-11-12 02:13:44,407 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1701 states and 2506 transitions. [2023-11-12 02:13:44,414 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1540 [2023-11-12 02:13:44,414 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-12 02:13:44,414 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-12 02:13:44,417 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-12 02:13:44,417 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-12 02:13:44,418 INFO L748 eck$LassoCheckResult]: Stem: 41201#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2; 41202#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~14#1;havoc main_~__retres1~14#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1; 41994#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret32#1, start_simulation_#t~ret33#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 41995#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 41862#L821 assume 1 == ~m_i~0;~m_st~0 := 0; 41863#L821-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 41956#L826-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 42255#L831-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 42390#L836-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 42391#L841-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 41177#L846-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 41178#L851-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 42322#L856-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 41760#L861-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 41761#L866-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 41671#L871-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 41672#L876-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 42065#L881-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 41416#L1174 assume !(0 == ~M_E~0); 41417#L1174-2 assume 0 == ~T1_E~0;~T1_E~0 := 1; 41268#L1179-1 assume !(0 == ~T2_E~0); 41174#L1184-1 assume !(0 == ~T3_E~0); 41175#L1189-1 assume !(0 == ~T4_E~0); 41217#L1194-1 assume !(0 == ~T5_E~0); 41310#L1199-1 assume !(0 == ~T6_E~0); 42189#L1204-1 assume !(0 == ~T7_E~0); 42110#L1209-1 assume !(0 == ~T8_E~0); 42111#L1214-1 assume 0 == ~T9_E~0;~T9_E~0 := 1; 42534#L1219-1 assume !(0 == ~T10_E~0); 42619#L1224-1 assume !(0 == ~T11_E~0); 41533#L1229-1 assume !(0 == ~T12_E~0); 41104#L1234-1 assume !(0 == ~E_1~0); 41105#L1239-1 assume !(0 == ~E_2~0); 41137#L1244-1 assume !(0 == ~E_3~0); 41138#L1249-1 assume !(0 == ~E_4~0); 41780#L1254-1 assume 0 == ~E_5~0;~E_5~0 := 1; 41034#L1259-1 assume !(0 == ~E_6~0); 40987#L1264-1 assume !(0 == ~E_7~0); 40988#L1269-1 assume !(0 == ~E_8~0); 42622#L1274-1 assume !(0 == ~E_9~0); 42561#L1279-1 assume !(0 == ~E_10~0); 41221#L1284-1 assume !(0 == ~E_11~0); 41222#L1289-1 assume !(0 == ~E_12~0); 41832#L1294-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 41833#L566 assume 1 == ~m_pc~0; 41004#L567 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 41005#L577 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 41876#is_master_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 41877#L1455 assume !(0 != activate_threads_~tmp~1#1); 41443#L1455-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 41444#L585 assume 1 == ~t1_pc~0; 41101#L586 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 41102#L596 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 42245#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 42246#L1463 assume !(0 != activate_threads_~tmp___0~0#1); 42590#L1463-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 42586#L604 assume !(1 == ~t2_pc~0); 42151#L604-2 is_transmit2_triggered_~__retres1~2#1 := 0; 42152#L615 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 41386#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 41387#L1471 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 42350#L1471-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 42351#L623 assume 1 == ~t3_pc~0; 41617#L624 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 40963#L634 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 42220#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 42221#L1479 assume !(0 != activate_threads_~tmp___2~0#1); 42384#L1479-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 41001#L642 assume !(1 == ~t4_pc~0); 41002#L642-2 is_transmit4_triggered_~__retres1~4#1 := 0; 41454#L653 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 41056#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 41057#L1487 assume !(0 != activate_threads_~tmp___3~0#1); 41078#L1487-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 42164#L661 assume 1 == ~t5_pc~0; 41234#L662 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 41235#L672 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 42082#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 42449#L1495 assume !(0 != activate_threads_~tmp___4~0#1); 42196#L1495-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 42197#L680 assume !(1 == ~t6_pc~0); 41650#L680-2 is_transmit6_triggered_~__retres1~6#1 := 0; 41651#L691 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 41377#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 41378#L1503 assume !(0 != activate_threads_~tmp___5~0#1); 42459#L1503-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 42583#L699 assume 1 == ~t7_pc~0; 42045#L700 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 42046#L710 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 42278#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 41938#L1511 assume !(0 != activate_threads_~tmp___6~0#1); 41939#L1511-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 41834#L718 assume !(1 == ~t8_pc~0); 41835#L718-2 is_transmit8_triggered_~__retres1~8#1 := 0; 41215#L729 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 41216#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 41250#L1519 assume !(0 != activate_threads_~tmp___7~0#1); 41251#L1519-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 41383#L737 assume 1 == ~t9_pc~0; 42234#L738 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 41514#L748 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 41423#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 41424#L1527 assume !(0 != activate_threads_~tmp___8~0#1); 41691#L1527-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 41692#L756 assume 1 == ~t10_pc~0; 42268#L757 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 41929#L767 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 42184#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 41869#L1535 assume !(0 != activate_threads_~tmp___9~0#1); 41493#L1535-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 41494#L775 assume !(1 == ~t11_pc~0); 41752#L775-2 is_transmit11_triggered_~__retres1~11#1 := 0; 41753#L786 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 42527#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 41149#L1543 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 41150#L1543-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 41331#L794 assume 1 == ~t12_pc~0; 41172#L795 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 41152#L805 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 41007#is_transmit12_triggered_returnLabel#1 activate_threads_#t~ret30#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 41008#L1551 assume !(0 != activate_threads_~tmp___11~0#1); 41296#L1551-2 havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 41764#L1307 assume !(1 == ~M_E~0); 41765#L1307-2 assume !(1 == ~T1_E~0); 41873#L1312-1 assume !(1 == ~T2_E~0); 41793#L1317-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 41794#L1322-1 assume !(1 == ~T4_E~0); 41504#L1327-1 assume !(1 == ~T5_E~0); 41505#L1332-1 assume !(1 == ~T6_E~0); 42050#L1337-1 assume !(1 == ~T7_E~0); 42007#L1342-1 assume !(1 == ~T8_E~0); 42008#L1347-1 assume !(1 == ~T9_E~0); 42420#L1352-1 assume !(1 == ~T10_E~0); 42279#L1357-1 assume 1 == ~T11_E~0;~T11_E~0 := 2; 41669#L1362-1 assume !(1 == ~T12_E~0); 41670#L1367-1 assume !(1 == ~E_1~0); 41311#L1372-1 assume !(1 == ~E_2~0); 41312#L1377-1 assume !(1 == ~E_3~0); 41602#L1382-1 assume !(1 == ~E_4~0); 41603#L1387-1 assume !(1 == ~E_5~0); 42153#L1392-1 assume !(1 == ~E_6~0); 41620#L1397-1 assume 1 == ~E_7~0;~E_7~0 := 2; 41621#L1402-1 assume !(1 == ~E_8~0); 41326#L1407-1 assume !(1 == ~E_9~0); 41327#L1412-1 assume !(1 == ~E_10~0); 42345#L1417-1 assume !(1 == ~E_11~0); 42346#L1422-1 assume !(1 == ~E_12~0); 42580#L1427-1 assume { :end_inline_reset_delta_events } true; 41133#L1768-2 [2023-11-12 02:13:44,419 INFO L750 eck$LassoCheckResult]: Loop: 41133#L1768-2 assume !false; 41134#L1769 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 41797#L1149-1 assume !false; 42175#L972 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 42402#L894 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 41511#L961 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 42327#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 42397#L976 assume !(0 != eval_~tmp~0#1); 41825#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 41554#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 41555#L1174-3 assume 0 == ~M_E~0;~M_E~0 := 1; 42355#L1174-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 42093#L1179-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 42094#L1184-3 assume !(0 == ~T3_E~0); 42280#L1189-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 41924#L1194-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 41287#L1199-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 41288#L1204-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 41524#L1209-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 40947#L1214-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 40948#L1219-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 41704#L1224-3 assume !(0 == ~T11_E~0); 41705#L1229-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 41719#L1234-3 assume 0 == ~E_1~0;~E_1~0 := 1; 41143#L1239-3 assume 0 == ~E_2~0;~E_2~0 := 1; 41144#L1244-3 assume 0 == ~E_3~0;~E_3~0 := 1; 41579#L1249-3 assume 0 == ~E_4~0;~E_4~0 := 1; 42037#L1254-3 assume 0 == ~E_5~0;~E_5~0 := 1; 42530#L1259-3 assume 0 == ~E_6~0;~E_6~0 := 1; 42136#L1264-3 assume !(0 == ~E_7~0); 41147#L1269-3 assume 0 == ~E_8~0;~E_8~0 := 1; 41148#L1274-3 assume 0 == ~E_9~0;~E_9~0 := 1; 42560#L1279-3 assume 0 == ~E_10~0;~E_10~0 := 1; 41700#L1284-3 assume 0 == ~E_11~0;~E_11~0 := 1; 41701#L1289-3 assume 0 == ~E_12~0;~E_12~0 := 1; 41688#L1294-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 41367#L566-39 assume 1 == ~m_pc~0; 41368#L567-13 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 41967#L577-13 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 41968#is_master_triggered_returnLabel#14 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 42020#L1455-39 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 42211#L1455-41 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 42212#L585-39 assume 1 == ~t1_pc~0; 42341#L586-13 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 41376#L596-13 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 41576#is_transmit1_triggered_returnLabel#14 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 42524#L1463-39 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 42249#L1463-41 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 41944#L604-39 assume 1 == ~t2_pc~0; 41945#L605-13 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 41583#L615-13 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 41584#is_transmit2_triggered_returnLabel#14 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 41763#L1471-39 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 41997#L1471-41 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 41565#L623-39 assume 1 == ~t3_pc~0; 40964#L624-13 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 40965#L634-13 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 42229#is_transmit3_triggered_returnLabel#14 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 41418#L1479-39 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 41419#L1479-41 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 42171#L642-39 assume 1 == ~t4_pc~0; 41754#L643-13 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 41755#L653-13 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 41919#is_transmit4_triggered_returnLabel#14 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 41920#L1487-39 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 42401#L1487-41 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 41337#L661-39 assume 1 == ~t5_pc~0; 41338#L662-13 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 40973#L672-13 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 41951#is_transmit5_triggered_returnLabel#14 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 41952#L1495-39 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 42231#L1495-41 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 42232#L680-39 assume !(1 == ~t6_pc~0); 41041#L680-41 is_transmit6_triggered_~__retres1~6#1 := 0; 41040#L691-13 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 42480#is_transmit6_triggered_returnLabel#14 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 41491#L1503-39 assume !(0 != activate_threads_~tmp___5~0#1); 41492#L1503-41 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 42536#L699-39 assume 1 == ~t7_pc~0; 41926#L700-13 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 41653#L710-13 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 41654#is_transmit7_triggered_returnLabel#14 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 42236#L1511-39 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 42476#L1511-41 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 42473#L718-39 assume !(1 == ~t8_pc~0); 41840#L718-41 is_transmit8_triggered_~__retres1~8#1 := 0; 41839#L729-13 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 42332#is_transmit8_triggered_returnLabel#14 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 42333#L1519-39 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 42081#L1519-41 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 42058#L737-39 assume 1 == ~t9_pc~0; 41472#L738-13 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 41473#L748-13 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 41067#is_transmit9_triggered_returnLabel#14 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 41068#L1527-39 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 42448#L1527-41 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 42385#L756-39 assume 1 == ~t10_pc~0; 42386#L757-13 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 41853#L767-13 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 42523#is_transmit10_triggered_returnLabel#14 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 41737#L1535-39 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 41738#L1535-41 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 41088#L775-39 assume 1 == ~t11_pc~0; 41089#L776-13 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 41728#L786-13 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 41729#is_transmit11_triggered_returnLabel#14 activate_threads_#t~ret29#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 41978#L1543-39 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 42129#L1543-41 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 41779#L794-39 assume 1 == ~t12_pc~0; 41475#L795-13 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 41469#L805-13 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 41562#is_transmit12_triggered_returnLabel#14 activate_threads_#t~ret30#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 41563#L1551-39 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 41030#L1551-41 havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 41031#L1307-3 assume 1 == ~M_E~0;~M_E~0 := 2; 42507#L1307-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 42508#L1312-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 42621#L1317-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 42198#L1322-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 42199#L1327-3 assume !(1 == ~T5_E~0); 41164#L1332-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 41139#L1337-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 41140#L1342-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 41867#L1347-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 42000#L1352-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 42001#L1357-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 42456#L1362-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 42616#L1367-3 assume !(1 == ~E_1~0); 42607#L1372-3 assume 1 == ~E_2~0;~E_2~0 := 2; 40960#L1377-3 assume 1 == ~E_3~0;~E_3~0 := 2; 40961#L1382-3 assume 1 == ~E_4~0;~E_4~0 := 2; 41586#L1387-3 assume 1 == ~E_5~0;~E_5~0 := 2; 41587#L1392-3 assume 1 == ~E_6~0;~E_6~0 := 2; 42306#L1397-3 assume 1 == ~E_7~0;~E_7~0 := 2; 42574#L1402-3 assume 1 == ~E_8~0;~E_8~0 := 2; 41966#L1407-3 assume !(1 == ~E_9~0); 41246#L1412-3 assume 1 == ~E_10~0;~E_10~0 := 2; 41247#L1417-3 assume 1 == ~E_11~0;~E_11~0 := 2; 41881#L1422-3 assume 1 == ~E_12~0;~E_12~0 := 2; 41882#L1427-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 41254#L894-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 41255#L961-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 41322#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret32#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret32#1;havoc start_simulation_#t~ret32#1; 41323#L1787 assume !(0 == start_simulation_~tmp~3#1); 41970#L1787-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret31#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 42516#L894-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 41231#L961-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 40979#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret31#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret31#1;havoc stop_simulation_#t~ret31#1; 40980#L1742 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 41572#L1749 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 41573#stop_simulation_returnLabel#1 start_simulation_#t~ret33#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret31#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret33#1;havoc start_simulation_#t~ret33#1; 42483#L1800 assume !(0 != start_simulation_~tmp___0~1#1); 41133#L1768-2 [2023-11-12 02:13:44,420 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-12 02:13:44,420 INFO L85 PathProgramCache]: Analyzing trace with hash -1368382701, now seen corresponding path program 1 times [2023-11-12 02:13:44,420 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-12 02:13:44,420 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1910075058] [2023-11-12 02:13:44,421 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-12 02:13:44,421 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-12 02:13:44,438 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-12 02:13:44,490 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-12 02:13:44,490 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-12 02:13:44,491 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1910075058] [2023-11-12 02:13:44,491 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1910075058] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-12 02:13:44,491 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-12 02:13:44,491 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2023-11-12 02:13:44,491 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2126441572] [2023-11-12 02:13:44,492 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-12 02:13:44,492 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-12 02:13:44,492 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-12 02:13:44,493 INFO L85 PathProgramCache]: Analyzing trace with hash -767287619, now seen corresponding path program 1 times [2023-11-12 02:13:44,493 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-12 02:13:44,493 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [635843524] [2023-11-12 02:13:44,493 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-12 02:13:44,493 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-12 02:13:44,512 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-12 02:13:44,562 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-12 02:13:44,563 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-12 02:13:44,563 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [635843524] [2023-11-12 02:13:44,563 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [635843524] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-12 02:13:44,563 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-12 02:13:44,564 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-12 02:13:44,564 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [249181476] [2023-11-12 02:13:44,564 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-12 02:13:44,564 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-12 02:13:44,565 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-12 02:13:44,565 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-12 02:13:44,565 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-12 02:13:44,566 INFO L87 Difference]: Start difference. First operand 1701 states and 2506 transitions. cyclomatic complexity: 806 Second operand has 3 states, 3 states have (on average 49.333333333333336) internal successors, (148), 2 states have internal predecessors, (148), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-12 02:13:44,617 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-12 02:13:44,617 INFO L93 Difference]: Finished difference Result 1701 states and 2501 transitions. [2023-11-12 02:13:44,617 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1701 states and 2501 transitions. [2023-11-12 02:13:44,627 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1540 [2023-11-12 02:13:44,637 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1701 states to 1701 states and 2501 transitions. [2023-11-12 02:13:44,637 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1701 [2023-11-12 02:13:44,639 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1701 [2023-11-12 02:13:44,639 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1701 states and 2501 transitions. [2023-11-12 02:13:44,642 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-12 02:13:44,642 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1701 states and 2501 transitions. [2023-11-12 02:13:44,646 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1701 states and 2501 transitions. [2023-11-12 02:13:44,672 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1701 to 1701. [2023-11-12 02:13:44,675 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1701 states, 1701 states have (on average 1.4703115814226926) internal successors, (2501), 1700 states have internal predecessors, (2501), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-12 02:13:44,681 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1701 states to 1701 states and 2501 transitions. [2023-11-12 02:13:44,681 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1701 states and 2501 transitions. [2023-11-12 02:13:44,681 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-12 02:13:44,682 INFO L428 stractBuchiCegarLoop]: Abstraction has 1701 states and 2501 transitions. [2023-11-12 02:13:44,683 INFO L335 stractBuchiCegarLoop]: ======== Iteration 14 ============ [2023-11-12 02:13:44,683 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1701 states and 2501 transitions. [2023-11-12 02:13:44,690 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1540 [2023-11-12 02:13:44,691 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-12 02:13:44,691 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-12 02:13:44,693 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-12 02:13:44,694 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-12 02:13:44,694 INFO L748 eck$LassoCheckResult]: Stem: 44610#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2; 44611#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~14#1;havoc main_~__retres1~14#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1; 45403#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret32#1, start_simulation_#t~ret33#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 45404#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 45271#L821 assume 1 == ~m_i~0;~m_st~0 := 0; 45272#L821-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 45365#L826-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 45664#L831-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 45799#L836-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 45800#L841-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 44586#L846-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 44587#L851-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 45731#L856-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 45169#L861-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 45170#L866-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 45080#L871-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 45081#L876-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 45474#L881-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 44825#L1174 assume !(0 == ~M_E~0); 44826#L1174-2 assume !(0 == ~T1_E~0); 44677#L1179-1 assume !(0 == ~T2_E~0); 44583#L1184-1 assume !(0 == ~T3_E~0); 44584#L1189-1 assume !(0 == ~T4_E~0); 44626#L1194-1 assume !(0 == ~T5_E~0); 44719#L1199-1 assume !(0 == ~T6_E~0); 45598#L1204-1 assume !(0 == ~T7_E~0); 45519#L1209-1 assume !(0 == ~T8_E~0); 45520#L1214-1 assume 0 == ~T9_E~0;~T9_E~0 := 1; 45943#L1219-1 assume !(0 == ~T10_E~0); 46028#L1224-1 assume !(0 == ~T11_E~0); 44942#L1229-1 assume !(0 == ~T12_E~0); 44513#L1234-1 assume !(0 == ~E_1~0); 44514#L1239-1 assume !(0 == ~E_2~0); 44546#L1244-1 assume !(0 == ~E_3~0); 44547#L1249-1 assume !(0 == ~E_4~0); 45189#L1254-1 assume 0 == ~E_5~0;~E_5~0 := 1; 44443#L1259-1 assume !(0 == ~E_6~0); 44396#L1264-1 assume !(0 == ~E_7~0); 44397#L1269-1 assume !(0 == ~E_8~0); 46031#L1274-1 assume !(0 == ~E_9~0); 45970#L1279-1 assume !(0 == ~E_10~0); 44630#L1284-1 assume !(0 == ~E_11~0); 44631#L1289-1 assume !(0 == ~E_12~0); 45241#L1294-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 45242#L566 assume 1 == ~m_pc~0; 44413#L567 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 44414#L577 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 45285#is_master_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 45286#L1455 assume !(0 != activate_threads_~tmp~1#1); 44852#L1455-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 44853#L585 assume 1 == ~t1_pc~0; 44510#L586 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 44511#L596 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 45654#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 45655#L1463 assume !(0 != activate_threads_~tmp___0~0#1); 45999#L1463-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 45995#L604 assume !(1 == ~t2_pc~0); 45560#L604-2 is_transmit2_triggered_~__retres1~2#1 := 0; 45561#L615 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 44795#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 44796#L1471 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 45759#L1471-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 45760#L623 assume 1 == ~t3_pc~0; 45026#L624 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 44372#L634 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 45629#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 45630#L1479 assume !(0 != activate_threads_~tmp___2~0#1); 45793#L1479-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 44410#L642 assume !(1 == ~t4_pc~0); 44411#L642-2 is_transmit4_triggered_~__retres1~4#1 := 0; 44863#L653 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 44465#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 44466#L1487 assume !(0 != activate_threads_~tmp___3~0#1); 44487#L1487-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 45573#L661 assume 1 == ~t5_pc~0; 44643#L662 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 44644#L672 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 45491#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 45858#L1495 assume !(0 != activate_threads_~tmp___4~0#1); 45605#L1495-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 45606#L680 assume !(1 == ~t6_pc~0); 45059#L680-2 is_transmit6_triggered_~__retres1~6#1 := 0; 45060#L691 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 44786#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 44787#L1503 assume !(0 != activate_threads_~tmp___5~0#1); 45868#L1503-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 45992#L699 assume 1 == ~t7_pc~0; 45454#L700 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 45455#L710 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 45687#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 45347#L1511 assume !(0 != activate_threads_~tmp___6~0#1); 45348#L1511-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 45243#L718 assume !(1 == ~t8_pc~0); 45244#L718-2 is_transmit8_triggered_~__retres1~8#1 := 0; 44624#L729 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 44625#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 44659#L1519 assume !(0 != activate_threads_~tmp___7~0#1); 44660#L1519-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 44792#L737 assume 1 == ~t9_pc~0; 45643#L738 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 44923#L748 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 44832#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 44833#L1527 assume !(0 != activate_threads_~tmp___8~0#1); 45100#L1527-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 45101#L756 assume 1 == ~t10_pc~0; 45677#L757 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 45338#L767 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 45593#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 45278#L1535 assume !(0 != activate_threads_~tmp___9~0#1); 44902#L1535-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 44903#L775 assume !(1 == ~t11_pc~0); 45161#L775-2 is_transmit11_triggered_~__retres1~11#1 := 0; 45162#L786 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 45936#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 44558#L1543 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 44559#L1543-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 44740#L794 assume 1 == ~t12_pc~0; 44581#L795 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 44561#L805 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 44416#is_transmit12_triggered_returnLabel#1 activate_threads_#t~ret30#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 44417#L1551 assume !(0 != activate_threads_~tmp___11~0#1); 44705#L1551-2 havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 45173#L1307 assume !(1 == ~M_E~0); 45174#L1307-2 assume !(1 == ~T1_E~0); 45282#L1312-1 assume !(1 == ~T2_E~0); 45202#L1317-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 45203#L1322-1 assume !(1 == ~T4_E~0); 44913#L1327-1 assume !(1 == ~T5_E~0); 44914#L1332-1 assume !(1 == ~T6_E~0); 45459#L1337-1 assume !(1 == ~T7_E~0); 45416#L1342-1 assume !(1 == ~T8_E~0); 45417#L1347-1 assume !(1 == ~T9_E~0); 45829#L1352-1 assume !(1 == ~T10_E~0); 45688#L1357-1 assume 1 == ~T11_E~0;~T11_E~0 := 2; 45078#L1362-1 assume !(1 == ~T12_E~0); 45079#L1367-1 assume !(1 == ~E_1~0); 44720#L1372-1 assume !(1 == ~E_2~0); 44721#L1377-1 assume !(1 == ~E_3~0); 45011#L1382-1 assume !(1 == ~E_4~0); 45012#L1387-1 assume !(1 == ~E_5~0); 45562#L1392-1 assume !(1 == ~E_6~0); 45029#L1397-1 assume 1 == ~E_7~0;~E_7~0 := 2; 45030#L1402-1 assume !(1 == ~E_8~0); 44735#L1407-1 assume !(1 == ~E_9~0); 44736#L1412-1 assume !(1 == ~E_10~0); 45754#L1417-1 assume !(1 == ~E_11~0); 45755#L1422-1 assume !(1 == ~E_12~0); 45989#L1427-1 assume { :end_inline_reset_delta_events } true; 44542#L1768-2 [2023-11-12 02:13:44,695 INFO L750 eck$LassoCheckResult]: Loop: 44542#L1768-2 assume !false; 44543#L1769 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 45206#L1149-1 assume !false; 45584#L972 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 45811#L894 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 44920#L961 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 45736#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 45806#L976 assume !(0 != eval_~tmp~0#1); 45234#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 44963#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 44964#L1174-3 assume 0 == ~M_E~0;~M_E~0 := 1; 45764#L1174-5 assume !(0 == ~T1_E~0); 45502#L1179-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 45503#L1184-3 assume !(0 == ~T3_E~0); 45689#L1189-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 45333#L1194-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 44696#L1199-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 44697#L1204-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 44933#L1209-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 44356#L1214-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 44357#L1219-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 45113#L1224-3 assume !(0 == ~T11_E~0); 45114#L1229-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 45128#L1234-3 assume 0 == ~E_1~0;~E_1~0 := 1; 44552#L1239-3 assume 0 == ~E_2~0;~E_2~0 := 1; 44553#L1244-3 assume 0 == ~E_3~0;~E_3~0 := 1; 44988#L1249-3 assume 0 == ~E_4~0;~E_4~0 := 1; 45446#L1254-3 assume 0 == ~E_5~0;~E_5~0 := 1; 45939#L1259-3 assume 0 == ~E_6~0;~E_6~0 := 1; 45545#L1264-3 assume !(0 == ~E_7~0); 44556#L1269-3 assume 0 == ~E_8~0;~E_8~0 := 1; 44557#L1274-3 assume 0 == ~E_9~0;~E_9~0 := 1; 45969#L1279-3 assume 0 == ~E_10~0;~E_10~0 := 1; 45109#L1284-3 assume 0 == ~E_11~0;~E_11~0 := 1; 45110#L1289-3 assume 0 == ~E_12~0;~E_12~0 := 1; 45097#L1294-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 44776#L566-39 assume 1 == ~m_pc~0; 44777#L567-13 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 45376#L577-13 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 45377#is_master_triggered_returnLabel#14 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 45429#L1455-39 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 45620#L1455-41 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 45621#L585-39 assume !(1 == ~t1_pc~0); 44784#L585-41 is_transmit1_triggered_~__retres1~1#1 := 0; 44785#L596-13 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 44985#is_transmit1_triggered_returnLabel#14 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 45933#L1463-39 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 45658#L1463-41 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 45353#L604-39 assume 1 == ~t2_pc~0; 45354#L605-13 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 44992#L615-13 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 44993#is_transmit2_triggered_returnLabel#14 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 45172#L1471-39 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 45406#L1471-41 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 44974#L623-39 assume 1 == ~t3_pc~0; 44373#L624-13 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 44374#L634-13 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 45638#is_transmit3_triggered_returnLabel#14 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 44827#L1479-39 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 44828#L1479-41 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 45580#L642-39 assume 1 == ~t4_pc~0; 45163#L643-13 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 45164#L653-13 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 45328#is_transmit4_triggered_returnLabel#14 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 45329#L1487-39 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 45810#L1487-41 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 44746#L661-39 assume 1 == ~t5_pc~0; 44747#L662-13 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 44382#L672-13 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 45360#is_transmit5_triggered_returnLabel#14 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 45361#L1495-39 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 45640#L1495-41 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 45641#L680-39 assume 1 == ~t6_pc~0; 44448#L681-13 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 44449#L691-13 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 45889#is_transmit6_triggered_returnLabel#14 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 44900#L1503-39 assume !(0 != activate_threads_~tmp___5~0#1); 44901#L1503-41 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 45945#L699-39 assume 1 == ~t7_pc~0; 45335#L700-13 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 45062#L710-13 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 45063#is_transmit7_triggered_returnLabel#14 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 45645#L1511-39 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 45885#L1511-41 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 45882#L718-39 assume !(1 == ~t8_pc~0); 45249#L718-41 is_transmit8_triggered_~__retres1~8#1 := 0; 45248#L729-13 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 45741#is_transmit8_triggered_returnLabel#14 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 45742#L1519-39 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 45490#L1519-41 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 45467#L737-39 assume 1 == ~t9_pc~0; 44881#L738-13 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 44882#L748-13 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 44476#is_transmit9_triggered_returnLabel#14 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 44477#L1527-39 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 45857#L1527-41 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 45794#L756-39 assume 1 == ~t10_pc~0; 45795#L757-13 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 45262#L767-13 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 45932#is_transmit10_triggered_returnLabel#14 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 45146#L1535-39 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 45147#L1535-41 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 44497#L775-39 assume 1 == ~t11_pc~0; 44498#L776-13 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 45137#L786-13 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 45138#is_transmit11_triggered_returnLabel#14 activate_threads_#t~ret29#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 45387#L1543-39 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 45538#L1543-41 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 45188#L794-39 assume 1 == ~t12_pc~0; 44884#L795-13 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 44878#L805-13 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 44971#is_transmit12_triggered_returnLabel#14 activate_threads_#t~ret30#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 44972#L1551-39 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 44439#L1551-41 havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 44440#L1307-3 assume 1 == ~M_E~0;~M_E~0 := 2; 45916#L1307-5 assume !(1 == ~T1_E~0); 45917#L1312-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 46030#L1317-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 45607#L1322-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 45608#L1327-3 assume !(1 == ~T5_E~0); 44573#L1332-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 44548#L1337-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 44549#L1342-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 45276#L1347-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 45409#L1352-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 45410#L1357-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 45865#L1362-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 46025#L1367-3 assume !(1 == ~E_1~0); 46016#L1372-3 assume 1 == ~E_2~0;~E_2~0 := 2; 44369#L1377-3 assume 1 == ~E_3~0;~E_3~0 := 2; 44370#L1382-3 assume 1 == ~E_4~0;~E_4~0 := 2; 44995#L1387-3 assume 1 == ~E_5~0;~E_5~0 := 2; 44996#L1392-3 assume 1 == ~E_6~0;~E_6~0 := 2; 45715#L1397-3 assume 1 == ~E_7~0;~E_7~0 := 2; 45983#L1402-3 assume 1 == ~E_8~0;~E_8~0 := 2; 45375#L1407-3 assume !(1 == ~E_9~0); 44655#L1412-3 assume 1 == ~E_10~0;~E_10~0 := 2; 44656#L1417-3 assume 1 == ~E_11~0;~E_11~0 := 2; 45290#L1422-3 assume 1 == ~E_12~0;~E_12~0 := 2; 45291#L1427-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 44663#L894-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 44664#L961-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 44731#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret32#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret32#1;havoc start_simulation_#t~ret32#1; 44732#L1787 assume !(0 == start_simulation_~tmp~3#1); 45379#L1787-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret31#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 45925#L894-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 44640#L961-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 44388#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret31#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret31#1;havoc stop_simulation_#t~ret31#1; 44389#L1742 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 44981#L1749 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 44982#stop_simulation_returnLabel#1 start_simulation_#t~ret33#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret31#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret33#1;havoc start_simulation_#t~ret33#1; 45892#L1800 assume !(0 != start_simulation_~tmp___0~1#1); 44542#L1768-2 [2023-11-12 02:13:44,696 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-12 02:13:44,696 INFO L85 PathProgramCache]: Analyzing trace with hash 1978532629, now seen corresponding path program 1 times [2023-11-12 02:13:44,697 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-12 02:13:44,697 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1869911368] [2023-11-12 02:13:44,697 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-12 02:13:44,697 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-12 02:13:44,716 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-12 02:13:44,805 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-12 02:13:44,805 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-12 02:13:44,806 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1869911368] [2023-11-12 02:13:44,806 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1869911368] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-12 02:13:44,806 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-12 02:13:44,806 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-12 02:13:44,806 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1312952509] [2023-11-12 02:13:44,806 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-12 02:13:44,809 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-12 02:13:44,809 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-12 02:13:44,809 INFO L85 PathProgramCache]: Analyzing trace with hash -1118727551, now seen corresponding path program 1 times [2023-11-12 02:13:44,809 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-12 02:13:44,810 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [981630931] [2023-11-12 02:13:44,811 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-12 02:13:44,811 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-12 02:13:44,829 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-12 02:13:44,878 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-12 02:13:44,879 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-12 02:13:44,879 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [981630931] [2023-11-12 02:13:44,879 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [981630931] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-12 02:13:44,879 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-12 02:13:44,879 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-12 02:13:44,880 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [732753785] [2023-11-12 02:13:44,880 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-12 02:13:44,881 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-12 02:13:44,881 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-12 02:13:44,881 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2023-11-12 02:13:44,882 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2023-11-12 02:13:44,882 INFO L87 Difference]: Start difference. First operand 1701 states and 2501 transitions. cyclomatic complexity: 801 Second operand has 4 states, 4 states have (on average 37.0) internal successors, (148), 3 states have internal predecessors, (148), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-12 02:13:45,145 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-12 02:13:45,145 INFO L93 Difference]: Finished difference Result 3264 states and 4792 transitions. [2023-11-12 02:13:45,146 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 3264 states and 4792 transitions. [2023-11-12 02:13:45,165 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 3080 [2023-11-12 02:13:45,194 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 3264 states to 3264 states and 4792 transitions. [2023-11-12 02:13:45,194 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 3264 [2023-11-12 02:13:45,198 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 3264 [2023-11-12 02:13:45,198 INFO L73 IsDeterministic]: Start isDeterministic. Operand 3264 states and 4792 transitions. [2023-11-12 02:13:45,203 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-12 02:13:45,203 INFO L218 hiAutomatonCegarLoop]: Abstraction has 3264 states and 4792 transitions. [2023-11-12 02:13:45,209 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3264 states and 4792 transitions. [2023-11-12 02:13:45,275 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3264 to 3264. [2023-11-12 02:13:45,280 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 3264 states, 3264 states have (on average 1.4681372549019607) internal successors, (4792), 3263 states have internal predecessors, (4792), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-12 02:13:45,291 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3264 states to 3264 states and 4792 transitions. [2023-11-12 02:13:45,291 INFO L240 hiAutomatonCegarLoop]: Abstraction has 3264 states and 4792 transitions. [2023-11-12 02:13:45,292 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2023-11-12 02:13:45,293 INFO L428 stractBuchiCegarLoop]: Abstraction has 3264 states and 4792 transitions. [2023-11-12 02:13:45,293 INFO L335 stractBuchiCegarLoop]: ======== Iteration 15 ============ [2023-11-12 02:13:45,293 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 3264 states and 4792 transitions. [2023-11-12 02:13:45,308 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 3080 [2023-11-12 02:13:45,308 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-12 02:13:45,308 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-12 02:13:45,311 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-12 02:13:45,311 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-12 02:13:45,312 INFO L748 eck$LassoCheckResult]: Stem: 49587#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2; 49588#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~14#1;havoc main_~__retres1~14#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1; 50398#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret32#1, start_simulation_#t~ret33#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 50399#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 50259#L821 assume 1 == ~m_i~0;~m_st~0 := 0; 50260#L821-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 50358#L826-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 50669#L831-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 50824#L836-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 50825#L841-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 49563#L846-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 49564#L851-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 50746#L856-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 50154#L861-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 50155#L866-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 50064#L871-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 50065#L876-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 50473#L881-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 49802#L1174 assume !(0 == ~M_E~0); 49803#L1174-2 assume !(0 == ~T1_E~0); 49654#L1179-1 assume !(0 == ~T2_E~0); 49560#L1184-1 assume !(0 == ~T3_E~0); 49561#L1189-1 assume !(0 == ~T4_E~0); 49603#L1194-1 assume !(0 == ~T5_E~0); 49696#L1199-1 assume !(0 == ~T6_E~0); 50601#L1204-1 assume !(0 == ~T7_E~0); 50518#L1209-1 assume !(0 == ~T8_E~0); 50519#L1214-1 assume !(0 == ~T9_E~0); 50993#L1219-1 assume !(0 == ~T10_E~0); 51129#L1224-1 assume !(0 == ~T11_E~0); 49921#L1229-1 assume !(0 == ~T12_E~0); 49489#L1234-1 assume !(0 == ~E_1~0); 49490#L1239-1 assume !(0 == ~E_2~0); 49522#L1244-1 assume !(0 == ~E_3~0); 49523#L1249-1 assume !(0 == ~E_4~0); 50175#L1254-1 assume 0 == ~E_5~0;~E_5~0 := 1; 49419#L1259-1 assume !(0 == ~E_6~0); 49371#L1264-1 assume !(0 == ~E_7~0); 49372#L1269-1 assume !(0 == ~E_8~0); 51139#L1274-1 assume !(0 == ~E_9~0); 51037#L1279-1 assume !(0 == ~E_10~0); 49607#L1284-1 assume !(0 == ~E_11~0); 49608#L1289-1 assume !(0 == ~E_12~0); 50229#L1294-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 50230#L566 assume 1 == ~m_pc~0; 49388#L567 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 49389#L577 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 50274#is_master_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 50275#L1455 assume !(0 != activate_threads_~tmp~1#1); 49829#L1455-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 49830#L585 assume 1 == ~t1_pc~0; 49486#L586 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 49487#L596 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 50659#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 50660#L1463 assume !(0 != activate_threads_~tmp___0~0#1); 51080#L1463-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 51073#L604 assume !(1 == ~t2_pc~0); 50559#L604-2 is_transmit2_triggered_~__retres1~2#1 := 0; 50560#L615 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 49772#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 49773#L1471 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 50781#L1471-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 50782#L623 assume 1 == ~t3_pc~0; 50009#L624 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 49347#L634 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 50634#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 50635#L1479 assume !(0 != activate_threads_~tmp___2~0#1); 50818#L1479-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 49385#L642 assume !(1 == ~t4_pc~0); 49386#L642-2 is_transmit4_triggered_~__retres1~4#1 := 0; 49840#L653 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 49441#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 49442#L1487 assume !(0 != activate_threads_~tmp___3~0#1); 49463#L1487-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 50573#L661 assume 1 == ~t5_pc~0; 49620#L662 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 49621#L672 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 50490#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 50888#L1495 assume !(0 != activate_threads_~tmp___4~0#1); 50609#L1495-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 50610#L680 assume !(1 == ~t6_pc~0); 50043#L680-2 is_transmit6_triggered_~__retres1~6#1 := 0; 50044#L691 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 49763#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 49764#L1503 assume !(0 != activate_threads_~tmp___5~0#1); 50900#L1503-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 51070#L699 assume 1 == ~t7_pc~0; 50450#L700 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 50451#L710 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 50694#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 50340#L1511 assume !(0 != activate_threads_~tmp___6~0#1); 50341#L1511-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 50231#L718 assume !(1 == ~t8_pc~0); 50232#L718-2 is_transmit8_triggered_~__retres1~8#1 := 0; 49601#L729 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 49602#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 49636#L1519 assume !(0 != activate_threads_~tmp___7~0#1); 49637#L1519-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 49769#L737 assume 1 == ~t9_pc~0; 50648#L738 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 49902#L748 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 49809#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 49810#L1527 assume !(0 != activate_threads_~tmp___8~0#1); 50084#L1527-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 50085#L756 assume 1 == ~t10_pc~0; 50682#L757 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 50331#L767 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 50596#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 50267#L1535 assume !(0 != activate_threads_~tmp___9~0#1); 49880#L1535-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 49881#L775 assume !(1 == ~t11_pc~0); 50146#L775-2 is_transmit11_triggered_~__retres1~11#1 := 0; 50147#L786 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 50984#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 49534#L1543 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 49535#L1543-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 49717#L794 assume 1 == ~t12_pc~0; 49559#L795 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 49537#L805 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 49394#is_transmit12_triggered_returnLabel#1 activate_threads_#t~ret30#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 49395#L1551 assume !(0 != activate_threads_~tmp___11~0#1); 49682#L1551-2 havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 50158#L1307 assume !(1 == ~M_E~0); 50159#L1307-2 assume !(1 == ~T1_E~0); 50271#L1312-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 51094#L1317-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 51386#L1322-1 assume !(1 == ~T4_E~0); 51385#L1327-1 assume !(1 == ~T5_E~0); 50455#L1332-1 assume !(1 == ~T6_E~0); 50456#L1337-1 assume !(1 == ~T7_E~0); 51384#L1342-1 assume !(1 == ~T8_E~0); 51034#L1347-1 assume !(1 == ~T9_E~0); 51035#L1352-1 assume !(1 == ~T10_E~0); 50695#L1357-1 assume 1 == ~T11_E~0;~T11_E~0 := 2; 50062#L1362-1 assume !(1 == ~T12_E~0); 50063#L1367-1 assume !(1 == ~E_1~0); 51382#L1372-1 assume !(1 == ~E_2~0); 51381#L1377-1 assume !(1 == ~E_3~0); 51380#L1382-1 assume !(1 == ~E_4~0); 50561#L1387-1 assume !(1 == ~E_5~0); 50562#L1392-1 assume !(1 == ~E_6~0); 50012#L1397-1 assume 1 == ~E_7~0;~E_7~0 := 2; 50013#L1402-1 assume !(1 == ~E_8~0); 49712#L1407-1 assume !(1 == ~E_9~0); 49713#L1412-1 assume !(1 == ~E_10~0); 51115#L1417-1 assume !(1 == ~E_11~0); 51196#L1422-1 assume !(1 == ~E_12~0); 51189#L1427-1 assume { :end_inline_reset_delta_events } true; 51183#L1768-2 [2023-11-12 02:13:45,313 INFO L750 eck$LassoCheckResult]: Loop: 51183#L1768-2 assume !false; 51178#L1769 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 51174#L1149-1 assume !false; 51173#L972 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 51165#L894 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 51159#L961 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 51158#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 51157#L976 assume !(0 != eval_~tmp~0#1); 51156#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 51155#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 51154#L1174-3 assume 0 == ~M_E~0;~M_E~0 := 1; 51153#L1174-5 assume !(0 == ~T1_E~0); 51151#L1179-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 51152#L1184-3 assume !(0 == ~T3_E~0); 51776#L1189-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 51775#L1194-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 51774#L1199-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 51773#L1204-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 51772#L1209-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 51771#L1214-3 assume !(0 == ~T9_E~0); 51770#L1219-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 51769#L1224-3 assume !(0 == ~T11_E~0); 51768#L1229-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 51767#L1234-3 assume 0 == ~E_1~0;~E_1~0 := 1; 51766#L1239-3 assume 0 == ~E_2~0;~E_2~0 := 1; 51765#L1244-3 assume 0 == ~E_3~0;~E_3~0 := 1; 51764#L1249-3 assume 0 == ~E_4~0;~E_4~0 := 1; 51763#L1254-3 assume 0 == ~E_5~0;~E_5~0 := 1; 51762#L1259-3 assume 0 == ~E_6~0;~E_6~0 := 1; 51761#L1264-3 assume !(0 == ~E_7~0); 51760#L1269-3 assume 0 == ~E_8~0;~E_8~0 := 1; 51759#L1274-3 assume 0 == ~E_9~0;~E_9~0 := 1; 51758#L1279-3 assume 0 == ~E_10~0;~E_10~0 := 1; 51757#L1284-3 assume 0 == ~E_11~0;~E_11~0 := 1; 51756#L1289-3 assume 0 == ~E_12~0;~E_12~0 := 1; 51755#L1294-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 51754#L566-39 assume 1 == ~m_pc~0; 51752#L567-13 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 51751#L577-13 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 51750#is_master_triggered_returnLabel#14 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 51749#L1455-39 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 51748#L1455-41 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 51747#L585-39 assume !(1 == ~t1_pc~0); 51745#L585-41 is_transmit1_triggered_~__retres1~1#1 := 0; 51744#L596-13 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 51743#is_transmit1_triggered_returnLabel#14 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 51742#L1463-39 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 51741#L1463-41 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 51740#L604-39 assume 1 == ~t2_pc~0; 51738#L605-13 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 51737#L615-13 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 51736#is_transmit2_triggered_returnLabel#14 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 51735#L1471-39 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 51734#L1471-41 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 51733#L623-39 assume !(1 == ~t3_pc~0); 51731#L623-41 is_transmit3_triggered_~__retres1~3#1 := 0; 51730#L634-13 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 51729#is_transmit3_triggered_returnLabel#14 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 51728#L1479-39 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 51727#L1479-41 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 51726#L642-39 assume 1 == ~t4_pc~0; 51724#L643-13 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 51723#L653-13 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 51722#is_transmit4_triggered_returnLabel#14 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 51721#L1487-39 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 51720#L1487-41 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 51719#L661-39 assume !(1 == ~t5_pc~0); 51717#L661-41 is_transmit5_triggered_~__retres1~5#1 := 0; 51716#L672-13 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 51715#is_transmit5_triggered_returnLabel#14 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 51714#L1495-39 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 51713#L1495-41 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 51712#L680-39 assume 1 == ~t6_pc~0; 51710#L681-13 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 51709#L691-13 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 51708#is_transmit6_triggered_returnLabel#14 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 51707#L1503-39 assume !(0 != activate_threads_~tmp___5~0#1); 51706#L1503-41 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 51705#L699-39 assume 1 == ~t7_pc~0; 51703#L700-13 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 51702#L710-13 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 51701#is_transmit7_triggered_returnLabel#14 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 51700#L1511-39 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 51699#L1511-41 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 50918#L718-39 assume !(1 == ~t8_pc~0); 50919#L718-41 is_transmit8_triggered_~__retres1~8#1 := 0; 51692#L729-13 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 51691#is_transmit8_triggered_returnLabel#14 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 51690#L1519-39 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 51689#L1519-41 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 51688#L737-39 assume 1 == ~t9_pc~0; 51686#L738-13 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 51685#L748-13 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 51684#is_transmit9_triggered_returnLabel#14 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 51683#L1527-39 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 51682#L1527-41 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 51681#L756-39 assume 1 == ~t10_pc~0; 51680#L757-13 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 51678#L767-13 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 51677#is_transmit10_triggered_returnLabel#14 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 51676#L1535-39 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 50310#L1535-41 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 49473#L775-39 assume 1 == ~t11_pc~0; 49474#L776-13 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 51654#L786-13 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 51653#is_transmit11_triggered_returnLabel#14 activate_threads_#t~ret29#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 51652#L1543-39 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 51651#L1543-41 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 51650#L794-39 assume !(1 == ~t12_pc~0); 51648#L794-41 is_transmit12_triggered_~__retres1~12#1 := 0; 51647#L805-13 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 51646#is_transmit12_triggered_returnLabel#14 activate_threads_#t~ret30#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 50588#L1551-39 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 50589#L1551-41 havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 51024#L1307-3 assume 1 == ~M_E~0;~M_E~0 := 2; 51025#L1307-5 assume !(1 == ~T1_E~0); 51644#L1312-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 51138#L1317-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 50611#L1322-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 50612#L1327-3 assume !(1 == ~T5_E~0); 49549#L1332-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 49550#L1337-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 50264#L1342-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 50265#L1347-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 50404#L1352-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 50405#L1357-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 50897#L1362-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 51122#L1367-3 assume !(1 == ~E_1~0); 51110#L1372-3 assume 1 == ~E_2~0;~E_2~0 := 2; 49344#L1377-3 assume 1 == ~E_3~0;~E_3~0 := 2; 49345#L1382-3 assume 1 == ~E_4~0;~E_4~0 := 2; 49976#L1387-3 assume 1 == ~E_5~0;~E_5~0 := 2; 49977#L1392-3 assume 1 == ~E_6~0;~E_6~0 := 2; 50729#L1397-3 assume 1 == ~E_7~0;~E_7~0 := 2; 51057#L1402-3 assume 1 == ~E_8~0;~E_8~0 := 2; 50368#L1407-3 assume !(1 == ~E_9~0); 49632#L1412-3 assume 1 == ~E_10~0;~E_10~0 := 2; 49633#L1417-3 assume 1 == ~E_11~0;~E_11~0 := 2; 50280#L1422-3 assume 1 == ~E_12~0;~E_12~0 := 2; 50281#L1427-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 51550#L894-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 51544#L961-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 51543#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret32#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret32#1;havoc start_simulation_#t~ret32#1; 51541#L1787 assume !(0 == start_simulation_~tmp~3#1); 51539#L1787-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret31#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 51538#L894-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 51525#L961-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 51524#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret31#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret31#1;havoc stop_simulation_#t~ret31#1; 51523#L1742 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 51203#L1749 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 51197#stop_simulation_returnLabel#1 start_simulation_#t~ret33#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret31#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret33#1;havoc start_simulation_#t~ret33#1; 51190#L1800 assume !(0 != start_simulation_~tmp___0~1#1); 51183#L1768-2 [2023-11-12 02:13:45,314 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-12 02:13:45,315 INFO L85 PathProgramCache]: Analyzing trace with hash -1694374055, now seen corresponding path program 1 times [2023-11-12 02:13:45,315 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-12 02:13:45,315 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [246569943] [2023-11-12 02:13:45,315 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-12 02:13:45,315 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-12 02:13:45,334 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-12 02:13:45,423 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-12 02:13:45,424 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-12 02:13:45,424 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [246569943] [2023-11-12 02:13:45,424 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [246569943] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-12 02:13:45,424 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-12 02:13:45,424 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-12 02:13:45,425 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [465505682] [2023-11-12 02:13:45,425 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-12 02:13:45,425 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-12 02:13:45,426 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-12 02:13:45,426 INFO L85 PathProgramCache]: Analyzing trace with hash 1317325792, now seen corresponding path program 1 times [2023-11-12 02:13:45,426 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-12 02:13:45,426 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2065226342] [2023-11-12 02:13:45,426 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-12 02:13:45,427 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-12 02:13:45,446 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-12 02:13:45,501 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-12 02:13:45,502 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-12 02:13:45,502 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2065226342] [2023-11-12 02:13:45,502 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2065226342] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-12 02:13:45,502 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-12 02:13:45,502 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-12 02:13:45,502 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1748134126] [2023-11-12 02:13:45,503 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-12 02:13:45,503 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-12 02:13:45,503 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-12 02:13:45,504 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2023-11-12 02:13:45,504 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2023-11-12 02:13:45,504 INFO L87 Difference]: Start difference. First operand 3264 states and 4792 transitions. cyclomatic complexity: 1530 Second operand has 4 states, 4 states have (on average 37.0) internal successors, (148), 3 states have internal predecessors, (148), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-12 02:13:45,772 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-12 02:13:45,773 INFO L93 Difference]: Finished difference Result 6184 states and 9069 transitions. [2023-11-12 02:13:45,773 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 6184 states and 9069 transitions. [2023-11-12 02:13:45,811 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 5974 [2023-11-12 02:13:45,839 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 6184 states to 6184 states and 9069 transitions. [2023-11-12 02:13:45,839 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 6184 [2023-11-12 02:13:45,846 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 6184 [2023-11-12 02:13:45,847 INFO L73 IsDeterministic]: Start isDeterministic. Operand 6184 states and 9069 transitions. [2023-11-12 02:13:45,856 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-12 02:13:45,856 INFO L218 hiAutomatonCegarLoop]: Abstraction has 6184 states and 9069 transitions. [2023-11-12 02:13:45,865 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 6184 states and 9069 transitions. [2023-11-12 02:13:46,011 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 6184 to 6182. [2023-11-12 02:13:46,020 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 6182 states, 6182 states have (on average 1.4666774506632159) internal successors, (9067), 6181 states have internal predecessors, (9067), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-12 02:13:46,041 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 6182 states to 6182 states and 9067 transitions. [2023-11-12 02:13:46,041 INFO L240 hiAutomatonCegarLoop]: Abstraction has 6182 states and 9067 transitions. [2023-11-12 02:13:46,042 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2023-11-12 02:13:46,042 INFO L428 stractBuchiCegarLoop]: Abstraction has 6182 states and 9067 transitions. [2023-11-12 02:13:46,042 INFO L335 stractBuchiCegarLoop]: ======== Iteration 16 ============ [2023-11-12 02:13:46,043 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 6182 states and 9067 transitions. [2023-11-12 02:13:46,068 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 5974 [2023-11-12 02:13:46,068 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-12 02:13:46,068 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-12 02:13:46,071 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-12 02:13:46,072 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-12 02:13:46,072 INFO L748 eck$LassoCheckResult]: Stem: 59044#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2; 59045#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~14#1;havoc main_~__retres1~14#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1; 59842#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret32#1, start_simulation_#t~ret33#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 59843#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 59709#L821 assume 1 == ~m_i~0;~m_st~0 := 0; 59710#L821-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 59803#L826-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 60110#L831-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 60256#L836-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 60257#L841-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 59020#L846-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 59021#L851-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 60182#L856-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 59607#L861-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 59608#L866-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 59517#L871-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 59518#L876-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 59914#L881-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 59259#L1174 assume !(0 == ~M_E~0); 59260#L1174-2 assume !(0 == ~T1_E~0); 59111#L1179-1 assume !(0 == ~T2_E~0); 59017#L1184-1 assume !(0 == ~T3_E~0); 59018#L1189-1 assume !(0 == ~T4_E~0); 59060#L1194-1 assume !(0 == ~T5_E~0); 59153#L1199-1 assume !(0 == ~T6_E~0); 60044#L1204-1 assume !(0 == ~T7_E~0); 59960#L1209-1 assume !(0 == ~T8_E~0); 59961#L1214-1 assume !(0 == ~T9_E~0); 60405#L1219-1 assume !(0 == ~T10_E~0); 60504#L1224-1 assume !(0 == ~T11_E~0); 59378#L1229-1 assume !(0 == ~T12_E~0); 58947#L1234-1 assume !(0 == ~E_1~0); 58948#L1239-1 assume !(0 == ~E_2~0); 58980#L1244-1 assume !(0 == ~E_3~0); 58981#L1249-1 assume !(0 == ~E_4~0); 59627#L1254-1 assume !(0 == ~E_5~0); 58877#L1259-1 assume !(0 == ~E_6~0); 58829#L1264-1 assume !(0 == ~E_7~0); 58830#L1269-1 assume !(0 == ~E_8~0); 60509#L1274-1 assume !(0 == ~E_9~0); 60437#L1279-1 assume !(0 == ~E_10~0); 59064#L1284-1 assume !(0 == ~E_11~0); 59065#L1289-1 assume !(0 == ~E_12~0); 59679#L1294-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 59680#L566 assume 1 == ~m_pc~0; 58846#L567 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 58847#L577 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 59723#is_master_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 59724#L1455 assume !(0 != activate_threads_~tmp~1#1); 59286#L1455-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 59287#L585 assume 1 == ~t1_pc~0; 58944#L586 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 58945#L596 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 60100#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 60101#L1463 assume !(0 != activate_threads_~tmp___0~0#1); 60467#L1463-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 60463#L604 assume !(1 == ~t2_pc~0); 60004#L604-2 is_transmit2_triggered_~__retres1~2#1 := 0; 60005#L615 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 59229#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 59230#L1471 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 60213#L1471-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 60214#L623 assume 1 == ~t3_pc~0; 59462#L624 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 58805#L634 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 60075#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 60076#L1479 assume !(0 != activate_threads_~tmp___2~0#1); 60249#L1479-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 58843#L642 assume !(1 == ~t4_pc~0); 58844#L642-2 is_transmit4_triggered_~__retres1~4#1 := 0; 59299#L653 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 58899#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 58900#L1487 assume !(0 != activate_threads_~tmp___3~0#1); 58921#L1487-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 60019#L661 assume 1 == ~t5_pc~0; 59077#L662 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 59078#L672 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 59932#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 60316#L1495 assume !(0 != activate_threads_~tmp___4~0#1); 60051#L1495-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 60052#L680 assume !(1 == ~t6_pc~0); 59495#L680-2 is_transmit6_triggered_~__retres1~6#1 := 0; 59496#L691 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 59220#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 59221#L1503 assume !(0 != activate_threads_~tmp___5~0#1); 60326#L1503-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 60460#L699 assume 1 == ~t7_pc~0; 59894#L700 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 59895#L710 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 60134#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 59785#L1511 assume !(0 != activate_threads_~tmp___6~0#1); 59786#L1511-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 59681#L718 assume !(1 == ~t8_pc~0); 59682#L718-2 is_transmit8_triggered_~__retres1~8#1 := 0; 59058#L729 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 59059#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 59093#L1519 assume !(0 != activate_threads_~tmp___7~0#1); 59094#L1519-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 59226#L737 assume 1 == ~t9_pc~0; 60089#L738 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 59359#L748 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 59266#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 59267#L1527 assume !(0 != activate_threads_~tmp___8~0#1); 59537#L1527-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 59538#L756 assume 1 == ~t10_pc~0; 60124#L757 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 59776#L767 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 60039#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 59716#L1535 assume !(0 != activate_threads_~tmp___9~0#1); 59338#L1535-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 59339#L775 assume !(1 == ~t11_pc~0); 59599#L775-2 is_transmit11_triggered_~__retres1~11#1 := 0; 59600#L786 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 60397#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 58992#L1543 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 58993#L1543-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 59174#L794 assume 1 == ~t12_pc~0; 59015#L795 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 58995#L805 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 58849#is_transmit12_triggered_returnLabel#1 activate_threads_#t~ret30#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 58850#L1551 assume !(0 != activate_threads_~tmp___11~0#1); 59139#L1551-2 havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 59611#L1307 assume !(1 == ~M_E~0); 59612#L1307-2 assume !(1 == ~T1_E~0); 59720#L1312-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 59640#L1317-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 59641#L1322-1 assume !(1 == ~T4_E~0); 59349#L1327-1 assume !(1 == ~T5_E~0); 59350#L1332-1 assume !(1 == ~T6_E~0); 59899#L1337-1 assume !(1 == ~T7_E~0); 59855#L1342-1 assume !(1 == ~T8_E~0); 59856#L1347-1 assume !(1 == ~T9_E~0); 60436#L1352-1 assume !(1 == ~T10_E~0); 61137#L1357-1 assume 1 == ~T11_E~0;~T11_E~0 := 2; 59515#L1362-1 assume !(1 == ~T12_E~0); 59516#L1367-1 assume !(1 == ~E_1~0); 59154#L1372-1 assume !(1 == ~E_2~0); 59155#L1377-1 assume !(1 == ~E_3~0); 59447#L1382-1 assume !(1 == ~E_4~0); 59448#L1387-1 assume !(1 == ~E_5~0); 60608#L1392-1 assume !(1 == ~E_6~0); 60606#L1397-1 assume 1 == ~E_7~0;~E_7~0 := 2; 60604#L1402-1 assume !(1 == ~E_8~0); 60601#L1407-1 assume !(1 == ~E_9~0); 60587#L1412-1 assume !(1 == ~E_10~0); 60575#L1417-1 assume !(1 == ~E_11~0); 60565#L1422-1 assume !(1 == ~E_12~0); 60556#L1427-1 assume { :end_inline_reset_delta_events } true; 60549#L1768-2 [2023-11-12 02:13:46,073 INFO L750 eck$LassoCheckResult]: Loop: 60549#L1768-2 assume !false; 60543#L1769 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 60539#L1149-1 assume !false; 60538#L972 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 60530#L894 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 60524#L961 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 60523#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 60521#L976 assume !(0 != eval_~tmp~0#1); 60520#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 60519#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 60518#L1174-3 assume 0 == ~M_E~0;~M_E~0 := 1; 60517#L1174-5 assume !(0 == ~T1_E~0); 60515#L1179-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 60516#L1184-3 assume !(0 == ~T3_E~0); 62500#L1189-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 62498#L1194-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 62496#L1199-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 62493#L1204-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 62491#L1209-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 62490#L1214-3 assume !(0 == ~T9_E~0); 62489#L1219-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 62488#L1224-3 assume !(0 == ~T11_E~0); 62487#L1229-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 62485#L1234-3 assume 0 == ~E_1~0;~E_1~0 := 1; 62483#L1239-3 assume 0 == ~E_2~0;~E_2~0 := 1; 62481#L1244-3 assume 0 == ~E_3~0;~E_3~0 := 1; 62479#L1249-3 assume 0 == ~E_4~0;~E_4~0 := 1; 62477#L1254-3 assume !(0 == ~E_5~0); 62475#L1259-3 assume 0 == ~E_6~0;~E_6~0 := 1; 62473#L1264-3 assume !(0 == ~E_7~0); 62471#L1269-3 assume 0 == ~E_8~0;~E_8~0 := 1; 62469#L1274-3 assume 0 == ~E_9~0;~E_9~0 := 1; 62467#L1279-3 assume 0 == ~E_10~0;~E_10~0 := 1; 62465#L1284-3 assume 0 == ~E_11~0;~E_11~0 := 1; 62463#L1289-3 assume 0 == ~E_12~0;~E_12~0 := 1; 62461#L1294-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 62459#L566-39 assume 1 == ~m_pc~0; 62456#L567-13 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 62455#L577-13 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 62454#is_master_triggered_returnLabel#14 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 62453#L1455-39 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 62452#L1455-41 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 62451#L585-39 assume !(1 == ~t1_pc~0); 62448#L585-41 is_transmit1_triggered_~__retres1~1#1 := 0; 62446#L596-13 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 62444#is_transmit1_triggered_returnLabel#14 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 62441#L1463-39 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 62439#L1463-41 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 62437#L604-39 assume 1 == ~t2_pc~0; 62434#L605-13 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 62432#L615-13 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 62430#is_transmit2_triggered_returnLabel#14 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 62429#L1471-39 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 62426#L1471-41 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 62424#L623-39 assume !(1 == ~t3_pc~0); 62358#L623-41 is_transmit3_triggered_~__retres1~3#1 := 0; 62351#L634-13 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 62347#is_transmit3_triggered_returnLabel#14 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 62341#L1479-39 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 62336#L1479-41 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 62331#L642-39 assume 1 == ~t4_pc~0; 62324#L643-13 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 62318#L653-13 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 62312#is_transmit4_triggered_returnLabel#14 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 62306#L1487-39 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 62301#L1487-41 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 62296#L661-39 assume !(1 == ~t5_pc~0); 62289#L661-41 is_transmit5_triggered_~__retres1~5#1 := 0; 62283#L672-13 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 62277#is_transmit5_triggered_returnLabel#14 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 62271#L1495-39 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 62266#L1495-41 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 62261#L680-39 assume 1 == ~t6_pc~0; 62254#L681-13 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 62248#L691-13 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 62242#is_transmit6_triggered_returnLabel#14 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 62236#L1503-39 assume !(0 != activate_threads_~tmp___5~0#1); 62231#L1503-41 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 62226#L699-39 assume 1 == ~t7_pc~0; 62219#L700-13 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 62213#L710-13 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 62207#is_transmit7_triggered_returnLabel#14 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 62201#L1511-39 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 62196#L1511-41 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 62191#L718-39 assume 1 == ~t8_pc~0; 62184#L719-13 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 62178#L729-13 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 62172#is_transmit8_triggered_returnLabel#14 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 62166#L1519-39 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 62161#L1519-41 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 62156#L737-39 assume 1 == ~t9_pc~0; 62149#L738-13 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 62143#L748-13 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 62137#is_transmit9_triggered_returnLabel#14 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 62132#L1527-39 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 62058#L1527-41 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 62055#L756-39 assume !(1 == ~t10_pc~0); 62052#L756-41 is_transmit10_triggered_~__retres1~10#1 := 0; 62050#L767-13 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 62048#is_transmit10_triggered_returnLabel#14 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 62046#L1535-39 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 62044#L1535-41 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 62043#L775-39 assume 1 == ~t11_pc~0; 62039#L776-13 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 62037#L786-13 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 62035#is_transmit11_triggered_returnLabel#14 activate_threads_#t~ret29#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 62033#L1543-39 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 62031#L1543-41 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 62029#L794-39 assume !(1 == ~t12_pc~0); 61982#L794-41 is_transmit12_triggered_~__retres1~12#1 := 0; 61973#L805-13 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 61965#is_transmit12_triggered_returnLabel#14 activate_threads_#t~ret30#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 61958#L1551-39 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 61950#L1551-41 havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 61943#L1307-3 assume 1 == ~M_E~0;~M_E~0 := 2; 61928#L1307-5 assume !(1 == ~T1_E~0); 61920#L1312-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 60508#L1317-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 61907#L1322-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 61900#L1327-3 assume !(1 == ~T5_E~0); 61892#L1332-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 61883#L1337-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 61874#L1342-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 61866#L1347-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 60195#L1352-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 61851#L1357-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 61844#L1362-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 61836#L1367-3 assume !(1 == ~E_1~0); 61824#L1372-3 assume 1 == ~E_2~0;~E_2~0 := 2; 61814#L1377-3 assume 1 == ~E_3~0;~E_3~0 := 2; 61807#L1382-3 assume 1 == ~E_4~0;~E_4~0 := 2; 61798#L1387-3 assume 1 == ~E_5~0;~E_5~0 := 2; 61789#L1392-3 assume 1 == ~E_6~0;~E_6~0 := 2; 61781#L1397-3 assume 1 == ~E_7~0;~E_7~0 := 2; 61772#L1402-3 assume 1 == ~E_8~0;~E_8~0 := 2; 61764#L1407-3 assume !(1 == ~E_9~0); 61759#L1412-3 assume 1 == ~E_10~0;~E_10~0 := 2; 61025#L1417-3 assume 1 == ~E_11~0;~E_11~0 := 2; 61023#L1422-3 assume 1 == ~E_12~0;~E_12~0 := 2; 61021#L1427-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 60768#L894-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 60761#L961-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 60759#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret32#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret32#1;havoc start_simulation_#t~ret32#1; 60757#L1787 assume !(0 == start_simulation_~tmp~3#1); 60755#L1787-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret31#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 60621#L894-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 60607#L961-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 60605#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret31#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret31#1;havoc stop_simulation_#t~ret31#1; 60588#L1742 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 60576#L1749 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 60566#stop_simulation_returnLabel#1 start_simulation_#t~ret33#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret31#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret33#1;havoc start_simulation_#t~ret33#1; 60557#L1800 assume !(0 != start_simulation_~tmp___0~1#1); 60549#L1768-2 [2023-11-12 02:13:46,073 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-12 02:13:46,074 INFO L85 PathProgramCache]: Analyzing trace with hash 32770907, now seen corresponding path program 1 times [2023-11-12 02:13:46,074 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-12 02:13:46,074 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [511893172] [2023-11-12 02:13:46,074 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-12 02:13:46,074 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-12 02:13:46,094 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-12 02:13:46,161 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-12 02:13:46,162 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-12 02:13:46,162 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [511893172] [2023-11-12 02:13:46,162 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [511893172] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-12 02:13:46,162 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-12 02:13:46,162 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2023-11-12 02:13:46,163 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1641519371] [2023-11-12 02:13:46,163 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-12 02:13:46,163 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-12 02:13:46,163 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-12 02:13:46,164 INFO L85 PathProgramCache]: Analyzing trace with hash -1219333278, now seen corresponding path program 1 times [2023-11-12 02:13:46,164 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-12 02:13:46,164 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [590691621] [2023-11-12 02:13:46,164 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-12 02:13:46,164 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-12 02:13:46,183 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-12 02:13:46,228 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-12 02:13:46,228 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-12 02:13:46,229 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [590691621] [2023-11-12 02:13:46,229 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [590691621] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-12 02:13:46,229 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-12 02:13:46,229 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-12 02:13:46,229 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [326300070] [2023-11-12 02:13:46,229 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-12 02:13:46,230 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-12 02:13:46,230 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-12 02:13:46,231 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-12 02:13:46,231 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-12 02:13:46,231 INFO L87 Difference]: Start difference. First operand 6182 states and 9067 transitions. cyclomatic complexity: 2889 Second operand has 3 states, 3 states have (on average 49.333333333333336) internal successors, (148), 2 states have internal predecessors, (148), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-12 02:13:46,418 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-12 02:13:46,419 INFO L93 Difference]: Finished difference Result 12093 states and 17615 transitions. [2023-11-12 02:13:46,419 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 12093 states and 17615 transitions. [2023-11-12 02:13:46,472 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 11882 [2023-11-12 02:13:46,515 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 12093 states to 12093 states and 17615 transitions. [2023-11-12 02:13:46,515 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 12093 [2023-11-12 02:13:46,529 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 12093 [2023-11-12 02:13:46,530 INFO L73 IsDeterministic]: Start isDeterministic. Operand 12093 states and 17615 transitions. [2023-11-12 02:13:46,641 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-12 02:13:46,641 INFO L218 hiAutomatonCegarLoop]: Abstraction has 12093 states and 17615 transitions. [2023-11-12 02:13:46,660 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 12093 states and 17615 transitions. [2023-11-12 02:13:46,848 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 12093 to 11725. [2023-11-12 02:13:46,865 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 11725 states, 11725 states have (on average 1.4583368869936033) internal successors, (17099), 11724 states have internal predecessors, (17099), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-12 02:13:46,901 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 11725 states to 11725 states and 17099 transitions. [2023-11-12 02:13:46,902 INFO L240 hiAutomatonCegarLoop]: Abstraction has 11725 states and 17099 transitions. [2023-11-12 02:13:46,902 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-12 02:13:46,903 INFO L428 stractBuchiCegarLoop]: Abstraction has 11725 states and 17099 transitions. [2023-11-12 02:13:46,903 INFO L335 stractBuchiCegarLoop]: ======== Iteration 17 ============ [2023-11-12 02:13:46,903 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 11725 states and 17099 transitions. [2023-11-12 02:13:46,950 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 11514 [2023-11-12 02:13:46,950 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-12 02:13:46,951 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-12 02:13:46,954 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-12 02:13:46,954 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-12 02:13:46,955 INFO L748 eck$LassoCheckResult]: Stem: 77323#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2; 77324#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~14#1;havoc main_~__retres1~14#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1; 78131#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret32#1, start_simulation_#t~ret33#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 78132#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 77994#L821 assume 1 == ~m_i~0;~m_st~0 := 0; 77995#L821-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 78089#L826-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 78428#L831-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 78583#L836-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 78584#L841-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 77299#L846-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 77300#L851-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 78499#L856-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 77888#L861-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 77889#L866-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 77799#L871-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 77800#L876-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 78210#L881-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 77536#L1174 assume !(0 == ~M_E~0); 77537#L1174-2 assume !(0 == ~T1_E~0); 77392#L1179-1 assume !(0 == ~T2_E~0); 77297#L1184-1 assume !(0 == ~T3_E~0); 77298#L1189-1 assume !(0 == ~T4_E~0); 77339#L1194-1 assume !(0 == ~T5_E~0); 77434#L1199-1 assume !(0 == ~T6_E~0); 78346#L1204-1 assume !(0 == ~T7_E~0); 78256#L1209-1 assume !(0 == ~T8_E~0); 78257#L1214-1 assume !(0 == ~T9_E~0); 78742#L1219-1 assume !(0 == ~T10_E~0); 78885#L1224-1 assume !(0 == ~T11_E~0); 77656#L1229-1 assume !(0 == ~T12_E~0); 77226#L1234-1 assume !(0 == ~E_1~0); 77227#L1239-1 assume !(0 == ~E_2~0); 77261#L1244-1 assume !(0 == ~E_3~0); 77262#L1249-1 assume !(0 == ~E_4~0); 77908#L1254-1 assume !(0 == ~E_5~0); 77156#L1259-1 assume !(0 == ~E_6~0); 77111#L1264-1 assume !(0 == ~E_7~0); 77112#L1269-1 assume !(0 == ~E_8~0); 78899#L1274-1 assume !(0 == ~E_9~0); 78782#L1279-1 assume !(0 == ~E_10~0); 77343#L1284-1 assume !(0 == ~E_11~0); 77344#L1289-1 assume !(0 == ~E_12~0); 77963#L1294-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 77964#L566 assume !(1 == ~m_pc~0); 78419#L566-2 is_master_triggered_~__retres1~0#1 := 0; 78420#L577 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 78009#is_master_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 78010#L1455 assume !(0 != activate_threads_~tmp~1#1); 77563#L1455-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 77564#L585 assume 1 == ~t1_pc~0; 77223#L586 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 77224#L596 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 78410#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 78411#L1463 assume !(0 != activate_threads_~tmp___0~0#1); 78828#L1463-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 78821#L604 assume !(1 == ~t2_pc~0); 78304#L604-2 is_transmit2_triggered_~__retres1~2#1 := 0; 78305#L615 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 77511#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 77512#L1471 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 78538#L1471-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 78539#L623 assume 1 == ~t3_pc~0; 77741#L624 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 77087#L634 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 78386#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 78387#L1479 assume !(0 != activate_threads_~tmp___2~0#1); 78576#L1479-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 77125#L642 assume !(1 == ~t4_pc~0); 77126#L642-2 is_transmit4_triggered_~__retres1~4#1 := 0; 77574#L653 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 77184#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 77185#L1487 assume !(0 != activate_threads_~tmp___3~0#1); 77200#L1487-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 78319#L661 assume 1 == ~t5_pc~0; 77356#L662 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 77357#L672 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 78228#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 78647#L1495 assume !(0 != activate_threads_~tmp___4~0#1); 78357#L1495-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 78358#L680 assume !(1 == ~t6_pc~0); 77775#L680-2 is_transmit6_triggered_~__retres1~6#1 := 0; 77776#L691 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 77500#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 77501#L1503 assume !(0 != activate_threads_~tmp___5~0#1); 78657#L1503-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 78819#L699 assume 1 == ~t7_pc~0; 78187#L700 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 78188#L710 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 78447#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 78071#L1511 assume !(0 != activate_threads_~tmp___6~0#1); 78072#L1511-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 77965#L718 assume !(1 == ~t8_pc~0); 77966#L718-2 is_transmit8_triggered_~__retres1~8#1 := 0; 77337#L729 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 77338#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 77374#L1519 assume !(0 != activate_threads_~tmp___7~0#1); 77375#L1519-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 77503#L737 assume 1 == ~t9_pc~0; 78399#L738 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 77638#L748 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 77543#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 77544#L1527 assume !(0 != activate_threads_~tmp___8~0#1); 77817#L1527-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 77818#L756 assume 1 == ~t10_pc~0; 78438#L757 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 78063#L767 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 78340#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 78002#L1535 assume !(0 != activate_threads_~tmp___9~0#1); 77613#L1535-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 77614#L775 assume !(1 == ~t11_pc~0); 77880#L775-2 is_transmit11_triggered_~__retres1~11#1 := 0; 77881#L786 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 78735#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 77271#L1543 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 77272#L1543-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 77453#L794 assume 1 == ~t12_pc~0; 77295#L795 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 77274#L805 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 77131#is_transmit12_triggered_returnLabel#1 activate_threads_#t~ret30#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 77132#L1551 assume !(0 != activate_threads_~tmp___11~0#1); 77420#L1551-2 havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 77892#L1307 assume !(1 == ~M_E~0); 77893#L1307-2 assume !(1 == ~T1_E~0); 78006#L1312-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 77921#L1317-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 77922#L1322-1 assume !(1 == ~T4_E~0); 77626#L1327-1 assume !(1 == ~T5_E~0); 77627#L1332-1 assume !(1 == ~T6_E~0); 78193#L1337-1 assume !(1 == ~T7_E~0); 78144#L1342-1 assume !(1 == ~T8_E~0); 78145#L1347-1 assume !(1 == ~T9_E~0); 78777#L1352-1 assume !(1 == ~T10_E~0); 87329#L1357-1 assume 1 == ~T11_E~0;~T11_E~0 := 2; 87328#L1362-1 assume !(1 == ~T12_E~0); 87327#L1367-1 assume !(1 == ~E_1~0); 86271#L1372-1 assume !(1 == ~E_2~0); 86268#L1377-1 assume !(1 == ~E_3~0); 86266#L1382-1 assume !(1 == ~E_4~0); 86262#L1387-1 assume !(1 == ~E_5~0); 86259#L1392-1 assume !(1 == ~E_6~0); 84680#L1397-1 assume 1 == ~E_7~0;~E_7~0 := 2; 84678#L1402-1 assume !(1 == ~E_8~0); 84676#L1407-1 assume !(1 == ~E_9~0); 84345#L1412-1 assume !(1 == ~E_10~0); 84331#L1417-1 assume !(1 == ~E_11~0); 84329#L1422-1 assume !(1 == ~E_12~0); 84321#L1427-1 assume { :end_inline_reset_delta_events } true; 84314#L1768-2 [2023-11-12 02:13:46,956 INFO L750 eck$LassoCheckResult]: Loop: 84314#L1768-2 assume !false; 84308#L1769 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 84304#L1149-1 assume !false; 84303#L972 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 84295#L894 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 84289#L961 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 84288#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 84286#L976 assume !(0 != eval_~tmp~0#1); 84287#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 86633#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 86631#L1174-3 assume 0 == ~M_E~0;~M_E~0 := 1; 86629#L1174-5 assume !(0 == ~T1_E~0); 86627#L1179-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 86624#L1184-3 assume !(0 == ~T3_E~0); 86622#L1189-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 86620#L1194-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 86618#L1199-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 86616#L1204-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 86614#L1209-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 86611#L1214-3 assume !(0 == ~T9_E~0); 86609#L1219-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 86607#L1224-3 assume !(0 == ~T11_E~0); 86605#L1229-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 86603#L1234-3 assume 0 == ~E_1~0;~E_1~0 := 1; 86601#L1239-3 assume 0 == ~E_2~0;~E_2~0 := 1; 86598#L1244-3 assume 0 == ~E_3~0;~E_3~0 := 1; 86596#L1249-3 assume 0 == ~E_4~0;~E_4~0 := 1; 86594#L1254-3 assume !(0 == ~E_5~0); 86592#L1259-3 assume 0 == ~E_6~0;~E_6~0 := 1; 86590#L1264-3 assume !(0 == ~E_7~0); 86589#L1269-3 assume 0 == ~E_8~0;~E_8~0 := 1; 86585#L1274-3 assume 0 == ~E_9~0;~E_9~0 := 1; 86583#L1279-3 assume 0 == ~E_10~0;~E_10~0 := 1; 86581#L1284-3 assume 0 == ~E_11~0;~E_11~0 := 1; 86580#L1289-3 assume 0 == ~E_12~0;~E_12~0 := 1; 77814#L1294-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 77485#L566-39 assume !(1 == ~m_pc~0); 77486#L566-41 is_master_triggered_~__retres1~0#1 := 0; 78100#L577-13 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 78101#is_master_triggered_returnLabel#14 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 78156#L1455-39 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 78371#L1455-41 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 78372#L585-39 assume !(1 == ~t1_pc~0); 77495#L585-41 is_transmit1_triggered_~__retres1~1#1 := 0; 77496#L596-13 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 77698#is_transmit1_triggered_returnLabel#14 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 78732#L1463-39 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 78414#L1463-41 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 78077#L604-39 assume !(1 == ~t2_pc~0); 78079#L604-41 is_transmit2_triggered_~__retres1~2#1 := 0; 77707#L615-13 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 77708#is_transmit2_triggered_returnLabel#14 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 77891#L1471-39 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 78133#L1471-41 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 77686#L623-39 assume 1 == ~t3_pc~0; 77088#L624-13 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 77089#L634-13 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 78392#is_transmit3_triggered_returnLabel#14 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 77538#L1479-39 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 77539#L1479-41 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 78326#L642-39 assume 1 == ~t4_pc~0; 77882#L643-13 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 77883#L653-13 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 78052#is_transmit4_triggered_returnLabel#14 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 78053#L1487-39 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 78595#L1487-41 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 77459#L661-39 assume 1 == ~t5_pc~0; 77460#L662-13 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 77097#L672-13 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 78084#is_transmit5_triggered_returnLabel#14 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 78085#L1495-39 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 78394#L1495-41 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 78395#L680-39 assume 1 == ~t6_pc~0; 77161#L681-13 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 77162#L691-13 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 78679#is_transmit6_triggered_returnLabel#14 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 77611#L1503-39 assume !(0 != activate_threads_~tmp___5~0#1); 77612#L1503-41 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 78744#L699-39 assume 1 == ~t7_pc~0; 78059#L700-13 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 77778#L710-13 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 77779#is_transmit7_triggered_returnLabel#14 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 78398#L1511-39 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 78675#L1511-41 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 78672#L718-39 assume 1 == ~t8_pc~0; 77969#L719-13 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 77970#L729-13 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 78513#is_transmit8_triggered_returnLabel#14 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 78514#L1519-39 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 78227#L1519-41 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 78202#L737-39 assume 1 == ~t9_pc~0; 77592#L738-13 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 77593#L748-13 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 77189#is_transmit9_triggered_returnLabel#14 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 77190#L1527-39 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 78646#L1527-41 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 78577#L756-39 assume 1 == ~t10_pc~0; 78578#L757-13 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 77984#L767-13 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 78731#is_transmit10_triggered_returnLabel#14 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 77865#L1535-39 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 77866#L1535-41 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 77210#L775-39 assume 1 == ~t11_pc~0; 77211#L776-13 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 77856#L786-13 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 77857#is_transmit11_triggered_returnLabel#14 activate_threads_#t~ret29#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 78112#L1543-39 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 78279#L1543-41 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 77907#L794-39 assume !(1 == ~t12_pc~0); 77588#L794-41 is_transmit12_triggered_~__retres1~12#1 := 0; 77589#L805-13 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 77683#is_transmit12_triggered_returnLabel#14 activate_threads_#t~ret30#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 77684#L1551-39 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 77152#L1551-41 havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 77153#L1307-3 assume 1 == ~M_E~0;~M_E~0 := 2; 78711#L1307-5 assume !(1 == ~T1_E~0); 78712#L1312-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 78898#L1317-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 78355#L1322-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 78356#L1327-3 assume !(1 == ~T5_E~0); 77286#L1332-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 77259#L1337-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 77260#L1342-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 78000#L1347-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 78136#L1352-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 78137#L1357-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 78654#L1362-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 78880#L1367-3 assume !(1 == ~E_1~0); 78864#L1372-3 assume 1 == ~E_2~0;~E_2~0 := 2; 77084#L1377-3 assume 1 == ~E_3~0;~E_3~0 := 2; 77085#L1382-3 assume 1 == ~E_4~0;~E_4~0 := 2; 77710#L1387-3 assume 1 == ~E_5~0;~E_5~0 := 2; 77711#L1392-3 assume 1 == ~E_6~0;~E_6~0 := 2; 86497#L1397-3 assume 1 == ~E_7~0;~E_7~0 := 2; 86260#L1402-3 assume 1 == ~E_8~0;~E_8~0 := 2; 86258#L1407-3 assume !(1 == ~E_9~0); 86257#L1412-3 assume 1 == ~E_10~0;~E_10~0 := 2; 86255#L1417-3 assume 1 == ~E_11~0;~E_11~0 := 2; 86254#L1422-3 assume 1 == ~E_12~0;~E_12~0 := 2; 86252#L1427-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 84666#L894-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 84659#L961-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 84657#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret32#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret32#1;havoc start_simulation_#t~ret32#1; 84654#L1787 assume !(0 == start_simulation_~tmp~3#1); 84651#L1787-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret31#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 84344#L894-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 84330#L961-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 84328#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret31#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret31#1;havoc stop_simulation_#t~ret31#1; 84327#L1742 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 84326#L1749 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 84324#stop_simulation_returnLabel#1 start_simulation_#t~ret33#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret31#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret33#1;havoc start_simulation_#t~ret33#1; 84322#L1800 assume !(0 != start_simulation_~tmp___0~1#1); 84314#L1768-2 [2023-11-12 02:13:46,956 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-12 02:13:46,957 INFO L85 PathProgramCache]: Analyzing trace with hash -1204882182, now seen corresponding path program 1 times [2023-11-12 02:13:46,957 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-12 02:13:46,957 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [137437480] [2023-11-12 02:13:46,957 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-12 02:13:46,958 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-12 02:13:46,978 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-12 02:13:47,065 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-12 02:13:47,066 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-12 02:13:47,066 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [137437480] [2023-11-12 02:13:47,066 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [137437480] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-12 02:13:47,066 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-12 02:13:47,066 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-12 02:13:47,067 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [826597913] [2023-11-12 02:13:47,067 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-12 02:13:47,067 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-12 02:13:47,068 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-12 02:13:47,068 INFO L85 PathProgramCache]: Analyzing trace with hash 957602883, now seen corresponding path program 1 times [2023-11-12 02:13:47,068 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-12 02:13:47,068 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1671716283] [2023-11-12 02:13:47,069 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-12 02:13:47,069 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-12 02:13:47,090 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-12 02:13:47,148 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-12 02:13:47,148 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-12 02:13:47,148 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1671716283] [2023-11-12 02:13:47,149 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1671716283] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-12 02:13:47,149 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-12 02:13:47,149 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-12 02:13:47,149 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1049262611] [2023-11-12 02:13:47,150 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-12 02:13:47,150 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-12 02:13:47,150 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-12 02:13:47,151 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2023-11-12 02:13:47,151 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2023-11-12 02:13:47,151 INFO L87 Difference]: Start difference. First operand 11725 states and 17099 transitions. cyclomatic complexity: 5382 Second operand has 4 states, 4 states have (on average 37.0) internal successors, (148), 3 states have internal predecessors, (148), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-12 02:13:47,787 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-12 02:13:47,787 INFO L93 Difference]: Finished difference Result 28552 states and 41325 transitions. [2023-11-12 02:13:47,787 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 28552 states and 41325 transitions. [2023-11-12 02:13:47,912 INFO L131 ngComponentsAnalysis]: Automaton has 12 accepting balls. 27942 [2023-11-12 02:13:48,011 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 28552 states to 28552 states and 41325 transitions. [2023-11-12 02:13:48,012 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 28552 [2023-11-12 02:13:48,045 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 28552 [2023-11-12 02:13:48,045 INFO L73 IsDeterministic]: Start isDeterministic. Operand 28552 states and 41325 transitions. [2023-11-12 02:13:48,072 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-12 02:13:48,072 INFO L218 hiAutomatonCegarLoop]: Abstraction has 28552 states and 41325 transitions. [2023-11-12 02:13:48,102 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 28552 states and 41325 transitions. [2023-11-12 02:13:48,528 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 28552 to 22382. [2023-11-12 02:13:48,557 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 22382 states, 22382 states have (on average 1.4518809757841122) internal successors, (32496), 22381 states have internal predecessors, (32496), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-12 02:13:48,616 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 22382 states to 22382 states and 32496 transitions. [2023-11-12 02:13:48,616 INFO L240 hiAutomatonCegarLoop]: Abstraction has 22382 states and 32496 transitions. [2023-11-12 02:13:48,617 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2023-11-12 02:13:48,617 INFO L428 stractBuchiCegarLoop]: Abstraction has 22382 states and 32496 transitions. [2023-11-12 02:13:48,618 INFO L335 stractBuchiCegarLoop]: ======== Iteration 18 ============ [2023-11-12 02:13:48,618 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 22382 states and 32496 transitions. [2023-11-12 02:13:48,687 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 22168 [2023-11-12 02:13:48,687 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-12 02:13:48,687 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-12 02:13:48,690 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-12 02:13:48,691 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-12 02:13:48,691 INFO L748 eck$LassoCheckResult]: Stem: 117605#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2; 117606#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~14#1;havoc main_~__retres1~14#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1; 118418#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret32#1, start_simulation_#t~ret33#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 118419#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 118283#L821 assume 1 == ~m_i~0;~m_st~0 := 0; 118284#L821-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 118379#L826-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 118702#L831-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 118851#L836-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 118852#L841-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 117581#L846-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 117582#L851-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 118772#L856-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 118178#L861-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 118179#L866-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 118089#L871-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 118090#L876-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 118496#L881-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 117822#L1174 assume !(0 == ~M_E~0); 117823#L1174-2 assume !(0 == ~T1_E~0); 117674#L1179-1 assume !(0 == ~T2_E~0); 117578#L1184-1 assume !(0 == ~T3_E~0); 117579#L1189-1 assume !(0 == ~T4_E~0); 117622#L1194-1 assume !(0 == ~T5_E~0); 117716#L1199-1 assume !(0 == ~T6_E~0); 118630#L1204-1 assume !(0 == ~T7_E~0); 118544#L1209-1 assume !(0 == ~T8_E~0); 118545#L1214-1 assume !(0 == ~T9_E~0); 119003#L1219-1 assume !(0 == ~T10_E~0); 119123#L1224-1 assume !(0 == ~T11_E~0); 117944#L1229-1 assume !(0 == ~T12_E~0); 117509#L1234-1 assume !(0 == ~E_1~0); 117510#L1239-1 assume !(0 == ~E_2~0); 117542#L1244-1 assume !(0 == ~E_3~0); 117543#L1249-1 assume !(0 == ~E_4~0); 118197#L1254-1 assume !(0 == ~E_5~0); 117442#L1259-1 assume !(0 == ~E_6~0); 117397#L1264-1 assume !(0 == ~E_7~0); 117398#L1269-1 assume !(0 == ~E_8~0); 119138#L1274-1 assume !(0 == ~E_9~0); 119041#L1279-1 assume !(0 == ~E_10~0); 117625#L1284-1 assume !(0 == ~E_11~0); 117626#L1289-1 assume !(0 == ~E_12~0); 118252#L1294-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 118253#L566 assume !(1 == ~m_pc~0); 118697#L566-2 is_master_triggered_~__retres1~0#1 := 0; 118698#L577 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 118297#is_master_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 118298#L1455 assume !(0 != activate_threads_~tmp~1#1); 117850#L1455-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 117851#L585 assume !(1 == ~t1_pc~0); 118034#L585-2 is_transmit1_triggered_~__retres1~1#1 := 0; 118035#L596 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 118690#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 118691#L1463 assume !(0 != activate_threads_~tmp___0~0#1); 119083#L1463-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 119079#L604 assume !(1 == ~t2_pc~0); 118589#L604-2 is_transmit2_triggered_~__retres1~2#1 := 0; 118590#L615 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 117792#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 117793#L1471 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 118807#L1471-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 118808#L623 assume 1 == ~t3_pc~0; 118033#L624 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 117373#L634 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 118665#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 118666#L1479 assume !(0 != activate_threads_~tmp___2~0#1); 118844#L1479-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 117411#L642 assume !(1 == ~t4_pc~0); 117412#L642-2 is_transmit4_triggered_~__retres1~4#1 := 0; 117863#L653 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 117464#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 117465#L1487 assume !(0 != activate_threads_~tmp___3~0#1); 117486#L1487-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 118604#L661 assume 1 == ~t5_pc~0; 117640#L662 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 117641#L672 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 118514#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 118917#L1495 assume !(0 != activate_threads_~tmp___4~0#1); 118637#L1495-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 118638#L680 assume !(1 == ~t6_pc~0); 118068#L680-2 is_transmit6_triggered_~__retres1~6#1 := 0; 118069#L691 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 117783#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 117784#L1503 assume !(0 != activate_threads_~tmp___5~0#1); 118927#L1503-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 119076#L699 assume 1 == ~t7_pc~0; 118476#L700 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 118477#L710 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 118727#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 118361#L1511 assume !(0 != activate_threads_~tmp___6~0#1); 118362#L1511-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 118254#L718 assume !(1 == ~t8_pc~0); 118255#L718-2 is_transmit8_triggered_~__retres1~8#1 := 0; 117620#L729 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 117621#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 117656#L1519 assume !(0 != activate_threads_~tmp___7~0#1); 117657#L1519-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 117789#L737 assume 1 == ~t9_pc~0; 118679#L738 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 117926#L748 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 117830#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 117831#L1527 assume !(0 != activate_threads_~tmp___8~0#1); 118109#L1527-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 118110#L756 assume 1 == ~t10_pc~0; 118716#L757 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 118351#L767 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 118625#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 118290#L1535 assume !(0 != activate_threads_~tmp___9~0#1); 117904#L1535-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 117905#L775 assume !(1 == ~t11_pc~0); 118170#L775-2 is_transmit11_triggered_~__retres1~11#1 := 0; 118171#L786 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 118996#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 117554#L1543 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 117555#L1543-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 117737#L794 assume 1 == ~t12_pc~0; 117576#L795 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 117557#L805 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 117414#is_transmit12_triggered_returnLabel#1 activate_threads_#t~ret30#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 117415#L1551 assume !(0 != activate_threads_~tmp___11~0#1); 117702#L1551-2 havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 118182#L1307 assume !(1 == ~M_E~0); 118183#L1307-2 assume !(1 == ~T1_E~0); 118294#L1312-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 118210#L1317-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 118211#L1322-1 assume !(1 == ~T4_E~0); 117916#L1327-1 assume !(1 == ~T5_E~0); 117917#L1332-1 assume !(1 == ~T6_E~0); 118481#L1337-1 assume !(1 == ~T7_E~0); 118432#L1342-1 assume !(1 == ~T8_E~0); 118433#L1347-1 assume !(1 == ~T9_E~0); 118884#L1352-1 assume !(1 == ~T10_E~0); 118885#L1357-1 assume 1 == ~T11_E~0;~T11_E~0 := 2; 118087#L1362-1 assume !(1 == ~T12_E~0); 118088#L1367-1 assume !(1 == ~E_1~0); 117717#L1372-1 assume !(1 == ~E_2~0); 117718#L1377-1 assume !(1 == ~E_3~0); 118018#L1382-1 assume !(1 == ~E_4~0); 118019#L1387-1 assume !(1 == ~E_5~0); 118592#L1392-1 assume !(1 == ~E_6~0); 136351#L1397-1 assume 1 == ~E_7~0;~E_7~0 := 2; 136350#L1402-1 assume !(1 == ~E_8~0); 136349#L1407-1 assume !(1 == ~E_9~0); 136348#L1412-1 assume !(1 == ~E_10~0); 136347#L1417-1 assume !(1 == ~E_11~0); 136346#L1422-1 assume !(1 == ~E_12~0); 136344#L1427-1 assume { :end_inline_reset_delta_events } true; 136335#L1768-2 [2023-11-12 02:13:48,692 INFO L750 eck$LassoCheckResult]: Loop: 136335#L1768-2 assume !false; 136327#L1769 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 136320#L1149-1 assume !false; 136318#L972 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 136281#L894 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 136273#L961 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 136269#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 136265#L976 assume !(0 != eval_~tmp~0#1); 136266#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 139277#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 139275#L1174-3 assume 0 == ~M_E~0;~M_E~0 := 1; 139273#L1174-5 assume !(0 == ~T1_E~0); 139271#L1179-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 139269#L1184-3 assume !(0 == ~T3_E~0); 139267#L1189-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 139264#L1194-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 139262#L1199-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 139260#L1204-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 139258#L1209-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 139256#L1214-3 assume !(0 == ~T9_E~0); 139254#L1219-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 139251#L1224-3 assume !(0 == ~T11_E~0); 139249#L1229-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 139247#L1234-3 assume 0 == ~E_1~0;~E_1~0 := 1; 139245#L1239-3 assume 0 == ~E_2~0;~E_2~0 := 1; 139243#L1244-3 assume 0 == ~E_3~0;~E_3~0 := 1; 139241#L1249-3 assume 0 == ~E_4~0;~E_4~0 := 1; 139238#L1254-3 assume !(0 == ~E_5~0); 139236#L1259-3 assume 0 == ~E_6~0;~E_6~0 := 1; 139234#L1264-3 assume !(0 == ~E_7~0); 139232#L1269-3 assume 0 == ~E_8~0;~E_8~0 := 1; 139230#L1274-3 assume 0 == ~E_9~0;~E_9~0 := 1; 139228#L1279-3 assume 0 == ~E_10~0;~E_10~0 := 1; 139225#L1284-3 assume 0 == ~E_11~0;~E_11~0 := 1; 139223#L1289-3 assume 0 == ~E_12~0;~E_12~0 := 1; 139221#L1294-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 139219#L566-39 assume !(1 == ~m_pc~0); 139217#L566-41 is_master_triggered_~__retres1~0#1 := 0; 139215#L577-13 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 139212#is_master_triggered_returnLabel#14 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 139210#L1455-39 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 139208#L1455-41 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 139206#L585-39 assume !(1 == ~t1_pc~0); 129906#L585-41 is_transmit1_triggered_~__retres1~1#1 := 0; 139203#L596-13 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 139200#is_transmit1_triggered_returnLabel#14 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 139198#L1463-39 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 139196#L1463-41 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 139194#L604-39 assume 1 == ~t2_pc~0; 139191#L605-13 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 139189#L615-13 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 139186#is_transmit2_triggered_returnLabel#14 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 139185#L1471-39 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 139184#L1471-41 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 139183#L623-39 assume 1 == ~t3_pc~0; 139182#L624-13 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 139180#L634-13 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 139179#is_transmit3_triggered_returnLabel#14 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 139178#L1479-39 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 139177#L1479-41 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 139176#L642-39 assume 1 == ~t4_pc~0; 139174#L643-13 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 139173#L653-13 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 138618#is_transmit4_triggered_returnLabel#14 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 138617#L1487-39 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 138616#L1487-41 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 138615#L661-39 assume 1 == ~t5_pc~0; 138614#L662-13 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 138612#L672-13 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 138611#is_transmit5_triggered_returnLabel#14 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 138610#L1495-39 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 138609#L1495-41 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 138608#L680-39 assume 1 == ~t6_pc~0; 138606#L681-13 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 138605#L691-13 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 138604#is_transmit6_triggered_returnLabel#14 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 138603#L1503-39 assume !(0 != activate_threads_~tmp___5~0#1); 138602#L1503-41 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 138601#L699-39 assume 1 == ~t7_pc~0; 138598#L700-13 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 138596#L710-13 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 138594#is_transmit7_triggered_returnLabel#14 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 138592#L1511-39 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 138590#L1511-41 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 138588#L718-39 assume !(1 == ~t8_pc~0); 138586#L718-41 is_transmit8_triggered_~__retres1~8#1 := 0; 138584#L729-13 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 138582#is_transmit8_triggered_returnLabel#14 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 138580#L1519-39 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 138578#L1519-41 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 138576#L737-39 assume !(1 == ~t9_pc~0); 138574#L737-41 is_transmit9_triggered_~__retres1~9#1 := 0; 138570#L748-13 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 138568#is_transmit9_triggered_returnLabel#14 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 138566#L1527-39 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 138564#L1527-41 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 138562#L756-39 assume 1 == ~t10_pc~0; 138560#L757-13 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 138556#L767-13 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 138554#is_transmit10_triggered_returnLabel#14 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 138552#L1535-39 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 138550#L1535-41 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 138548#L775-39 assume !(1 == ~t11_pc~0); 138546#L775-41 is_transmit11_triggered_~__retres1~11#1 := 0; 138542#L786-13 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 138540#is_transmit11_triggered_returnLabel#14 activate_threads_#t~ret29#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 138538#L1543-39 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 138389#L1543-41 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 138387#L794-39 assume !(1 == ~t12_pc~0); 138384#L794-41 is_transmit12_triggered_~__retres1~12#1 := 0; 138382#L805-13 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 138380#is_transmit12_triggered_returnLabel#14 activate_threads_#t~ret30#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 138378#L1551-39 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 138375#L1551-41 havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 138373#L1307-3 assume 1 == ~M_E~0;~M_E~0 := 2; 138371#L1307-5 assume !(1 == ~T1_E~0); 138369#L1312-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 119137#L1317-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 138366#L1322-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 138363#L1327-3 assume !(1 == ~T5_E~0); 138361#L1332-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 138359#L1337-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 138357#L1342-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 138355#L1347-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 138143#L1352-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 138351#L1357-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 138349#L1362-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 138347#L1367-3 assume !(1 == ~E_1~0); 138345#L1372-3 assume 1 == ~E_2~0;~E_2~0 := 2; 138343#L1377-3 assume 1 == ~E_3~0;~E_3~0 := 2; 138341#L1382-3 assume 1 == ~E_4~0;~E_4~0 := 2; 138338#L1387-3 assume 1 == ~E_5~0;~E_5~0 := 2; 118002#L1392-3 assume 1 == ~E_6~0;~E_6~0 := 2; 138335#L1397-3 assume 1 == ~E_7~0;~E_7~0 := 2; 138333#L1402-3 assume 1 == ~E_8~0;~E_8~0 := 2; 138331#L1407-3 assume !(1 == ~E_9~0); 138329#L1412-3 assume 1 == ~E_10~0;~E_10~0 := 2; 138326#L1417-3 assume 1 == ~E_11~0;~E_11~0 := 2; 138324#L1422-3 assume 1 == ~E_12~0;~E_12~0 := 2; 138322#L1427-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 138063#L894-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 138056#L961-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 138055#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret32#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret32#1;havoc start_simulation_#t~ret32#1; 138053#L1787 assume !(0 == start_simulation_~tmp~3#1); 136769#L1787-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret31#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 136433#L894-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 136419#L961-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 136384#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret31#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret31#1;havoc stop_simulation_#t~ret31#1; 136374#L1742 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 136373#L1749 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 136362#stop_simulation_returnLabel#1 start_simulation_#t~ret33#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret31#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret33#1;havoc start_simulation_#t~ret33#1; 136345#L1800 assume !(0 != start_simulation_~tmp___0~1#1); 136335#L1768-2 [2023-11-12 02:13:48,692 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-12 02:13:48,693 INFO L85 PathProgramCache]: Analyzing trace with hash 1220887001, now seen corresponding path program 1 times [2023-11-12 02:13:48,693 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-12 02:13:48,693 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [565270725] [2023-11-12 02:13:48,693 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-12 02:13:48,694 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-12 02:13:48,710 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-12 02:13:48,783 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-12 02:13:48,783 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-12 02:13:48,783 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [565270725] [2023-11-12 02:13:48,784 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [565270725] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-12 02:13:48,784 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-12 02:13:48,784 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2023-11-12 02:13:48,784 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [223495175] [2023-11-12 02:13:48,784 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-12 02:13:48,785 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-12 02:13:48,785 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-12 02:13:48,785 INFO L85 PathProgramCache]: Analyzing trace with hash -172509439, now seen corresponding path program 1 times [2023-11-12 02:13:48,786 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-12 02:13:48,786 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [588542378] [2023-11-12 02:13:48,786 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-12 02:13:48,786 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-12 02:13:48,805 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-12 02:13:48,852 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-12 02:13:48,852 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-12 02:13:48,852 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [588542378] [2023-11-12 02:13:48,852 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [588542378] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-12 02:13:48,853 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-12 02:13:48,853 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-12 02:13:48,853 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [68466465] [2023-11-12 02:13:48,853 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-12 02:13:48,854 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-12 02:13:48,854 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-12 02:13:48,854 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2023-11-12 02:13:48,854 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2023-11-12 02:13:48,855 INFO L87 Difference]: Start difference. First operand 22382 states and 32496 transitions. cyclomatic complexity: 10122 Second operand has 5 states, 5 states have (on average 29.6) internal successors, (148), 5 states have internal predecessors, (148), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-12 02:13:49,749 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-12 02:13:49,749 INFO L93 Difference]: Finished difference Result 58376 states and 84006 transitions. [2023-11-12 02:13:49,749 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 58376 states and 84006 transitions. [2023-11-12 02:13:50,270 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 57936 [2023-11-12 02:13:50,552 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 58376 states to 58376 states and 84006 transitions. [2023-11-12 02:13:50,552 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 58376 [2023-11-12 02:13:50,763 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 58376 [2023-11-12 02:13:50,763 INFO L73 IsDeterministic]: Start isDeterministic. Operand 58376 states and 84006 transitions. [2023-11-12 02:13:50,804 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-12 02:13:50,804 INFO L218 hiAutomatonCegarLoop]: Abstraction has 58376 states and 84006 transitions. [2023-11-12 02:13:50,854 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 58376 states and 84006 transitions. [2023-11-12 02:13:51,327 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 58376 to 22985. [2023-11-12 02:13:51,352 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 22985 states, 22985 states have (on average 1.440026103980857) internal successors, (33099), 22984 states have internal predecessors, (33099), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-12 02:13:51,404 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 22985 states to 22985 states and 33099 transitions. [2023-11-12 02:13:51,404 INFO L240 hiAutomatonCegarLoop]: Abstraction has 22985 states and 33099 transitions. [2023-11-12 02:13:51,405 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2023-11-12 02:13:51,405 INFO L428 stractBuchiCegarLoop]: Abstraction has 22985 states and 33099 transitions. [2023-11-12 02:13:51,405 INFO L335 stractBuchiCegarLoop]: ======== Iteration 19 ============ [2023-11-12 02:13:51,405 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 22985 states and 33099 transitions. [2023-11-12 02:13:51,474 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 22768 [2023-11-12 02:13:51,474 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-12 02:13:51,474 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-12 02:13:51,477 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-12 02:13:51,477 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-12 02:13:51,478 INFO L748 eck$LassoCheckResult]: Stem: 198377#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2; 198378#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~14#1;havoc main_~__retres1~14#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1; 199212#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret32#1, start_simulation_#t~ret33#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 199213#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 199061#L821 assume 1 == ~m_i~0;~m_st~0 := 0; 199062#L821-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 199167#L826-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 199513#L831-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 199691#L836-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 199692#L841-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 198353#L846-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 198354#L851-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 199598#L856-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 198954#L861-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 198955#L866-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 198863#L871-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 198864#L876-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 199297#L881-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 198596#L1174 assume !(0 == ~M_E~0); 198597#L1174-2 assume !(0 == ~T1_E~0); 198446#L1179-1 assume !(0 == ~T2_E~0); 198350#L1184-1 assume !(0 == ~T3_E~0); 198351#L1189-1 assume !(0 == ~T4_E~0); 198394#L1194-1 assume !(0 == ~T5_E~0); 198489#L1199-1 assume !(0 == ~T6_E~0); 199437#L1204-1 assume !(0 == ~T7_E~0); 199347#L1209-1 assume !(0 == ~T8_E~0); 199348#L1214-1 assume !(0 == ~T9_E~0); 199883#L1219-1 assume !(0 == ~T10_E~0); 200063#L1224-1 assume !(0 == ~T11_E~0); 198719#L1229-1 assume !(0 == ~T12_E~0); 198280#L1234-1 assume !(0 == ~E_1~0); 198281#L1239-1 assume !(0 == ~E_2~0); 198313#L1244-1 assume !(0 == ~E_3~0); 198314#L1249-1 assume !(0 == ~E_4~0); 198974#L1254-1 assume !(0 == ~E_5~0); 198213#L1259-1 assume !(0 == ~E_6~0); 198168#L1264-1 assume !(0 == ~E_7~0); 198169#L1269-1 assume !(0 == ~E_8~0); 200079#L1274-1 assume !(0 == ~E_9~0); 199935#L1279-1 assume !(0 == ~E_10~0); 198397#L1284-1 assume !(0 == ~E_11~0); 198398#L1289-1 assume !(0 == ~E_12~0); 199031#L1294-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 199032#L566 assume !(1 == ~m_pc~0); 199508#L566-2 is_master_triggered_~__retres1~0#1 := 0; 199509#L577 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 199079#is_master_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 199080#L1455 assume !(0 != activate_threads_~tmp~1#1); 198623#L1455-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 198624#L585 assume !(1 == ~t1_pc~0); 198808#L585-2 is_transmit1_triggered_~__retres1~1#1 := 0; 198809#L596 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 199499#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 199500#L1463 assume !(0 != activate_threads_~tmp___0~0#1); 199990#L1463-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 199985#L604 assume !(1 == ~t2_pc~0); 199395#L604-2 is_transmit2_triggered_~__retres1~2#1 := 0; 199396#L615 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 199955#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 199849#L1471 assume !(0 != activate_threads_~tmp___1~0#1); 199646#L1471-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 199647#L623 assume 1 == ~t3_pc~0; 198807#L624 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 198144#L634 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 199472#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 199473#L1479 assume !(0 != activate_threads_~tmp___2~0#1); 199684#L1479-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 198182#L642 assume !(1 == ~t4_pc~0); 198183#L642-2 is_transmit4_triggered_~__retres1~4#1 := 0; 198636#L653 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 198235#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 198236#L1487 assume !(0 != activate_threads_~tmp___3~0#1); 198257#L1487-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 199410#L661 assume 1 == ~t5_pc~0; 198412#L662 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 198413#L672 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 199314#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 199774#L1495 assume !(0 != activate_threads_~tmp___4~0#1); 199445#L1495-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 199446#L680 assume !(1 == ~t6_pc~0); 198842#L680-2 is_transmit6_triggered_~__retres1~6#1 := 0; 198843#L691 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 198557#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 198558#L1503 assume !(0 != activate_threads_~tmp___5~0#1); 199787#L1503-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 199982#L699 assume 1 == ~t7_pc~0; 199272#L700 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 199273#L710 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 199541#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 199147#L1511 assume !(0 != activate_threads_~tmp___6~0#1); 199148#L1511-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 199033#L718 assume !(1 == ~t8_pc~0); 199034#L718-2 is_transmit8_triggered_~__retres1~8#1 := 0; 198392#L729 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 198393#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 198428#L1519 assume !(0 != activate_threads_~tmp___7~0#1); 198429#L1519-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 198563#L737 assume 1 == ~t9_pc~0; 199488#L738 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 198701#L748 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 198603#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 198604#L1527 assume !(0 != activate_threads_~tmp___8~0#1); 198883#L1527-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 198884#L756 assume 1 == ~t10_pc~0; 199531#L757 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 199138#L767 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 199432#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 199068#L1535 assume !(0 != activate_threads_~tmp___9~0#1); 198677#L1535-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 198678#L775 assume !(1 == ~t11_pc~0); 198946#L775-2 is_transmit11_triggered_~__retres1~11#1 := 0; 198947#L786 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 199876#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 198325#L1543 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 198326#L1543-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 198510#L794 assume 1 == ~t12_pc~0; 198348#L795 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 198328#L805 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 198185#is_transmit12_triggered_returnLabel#1 activate_threads_#t~ret30#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 198186#L1551 assume !(0 != activate_threads_~tmp___11~0#1); 198474#L1551-2 havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 198959#L1307 assume !(1 == ~M_E~0); 198960#L1307-2 assume !(1 == ~T1_E~0); 199073#L1312-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 200022#L1317-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 204892#L1322-1 assume !(1 == ~T4_E~0); 204891#L1327-1 assume !(1 == ~T5_E~0); 204890#L1332-1 assume !(1 == ~T6_E~0); 204889#L1337-1 assume !(1 == ~T7_E~0); 204888#L1342-1 assume !(1 == ~T8_E~0); 204887#L1347-1 assume !(1 == ~T9_E~0); 204885#L1352-1 assume !(1 == ~T10_E~0); 204883#L1357-1 assume 1 == ~T11_E~0;~T11_E~0 := 2; 198861#L1362-1 assume !(1 == ~T12_E~0); 198862#L1367-1 assume !(1 == ~E_1~0); 198490#L1372-1 assume !(1 == ~E_2~0); 198491#L1377-1 assume !(1 == ~E_3~0); 198792#L1382-1 assume !(1 == ~E_4~0); 198793#L1387-1 assume !(1 == ~E_5~0); 204742#L1392-1 assume !(1 == ~E_6~0); 204738#L1397-1 assume 1 == ~E_7~0;~E_7~0 := 2; 204737#L1402-1 assume !(1 == ~E_8~0); 204735#L1407-1 assume !(1 == ~E_9~0); 204715#L1412-1 assume !(1 == ~E_10~0); 204633#L1417-1 assume !(1 == ~E_11~0); 204611#L1422-1 assume !(1 == ~E_12~0); 204593#L1427-1 assume { :end_inline_reset_delta_events } true; 204578#L1768-2 [2023-11-12 02:13:51,479 INFO L750 eck$LassoCheckResult]: Loop: 204578#L1768-2 assume !false; 204565#L1769 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 204555#L1149-1 assume !false; 204548#L972 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 204527#L894 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 204520#L961 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 204518#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 204513#L976 assume !(0 != eval_~tmp~0#1); 204511#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 204512#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 204507#L1174-3 assume 0 == ~M_E~0;~M_E~0 := 1; 204508#L1174-5 assume !(0 == ~T1_E~0); 204502#L1179-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 204500#L1184-3 assume !(0 == ~T3_E~0); 204498#L1189-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 204497#L1194-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 204494#L1199-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 204492#L1204-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 204490#L1209-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 204488#L1214-3 assume !(0 == ~T9_E~0); 204486#L1219-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 204484#L1224-3 assume !(0 == ~T11_E~0); 204481#L1229-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 204479#L1234-3 assume 0 == ~E_1~0;~E_1~0 := 1; 204477#L1239-3 assume 0 == ~E_2~0;~E_2~0 := 1; 204475#L1244-3 assume 0 == ~E_3~0;~E_3~0 := 1; 204473#L1249-3 assume 0 == ~E_4~0;~E_4~0 := 1; 204471#L1254-3 assume !(0 == ~E_5~0); 204468#L1259-3 assume 0 == ~E_6~0;~E_6~0 := 1; 204466#L1264-3 assume !(0 == ~E_7~0); 204464#L1269-3 assume 0 == ~E_8~0;~E_8~0 := 1; 204455#L1274-3 assume 0 == ~E_9~0;~E_9~0 := 1; 199933#L1279-3 assume 0 == ~E_10~0;~E_10~0 := 1; 198893#L1284-3 assume 0 == ~E_11~0;~E_11~0 := 1; 198894#L1289-3 assume 0 == ~E_12~0;~E_12~0 := 1; 211665#L1294-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 211664#L566-39 assume !(1 == ~m_pc~0); 211663#L566-41 is_master_triggered_~__retres1~0#1 := 0; 211662#L577-13 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 211661#is_master_triggered_returnLabel#14 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 211660#L1455-39 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 211602#L1455-41 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 209360#L585-39 assume !(1 == ~t1_pc~0); 209359#L585-41 is_transmit1_triggered_~__retres1~1#1 := 0; 209358#L596-13 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 209357#is_transmit1_triggered_returnLabel#14 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 209356#L1463-39 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 209355#L1463-41 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 203914#L604-39 assume 1 == ~t2_pc~0; 203915#L605-13 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 203906#L615-13 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 203907#is_transmit2_triggered_returnLabel#14 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 203900#L1471-39 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 203898#L1471-41 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 203895#L623-39 assume 1 == ~t3_pc~0; 203893#L624-13 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 203890#L634-13 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 203883#is_transmit3_triggered_returnLabel#14 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 203878#L1479-39 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 203872#L1479-41 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 203866#L642-39 assume !(1 == ~t4_pc~0); 203861#L642-41 is_transmit4_triggered_~__retres1~4#1 := 0; 203855#L653-13 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 203848#is_transmit4_triggered_returnLabel#14 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 203842#L1487-39 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 203835#L1487-41 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 203829#L661-39 assume 1 == ~t5_pc~0; 203824#L662-13 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 203818#L672-13 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 203810#is_transmit5_triggered_returnLabel#14 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 203804#L1495-39 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 203764#L1495-41 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 203758#L680-39 assume 1 == ~t6_pc~0; 203751#L681-13 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 203749#L691-13 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 203747#is_transmit6_triggered_returnLabel#14 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 203745#L1503-39 assume !(0 != activate_threads_~tmp___5~0#1); 203743#L1503-41 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 203740#L699-39 assume !(1 == ~t7_pc~0); 203738#L699-41 is_transmit7_triggered_~__retres1~7#1 := 0; 203735#L710-13 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 203733#is_transmit7_triggered_returnLabel#14 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 203731#L1511-39 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 203729#L1511-41 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 203726#L718-39 assume 1 == ~t8_pc~0; 203723#L719-13 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 203722#L729-13 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 203721#is_transmit8_triggered_returnLabel#14 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 203719#L1519-39 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 203720#L1519-41 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 206599#L737-39 assume !(1 == ~t9_pc~0); 206571#L737-41 is_transmit9_triggered_~__retres1~9#1 := 0; 206568#L748-13 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 206566#is_transmit9_triggered_returnLabel#14 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 206564#L1527-39 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 206562#L1527-41 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 206560#L756-39 assume 1 == ~t10_pc~0; 206557#L757-13 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 206554#L767-13 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 206553#is_transmit10_triggered_returnLabel#14 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 206551#L1535-39 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 206549#L1535-41 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 206548#L775-39 assume !(1 == ~t11_pc~0); 206510#L775-41 is_transmit11_triggered_~__retres1~11#1 := 0; 206507#L786-13 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 206505#is_transmit11_triggered_returnLabel#14 activate_threads_#t~ret29#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 206503#L1543-39 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 206501#L1543-41 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 206500#L794-39 assume !(1 == ~t12_pc~0); 206451#L794-41 is_transmit12_triggered_~__retres1~12#1 := 0; 206448#L805-13 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 206446#is_transmit12_triggered_returnLabel#14 activate_threads_#t~ret30#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 206444#L1551-39 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 206442#L1551-41 havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 206441#L1307-3 assume 1 == ~M_E~0;~M_E~0 := 2; 206440#L1307-5 assume !(1 == ~T1_E~0); 206439#L1312-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 200858#L1317-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 206438#L1322-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 206437#L1327-3 assume !(1 == ~T5_E~0); 206436#L1332-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 206434#L1337-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 206432#L1342-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 206430#L1347-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 205887#L1352-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 206428#L1357-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 206426#L1362-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 206424#L1367-3 assume !(1 == ~E_1~0); 206422#L1372-3 assume 1 == ~E_2~0;~E_2~0 := 2; 206420#L1377-3 assume 1 == ~E_3~0;~E_3~0 := 2; 206418#L1382-3 assume 1 == ~E_4~0;~E_4~0 := 2; 206416#L1387-3 assume 1 == ~E_5~0;~E_5~0 := 2; 200826#L1392-3 assume 1 == ~E_6~0;~E_6~0 := 2; 206414#L1397-3 assume 1 == ~E_7~0;~E_7~0 := 2; 206412#L1402-3 assume 1 == ~E_8~0;~E_8~0 := 2; 206410#L1407-3 assume !(1 == ~E_9~0); 206408#L1412-3 assume 1 == ~E_10~0;~E_10~0 := 2; 206406#L1417-3 assume 1 == ~E_11~0;~E_11~0 := 2; 206404#L1422-3 assume 1 == ~E_12~0;~E_12~0 := 2; 206402#L1427-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 206391#L894-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 206384#L961-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 206382#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret32#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret32#1;havoc start_simulation_#t~ret32#1; 206380#L1787 assume !(0 == start_simulation_~tmp~3#1); 206378#L1787-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret31#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 206377#L894-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 206364#L961-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 206361#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret31#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret31#1;havoc stop_simulation_#t~ret31#1; 204910#L1742 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 204634#L1749 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 204612#stop_simulation_returnLabel#1 start_simulation_#t~ret33#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret31#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret33#1;havoc start_simulation_#t~ret33#1; 204594#L1800 assume !(0 != start_simulation_~tmp___0~1#1); 204578#L1768-2 [2023-11-12 02:13:51,480 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-12 02:13:51,480 INFO L85 PathProgramCache]: Analyzing trace with hash 226193303, now seen corresponding path program 1 times [2023-11-12 02:13:51,481 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-12 02:13:51,481 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1067583161] [2023-11-12 02:13:51,481 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-12 02:13:51,481 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-12 02:13:51,500 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-12 02:13:51,578 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-12 02:13:51,579 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-12 02:13:51,579 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1067583161] [2023-11-12 02:13:51,579 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1067583161] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-12 02:13:51,579 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-12 02:13:51,580 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-12 02:13:51,580 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [328612158] [2023-11-12 02:13:51,580 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-12 02:13:51,580 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-12 02:13:51,581 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-12 02:13:51,581 INFO L85 PathProgramCache]: Analyzing trace with hash -1969732640, now seen corresponding path program 1 times [2023-11-12 02:13:51,581 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-12 02:13:51,581 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1418053670] [2023-11-12 02:13:51,582 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-12 02:13:51,582 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-12 02:13:51,599 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-12 02:13:51,644 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-12 02:13:51,644 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-12 02:13:51,645 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1418053670] [2023-11-12 02:13:51,645 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1418053670] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-12 02:13:51,645 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-12 02:13:51,645 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-12 02:13:51,645 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [716927344] [2023-11-12 02:13:51,645 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-12 02:13:51,646 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-12 02:13:51,646 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-12 02:13:51,646 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2023-11-12 02:13:51,647 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2023-11-12 02:13:51,647 INFO L87 Difference]: Start difference. First operand 22985 states and 33099 transitions. cyclomatic complexity: 10122 Second operand has 4 states, 4 states have (on average 37.0) internal successors, (148), 3 states have internal predecessors, (148), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-12 02:13:52,290 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-12 02:13:52,290 INFO L93 Difference]: Finished difference Result 55990 states and 80100 transitions. [2023-11-12 02:13:52,291 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 55990 states and 80100 transitions. [2023-11-12 02:13:52,516 INFO L131 ngComponentsAnalysis]: Automaton has 12 accepting balls. 54954 [2023-11-12 02:13:52,884 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 55990 states to 55990 states and 80100 transitions. [2023-11-12 02:13:52,884 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 55990 [2023-11-12 02:13:52,913 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 55990 [2023-11-12 02:13:52,914 INFO L73 IsDeterministic]: Start isDeterministic. Operand 55990 states and 80100 transitions. [2023-11-12 02:13:52,962 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-12 02:13:52,962 INFO L218 hiAutomatonCegarLoop]: Abstraction has 55990 states and 80100 transitions. [2023-11-12 02:13:52,998 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 55990 states and 80100 transitions. [2023-11-12 02:13:53,585 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 55990 to 44008. [2023-11-12 02:13:53,629 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 44008 states, 44008 states have (on average 1.4345573532085076) internal successors, (63132), 44007 states have internal predecessors, (63132), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-12 02:13:53,717 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 44008 states to 44008 states and 63132 transitions. [2023-11-12 02:13:53,717 INFO L240 hiAutomatonCegarLoop]: Abstraction has 44008 states and 63132 transitions. [2023-11-12 02:13:53,717 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2023-11-12 02:13:53,718 INFO L428 stractBuchiCegarLoop]: Abstraction has 44008 states and 63132 transitions. [2023-11-12 02:13:53,719 INFO L335 stractBuchiCegarLoop]: ======== Iteration 20 ============ [2023-11-12 02:13:53,719 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 44008 states and 63132 transitions. [2023-11-12 02:13:53,849 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 43784 [2023-11-12 02:13:53,849 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-12 02:13:53,849 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-12 02:13:53,853 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-12 02:13:53,853 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-12 02:13:53,854 INFO L748 eck$LassoCheckResult]: Stem: 277359#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2; 277360#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~14#1;havoc main_~__retres1~14#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1; 278187#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret32#1, start_simulation_#t~ret33#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 278188#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 278043#L821 assume 1 == ~m_i~0;~m_st~0 := 0; 278044#L821-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 278145#L826-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 278483#L831-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 278641#L836-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 278642#L841-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 277335#L846-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 277336#L851-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 278556#L856-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 277935#L861-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 277936#L866-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 277847#L871-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 277848#L876-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 278272#L881-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 277578#L1174 assume !(0 == ~M_E~0); 277579#L1174-2 assume !(0 == ~T1_E~0); 277430#L1179-1 assume !(0 == ~T2_E~0); 277332#L1184-1 assume !(0 == ~T3_E~0); 277333#L1189-1 assume !(0 == ~T4_E~0); 277376#L1194-1 assume !(0 == ~T5_E~0); 277474#L1199-1 assume !(0 == ~T6_E~0); 278410#L1204-1 assume !(0 == ~T7_E~0); 278323#L1209-1 assume !(0 == ~T8_E~0); 278324#L1214-1 assume !(0 == ~T9_E~0); 278816#L1219-1 assume !(0 == ~T10_E~0); 278948#L1224-1 assume !(0 == ~T11_E~0); 277702#L1229-1 assume !(0 == ~T12_E~0); 277263#L1234-1 assume !(0 == ~E_1~0); 277264#L1239-1 assume !(0 == ~E_2~0); 277298#L1244-1 assume !(0 == ~E_3~0); 277299#L1249-1 assume !(0 == ~E_4~0); 277956#L1254-1 assume !(0 == ~E_5~0); 277196#L1259-1 assume !(0 == ~E_6~0); 277152#L1264-1 assume !(0 == ~E_7~0); 277153#L1269-1 assume !(0 == ~E_8~0); 278960#L1274-1 assume !(0 == ~E_9~0); 278854#L1279-1 assume !(0 == ~E_10~0); 277379#L1284-1 assume !(0 == ~E_11~0); 277380#L1289-1 assume !(0 == ~E_12~0); 278013#L1294-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 278014#L566 assume !(1 == ~m_pc~0); 278477#L566-2 is_master_triggered_~__retres1~0#1 := 0; 278478#L577 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 278061#is_master_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 278062#L1455 assume !(0 != activate_threads_~tmp~1#1); 277605#L1455-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 277606#L585 assume !(1 == ~t1_pc~0); 277791#L585-2 is_transmit1_triggered_~__retres1~1#1 := 0; 277792#L596 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 278469#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 278470#L1463 assume !(0 != activate_threads_~tmp___0~0#1); 278892#L1463-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 278888#L604 assume !(1 == ~t2_pc~0); 278368#L604-2 is_transmit2_triggered_~__retres1~2#1 := 0; 278369#L615 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 277553#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 277554#L1471 assume !(0 != activate_threads_~tmp___1~0#1); 278598#L1471-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 278599#L623 assume !(1 == ~t3_pc~0); 277127#L623-2 is_transmit3_triggered_~__retres1~3#1 := 0; 277128#L634 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 278447#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 278448#L1479 assume !(0 != activate_threads_~tmp___2~0#1); 278634#L1479-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 277166#L642 assume !(1 == ~t4_pc~0); 277167#L642-2 is_transmit4_triggered_~__retres1~4#1 := 0; 277618#L653 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 277221#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 277222#L1487 assume !(0 != activate_threads_~tmp___3~0#1); 277240#L1487-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 278384#L661 assume 1 == ~t5_pc~0; 277394#L662 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 277395#L672 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 278289#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 278715#L1495 assume !(0 != activate_threads_~tmp___4~0#1); 278419#L1495-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 278420#L680 assume !(1 == ~t6_pc~0); 277826#L680-2 is_transmit6_triggered_~__retres1~6#1 := 0; 277827#L691 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 277539#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 277540#L1503 assume !(0 != activate_threads_~tmp___5~0#1); 278725#L1503-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 278885#L699 assume 1 == ~t7_pc~0; 278250#L700 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 278251#L710 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 278505#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 278127#L1511 assume !(0 != activate_threads_~tmp___6~0#1); 278128#L1511-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 278015#L718 assume !(1 == ~t8_pc~0); 278016#L718-2 is_transmit8_triggered_~__retres1~8#1 := 0; 277374#L729 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 277375#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 277410#L1519 assume !(0 != activate_threads_~tmp___7~0#1); 277411#L1519-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 277545#L737 assume 1 == ~t9_pc~0; 278460#L738 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 277684#L748 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 277585#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 277586#L1527 assume !(0 != activate_threads_~tmp___8~0#1); 277867#L1527-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 277868#L756 assume 1 == ~t10_pc~0; 278495#L757 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 278117#L767 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 278405#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 278054#L1535 assume !(0 != activate_threads_~tmp___9~0#1); 277662#L1535-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 277663#L775 assume !(1 == ~t11_pc~0); 277927#L775-2 is_transmit11_triggered_~__retres1~11#1 := 0; 277928#L786 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 278807#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 277308#L1543 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 277309#L1543-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 277492#L794 assume 1 == ~t12_pc~0; 277331#L795 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 277311#L805 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 277172#is_transmit12_triggered_returnLabel#1 activate_threads_#t~ret30#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 277173#L1551 assume !(0 != activate_threads_~tmp___11~0#1); 277459#L1551-2 havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 277939#L1307 assume !(1 == ~M_E~0); 277940#L1307-2 assume !(1 == ~T1_E~0); 278058#L1312-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 277970#L1317-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 277971#L1322-1 assume !(1 == ~T4_E~0); 277674#L1327-1 assume !(1 == ~T5_E~0); 277675#L1332-1 assume !(1 == ~T6_E~0); 278901#L1337-1 assume !(1 == ~T7_E~0); 278902#L1342-1 assume !(1 == ~T8_E~0); 278852#L1347-1 assume !(1 == ~T9_E~0); 278675#L1352-1 assume !(1 == ~T10_E~0); 278676#L1357-1 assume 1 == ~T11_E~0;~T11_E~0 := 2; 277845#L1362-1 assume !(1 == ~T12_E~0); 277846#L1367-1 assume !(1 == ~E_1~0); 277475#L1372-1 assume !(1 == ~E_2~0); 277476#L1377-1 assume !(1 == ~E_3~0); 277776#L1382-1 assume !(1 == ~E_4~0); 277777#L1387-1 assume !(1 == ~E_5~0); 278371#L1392-1 assume !(1 == ~E_6~0); 316495#L1397-1 assume 1 == ~E_7~0;~E_7~0 := 2; 316481#L1402-1 assume !(1 == ~E_8~0); 316479#L1407-1 assume !(1 == ~E_9~0); 316477#L1412-1 assume !(1 == ~E_10~0); 316475#L1417-1 assume !(1 == ~E_11~0); 316473#L1422-1 assume !(1 == ~E_12~0); 316467#L1427-1 assume { :end_inline_reset_delta_events } true; 316465#L1768-2 [2023-11-12 02:13:53,854 INFO L750 eck$LassoCheckResult]: Loop: 316465#L1768-2 assume !false; 316463#L1769 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 316458#L1149-1 assume !false; 316456#L972 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 316431#L894 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 316424#L961 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 316422#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 316419#L976 assume !(0 != eval_~tmp~0#1); 316420#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 319627#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 319626#L1174-3 assume 0 == ~M_E~0;~M_E~0 := 1; 319624#L1174-5 assume !(0 == ~T1_E~0); 319623#L1179-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 319622#L1184-3 assume !(0 == ~T3_E~0); 319621#L1189-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 319619#L1194-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 319617#L1199-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 319615#L1204-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 319613#L1209-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 319611#L1214-3 assume !(0 == ~T9_E~0); 319609#L1219-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 319607#L1224-3 assume !(0 == ~T11_E~0); 319606#L1229-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 319604#L1234-3 assume 0 == ~E_1~0;~E_1~0 := 1; 319602#L1239-3 assume 0 == ~E_2~0;~E_2~0 := 1; 319600#L1244-3 assume 0 == ~E_3~0;~E_3~0 := 1; 319598#L1249-3 assume 0 == ~E_4~0;~E_4~0 := 1; 319594#L1254-3 assume !(0 == ~E_5~0); 319592#L1259-3 assume 0 == ~E_6~0;~E_6~0 := 1; 319590#L1264-3 assume !(0 == ~E_7~0); 319588#L1269-3 assume 0 == ~E_8~0;~E_8~0 := 1; 318789#L1274-3 assume 0 == ~E_9~0;~E_9~0 := 1; 318788#L1279-3 assume 0 == ~E_10~0;~E_10~0 := 1; 318787#L1284-3 assume 0 == ~E_11~0;~E_11~0 := 1; 318786#L1289-3 assume 0 == ~E_12~0;~E_12~0 := 1; 318785#L1294-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 318784#L566-39 assume !(1 == ~m_pc~0); 318783#L566-41 is_master_triggered_~__retres1~0#1 := 0; 318782#L577-13 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 318781#is_master_triggered_returnLabel#14 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 318780#L1455-39 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 318778#L1455-41 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 318776#L585-39 assume !(1 == ~t1_pc~0); 315847#L585-41 is_transmit1_triggered_~__retres1~1#1 := 0; 318773#L596-13 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 318771#is_transmit1_triggered_returnLabel#14 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 318769#L1463-39 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 318765#L1463-41 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 317716#L604-39 assume !(1 == ~t2_pc~0); 317712#L604-41 is_transmit2_triggered_~__retres1~2#1 := 0; 317710#L615-13 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 317708#is_transmit2_triggered_returnLabel#14 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 317706#L1471-39 assume !(0 != activate_threads_~tmp___1~0#1); 317703#L1471-41 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 317700#L623-39 assume !(1 == ~t3_pc~0); 295146#L623-41 is_transmit3_triggered_~__retres1~3#1 := 0; 317697#L634-13 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 317695#is_transmit3_triggered_returnLabel#14 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 317693#L1479-39 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 317691#L1479-41 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 317688#L642-39 assume 1 == ~t4_pc~0; 317685#L643-13 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 317683#L653-13 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 317681#is_transmit4_triggered_returnLabel#14 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 317679#L1487-39 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 317677#L1487-41 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 317674#L661-39 assume !(1 == ~t5_pc~0); 317671#L661-41 is_transmit5_triggered_~__retres1~5#1 := 0; 317669#L672-13 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 317667#is_transmit5_triggered_returnLabel#14 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 317665#L1495-39 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 317663#L1495-41 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 317660#L680-39 assume 1 == ~t6_pc~0; 317657#L681-13 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 317655#L691-13 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 317653#is_transmit6_triggered_returnLabel#14 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 317651#L1503-39 assume !(0 != activate_threads_~tmp___5~0#1); 317649#L1503-41 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 317646#L699-39 assume !(1 == ~t7_pc~0); 317644#L699-41 is_transmit7_triggered_~__retres1~7#1 := 0; 317641#L710-13 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 317639#is_transmit7_triggered_returnLabel#14 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 317637#L1511-39 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 317635#L1511-41 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 317632#L718-39 assume 1 == ~t8_pc~0; 317629#L719-13 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 317627#L729-13 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 317625#is_transmit8_triggered_returnLabel#14 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 317623#L1519-39 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 317621#L1519-41 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 317618#L737-39 assume !(1 == ~t9_pc~0); 317616#L737-41 is_transmit9_triggered_~__retres1~9#1 := 0; 317613#L748-13 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 317611#is_transmit9_triggered_returnLabel#14 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 317609#L1527-39 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 317607#L1527-41 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 317604#L756-39 assume !(1 == ~t10_pc~0); 317601#L756-41 is_transmit10_triggered_~__retres1~10#1 := 0; 317599#L767-13 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 317597#is_transmit10_triggered_returnLabel#14 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 317595#L1535-39 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 317593#L1535-41 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 317591#L775-39 assume 1 == ~t11_pc~0; 317588#L776-13 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 317586#L786-13 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 317584#is_transmit11_triggered_returnLabel#14 activate_threads_#t~ret29#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 317582#L1543-39 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 317580#L1543-41 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 317578#L794-39 assume !(1 == ~t12_pc~0); 317575#L794-41 is_transmit12_triggered_~__retres1~12#1 := 0; 317574#L805-13 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 317573#is_transmit12_triggered_returnLabel#14 activate_threads_#t~ret30#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 317571#L1551-39 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 317569#L1551-41 havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 317567#L1307-3 assume 1 == ~M_E~0;~M_E~0 := 2; 317565#L1307-5 assume !(1 == ~T1_E~0); 317563#L1312-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 278959#L1317-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 317560#L1322-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 317559#L1327-3 assume !(1 == ~T5_E~0); 317557#L1332-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 317555#L1337-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 317553#L1342-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 317551#L1347-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 317546#L1352-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 317544#L1357-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 317542#L1362-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 317540#L1367-3 assume !(1 == ~E_1~0); 317537#L1372-3 assume 1 == ~E_2~0;~E_2~0 := 2; 317535#L1377-3 assume 1 == ~E_3~0;~E_3~0 := 2; 317533#L1382-3 assume 1 == ~E_4~0;~E_4~0 := 2; 317532#L1387-3 assume 1 == ~E_5~0;~E_5~0 := 2; 317529#L1392-3 assume 1 == ~E_6~0;~E_6~0 := 2; 317527#L1397-3 assume 1 == ~E_7~0;~E_7~0 := 2; 317317#L1402-3 assume 1 == ~E_8~0;~E_8~0 := 2; 316712#L1407-3 assume !(1 == ~E_9~0); 316661#L1412-3 assume 1 == ~E_10~0;~E_10~0 := 2; 316644#L1417-3 assume 1 == ~E_11~0;~E_11~0 := 2; 316634#L1422-3 assume 1 == ~E_12~0;~E_12~0 := 2; 316625#L1427-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 316603#L894-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 316596#L961-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 316594#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret32#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret32#1;havoc start_simulation_#t~ret32#1; 316499#L1787 assume !(0 == start_simulation_~tmp~3#1); 316496#L1787-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret31#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 316494#L894-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 316480#L961-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 316478#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret31#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret31#1;havoc stop_simulation_#t~ret31#1; 316476#L1742 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 316474#L1749 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 316472#stop_simulation_returnLabel#1 start_simulation_#t~ret33#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret31#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret33#1;havoc start_simulation_#t~ret33#1; 316468#L1800 assume !(0 != start_simulation_~tmp___0~1#1); 316465#L1768-2 [2023-11-12 02:13:53,855 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-12 02:13:53,855 INFO L85 PathProgramCache]: Analyzing trace with hash 1148113654, now seen corresponding path program 1 times [2023-11-12 02:13:53,855 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-12 02:13:53,856 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [693208596] [2023-11-12 02:13:53,856 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-12 02:13:53,856 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-12 02:13:53,874 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-12 02:13:53,930 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-12 02:13:53,930 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-12 02:13:53,930 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [693208596] [2023-11-12 02:13:53,930 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [693208596] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-12 02:13:53,931 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-12 02:13:53,931 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2023-11-12 02:13:53,931 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2062913128] [2023-11-12 02:13:53,931 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-12 02:13:53,932 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-12 02:13:53,932 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-12 02:13:53,932 INFO L85 PathProgramCache]: Analyzing trace with hash 1107450652, now seen corresponding path program 1 times [2023-11-12 02:13:53,932 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-12 02:13:53,932 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [819051276] [2023-11-12 02:13:53,933 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-12 02:13:53,933 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-12 02:13:53,950 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-12 02:13:54,181 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-12 02:13:54,182 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-12 02:13:54,182 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [819051276] [2023-11-12 02:13:54,182 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [819051276] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-12 02:13:54,182 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-12 02:13:54,182 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-12 02:13:54,182 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1622914908] [2023-11-12 02:13:54,182 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-12 02:13:54,183 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-12 02:13:54,183 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-12 02:13:54,183 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-12 02:13:54,183 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-12 02:13:54,183 INFO L87 Difference]: Start difference. First operand 44008 states and 63132 transitions. cyclomatic complexity: 19132 Second operand has 3 states, 3 states have (on average 49.333333333333336) internal successors, (148), 2 states have internal predecessors, (148), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-12 02:13:54,617 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-12 02:13:54,617 INFO L93 Difference]: Finished difference Result 84399 states and 120633 transitions. [2023-11-12 02:13:54,617 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 84399 states and 120633 transitions. [2023-11-12 02:13:55,142 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 84096 [2023-11-12 02:13:55,605 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 84399 states to 84399 states and 120633 transitions. [2023-11-12 02:13:55,606 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 84399 [2023-11-12 02:13:55,659 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 84399 [2023-11-12 02:13:55,659 INFO L73 IsDeterministic]: Start isDeterministic. Operand 84399 states and 120633 transitions. [2023-11-12 02:13:55,798 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-12 02:13:55,798 INFO L218 hiAutomatonCegarLoop]: Abstraction has 84399 states and 120633 transitions. [2023-11-12 02:13:55,861 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 84399 states and 120633 transitions. [2023-11-12 02:13:56,718 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 84399 to 84335. [2023-11-12 02:13:56,789 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 84335 states, 84335 states have (on average 1.4296436829311674) internal successors, (120569), 84334 states have internal predecessors, (120569), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-12 02:13:57,313 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 84335 states to 84335 states and 120569 transitions. [2023-11-12 02:13:57,313 INFO L240 hiAutomatonCegarLoop]: Abstraction has 84335 states and 120569 transitions. [2023-11-12 02:13:57,313 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-12 02:13:57,314 INFO L428 stractBuchiCegarLoop]: Abstraction has 84335 states and 120569 transitions. [2023-11-12 02:13:57,314 INFO L335 stractBuchiCegarLoop]: ======== Iteration 21 ============ [2023-11-12 02:13:57,314 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 84335 states and 120569 transitions. [2023-11-12 02:13:57,539 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 84032 [2023-11-12 02:13:57,539 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-12 02:13:57,539 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-12 02:13:57,543 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-12 02:13:57,543 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-12 02:13:57,544 INFO L748 eck$LassoCheckResult]: Stem: 405778#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2; 405779#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~14#1;havoc main_~__retres1~14#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1; 406613#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret32#1, start_simulation_#t~ret33#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 406614#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 406469#L821 assume 1 == ~m_i~0;~m_st~0 := 0; 406470#L821-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 406571#L826-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 406921#L831-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 407095#L836-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 407096#L841-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 405754#L846-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 405755#L851-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 407003#L856-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 406359#L861-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 406360#L866-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 406266#L871-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 406267#L876-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 406704#L881-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 405996#L1174 assume !(0 == ~M_E~0); 405997#L1174-2 assume !(0 == ~T1_E~0); 405847#L1179-1 assume !(0 == ~T2_E~0); 405749#L1184-1 assume !(0 == ~T3_E~0); 405750#L1189-1 assume !(0 == ~T4_E~0); 405795#L1194-1 assume !(0 == ~T5_E~0); 405888#L1199-1 assume !(0 == ~T6_E~0); 406849#L1204-1 assume !(0 == ~T7_E~0); 406758#L1209-1 assume !(0 == ~T8_E~0); 406759#L1214-1 assume !(0 == ~T9_E~0); 407278#L1219-1 assume !(0 == ~T10_E~0); 407441#L1224-1 assume !(0 == ~T11_E~0); 406120#L1229-1 assume !(0 == ~T12_E~0); 405679#L1234-1 assume !(0 == ~E_1~0); 405680#L1239-1 assume !(0 == ~E_2~0); 405714#L1244-1 assume !(0 == ~E_3~0); 405715#L1249-1 assume !(0 == ~E_4~0); 406380#L1254-1 assume !(0 == ~E_5~0); 405610#L1259-1 assume !(0 == ~E_6~0); 405566#L1264-1 assume !(0 == ~E_7~0); 405567#L1269-1 assume !(0 == ~E_8~0); 407454#L1274-1 assume !(0 == ~E_9~0); 407328#L1279-1 assume !(0 == ~E_10~0); 405798#L1284-1 assume !(0 == ~E_11~0); 405799#L1289-1 assume !(0 == ~E_12~0); 406437#L1294-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 406438#L566 assume !(1 == ~m_pc~0); 406916#L566-2 is_master_triggered_~__retres1~0#1 := 0; 406917#L577 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 406485#is_master_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 406486#L1455 assume !(0 != activate_threads_~tmp~1#1); 406023#L1455-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 406024#L585 assume !(1 == ~t1_pc~0); 406211#L585-2 is_transmit1_triggered_~__retres1~1#1 := 0; 406212#L596 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 406909#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 406910#L1463 assume !(0 != activate_threads_~tmp___0~0#1); 407375#L1463-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 407369#L604 assume !(1 == ~t2_pc~0); 406807#L604-2 is_transmit2_triggered_~__retres1~2#1 := 0; 406808#L615 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 405969#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 405970#L1471 assume !(0 != activate_threads_~tmp___1~0#1); 407044#L1471-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 407045#L623 assume !(1 == ~t3_pc~0); 405541#L623-2 is_transmit3_triggered_~__retres1~3#1 := 0; 405542#L634 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 406884#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 406885#L1479 assume !(0 != activate_threads_~tmp___2~0#1); 407088#L1479-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 405580#L642 assume !(1 == ~t4_pc~0); 405581#L642-2 is_transmit4_triggered_~__retres1~4#1 := 0; 406035#L653 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 405635#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 405636#L1487 assume !(0 != activate_threads_~tmp___3~0#1); 405656#L1487-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 406821#L661 assume !(1 == ~t5_pc~0); 407007#L661-2 is_transmit5_triggered_~__retres1~5#1 := 0; 406721#L672 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 406722#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 407170#L1495 assume !(0 != activate_threads_~tmp___4~0#1); 406859#L1495-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 406860#L680 assume !(1 == ~t6_pc~0); 406246#L680-2 is_transmit6_triggered_~__retres1~6#1 := 0; 406247#L691 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 405955#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 405956#L1503 assume !(0 != activate_threads_~tmp___5~0#1); 407183#L1503-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 407366#L699 assume 1 == ~t7_pc~0; 406680#L700 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 406681#L710 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 406948#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 406553#L1511 assume !(0 != activate_threads_~tmp___6~0#1); 406554#L1511-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 406439#L718 assume !(1 == ~t8_pc~0); 406440#L718-2 is_transmit8_triggered_~__retres1~8#1 := 0; 405793#L729 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 405794#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 405827#L1519 assume !(0 != activate_threads_~tmp___7~0#1); 405828#L1519-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 405961#L737 assume 1 == ~t9_pc~0; 406899#L738 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 406103#L748 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 406003#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 406004#L1527 assume !(0 != activate_threads_~tmp___8~0#1); 406288#L1527-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 406289#L756 assume 1 == ~t10_pc~0; 406937#L757 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 406543#L767 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 406844#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 406477#L1535 assume !(0 != activate_threads_~tmp___9~0#1); 406080#L1535-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 406081#L775 assume !(1 == ~t11_pc~0); 406351#L775-2 is_transmit11_triggered_~__retres1~11#1 := 0; 406352#L786 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 407270#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 405724#L1543 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 405725#L1543-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 405908#L794 assume 1 == ~t12_pc~0; 405748#L795 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 405727#L805 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 405586#is_transmit12_triggered_returnLabel#1 activate_threads_#t~ret30#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 405587#L1551 assume !(0 != activate_threads_~tmp___11~0#1); 405873#L1551-2 havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 406363#L1307 assume !(1 == ~M_E~0); 406364#L1307-2 assume !(1 == ~T1_E~0); 406482#L1312-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 407398#L1317-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 406633#L1322-1 assume !(1 == ~T4_E~0); 406634#L1327-1 assume !(1 == ~T5_E~0); 406685#L1332-1 assume !(1 == ~T6_E~0); 406686#L1337-1 assume !(1 == ~T7_E~0); 417566#L1342-1 assume !(1 == ~T8_E~0); 407325#L1347-1 assume !(1 == ~T9_E~0); 407326#L1352-1 assume !(1 == ~T10_E~0); 419352#L1357-1 assume 1 == ~T11_E~0;~T11_E~0 := 2; 419347#L1362-1 assume !(1 == ~T12_E~0); 419342#L1367-1 assume !(1 == ~E_1~0); 419336#L1372-1 assume !(1 == ~E_2~0); 406409#L1377-1 assume !(1 == ~E_3~0); 406196#L1382-1 assume !(1 == ~E_4~0); 406197#L1387-1 assume !(1 == ~E_5~0); 406809#L1392-1 assume !(1 == ~E_6~0); 422590#L1397-1 assume 1 == ~E_7~0;~E_7~0 := 2; 422588#L1402-1 assume !(1 == ~E_8~0); 422586#L1407-1 assume !(1 == ~E_9~0); 422584#L1412-1 assume !(1 == ~E_10~0); 422582#L1417-1 assume !(1 == ~E_11~0); 422579#L1422-1 assume !(1 == ~E_12~0); 422535#L1427-1 assume { :end_inline_reset_delta_events } true; 422533#L1768-2 [2023-11-12 02:13:57,545 INFO L750 eck$LassoCheckResult]: Loop: 422533#L1768-2 assume !false; 422531#L1769 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 422525#L1149-1 assume !false; 422523#L972 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 422476#L894 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 422467#L961 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 422463#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 422456#L976 assume !(0 != eval_~tmp~0#1); 422457#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 429921#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 429919#L1174-3 assume 0 == ~M_E~0;~M_E~0 := 1; 429917#L1174-5 assume !(0 == ~T1_E~0); 429915#L1179-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 429913#L1184-3 assume !(0 == ~T3_E~0); 429911#L1189-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 429909#L1194-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 429907#L1199-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 429906#L1204-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 429905#L1209-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 429903#L1214-3 assume !(0 == ~T9_E~0); 429901#L1219-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 429899#L1224-3 assume !(0 == ~T11_E~0); 429897#L1229-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 429895#L1234-3 assume 0 == ~E_1~0;~E_1~0 := 1; 429892#L1239-3 assume 0 == ~E_2~0;~E_2~0 := 1; 429890#L1244-3 assume 0 == ~E_3~0;~E_3~0 := 1; 429888#L1249-3 assume 0 == ~E_4~0;~E_4~0 := 1; 429885#L1254-3 assume !(0 == ~E_5~0); 429883#L1259-3 assume 0 == ~E_6~0;~E_6~0 := 1; 429881#L1264-3 assume !(0 == ~E_7~0); 429879#L1269-3 assume 0 == ~E_8~0;~E_8~0 := 1; 429877#L1274-3 assume 0 == ~E_9~0;~E_9~0 := 1; 429875#L1279-3 assume 0 == ~E_10~0;~E_10~0 := 1; 429872#L1284-3 assume 0 == ~E_11~0;~E_11~0 := 1; 429869#L1289-3 assume 0 == ~E_12~0;~E_12~0 := 1; 429865#L1294-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 429860#L566-39 assume !(1 == ~m_pc~0); 429855#L566-41 is_master_triggered_~__retres1~0#1 := 0; 429850#L577-13 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 429846#is_master_triggered_returnLabel#14 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 429064#L1455-39 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 429063#L1455-41 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 424477#L585-39 assume !(1 == ~t1_pc~0); 424475#L585-41 is_transmit1_triggered_~__retres1~1#1 := 0; 424473#L596-13 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 424471#is_transmit1_triggered_returnLabel#14 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 424469#L1463-39 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 424467#L1463-41 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 423799#L604-39 assume 1 == ~t2_pc~0; 423797#L605-13 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 423798#L615-13 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 423805#is_transmit2_triggered_returnLabel#14 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 423788#L1471-39 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 423785#L1471-41 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 423783#L623-39 assume !(1 == ~t3_pc~0); 423080#L623-41 is_transmit3_triggered_~__retres1~3#1 := 0; 423780#L634-13 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 423778#is_transmit3_triggered_returnLabel#14 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 423776#L1479-39 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 423773#L1479-41 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 423771#L642-39 assume 1 == ~t4_pc~0; 423768#L643-13 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 423766#L653-13 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 423764#is_transmit4_triggered_returnLabel#14 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 423762#L1487-39 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 423759#L1487-41 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 423757#L661-39 assume !(1 == ~t5_pc~0); 423755#L661-41 is_transmit5_triggered_~__retres1~5#1 := 0; 423753#L672-13 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 423751#is_transmit5_triggered_returnLabel#14 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 423749#L1495-39 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 423746#L1495-41 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 423744#L680-39 assume !(1 == ~t6_pc~0); 423742#L680-41 is_transmit6_triggered_~__retres1~6#1 := 0; 423739#L691-13 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 423737#is_transmit6_triggered_returnLabel#14 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 423735#L1503-39 assume !(0 != activate_threads_~tmp___5~0#1); 423732#L1503-41 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 423730#L699-39 assume !(1 == ~t7_pc~0); 423728#L699-41 is_transmit7_triggered_~__retres1~7#1 := 0; 423725#L710-13 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 423723#is_transmit7_triggered_returnLabel#14 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 423721#L1511-39 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 423719#L1511-41 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 423718#L718-39 assume 1 == ~t8_pc~0; 423716#L719-13 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 423715#L729-13 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 423714#is_transmit8_triggered_returnLabel#14 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 423713#L1519-39 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 423712#L1519-41 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 423711#L737-39 assume 1 == ~t9_pc~0; 423708#L738-13 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 423706#L748-13 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 423704#is_transmit9_triggered_returnLabel#14 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 423702#L1527-39 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 423700#L1527-41 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 423697#L756-39 assume !(1 == ~t10_pc~0); 423694#L756-41 is_transmit10_triggered_~__retres1~10#1 := 0; 423692#L767-13 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 423690#is_transmit10_triggered_returnLabel#14 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 423688#L1535-39 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 423686#L1535-41 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 423685#L775-39 assume !(1 == ~t11_pc~0); 423682#L775-41 is_transmit11_triggered_~__retres1~11#1 := 0; 423679#L786-13 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 423677#is_transmit11_triggered_returnLabel#14 activate_threads_#t~ret29#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 423675#L1543-39 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 423673#L1543-41 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 423671#L794-39 assume 1 == ~t12_pc~0; 423668#L795-13 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 423665#L805-13 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 423663#is_transmit12_triggered_returnLabel#14 activate_threads_#t~ret30#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 423661#L1551-39 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 423659#L1551-41 havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 423657#L1307-3 assume 1 == ~M_E~0;~M_E~0 := 2; 423654#L1307-5 assume !(1 == ~T1_E~0); 423652#L1312-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 417044#L1317-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 423647#L1322-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 423645#L1327-3 assume !(1 == ~T5_E~0); 423643#L1332-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 423640#L1337-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 423638#L1342-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 423636#L1347-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 423632#L1352-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 423630#L1357-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 423628#L1362-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 423626#L1367-3 assume !(1 == ~E_1~0); 423622#L1372-3 assume 1 == ~E_2~0;~E_2~0 := 2; 423621#L1377-3 assume 1 == ~E_3~0;~E_3~0 := 2; 423619#L1382-3 assume 1 == ~E_4~0;~E_4~0 := 2; 423617#L1387-3 assume 1 == ~E_5~0;~E_5~0 := 2; 417008#L1392-3 assume 1 == ~E_6~0;~E_6~0 := 2; 423614#L1397-3 assume 1 == ~E_7~0;~E_7~0 := 2; 423612#L1402-3 assume 1 == ~E_8~0;~E_8~0 := 2; 423608#L1407-3 assume !(1 == ~E_9~0); 423606#L1412-3 assume 1 == ~E_10~0;~E_10~0 := 2; 423604#L1417-3 assume 1 == ~E_11~0;~E_11~0 := 2; 423602#L1422-3 assume 1 == ~E_12~0;~E_12~0 := 2; 423600#L1427-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 423584#L894-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 423577#L961-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 423575#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret32#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret32#1;havoc start_simulation_#t~ret32#1; 423573#L1787 assume !(0 == start_simulation_~tmp~3#1); 423571#L1787-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret31#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 422560#L894-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 422546#L961-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 422545#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret31#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret31#1;havoc stop_simulation_#t~ret31#1; 422542#L1742 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 422540#L1749 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 422538#stop_simulation_returnLabel#1 start_simulation_#t~ret33#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret31#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret33#1;havoc start_simulation_#t~ret33#1; 422536#L1800 assume !(0 != start_simulation_~tmp___0~1#1); 422533#L1768-2 [2023-11-12 02:13:57,545 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-12 02:13:57,546 INFO L85 PathProgramCache]: Analyzing trace with hash -1479734059, now seen corresponding path program 1 times [2023-11-12 02:13:57,546 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-12 02:13:57,546 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [120413914] [2023-11-12 02:13:57,546 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-12 02:13:57,547 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-12 02:13:57,564 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-12 02:13:57,641 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-12 02:13:57,641 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-12 02:13:57,641 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [120413914] [2023-11-12 02:13:57,642 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [120413914] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-12 02:13:57,642 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-12 02:13:57,642 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-12 02:13:57,642 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1141653458] [2023-11-12 02:13:57,642 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-12 02:13:57,643 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-12 02:13:57,643 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-12 02:13:57,643 INFO L85 PathProgramCache]: Analyzing trace with hash -810425409, now seen corresponding path program 1 times [2023-11-12 02:13:57,643 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-12 02:13:57,644 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [256565341] [2023-11-12 02:13:57,644 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-12 02:13:57,644 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-12 02:13:57,660 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-12 02:13:57,705 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-12 02:13:57,705 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-12 02:13:57,705 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [256565341] [2023-11-12 02:13:57,705 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [256565341] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-12 02:13:57,705 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-12 02:13:57,706 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-12 02:13:57,706 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1838783456] [2023-11-12 02:13:57,706 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-12 02:13:57,706 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-12 02:13:57,707 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-12 02:13:57,707 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2023-11-12 02:13:57,707 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2023-11-12 02:13:57,707 INFO L87 Difference]: Start difference. First operand 84335 states and 120569 transitions. cyclomatic complexity: 36250 Second operand has 4 states, 4 states have (on average 37.0) internal successors, (148), 3 states have internal predecessors, (148), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-12 02:13:59,361 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-12 02:13:59,361 INFO L93 Difference]: Finished difference Result 204294 states and 290374 transitions. [2023-11-12 02:13:59,361 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 204294 states and 290374 transitions. [2023-11-12 02:14:00,150 INFO L131 ngComponentsAnalysis]: Automaton has 24 accepting balls. 200648 [2023-11-12 02:14:01,053 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 204294 states to 204294 states and 290374 transitions. [2023-11-12 02:14:01,053 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 204294 [2023-11-12 02:14:01,129 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 204294 [2023-11-12 02:14:01,129 INFO L73 IsDeterministic]: Start isDeterministic. Operand 204294 states and 290374 transitions. [2023-11-12 02:14:01,187 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-12 02:14:01,187 INFO L218 hiAutomatonCegarLoop]: Abstraction has 204294 states and 290374 transitions. [2023-11-12 02:14:01,295 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 204294 states and 290374 transitions. [2023-11-12 02:14:03,197 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 204294 to 161582. [2023-11-12 02:14:03,381 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 161582 states, 161582 states have (on average 1.4251463653129681) internal successors, (230278), 161581 states have internal predecessors, (230278), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-12 02:14:03,856 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 161582 states to 161582 states and 230278 transitions. [2023-11-12 02:14:03,856 INFO L240 hiAutomatonCegarLoop]: Abstraction has 161582 states and 230278 transitions. [2023-11-12 02:14:03,857 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2023-11-12 02:14:03,857 INFO L428 stractBuchiCegarLoop]: Abstraction has 161582 states and 230278 transitions. [2023-11-12 02:14:03,857 INFO L335 stractBuchiCegarLoop]: ======== Iteration 22 ============ [2023-11-12 02:14:03,857 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 161582 states and 230278 transitions. [2023-11-12 02:14:04,255 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 161184 [2023-11-12 02:14:04,255 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-12 02:14:04,255 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-12 02:14:04,259 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-12 02:14:04,259 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-12 02:14:04,260 INFO L748 eck$LassoCheckResult]: Stem: 694414#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2; 694415#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~14#1;havoc main_~__retres1~14#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1; 695256#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret32#1, start_simulation_#t~ret33#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 695257#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 695112#L821 assume 1 == ~m_i~0;~m_st~0 := 0; 695113#L821-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 695215#L826-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 695577#L831-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 695741#L836-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 695742#L841-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 694390#L846-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 694391#L851-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 695653#L856-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 694999#L861-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 695000#L866-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 694906#L871-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 694907#L876-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 695348#L881-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 694627#L1174 assume !(0 == ~M_E~0); 694628#L1174-2 assume !(0 == ~T1_E~0); 694482#L1179-1 assume !(0 == ~T2_E~0); 694388#L1184-1 assume !(0 == ~T3_E~0); 694389#L1189-1 assume !(0 == ~T4_E~0); 694431#L1194-1 assume !(0 == ~T5_E~0); 694525#L1199-1 assume !(0 == ~T6_E~0); 695493#L1204-1 assume !(0 == ~T7_E~0); 695400#L1209-1 assume !(0 == ~T8_E~0); 695401#L1214-1 assume !(0 == ~T9_E~0); 695930#L1219-1 assume !(0 == ~T10_E~0); 696109#L1224-1 assume !(0 == ~T11_E~0); 694756#L1229-1 assume !(0 == ~T12_E~0); 694316#L1234-1 assume !(0 == ~E_1~0); 694317#L1239-1 assume !(0 == ~E_2~0); 694351#L1244-1 assume !(0 == ~E_3~0); 694352#L1249-1 assume !(0 == ~E_4~0); 695022#L1254-1 assume !(0 == ~E_5~0); 694248#L1259-1 assume !(0 == ~E_6~0); 694205#L1264-1 assume !(0 == ~E_7~0); 694206#L1269-1 assume !(0 == ~E_8~0); 696133#L1274-1 assume !(0 == ~E_9~0); 695983#L1279-1 assume !(0 == ~E_10~0); 694434#L1284-1 assume !(0 == ~E_11~0); 694435#L1289-1 assume !(0 == ~E_12~0); 695080#L1294-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 695081#L566 assume !(1 == ~m_pc~0); 695568#L566-2 is_master_triggered_~__retres1~0#1 := 0; 695569#L577 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 695127#is_master_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 695128#L1455 assume !(0 != activate_threads_~tmp~1#1); 694654#L1455-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 694655#L585 assume !(1 == ~t1_pc~0); 694846#L585-2 is_transmit1_triggered_~__retres1~1#1 := 0; 694847#L596 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 695559#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 695560#L1463 assume !(0 != activate_threads_~tmp___0~0#1); 696034#L1463-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 696027#L604 assume !(1 == ~t2_pc~0); 695450#L604-2 is_transmit2_triggered_~__retres1~2#1 := 0; 695451#L615 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 694602#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 694603#L1471 assume !(0 != activate_threads_~tmp___1~0#1); 695693#L1471-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 695694#L623 assume !(1 == ~t3_pc~0); 694180#L623-2 is_transmit3_triggered_~__retres1~3#1 := 0; 694181#L634 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 695533#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 695534#L1479 assume !(0 != activate_threads_~tmp___2~0#1); 695734#L1479-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 694219#L642 assume !(1 == ~t4_pc~0); 694220#L642-2 is_transmit4_triggered_~__retres1~4#1 := 0; 694667#L653 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 694276#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 694277#L1487 assume !(0 != activate_threads_~tmp___3~0#1); 694293#L1487-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 695466#L661 assume !(1 == ~t5_pc~0); 695660#L661-2 is_transmit5_triggered_~__retres1~5#1 := 0; 695366#L672 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 695367#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 695815#L1495 assume !(0 != activate_threads_~tmp___4~0#1); 695503#L1495-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 695504#L680 assume !(1 == ~t6_pc~0); 694883#L680-2 is_transmit6_triggered_~__retres1~6#1 := 0; 694884#L691 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 694591#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 694592#L1503 assume !(0 != activate_threads_~tmp___5~0#1); 695828#L1503-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 696024#L699 assume !(1 == ~t7_pc~0); 696025#L699-2 is_transmit7_triggered_~__retres1~7#1 := 0; 695596#L710 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 695597#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 695197#L1511 assume !(0 != activate_threads_~tmp___6~0#1); 695198#L1511-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 695082#L718 assume !(1 == ~t8_pc~0); 695083#L718-2 is_transmit8_triggered_~__retres1~8#1 := 0; 694429#L729 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 694430#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 694464#L1519 assume !(0 != activate_threads_~tmp___7~0#1); 694465#L1519-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 694594#L737 assume 1 == ~t9_pc~0; 695549#L738 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 694737#L748 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 694634#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 694635#L1527 assume !(0 != activate_threads_~tmp___8~0#1); 694925#L1527-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 694926#L756 assume 1 == ~t10_pc~0; 695585#L757 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 695187#L767 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 695488#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 695120#L1535 assume !(0 != activate_threads_~tmp___9~0#1); 694713#L1535-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 694714#L775 assume !(1 == ~t11_pc~0); 694990#L775-2 is_transmit11_triggered_~__retres1~11#1 := 0; 694991#L786 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 695923#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 694361#L1543 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 694362#L1543-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 694542#L794 assume 1 == ~t12_pc~0; 694385#L795 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 694364#L805 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 694224#is_transmit12_triggered_returnLabel#1 activate_threads_#t~ret30#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 694225#L1551 assume !(0 != activate_threads_~tmp___11~0#1); 694510#L1551-2 havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 695005#L1307 assume !(1 == ~M_E~0); 695006#L1307-2 assume !(1 == ~T1_E~0); 695124#L1312-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 695037#L1317-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 695038#L1322-1 assume !(1 == ~T4_E~0); 694725#L1327-1 assume !(1 == ~T5_E~0); 694726#L1332-1 assume !(1 == ~T6_E~0); 696047#L1337-1 assume !(1 == ~T7_E~0); 696048#L1342-1 assume !(1 == ~T8_E~0); 695980#L1347-1 assume !(1 == ~T9_E~0); 695981#L1352-1 assume !(1 == ~T10_E~0); 695598#L1357-1 assume 1 == ~T11_E~0;~T11_E~0 := 2; 695599#L1362-1 assume !(1 == ~T12_E~0); 695843#L1367-1 assume !(1 == ~E_1~0); 695844#L1372-1 assume !(1 == ~E_2~0); 695052#L1377-1 assume !(1 == ~E_3~0); 695053#L1382-1 assume !(1 == ~E_4~0); 695452#L1387-1 assume !(1 == ~E_5~0); 695453#L1392-1 assume !(1 == ~E_6~0); 694852#L1397-1 assume 1 == ~E_7~0;~E_7~0 := 2; 694853#L1402-1 assume !(1 == ~E_8~0); 694540#L1407-1 assume !(1 == ~E_9~0); 694541#L1412-1 assume !(1 == ~E_10~0); 695686#L1417-1 assume !(1 == ~E_11~0); 695687#L1422-1 assume !(1 == ~E_12~0); 696014#L1427-1 assume { :end_inline_reset_delta_events } true; 696015#L1768-2 [2023-11-12 02:14:04,260 INFO L750 eck$LassoCheckResult]: Loop: 696015#L1768-2 assume !false; 771765#L1769 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 771758#L1149-1 assume !false; 771756#L972 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 771629#L894 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 771618#L961 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 771524#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 771461#L976 assume !(0 != eval_~tmp~0#1); 771462#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 795590#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 795589#L1174-3 assume 0 == ~M_E~0;~M_E~0 := 1; 795588#L1174-5 assume !(0 == ~T1_E~0); 795587#L1179-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 795586#L1184-3 assume !(0 == ~T3_E~0); 795585#L1189-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 795584#L1194-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 795583#L1199-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 795582#L1204-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 795581#L1209-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 795580#L1214-3 assume !(0 == ~T9_E~0); 795579#L1219-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 795578#L1224-3 assume !(0 == ~T11_E~0); 795577#L1229-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 795576#L1234-3 assume 0 == ~E_1~0;~E_1~0 := 1; 795575#L1239-3 assume 0 == ~E_2~0;~E_2~0 := 1; 795574#L1244-3 assume 0 == ~E_3~0;~E_3~0 := 1; 795573#L1249-3 assume 0 == ~E_4~0;~E_4~0 := 1; 795572#L1254-3 assume !(0 == ~E_5~0); 795571#L1259-3 assume 0 == ~E_6~0;~E_6~0 := 1; 795570#L1264-3 assume !(0 == ~E_7~0); 795569#L1269-3 assume 0 == ~E_8~0;~E_8~0 := 1; 795567#L1274-3 assume 0 == ~E_9~0;~E_9~0 := 1; 795565#L1279-3 assume 0 == ~E_10~0;~E_10~0 := 1; 775382#L1284-3 assume 0 == ~E_11~0;~E_11~0 := 1; 775381#L1289-3 assume 0 == ~E_12~0;~E_12~0 := 1; 775380#L1294-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 775378#L566-39 assume !(1 == ~m_pc~0); 775376#L566-41 is_master_triggered_~__retres1~0#1 := 0; 775374#L577-13 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 775372#is_master_triggered_returnLabel#14 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 775370#L1455-39 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 775369#L1455-41 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 775368#L585-39 assume !(1 == ~t1_pc~0); 770575#L585-41 is_transmit1_triggered_~__retres1~1#1 := 0; 775365#L596-13 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 775363#is_transmit1_triggered_returnLabel#14 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 775361#L1463-39 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 775359#L1463-41 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 772659#L604-39 assume !(1 == ~t2_pc~0); 772655#L604-41 is_transmit2_triggered_~__retres1~2#1 := 0; 772653#L615-13 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 772651#is_transmit2_triggered_returnLabel#14 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 772649#L1471-39 assume !(0 != activate_threads_~tmp___1~0#1); 772646#L1471-41 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 772644#L623-39 assume !(1 == ~t3_pc~0); 769234#L623-41 is_transmit3_triggered_~__retres1~3#1 := 0; 772634#L634-13 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 772628#is_transmit3_triggered_returnLabel#14 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 772622#L1479-39 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 772615#L1479-41 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 772608#L642-39 assume !(1 == ~t4_pc~0); 772602#L642-41 is_transmit4_triggered_~__retres1~4#1 := 0; 772594#L653-13 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 772589#is_transmit4_triggered_returnLabel#14 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 772583#L1487-39 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 772578#L1487-41 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 772573#L661-39 assume !(1 == ~t5_pc~0); 772569#L661-41 is_transmit5_triggered_~__retres1~5#1 := 0; 772565#L672-13 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 772559#is_transmit5_triggered_returnLabel#14 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 772554#L1495-39 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 772548#L1495-41 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 772544#L680-39 assume 1 == ~t6_pc~0; 772539#L681-13 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 772535#L691-13 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 772531#is_transmit6_triggered_returnLabel#14 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 772526#L1503-39 assume !(0 != activate_threads_~tmp___5~0#1); 772521#L1503-41 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 772516#L699-39 assume !(1 == ~t7_pc~0); 738319#L699-41 is_transmit7_triggered_~__retres1~7#1 := 0; 772506#L710-13 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 772500#is_transmit7_triggered_returnLabel#14 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 772496#L1511-39 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 772490#L1511-41 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 772485#L718-39 assume 1 == ~t8_pc~0; 772479#L719-13 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 772473#L729-13 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 772468#is_transmit8_triggered_returnLabel#14 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 772461#L1519-39 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 772456#L1519-41 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 772451#L737-39 assume !(1 == ~t9_pc~0); 772446#L737-41 is_transmit9_triggered_~__retres1~9#1 := 0; 772441#L748-13 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 772435#is_transmit9_triggered_returnLabel#14 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 772430#L1527-39 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 772424#L1527-41 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 772419#L756-39 assume 1 == ~t10_pc~0; 772414#L757-13 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 772407#L767-13 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 772401#is_transmit10_triggered_returnLabel#14 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 772395#L1535-39 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 772389#L1535-41 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 772384#L775-39 assume !(1 == ~t11_pc~0); 772379#L775-41 is_transmit11_triggered_~__retres1~11#1 := 0; 772373#L786-13 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 772367#is_transmit11_triggered_returnLabel#14 activate_threads_#t~ret29#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 772362#L1543-39 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 772355#L1543-41 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 772349#L794-39 assume 1 == ~t12_pc~0; 772343#L795-13 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 772336#L805-13 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 772330#is_transmit12_triggered_returnLabel#14 activate_threads_#t~ret30#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 772327#L1551-39 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 772326#L1551-41 havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 772325#L1307-3 assume 1 == ~M_E~0;~M_E~0 := 2; 772323#L1307-5 assume !(1 == ~T1_E~0); 772322#L1312-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 743856#L1317-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 772320#L1322-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 772318#L1327-3 assume !(1 == ~T5_E~0); 772316#L1332-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 772314#L1337-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 772312#L1342-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 772310#L1347-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 771267#L1352-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 772305#L1357-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 772303#L1362-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 772301#L1367-3 assume !(1 == ~E_1~0); 772298#L1372-3 assume 1 == ~E_2~0;~E_2~0 := 2; 772296#L1377-3 assume 1 == ~E_3~0;~E_3~0 := 2; 772294#L1382-3 assume 1 == ~E_4~0;~E_4~0 := 2; 772293#L1387-3 assume 1 == ~E_5~0;~E_5~0 := 2; 753820#L1392-3 assume 1 == ~E_6~0;~E_6~0 := 2; 772290#L1397-3 assume 1 == ~E_7~0;~E_7~0 := 2; 772288#L1402-3 assume 1 == ~E_8~0;~E_8~0 := 2; 772286#L1407-3 assume !(1 == ~E_9~0); 772284#L1412-3 assume 1 == ~E_10~0;~E_10~0 := 2; 772281#L1417-3 assume 1 == ~E_11~0;~E_11~0 := 2; 772279#L1422-3 assume 1 == ~E_12~0;~E_12~0 := 2; 772277#L1427-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 772111#L894-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 772099#L961-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 772092#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret32#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret32#1;havoc start_simulation_#t~ret32#1; 772085#L1787 assume !(0 == start_simulation_~tmp~3#1); 772078#L1787-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret31#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 771995#L894-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 771981#L961-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 771980#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret31#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret31#1;havoc stop_simulation_#t~ret31#1; 771828#L1742 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 771824#L1749 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 771796#stop_simulation_returnLabel#1 start_simulation_#t~ret33#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret31#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret33#1;havoc start_simulation_#t~ret33#1; 771784#L1800 assume !(0 != start_simulation_~tmp___0~1#1); 696015#L1768-2 [2023-11-12 02:14:04,261 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-12 02:14:04,261 INFO L85 PathProgramCache]: Analyzing trace with hash 339991860, now seen corresponding path program 1 times [2023-11-12 02:14:04,262 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-12 02:14:04,262 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1571536740] [2023-11-12 02:14:04,262 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-12 02:14:04,262 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-12 02:14:04,281 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-12 02:14:04,947 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-12 02:14:04,947 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-12 02:14:04,947 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1571536740] [2023-11-12 02:14:04,949 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1571536740] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-12 02:14:04,949 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-12 02:14:04,950 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-12 02:14:04,950 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1876208104] [2023-11-12 02:14:04,950 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-12 02:14:04,950 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-12 02:14:04,951 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-12 02:14:04,951 INFO L85 PathProgramCache]: Analyzing trace with hash -982064036, now seen corresponding path program 1 times [2023-11-12 02:14:04,952 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-12 02:14:04,952 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [75598976] [2023-11-12 02:14:04,952 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-12 02:14:04,952 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-12 02:14:04,990 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-12 02:14:05,088 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-12 02:14:05,088 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-12 02:14:05,089 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [75598976] [2023-11-12 02:14:05,089 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [75598976] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-12 02:14:05,089 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-12 02:14:05,089 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-12 02:14:05,090 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1574226687] [2023-11-12 02:14:05,090 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-12 02:14:05,090 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-12 02:14:05,090 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-12 02:14:05,091 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2023-11-12 02:14:05,091 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2023-11-12 02:14:05,092 INFO L87 Difference]: Start difference. First operand 161582 states and 230278 transitions. cyclomatic complexity: 68712 Second operand has 4 states, 4 states have (on average 37.0) internal successors, (148), 3 states have internal predecessors, (148), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-12 02:14:07,430 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-12 02:14:07,431 INFO L93 Difference]: Finished difference Result 389581 states and 552115 transitions. [2023-11-12 02:14:07,431 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 389581 states and 552115 transitions. [2023-11-12 02:14:09,328 INFO L131 ngComponentsAnalysis]: Automaton has 24 accepting balls. 382528 [2023-11-12 02:14:10,242 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 389581 states to 389581 states and 552115 transitions. [2023-11-12 02:14:10,242 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 389581 [2023-11-12 02:14:10,430 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 389581 [2023-11-12 02:14:10,430 INFO L73 IsDeterministic]: Start isDeterministic. Operand 389581 states and 552115 transitions. [2023-11-12 02:14:10,589 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-12 02:14:10,589 INFO L218 hiAutomatonCegarLoop]: Abstraction has 389581 states and 552115 transitions. [2023-11-12 02:14:11,270 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 389581 states and 552115 transitions. [2023-11-12 02:14:15,022 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 389581 to 309325. [2023-11-12 02:14:15,250 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 309325 states, 309325 states have (on average 1.4210134971308495) internal successors, (439555), 309324 states have internal predecessors, (439555), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-12 02:14:15,953 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 309325 states to 309325 states and 439555 transitions. [2023-11-12 02:14:15,953 INFO L240 hiAutomatonCegarLoop]: Abstraction has 309325 states and 439555 transitions. [2023-11-12 02:14:15,953 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2023-11-12 02:14:15,954 INFO L428 stractBuchiCegarLoop]: Abstraction has 309325 states and 439555 transitions. [2023-11-12 02:14:15,954 INFO L335 stractBuchiCegarLoop]: ======== Iteration 23 ============ [2023-11-12 02:14:15,954 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 309325 states and 439555 transitions. [2023-11-12 02:14:17,722 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 308736 [2023-11-12 02:14:17,722 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-12 02:14:17,722 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-12 02:14:17,726 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-12 02:14:17,726 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-12 02:14:17,727 INFO L748 eck$LassoCheckResult]: Stem: 1245582#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2; 1245583#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~14#1;havoc main_~__retres1~14#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1; 1246418#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret32#1, start_simulation_#t~ret33#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 1246419#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 1246270#L821 assume 1 == ~m_i~0;~m_st~0 := 0; 1246271#L821-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 1246376#L826-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 1246739#L831-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 1246900#L836-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 1246901#L841-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 1245559#L846-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 1245560#L851-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 1246814#L856-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 1246160#L861-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 1246161#L866-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 1246070#L871-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 1246071#L876-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 1246508#L881-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 1245797#L1174 assume !(0 == ~M_E~0); 1245798#L1174-2 assume !(0 == ~T1_E~0); 1245650#L1179-1 assume !(0 == ~T2_E~0); 1245557#L1184-1 assume !(0 == ~T3_E~0); 1245558#L1189-1 assume !(0 == ~T4_E~0); 1245599#L1194-1 assume !(0 == ~T5_E~0); 1245693#L1199-1 assume !(0 == ~T6_E~0); 1246653#L1204-1 assume !(0 == ~T7_E~0); 1246558#L1209-1 assume !(0 == ~T8_E~0); 1246559#L1214-1 assume !(0 == ~T9_E~0); 1247092#L1219-1 assume !(0 == ~T10_E~0); 1247257#L1224-1 assume !(0 == ~T11_E~0); 1245921#L1229-1 assume !(0 == ~T12_E~0); 1245488#L1234-1 assume !(0 == ~E_1~0); 1245489#L1239-1 assume !(0 == ~E_2~0); 1245522#L1244-1 assume !(0 == ~E_3~0); 1245523#L1249-1 assume !(0 == ~E_4~0); 1246184#L1254-1 assume !(0 == ~E_5~0); 1245421#L1259-1 assume !(0 == ~E_6~0); 1245378#L1264-1 assume !(0 == ~E_7~0); 1245379#L1269-1 assume !(0 == ~E_8~0); 1247279#L1274-1 assume !(0 == ~E_9~0); 1247146#L1279-1 assume !(0 == ~E_10~0); 1245602#L1284-1 assume !(0 == ~E_11~0); 1245603#L1289-1 assume !(0 == ~E_12~0); 1246239#L1294-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1246240#L566 assume !(1 == ~m_pc~0); 1246730#L566-2 is_master_triggered_~__retres1~0#1 := 0; 1246731#L577 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1246287#is_master_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1246288#L1455 assume !(0 != activate_threads_~tmp~1#1); 1245824#L1455-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1245825#L585 assume !(1 == ~t1_pc~0); 1246010#L585-2 is_transmit1_triggered_~__retres1~1#1 := 0; 1246011#L596 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1246720#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1246721#L1463 assume !(0 != activate_threads_~tmp___0~0#1); 1247198#L1463-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1247193#L604 assume !(1 == ~t2_pc~0); 1246605#L604-2 is_transmit2_triggered_~__retres1~2#1 := 0; 1246606#L615 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1245771#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1245772#L1471 assume !(0 != activate_threads_~tmp___1~0#1); 1246852#L1471-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1246853#L623 assume !(1 == ~t3_pc~0); 1245353#L623-2 is_transmit3_triggered_~__retres1~3#1 := 0; 1245354#L634 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1246692#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1246693#L1479 assume !(0 != activate_threads_~tmp___2~0#1); 1246893#L1479-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1245392#L642 assume !(1 == ~t4_pc~0); 1245393#L642-2 is_transmit4_triggered_~__retres1~4#1 := 0; 1245835#L653 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1245449#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 1245450#L1487 assume !(0 != activate_threads_~tmp___3~0#1); 1245465#L1487-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1246620#L661 assume !(1 == ~t5_pc~0); 1246821#L661-2 is_transmit5_triggered_~__retres1~5#1 := 0; 1246525#L672 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1246526#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 1246974#L1495 assume !(0 != activate_threads_~tmp___4~0#1); 1246665#L1495-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1246666#L680 assume !(1 == ~t6_pc~0); 1246048#L680-2 is_transmit6_triggered_~__retres1~6#1 := 0; 1246049#L691 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1245760#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 1245761#L1503 assume !(0 != activate_threads_~tmp___5~0#1); 1246989#L1503-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1247189#L699 assume !(1 == ~t7_pc~0); 1247190#L699-2 is_transmit7_triggered_~__retres1~7#1 := 0; 1246760#L710 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1246761#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 1246358#L1511 assume !(0 != activate_threads_~tmp___6~0#1); 1246359#L1511-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 1246241#L718 assume !(1 == ~t8_pc~0); 1246242#L718-2 is_transmit8_triggered_~__retres1~8#1 := 0; 1245597#L729 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 1245598#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 1245632#L1519 assume !(0 != activate_threads_~tmp___7~0#1); 1245633#L1519-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 1245763#L737 assume !(1 == ~t9_pc~0); 1245901#L737-2 is_transmit9_triggered_~__retres1~9#1 := 0; 1245902#L748 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 1245804#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 1245805#L1527 assume !(0 != activate_threads_~tmp___8~0#1); 1246090#L1527-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 1246091#L756 assume 1 == ~t10_pc~0; 1246749#L757 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 1246347#L767 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 1246644#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 1246280#L1535 assume !(0 != activate_threads_~tmp___9~0#1); 1245879#L1535-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 1245880#L775 assume !(1 == ~t11_pc~0); 1246152#L775-2 is_transmit11_triggered_~__retres1~11#1 := 0; 1246153#L786 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 1247082#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 1245532#L1543 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 1245533#L1543-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 1245712#L794 assume 1 == ~t12_pc~0; 1245555#L795 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 1245535#L805 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 1245397#is_transmit12_triggered_returnLabel#1 activate_threads_#t~ret30#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 1245398#L1551 assume !(0 != activate_threads_~tmp___11~0#1); 1245678#L1551-2 havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1246165#L1307 assume !(1 == ~M_E~0); 1246166#L1307-2 assume !(1 == ~T1_E~0); 1246284#L1312-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 1246196#L1317-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 1246197#L1322-1 assume !(1 == ~T4_E~0); 1245890#L1327-1 assume !(1 == ~T5_E~0); 1245891#L1332-1 assume !(1 == ~T6_E~0); 1246486#L1337-1 assume !(1 == ~T7_E~0); 1246433#L1342-1 assume !(1 == ~T8_E~0); 1246434#L1347-1 assume !(1 == ~T9_E~0); 1247144#L1352-1 assume !(1 == ~T10_E~0); 1246762#L1357-1 assume 1 == ~T11_E~0;~T11_E~0 := 2; 1246763#L1362-1 assume !(1 == ~T12_E~0); 1247002#L1367-1 assume !(1 == ~E_1~0); 1247003#L1372-1 assume !(1 == ~E_2~0); 1246210#L1377-1 assume !(1 == ~E_3~0); 1246211#L1382-1 assume !(1 == ~E_4~0); 1246607#L1387-1 assume !(1 == ~E_5~0); 1246608#L1392-1 assume !(1 == ~E_6~0); 1246016#L1397-1 assume 1 == ~E_7~0;~E_7~0 := 2; 1246017#L1402-1 assume !(1 == ~E_8~0); 1245710#L1407-1 assume !(1 == ~E_9~0); 1245711#L1412-1 assume !(1 == ~E_10~0); 1246845#L1417-1 assume !(1 == ~E_11~0); 1246846#L1422-1 assume !(1 == ~E_12~0); 1247182#L1427-1 assume { :end_inline_reset_delta_events } true; 1247183#L1768-2 [2023-11-12 02:14:17,727 INFO L750 eck$LassoCheckResult]: Loop: 1247183#L1768-2 assume !false; 1540999#L1769 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 1540989#L1149-1 assume !false; 1540823#L972 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 1540754#L894 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 1540747#L961 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 1540745#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 1540742#L976 assume !(0 != eval_~tmp~0#1); 1540743#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 1551898#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 1551897#L1174-3 assume 0 == ~M_E~0;~M_E~0 := 1; 1551896#L1174-5 assume !(0 == ~T1_E~0); 1551894#L1179-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 1551891#L1184-3 assume !(0 == ~T3_E~0); 1551888#L1189-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 1551885#L1194-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 1551881#L1199-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 1551875#L1204-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 1245909#L1209-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 1245340#L1214-3 assume !(0 == ~T9_E~0); 1245341#L1219-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 1246103#L1224-3 assume !(0 == ~T11_E~0); 1246104#L1229-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 1246118#L1234-3 assume 0 == ~E_1~0;~E_1~0 := 1; 1245526#L1239-3 assume 0 == ~E_2~0;~E_2~0 := 1; 1245527#L1244-3 assume 0 == ~E_3~0;~E_3~0 := 1; 1245972#L1249-3 assume 0 == ~E_4~0;~E_4~0 := 1; 1246475#L1254-3 assume !(0 == ~E_5~0); 1247088#L1259-3 assume 0 == ~E_6~0;~E_6~0 := 1; 1246588#L1264-3 assume !(0 == ~E_7~0); 1245530#L1269-3 assume 0 == ~E_8~0;~E_8~0 := 1; 1245531#L1274-3 assume 0 == ~E_9~0;~E_9~0 := 1; 1247143#L1279-3 assume 0 == ~E_10~0;~E_10~0 := 1; 1246099#L1284-3 assume 0 == ~E_11~0;~E_11~0 := 1; 1246100#L1289-3 assume 0 == ~E_12~0;~E_12~0 := 1; 1246087#L1294-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1245746#L566-39 assume !(1 == ~m_pc~0); 1245747#L566-41 is_master_triggered_~__retres1~0#1 := 0; 1246387#L577-13 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1246388#is_master_triggered_returnLabel#14 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1246445#L1455-39 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 1247098#L1455-41 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1542076#L585-39 assume !(1 == ~t1_pc~0); 1542074#L585-41 is_transmit1_triggered_~__retres1~1#1 := 0; 1542072#L596-13 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1542070#is_transmit1_triggered_returnLabel#14 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1542068#L1463-39 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 1542066#L1463-41 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1542063#L604-39 assume !(1 == ~t2_pc~0); 1542059#L604-41 is_transmit2_triggered_~__retres1~2#1 := 0; 1542055#L615-13 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1542051#is_transmit2_triggered_returnLabel#14 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1542046#L1471-39 assume !(0 != activate_threads_~tmp___1~0#1); 1542041#L1471-41 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1542037#L623-39 assume !(1 == ~t3_pc~0); 1533632#L623-41 is_transmit3_triggered_~__retres1~3#1 := 0; 1542030#L634-13 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1542025#is_transmit3_triggered_returnLabel#14 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1542020#L1479-39 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 1542014#L1479-41 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1542009#L642-39 assume !(1 == ~t4_pc~0); 1542003#L642-41 is_transmit4_triggered_~__retres1~4#1 := 0; 1541998#L653-13 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1541994#is_transmit4_triggered_returnLabel#14 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 1541990#L1487-39 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 1541987#L1487-41 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1541983#L661-39 assume !(1 == ~t5_pc~0); 1541980#L661-41 is_transmit5_triggered_~__retres1~5#1 := 0; 1541975#L672-13 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1541971#is_transmit5_triggered_returnLabel#14 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 1541967#L1495-39 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 1541962#L1495-41 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1541958#L680-39 assume !(1 == ~t6_pc~0); 1541953#L680-41 is_transmit6_triggered_~__retres1~6#1 := 0; 1541948#L691-13 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1541943#is_transmit6_triggered_returnLabel#14 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 1541938#L1503-39 assume !(0 != activate_threads_~tmp___5~0#1); 1541933#L1503-41 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1541928#L699-39 assume !(1 == ~t7_pc~0); 1512592#L699-41 is_transmit7_triggered_~__retres1~7#1 := 0; 1541917#L710-13 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1541912#is_transmit7_triggered_returnLabel#14 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 1541906#L1511-39 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 1541899#L1511-41 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 1541893#L718-39 assume !(1 == ~t8_pc~0); 1541886#L718-41 is_transmit8_triggered_~__retres1~8#1 := 0; 1541881#L729-13 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 1541876#is_transmit8_triggered_returnLabel#14 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 1541872#L1519-39 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 1541867#L1519-41 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 1541861#L737-39 assume !(1 == ~t9_pc~0); 1370370#L737-41 is_transmit9_triggered_~__retres1~9#1 := 0; 1541849#L748-13 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 1541844#is_transmit9_triggered_returnLabel#14 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 1541837#L1527-39 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 1541830#L1527-41 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 1541823#L756-39 assume 1 == ~t10_pc~0; 1541817#L757-13 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 1541812#L767-13 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 1541807#is_transmit10_triggered_returnLabel#14 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 1541803#L1535-39 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 1541799#L1535-41 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 1541792#L775-39 assume !(1 == ~t11_pc~0); 1541786#L775-41 is_transmit11_triggered_~__retres1~11#1 := 0; 1541779#L786-13 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 1541774#is_transmit11_triggered_returnLabel#14 activate_threads_#t~ret29#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 1541768#L1543-39 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 1541761#L1543-41 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 1541755#L794-39 assume 1 == ~t12_pc~0; 1541749#L795-13 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 1541741#L805-13 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 1541735#is_transmit12_triggered_returnLabel#14 activate_threads_#t~ret30#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 1541729#L1551-39 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 1541721#L1551-41 havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1541717#L1307-3 assume 1 == ~M_E~0;~M_E~0 := 2; 1541712#L1307-5 assume !(1 == ~T1_E~0); 1541707#L1312-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 1401101#L1317-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 1541534#L1322-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 1541531#L1327-3 assume !(1 == ~T5_E~0); 1541529#L1332-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 1541527#L1337-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 1541525#L1342-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 1541523#L1347-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 1507781#L1352-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 1541519#L1357-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 1541517#L1362-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 1541515#L1367-3 assume !(1 == ~E_1~0); 1541463#L1372-3 assume 1 == ~E_2~0;~E_2~0 := 2; 1541453#L1377-3 assume 1 == ~E_3~0;~E_3~0 := 2; 1541439#L1382-3 assume 1 == ~E_4~0;~E_4~0 := 2; 1541438#L1387-3 assume 1 == ~E_5~0;~E_5~0 := 2; 1529060#L1392-3 assume 1 == ~E_6~0;~E_6~0 := 2; 1541418#L1397-3 assume 1 == ~E_7~0;~E_7~0 := 2; 1541408#L1402-3 assume 1 == ~E_8~0;~E_8~0 := 2; 1541398#L1407-3 assume !(1 == ~E_9~0); 1541393#L1412-3 assume 1 == ~E_10~0;~E_10~0 := 2; 1541388#L1417-3 assume 1 == ~E_11~0;~E_11~0 := 2; 1541382#L1422-3 assume 1 == ~E_12~0;~E_12~0 := 2; 1541377#L1427-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 1541129#L894-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 1541123#L961-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 1541122#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret32#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret32#1;havoc start_simulation_#t~ret32#1; 1541119#L1787 assume !(0 == start_simulation_~tmp~3#1); 1541116#L1787-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret31#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 1541040#L894-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 1541026#L961-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 1541024#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret31#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret31#1;havoc stop_simulation_#t~ret31#1; 1541021#L1742 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 1541019#L1749 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 1541017#stop_simulation_returnLabel#1 start_simulation_#t~ret33#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret31#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret33#1;havoc start_simulation_#t~ret33#1; 1541016#L1800 assume !(0 != start_simulation_~tmp___0~1#1); 1247183#L1768-2 [2023-11-12 02:14:17,728 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-12 02:14:17,728 INFO L85 PathProgramCache]: Analyzing trace with hash -1390345197, now seen corresponding path program 1 times [2023-11-12 02:14:17,728 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-12 02:14:17,729 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [299612348] [2023-11-12 02:14:17,729 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-12 02:14:17,729 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-12 02:14:17,747 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-12 02:14:17,818 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-12 02:14:17,818 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-12 02:14:17,818 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [299612348] [2023-11-12 02:14:17,819 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [299612348] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-12 02:14:17,819 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-12 02:14:17,819 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-12 02:14:17,819 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1389910761] [2023-11-12 02:14:17,819 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-12 02:14:17,820 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-12 02:14:17,820 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-12 02:14:17,820 INFO L85 PathProgramCache]: Analyzing trace with hash 1872676890, now seen corresponding path program 1 times [2023-11-12 02:14:17,820 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-12 02:14:17,821 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [430689245] [2023-11-12 02:14:17,821 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-12 02:14:17,821 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-12 02:14:17,836 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-12 02:14:17,878 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-12 02:14:17,878 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-12 02:14:17,878 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [430689245] [2023-11-12 02:14:17,879 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [430689245] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-12 02:14:17,879 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-12 02:14:17,879 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-12 02:14:17,879 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1099872549] [2023-11-12 02:14:17,879 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-12 02:14:17,880 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-12 02:14:17,880 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-12 02:14:17,880 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2023-11-12 02:14:17,880 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2023-11-12 02:14:17,881 INFO L87 Difference]: Start difference. First operand 309325 states and 439555 transitions. cyclomatic complexity: 130246 Second operand has 4 states, 4 states have (on average 37.0) internal successors, (148), 3 states have internal predecessors, (148), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-12 02:14:20,922 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-12 02:14:20,923 INFO L93 Difference]: Finished difference Result 743468 states and 1050816 transitions. [2023-11-12 02:14:20,923 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 743468 states and 1050816 transitions.