./Ultimate.py --spec ../../sv-benchmarks/c/properties/termination.prp --file ../../sv-benchmarks/c/systemc/pc_sfifo_2.cil-2.c --full-output --architecture 32bit -------------------------------------------------------------------------------- Checking for termination Using default analysis Version 9bd2c7ff Calling Ultimate with: /usr/lib/jvm/java-1.11.0-openjdk-amd64/bin/java -Dosgi.configuration.area=/tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4334fb4b-5faa-4749-a3d0-a7ded1eaf4de/bin/uautomizer-verify-uCwYo4JHxu/data/config -Xmx15G -Xms4m -jar /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4334fb4b-5faa-4749-a3d0-a7ded1eaf4de/bin/uautomizer-verify-uCwYo4JHxu/plugins/org.eclipse.equinox.launcher_1.5.800.v20200727-1323.jar -data @noDefault -ultimatedata /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4334fb4b-5faa-4749-a3d0-a7ded1eaf4de/bin/uautomizer-verify-uCwYo4JHxu/data -tc /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4334fb4b-5faa-4749-a3d0-a7ded1eaf4de/bin/uautomizer-verify-uCwYo4JHxu/config/AutomizerTermination.xml -i ../../sv-benchmarks/c/systemc/pc_sfifo_2.cil-2.c -s /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4334fb4b-5faa-4749-a3d0-a7ded1eaf4de/bin/uautomizer-verify-uCwYo4JHxu/config/svcomp-Termination-32bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4334fb4b-5faa-4749-a3d0-a7ded1eaf4de/bin/uautomizer-verify-uCwYo4JHxu --witnessprinter.witness.filename witness --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(F end) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 32bit --witnessprinter.graph.data.programhash 5adc3402a12b42bc2aef7c382784898827eb467d1d3955bed162b3bd231708de --- Real Ultimate output --- This is Ultimate 0.2.3-dev-9bd2c7f [2023-11-19 07:48:46,892 INFO L188 SettingsManager]: Resetting all preferences to default values... [2023-11-19 07:48:46,987 INFO L114 SettingsManager]: Loading settings from /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4334fb4b-5faa-4749-a3d0-a7ded1eaf4de/bin/uautomizer-verify-uCwYo4JHxu/config/svcomp-Termination-32bit-Automizer_Default.epf [2023-11-19 07:48:46,992 WARN L101 SettingsManager]: Preference file contains the following unknown settings: [2023-11-19 07:48:46,992 WARN L103 SettingsManager]: * de.uni_freiburg.informatik.ultimate.core.Log level for class [2023-11-19 07:48:47,018 INFO L130 SettingsManager]: Preferences different from defaults after loading the file: [2023-11-19 07:48:47,019 INFO L151 SettingsManager]: Preferences of UltimateCore differ from their defaults: [2023-11-19 07:48:47,020 INFO L153 SettingsManager]: * Log level for class=de.uni_freiburg.informatik.ultimate.lib.smtlibutils.quantifier.QuantifierPusher=ERROR; [2023-11-19 07:48:47,021 INFO L151 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2023-11-19 07:48:47,022 INFO L153 SettingsManager]: * Create parallel compositions if possible=false [2023-11-19 07:48:47,022 INFO L153 SettingsManager]: * Use SBE=true [2023-11-19 07:48:47,023 INFO L151 SettingsManager]: Preferences of BuchiAutomizer differ from their defaults: [2023-11-19 07:48:47,024 INFO L153 SettingsManager]: * NCSB implementation=INTSET_LAZY3 [2023-11-19 07:48:47,024 INFO L153 SettingsManager]: * Use old map elimination=false [2023-11-19 07:48:47,025 INFO L153 SettingsManager]: * Use external solver (rank synthesis)=false [2023-11-19 07:48:47,025 INFO L153 SettingsManager]: * Use only trivial implications for array writes=true [2023-11-19 07:48:47,026 INFO L153 SettingsManager]: * Rank analysis=LINEAR_WITH_GUESSES [2023-11-19 07:48:47,027 INFO L151 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2023-11-19 07:48:47,027 INFO L153 SettingsManager]: * Pointer base address is valid at dereference=ASSUME [2023-11-19 07:48:47,028 INFO L153 SettingsManager]: * sizeof long=4 [2023-11-19 07:48:47,029 INFO L153 SettingsManager]: * Overapproximate operations on floating types=true [2023-11-19 07:48:47,029 INFO L153 SettingsManager]: * sizeof POINTER=4 [2023-11-19 07:48:47,030 INFO L153 SettingsManager]: * Check division by zero=IGNORE [2023-11-19 07:48:47,030 INFO L153 SettingsManager]: * Pointer to allocated memory at dereference=ASSUME [2023-11-19 07:48:47,031 INFO L153 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=ASSUME [2023-11-19 07:48:47,031 INFO L153 SettingsManager]: * Check array bounds for arrays that are off heap=ASSUME [2023-11-19 07:48:47,032 INFO L153 SettingsManager]: * Check unreachability of reach_error function=false [2023-11-19 07:48:47,032 INFO L153 SettingsManager]: * sizeof long double=12 [2023-11-19 07:48:47,033 INFO L153 SettingsManager]: * Check if freed pointer was valid=false [2023-11-19 07:48:47,033 INFO L153 SettingsManager]: * Assume nondeterminstic values are in range=false [2023-11-19 07:48:47,034 INFO L153 SettingsManager]: * Use constant arrays=true [2023-11-19 07:48:47,034 INFO L151 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2023-11-19 07:48:47,035 INFO L153 SettingsManager]: * Size of a code block=SequenceOfStatements [2023-11-19 07:48:47,036 INFO L151 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2023-11-19 07:48:47,037 INFO L153 SettingsManager]: * Trace refinement strategy=CAMEL [2023-11-19 07:48:47,037 INFO L151 SettingsManager]: Preferences of IcfgTransformer differ from their defaults: [2023-11-19 07:48:47,038 INFO L153 SettingsManager]: * TransformationType=MODULO_NEIGHBOR WARNING: An illegal reflective access operation has occurred WARNING: Illegal reflective access by com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 (file:/tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4334fb4b-5faa-4749-a3d0-a7ded1eaf4de/bin/uautomizer-verify-uCwYo4JHxu/plugins/com.sun.xml.bind_2.2.0.v201505121915.jar) to method java.lang.ClassLoader.defineClass(java.lang.String,byte[],int,int) WARNING: Please consider reporting this to the maintainers of com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 WARNING: Use --illegal-access=warn to enable warnings of further illegal reflective access operations WARNING: All illegal access operations will be denied in a future release Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4334fb4b-5faa-4749-a3d0-a7ded1eaf4de/bin/uautomizer-verify-uCwYo4JHxu Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(F end) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 32bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> 5adc3402a12b42bc2aef7c382784898827eb467d1d3955bed162b3bd231708de [2023-11-19 07:48:47,296 INFO L75 nceAwareModelManager]: Repository-Root is: /tmp [2023-11-19 07:48:47,320 INFO L261 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2023-11-19 07:48:47,323 INFO L217 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2023-11-19 07:48:47,324 INFO L270 PluginConnector]: Initializing CDTParser... [2023-11-19 07:48:47,325 INFO L274 PluginConnector]: CDTParser initialized [2023-11-19 07:48:47,327 INFO L431 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4334fb4b-5faa-4749-a3d0-a7ded1eaf4de/bin/uautomizer-verify-uCwYo4JHxu/../../sv-benchmarks/c/systemc/pc_sfifo_2.cil-2.c [2023-11-19 07:48:50,483 INFO L533 CDTParser]: Created temporary CDT project at NULL [2023-11-19 07:48:50,777 INFO L384 CDTParser]: Found 1 translation units. [2023-11-19 07:48:50,780 INFO L180 CDTParser]: Scanning /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4334fb4b-5faa-4749-a3d0-a7ded1eaf4de/sv-benchmarks/c/systemc/pc_sfifo_2.cil-2.c [2023-11-19 07:48:50,800 INFO L427 CDTParser]: About to delete temporary CDT project at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4334fb4b-5faa-4749-a3d0-a7ded1eaf4de/bin/uautomizer-verify-uCwYo4JHxu/data/d78e96cce/eb77e13ce8424cbe95c03062d64ba100/FLAG0dfb7eeee [2023-11-19 07:48:50,822 INFO L435 CDTParser]: Successfully deleted /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4334fb4b-5faa-4749-a3d0-a7ded1eaf4de/bin/uautomizer-verify-uCwYo4JHxu/data/d78e96cce/eb77e13ce8424cbe95c03062d64ba100 [2023-11-19 07:48:50,827 INFO L299 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2023-11-19 07:48:50,829 INFO L133 ToolchainWalker]: Walking toolchain with 6 elements. [2023-11-19 07:48:50,831 INFO L112 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2023-11-19 07:48:50,831 INFO L270 PluginConnector]: Initializing CACSL2BoogieTranslator... [2023-11-19 07:48:50,837 INFO L274 PluginConnector]: CACSL2BoogieTranslator initialized [2023-11-19 07:48:50,837 INFO L184 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 19.11 07:48:50" (1/1) ... [2023-11-19 07:48:50,838 INFO L204 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@32b0986b and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 19.11 07:48:50, skipping insertion in model container [2023-11-19 07:48:50,839 INFO L184 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 19.11 07:48:50" (1/1) ... [2023-11-19 07:48:50,877 INFO L177 MainTranslator]: Built tables and reachable declarations [2023-11-19 07:48:51,071 INFO L209 PostProcessor]: Analyzing one entry point: main [2023-11-19 07:48:51,086 INFO L202 MainTranslator]: Completed pre-run [2023-11-19 07:48:51,144 INFO L209 PostProcessor]: Analyzing one entry point: main [2023-11-19 07:48:51,162 INFO L206 MainTranslator]: Completed translation [2023-11-19 07:48:51,162 INFO L201 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 19.11 07:48:51 WrapperNode [2023-11-19 07:48:51,163 INFO L131 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2023-11-19 07:48:51,164 INFO L112 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2023-11-19 07:48:51,164 INFO L270 PluginConnector]: Initializing Boogie Procedure Inliner... [2023-11-19 07:48:51,164 INFO L274 PluginConnector]: Boogie Procedure Inliner initialized [2023-11-19 07:48:51,172 INFO L184 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 19.11 07:48:51" (1/1) ... [2023-11-19 07:48:51,180 INFO L184 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 19.11 07:48:51" (1/1) ... [2023-11-19 07:48:51,217 INFO L138 Inliner]: procedures = 29, calls = 33, calls flagged for inlining = 28, calls inlined = 31, statements flattened = 313 [2023-11-19 07:48:51,219 INFO L131 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2023-11-19 07:48:51,220 INFO L112 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2023-11-19 07:48:51,220 INFO L270 PluginConnector]: Initializing Boogie Preprocessor... [2023-11-19 07:48:51,221 INFO L274 PluginConnector]: Boogie Preprocessor initialized [2023-11-19 07:48:51,230 INFO L184 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 19.11 07:48:51" (1/1) ... [2023-11-19 07:48:51,231 INFO L184 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 19.11 07:48:51" (1/1) ... [2023-11-19 07:48:51,234 INFO L184 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 19.11 07:48:51" (1/1) ... [2023-11-19 07:48:51,235 INFO L184 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 19.11 07:48:51" (1/1) ... [2023-11-19 07:48:51,257 INFO L184 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 19.11 07:48:51" (1/1) ... [2023-11-19 07:48:51,263 INFO L184 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 19.11 07:48:51" (1/1) ... [2023-11-19 07:48:51,265 INFO L184 PluginConnector]: Executing the observer LTLStepAnnotator from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 19.11 07:48:51" (1/1) ... [2023-11-19 07:48:51,278 INFO L184 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 19.11 07:48:51" (1/1) ... [2023-11-19 07:48:51,281 INFO L131 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2023-11-19 07:48:51,282 INFO L112 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2023-11-19 07:48:51,283 INFO L270 PluginConnector]: Initializing RCFGBuilder... [2023-11-19 07:48:51,283 INFO L274 PluginConnector]: RCFGBuilder initialized [2023-11-19 07:48:51,284 INFO L184 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 19.11 07:48:51" (1/1) ... [2023-11-19 07:48:51,292 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2023-11-19 07:48:51,309 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4334fb4b-5faa-4749-a3d0-a7ded1eaf4de/bin/uautomizer-verify-uCwYo4JHxu/z3 [2023-11-19 07:48:51,322 INFO L229 MonitoredProcess]: Starting monitored process 1 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4334fb4b-5faa-4749-a3d0-a7ded1eaf4de/bin/uautomizer-verify-uCwYo4JHxu/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2023-11-19 07:48:51,343 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4334fb4b-5faa-4749-a3d0-a7ded1eaf4de/bin/uautomizer-verify-uCwYo4JHxu/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (1)] Waiting until timeout for monitored process [2023-11-19 07:48:51,362 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocInit [2023-11-19 07:48:51,362 INFO L130 BoogieDeclarations]: Found specification of procedure write~init~int [2023-11-19 07:48:51,362 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2023-11-19 07:48:51,363 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2023-11-19 07:48:51,446 INFO L236 CfgBuilder]: Building ICFG [2023-11-19 07:48:51,448 INFO L262 CfgBuilder]: Building CFG for each procedure with an implementation [2023-11-19 07:48:51,814 INFO L277 CfgBuilder]: Performing block encoding [2023-11-19 07:48:51,824 INFO L297 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2023-11-19 07:48:51,824 INFO L302 CfgBuilder]: Removed 4 assume(true) statements. [2023-11-19 07:48:51,829 INFO L201 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 19.11 07:48:51 BoogieIcfgContainer [2023-11-19 07:48:51,830 INFO L131 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2023-11-19 07:48:51,831 INFO L112 PluginConnector]: ------------------------BuchiAutomizer---------------------------- [2023-11-19 07:48:51,831 INFO L270 PluginConnector]: Initializing BuchiAutomizer... [2023-11-19 07:48:51,836 INFO L274 PluginConnector]: BuchiAutomizer initialized [2023-11-19 07:48:51,837 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2023-11-19 07:48:51,837 INFO L184 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "CDTParser AST 19.11 07:48:50" (1/3) ... [2023-11-19 07:48:51,838 INFO L204 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@675d422e and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 19.11 07:48:51, skipping insertion in model container [2023-11-19 07:48:51,839 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2023-11-19 07:48:51,839 INFO L184 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 19.11 07:48:51" (2/3) ... [2023-11-19 07:48:51,839 INFO L204 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@675d422e and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 19.11 07:48:51, skipping insertion in model container [2023-11-19 07:48:51,843 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2023-11-19 07:48:51,843 INFO L184 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 19.11 07:48:51" (3/3) ... [2023-11-19 07:48:51,845 INFO L332 chiAutomizerObserver]: Analyzing ICFG pc_sfifo_2.cil-2.c [2023-11-19 07:48:51,946 INFO L303 stractBuchiCegarLoop]: Interprodecural is true [2023-11-19 07:48:51,946 INFO L304 stractBuchiCegarLoop]: Hoare is false [2023-11-19 07:48:51,947 INFO L305 stractBuchiCegarLoop]: Compute interpolants for ForwardPredicates [2023-11-19 07:48:51,947 INFO L306 stractBuchiCegarLoop]: Backedges is STRAIGHT_LINE [2023-11-19 07:48:51,947 INFO L307 stractBuchiCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2023-11-19 07:48:51,947 INFO L308 stractBuchiCegarLoop]: Difference is false [2023-11-19 07:48:51,948 INFO L309 stractBuchiCegarLoop]: Minimize is MINIMIZE_SEVPA [2023-11-19 07:48:51,948 INFO L313 stractBuchiCegarLoop]: ======== Iteration 0 == of CEGAR loop == BuchiAutomatonCegarLoop ======== [2023-11-19 07:48:51,956 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 108 states, 107 states have (on average 1.514018691588785) internal successors, (162), 107 states have internal predecessors, (162), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-19 07:48:52,001 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 72 [2023-11-19 07:48:52,003 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-19 07:48:52,003 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-19 07:48:52,014 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-19 07:48:52,015 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-19 07:48:52,015 INFO L335 stractBuchiCegarLoop]: ======== Iteration 1 ============ [2023-11-19 07:48:52,018 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 108 states, 107 states have (on average 1.514018691588785) internal successors, (162), 107 states have internal predecessors, (162), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-19 07:48:52,036 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 72 [2023-11-19 07:48:52,038 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-19 07:48:52,038 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-19 07:48:52,042 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-19 07:48:52,043 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-19 07:48:52,054 INFO L748 eck$LassoCheckResult]: Stem: 19#$Ultimate##0true assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(19, 2);call #Ultimate.allocInit(12, 3);~q_buf_0~0 := 0;~q_free~0 := 0;~q_read_ev~0 := 0;~q_write_ev~0 := 0;~q_req_up~0 := 0;~q_ev~0 := 0;~p_num_write~0 := 0;~p_last_write~0 := 0;~p_dw_st~0 := 0;~p_dw_pc~0 := 0;~p_dw_i~0 := 0;~c_num_read~0 := 0;~c_last_read~0 := 0;~c_dr_st~0 := 0;~c_dr_pc~0 := 0;~c_dr_i~0 := 0;~a_t~0 := 0; 31#L-1true assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~3#1;havoc main_~__retres1~3#1;assume { :begin_inline_init_model } true;~q_free~0 := 1;~q_write_ev~0 := 2;~q_read_ev~0 := ~q_write_ev~0;~p_num_write~0 := 0;~p_dw_pc~0 := 0;~p_dw_i~0 := 1;~c_num_read~0 := 0;~c_dr_pc~0 := 0;~c_dr_i~0 := 1; 104#init_model_returnLabel#1true assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret13#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~4#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~4#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 65#L222true assume !(1 == ~q_req_up~0); 9#L222-2true assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 82#L237true assume 1 == ~p_dw_i~0;~p_dw_st~0 := 0; 32#L237-2true assume !(1 == ~c_dr_i~0);~c_dr_st~0 := 2; 39#L242-1true assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 89#L275true assume !(0 == ~q_read_ev~0); 96#L275-2true assume !(0 == ~q_write_ev~0); 23#L280-1true assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;assume { :begin_inline_is_do_write_p_triggered } true;havoc is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;havoc is_do_write_p_triggered_~__retres1~0#1; 109#L65true assume !(1 == ~p_dw_pc~0); 30#L65-2true is_do_write_p_triggered_~__retres1~0#1 := 0; 56#L76true is_do_write_p_triggered_#res#1 := is_do_write_p_triggered_~__retres1~0#1; 76#is_do_write_p_triggered_returnLabel#1true activate_threads_#t~ret7#1 := is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;assume { :end_inline_is_do_write_p_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1; 36#L315true assume !(0 != activate_threads_~tmp~1#1); 63#L315-2true assume { :begin_inline_is_do_read_c_triggered } true;havoc is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;havoc is_do_read_c_triggered_~__retres1~1#1; 99#L84true assume 1 == ~c_dr_pc~0; 25#L85true assume 1 == ~q_write_ev~0;is_do_read_c_triggered_~__retres1~1#1 := 1; 69#L95true is_do_read_c_triggered_#res#1 := is_do_read_c_triggered_~__retres1~1#1; 21#is_do_read_c_triggered_returnLabel#1true activate_threads_#t~ret8#1 := is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;assume { :end_inline_is_do_read_c_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 4#L323true assume !(0 != activate_threads_~tmp___0~1#1); 47#L323-2true havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 100#L293true assume !(1 == ~q_read_ev~0); 2#L293-2true assume 1 == ~q_write_ev~0;~q_write_ev~0 := 2; 37#L298-1true assume { :end_inline_reset_delta_events } true; 11#L419-2true [2023-11-19 07:48:52,056 INFO L750 eck$LassoCheckResult]: Loop: 11#L419-2true assume !false; 27#L420true start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret9#1, eval_#t~nondet10#1, eval_#t~nondet11#1, eval_~tmp~2#1, eval_~tmp___0~2#1, eval_~tmp___1~0#1;havoc eval_~tmp~2#1;havoc eval_~tmp___0~2#1;havoc eval_~tmp___1~0#1; 105#L364true assume false; 66#eval_returnLabel#1true havoc eval_#t~ret9#1, eval_#t~nondet10#1, eval_#t~nondet11#1, eval_~tmp~2#1, eval_~tmp___0~2#1, eval_~tmp___1~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 85#L222-3true assume !(1 == ~q_req_up~0); 33#L222-5true assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 81#L275-3true assume 0 == ~q_read_ev~0;~q_read_ev~0 := 1; 41#L275-5true assume 0 == ~q_write_ev~0;~q_write_ev~0 := 1; 54#L280-3true assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;assume { :begin_inline_is_do_write_p_triggered } true;havoc is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;havoc is_do_write_p_triggered_~__retres1~0#1; 61#L65-3true assume !(1 == ~p_dw_pc~0); 17#L65-5true is_do_write_p_triggered_~__retres1~0#1 := 0; 97#L76-1true is_do_write_p_triggered_#res#1 := is_do_write_p_triggered_~__retres1~0#1; 55#is_do_write_p_triggered_returnLabel#2true activate_threads_#t~ret7#1 := is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;assume { :end_inline_is_do_write_p_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1; 42#L315-3true assume 0 != activate_threads_~tmp~1#1;~p_dw_st~0 := 0; 86#L315-5true assume { :begin_inline_is_do_read_c_triggered } true;havoc is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;havoc is_do_read_c_triggered_~__retres1~1#1; 59#L84-3true assume 1 == ~c_dr_pc~0; 44#L85-1true assume 1 == ~q_write_ev~0;is_do_read_c_triggered_~__retres1~1#1 := 1; 80#L95-1true is_do_read_c_triggered_#res#1 := is_do_read_c_triggered_~__retres1~1#1; 29#is_do_read_c_triggered_returnLabel#2true activate_threads_#t~ret8#1 := is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;assume { :end_inline_is_do_read_c_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 107#L323-3true assume 0 != activate_threads_~tmp___0~1#1;~c_dr_st~0 := 0; 79#L323-5true havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 93#L293-3true assume 1 == ~q_read_ev~0;~q_read_ev~0 := 2; 5#L293-5true assume 1 == ~q_write_ev~0;~q_write_ev~0 := 2; 53#L298-3true assume { :end_inline_reset_delta_events } true;assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret12#1, stop_simulation_~tmp~3#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~3#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 24#L255-1true assume 0 == ~p_dw_st~0;exists_runnable_thread_~__retres1~2#1 := 1; 26#L267-1true exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 77#exists_runnable_thread_returnLabel#2true stop_simulation_#t~ret12#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~3#1 := stop_simulation_#t~ret12#1;havoc stop_simulation_#t~ret12#1; 13#L394true assume !(0 != stop_simulation_~tmp~3#1);stop_simulation_~__retres2~0#1 := 1; 7#L401true stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 106#stop_simulation_returnLabel#1true start_simulation_#t~ret13#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret12#1, stop_simulation_~tmp~3#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp~4#1 := start_simulation_#t~ret13#1;havoc start_simulation_#t~ret13#1; 28#L436true assume !(0 != start_simulation_~tmp~4#1); 11#L419-2true [2023-11-19 07:48:52,067 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-19 07:48:52,068 INFO L85 PathProgramCache]: Analyzing trace with hash -239976594, now seen corresponding path program 1 times [2023-11-19 07:48:52,079 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-19 07:48:52,079 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [816270963] [2023-11-19 07:48:52,080 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-19 07:48:52,081 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-19 07:48:52,213 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-19 07:48:52,356 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-19 07:48:52,356 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-19 07:48:52,357 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [816270963] [2023-11-19 07:48:52,358 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [816270963] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-19 07:48:52,358 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-19 07:48:52,358 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-19 07:48:52,360 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1804485774] [2023-11-19 07:48:52,361 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-19 07:48:52,366 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-19 07:48:52,367 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-19 07:48:52,367 INFO L85 PathProgramCache]: Analyzing trace with hash 1757542019, now seen corresponding path program 1 times [2023-11-19 07:48:52,367 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-19 07:48:52,367 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [491047419] [2023-11-19 07:48:52,368 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-19 07:48:52,368 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-19 07:48:52,378 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-19 07:48:52,393 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-19 07:48:52,394 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-19 07:48:52,394 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [491047419] [2023-11-19 07:48:52,394 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [491047419] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-19 07:48:52,394 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-19 07:48:52,395 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2023-11-19 07:48:52,395 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1504650010] [2023-11-19 07:48:52,395 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-19 07:48:52,396 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-19 07:48:52,397 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-19 07:48:52,432 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-19 07:48:52,432 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-19 07:48:52,435 INFO L87 Difference]: Start difference. First operand has 108 states, 107 states have (on average 1.514018691588785) internal successors, (162), 107 states have internal predecessors, (162), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand has 3 states, 3 states have (on average 8.666666666666666) internal successors, (26), 3 states have internal predecessors, (26), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-19 07:48:52,461 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-19 07:48:52,462 INFO L93 Difference]: Finished difference Result 102 states and 144 transitions. [2023-11-19 07:48:52,463 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 102 states and 144 transitions. [2023-11-19 07:48:52,467 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 63 [2023-11-19 07:48:52,473 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 102 states to 95 states and 137 transitions. [2023-11-19 07:48:52,474 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 95 [2023-11-19 07:48:52,475 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 95 [2023-11-19 07:48:52,476 INFO L73 IsDeterministic]: Start isDeterministic. Operand 95 states and 137 transitions. [2023-11-19 07:48:52,477 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-19 07:48:52,477 INFO L218 hiAutomatonCegarLoop]: Abstraction has 95 states and 137 transitions. [2023-11-19 07:48:52,496 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 95 states and 137 transitions. [2023-11-19 07:48:52,510 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 95 to 95. [2023-11-19 07:48:52,512 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 95 states, 95 states have (on average 1.4421052631578948) internal successors, (137), 94 states have internal predecessors, (137), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-19 07:48:52,513 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 95 states to 95 states and 137 transitions. [2023-11-19 07:48:52,515 INFO L240 hiAutomatonCegarLoop]: Abstraction has 95 states and 137 transitions. [2023-11-19 07:48:52,516 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-19 07:48:52,520 INFO L428 stractBuchiCegarLoop]: Abstraction has 95 states and 137 transitions. [2023-11-19 07:48:52,520 INFO L335 stractBuchiCegarLoop]: ======== Iteration 2 ============ [2023-11-19 07:48:52,521 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 95 states and 137 transitions. [2023-11-19 07:48:52,523 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 63 [2023-11-19 07:48:52,523 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-19 07:48:52,523 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-19 07:48:52,525 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-19 07:48:52,525 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-19 07:48:52,526 INFO L748 eck$LassoCheckResult]: Stem: 276#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(19, 2);call #Ultimate.allocInit(12, 3);~q_buf_0~0 := 0;~q_free~0 := 0;~q_read_ev~0 := 0;~q_write_ev~0 := 0;~q_req_up~0 := 0;~q_ev~0 := 0;~p_num_write~0 := 0;~p_last_write~0 := 0;~p_dw_st~0 := 0;~p_dw_pc~0 := 0;~p_dw_i~0 := 0;~c_num_read~0 := 0;~c_last_read~0 := 0;~c_dr_st~0 := 0;~c_dr_pc~0 := 0;~c_dr_i~0 := 0;~a_t~0 := 0; 277#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~3#1;havoc main_~__retres1~3#1;assume { :begin_inline_init_model } true;~q_free~0 := 1;~q_write_ev~0 := 2;~q_read_ev~0 := ~q_write_ev~0;~p_num_write~0 := 0;~p_dw_pc~0 := 0;~p_dw_i~0 := 1;~c_num_read~0 := 0;~c_dr_pc~0 := 0;~c_dr_i~0 := 1; 301#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret13#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~4#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~4#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 254#L222 assume !(1 == ~q_req_up~0); 243#L222-2 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 244#L237 assume 1 == ~p_dw_i~0;~p_dw_st~0 := 0; 284#L237-2 assume 1 == ~c_dr_i~0;~c_dr_st~0 := 0; 305#L242-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 303#L275 assume !(0 == ~q_read_ev~0); 304#L275-2 assume !(0 == ~q_write_ev~0); 290#L280-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;assume { :begin_inline_is_do_write_p_triggered } true;havoc is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;havoc is_do_write_p_triggered_~__retres1~0#1; 291#L65 assume !(1 == ~p_dw_pc~0); 287#L65-2 is_do_write_p_triggered_~__retres1~0#1 := 0; 286#L76 is_do_write_p_triggered_#res#1 := is_do_write_p_triggered_~__retres1~0#1; 271#is_do_write_p_triggered_returnLabel#1 activate_threads_#t~ret7#1 := is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;assume { :end_inline_is_do_write_p_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1; 272#L315 assume !(0 != activate_threads_~tmp~1#1); 249#L315-2 assume { :begin_inline_is_do_read_c_triggered } true;havoc is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;havoc is_do_read_c_triggered_~__retres1~1#1; 250#L84 assume 1 == ~c_dr_pc~0; 296#L85 assume 1 == ~q_write_ev~0;is_do_read_c_triggered_~__retres1~1#1 := 1; 263#L95 is_do_read_c_triggered_#res#1 := is_do_read_c_triggered_~__retres1~1#1; 264#is_do_read_c_triggered_returnLabel#1 activate_threads_#t~ret8#1 := is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;assume { :end_inline_is_do_read_c_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 226#L323 assume !(0 != activate_threads_~tmp___0~1#1); 227#L323-2 havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 312#L293 assume !(1 == ~q_read_ev~0); 219#L293-2 assume 1 == ~q_write_ev~0;~q_write_ev~0 := 2; 220#L298-1 assume { :end_inline_reset_delta_events } true; 245#L419-2 [2023-11-19 07:48:52,526 INFO L750 eck$LassoCheckResult]: Loop: 245#L419-2 assume !false; 246#L420 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret9#1, eval_#t~nondet10#1, eval_#t~nondet11#1, eval_~tmp~2#1, eval_~tmp___0~2#1, eval_~tmp___1~0#1;havoc eval_~tmp~2#1;havoc eval_~tmp___0~2#1;havoc eval_~tmp___1~0#1; 261#L364 assume !false; 292#L340 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 256#L255 assume 0 == ~p_dw_st~0;exists_runnable_thread_~__retres1~2#1 := 1; 222#L267 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 241#exists_runnable_thread_returnLabel#1 eval_#t~ret9#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp___1~0#1 := eval_#t~ret9#1;havoc eval_#t~ret9#1; 242#L344 assume !(0 != eval_~tmp___1~0#1); 257#eval_returnLabel#1 havoc eval_#t~ret9#1, eval_#t~nondet10#1, eval_#t~nondet11#1, eval_~tmp~2#1, eval_~tmp___0~2#1, eval_~tmp___1~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 258#L222-3 assume !(1 == ~q_req_up~0); 289#L222-5 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 282#L275-3 assume 0 == ~q_read_ev~0;~q_read_ev~0 := 1; 283#L275-5 assume 0 == ~q_write_ev~0;~q_write_ev~0 := 1; 310#L280-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;assume { :begin_inline_is_do_write_p_triggered } true;havoc is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;havoc is_do_write_p_triggered_~__retres1~0#1; 232#L65-3 assume 1 == ~p_dw_pc~0; 233#L66-1 assume 1 == ~q_read_ev~0;is_do_write_p_triggered_~__retres1~0#1 := 1; 267#L76-1 is_do_write_p_triggered_#res#1 := is_do_write_p_triggered_~__retres1~0#1; 309#is_do_write_p_triggered_returnLabel#2 activate_threads_#t~ret7#1 := is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;assume { :end_inline_is_do_write_p_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1; 311#L315-3 assume 0 != activate_threads_~tmp~1#1;~p_dw_st~0 := 0; 299#L315-5 assume { :begin_inline_is_do_read_c_triggered } true;havoc is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;havoc is_do_read_c_triggered_~__retres1~1#1; 223#L84-3 assume !(1 == ~c_dr_pc~0); 224#L84-5 is_do_read_c_triggered_~__retres1~1#1 := 0; 280#L95-1 is_do_read_c_triggered_#res#1 := is_do_read_c_triggered_~__retres1~1#1; 281#is_do_read_c_triggered_returnLabel#2 activate_threads_#t~ret8#1 := is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;assume { :end_inline_is_do_read_c_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 298#L323-3 assume 0 != activate_threads_~tmp___0~1#1;~c_dr_st~0 := 0; 278#L323-5 havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 279#L293-3 assume 1 == ~q_read_ev~0;~q_read_ev~0 := 2; 230#L293-5 assume 1 == ~q_write_ev~0;~q_write_ev~0 := 2; 231#L298-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret12#1, stop_simulation_~tmp~3#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~3#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 293#L255-1 assume 0 == ~p_dw_st~0;exists_runnable_thread_~__retres1~2#1 := 1; 294#L267-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 273#exists_runnable_thread_returnLabel#2 stop_simulation_#t~ret12#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~3#1 := stop_simulation_#t~ret12#1;havoc stop_simulation_#t~ret12#1; 251#L394 assume !(0 != stop_simulation_~tmp~3#1);stop_simulation_~__retres2~0#1 := 1; 237#L401 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 238#stop_simulation_returnLabel#1 start_simulation_#t~ret13#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret12#1, stop_simulation_~tmp~3#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp~4#1 := start_simulation_#t~ret13#1;havoc start_simulation_#t~ret13#1; 297#L436 assume !(0 != start_simulation_~tmp~4#1); 245#L419-2 [2023-11-19 07:48:52,527 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-19 07:48:52,528 INFO L85 PathProgramCache]: Analyzing trace with hash 577671856, now seen corresponding path program 1 times [2023-11-19 07:48:52,528 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-19 07:48:52,528 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2034299758] [2023-11-19 07:48:52,528 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-19 07:48:52,529 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-19 07:48:52,547 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-19 07:48:52,680 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-19 07:48:52,687 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-19 07:48:52,687 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2034299758] [2023-11-19 07:48:52,687 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2034299758] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-19 07:48:52,688 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-19 07:48:52,688 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2023-11-19 07:48:52,688 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [551220506] [2023-11-19 07:48:52,689 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-19 07:48:52,689 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-19 07:48:52,690 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-19 07:48:52,693 INFO L85 PathProgramCache]: Analyzing trace with hash 755463123, now seen corresponding path program 1 times [2023-11-19 07:48:52,693 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-19 07:48:52,694 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [624509657] [2023-11-19 07:48:52,695 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-19 07:48:52,695 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-19 07:48:52,724 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-19 07:48:52,808 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-19 07:48:52,809 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-19 07:48:52,809 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [624509657] [2023-11-19 07:48:52,809 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [624509657] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-19 07:48:52,810 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-19 07:48:52,810 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2023-11-19 07:48:52,810 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1717754475] [2023-11-19 07:48:52,810 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-19 07:48:52,811 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-19 07:48:52,811 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-19 07:48:52,812 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2023-11-19 07:48:52,812 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2023-11-19 07:48:52,813 INFO L87 Difference]: Start difference. First operand 95 states and 137 transitions. cyclomatic complexity: 43 Second operand has 5 states, 5 states have (on average 5.2) internal successors, (26), 4 states have internal predecessors, (26), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-19 07:48:52,952 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-19 07:48:52,952 INFO L93 Difference]: Finished difference Result 312 states and 441 transitions. [2023-11-19 07:48:52,952 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 312 states and 441 transitions. [2023-11-19 07:48:52,960 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 283 [2023-11-19 07:48:52,968 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 312 states to 312 states and 441 transitions. [2023-11-19 07:48:52,969 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 312 [2023-11-19 07:48:52,971 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 312 [2023-11-19 07:48:52,972 INFO L73 IsDeterministic]: Start isDeterministic. Operand 312 states and 441 transitions. [2023-11-19 07:48:52,978 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-19 07:48:52,978 INFO L218 hiAutomatonCegarLoop]: Abstraction has 312 states and 441 transitions. [2023-11-19 07:48:52,979 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 312 states and 441 transitions. [2023-11-19 07:48:53,012 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 312 to 298. [2023-11-19 07:48:53,014 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 298 states, 298 states have (on average 1.4261744966442953) internal successors, (425), 297 states have internal predecessors, (425), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-19 07:48:53,019 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 298 states to 298 states and 425 transitions. [2023-11-19 07:48:53,019 INFO L240 hiAutomatonCegarLoop]: Abstraction has 298 states and 425 transitions. [2023-11-19 07:48:53,023 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2023-11-19 07:48:53,024 INFO L428 stractBuchiCegarLoop]: Abstraction has 298 states and 425 transitions. [2023-11-19 07:48:53,024 INFO L335 stractBuchiCegarLoop]: ======== Iteration 3 ============ [2023-11-19 07:48:53,025 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 298 states and 425 transitions. [2023-11-19 07:48:53,028 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 270 [2023-11-19 07:48:53,029 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-19 07:48:53,030 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-19 07:48:53,032 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-19 07:48:53,034 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-19 07:48:53,034 INFO L748 eck$LassoCheckResult]: Stem: 695#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(19, 2);call #Ultimate.allocInit(12, 3);~q_buf_0~0 := 0;~q_free~0 := 0;~q_read_ev~0 := 0;~q_write_ev~0 := 0;~q_req_up~0 := 0;~q_ev~0 := 0;~p_num_write~0 := 0;~p_last_write~0 := 0;~p_dw_st~0 := 0;~p_dw_pc~0 := 0;~p_dw_i~0 := 0;~c_num_read~0 := 0;~c_last_read~0 := 0;~c_dr_st~0 := 0;~c_dr_pc~0 := 0;~c_dr_i~0 := 0;~a_t~0 := 0; 696#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~3#1;havoc main_~__retres1~3#1;assume { :begin_inline_init_model } true;~q_free~0 := 1;~q_write_ev~0 := 2;~q_read_ev~0 := ~q_write_ev~0;~p_num_write~0 := 0;~p_dw_pc~0 := 0;~p_dw_i~0 := 1;~c_num_read~0 := 0;~c_dr_pc~0 := 0;~c_dr_i~0 := 1; 720#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret13#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~4#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~4#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 673#L222 assume !(1 == ~q_req_up~0); 664#L222-2 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 665#L237 assume 1 == ~p_dw_i~0;~p_dw_st~0 := 0; 703#L237-2 assume 1 == ~c_dr_i~0;~c_dr_st~0 := 0; 726#L242-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 722#L275 assume !(0 == ~q_read_ev~0); 723#L275-2 assume !(0 == ~q_write_ev~0); 710#L280-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;assume { :begin_inline_is_do_write_p_triggered } true;havoc is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;havoc is_do_write_p_triggered_~__retres1~0#1; 711#L65 assume !(1 == ~p_dw_pc~0); 708#L65-2 is_do_write_p_triggered_~__retres1~0#1 := 0; 707#L76 is_do_write_p_triggered_#res#1 := is_do_write_p_triggered_~__retres1~0#1; 691#is_do_write_p_triggered_returnLabel#1 activate_threads_#t~ret7#1 := is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;assume { :end_inline_is_do_write_p_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1; 692#L315 assume !(0 != activate_threads_~tmp~1#1); 670#L315-2 assume { :begin_inline_is_do_read_c_triggered } true;havoc is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;havoc is_do_read_c_triggered_~__retres1~1#1; 671#L84 assume !(1 == ~c_dr_pc~0); 687#L84-2 is_do_read_c_triggered_~__retres1~1#1 := 0; 682#L95 is_do_read_c_triggered_#res#1 := is_do_read_c_triggered_~__retres1~1#1; 683#is_do_read_c_triggered_returnLabel#1 activate_threads_#t~ret8#1 := is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;assume { :end_inline_is_do_read_c_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 647#L323 assume !(0 != activate_threads_~tmp___0~1#1); 648#L323-2 havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 737#L293 assume !(1 == ~q_read_ev~0); 641#L293-2 assume 1 == ~q_write_ev~0;~q_write_ev~0 := 2; 642#L298-1 assume { :end_inline_reset_delta_events } true; 733#L419-2 [2023-11-19 07:48:53,035 INFO L750 eck$LassoCheckResult]: Loop: 733#L419-2 assume !false; 869#L420 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret9#1, eval_#t~nondet10#1, eval_#t~nondet11#1, eval_~tmp~2#1, eval_~tmp___0~2#1, eval_~tmp___1~0#1;havoc eval_~tmp~2#1;havoc eval_~tmp___0~2#1;havoc eval_~tmp___1~0#1; 679#L364 assume !false; 709#L340 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 674#L255 assume 0 == ~p_dw_st~0;exists_runnable_thread_~__retres1~2#1 := 1; 646#L267 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 662#exists_runnable_thread_returnLabel#1 eval_#t~ret9#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp___1~0#1 := eval_#t~ret9#1;havoc eval_#t~ret9#1; 663#L344 assume !(0 != eval_~tmp___1~0#1); 675#eval_returnLabel#1 havoc eval_#t~ret9#1, eval_#t~nondet10#1, eval_#t~nondet11#1, eval_~tmp~2#1, eval_~tmp___0~2#1, eval_~tmp___1~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 676#L222-3 assume !(1 == ~q_req_up~0); 715#L222-5 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 701#L275-3 assume 0 == ~q_read_ev~0;~q_read_ev~0 := 1; 702#L275-5 assume 0 == ~q_write_ev~0;~q_write_ev~0 := 1; 735#L280-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;assume { :begin_inline_is_do_write_p_triggered } true;havoc is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;havoc is_do_write_p_triggered_~__retres1~0#1; 653#L65-3 assume 1 == ~p_dw_pc~0; 654#L66-1 assume 1 == ~q_read_ev~0;is_do_write_p_triggered_~__retres1~0#1 := 1; 686#L76-1 is_do_write_p_triggered_#res#1 := is_do_write_p_triggered_~__retres1~0#1; 734#is_do_write_p_triggered_returnLabel#2 activate_threads_#t~ret7#1 := is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;assume { :end_inline_is_do_write_p_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1; 736#L315-3 assume 0 != activate_threads_~tmp~1#1;~p_dw_st~0 := 0; 718#L315-5 assume { :begin_inline_is_do_read_c_triggered } true;havoc is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;havoc is_do_read_c_triggered_~__retres1~1#1; 643#L84-3 assume !(1 == ~c_dr_pc~0); 644#L84-5 is_do_read_c_triggered_~__retres1~1#1 := 0; 912#L95-1 is_do_read_c_triggered_#res#1 := is_do_read_c_triggered_~__retres1~1#1; 909#is_do_read_c_triggered_returnLabel#2 activate_threads_#t~ret8#1 := is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;assume { :end_inline_is_do_read_c_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 907#L323-3 assume 0 != activate_threads_~tmp___0~1#1;~c_dr_st~0 := 0; 906#L323-5 havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 905#L293-3 assume 1 == ~q_read_ev~0;~q_read_ev~0 := 2; 903#L293-5 assume 1 == ~q_write_ev~0;~q_write_ev~0 := 2; 902#L298-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret12#1, stop_simulation_~tmp~3#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~3#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 896#L255-1 assume 0 == ~p_dw_st~0;exists_runnable_thread_~__retres1~2#1 := 1; 892#L267-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 889#exists_runnable_thread_returnLabel#2 stop_simulation_#t~ret12#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~3#1 := stop_simulation_#t~ret12#1;havoc stop_simulation_#t~ret12#1; 886#L394 assume !(0 != stop_simulation_~tmp~3#1);stop_simulation_~__retres2~0#1 := 1; 878#L401 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 875#stop_simulation_returnLabel#1 start_simulation_#t~ret13#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret12#1, stop_simulation_~tmp~3#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp~4#1 := start_simulation_#t~ret13#1;havoc start_simulation_#t~ret13#1; 874#L436 assume !(0 != start_simulation_~tmp~4#1); 733#L419-2 [2023-11-19 07:48:53,036 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-19 07:48:53,039 INFO L85 PathProgramCache]: Analyzing trace with hash -1617647375, now seen corresponding path program 1 times [2023-11-19 07:48:53,039 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-19 07:48:53,042 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2083673571] [2023-11-19 07:48:53,042 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-19 07:48:53,042 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-19 07:48:53,054 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-19 07:48:53,130 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-19 07:48:53,131 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-19 07:48:53,131 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2083673571] [2023-11-19 07:48:53,131 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2083673571] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-19 07:48:53,132 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-19 07:48:53,132 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2023-11-19 07:48:53,132 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1542167050] [2023-11-19 07:48:53,132 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-19 07:48:53,133 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-19 07:48:53,133 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-19 07:48:53,134 INFO L85 PathProgramCache]: Analyzing trace with hash 755463123, now seen corresponding path program 2 times [2023-11-19 07:48:53,134 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-19 07:48:53,134 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [375549900] [2023-11-19 07:48:53,134 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-19 07:48:53,135 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-19 07:48:53,146 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-19 07:48:53,268 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-19 07:48:53,268 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-19 07:48:53,268 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [375549900] [2023-11-19 07:48:53,269 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [375549900] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-19 07:48:53,269 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-19 07:48:53,270 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2023-11-19 07:48:53,270 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1767577040] [2023-11-19 07:48:53,270 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-19 07:48:53,270 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-19 07:48:53,271 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-19 07:48:53,271 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2023-11-19 07:48:53,271 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2023-11-19 07:48:53,272 INFO L87 Difference]: Start difference. First operand 298 states and 425 transitions. cyclomatic complexity: 129 Second operand has 4 states, 4 states have (on average 6.5) internal successors, (26), 4 states have internal predecessors, (26), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-19 07:48:53,393 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-19 07:48:53,393 INFO L93 Difference]: Finished difference Result 683 states and 947 transitions. [2023-11-19 07:48:53,393 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 683 states and 947 transitions. [2023-11-19 07:48:53,400 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 620 [2023-11-19 07:48:53,406 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 683 states to 683 states and 947 transitions. [2023-11-19 07:48:53,407 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 683 [2023-11-19 07:48:53,408 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 683 [2023-11-19 07:48:53,408 INFO L73 IsDeterministic]: Start isDeterministic. Operand 683 states and 947 transitions. [2023-11-19 07:48:53,409 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-19 07:48:53,409 INFO L218 hiAutomatonCegarLoop]: Abstraction has 683 states and 947 transitions. [2023-11-19 07:48:53,414 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 683 states and 947 transitions. [2023-11-19 07:48:53,450 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 683 to 683. [2023-11-19 07:48:53,452 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 683 states, 683 states have (on average 1.3865300146412884) internal successors, (947), 682 states have internal predecessors, (947), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-19 07:48:53,456 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 683 states to 683 states and 947 transitions. [2023-11-19 07:48:53,456 INFO L240 hiAutomatonCegarLoop]: Abstraction has 683 states and 947 transitions. [2023-11-19 07:48:53,456 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2023-11-19 07:48:53,459 INFO L428 stractBuchiCegarLoop]: Abstraction has 683 states and 947 transitions. [2023-11-19 07:48:53,459 INFO L335 stractBuchiCegarLoop]: ======== Iteration 4 ============ [2023-11-19 07:48:53,459 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 683 states and 947 transitions. [2023-11-19 07:48:53,464 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 620 [2023-11-19 07:48:53,465 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-19 07:48:53,465 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-19 07:48:53,468 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-19 07:48:53,468 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-19 07:48:53,469 INFO L748 eck$LassoCheckResult]: Stem: 1693#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(19, 2);call #Ultimate.allocInit(12, 3);~q_buf_0~0 := 0;~q_free~0 := 0;~q_read_ev~0 := 0;~q_write_ev~0 := 0;~q_req_up~0 := 0;~q_ev~0 := 0;~p_num_write~0 := 0;~p_last_write~0 := 0;~p_dw_st~0 := 0;~p_dw_pc~0 := 0;~p_dw_i~0 := 0;~c_num_read~0 := 0;~c_last_read~0 := 0;~c_dr_st~0 := 0;~c_dr_pc~0 := 0;~c_dr_i~0 := 0;~a_t~0 := 0; 1694#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~3#1;havoc main_~__retres1~3#1;assume { :begin_inline_init_model } true;~q_free~0 := 1;~q_write_ev~0 := 2;~q_read_ev~0 := ~q_write_ev~0;~p_num_write~0 := 0;~p_dw_pc~0 := 0;~p_dw_i~0 := 1;~c_num_read~0 := 0;~c_dr_pc~0 := 0;~c_dr_i~0 := 1; 1721#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret13#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~4#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~4#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 1668#L222 assume !(1 == ~q_req_up~0); 1659#L222-2 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 1660#L237 assume 1 == ~p_dw_i~0;~p_dw_st~0 := 0; 1703#L237-2 assume 1 == ~c_dr_i~0;~c_dr_st~0 := 0; 1728#L242-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 1723#L275 assume 0 == ~q_read_ev~0;~q_read_ev~0 := 1; 1724#L275-2 assume 0 == ~q_write_ev~0;~q_write_ev~0 := 1; 1739#L280-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;assume { :begin_inline_is_do_write_p_triggered } true;havoc is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;havoc is_do_write_p_triggered_~__retres1~0#1; 1769#L65 assume !(1 == ~p_dw_pc~0); 1767#L65-2 is_do_write_p_triggered_~__retres1~0#1 := 0; 1766#L76 is_do_write_p_triggered_#res#1 := is_do_write_p_triggered_~__retres1~0#1; 1765#is_do_write_p_triggered_returnLabel#1 activate_threads_#t~ret7#1 := is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;assume { :end_inline_is_do_write_p_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1; 1764#L315 assume !(0 != activate_threads_~tmp~1#1); 1763#L315-2 assume { :begin_inline_is_do_read_c_triggered } true;havoc is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;havoc is_do_read_c_triggered_~__retres1~1#1; 1762#L84 assume !(1 == ~c_dr_pc~0); 1761#L84-2 is_do_read_c_triggered_~__retres1~1#1 := 0; 1760#L95 is_do_read_c_triggered_#res#1 := is_do_read_c_triggered_~__retres1~1#1; 1759#is_do_read_c_triggered_returnLabel#1 activate_threads_#t~ret8#1 := is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;assume { :end_inline_is_do_read_c_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 1758#L323 assume !(0 != activate_threads_~tmp___0~1#1); 1757#L323-2 havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1756#L293 assume !(1 == ~q_read_ev~0); 1755#L293-2 assume 1 == ~q_write_ev~0;~q_write_ev~0 := 2; 1736#L298-1 assume { :end_inline_reset_delta_events } true; 1737#L419-2 [2023-11-19 07:48:53,469 INFO L750 eck$LassoCheckResult]: Loop: 1737#L419-2 assume !false; 1859#L420 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret9#1, eval_#t~nondet10#1, eval_#t~nondet11#1, eval_~tmp~2#1, eval_~tmp___0~2#1, eval_~tmp___1~0#1;havoc eval_~tmp~2#1;havoc eval_~tmp___0~2#1;havoc eval_~tmp___1~0#1; 1674#L364 assume !false; 1853#L340 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 1854#L255 assume 0 == ~p_dw_st~0;exists_runnable_thread_~__retres1~2#1 := 1; 1846#L267 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 1847#exists_runnable_thread_returnLabel#1 eval_#t~ret9#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp___1~0#1 := eval_#t~ret9#1;havoc eval_#t~ret9#1; 1824#L344 assume !(0 != eval_~tmp___1~0#1); 1826#eval_returnLabel#1 havoc eval_#t~ret9#1, eval_#t~nondet10#1, eval_#t~nondet11#1, eval_~tmp~2#1, eval_~tmp___0~2#1, eval_~tmp___1~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 1961#L222-3 assume !(1 == ~q_req_up~0); 1962#L222-5 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 1955#L275-3 assume 0 == ~q_read_ev~0;~q_read_ev~0 := 1; 1956#L275-5 assume !(0 == ~q_write_ev~0); 2000#L280-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;assume { :begin_inline_is_do_write_p_triggered } true;havoc is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;havoc is_do_write_p_triggered_~__retres1~0#1; 1997#L65-3 assume 1 == ~p_dw_pc~0; 1994#L66-1 assume 1 == ~q_read_ev~0;is_do_write_p_triggered_~__retres1~0#1 := 1; 1992#L76-1 is_do_write_p_triggered_#res#1 := is_do_write_p_triggered_~__retres1~0#1; 1990#is_do_write_p_triggered_returnLabel#2 activate_threads_#t~ret7#1 := is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;assume { :end_inline_is_do_write_p_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1; 1988#L315-3 assume 0 != activate_threads_~tmp~1#1;~p_dw_st~0 := 0; 1986#L315-5 assume { :begin_inline_is_do_read_c_triggered } true;havoc is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;havoc is_do_read_c_triggered_~__retres1~1#1; 1984#L84-3 assume !(1 == ~c_dr_pc~0); 1982#L84-5 is_do_read_c_triggered_~__retres1~1#1 := 0; 1980#L95-1 is_do_read_c_triggered_#res#1 := is_do_read_c_triggered_~__retres1~1#1; 1978#is_do_read_c_triggered_returnLabel#2 activate_threads_#t~ret8#1 := is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;assume { :end_inline_is_do_read_c_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 1976#L323-3 assume 0 != activate_threads_~tmp___0~1#1;~c_dr_st~0 := 0; 1974#L323-5 havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1971#L293-3 assume 1 == ~q_read_ev~0;~q_read_ev~0 := 2; 1937#L293-5 assume !(1 == ~q_write_ev~0); 1936#L298-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret12#1, stop_simulation_~tmp~3#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~3#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 1929#L255-1 assume 0 == ~p_dw_st~0;exists_runnable_thread_~__retres1~2#1 := 1; 1930#L267-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 1924#exists_runnable_thread_returnLabel#2 stop_simulation_#t~ret12#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~3#1 := stop_simulation_#t~ret12#1;havoc stop_simulation_#t~ret12#1; 1925#L394 assume !(0 != stop_simulation_~tmp~3#1);stop_simulation_~__retres2~0#1 := 1; 1869#L401 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 1870#stop_simulation_returnLabel#1 start_simulation_#t~ret13#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret12#1, stop_simulation_~tmp~3#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp~4#1 := start_simulation_#t~ret13#1;havoc start_simulation_#t~ret13#1; 1864#L436 assume !(0 != start_simulation_~tmp~4#1); 1737#L419-2 [2023-11-19 07:48:53,469 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-19 07:48:53,470 INFO L85 PathProgramCache]: Analyzing trace with hash 1964845233, now seen corresponding path program 1 times [2023-11-19 07:48:53,470 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-19 07:48:53,470 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [699221734] [2023-11-19 07:48:53,470 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-19 07:48:53,470 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-19 07:48:53,497 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-19 07:48:53,541 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-19 07:48:53,541 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-19 07:48:53,541 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [699221734] [2023-11-19 07:48:53,541 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [699221734] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-19 07:48:53,542 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-19 07:48:53,542 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-19 07:48:53,543 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [838697993] [2023-11-19 07:48:53,543 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-19 07:48:53,543 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-19 07:48:53,544 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-19 07:48:53,544 INFO L85 PathProgramCache]: Analyzing trace with hash 1301507987, now seen corresponding path program 1 times [2023-11-19 07:48:53,544 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-19 07:48:53,547 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1384574034] [2023-11-19 07:48:53,549 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-19 07:48:53,549 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-19 07:48:53,563 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-19 07:48:53,613 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-19 07:48:53,613 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-19 07:48:53,614 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1384574034] [2023-11-19 07:48:53,614 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1384574034] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-19 07:48:53,614 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-19 07:48:53,614 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2023-11-19 07:48:53,614 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [611403024] [2023-11-19 07:48:53,615 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-19 07:48:53,615 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-19 07:48:53,615 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-19 07:48:53,616 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-19 07:48:53,616 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-19 07:48:53,616 INFO L87 Difference]: Start difference. First operand 683 states and 947 transitions. cyclomatic complexity: 268 Second operand has 3 states, 3 states have (on average 8.666666666666666) internal successors, (26), 3 states have internal predecessors, (26), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-19 07:48:53,647 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-19 07:48:53,647 INFO L93 Difference]: Finished difference Result 952 states and 1297 transitions. [2023-11-19 07:48:53,647 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 952 states and 1297 transitions. [2023-11-19 07:48:53,656 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 906 [2023-11-19 07:48:53,665 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 952 states to 952 states and 1297 transitions. [2023-11-19 07:48:53,665 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 952 [2023-11-19 07:48:53,666 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 952 [2023-11-19 07:48:53,667 INFO L73 IsDeterministic]: Start isDeterministic. Operand 952 states and 1297 transitions. [2023-11-19 07:48:53,668 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-19 07:48:53,668 INFO L218 hiAutomatonCegarLoop]: Abstraction has 952 states and 1297 transitions. [2023-11-19 07:48:53,669 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 952 states and 1297 transitions. [2023-11-19 07:48:53,682 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 952 to 680. [2023-11-19 07:48:53,684 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 680 states, 680 states have (on average 1.3661764705882353) internal successors, (929), 679 states have internal predecessors, (929), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-19 07:48:53,687 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 680 states to 680 states and 929 transitions. [2023-11-19 07:48:53,687 INFO L240 hiAutomatonCegarLoop]: Abstraction has 680 states and 929 transitions. [2023-11-19 07:48:53,688 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-19 07:48:53,689 INFO L428 stractBuchiCegarLoop]: Abstraction has 680 states and 929 transitions. [2023-11-19 07:48:53,689 INFO L335 stractBuchiCegarLoop]: ======== Iteration 5 ============ [2023-11-19 07:48:53,689 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 680 states and 929 transitions. [2023-11-19 07:48:53,694 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 636 [2023-11-19 07:48:53,694 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-19 07:48:53,694 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-19 07:48:53,695 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-19 07:48:53,695 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-19 07:48:53,696 INFO L748 eck$LassoCheckResult]: Stem: 3334#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(19, 2);call #Ultimate.allocInit(12, 3);~q_buf_0~0 := 0;~q_free~0 := 0;~q_read_ev~0 := 0;~q_write_ev~0 := 0;~q_req_up~0 := 0;~q_ev~0 := 0;~p_num_write~0 := 0;~p_last_write~0 := 0;~p_dw_st~0 := 0;~p_dw_pc~0 := 0;~p_dw_i~0 := 0;~c_num_read~0 := 0;~c_last_read~0 := 0;~c_dr_st~0 := 0;~c_dr_pc~0 := 0;~c_dr_i~0 := 0;~a_t~0 := 0; 3335#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~3#1;havoc main_~__retres1~3#1;assume { :begin_inline_init_model } true;~q_free~0 := 1;~q_write_ev~0 := 2;~q_read_ev~0 := ~q_write_ev~0;~p_num_write~0 := 0;~p_dw_pc~0 := 0;~p_dw_i~0 := 1;~c_num_read~0 := 0;~c_dr_pc~0 := 0;~c_dr_i~0 := 1; 3365#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret13#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~4#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~4#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 3311#L222 assume !(1 == ~q_req_up~0); 3300#L222-2 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 3301#L237 assume 1 == ~p_dw_i~0;~p_dw_st~0 := 0; 3347#L237-2 assume 1 == ~c_dr_i~0;~c_dr_st~0 := 0; 3374#L242-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 3370#L275 assume !(0 == ~q_read_ev~0); 3371#L275-2 assume 0 == ~q_write_ev~0;~q_write_ev~0 := 1; 3383#L280-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;assume { :begin_inline_is_do_write_p_triggered } true;havoc is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;havoc is_do_write_p_triggered_~__retres1~0#1; 3404#L65 assume !(1 == ~p_dw_pc~0); 3349#L65-2 is_do_write_p_triggered_~__retres1~0#1 := 0; 3402#L76 is_do_write_p_triggered_#res#1 := is_do_write_p_triggered_~__retres1~0#1; 3403#is_do_write_p_triggered_returnLabel#1 activate_threads_#t~ret7#1 := is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;assume { :end_inline_is_do_write_p_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1; 3379#L315 assume !(0 != activate_threads_~tmp~1#1); 3380#L315-2 assume { :begin_inline_is_do_read_c_triggered } true;havoc is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;havoc is_do_read_c_triggered_~__retres1~1#1; 3389#L84 assume !(1 == ~c_dr_pc~0); 3390#L84-2 is_do_read_c_triggered_~__retres1~1#1 := 0; 3319#L95 is_do_read_c_triggered_#res#1 := is_do_read_c_triggered_~__retres1~1#1; 3320#is_do_read_c_triggered_returnLabel#1 activate_threads_#t~ret8#1 := is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;assume { :end_inline_is_do_read_c_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 3285#L323 assume !(0 != activate_threads_~tmp___0~1#1); 3286#L323-2 havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 3391#L293 assume !(1 == ~q_read_ev~0); 3392#L293-2 assume 1 == ~q_write_ev~0;~q_write_ev~0 := 2; 3280#L298-1 assume { :end_inline_reset_delta_events } true; 3381#L419-2 [2023-11-19 07:48:53,698 INFO L750 eck$LassoCheckResult]: Loop: 3381#L419-2 assume !false; 3439#L420 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret9#1, eval_#t~nondet10#1, eval_#t~nondet11#1, eval_~tmp~2#1, eval_~tmp___0~2#1, eval_~tmp___1~0#1;havoc eval_~tmp~2#1;havoc eval_~tmp___0~2#1;havoc eval_~tmp___1~0#1; 3367#L364 assume !false; 3438#L340 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 3437#L255 assume 0 == ~p_dw_st~0;exists_runnable_thread_~__retres1~2#1 := 1; 3433#L267 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 3431#exists_runnable_thread_returnLabel#1 eval_#t~ret9#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp___1~0#1 := eval_#t~ret9#1;havoc eval_#t~ret9#1; 3428#L344 assume !(0 != eval_~tmp___1~0#1); 3429#eval_returnLabel#1 havoc eval_#t~ret9#1, eval_#t~nondet10#1, eval_#t~nondet11#1, eval_~tmp~2#1, eval_~tmp___0~2#1, eval_~tmp___1~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 3473#L222-3 assume !(1 == ~q_req_up~0); 3471#L222-5 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 3469#L275-3 assume !(0 == ~q_read_ev~0); 3466#L275-5 assume 0 == ~q_write_ev~0;~q_write_ev~0 := 1; 3465#L280-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;assume { :begin_inline_is_do_write_p_triggered } true;havoc is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;havoc is_do_write_p_triggered_~__retres1~0#1; 3464#L65-3 assume !(1 == ~p_dw_pc~0); 3462#L65-5 is_do_write_p_triggered_~__retres1~0#1 := 0; 3461#L76-1 is_do_write_p_triggered_#res#1 := is_do_write_p_triggered_~__retres1~0#1; 3460#is_do_write_p_triggered_returnLabel#2 activate_threads_#t~ret7#1 := is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;assume { :end_inline_is_do_write_p_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1; 3459#L315-3 assume 0 != activate_threads_~tmp~1#1;~p_dw_st~0 := 0; 3458#L315-5 assume { :begin_inline_is_do_read_c_triggered } true;havoc is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;havoc is_do_read_c_triggered_~__retres1~1#1; 3457#L84-3 assume !(1 == ~c_dr_pc~0); 3456#L84-5 is_do_read_c_triggered_~__retres1~1#1 := 0; 3455#L95-1 is_do_read_c_triggered_#res#1 := is_do_read_c_triggered_~__retres1~1#1; 3454#is_do_read_c_triggered_returnLabel#2 activate_threads_#t~ret8#1 := is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;assume { :end_inline_is_do_read_c_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 3453#L323-3 assume 0 != activate_threads_~tmp___0~1#1;~c_dr_st~0 := 0; 3452#L323-5 havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 3451#L293-3 assume !(1 == ~q_read_ev~0); 3449#L293-5 assume 1 == ~q_write_ev~0;~q_write_ev~0 := 2; 3448#L298-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret12#1, stop_simulation_~tmp~3#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~3#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 3446#L255-1 assume 0 == ~p_dw_st~0;exists_runnable_thread_~__retres1~2#1 := 1; 3445#L267-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 3444#exists_runnable_thread_returnLabel#2 stop_simulation_#t~ret12#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~3#1 := stop_simulation_#t~ret12#1;havoc stop_simulation_#t~ret12#1; 3443#L394 assume !(0 != stop_simulation_~tmp~3#1);stop_simulation_~__retres2~0#1 := 1; 3442#L401 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 3441#stop_simulation_returnLabel#1 start_simulation_#t~ret13#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret12#1, stop_simulation_~tmp~3#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp~4#1 := start_simulation_#t~ret13#1;havoc start_simulation_#t~ret13#1; 3440#L436 assume !(0 != start_simulation_~tmp~4#1); 3381#L419-2 [2023-11-19 07:48:53,700 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-19 07:48:53,708 INFO L85 PathProgramCache]: Analyzing trace with hash -29299473, now seen corresponding path program 1 times [2023-11-19 07:48:53,708 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-19 07:48:53,708 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1371850347] [2023-11-19 07:48:53,709 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-19 07:48:53,709 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-19 07:48:53,720 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-19 07:48:53,771 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-19 07:48:53,771 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-19 07:48:53,771 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1371850347] [2023-11-19 07:48:53,771 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1371850347] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-19 07:48:53,772 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-19 07:48:53,772 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2023-11-19 07:48:53,772 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [213268130] [2023-11-19 07:48:53,772 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-19 07:48:53,773 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-19 07:48:53,773 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-19 07:48:53,773 INFO L85 PathProgramCache]: Analyzing trace with hash 389598066, now seen corresponding path program 1 times [2023-11-19 07:48:53,773 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-19 07:48:53,774 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1892921232] [2023-11-19 07:48:53,774 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-19 07:48:53,774 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-19 07:48:53,783 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-19 07:48:53,820 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-19 07:48:53,821 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-19 07:48:53,821 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1892921232] [2023-11-19 07:48:53,821 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1892921232] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-19 07:48:53,822 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-19 07:48:53,822 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2023-11-19 07:48:53,822 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [885082348] [2023-11-19 07:48:53,822 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-19 07:48:53,823 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-19 07:48:53,823 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-19 07:48:53,823 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2023-11-19 07:48:53,823 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2023-11-19 07:48:53,824 INFO L87 Difference]: Start difference. First operand 680 states and 929 transitions. cyclomatic complexity: 251 Second operand has 4 states, 4 states have (on average 6.5) internal successors, (26), 4 states have internal predecessors, (26), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-19 07:48:53,881 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-19 07:48:53,881 INFO L93 Difference]: Finished difference Result 830 states and 1123 transitions. [2023-11-19 07:48:53,881 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 830 states and 1123 transitions. [2023-11-19 07:48:53,889 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 802 [2023-11-19 07:48:53,896 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 830 states to 830 states and 1123 transitions. [2023-11-19 07:48:53,896 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 830 [2023-11-19 07:48:53,897 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 830 [2023-11-19 07:48:53,898 INFO L73 IsDeterministic]: Start isDeterministic. Operand 830 states and 1123 transitions. [2023-11-19 07:48:53,899 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-19 07:48:53,899 INFO L218 hiAutomatonCegarLoop]: Abstraction has 830 states and 1123 transitions. [2023-11-19 07:48:53,900 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 830 states and 1123 transitions. [2023-11-19 07:48:53,931 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 830 to 608. [2023-11-19 07:48:53,932 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 608 states, 608 states have (on average 1.356907894736842) internal successors, (825), 607 states have internal predecessors, (825), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-19 07:48:53,935 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 608 states to 608 states and 825 transitions. [2023-11-19 07:48:53,936 INFO L240 hiAutomatonCegarLoop]: Abstraction has 608 states and 825 transitions. [2023-11-19 07:48:53,936 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2023-11-19 07:48:53,937 INFO L428 stractBuchiCegarLoop]: Abstraction has 608 states and 825 transitions. [2023-11-19 07:48:53,937 INFO L335 stractBuchiCegarLoop]: ======== Iteration 6 ============ [2023-11-19 07:48:53,937 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 608 states and 825 transitions. [2023-11-19 07:48:53,942 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 580 [2023-11-19 07:48:53,942 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-19 07:48:53,942 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-19 07:48:53,943 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-19 07:48:53,943 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-19 07:48:53,944 INFO L748 eck$LassoCheckResult]: Stem: 4859#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(19, 2);call #Ultimate.allocInit(12, 3);~q_buf_0~0 := 0;~q_free~0 := 0;~q_read_ev~0 := 0;~q_write_ev~0 := 0;~q_req_up~0 := 0;~q_ev~0 := 0;~p_num_write~0 := 0;~p_last_write~0 := 0;~p_dw_st~0 := 0;~p_dw_pc~0 := 0;~p_dw_i~0 := 0;~c_num_read~0 := 0;~c_last_read~0 := 0;~c_dr_st~0 := 0;~c_dr_pc~0 := 0;~c_dr_i~0 := 0;~a_t~0 := 0; 4860#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~3#1;havoc main_~__retres1~3#1;assume { :begin_inline_init_model } true;~q_free~0 := 1;~q_write_ev~0 := 2;~q_read_ev~0 := ~q_write_ev~0;~p_num_write~0 := 0;~p_dw_pc~0 := 0;~p_dw_i~0 := 1;~c_num_read~0 := 0;~c_dr_pc~0 := 0;~c_dr_i~0 := 1; 4887#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret13#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~4#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~4#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 4834#L222 assume !(1 == ~q_req_up~0); 4825#L222-2 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 4826#L237 assume 1 == ~p_dw_i~0;~p_dw_st~0 := 0; 4867#L237-2 assume 1 == ~c_dr_i~0;~c_dr_st~0 := 0; 4894#L242-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 4890#L275 assume !(0 == ~q_read_ev~0); 4891#L275-2 assume !(0 == ~q_write_ev~0); 4873#L280-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;assume { :begin_inline_is_do_write_p_triggered } true;havoc is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;havoc is_do_write_p_triggered_~__retres1~0#1; 4874#L65 assume !(1 == ~p_dw_pc~0); 4871#L65-2 is_do_write_p_triggered_~__retres1~0#1 := 0; 4883#L76 is_do_write_p_triggered_#res#1 := is_do_write_p_triggered_~__retres1~0#1; 4853#is_do_write_p_triggered_returnLabel#1 activate_threads_#t~ret7#1 := is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;assume { :end_inline_is_do_write_p_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1; 4854#L315 assume !(0 != activate_threads_~tmp~1#1); 4831#L315-2 assume { :begin_inline_is_do_read_c_triggered } true;havoc is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;havoc is_do_read_c_triggered_~__retres1~1#1; 4832#L84 assume !(1 == ~c_dr_pc~0); 4849#L84-2 is_do_read_c_triggered_~__retres1~1#1 := 0; 4843#L95 is_do_read_c_triggered_#res#1 := is_do_read_c_triggered_~__retres1~1#1; 4844#is_do_read_c_triggered_returnLabel#1 activate_threads_#t~ret8#1 := is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;assume { :end_inline_is_do_read_c_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 4807#L323 assume !(0 != activate_threads_~tmp___0~1#1); 4808#L323-2 havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 4903#L293 assume !(1 == ~q_read_ev~0); 4801#L293-2 assume !(1 == ~q_write_ev~0); 4802#L298-1 assume { :end_inline_reset_delta_events } true; 4899#L419-2 [2023-11-19 07:48:53,944 INFO L750 eck$LassoCheckResult]: Loop: 4899#L419-2 assume !false; 4972#L420 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret9#1, eval_#t~nondet10#1, eval_#t~nondet11#1, eval_~tmp~2#1, eval_~tmp___0~2#1, eval_~tmp___1~0#1;havoc eval_~tmp~2#1;havoc eval_~tmp___0~2#1;havoc eval_~tmp___1~0#1; 4840#L364 assume !false; 4971#L340 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 4970#L255 assume 0 == ~p_dw_st~0;exists_runnable_thread_~__retres1~2#1 := 1; 4968#L267 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 4967#exists_runnable_thread_returnLabel#1 eval_#t~ret9#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp___1~0#1 := eval_#t~ret9#1;havoc eval_#t~ret9#1; 4856#L344 assume !(0 != eval_~tmp___1~0#1); 4858#eval_returnLabel#1 havoc eval_#t~ret9#1, eval_#t~nondet10#1, eval_#t~nondet11#1, eval_~tmp~2#1, eval_~tmp___0~2#1, eval_~tmp___1~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 5001#L222-3 assume !(1 == ~q_req_up~0); 5000#L222-5 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 4999#L275-3 assume !(0 == ~q_read_ev~0); 4998#L275-5 assume !(0 == ~q_write_ev~0); 4997#L280-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;assume { :begin_inline_is_do_write_p_triggered } true;havoc is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;havoc is_do_write_p_triggered_~__retres1~0#1; 4996#L65-3 assume !(1 == ~p_dw_pc~0); 4994#L65-5 is_do_write_p_triggered_~__retres1~0#1 := 0; 4993#L76-1 is_do_write_p_triggered_#res#1 := is_do_write_p_triggered_~__retres1~0#1; 4992#is_do_write_p_triggered_returnLabel#2 activate_threads_#t~ret7#1 := is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;assume { :end_inline_is_do_write_p_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1; 4991#L315-3 assume 0 != activate_threads_~tmp~1#1;~p_dw_st~0 := 0; 4990#L315-5 assume { :begin_inline_is_do_read_c_triggered } true;havoc is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;havoc is_do_read_c_triggered_~__retres1~1#1; 4989#L84-3 assume !(1 == ~c_dr_pc~0); 4988#L84-5 is_do_read_c_triggered_~__retres1~1#1 := 0; 4987#L95-1 is_do_read_c_triggered_#res#1 := is_do_read_c_triggered_~__retres1~1#1; 4986#is_do_read_c_triggered_returnLabel#2 activate_threads_#t~ret8#1 := is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;assume { :end_inline_is_do_read_c_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 4985#L323-3 assume 0 != activate_threads_~tmp___0~1#1;~c_dr_st~0 := 0; 4984#L323-5 havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 4983#L293-3 assume !(1 == ~q_read_ev~0); 4982#L293-5 assume !(1 == ~q_write_ev~0); 4981#L298-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret12#1, stop_simulation_~tmp~3#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~3#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 4979#L255-1 assume 0 == ~p_dw_st~0;exists_runnable_thread_~__retres1~2#1 := 1; 4978#L267-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 4977#exists_runnable_thread_returnLabel#2 stop_simulation_#t~ret12#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~3#1 := stop_simulation_#t~ret12#1;havoc stop_simulation_#t~ret12#1; 4976#L394 assume !(0 != stop_simulation_~tmp~3#1);stop_simulation_~__retres2~0#1 := 1; 4975#L401 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 4974#stop_simulation_returnLabel#1 start_simulation_#t~ret13#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret12#1, stop_simulation_~tmp~3#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp~4#1 := start_simulation_#t~ret13#1;havoc start_simulation_#t~ret13#1; 4973#L436 assume !(0 != start_simulation_~tmp~4#1); 4899#L419-2 [2023-11-19 07:48:53,944 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-19 07:48:53,945 INFO L85 PathProgramCache]: Analyzing trace with hash -1617647313, now seen corresponding path program 1 times [2023-11-19 07:48:53,945 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-19 07:48:53,945 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1023628289] [2023-11-19 07:48:53,945 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-19 07:48:53,945 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-19 07:48:53,954 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-19 07:48:53,954 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-19 07:48:53,959 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-19 07:48:53,983 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-19 07:48:53,984 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-19 07:48:53,984 INFO L85 PathProgramCache]: Analyzing trace with hash 935642930, now seen corresponding path program 1 times [2023-11-19 07:48:53,984 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-19 07:48:53,985 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [556394507] [2023-11-19 07:48:53,985 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-19 07:48:53,985 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-19 07:48:53,993 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-19 07:48:54,042 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-19 07:48:54,042 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-19 07:48:54,046 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [556394507] [2023-11-19 07:48:54,050 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [556394507] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-19 07:48:54,050 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-19 07:48:54,050 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2023-11-19 07:48:54,050 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [515295081] [2023-11-19 07:48:54,050 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-19 07:48:54,051 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-19 07:48:54,051 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-19 07:48:54,052 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2023-11-19 07:48:54,052 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2023-11-19 07:48:54,052 INFO L87 Difference]: Start difference. First operand 608 states and 825 transitions. cyclomatic complexity: 219 Second operand has 5 states, 5 states have (on average 7.2) internal successors, (36), 5 states have internal predecessors, (36), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-19 07:48:54,138 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-19 07:48:54,138 INFO L93 Difference]: Finished difference Result 919 states and 1233 transitions. [2023-11-19 07:48:54,138 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 919 states and 1233 transitions. [2023-11-19 07:48:54,148 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 890 [2023-11-19 07:48:54,156 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 919 states to 919 states and 1233 transitions. [2023-11-19 07:48:54,156 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 919 [2023-11-19 07:48:54,157 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 919 [2023-11-19 07:48:54,157 INFO L73 IsDeterministic]: Start isDeterministic. Operand 919 states and 1233 transitions. [2023-11-19 07:48:54,159 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-19 07:48:54,159 INFO L218 hiAutomatonCegarLoop]: Abstraction has 919 states and 1233 transitions. [2023-11-19 07:48:54,160 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 919 states and 1233 transitions. [2023-11-19 07:48:54,172 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 919 to 635. [2023-11-19 07:48:54,173 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 635 states, 635 states have (on average 1.3417322834645669) internal successors, (852), 634 states have internal predecessors, (852), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-19 07:48:54,176 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 635 states to 635 states and 852 transitions. [2023-11-19 07:48:54,177 INFO L240 hiAutomatonCegarLoop]: Abstraction has 635 states and 852 transitions. [2023-11-19 07:48:54,177 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 9 states. [2023-11-19 07:48:54,180 INFO L428 stractBuchiCegarLoop]: Abstraction has 635 states and 852 transitions. [2023-11-19 07:48:54,181 INFO L335 stractBuchiCegarLoop]: ======== Iteration 7 ============ [2023-11-19 07:48:54,181 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 635 states and 852 transitions. [2023-11-19 07:48:54,184 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 607 [2023-11-19 07:48:54,184 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-19 07:48:54,184 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-19 07:48:54,185 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-19 07:48:54,185 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-19 07:48:54,185 INFO L748 eck$LassoCheckResult]: Stem: 6405#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(19, 2);call #Ultimate.allocInit(12, 3);~q_buf_0~0 := 0;~q_free~0 := 0;~q_read_ev~0 := 0;~q_write_ev~0 := 0;~q_req_up~0 := 0;~q_ev~0 := 0;~p_num_write~0 := 0;~p_last_write~0 := 0;~p_dw_st~0 := 0;~p_dw_pc~0 := 0;~p_dw_i~0 := 0;~c_num_read~0 := 0;~c_last_read~0 := 0;~c_dr_st~0 := 0;~c_dr_pc~0 := 0;~c_dr_i~0 := 0;~a_t~0 := 0; 6406#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~3#1;havoc main_~__retres1~3#1;assume { :begin_inline_init_model } true;~q_free~0 := 1;~q_write_ev~0 := 2;~q_read_ev~0 := ~q_write_ev~0;~p_num_write~0 := 0;~p_dw_pc~0 := 0;~p_dw_i~0 := 1;~c_num_read~0 := 0;~c_dr_pc~0 := 0;~c_dr_i~0 := 1; 6431#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret13#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~4#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~4#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 6379#L222 assume !(1 == ~q_req_up~0); 6370#L222-2 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 6371#L237 assume 1 == ~p_dw_i~0;~p_dw_st~0 := 0; 6413#L237-2 assume 1 == ~c_dr_i~0;~c_dr_st~0 := 0; 6435#L242-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 6433#L275 assume !(0 == ~q_read_ev~0); 6434#L275-2 assume !(0 == ~q_write_ev~0); 6419#L280-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;assume { :begin_inline_is_do_write_p_triggered } true;havoc is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;havoc is_do_write_p_triggered_~__retres1~0#1; 6420#L65 assume !(1 == ~p_dw_pc~0); 6415#L65-2 is_do_write_p_triggered_~__retres1~0#1 := 0; 6428#L76 is_do_write_p_triggered_#res#1 := is_do_write_p_triggered_~__retres1~0#1; 6400#is_do_write_p_triggered_returnLabel#1 activate_threads_#t~ret7#1 := is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;assume { :end_inline_is_do_write_p_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1; 6401#L315 assume !(0 != activate_threads_~tmp~1#1); 6376#L315-2 assume { :begin_inline_is_do_read_c_triggered } true;havoc is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;havoc is_do_read_c_triggered_~__retres1~1#1; 6377#L84 assume !(1 == ~c_dr_pc~0); 6395#L84-2 is_do_read_c_triggered_~__retres1~1#1 := 0; 6388#L95 is_do_read_c_triggered_#res#1 := is_do_read_c_triggered_~__retres1~1#1; 6389#is_do_read_c_triggered_returnLabel#1 activate_threads_#t~ret8#1 := is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;assume { :end_inline_is_do_read_c_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 6352#L323 assume !(0 != activate_threads_~tmp___0~1#1); 6353#L323-2 havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 6449#L293 assume !(1 == ~q_read_ev~0); 6345#L293-2 assume !(1 == ~q_write_ev~0); 6346#L298-1 assume { :end_inline_reset_delta_events } true; 6442#L419-2 [2023-11-19 07:48:54,185 INFO L750 eck$LassoCheckResult]: Loop: 6442#L419-2 assume !false; 6961#L420 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret9#1, eval_#t~nondet10#1, eval_#t~nondet11#1, eval_~tmp~2#1, eval_~tmp___0~2#1, eval_~tmp___1~0#1;havoc eval_~tmp~2#1;havoc eval_~tmp___0~2#1;havoc eval_~tmp___1~0#1; 6383#L364 assume !false; 6418#L340 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 6380#L255 assume !(0 == ~p_dw_st~0); 6347#L259 assume !(0 == ~c_dr_st~0);exists_runnable_thread_~__retres1~2#1 := 0; 6349#L267 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 6482#exists_runnable_thread_returnLabel#1 eval_#t~ret9#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp___1~0#1 := eval_#t~ret9#1;havoc eval_#t~ret9#1; 6481#L344 assume !(0 != eval_~tmp___1~0#1); 6384#eval_returnLabel#1 havoc eval_#t~ret9#1, eval_#t~nondet10#1, eval_#t~nondet11#1, eval_~tmp~2#1, eval_~tmp___0~2#1, eval_~tmp___1~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 6385#L222-3 assume !(1 == ~q_req_up~0); 6439#L222-5 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 6440#L275-3 assume !(0 == ~q_read_ev~0); 6444#L275-5 assume !(0 == ~q_write_ev~0); 6445#L280-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;assume { :begin_inline_is_do_write_p_triggered } true;havoc is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;havoc is_do_write_p_triggered_~__retres1~0#1; 6358#L65-3 assume !(1 == ~p_dw_pc~0); 6360#L65-5 is_do_write_p_triggered_~__retres1~0#1 := 0; 6394#L76-1 is_do_write_p_triggered_#res#1 := is_do_write_p_triggered_~__retres1~0#1; 6443#is_do_write_p_triggered_returnLabel#2 activate_threads_#t~ret7#1 := is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;assume { :end_inline_is_do_write_p_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1; 6446#L315-3 assume 0 != activate_threads_~tmp~1#1;~p_dw_st~0 := 0; 6429#L315-5 assume { :begin_inline_is_do_read_c_triggered } true;havoc is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;havoc is_do_read_c_triggered_~__retres1~1#1; 6350#L84-3 assume !(1 == ~c_dr_pc~0); 6351#L84-5 is_do_read_c_triggered_~__retres1~1#1 := 0; 6409#L95-1 is_do_read_c_triggered_#res#1 := is_do_read_c_triggered_~__retres1~1#1; 6410#is_do_read_c_triggered_returnLabel#2 activate_threads_#t~ret8#1 := is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;assume { :end_inline_is_do_read_c_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 6427#L323-3 assume 0 != activate_threads_~tmp___0~1#1;~c_dr_st~0 := 0; 6407#L323-5 havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 6408#L293-3 assume !(1 == ~q_read_ev~0); 6356#L293-5 assume !(1 == ~q_write_ev~0); 6357#L298-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret12#1, stop_simulation_~tmp~3#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~3#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 6421#L255-1 assume 0 == ~p_dw_st~0;exists_runnable_thread_~__retres1~2#1 := 1; 6422#L267-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 6399#exists_runnable_thread_returnLabel#2 stop_simulation_#t~ret12#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~3#1 := stop_simulation_#t~ret12#1;havoc stop_simulation_#t~ret12#1; 6378#L394 assume !(0 != stop_simulation_~tmp~3#1);stop_simulation_~__retres2~0#1 := 1; 6363#L401 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 6364#stop_simulation_returnLabel#1 start_simulation_#t~ret13#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret12#1, stop_simulation_~tmp~3#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp~4#1 := start_simulation_#t~ret13#1;havoc start_simulation_#t~ret13#1; 6962#L436 assume !(0 != start_simulation_~tmp~4#1); 6442#L419-2 [2023-11-19 07:48:54,186 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-19 07:48:54,186 INFO L85 PathProgramCache]: Analyzing trace with hash -1617647313, now seen corresponding path program 2 times [2023-11-19 07:48:54,186 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-19 07:48:54,186 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1544696112] [2023-11-19 07:48:54,186 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-19 07:48:54,186 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-19 07:48:54,199 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-19 07:48:54,199 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-19 07:48:54,205 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-19 07:48:54,213 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-19 07:48:54,214 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-19 07:48:54,214 INFO L85 PathProgramCache]: Analyzing trace with hash 1296496688, now seen corresponding path program 1 times [2023-11-19 07:48:54,214 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-19 07:48:54,214 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1482395921] [2023-11-19 07:48:54,214 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-19 07:48:54,214 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-19 07:48:54,221 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-19 07:48:54,288 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-19 07:48:54,289 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-19 07:48:54,289 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1482395921] [2023-11-19 07:48:54,289 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1482395921] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-19 07:48:54,289 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-19 07:48:54,289 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2023-11-19 07:48:54,289 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [427644326] [2023-11-19 07:48:54,290 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-19 07:48:54,290 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-19 07:48:54,290 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-19 07:48:54,290 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2023-11-19 07:48:54,291 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2023-11-19 07:48:54,291 INFO L87 Difference]: Start difference. First operand 635 states and 852 transitions. cyclomatic complexity: 219 Second operand has 5 states, 5 states have (on average 7.4) internal successors, (37), 5 states have internal predecessors, (37), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-19 07:48:54,342 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-19 07:48:54,342 INFO L93 Difference]: Finished difference Result 847 states and 1134 transitions. [2023-11-19 07:48:54,342 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 847 states and 1134 transitions. [2023-11-19 07:48:54,349 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 818 [2023-11-19 07:48:54,357 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 847 states to 847 states and 1134 transitions. [2023-11-19 07:48:54,357 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 847 [2023-11-19 07:48:54,358 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 847 [2023-11-19 07:48:54,358 INFO L73 IsDeterministic]: Start isDeterministic. Operand 847 states and 1134 transitions. [2023-11-19 07:48:54,359 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-19 07:48:54,359 INFO L218 hiAutomatonCegarLoop]: Abstraction has 847 states and 1134 transitions. [2023-11-19 07:48:54,360 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 847 states and 1134 transitions. [2023-11-19 07:48:54,370 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 847 to 662. [2023-11-19 07:48:54,372 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 662 states, 662 states have (on average 1.3277945619335347) internal successors, (879), 661 states have internal predecessors, (879), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-19 07:48:54,374 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 662 states to 662 states and 879 transitions. [2023-11-19 07:48:54,375 INFO L240 hiAutomatonCegarLoop]: Abstraction has 662 states and 879 transitions. [2023-11-19 07:48:54,375 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2023-11-19 07:48:54,376 INFO L428 stractBuchiCegarLoop]: Abstraction has 662 states and 879 transitions. [2023-11-19 07:48:54,376 INFO L335 stractBuchiCegarLoop]: ======== Iteration 8 ============ [2023-11-19 07:48:54,376 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 662 states and 879 transitions. [2023-11-19 07:48:54,380 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 634 [2023-11-19 07:48:54,380 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-19 07:48:54,380 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-19 07:48:54,381 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-19 07:48:54,381 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-19 07:48:54,381 INFO L748 eck$LassoCheckResult]: Stem: 7896#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(19, 2);call #Ultimate.allocInit(12, 3);~q_buf_0~0 := 0;~q_free~0 := 0;~q_read_ev~0 := 0;~q_write_ev~0 := 0;~q_req_up~0 := 0;~q_ev~0 := 0;~p_num_write~0 := 0;~p_last_write~0 := 0;~p_dw_st~0 := 0;~p_dw_pc~0 := 0;~p_dw_i~0 := 0;~c_num_read~0 := 0;~c_last_read~0 := 0;~c_dr_st~0 := 0;~c_dr_pc~0 := 0;~c_dr_i~0 := 0;~a_t~0 := 0; 7897#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~3#1;havoc main_~__retres1~3#1;assume { :begin_inline_init_model } true;~q_free~0 := 1;~q_write_ev~0 := 2;~q_read_ev~0 := ~q_write_ev~0;~p_num_write~0 := 0;~p_dw_pc~0 := 0;~p_dw_i~0 := 1;~c_num_read~0 := 0;~c_dr_pc~0 := 0;~c_dr_i~0 := 1; 7924#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret13#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~4#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~4#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 7874#L222 assume !(1 == ~q_req_up~0); 7863#L222-2 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 7864#L237 assume 1 == ~p_dw_i~0;~p_dw_st~0 := 0; 7907#L237-2 assume 1 == ~c_dr_i~0;~c_dr_st~0 := 0; 7930#L242-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 7927#L275 assume !(0 == ~q_read_ev~0); 7928#L275-2 assume !(0 == ~q_write_ev~0); 7912#L280-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;assume { :begin_inline_is_do_write_p_triggered } true;havoc is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;havoc is_do_write_p_triggered_~__retres1~0#1; 7913#L65 assume !(1 == ~p_dw_pc~0); 7909#L65-2 is_do_write_p_triggered_~__retres1~0#1 := 0; 7922#L76 is_do_write_p_triggered_#res#1 := is_do_write_p_triggered_~__retres1~0#1; 7893#is_do_write_p_triggered_returnLabel#1 activate_threads_#t~ret7#1 := is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;assume { :end_inline_is_do_write_p_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1; 7894#L315 assume !(0 != activate_threads_~tmp~1#1); 7871#L315-2 assume { :begin_inline_is_do_read_c_triggered } true;havoc is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;havoc is_do_read_c_triggered_~__retres1~1#1; 7872#L84 assume !(1 == ~c_dr_pc~0); 7890#L84-2 is_do_read_c_triggered_~__retres1~1#1 := 0; 7883#L95 is_do_read_c_triggered_#res#1 := is_do_read_c_triggered_~__retres1~1#1; 7884#is_do_read_c_triggered_returnLabel#1 activate_threads_#t~ret8#1 := is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;assume { :end_inline_is_do_read_c_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 7847#L323 assume !(0 != activate_threads_~tmp___0~1#1); 7848#L323-2 havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 7939#L293 assume !(1 == ~q_read_ev~0); 7840#L293-2 assume !(1 == ~q_write_ev~0); 7841#L298-1 assume { :end_inline_reset_delta_events } true; 7867#L419-2 [2023-11-19 07:48:54,382 INFO L750 eck$LassoCheckResult]: Loop: 7867#L419-2 assume !false; 7868#L420 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret9#1, eval_#t~nondet10#1, eval_#t~nondet11#1, eval_~tmp~2#1, eval_~tmp___0~2#1, eval_~tmp___1~0#1;havoc eval_~tmp~2#1;havoc eval_~tmp___0~2#1;havoc eval_~tmp___1~0#1; 7878#L364 assume !false; 7914#L340 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 7915#L255 assume !(0 == ~p_dw_st~0); 8399#L259 assume !(0 == ~c_dr_st~0);exists_runnable_thread_~__retres1~2#1 := 0; 8400#L267 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 8495#exists_runnable_thread_returnLabel#1 eval_#t~ret9#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp___1~0#1 := eval_#t~ret9#1;havoc eval_#t~ret9#1; 8494#L344 assume !(0 != eval_~tmp___1~0#1); 7879#eval_returnLabel#1 havoc eval_#t~ret9#1, eval_#t~nondet10#1, eval_#t~nondet11#1, eval_~tmp~2#1, eval_~tmp___0~2#1, eval_~tmp___1~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 7880#L222-3 assume !(1 == ~q_req_up~0); 8489#L222-5 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 8488#L275-3 assume !(0 == ~q_read_ev~0); 8487#L275-5 assume !(0 == ~q_write_ev~0); 8486#L280-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;assume { :begin_inline_is_do_write_p_triggered } true;havoc is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;havoc is_do_write_p_triggered_~__retres1~0#1; 8484#L65-3 assume !(1 == ~p_dw_pc~0); 7888#L65-5 is_do_write_p_triggered_~__retres1~0#1 := 0; 7889#L76-1 is_do_write_p_triggered_#res#1 := is_do_write_p_triggered_~__retres1~0#1; 7934#is_do_write_p_triggered_returnLabel#2 activate_threads_#t~ret7#1 := is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;assume { :end_inline_is_do_write_p_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1; 7936#L315-3 assume 0 != activate_threads_~tmp~1#1;~p_dw_st~0 := 0; 7923#L315-5 assume { :begin_inline_is_do_read_c_triggered } true;havoc is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;havoc is_do_read_c_triggered_~__retres1~1#1; 7845#L84-3 assume !(1 == ~c_dr_pc~0); 7846#L84-5 is_do_read_c_triggered_~__retres1~1#1 := 0; 7903#L95-1 is_do_read_c_triggered_#res#1 := is_do_read_c_triggered_~__retres1~1#1; 7904#is_do_read_c_triggered_returnLabel#2 activate_threads_#t~ret8#1 := is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;assume { :end_inline_is_do_read_c_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 7921#L323-3 assume 0 != activate_threads_~tmp___0~1#1;~c_dr_st~0 := 0; 7901#L323-5 havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 7902#L293-3 assume !(1 == ~q_read_ev~0); 7851#L293-5 assume !(1 == ~q_write_ev~0); 7852#L298-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret12#1, stop_simulation_~tmp~3#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~3#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 7916#L255-1 assume 0 == ~p_dw_st~0;exists_runnable_thread_~__retres1~2#1 := 1; 7917#L267-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 7895#exists_runnable_thread_returnLabel#2 stop_simulation_#t~ret12#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~3#1 := stop_simulation_#t~ret12#1;havoc stop_simulation_#t~ret12#1; 7873#L394 assume 0 != stop_simulation_~tmp~3#1;stop_simulation_~__retres2~0#1 := 0; 7858#L401 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 7859#stop_simulation_returnLabel#1 start_simulation_#t~ret13#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret12#1, stop_simulation_~tmp~3#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp~4#1 := start_simulation_#t~ret13#1;havoc start_simulation_#t~ret13#1; 7920#L436 assume !(0 != start_simulation_~tmp~4#1); 7867#L419-2 [2023-11-19 07:48:54,382 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-19 07:48:54,382 INFO L85 PathProgramCache]: Analyzing trace with hash -1617647313, now seen corresponding path program 3 times [2023-11-19 07:48:54,382 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-19 07:48:54,382 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [339571925] [2023-11-19 07:48:54,383 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-19 07:48:54,383 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-19 07:48:54,389 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-19 07:48:54,389 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-19 07:48:54,394 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-19 07:48:54,399 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-19 07:48:54,400 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-19 07:48:54,400 INFO L85 PathProgramCache]: Analyzing trace with hash 1296437106, now seen corresponding path program 1 times [2023-11-19 07:48:54,400 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-19 07:48:54,400 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [265441935] [2023-11-19 07:48:54,400 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-19 07:48:54,401 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-19 07:48:54,408 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-19 07:48:54,477 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-19 07:48:54,478 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-19 07:48:54,478 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [265441935] [2023-11-19 07:48:54,478 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [265441935] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-19 07:48:54,478 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-19 07:48:54,478 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2023-11-19 07:48:54,479 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [492450939] [2023-11-19 07:48:54,479 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-19 07:48:54,479 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-19 07:48:54,479 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-19 07:48:54,480 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2023-11-19 07:48:54,480 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2023-11-19 07:48:54,480 INFO L87 Difference]: Start difference. First operand 662 states and 879 transitions. cyclomatic complexity: 219 Second operand has 5 states, 5 states have (on average 7.4) internal successors, (37), 5 states have internal predecessors, (37), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-19 07:48:54,534 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-19 07:48:54,535 INFO L93 Difference]: Finished difference Result 1182 states and 1559 transitions. [2023-11-19 07:48:54,535 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1182 states and 1559 transitions. [2023-11-19 07:48:54,547 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 1154 [2023-11-19 07:48:54,557 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1182 states to 1182 states and 1559 transitions. [2023-11-19 07:48:54,558 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1182 [2023-11-19 07:48:54,559 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1182 [2023-11-19 07:48:54,559 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1182 states and 1559 transitions. [2023-11-19 07:48:54,561 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-19 07:48:54,562 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1182 states and 1559 transitions. [2023-11-19 07:48:54,563 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1182 states and 1559 transitions. [2023-11-19 07:48:54,579 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1182 to 680. [2023-11-19 07:48:54,581 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 680 states, 680 states have (on average 1.3073529411764706) internal successors, (889), 679 states have internal predecessors, (889), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-19 07:48:54,585 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 680 states to 680 states and 889 transitions. [2023-11-19 07:48:54,585 INFO L240 hiAutomatonCegarLoop]: Abstraction has 680 states and 889 transitions. [2023-11-19 07:48:54,586 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2023-11-19 07:48:54,586 INFO L428 stractBuchiCegarLoop]: Abstraction has 680 states and 889 transitions. [2023-11-19 07:48:54,586 INFO L335 stractBuchiCegarLoop]: ======== Iteration 9 ============ [2023-11-19 07:48:54,587 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 680 states and 889 transitions. [2023-11-19 07:48:54,592 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 652 [2023-11-19 07:48:54,592 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-19 07:48:54,592 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-19 07:48:54,593 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-19 07:48:54,593 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-19 07:48:54,593 INFO L748 eck$LassoCheckResult]: Stem: 9753#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(19, 2);call #Ultimate.allocInit(12, 3);~q_buf_0~0 := 0;~q_free~0 := 0;~q_read_ev~0 := 0;~q_write_ev~0 := 0;~q_req_up~0 := 0;~q_ev~0 := 0;~p_num_write~0 := 0;~p_last_write~0 := 0;~p_dw_st~0 := 0;~p_dw_pc~0 := 0;~p_dw_i~0 := 0;~c_num_read~0 := 0;~c_last_read~0 := 0;~c_dr_st~0 := 0;~c_dr_pc~0 := 0;~c_dr_i~0 := 0;~a_t~0 := 0; 9754#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~3#1;havoc main_~__retres1~3#1;assume { :begin_inline_init_model } true;~q_free~0 := 1;~q_write_ev~0 := 2;~q_read_ev~0 := ~q_write_ev~0;~p_num_write~0 := 0;~p_dw_pc~0 := 0;~p_dw_i~0 := 1;~c_num_read~0 := 0;~c_dr_pc~0 := 0;~c_dr_i~0 := 1; 9782#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret13#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~4#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~4#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 9730#L222 assume !(1 == ~q_req_up~0); 9719#L222-2 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 9720#L237 assume 1 == ~p_dw_i~0;~p_dw_st~0 := 0; 9764#L237-2 assume 1 == ~c_dr_i~0;~c_dr_st~0 := 0; 9787#L242-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 9785#L275 assume !(0 == ~q_read_ev~0); 9786#L275-2 assume !(0 == ~q_write_ev~0); 9769#L280-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;assume { :begin_inline_is_do_write_p_triggered } true;havoc is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;havoc is_do_write_p_triggered_~__retres1~0#1; 9770#L65 assume !(1 == ~p_dw_pc~0); 9766#L65-2 is_do_write_p_triggered_~__retres1~0#1 := 0; 9779#L76 is_do_write_p_triggered_#res#1 := is_do_write_p_triggered_~__retres1~0#1; 9749#is_do_write_p_triggered_returnLabel#1 activate_threads_#t~ret7#1 := is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;assume { :end_inline_is_do_write_p_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1; 9750#L315 assume !(0 != activate_threads_~tmp~1#1); 9727#L315-2 assume { :begin_inline_is_do_read_c_triggered } true;havoc is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;havoc is_do_read_c_triggered_~__retres1~1#1; 9728#L84 assume !(1 == ~c_dr_pc~0); 9745#L84-2 is_do_read_c_triggered_~__retres1~1#1 := 0; 9739#L95 is_do_read_c_triggered_#res#1 := is_do_read_c_triggered_~__retres1~1#1; 9740#is_do_read_c_triggered_returnLabel#1 activate_threads_#t~ret8#1 := is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;assume { :end_inline_is_do_read_c_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 9703#L323 assume !(0 != activate_threads_~tmp___0~1#1); 9704#L323-2 havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 9796#L293 assume !(1 == ~q_read_ev~0); 9696#L293-2 assume !(1 == ~q_write_ev~0); 9697#L298-1 assume { :end_inline_reset_delta_events } true; 9792#L419-2 [2023-11-19 07:48:54,593 INFO L750 eck$LassoCheckResult]: Loop: 9792#L419-2 assume !false; 10080#L420 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret9#1, eval_#t~nondet10#1, eval_#t~nondet11#1, eval_~tmp~2#1, eval_~tmp___0~2#1, eval_~tmp___1~0#1;havoc eval_~tmp~2#1;havoc eval_~tmp___0~2#1;havoc eval_~tmp___1~0#1; 9734#L364 assume !false; 10077#L340 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 10075#L255 assume !(0 == ~p_dw_st~0); 10074#L259 assume !(0 == ~c_dr_st~0);exists_runnable_thread_~__retres1~2#1 := 0; 10073#L267 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 9932#exists_runnable_thread_returnLabel#1 eval_#t~ret9#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp___1~0#1 := eval_#t~ret9#1;havoc eval_#t~ret9#1; 9933#L344 assume !(0 != eval_~tmp___1~0#1); 10061#eval_returnLabel#1 havoc eval_#t~ret9#1, eval_#t~nondet10#1, eval_#t~nondet11#1, eval_~tmp~2#1, eval_~tmp___0~2#1, eval_~tmp___1~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 10052#L222-3 assume !(1 == ~q_req_up~0); 10047#L222-5 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 10042#L275-3 assume !(0 == ~q_read_ev~0); 10037#L275-5 assume !(0 == ~q_write_ev~0); 10032#L280-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;assume { :begin_inline_is_do_write_p_triggered } true;havoc is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;havoc is_do_write_p_triggered_~__retres1~0#1; 10028#L65-3 assume !(1 == ~p_dw_pc~0); 10025#L65-5 is_do_write_p_triggered_~__retres1~0#1 := 0; 10022#L76-1 is_do_write_p_triggered_#res#1 := is_do_write_p_triggered_~__retres1~0#1; 10019#is_do_write_p_triggered_returnLabel#2 activate_threads_#t~ret7#1 := is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;assume { :end_inline_is_do_write_p_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1; 10016#L315-3 assume !(0 != activate_threads_~tmp~1#1); 10013#L315-5 assume { :begin_inline_is_do_read_c_triggered } true;havoc is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;havoc is_do_read_c_triggered_~__retres1~1#1; 9993#L84-3 assume !(1 == ~c_dr_pc~0); 9988#L84-5 is_do_read_c_triggered_~__retres1~1#1 := 0; 9989#L95-1 is_do_read_c_triggered_#res#1 := is_do_read_c_triggered_~__retres1~1#1; 9982#is_do_read_c_triggered_returnLabel#2 activate_threads_#t~ret8#1 := is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;assume { :end_inline_is_do_read_c_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 9983#L323-3 assume 0 != activate_threads_~tmp___0~1#1;~c_dr_st~0 := 0; 9977#L323-5 havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 9978#L293-3 assume !(1 == ~q_read_ev~0); 10112#L293-5 assume !(1 == ~q_write_ev~0); 10111#L298-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret12#1, stop_simulation_~tmp~3#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~3#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 10110#L255-1 assume 0 == ~p_dw_st~0;exists_runnable_thread_~__retres1~2#1 := 1; 10106#L267-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 10100#exists_runnable_thread_returnLabel#2 stop_simulation_#t~ret12#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~3#1 := stop_simulation_#t~ret12#1;havoc stop_simulation_#t~ret12#1; 10096#L394 assume 0 != stop_simulation_~tmp~3#1;stop_simulation_~__retres2~0#1 := 0; 10092#L401 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 10089#stop_simulation_returnLabel#1 start_simulation_#t~ret13#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret12#1, stop_simulation_~tmp~3#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp~4#1 := start_simulation_#t~ret13#1;havoc start_simulation_#t~ret13#1; 10086#L436 assume !(0 != start_simulation_~tmp~4#1); 9792#L419-2 [2023-11-19 07:48:54,594 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-19 07:48:54,594 INFO L85 PathProgramCache]: Analyzing trace with hash -1617647313, now seen corresponding path program 4 times [2023-11-19 07:48:54,594 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-19 07:48:54,594 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2047641068] [2023-11-19 07:48:54,594 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-19 07:48:54,595 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-19 07:48:54,603 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-19 07:48:54,603 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-19 07:48:54,608 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-19 07:48:54,614 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-19 07:48:54,614 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-19 07:48:54,615 INFO L85 PathProgramCache]: Analyzing trace with hash -697707600, now seen corresponding path program 1 times [2023-11-19 07:48:54,615 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-19 07:48:54,615 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [833987635] [2023-11-19 07:48:54,615 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-19 07:48:54,616 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-19 07:48:54,622 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-19 07:48:54,644 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-19 07:48:54,644 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-19 07:48:54,644 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [833987635] [2023-11-19 07:48:54,644 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [833987635] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-19 07:48:54,644 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-19 07:48:54,645 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-19 07:48:54,645 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1854220997] [2023-11-19 07:48:54,645 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-19 07:48:54,645 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-19 07:48:54,646 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-19 07:48:54,646 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-19 07:48:54,646 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-19 07:48:54,646 INFO L87 Difference]: Start difference. First operand 680 states and 889 transitions. cyclomatic complexity: 211 Second operand has 3 states, 3 states have (on average 12.333333333333334) internal successors, (37), 3 states have internal predecessors, (37), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-19 07:48:54,679 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-19 07:48:54,679 INFO L93 Difference]: Finished difference Result 908 states and 1138 transitions. [2023-11-19 07:48:54,679 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 908 states and 1138 transitions. [2023-11-19 07:48:54,687 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 844 [2023-11-19 07:48:54,695 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 908 states to 908 states and 1138 transitions. [2023-11-19 07:48:54,695 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 908 [2023-11-19 07:48:54,696 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 908 [2023-11-19 07:48:54,696 INFO L73 IsDeterministic]: Start isDeterministic. Operand 908 states and 1138 transitions. [2023-11-19 07:48:54,697 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-19 07:48:54,697 INFO L218 hiAutomatonCegarLoop]: Abstraction has 908 states and 1138 transitions. [2023-11-19 07:48:54,699 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 908 states and 1138 transitions. [2023-11-19 07:48:54,713 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 908 to 908. [2023-11-19 07:48:54,715 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 908 states, 908 states have (on average 1.2533039647577093) internal successors, (1138), 907 states have internal predecessors, (1138), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-19 07:48:54,719 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 908 states to 908 states and 1138 transitions. [2023-11-19 07:48:54,719 INFO L240 hiAutomatonCegarLoop]: Abstraction has 908 states and 1138 transitions. [2023-11-19 07:48:54,720 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-19 07:48:54,720 INFO L428 stractBuchiCegarLoop]: Abstraction has 908 states and 1138 transitions. [2023-11-19 07:48:54,720 INFO L335 stractBuchiCegarLoop]: ======== Iteration 10 ============ [2023-11-19 07:48:54,720 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 908 states and 1138 transitions. [2023-11-19 07:48:54,726 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 844 [2023-11-19 07:48:54,726 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-19 07:48:54,726 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-19 07:48:54,727 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-19 07:48:54,727 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-19 07:48:54,727 INFO L748 eck$LassoCheckResult]: Stem: 11349#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(19, 2);call #Ultimate.allocInit(12, 3);~q_buf_0~0 := 0;~q_free~0 := 0;~q_read_ev~0 := 0;~q_write_ev~0 := 0;~q_req_up~0 := 0;~q_ev~0 := 0;~p_num_write~0 := 0;~p_last_write~0 := 0;~p_dw_st~0 := 0;~p_dw_pc~0 := 0;~p_dw_i~0 := 0;~c_num_read~0 := 0;~c_last_read~0 := 0;~c_dr_st~0 := 0;~c_dr_pc~0 := 0;~c_dr_i~0 := 0;~a_t~0 := 0; 11350#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~3#1;havoc main_~__retres1~3#1;assume { :begin_inline_init_model } true;~q_free~0 := 1;~q_write_ev~0 := 2;~q_read_ev~0 := ~q_write_ev~0;~p_num_write~0 := 0;~p_dw_pc~0 := 0;~p_dw_i~0 := 1;~c_num_read~0 := 0;~c_dr_pc~0 := 0;~c_dr_i~0 := 1; 11384#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret13#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~4#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~4#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 11325#L222 assume !(1 == ~q_req_up~0); 11313#L222-2 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 11314#L237 assume !(1 == ~p_dw_i~0);~p_dw_st~0 := 2; 11362#L237-2 assume 1 == ~c_dr_i~0;~c_dr_st~0 := 0; 11404#L242-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 11405#L275 assume !(0 == ~q_read_ev~0); 11406#L275-2 assume !(0 == ~q_write_ev~0); 11407#L280-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;assume { :begin_inline_is_do_write_p_triggered } true;havoc is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;havoc is_do_write_p_triggered_~__retres1~0#1; 11433#L65 assume !(1 == ~p_dw_pc~0); 11365#L65-2 is_do_write_p_triggered_~__retres1~0#1 := 0; 11431#L76 is_do_write_p_triggered_#res#1 := is_do_write_p_triggered_~__retres1~0#1; 11432#is_do_write_p_triggered_returnLabel#1 activate_threads_#t~ret7#1 := is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;assume { :end_inline_is_do_write_p_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1; 11398#L315 assume !(0 != activate_threads_~tmp~1#1); 11399#L315-2 assume { :begin_inline_is_do_read_c_triggered } true;havoc is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;havoc is_do_read_c_triggered_~__retres1~1#1; 11412#L84 assume !(1 == ~c_dr_pc~0); 11413#L84-2 is_do_read_c_triggered_~__retres1~1#1 := 0; 11334#L95 is_do_read_c_triggered_#res#1 := is_do_read_c_triggered_~__retres1~1#1; 11335#is_do_read_c_triggered_returnLabel#1 activate_threads_#t~ret8#1 := is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;assume { :end_inline_is_do_read_c_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 11297#L323 assume !(0 != activate_threads_~tmp___0~1#1); 11298#L323-2 havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 11414#L293 assume !(1 == ~q_read_ev~0); 11415#L293-2 assume !(1 == ~q_write_ev~0); 11400#L298-1 assume { :end_inline_reset_delta_events } true; 11401#L419-2 [2023-11-19 07:48:54,727 INFO L750 eck$LassoCheckResult]: Loop: 11401#L419-2 assume !false; 11472#L420 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret9#1, eval_#t~nondet10#1, eval_#t~nondet11#1, eval_~tmp~2#1, eval_~tmp___0~2#1, eval_~tmp___1~0#1;havoc eval_~tmp~2#1;havoc eval_~tmp___0~2#1;havoc eval_~tmp___1~0#1; 11386#L364 assume !false; 11471#L340 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 11470#L255 assume !(0 == ~p_dw_st~0); 11459#L259 assume !(0 == ~c_dr_st~0);exists_runnable_thread_~__retres1~2#1 := 0; 11469#L267 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 11465#exists_runnable_thread_returnLabel#1 eval_#t~ret9#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp___1~0#1 := eval_#t~ret9#1;havoc eval_#t~ret9#1; 11466#L344 assume !(0 != eval_~tmp___1~0#1); 11505#eval_returnLabel#1 havoc eval_#t~ret9#1, eval_#t~nondet10#1, eval_#t~nondet11#1, eval_~tmp~2#1, eval_~tmp___0~2#1, eval_~tmp___1~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 11504#L222-3 assume !(1 == ~q_req_up~0); 11503#L222-5 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 11502#L275-3 assume !(0 == ~q_read_ev~0); 11501#L275-5 assume !(0 == ~q_write_ev~0); 11500#L280-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;assume { :begin_inline_is_do_write_p_triggered } true;havoc is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;havoc is_do_write_p_triggered_~__retres1~0#1; 11499#L65-3 assume !(1 == ~p_dw_pc~0); 11497#L65-5 is_do_write_p_triggered_~__retres1~0#1 := 0; 11496#L76-1 is_do_write_p_triggered_#res#1 := is_do_write_p_triggered_~__retres1~0#1; 11495#is_do_write_p_triggered_returnLabel#2 activate_threads_#t~ret7#1 := is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;assume { :end_inline_is_do_write_p_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1; 11494#L315-3 assume !(0 != activate_threads_~tmp~1#1); 11493#L315-5 assume { :begin_inline_is_do_read_c_triggered } true;havoc is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;havoc is_do_read_c_triggered_~__retres1~1#1; 11492#L84-3 assume !(1 == ~c_dr_pc~0); 11491#L84-5 is_do_read_c_triggered_~__retres1~1#1 := 0; 11490#L95-1 is_do_read_c_triggered_#res#1 := is_do_read_c_triggered_~__retres1~1#1; 11489#is_do_read_c_triggered_returnLabel#2 activate_threads_#t~ret8#1 := is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;assume { :end_inline_is_do_read_c_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 11488#L323-3 assume 0 != activate_threads_~tmp___0~1#1;~c_dr_st~0 := 0; 11487#L323-5 havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 11486#L293-3 assume !(1 == ~q_read_ev~0); 11485#L293-5 assume !(1 == ~q_write_ev~0); 11484#L298-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret12#1, stop_simulation_~tmp~3#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~3#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 11483#L255-1 assume !(0 == ~p_dw_st~0); 11482#L259-1 assume !(0 == ~c_dr_st~0);exists_runnable_thread_~__retres1~2#1 := 0; 11480#L267-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 11478#exists_runnable_thread_returnLabel#2 stop_simulation_#t~ret12#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~3#1 := stop_simulation_#t~ret12#1;havoc stop_simulation_#t~ret12#1; 11476#L394 assume !(0 != stop_simulation_~tmp~3#1);stop_simulation_~__retres2~0#1 := 1; 11475#L401 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 11474#stop_simulation_returnLabel#1 start_simulation_#t~ret13#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret12#1, stop_simulation_~tmp~3#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp~4#1 := start_simulation_#t~ret13#1;havoc start_simulation_#t~ret13#1; 11473#L436 assume !(0 != start_simulation_~tmp~4#1); 11401#L419-2 [2023-11-19 07:48:54,728 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-19 07:48:54,728 INFO L85 PathProgramCache]: Analyzing trace with hash -1194945487, now seen corresponding path program 1 times [2023-11-19 07:48:54,728 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-19 07:48:54,728 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1949333587] [2023-11-19 07:48:54,728 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-19 07:48:54,728 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-19 07:48:54,734 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-19 07:48:54,748 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-19 07:48:54,748 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-19 07:48:54,749 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1949333587] [2023-11-19 07:48:54,749 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1949333587] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-19 07:48:54,749 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-19 07:48:54,749 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-19 07:48:54,749 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [121518990] [2023-11-19 07:48:54,749 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-19 07:48:54,750 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-19 07:48:54,750 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-19 07:48:54,750 INFO L85 PathProgramCache]: Analyzing trace with hash 1496424074, now seen corresponding path program 1 times [2023-11-19 07:48:54,750 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-19 07:48:54,750 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [764145817] [2023-11-19 07:48:54,750 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-19 07:48:54,751 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-19 07:48:54,757 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-19 07:48:54,772 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-19 07:48:54,772 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-19 07:48:54,772 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [764145817] [2023-11-19 07:48:54,772 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [764145817] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-19 07:48:54,772 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-19 07:48:54,772 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-19 07:48:54,773 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [514067045] [2023-11-19 07:48:54,773 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-19 07:48:54,773 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-19 07:48:54,773 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-19 07:48:54,774 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-19 07:48:54,774 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-19 07:48:54,774 INFO L87 Difference]: Start difference. First operand 908 states and 1138 transitions. cyclomatic complexity: 232 Second operand has 3 states, 3 states have (on average 8.666666666666666) internal successors, (26), 3 states have internal predecessors, (26), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-19 07:48:54,783 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-19 07:48:54,784 INFO L93 Difference]: Finished difference Result 887 states and 1114 transitions. [2023-11-19 07:48:54,784 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 887 states and 1114 transitions. [2023-11-19 07:48:54,791 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 844 [2023-11-19 07:48:54,798 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 887 states to 887 states and 1114 transitions. [2023-11-19 07:48:54,798 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 887 [2023-11-19 07:48:54,799 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 887 [2023-11-19 07:48:54,799 INFO L73 IsDeterministic]: Start isDeterministic. Operand 887 states and 1114 transitions. [2023-11-19 07:48:54,800 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-19 07:48:54,801 INFO L218 hiAutomatonCegarLoop]: Abstraction has 887 states and 1114 transitions. [2023-11-19 07:48:54,802 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 887 states and 1114 transitions. [2023-11-19 07:48:54,818 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 887 to 887. [2023-11-19 07:48:54,820 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 887 states, 887 states have (on average 1.2559188275084554) internal successors, (1114), 886 states have internal predecessors, (1114), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-19 07:48:54,824 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 887 states to 887 states and 1114 transitions. [2023-11-19 07:48:54,824 INFO L240 hiAutomatonCegarLoop]: Abstraction has 887 states and 1114 transitions. [2023-11-19 07:48:54,825 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-19 07:48:54,825 INFO L428 stractBuchiCegarLoop]: Abstraction has 887 states and 1114 transitions. [2023-11-19 07:48:54,825 INFO L335 stractBuchiCegarLoop]: ======== Iteration 11 ============ [2023-11-19 07:48:54,825 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 887 states and 1114 transitions. [2023-11-19 07:48:54,830 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 844 [2023-11-19 07:48:54,830 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-19 07:48:54,830 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-19 07:48:54,830 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-19 07:48:54,831 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-19 07:48:54,831 INFO L748 eck$LassoCheckResult]: Stem: 13152#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(19, 2);call #Ultimate.allocInit(12, 3);~q_buf_0~0 := 0;~q_free~0 := 0;~q_read_ev~0 := 0;~q_write_ev~0 := 0;~q_req_up~0 := 0;~q_ev~0 := 0;~p_num_write~0 := 0;~p_last_write~0 := 0;~p_dw_st~0 := 0;~p_dw_pc~0 := 0;~p_dw_i~0 := 0;~c_num_read~0 := 0;~c_last_read~0 := 0;~c_dr_st~0 := 0;~c_dr_pc~0 := 0;~c_dr_i~0 := 0;~a_t~0 := 0; 13153#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~3#1;havoc main_~__retres1~3#1;assume { :begin_inline_init_model } true;~q_free~0 := 1;~q_write_ev~0 := 2;~q_read_ev~0 := ~q_write_ev~0;~p_num_write~0 := 0;~p_dw_pc~0 := 0;~p_dw_i~0 := 1;~c_num_read~0 := 0;~c_dr_pc~0 := 0;~c_dr_i~0 := 1; 13180#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret13#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~4#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~4#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 13126#L222 assume !(1 == ~q_req_up~0); 13117#L222-2 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 13118#L237 assume 1 == ~p_dw_i~0;~p_dw_st~0 := 0; 13160#L237-2 assume 1 == ~c_dr_i~0;~c_dr_st~0 := 0; 13187#L242-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 13182#L275 assume !(0 == ~q_read_ev~0); 13183#L275-2 assume !(0 == ~q_write_ev~0); 13166#L280-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;assume { :begin_inline_is_do_write_p_triggered } true;havoc is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;havoc is_do_write_p_triggered_~__retres1~0#1; 13167#L65 assume !(1 == ~p_dw_pc~0); 13164#L65-2 is_do_write_p_triggered_~__retres1~0#1 := 0; 13175#L76 is_do_write_p_triggered_#res#1 := is_do_write_p_triggered_~__retres1~0#1; 13146#is_do_write_p_triggered_returnLabel#1 activate_threads_#t~ret7#1 := is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;assume { :end_inline_is_do_write_p_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1; 13147#L315 assume !(0 != activate_threads_~tmp~1#1); 13123#L315-2 assume { :begin_inline_is_do_read_c_triggered } true;havoc is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;havoc is_do_read_c_triggered_~__retres1~1#1; 13124#L84 assume !(1 == ~c_dr_pc~0); 13140#L84-2 is_do_read_c_triggered_~__retres1~1#1 := 0; 13135#L95 is_do_read_c_triggered_#res#1 := is_do_read_c_triggered_~__retres1~1#1; 13136#is_do_read_c_triggered_returnLabel#1 activate_threads_#t~ret8#1 := is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;assume { :end_inline_is_do_read_c_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 13099#L323 assume !(0 != activate_threads_~tmp___0~1#1); 13100#L323-2 havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 13202#L293 assume !(1 == ~q_read_ev~0); 13092#L293-2 assume !(1 == ~q_write_ev~0); 13093#L298-1 assume { :end_inline_reset_delta_events } true; 13194#L419-2 assume !false; 13245#L420 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret9#1, eval_#t~nondet10#1, eval_#t~nondet11#1, eval_~tmp~2#1, eval_~tmp___0~2#1, eval_~tmp___1~0#1;havoc eval_~tmp~2#1;havoc eval_~tmp___0~2#1;havoc eval_~tmp___1~0#1; 13244#L364 assume !false; 13243#L340 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 13241#L255 assume !(0 == ~p_dw_st~0); 13242#L259 [2023-11-19 07:48:54,831 INFO L750 eck$LassoCheckResult]: Loop: 13242#L259 assume 0 == ~c_dr_st~0;exists_runnable_thread_~__retres1~2#1 := 1; 13248#L267 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 13249#exists_runnable_thread_returnLabel#1 eval_#t~ret9#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp___1~0#1 := eval_#t~ret9#1;havoc eval_#t~ret9#1; 13237#L344 assume 0 != eval_~tmp___1~0#1; 13228#L344-1 assume !(0 == ~p_dw_st~0); 13227#L349 assume !(0 == ~c_dr_st~0); 13178#L364 assume !false; 13252#L340 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 13251#L255 assume !(0 == ~p_dw_st~0); 13242#L259 [2023-11-19 07:48:54,831 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-19 07:48:54,831 INFO L85 PathProgramCache]: Analyzing trace with hash -1220673252, now seen corresponding path program 1 times [2023-11-19 07:48:54,832 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-19 07:48:54,832 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2146954033] [2023-11-19 07:48:54,832 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-19 07:48:54,832 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-19 07:48:54,838 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-19 07:48:54,856 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-19 07:48:54,856 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-19 07:48:54,856 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2146954033] [2023-11-19 07:48:54,857 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2146954033] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-19 07:48:54,857 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-19 07:48:54,857 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2023-11-19 07:48:54,857 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1566480570] [2023-11-19 07:48:54,857 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-19 07:48:54,857 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-19 07:48:54,858 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-19 07:48:54,858 INFO L85 PathProgramCache]: Analyzing trace with hash -563681025, now seen corresponding path program 1 times [2023-11-19 07:48:54,858 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-19 07:48:54,858 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [619513032] [2023-11-19 07:48:54,858 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-19 07:48:54,859 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-19 07:48:54,861 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-19 07:48:54,868 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-19 07:48:54,868 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-19 07:48:54,868 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [619513032] [2023-11-19 07:48:54,869 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [619513032] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-19 07:48:54,869 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-19 07:48:54,869 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2023-11-19 07:48:54,869 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [933905751] [2023-11-19 07:48:54,869 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-19 07:48:54,869 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-19 07:48:54,870 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-19 07:48:54,870 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-19 07:48:54,870 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-19 07:48:54,870 INFO L87 Difference]: Start difference. First operand 887 states and 1114 transitions. cyclomatic complexity: 229 Second operand has 3 states, 3 states have (on average 3.0) internal successors, (9), 2 states have internal predecessors, (9), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-19 07:48:54,896 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-19 07:48:54,896 INFO L93 Difference]: Finished difference Result 1209 states and 1497 transitions. [2023-11-19 07:48:54,896 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1209 states and 1497 transitions. [2023-11-19 07:48:54,905 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 1166 [2023-11-19 07:48:54,915 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1209 states to 1209 states and 1497 transitions. [2023-11-19 07:48:54,915 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1209 [2023-11-19 07:48:54,916 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1209 [2023-11-19 07:48:54,916 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1209 states and 1497 transitions. [2023-11-19 07:48:54,918 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-19 07:48:54,918 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1209 states and 1497 transitions. [2023-11-19 07:48:54,920 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1209 states and 1497 transitions. [2023-11-19 07:48:54,968 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1209 to 1209. [2023-11-19 07:48:54,971 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1209 states, 1209 states have (on average 1.2382133995037221) internal successors, (1497), 1208 states have internal predecessors, (1497), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-19 07:48:54,976 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1209 states to 1209 states and 1497 transitions. [2023-11-19 07:48:54,976 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1209 states and 1497 transitions. [2023-11-19 07:48:54,977 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-19 07:48:54,977 INFO L428 stractBuchiCegarLoop]: Abstraction has 1209 states and 1497 transitions. [2023-11-19 07:48:54,978 INFO L335 stractBuchiCegarLoop]: ======== Iteration 12 ============ [2023-11-19 07:48:54,978 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1209 states and 1497 transitions. [2023-11-19 07:48:54,984 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 1166 [2023-11-19 07:48:54,984 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-19 07:48:54,985 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-19 07:48:54,985 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-19 07:48:54,985 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-19 07:48:54,985 INFO L748 eck$LassoCheckResult]: Stem: 15254#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(19, 2);call #Ultimate.allocInit(12, 3);~q_buf_0~0 := 0;~q_free~0 := 0;~q_read_ev~0 := 0;~q_write_ev~0 := 0;~q_req_up~0 := 0;~q_ev~0 := 0;~p_num_write~0 := 0;~p_last_write~0 := 0;~p_dw_st~0 := 0;~p_dw_pc~0 := 0;~p_dw_i~0 := 0;~c_num_read~0 := 0;~c_last_read~0 := 0;~c_dr_st~0 := 0;~c_dr_pc~0 := 0;~c_dr_i~0 := 0;~a_t~0 := 0; 15255#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~3#1;havoc main_~__retres1~3#1;assume { :begin_inline_init_model } true;~q_free~0 := 1;~q_write_ev~0 := 2;~q_read_ev~0 := ~q_write_ev~0;~p_num_write~0 := 0;~p_dw_pc~0 := 0;~p_dw_i~0 := 1;~c_num_read~0 := 0;~c_dr_pc~0 := 0;~c_dr_i~0 := 1; 15284#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret13#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~4#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~4#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 15229#L222 assume !(1 == ~q_req_up~0); 15219#L222-2 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 15220#L237 assume 1 == ~p_dw_i~0;~p_dw_st~0 := 0; 15262#L237-2 assume 1 == ~c_dr_i~0;~c_dr_st~0 := 0; 15289#L242-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 15287#L275 assume !(0 == ~q_read_ev~0); 15288#L275-2 assume !(0 == ~q_write_ev~0); 15268#L280-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;assume { :begin_inline_is_do_write_p_triggered } true;havoc is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;havoc is_do_write_p_triggered_~__retres1~0#1; 15269#L65 assume !(1 == ~p_dw_pc~0); 15266#L65-2 is_do_write_p_triggered_~__retres1~0#1 := 0; 15279#L76 is_do_write_p_triggered_#res#1 := is_do_write_p_triggered_~__retres1~0#1; 15250#is_do_write_p_triggered_returnLabel#1 activate_threads_#t~ret7#1 := is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;assume { :end_inline_is_do_write_p_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1; 15251#L315 assume !(0 != activate_threads_~tmp~1#1); 15225#L315-2 assume { :begin_inline_is_do_read_c_triggered } true;havoc is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;havoc is_do_read_c_triggered_~__retres1~1#1; 15226#L84 assume !(1 == ~c_dr_pc~0); 15243#L84-2 is_do_read_c_triggered_~__retres1~1#1 := 0; 15237#L95 is_do_read_c_triggered_#res#1 := is_do_read_c_triggered_~__retres1~1#1; 15238#is_do_read_c_triggered_returnLabel#1 activate_threads_#t~ret8#1 := is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;assume { :end_inline_is_do_read_c_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 15201#L323 assume !(0 != activate_threads_~tmp___0~1#1); 15202#L323-2 havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 15305#L293 assume !(1 == ~q_read_ev~0); 15195#L293-2 assume !(1 == ~q_write_ev~0); 15196#L298-1 assume { :end_inline_reset_delta_events } true; 15297#L419-2 assume !false; 15366#L420 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret9#1, eval_#t~nondet10#1, eval_#t~nondet11#1, eval_~tmp~2#1, eval_~tmp___0~2#1, eval_~tmp___1~0#1;havoc eval_~tmp~2#1;havoc eval_~tmp___0~2#1;havoc eval_~tmp___1~0#1; 15365#L364 assume !false; 15363#L340 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 15361#L255 assume !(0 == ~p_dw_st~0); 15360#L259 [2023-11-19 07:48:54,986 INFO L750 eck$LassoCheckResult]: Loop: 15360#L259 assume 0 == ~c_dr_st~0;exists_runnable_thread_~__retres1~2#1 := 1; 15358#L267 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 15356#exists_runnable_thread_returnLabel#1 eval_#t~ret9#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp___1~0#1 := eval_#t~ret9#1;havoc eval_#t~ret9#1; 15354#L344 assume 0 != eval_~tmp___1~0#1; 15345#L344-1 assume !(0 == ~p_dw_st~0); 15344#L349 assume 0 == ~c_dr_st~0;havoc eval_#t~nondet11#1;eval_~tmp___0~2#1 := eval_#t~nondet11#1;havoc eval_#t~nondet11#1; 15281#L368 assume !(0 != eval_~tmp___0~2#1); 15282#L364 assume !false; 15364#L340 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 15362#L255 assume !(0 == ~p_dw_st~0); 15360#L259 [2023-11-19 07:48:54,986 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-19 07:48:54,986 INFO L85 PathProgramCache]: Analyzing trace with hash -1220673252, now seen corresponding path program 2 times [2023-11-19 07:48:54,986 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-19 07:48:54,987 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [248579248] [2023-11-19 07:48:54,987 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-19 07:48:54,987 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-19 07:48:54,995 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-19 07:48:55,015 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-19 07:48:55,015 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-19 07:48:55,015 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [248579248] [2023-11-19 07:48:55,015 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [248579248] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-19 07:48:55,015 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-19 07:48:55,015 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2023-11-19 07:48:55,016 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2095018999] [2023-11-19 07:48:55,016 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-19 07:48:55,016 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-19 07:48:55,016 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-19 07:48:55,016 INFO L85 PathProgramCache]: Analyzing trace with hash -351055962, now seen corresponding path program 1 times [2023-11-19 07:48:55,017 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-19 07:48:55,017 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1282385995] [2023-11-19 07:48:55,017 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-19 07:48:55,017 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-19 07:48:55,020 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-19 07:48:55,021 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-19 07:48:55,023 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-19 07:48:55,025 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-19 07:48:55,099 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-19 07:48:55,100 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-19 07:48:55,100 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-19 07:48:55,100 INFO L87 Difference]: Start difference. First operand 1209 states and 1497 transitions. cyclomatic complexity: 290 Second operand has 3 states, 2 states have (on average 15.5) internal successors, (31), 3 states have internal predecessors, (31), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-19 07:48:55,143 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-19 07:48:55,144 INFO L93 Difference]: Finished difference Result 1209 states and 1447 transitions. [2023-11-19 07:48:55,144 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1209 states and 1447 transitions. [2023-11-19 07:48:55,152 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 1166 [2023-11-19 07:48:55,161 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1209 states to 1209 states and 1447 transitions. [2023-11-19 07:48:55,161 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1209 [2023-11-19 07:48:55,163 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1209 [2023-11-19 07:48:55,163 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1209 states and 1447 transitions. [2023-11-19 07:48:55,164 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-19 07:48:55,165 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1209 states and 1447 transitions. [2023-11-19 07:48:55,166 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1209 states and 1447 transitions. [2023-11-19 07:48:55,184 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1209 to 1209. [2023-11-19 07:48:55,187 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1209 states, 1209 states have (on average 1.196856906534326) internal successors, (1447), 1208 states have internal predecessors, (1447), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-19 07:48:55,192 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1209 states to 1209 states and 1447 transitions. [2023-11-19 07:48:55,192 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1209 states and 1447 transitions. [2023-11-19 07:48:55,193 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-19 07:48:55,195 INFO L428 stractBuchiCegarLoop]: Abstraction has 1209 states and 1447 transitions. [2023-11-19 07:48:55,195 INFO L335 stractBuchiCegarLoop]: ======== Iteration 13 ============ [2023-11-19 07:48:55,195 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1209 states and 1447 transitions. [2023-11-19 07:48:55,201 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 1166 [2023-11-19 07:48:55,201 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-19 07:48:55,202 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-19 07:48:55,202 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-19 07:48:55,202 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1] [2023-11-19 07:48:55,203 INFO L748 eck$LassoCheckResult]: Stem: 17676#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(19, 2);call #Ultimate.allocInit(12, 3);~q_buf_0~0 := 0;~q_free~0 := 0;~q_read_ev~0 := 0;~q_write_ev~0 := 0;~q_req_up~0 := 0;~q_ev~0 := 0;~p_num_write~0 := 0;~p_last_write~0 := 0;~p_dw_st~0 := 0;~p_dw_pc~0 := 0;~p_dw_i~0 := 0;~c_num_read~0 := 0;~c_last_read~0 := 0;~c_dr_st~0 := 0;~c_dr_pc~0 := 0;~c_dr_i~0 := 0;~a_t~0 := 0; 17677#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~3#1;havoc main_~__retres1~3#1;assume { :begin_inline_init_model } true;~q_free~0 := 1;~q_write_ev~0 := 2;~q_read_ev~0 := ~q_write_ev~0;~p_num_write~0 := 0;~p_dw_pc~0 := 0;~p_dw_i~0 := 1;~c_num_read~0 := 0;~c_dr_pc~0 := 0;~c_dr_i~0 := 1; 17707#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret13#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~4#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~4#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 17652#L222 assume !(1 == ~q_req_up~0); 17641#L222-2 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 17642#L237 assume 1 == ~p_dw_i~0;~p_dw_st~0 := 0; 17688#L237-2 assume 1 == ~c_dr_i~0;~c_dr_st~0 := 0; 17715#L242-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 17713#L275 assume !(0 == ~q_read_ev~0); 17714#L275-2 assume !(0 == ~q_write_ev~0); 17693#L280-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;assume { :begin_inline_is_do_write_p_triggered } true;havoc is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;havoc is_do_write_p_triggered_~__retres1~0#1; 17694#L65 assume !(1 == ~p_dw_pc~0); 17690#L65-2 is_do_write_p_triggered_~__retres1~0#1 := 0; 17705#L76 is_do_write_p_triggered_#res#1 := is_do_write_p_triggered_~__retres1~0#1; 17673#is_do_write_p_triggered_returnLabel#1 activate_threads_#t~ret7#1 := is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;assume { :end_inline_is_do_write_p_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1; 17674#L315 assume !(0 != activate_threads_~tmp~1#1); 17649#L315-2 assume { :begin_inline_is_do_read_c_triggered } true;havoc is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;havoc is_do_read_c_triggered_~__retres1~1#1; 17650#L84 assume !(1 == ~c_dr_pc~0); 17667#L84-2 is_do_read_c_triggered_~__retres1~1#1 := 0; 17660#L95 is_do_read_c_triggered_#res#1 := is_do_read_c_triggered_~__retres1~1#1; 17661#is_do_read_c_triggered_returnLabel#1 activate_threads_#t~ret8#1 := is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;assume { :end_inline_is_do_read_c_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 17625#L323 assume !(0 != activate_threads_~tmp___0~1#1); 17626#L323-2 havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 17727#L293 assume !(1 == ~q_read_ev~0); 17619#L293-2 assume !(1 == ~q_write_ev~0); 17620#L298-1 assume { :end_inline_reset_delta_events } true; 17720#L419-2 assume !false; 17780#L420 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret9#1, eval_#t~nondet10#1, eval_#t~nondet11#1, eval_~tmp~2#1, eval_~tmp___0~2#1, eval_~tmp___1~0#1;havoc eval_~tmp~2#1;havoc eval_~tmp___0~2#1;havoc eval_~tmp___1~0#1; 17779#L364 assume !false; 17778#L340 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 17777#L255 assume 0 == ~p_dw_st~0;exists_runnable_thread_~__retres1~2#1 := 1; 17776#L267 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 17775#exists_runnable_thread_returnLabel#1 eval_#t~ret9#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp___1~0#1 := eval_#t~ret9#1;havoc eval_#t~ret9#1; 17774#L344 assume 0 != eval_~tmp___1~0#1; 17772#L344-1 assume 0 == ~p_dw_st~0;havoc eval_#t~nondet10#1;eval_~tmp~2#1 := eval_#t~nondet10#1;havoc eval_#t~nondet10#1; 17770#L353 assume 0 != eval_~tmp~2#1;~p_dw_st~0 := 1;assume { :begin_inline_do_write_p } true;havoc do_write_p_#t~nondet6#1; 17767#L128 assume !(0 == ~p_dw_pc~0); 17768#L131 assume 1 == ~p_dw_pc~0; 17763#L141 [2023-11-19 07:48:55,203 INFO L750 eck$LassoCheckResult]: Loop: 17763#L141 havoc do_write_p_#t~nondet6#1;~q_buf_0~0 := do_write_p_#t~nondet6#1;havoc do_write_p_#t~nondet6#1;~p_last_write~0 := ~q_buf_0~0;~p_num_write~0 := 1 + ~p_num_write~0;~q_free~0 := 0;~q_req_up~0 := 1; 18105#L139-1 assume !false; 18102#L140 assume !(0 == ~q_free~0); 17763#L141 [2023-11-19 07:48:55,204 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-19 07:48:55,204 INFO L85 PathProgramCache]: Analyzing trace with hash -1071076411, now seen corresponding path program 1 times [2023-11-19 07:48:55,204 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-19 07:48:55,204 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [657383775] [2023-11-19 07:48:55,204 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-19 07:48:55,205 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-19 07:48:55,214 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-19 07:48:55,254 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-19 07:48:55,255 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-19 07:48:55,255 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [657383775] [2023-11-19 07:48:55,255 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [657383775] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-19 07:48:55,255 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-19 07:48:55,255 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-19 07:48:55,255 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [585951638] [2023-11-19 07:48:55,256 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-19 07:48:55,257 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-19 07:48:55,257 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-19 07:48:55,257 INFO L85 PathProgramCache]: Analyzing trace with hash 220166, now seen corresponding path program 1 times [2023-11-19 07:48:55,257 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-19 07:48:55,259 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [269527413] [2023-11-19 07:48:55,259 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-19 07:48:55,260 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-19 07:48:55,265 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-19 07:48:55,272 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-19 07:48:55,273 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-19 07:48:55,273 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [269527413] [2023-11-19 07:48:55,273 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [269527413] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-19 07:48:55,273 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-19 07:48:55,273 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [1] imperfect sequences [] total 1 [2023-11-19 07:48:55,273 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [239259371] [2023-11-19 07:48:55,274 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-19 07:48:55,274 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-19 07:48:55,274 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-19 07:48:55,275 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-19 07:48:55,275 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-19 07:48:55,275 INFO L87 Difference]: Start difference. First operand 1209 states and 1447 transitions. cyclomatic complexity: 240 Second operand has 3 states, 2 states have (on average 1.5) internal successors, (3), 2 states have internal predecessors, (3), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-19 07:48:55,310 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-19 07:48:55,310 INFO L93 Difference]: Finished difference Result 2195 states and 2579 transitions. [2023-11-19 07:48:55,310 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2195 states and 2579 transitions. [2023-11-19 07:48:55,330 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 2152 [2023-11-19 07:48:55,346 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2195 states to 2195 states and 2579 transitions. [2023-11-19 07:48:55,346 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2195 [2023-11-19 07:48:55,349 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2195 [2023-11-19 07:48:55,350 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2195 states and 2579 transitions. [2023-11-19 07:48:55,352 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-19 07:48:55,353 INFO L218 hiAutomatonCegarLoop]: Abstraction has 2195 states and 2579 transitions. [2023-11-19 07:48:55,355 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2195 states and 2579 transitions. [2023-11-19 07:48:55,386 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2195 to 1879. [2023-11-19 07:48:55,389 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1879 states, 1879 states have (on average 1.1852048962213944) internal successors, (2227), 1878 states have internal predecessors, (2227), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-19 07:48:55,397 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1879 states to 1879 states and 2227 transitions. [2023-11-19 07:48:55,397 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1879 states and 2227 transitions. [2023-11-19 07:48:55,397 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-19 07:48:55,398 INFO L428 stractBuchiCegarLoop]: Abstraction has 1879 states and 2227 transitions. [2023-11-19 07:48:55,399 INFO L335 stractBuchiCegarLoop]: ======== Iteration 14 ============ [2023-11-19 07:48:55,399 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1879 states and 2227 transitions. [2023-11-19 07:48:55,406 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 1836 [2023-11-19 07:48:55,406 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-19 07:48:55,407 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-19 07:48:55,412 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-19 07:48:55,412 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-19 07:48:55,413 INFO L748 eck$LassoCheckResult]: Stem: 21084#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(19, 2);call #Ultimate.allocInit(12, 3);~q_buf_0~0 := 0;~q_free~0 := 0;~q_read_ev~0 := 0;~q_write_ev~0 := 0;~q_req_up~0 := 0;~q_ev~0 := 0;~p_num_write~0 := 0;~p_last_write~0 := 0;~p_dw_st~0 := 0;~p_dw_pc~0 := 0;~p_dw_i~0 := 0;~c_num_read~0 := 0;~c_last_read~0 := 0;~c_dr_st~0 := 0;~c_dr_pc~0 := 0;~c_dr_i~0 := 0;~a_t~0 := 0; 21085#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~3#1;havoc main_~__retres1~3#1;assume { :begin_inline_init_model } true;~q_free~0 := 1;~q_write_ev~0 := 2;~q_read_ev~0 := ~q_write_ev~0;~p_num_write~0 := 0;~p_dw_pc~0 := 0;~p_dw_i~0 := 1;~c_num_read~0 := 0;~c_dr_pc~0 := 0;~c_dr_i~0 := 1; 21114#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret13#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~4#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~4#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 21062#L222 assume !(1 == ~q_req_up~0); 21053#L222-2 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 21054#L237 assume 1 == ~p_dw_i~0;~p_dw_st~0 := 0; 21094#L237-2 assume 1 == ~c_dr_i~0;~c_dr_st~0 := 0; 21119#L242-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 21117#L275 assume !(0 == ~q_read_ev~0); 21118#L275-2 assume !(0 == ~q_write_ev~0); 21101#L280-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;assume { :begin_inline_is_do_write_p_triggered } true;havoc is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;havoc is_do_write_p_triggered_~__retres1~0#1; 21102#L65 assume !(1 == ~p_dw_pc~0); 21096#L65-2 is_do_write_p_triggered_~__retres1~0#1 := 0; 21109#L76 is_do_write_p_triggered_#res#1 := is_do_write_p_triggered_~__retres1~0#1; 21081#is_do_write_p_triggered_returnLabel#1 activate_threads_#t~ret7#1 := is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;assume { :end_inline_is_do_write_p_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1; 21082#L315 assume !(0 != activate_threads_~tmp~1#1); 21059#L315-2 assume { :begin_inline_is_do_read_c_triggered } true;havoc is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;havoc is_do_read_c_triggered_~__retres1~1#1; 21060#L84 assume !(1 == ~c_dr_pc~0); 21076#L84-2 is_do_read_c_triggered_~__retres1~1#1 := 0; 21071#L95 is_do_read_c_triggered_#res#1 := is_do_read_c_triggered_~__retres1~1#1; 21072#is_do_read_c_triggered_returnLabel#1 activate_threads_#t~ret8#1 := is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;assume { :end_inline_is_do_read_c_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 21036#L323 assume !(0 != activate_threads_~tmp___0~1#1); 21037#L323-2 havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 21133#L293 assume !(1 == ~q_read_ev~0); 21030#L293-2 assume !(1 == ~q_write_ev~0); 21031#L298-1 assume { :end_inline_reset_delta_events } true; 21125#L419-2 assume !false; 21189#L420 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret9#1, eval_#t~nondet10#1, eval_#t~nondet11#1, eval_~tmp~2#1, eval_~tmp___0~2#1, eval_~tmp___1~0#1;havoc eval_~tmp~2#1;havoc eval_~tmp___0~2#1;havoc eval_~tmp___1~0#1; 21188#L364 assume !false; 21187#L340 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 21186#L255 assume 0 == ~p_dw_st~0;exists_runnable_thread_~__retres1~2#1 := 1; 21185#L267 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 21184#exists_runnable_thread_returnLabel#1 eval_#t~ret9#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp___1~0#1 := eval_#t~ret9#1;havoc eval_#t~ret9#1; 21183#L344 assume 0 != eval_~tmp___1~0#1; 21181#L344-1 assume 0 == ~p_dw_st~0;havoc eval_#t~nondet10#1;eval_~tmp~2#1 := eval_#t~nondet10#1;havoc eval_#t~nondet10#1; 21179#L353 assume 0 != eval_~tmp~2#1;~p_dw_st~0 := 1;assume { :begin_inline_do_write_p } true;havoc do_write_p_#t~nondet6#1; 21176#L128 assume !(0 == ~p_dw_pc~0); 21177#L131 assume 1 == ~p_dw_pc~0; 21172#L141 [2023-11-19 07:48:55,413 INFO L750 eck$LassoCheckResult]: Loop: 21172#L141 havoc do_write_p_#t~nondet6#1;~q_buf_0~0 := do_write_p_#t~nondet6#1;havoc do_write_p_#t~nondet6#1;~p_last_write~0 := ~q_buf_0~0;~p_num_write~0 := 1 + ~p_num_write~0;~q_free~0 := 0;~q_req_up~0 := 1; 22752#L139-1 assume !false; 22699#L140 assume 0 == ~q_free~0;~p_dw_st~0 := 2;~p_dw_pc~0 := 1; 21776#do_write_p_returnLabel#1 havoc do_write_p_#t~nondet6#1;assume { :end_inline_do_write_p } true; 21067#L349 assume 0 == ~c_dr_st~0;havoc eval_#t~nondet11#1;eval_~tmp___0~2#1 := eval_#t~nondet11#1;havoc eval_#t~nondet11#1; 21068#L368 assume 0 != eval_~tmp___0~2#1;~c_dr_st~0 := 1;assume { :begin_inline_do_read_c } true;havoc do_read_c_~a~0#1;havoc do_read_c_~a~0#1; 21191#L169 assume 0 == ~c_dr_pc~0; 21147#L198-1 assume !false; 21077#L181 assume !(1 == ~q_free~0); 21058#L182-1 do_read_c_~a~0#1 := ~q_buf_0~0;~c_last_read~0 := do_read_c_~a~0#1;~c_num_read~0 := 1 + ~c_num_read~0;~q_free~0 := 1;~q_req_up~0 := 1; 21038#L198 assume ~p_last_write~0 == ~c_last_read~0; 21039#L199 assume ~p_num_write~0 == ~c_num_read~0; 21239#L198-1 assume !false; 21240#L181 assume 1 == ~q_free~0;~c_dr_st~0 := 2;~c_dr_pc~0 := 1;~a_t~0 := do_read_c_~a~0#1; 21227#do_read_c_returnLabel#1 havoc do_read_c_~a~0#1;assume { :end_inline_do_read_c } true; 21228#L364 assume !false; 21218#L340 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 21219#L255 assume !(0 == ~p_dw_st~0); 21209#L259 assume !(0 == ~c_dr_st~0);exists_runnable_thread_~__retres1~2#1 := 0; 21211#L267 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 21201#exists_runnable_thread_returnLabel#1 eval_#t~ret9#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp___1~0#1 := eval_#t~ret9#1;havoc eval_#t~ret9#1; 21202#L344 assume !(0 != eval_~tmp___1~0#1); 21376#eval_returnLabel#1 havoc eval_#t~ret9#1, eval_#t~nondet10#1, eval_#t~nondet11#1, eval_~tmp~2#1, eval_~tmp___0~2#1, eval_~tmp___1~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 21374#L222-3 assume 1 == ~q_req_up~0;assume { :begin_inline_update_fifo_q } true; 21375#L35-3 assume !(0 == ~q_free~0); 21653#L35-5 assume 1 == ~q_free~0;~q_read_ev~0 := 0; 21654#L40-3 ~q_ev~0 := 0;~q_req_up~0 := 0; 21678#update_fifo_q_returnLabel#2 assume { :end_inline_update_fifo_q } true; 21675#L222-5 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 21673#L275-3 assume 0 == ~q_read_ev~0;~q_read_ev~0 := 1; 21669#L275-5 assume !(0 == ~q_write_ev~0); 21666#L280-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;assume { :begin_inline_is_do_write_p_triggered } true;havoc is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;havoc is_do_write_p_triggered_~__retres1~0#1; 21664#L65-3 assume 1 == ~p_dw_pc~0; 21660#L66-1 assume 1 == ~q_read_ev~0;is_do_write_p_triggered_~__retres1~0#1 := 1; 21657#L76-1 is_do_write_p_triggered_#res#1 := is_do_write_p_triggered_~__retres1~0#1; 21658#is_do_write_p_triggered_returnLabel#2 activate_threads_#t~ret7#1 := is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;assume { :end_inline_is_do_write_p_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1; 22354#L315-3 assume 0 != activate_threads_~tmp~1#1;~p_dw_st~0 := 0; 22353#L315-5 assume { :begin_inline_is_do_read_c_triggered } true;havoc is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;havoc is_do_read_c_triggered_~__retres1~1#1; 22351#L84-3 assume !(1 == ~c_dr_pc~0); 22080#L84-5 is_do_read_c_triggered_~__retres1~1#1 := 0; 22076#L95-1 is_do_read_c_triggered_#res#1 := is_do_read_c_triggered_~__retres1~1#1; 22071#is_do_read_c_triggered_returnLabel#2 activate_threads_#t~ret8#1 := is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;assume { :end_inline_is_do_read_c_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 22066#L323-3 assume 0 != activate_threads_~tmp___0~1#1;~c_dr_st~0 := 0; 22013#L323-5 havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 22794#L293-3 assume 1 == ~q_read_ev~0;~q_read_ev~0 := 2; 22792#L293-5 assume !(1 == ~q_write_ev~0); 22790#L298-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret12#1, stop_simulation_~tmp~3#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~3#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 22788#L255-1 assume 0 == ~p_dw_st~0;exists_runnable_thread_~__retres1~2#1 := 1; 22786#L267-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 22784#exists_runnable_thread_returnLabel#2 stop_simulation_#t~ret12#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~3#1 := stop_simulation_#t~ret12#1;havoc stop_simulation_#t~ret12#1; 22782#L394 assume 0 != stop_simulation_~tmp~3#1;stop_simulation_~__retres2~0#1 := 0; 22780#L401 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 22778#stop_simulation_returnLabel#1 start_simulation_#t~ret13#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret12#1, stop_simulation_~tmp~3#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp~4#1 := start_simulation_#t~ret13#1;havoc start_simulation_#t~ret13#1; 22776#L436 assume !(0 != start_simulation_~tmp~4#1); 22774#L419-2 assume !false; 22772#L420 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret9#1, eval_#t~nondet10#1, eval_#t~nondet11#1, eval_~tmp~2#1, eval_~tmp___0~2#1, eval_~tmp___1~0#1;havoc eval_~tmp~2#1;havoc eval_~tmp___0~2#1;havoc eval_~tmp___1~0#1; 22770#L364 assume !false; 22768#L340 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 22766#L255 assume 0 == ~p_dw_st~0;exists_runnable_thread_~__retres1~2#1 := 1; 22764#L267 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 22762#exists_runnable_thread_returnLabel#1 eval_#t~ret9#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp___1~0#1 := eval_#t~ret9#1;havoc eval_#t~ret9#1; 22760#L344 assume 0 != eval_~tmp___1~0#1; 22758#L344-1 assume 0 == ~p_dw_st~0;havoc eval_#t~nondet10#1;eval_~tmp~2#1 := eval_#t~nondet10#1;havoc eval_#t~nondet10#1; 22757#L353 assume 0 != eval_~tmp~2#1;~p_dw_st~0 := 1;assume { :begin_inline_do_write_p } true;havoc do_write_p_#t~nondet6#1; 22755#L128 assume !(0 == ~p_dw_pc~0); 22756#L131 assume 1 == ~p_dw_pc~0; 21172#L141 [2023-11-19 07:48:55,413 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-19 07:48:55,414 INFO L85 PathProgramCache]: Analyzing trace with hash -1071076411, now seen corresponding path program 2 times [2023-11-19 07:48:55,414 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-19 07:48:55,414 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1171599150] [2023-11-19 07:48:55,414 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-19 07:48:55,414 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-19 07:48:55,421 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-19 07:48:55,446 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-19 07:48:55,446 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-19 07:48:55,446 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1171599150] [2023-11-19 07:48:55,446 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1171599150] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-19 07:48:55,446 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-19 07:48:55,446 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-19 07:48:55,446 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [761867126] [2023-11-19 07:48:55,447 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-19 07:48:55,448 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-19 07:48:55,449 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-19 07:48:55,449 INFO L85 PathProgramCache]: Analyzing trace with hash -521763250, now seen corresponding path program 1 times [2023-11-19 07:48:55,449 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-19 07:48:55,449 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [770466084] [2023-11-19 07:48:55,449 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-19 07:48:55,450 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-19 07:48:55,460 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-19 07:48:55,500 INFO L134 CoverageAnalysis]: Checked inductivity of 8 backedges. 6 proven. 0 refuted. 0 times theorem prover too weak. 2 trivial. 0 not checked. [2023-11-19 07:48:55,501 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-19 07:48:55,501 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [770466084] [2023-11-19 07:48:55,501 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [770466084] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-19 07:48:55,501 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-19 07:48:55,501 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-19 07:48:55,501 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1645870621] [2023-11-19 07:48:55,501 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-19 07:48:55,502 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-19 07:48:55,502 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-19 07:48:55,502 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-19 07:48:55,502 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-19 07:48:55,502 INFO L87 Difference]: Start difference. First operand 1879 states and 2227 transitions. cyclomatic complexity: 350 Second operand has 3 states, 3 states have (on average 12.666666666666666) internal successors, (38), 3 states have internal predecessors, (38), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-19 07:48:55,531 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-19 07:48:55,531 INFO L93 Difference]: Finished difference Result 1933 states and 2290 transitions. [2023-11-19 07:48:55,531 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1933 states and 2290 transitions. [2023-11-19 07:48:55,564 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 1892 [2023-11-19 07:48:55,577 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1933 states to 1933 states and 2290 transitions. [2023-11-19 07:48:55,578 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1933 [2023-11-19 07:48:55,582 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1933 [2023-11-19 07:48:55,582 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1933 states and 2290 transitions. [2023-11-19 07:48:55,584 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-19 07:48:55,584 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1933 states and 2290 transitions. [2023-11-19 07:48:55,587 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1933 states and 2290 transitions. [2023-11-19 07:48:55,618 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1933 to 1877. [2023-11-19 07:48:55,621 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1877 states, 1877 states have (on average 1.1838039424613744) internal successors, (2222), 1876 states have internal predecessors, (2222), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-19 07:48:55,628 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1877 states to 1877 states and 2222 transitions. [2023-11-19 07:48:55,629 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1877 states and 2222 transitions. [2023-11-19 07:48:55,629 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-19 07:48:55,631 INFO L428 stractBuchiCegarLoop]: Abstraction has 1877 states and 2222 transitions. [2023-11-19 07:48:55,631 INFO L335 stractBuchiCegarLoop]: ======== Iteration 15 ============ [2023-11-19 07:48:55,632 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1877 states and 2222 transitions. [2023-11-19 07:48:55,639 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 1836 [2023-11-19 07:48:55,639 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-19 07:48:55,639 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-19 07:48:55,643 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-19 07:48:55,643 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-19 07:48:55,643 INFO L748 eck$LassoCheckResult]: Stem: 24906#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(19, 2);call #Ultimate.allocInit(12, 3);~q_buf_0~0 := 0;~q_free~0 := 0;~q_read_ev~0 := 0;~q_write_ev~0 := 0;~q_req_up~0 := 0;~q_ev~0 := 0;~p_num_write~0 := 0;~p_last_write~0 := 0;~p_dw_st~0 := 0;~p_dw_pc~0 := 0;~p_dw_i~0 := 0;~c_num_read~0 := 0;~c_last_read~0 := 0;~c_dr_st~0 := 0;~c_dr_pc~0 := 0;~c_dr_i~0 := 0;~a_t~0 := 0; 24907#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~3#1;havoc main_~__retres1~3#1;assume { :begin_inline_init_model } true;~q_free~0 := 1;~q_write_ev~0 := 2;~q_read_ev~0 := ~q_write_ev~0;~p_num_write~0 := 0;~p_dw_pc~0 := 0;~p_dw_i~0 := 1;~c_num_read~0 := 0;~c_dr_pc~0 := 0;~c_dr_i~0 := 1; 24936#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret13#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~4#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~4#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 24881#L222 assume !(1 == ~q_req_up~0); 24872#L222-2 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 24873#L237 assume 1 == ~p_dw_i~0;~p_dw_st~0 := 0; 24916#L237-2 assume 1 == ~c_dr_i~0;~c_dr_st~0 := 0; 24941#L242-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 24938#L275 assume !(0 == ~q_read_ev~0); 24939#L275-2 assume !(0 == ~q_write_ev~0); 24921#L280-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;assume { :begin_inline_is_do_write_p_triggered } true;havoc is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;havoc is_do_write_p_triggered_~__retres1~0#1; 24922#L65 assume !(1 == ~p_dw_pc~0); 24930#L65-2 is_do_write_p_triggered_~__retres1~0#1 := 0; 24931#L76 is_do_write_p_triggered_#res#1 := is_do_write_p_triggered_~__retres1~0#1; 24902#is_do_write_p_triggered_returnLabel#1 activate_threads_#t~ret7#1 := is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;assume { :end_inline_is_do_write_p_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1; 24903#L315 assume !(0 != activate_threads_~tmp~1#1); 24878#L315-2 assume { :begin_inline_is_do_read_c_triggered } true;havoc is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;havoc is_do_read_c_triggered_~__retres1~1#1; 24879#L84 assume !(1 == ~c_dr_pc~0); 24897#L84-2 is_do_read_c_triggered_~__retres1~1#1 := 0; 24890#L95 is_do_read_c_triggered_#res#1 := is_do_read_c_triggered_~__retres1~1#1; 24891#is_do_read_c_triggered_returnLabel#1 activate_threads_#t~ret8#1 := is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;assume { :end_inline_is_do_read_c_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 24855#L323 assume !(0 != activate_threads_~tmp___0~1#1); 24856#L323-2 havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 24958#L293 assume !(1 == ~q_read_ev~0); 24849#L293-2 assume !(1 == ~q_write_ev~0); 24850#L298-1 assume { :end_inline_reset_delta_events } true; 24948#L419-2 assume !false; 25012#L420 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret9#1, eval_#t~nondet10#1, eval_#t~nondet11#1, eval_~tmp~2#1, eval_~tmp___0~2#1, eval_~tmp___1~0#1;havoc eval_~tmp~2#1;havoc eval_~tmp___0~2#1;havoc eval_~tmp___1~0#1; 25011#L364 assume !false; 25010#L340 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 25009#L255 assume 0 == ~p_dw_st~0;exists_runnable_thread_~__retres1~2#1 := 1; 25008#L267 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 25007#exists_runnable_thread_returnLabel#1 eval_#t~ret9#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp___1~0#1 := eval_#t~ret9#1;havoc eval_#t~ret9#1; 25006#L344 assume 0 != eval_~tmp___1~0#1; 25004#L344-1 assume 0 == ~p_dw_st~0;havoc eval_#t~nondet10#1;eval_~tmp~2#1 := eval_#t~nondet10#1;havoc eval_#t~nondet10#1; 25002#L353 assume 0 != eval_~tmp~2#1;~p_dw_st~0 := 1;assume { :begin_inline_do_write_p } true;havoc do_write_p_#t~nondet6#1; 25000#L128 assume 0 == ~p_dw_pc~0; 24998#L139-1 assume !false; 24995#L140 assume !(0 == ~q_free~0); 24996#L141 [2023-11-19 07:48:55,644 INFO L750 eck$LassoCheckResult]: Loop: 24996#L141 havoc do_write_p_#t~nondet6#1;~q_buf_0~0 := do_write_p_#t~nondet6#1;havoc do_write_p_#t~nondet6#1;~p_last_write~0 := ~q_buf_0~0;~p_num_write~0 := 1 + ~p_num_write~0;~q_free~0 := 0;~q_req_up~0 := 1; 26371#L139-1 assume !false; 25399#L140 assume 0 == ~q_free~0;~p_dw_st~0 := 2;~p_dw_pc~0 := 1; 25095#do_write_p_returnLabel#1 havoc do_write_p_#t~nondet6#1;assume { :end_inline_do_write_p } true; 25094#L349 assume 0 == ~c_dr_st~0;havoc eval_#t~nondet11#1;eval_~tmp___0~2#1 := eval_#t~nondet11#1;havoc eval_#t~nondet11#1; 24986#L368 assume 0 != eval_~tmp___0~2#1;~c_dr_st~0 := 1;assume { :begin_inline_do_read_c } true;havoc do_read_c_~a~0#1;havoc do_read_c_~a~0#1; 24988#L169 assume 0 == ~c_dr_pc~0; 24982#L198-1 assume !false; 24898#L181 assume !(1 == ~q_free~0); 24877#L182-1 do_read_c_~a~0#1 := ~q_buf_0~0;~c_last_read~0 := do_read_c_~a~0#1;~c_num_read~0 := 1 + ~c_num_read~0;~q_free~0 := 1;~q_req_up~0 := 1; 24857#L198 assume ~p_last_write~0 == ~c_last_read~0; 24858#L199 assume ~p_num_write~0 == ~c_num_read~0; 25303#L198-1 assume !false; 25299#L181 assume 1 == ~q_free~0;~c_dr_st~0 := 2;~c_dr_pc~0 := 1;~a_t~0 := do_read_c_~a~0#1; 25293#do_read_c_returnLabel#1 havoc do_read_c_~a~0#1;assume { :end_inline_do_read_c } true; 25291#L364 assume !false; 25289#L340 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 25287#L255 assume !(0 == ~p_dw_st~0); 25284#L259 assume !(0 == ~c_dr_st~0);exists_runnable_thread_~__retres1~2#1 := 0; 25282#L267 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 25280#exists_runnable_thread_returnLabel#1 eval_#t~ret9#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp___1~0#1 := eval_#t~ret9#1;havoc eval_#t~ret9#1; 25275#L344 assume !(0 != eval_~tmp___1~0#1); 25277#eval_returnLabel#1 havoc eval_#t~ret9#1, eval_#t~nondet10#1, eval_#t~nondet11#1, eval_~tmp~2#1, eval_~tmp___0~2#1, eval_~tmp___1~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 25395#L222-3 assume 1 == ~q_req_up~0;assume { :begin_inline_update_fifo_q } true; 25396#L35-3 assume !(0 == ~q_free~0); 26037#L35-5 assume 1 == ~q_free~0;~q_read_ev~0 := 0; 24943#L40-3 ~q_ev~0 := 0;~q_req_up~0 := 0; 24917#update_fifo_q_returnLabel#2 assume { :end_inline_update_fifo_q } true; 24918#L222-5 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 26104#L275-3 assume 0 == ~q_read_ev~0;~q_read_ev~0 := 1; 26101#L275-5 assume !(0 == ~q_write_ev~0); 26100#L280-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;assume { :begin_inline_is_do_write_p_triggered } true;havoc is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;havoc is_do_write_p_triggered_~__retres1~0#1; 26099#L65-3 assume 1 == ~p_dw_pc~0; 26096#L66-1 assume 1 == ~q_read_ev~0;is_do_write_p_triggered_~__retres1~0#1 := 1; 26097#L76-1 is_do_write_p_triggered_#res#1 := is_do_write_p_triggered_~__retres1~0#1; 26085#is_do_write_p_triggered_returnLabel#2 activate_threads_#t~ret7#1 := is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;assume { :end_inline_is_do_write_p_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1; 26086#L315-3 assume 0 != activate_threads_~tmp~1#1;~p_dw_st~0 := 0; 26213#L315-5 assume { :begin_inline_is_do_read_c_triggered } true;havoc is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;havoc is_do_read_c_triggered_~__retres1~1#1; 26214#L84-3 assume !(1 == ~c_dr_pc~0); 24942#L84-5 is_do_read_c_triggered_~__retres1~1#1 := 0; 24912#L95-1 is_do_read_c_triggered_#res#1 := is_do_read_c_triggered_~__retres1~1#1; 24913#is_do_read_c_triggered_returnLabel#2 activate_threads_#t~ret8#1 := is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;assume { :end_inline_is_do_read_c_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 24970#L323-3 assume 0 != activate_threads_~tmp___0~1#1;~c_dr_st~0 := 0; 24971#L323-5 havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 26419#L293-3 assume 1 == ~q_read_ev~0;~q_read_ev~0 := 2; 26414#L293-5 assume !(1 == ~q_write_ev~0); 26411#L298-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret12#1, stop_simulation_~tmp~3#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~3#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 26409#L255-1 assume 0 == ~p_dw_st~0;exists_runnable_thread_~__retres1~2#1 := 1; 26407#L267-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 26405#exists_runnable_thread_returnLabel#2 stop_simulation_#t~ret12#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~3#1 := stop_simulation_#t~ret12#1;havoc stop_simulation_#t~ret12#1; 26403#L394 assume 0 != stop_simulation_~tmp~3#1;stop_simulation_~__retres2~0#1 := 0; 26401#L401 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 26399#stop_simulation_returnLabel#1 start_simulation_#t~ret13#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret12#1, stop_simulation_~tmp~3#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp~4#1 := start_simulation_#t~ret13#1;havoc start_simulation_#t~ret13#1; 26397#L436 assume !(0 != start_simulation_~tmp~4#1); 26395#L419-2 assume !false; 26393#L420 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret9#1, eval_#t~nondet10#1, eval_#t~nondet11#1, eval_~tmp~2#1, eval_~tmp___0~2#1, eval_~tmp___1~0#1;havoc eval_~tmp~2#1;havoc eval_~tmp___0~2#1;havoc eval_~tmp___1~0#1; 26391#L364 assume !false; 26389#L340 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 26387#L255 assume 0 == ~p_dw_st~0;exists_runnable_thread_~__retres1~2#1 := 1; 26385#L267 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 26383#exists_runnable_thread_returnLabel#1 eval_#t~ret9#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp___1~0#1 := eval_#t~ret9#1;havoc eval_#t~ret9#1; 26381#L344 assume 0 != eval_~tmp___1~0#1; 26379#L344-1 assume 0 == ~p_dw_st~0;havoc eval_#t~nondet10#1;eval_~tmp~2#1 := eval_#t~nondet10#1;havoc eval_#t~nondet10#1; 26374#L353 assume 0 != eval_~tmp~2#1;~p_dw_st~0 := 1;assume { :begin_inline_do_write_p } true;havoc do_write_p_#t~nondet6#1; 26375#L128 assume !(0 == ~p_dw_pc~0); 26378#L131 assume 1 == ~p_dw_pc~0; 24996#L141 [2023-11-19 07:48:55,644 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-19 07:48:55,644 INFO L85 PathProgramCache]: Analyzing trace with hash 1156368236, now seen corresponding path program 1 times [2023-11-19 07:48:55,644 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-19 07:48:55,644 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1015332315] [2023-11-19 07:48:55,644 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-19 07:48:55,645 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-19 07:48:55,656 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-19 07:48:55,657 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-19 07:48:55,661 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-19 07:48:55,673 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-19 07:48:55,674 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-19 07:48:55,674 INFO L85 PathProgramCache]: Analyzing trace with hash -521763250, now seen corresponding path program 2 times [2023-11-19 07:48:55,674 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-19 07:48:55,674 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [719948762] [2023-11-19 07:48:55,674 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-19 07:48:55,675 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-19 07:48:55,687 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-19 07:48:55,720 INFO L134 CoverageAnalysis]: Checked inductivity of 8 backedges. 6 proven. 0 refuted. 0 times theorem prover too weak. 2 trivial. 0 not checked. [2023-11-19 07:48:55,720 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-19 07:48:55,721 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [719948762] [2023-11-19 07:48:55,721 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [719948762] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-19 07:48:55,721 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-19 07:48:55,721 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-19 07:48:55,721 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1360208667] [2023-11-19 07:48:55,721 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-19 07:48:55,722 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-19 07:48:55,722 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-19 07:48:55,722 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-19 07:48:55,722 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-19 07:48:55,722 INFO L87 Difference]: Start difference. First operand 1877 states and 2222 transitions. cyclomatic complexity: 347 Second operand has 3 states, 3 states have (on average 21.666666666666668) internal successors, (65), 3 states have internal predecessors, (65), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-19 07:48:55,742 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-19 07:48:55,742 INFO L93 Difference]: Finished difference Result 995 states and 1157 transitions. [2023-11-19 07:48:55,742 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 995 states and 1157 transitions. [2023-11-19 07:48:55,747 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 946 [2023-11-19 07:48:55,754 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 995 states to 995 states and 1157 transitions. [2023-11-19 07:48:55,754 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 995 [2023-11-19 07:48:55,755 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 995 [2023-11-19 07:48:55,756 INFO L73 IsDeterministic]: Start isDeterministic. Operand 995 states and 1157 transitions. [2023-11-19 07:48:55,757 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-19 07:48:55,757 INFO L218 hiAutomatonCegarLoop]: Abstraction has 995 states and 1157 transitions. [2023-11-19 07:48:55,758 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 995 states and 1157 transitions. [2023-11-19 07:48:55,777 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 995 to 844. [2023-11-19 07:48:55,779 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 844 states, 844 states have (on average 1.1753554502369667) internal successors, (992), 843 states have internal predecessors, (992), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-19 07:48:55,783 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 844 states to 844 states and 992 transitions. [2023-11-19 07:48:55,783 INFO L240 hiAutomatonCegarLoop]: Abstraction has 844 states and 992 transitions. [2023-11-19 07:48:55,783 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-19 07:48:55,784 INFO L428 stractBuchiCegarLoop]: Abstraction has 844 states and 992 transitions. [2023-11-19 07:48:55,785 INFO L335 stractBuchiCegarLoop]: ======== Iteration 16 ============ [2023-11-19 07:48:55,785 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 844 states and 992 transitions. [2023-11-19 07:48:55,788 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 795 [2023-11-19 07:48:55,788 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-19 07:48:55,788 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-19 07:48:55,789 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-19 07:48:55,789 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-19 07:48:55,789 INFO L748 eck$LassoCheckResult]: Stem: 27780#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(19, 2);call #Ultimate.allocInit(12, 3);~q_buf_0~0 := 0;~q_free~0 := 0;~q_read_ev~0 := 0;~q_write_ev~0 := 0;~q_req_up~0 := 0;~q_ev~0 := 0;~p_num_write~0 := 0;~p_last_write~0 := 0;~p_dw_st~0 := 0;~p_dw_pc~0 := 0;~p_dw_i~0 := 0;~c_num_read~0 := 0;~c_last_read~0 := 0;~c_dr_st~0 := 0;~c_dr_pc~0 := 0;~c_dr_i~0 := 0;~a_t~0 := 0; 27781#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~3#1;havoc main_~__retres1~3#1;assume { :begin_inline_init_model } true;~q_free~0 := 1;~q_write_ev~0 := 2;~q_read_ev~0 := ~q_write_ev~0;~p_num_write~0 := 0;~p_dw_pc~0 := 0;~p_dw_i~0 := 1;~c_num_read~0 := 0;~c_dr_pc~0 := 0;~c_dr_i~0 := 1; 27805#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret13#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~4#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~4#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 27760#L222 assume !(1 == ~q_req_up~0); 27748#L222-2 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 27749#L237 assume 1 == ~p_dw_i~0;~p_dw_st~0 := 0; 27790#L237-2 assume 1 == ~c_dr_i~0;~c_dr_st~0 := 0; 27814#L242-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 27811#L275 assume !(0 == ~q_read_ev~0); 27812#L275-2 assume !(0 == ~q_write_ev~0); 27793#L280-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;assume { :begin_inline_is_do_write_p_triggered } true;havoc is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;havoc is_do_write_p_triggered_~__retres1~0#1; 27794#L65 assume !(1 == ~p_dw_pc~0); 27802#L65-2 is_do_write_p_triggered_~__retres1~0#1 := 0; 27803#L76 is_do_write_p_triggered_#res#1 := is_do_write_p_triggered_~__retres1~0#1; 27777#is_do_write_p_triggered_returnLabel#1 activate_threads_#t~ret7#1 := is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;assume { :end_inline_is_do_write_p_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1; 27778#L315 assume !(0 != activate_threads_~tmp~1#1); 27756#L315-2 assume { :begin_inline_is_do_read_c_triggered } true;havoc is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;havoc is_do_read_c_triggered_~__retres1~1#1; 27757#L84 assume !(1 == ~c_dr_pc~0); 27773#L84-2 is_do_read_c_triggered_~__retres1~1#1 := 0; 27768#L95 is_do_read_c_triggered_#res#1 := is_do_read_c_triggered_~__retres1~1#1; 27769#is_do_read_c_triggered_returnLabel#1 activate_threads_#t~ret8#1 := is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;assume { :end_inline_is_do_read_c_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 27733#L323 assume !(0 != activate_threads_~tmp___0~1#1); 27734#L323-2 havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 27824#L293 assume !(1 == ~q_read_ev~0); 27727#L293-2 assume !(1 == ~q_write_ev~0); 27728#L298-1 assume { :end_inline_reset_delta_events } true; 27820#L419-2 assume !false; 27866#L420 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret9#1, eval_#t~nondet10#1, eval_#t~nondet11#1, eval_~tmp~2#1, eval_~tmp___0~2#1, eval_~tmp___1~0#1;havoc eval_~tmp~2#1;havoc eval_~tmp___0~2#1;havoc eval_~tmp___1~0#1; 27865#L364 assume !false; 27864#L340 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 27863#L255 assume 0 == ~p_dw_st~0;exists_runnable_thread_~__retres1~2#1 := 1; 27862#L267 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 27861#exists_runnable_thread_returnLabel#1 eval_#t~ret9#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp___1~0#1 := eval_#t~ret9#1;havoc eval_#t~ret9#1; 27860#L344 assume 0 != eval_~tmp___1~0#1; 27859#L344-1 assume 0 == ~p_dw_st~0;havoc eval_#t~nondet10#1;eval_~tmp~2#1 := eval_#t~nondet10#1;havoc eval_#t~nondet10#1; 27858#L353 assume 0 != eval_~tmp~2#1;~p_dw_st~0 := 1;assume { :begin_inline_do_write_p } true;havoc do_write_p_#t~nondet6#1; 27856#L128 assume 0 == ~p_dw_pc~0; 27850#L139-1 assume !false; 27851#L140 assume 0 == ~q_free~0;~p_dw_st~0 := 2;~p_dw_pc~0 := 1; 27857#do_write_p_returnLabel#1 havoc do_write_p_#t~nondet6#1;assume { :end_inline_do_write_p } true; 27840#L349 [2023-11-19 07:48:55,789 INFO L750 eck$LassoCheckResult]: Loop: 27840#L349 assume 0 == ~c_dr_st~0;havoc eval_#t~nondet11#1;eval_~tmp___0~2#1 := eval_#t~nondet11#1;havoc eval_#t~nondet11#1; 27841#L368 assume !(0 != eval_~tmp___0~2#1); 27873#L364 assume !false; 27874#L340 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 27869#L255 assume !(0 == ~p_dw_st~0); 27870#L259 assume 0 == ~c_dr_st~0;exists_runnable_thread_~__retres1~2#1 := 1; 27852#L267 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 27853#exists_runnable_thread_returnLabel#1 eval_#t~ret9#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp___1~0#1 := eval_#t~ret9#1;havoc eval_#t~ret9#1; 27845#L344 assume 0 != eval_~tmp___1~0#1; 27846#L344-1 assume !(0 == ~p_dw_st~0); 27840#L349 [2023-11-19 07:48:55,790 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-19 07:48:55,790 INFO L85 PathProgramCache]: Analyzing trace with hash 1487677052, now seen corresponding path program 1 times [2023-11-19 07:48:55,790 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-19 07:48:55,790 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1759528432] [2023-11-19 07:48:55,790 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-19 07:48:55,791 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-19 07:48:55,800 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-19 07:48:55,867 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-19 07:48:55,867 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-19 07:48:55,867 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1759528432] [2023-11-19 07:48:55,867 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1759528432] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-19 07:48:55,868 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-19 07:48:55,868 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2023-11-19 07:48:55,868 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1826854902] [2023-11-19 07:48:55,868 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-19 07:48:55,868 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-19 07:48:55,868 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-19 07:48:55,869 INFO L85 PathProgramCache]: Analyzing trace with hash -682996676, now seen corresponding path program 2 times [2023-11-19 07:48:55,869 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-19 07:48:55,869 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [928567638] [2023-11-19 07:48:55,869 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-19 07:48:55,869 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-19 07:48:55,872 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-19 07:48:55,872 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-19 07:48:55,874 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-19 07:48:55,876 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-19 07:48:55,934 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-19 07:48:55,934 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2023-11-19 07:48:55,934 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2023-11-19 07:48:55,935 INFO L87 Difference]: Start difference. First operand 844 states and 992 transitions. cyclomatic complexity: 151 Second operand has 5 states, 5 states have (on average 8.0) internal successors, (40), 4 states have internal predecessors, (40), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-19 07:48:55,991 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-19 07:48:55,991 INFO L93 Difference]: Finished difference Result 1152 states and 1316 transitions. [2023-11-19 07:48:55,991 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1152 states and 1316 transitions. [2023-11-19 07:48:55,998 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 1105 [2023-11-19 07:48:56,005 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1152 states to 1152 states and 1316 transitions. [2023-11-19 07:48:56,006 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1152 [2023-11-19 07:48:56,007 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1152 [2023-11-19 07:48:56,007 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1152 states and 1316 transitions. [2023-11-19 07:48:56,009 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-19 07:48:56,009 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1152 states and 1316 transitions. [2023-11-19 07:48:56,010 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1152 states and 1316 transitions. [2023-11-19 07:48:56,023 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1152 to 777. [2023-11-19 07:48:56,025 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 777 states, 777 states have (on average 1.16988416988417) internal successors, (909), 776 states have internal predecessors, (909), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-19 07:48:56,028 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 777 states to 777 states and 909 transitions. [2023-11-19 07:48:56,028 INFO L240 hiAutomatonCegarLoop]: Abstraction has 777 states and 909 transitions. [2023-11-19 07:48:56,028 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2023-11-19 07:48:56,029 INFO L428 stractBuchiCegarLoop]: Abstraction has 777 states and 909 transitions. [2023-11-19 07:48:56,029 INFO L335 stractBuchiCegarLoop]: ======== Iteration 17 ============ [2023-11-19 07:48:56,029 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 777 states and 909 transitions. [2023-11-19 07:48:56,032 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 730 [2023-11-19 07:48:56,032 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-19 07:48:56,032 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-19 07:48:56,033 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-19 07:48:56,033 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-19 07:48:56,033 INFO L748 eck$LassoCheckResult]: Stem: 29790#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(19, 2);call #Ultimate.allocInit(12, 3);~q_buf_0~0 := 0;~q_free~0 := 0;~q_read_ev~0 := 0;~q_write_ev~0 := 0;~q_req_up~0 := 0;~q_ev~0 := 0;~p_num_write~0 := 0;~p_last_write~0 := 0;~p_dw_st~0 := 0;~p_dw_pc~0 := 0;~p_dw_i~0 := 0;~c_num_read~0 := 0;~c_last_read~0 := 0;~c_dr_st~0 := 0;~c_dr_pc~0 := 0;~c_dr_i~0 := 0;~a_t~0 := 0; 29791#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~3#1;havoc main_~__retres1~3#1;assume { :begin_inline_init_model } true;~q_free~0 := 1;~q_write_ev~0 := 2;~q_read_ev~0 := ~q_write_ev~0;~p_num_write~0 := 0;~p_dw_pc~0 := 0;~p_dw_i~0 := 1;~c_num_read~0 := 0;~c_dr_pc~0 := 0;~c_dr_i~0 := 1; 29815#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret13#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~4#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~4#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 29765#L222 assume !(1 == ~q_req_up~0); 29756#L222-2 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 29757#L237 assume 1 == ~p_dw_i~0;~p_dw_st~0 := 0; 29798#L237-2 assume 1 == ~c_dr_i~0;~c_dr_st~0 := 0; 29821#L242-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 29817#L275 assume !(0 == ~q_read_ev~0); 29818#L275-2 assume !(0 == ~q_write_ev~0); 29803#L280-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;assume { :begin_inline_is_do_write_p_triggered } true;havoc is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;havoc is_do_write_p_triggered_~__retres1~0#1; 29804#L65 assume !(1 == ~p_dw_pc~0); 29811#L65-2 is_do_write_p_triggered_~__retres1~0#1 := 0; 29812#L76 is_do_write_p_triggered_#res#1 := is_do_write_p_triggered_~__retres1~0#1; 29786#is_do_write_p_triggered_returnLabel#1 activate_threads_#t~ret7#1 := is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;assume { :end_inline_is_do_write_p_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1; 29787#L315 assume !(0 != activate_threads_~tmp~1#1); 29762#L315-2 assume { :begin_inline_is_do_read_c_triggered } true;havoc is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;havoc is_do_read_c_triggered_~__retres1~1#1; 29763#L84 assume !(1 == ~c_dr_pc~0); 29779#L84-2 is_do_read_c_triggered_~__retres1~1#1 := 0; 29773#L95 is_do_read_c_triggered_#res#1 := is_do_read_c_triggered_~__retres1~1#1; 29774#is_do_read_c_triggered_returnLabel#1 activate_threads_#t~ret8#1 := is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;assume { :end_inline_is_do_read_c_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 29739#L323 assume !(0 != activate_threads_~tmp___0~1#1); 29740#L323-2 havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 29832#L293 assume !(1 == ~q_read_ev~0); 29733#L293-2 assume !(1 == ~q_write_ev~0); 29734#L298-1 assume { :end_inline_reset_delta_events } true; 29827#L419-2 assume !false; 29865#L420 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret9#1, eval_#t~nondet10#1, eval_#t~nondet11#1, eval_~tmp~2#1, eval_~tmp___0~2#1, eval_~tmp___1~0#1;havoc eval_~tmp~2#1;havoc eval_~tmp___0~2#1;havoc eval_~tmp___1~0#1; 29864#L364 assume !false; 29863#L340 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 29862#L255 assume 0 == ~p_dw_st~0;exists_runnable_thread_~__retres1~2#1 := 1; 29861#L267 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 29860#exists_runnable_thread_returnLabel#1 eval_#t~ret9#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp___1~0#1 := eval_#t~ret9#1;havoc eval_#t~ret9#1; 29859#L344 assume 0 != eval_~tmp___1~0#1; 29858#L344-1 assume 0 == ~p_dw_st~0;havoc eval_#t~nondet10#1;eval_~tmp~2#1 := eval_#t~nondet10#1;havoc eval_#t~nondet10#1; 29857#L353 assume 0 != eval_~tmp~2#1;~p_dw_st~0 := 1;assume { :begin_inline_do_write_p } true;havoc do_write_p_#t~nondet6#1; 29856#L128 assume 0 == ~p_dw_pc~0; 29854#L139-1 assume !false; 29852#L140 assume !(0 == ~q_free~0); 29850#L141 havoc do_write_p_#t~nondet6#1;~q_buf_0~0 := do_write_p_#t~nondet6#1;havoc do_write_p_#t~nondet6#1;~p_last_write~0 := ~q_buf_0~0;~p_num_write~0 := 1 + ~p_num_write~0;~q_free~0 := 0;~q_req_up~0 := 1; 29848#L139-1 assume !false; 29846#L140 assume 0 == ~q_free~0;~p_dw_st~0 := 2;~p_dw_pc~0 := 1; 29844#do_write_p_returnLabel#1 havoc do_write_p_#t~nondet6#1;assume { :end_inline_do_write_p } true; 29842#L349 [2023-11-19 07:48:56,033 INFO L750 eck$LassoCheckResult]: Loop: 29842#L349 assume 0 == ~c_dr_st~0;havoc eval_#t~nondet11#1;eval_~tmp___0~2#1 := eval_#t~nondet11#1;havoc eval_#t~nondet11#1; 29840#L368 assume !(0 != eval_~tmp___0~2#1); 29841#L364 assume !false; 29855#L340 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 29853#L255 assume !(0 == ~p_dw_st~0); 29851#L259 assume 0 == ~c_dr_st~0;exists_runnable_thread_~__retres1~2#1 := 1; 29849#L267 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 29847#exists_runnable_thread_returnLabel#1 eval_#t~ret9#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp___1~0#1 := eval_#t~ret9#1;havoc eval_#t~ret9#1; 29845#L344 assume 0 != eval_~tmp___1~0#1; 29843#L344-1 assume !(0 == ~p_dw_st~0); 29842#L349 [2023-11-19 07:48:56,034 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-19 07:48:56,034 INFO L85 PathProgramCache]: Analyzing trace with hash -377667827, now seen corresponding path program 1 times [2023-11-19 07:48:56,034 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-19 07:48:56,034 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1327697736] [2023-11-19 07:48:56,034 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-19 07:48:56,035 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-19 07:48:56,043 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-19 07:48:56,043 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-19 07:48:56,049 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-19 07:48:56,055 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-19 07:48:56,056 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-19 07:48:56,056 INFO L85 PathProgramCache]: Analyzing trace with hash -682996676, now seen corresponding path program 3 times [2023-11-19 07:48:56,057 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-19 07:48:56,057 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1445745297] [2023-11-19 07:48:56,057 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-19 07:48:56,057 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-19 07:48:56,060 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-19 07:48:56,060 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-19 07:48:56,062 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-19 07:48:56,064 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-19 07:48:56,065 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-19 07:48:56,065 INFO L85 PathProgramCache]: Analyzing trace with hash 188558408, now seen corresponding path program 1 times [2023-11-19 07:48:56,065 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-19 07:48:56,065 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1053252282] [2023-11-19 07:48:56,065 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-19 07:48:56,066 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-19 07:48:56,075 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-19 07:48:56,075 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-19 07:48:56,081 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-19 07:48:56,088 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-19 07:48:57,212 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-19 07:48:57,213 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-19 07:48:57,228 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-19 07:48:57,335 INFO L201 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer CFG 19.11 07:48:57 BoogieIcfgContainer [2023-11-19 07:48:57,335 INFO L131 PluginConnector]: ------------------------ END BuchiAutomizer---------------------------- [2023-11-19 07:48:57,336 INFO L112 PluginConnector]: ------------------------Witness Printer---------------------------- [2023-11-19 07:48:57,336 INFO L270 PluginConnector]: Initializing Witness Printer... [2023-11-19 07:48:57,336 INFO L274 PluginConnector]: Witness Printer initialized [2023-11-19 07:48:57,337 INFO L184 PluginConnector]: Executing the observer RCFGCatcher from plugin Witness Printer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 19.11 07:48:51" (3/4) ... [2023-11-19 07:48:57,339 INFO L134 WitnessPrinter]: Generating witness for non-termination counterexample [2023-11-19 07:48:57,432 INFO L149 WitnessManager]: Wrote witness to /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4334fb4b-5faa-4749-a3d0-a7ded1eaf4de/bin/uautomizer-verify-uCwYo4JHxu/witness.graphml [2023-11-19 07:48:57,432 INFO L131 PluginConnector]: ------------------------ END Witness Printer---------------------------- [2023-11-19 07:48:57,433 INFO L158 Benchmark]: Toolchain (without parser) took 6603.81ms. Allocated memory was 144.7MB in the beginning and 209.7MB in the end (delta: 65.0MB). Free memory was 103.2MB in the beginning and 139.7MB in the end (delta: -36.5MB). Peak memory consumption was 30.2MB. Max. memory is 16.1GB. [2023-11-19 07:48:57,433 INFO L158 Benchmark]: CDTParser took 0.32ms. Allocated memory is still 115.3MB. Free memory is still 65.0MB. There was no memory consumed. Max. memory is 16.1GB. [2023-11-19 07:48:57,433 INFO L158 Benchmark]: CACSL2BoogieTranslator took 332.43ms. Allocated memory is still 144.7MB. Free memory was 102.7MB in the beginning and 89.6MB in the end (delta: 13.1MB). Peak memory consumption was 14.7MB. Max. memory is 16.1GB. [2023-11-19 07:48:57,434 INFO L158 Benchmark]: Boogie Procedure Inliner took 56.01ms. Allocated memory is still 144.7MB. Free memory was 89.6MB in the beginning and 87.5MB in the end (delta: 2.1MB). Peak memory consumption was 2.1MB. Max. memory is 16.1GB. [2023-11-19 07:48:57,434 INFO L158 Benchmark]: Boogie Preprocessor took 61.53ms. Allocated memory is still 144.7MB. Free memory was 87.5MB in the beginning and 85.4MB in the end (delta: 2.1MB). Peak memory consumption was 2.1MB. Max. memory is 16.1GB. [2023-11-19 07:48:57,434 INFO L158 Benchmark]: RCFGBuilder took 547.30ms. Allocated memory is still 144.7MB. Free memory was 85.4MB in the beginning and 67.6MB in the end (delta: 17.8MB). Peak memory consumption was 16.8MB. Max. memory is 16.1GB. [2023-11-19 07:48:57,435 INFO L158 Benchmark]: BuchiAutomizer took 5504.60ms. Allocated memory was 144.7MB in the beginning and 209.7MB in the end (delta: 65.0MB). Free memory was 67.6MB in the beginning and 144.9MB in the end (delta: -77.3MB). There was no memory consumed. Max. memory is 16.1GB. [2023-11-19 07:48:57,435 INFO L158 Benchmark]: Witness Printer took 96.03ms. Allocated memory is still 209.7MB. Free memory was 144.9MB in the beginning and 139.7MB in the end (delta: 5.2MB). Peak memory consumption was 4.2MB. Max. memory is 16.1GB. [2023-11-19 07:48:57,437 INFO L338 ainManager$Toolchain]: ####################### End [Toolchain 1] ####################### --- Results --- * Results from de.uni_freiburg.informatik.ultimate.core: - StatisticsResult: Toolchain Benchmarks Benchmark results are: * CDTParser took 0.32ms. Allocated memory is still 115.3MB. Free memory is still 65.0MB. There was no memory consumed. Max. memory is 16.1GB. * CACSL2BoogieTranslator took 332.43ms. Allocated memory is still 144.7MB. Free memory was 102.7MB in the beginning and 89.6MB in the end (delta: 13.1MB). Peak memory consumption was 14.7MB. Max. memory is 16.1GB. * Boogie Procedure Inliner took 56.01ms. Allocated memory is still 144.7MB. Free memory was 89.6MB in the beginning and 87.5MB in the end (delta: 2.1MB). Peak memory consumption was 2.1MB. Max. memory is 16.1GB. * Boogie Preprocessor took 61.53ms. Allocated memory is still 144.7MB. Free memory was 87.5MB in the beginning and 85.4MB in the end (delta: 2.1MB). Peak memory consumption was 2.1MB. Max. memory is 16.1GB. * RCFGBuilder took 547.30ms. Allocated memory is still 144.7MB. Free memory was 85.4MB in the beginning and 67.6MB in the end (delta: 17.8MB). Peak memory consumption was 16.8MB. Max. memory is 16.1GB. * BuchiAutomizer took 5504.60ms. Allocated memory was 144.7MB in the beginning and 209.7MB in the end (delta: 65.0MB). Free memory was 67.6MB in the beginning and 144.9MB in the end (delta: -77.3MB). There was no memory consumed. Max. memory is 16.1GB. * Witness Printer took 96.03ms. Allocated memory is still 209.7MB. Free memory was 144.9MB in the beginning and 139.7MB in the end (delta: 5.2MB). Peak memory consumption was 4.2MB. Max. memory is 16.1GB. * Results from de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction: - StatisticsResult: Constructed decomposition of program Your program was decomposed into 16 terminating modules (16 trivial, 0 deterministic, 0 nondeterministic) and one nonterminating remainder module.16 modules have a trivial ranking function, the largest among these consists of 5 locations. The remainder module has 777 locations. - StatisticsResult: Timing statistics BüchiAutomizer plugin needed 5.3s and 17 iterations. TraceHistogramMax:2. Analysis of lassos took 3.3s. Construction of modules took 0.3s. Büchi inclusion checks took 1.3s. Highest rank in rank-based complementation 0. Minimization of det autom 16. Minimization of nondet autom 0. Automata minimization 0.5s AutomataMinimizationTime, 16 MinimizatonAttempts, 2377 StatesRemovedByMinimization, 10 NontrivialMinimizations. Non-live state removal took 0.3s Buchi closure took 0.0s. Biggest automaton had -1 states and ocurred in iteration -1. Nontrivial modules had stage [0, 0, 0, 0, 0]. InterpolantCoveringCapabilityFinite: 0/0 InterpolantCoveringCapabilityBuchi: 0/0 HoareTripleCheckerStatistics: 0 mSolverCounterUnknown, 2259 SdHoareTripleChecker+Valid, 0.5s IncrementalHoareTripleChecker+Time, 0 mSdLazyCounter, 2259 mSDsluCounter, 4703 SdHoareTripleChecker+Invalid, 0.4s Time, 0 mProtectedAction, 0 SdHoareTripleChecker+Unchecked, 0 IncrementalHoareTripleChecker+Unchecked, 2473 mSDsCounter, 95 IncrementalHoareTripleChecker+Valid, 0 mProtectedPredicate, 340 IncrementalHoareTripleChecker+Invalid, 435 SdHoareTripleChecker+Unknown, 0 mSolverCounterNotChecked, 95 mSolverCounterUnsat, 2230 mSDtfsCounter, 340 mSolverCounterSat, 0.0s SdHoareTripleChecker+Time, 0 IncrementalHoareTripleChecker+Unknown LassoAnalysisResults: nont1 unkn0 SFLI5 SFLT0 conc0 concLT0 SILN2 SILU0 SILI9 SILT0 lasso0 LassoPreprocessingBenchmarks: LassoTerminationAnalysisBenchmarks: not availableLassoTerminationAnalysisBenchmarks: LassoNonterminationAnalysisSatFixpoint: 0 LassoNonterminationAnalysisSatUnbounded: 0 LassoNonterminationAnalysisUnsat: 0 LassoNonterminationAnalysisUnknown: 0 LassoNonterminationAnalysisTime: 0.0s InitialAbstractionConstructionTime: 0.0s - TerminationAnalysisResult: Nontermination possible Buchi Automizer proved that your program is nonterminating for some inputs - LassoShapedNonTerminationArgument [Line: 364]: Nontermination argument in form of an infinite program execution. Nontermination argument in form of an infinite program execution. Stem: [L25] int q_buf_0 ; [L26] int q_free ; [L27] int q_read_ev ; [L28] int q_write_ev ; [L29] int q_req_up ; [L30] int q_ev ; [L51] int p_num_write ; [L52] int p_last_write ; [L53] int p_dw_st ; [L54] int p_dw_pc ; [L55] int p_dw_i ; [L56] int c_num_read ; [L57] int c_last_read ; [L58] int c_dr_st ; [L59] int c_dr_pc ; [L60] int c_dr_i ; [L164] static int a_t ; VAL [a_t=0, c_dr_i=0, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, p_dw_i=0, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=0, q_read_ev=0, q_req_up=0, q_write_ev=0] [L466] int __retres1 ; [L470] CALL init_model() [L452] q_free = 1 [L453] q_write_ev = 2 [L454] q_read_ev = q_write_ev [L455] p_num_write = 0 [L456] p_dw_pc = 0 [L457] p_dw_i = 1 [L458] c_num_read = 0 [L459] c_dr_pc = 0 [L460] c_dr_i = 1 VAL [a_t=0, c_dr_i=1, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, p_dw_i=1, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=1, q_read_ev=2, q_req_up=0, q_write_ev=2] [L470] RET init_model() [L471] CALL start_simulation() [L406] int kernel_st ; [L407] int tmp ; [L411] kernel_st = 0 [L412] CALL update_channels() [L222] COND FALSE !((int )q_req_up == 1) VAL [a_t=0, c_dr_i=1, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, p_dw_i=1, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=1, q_read_ev=2, q_req_up=0, q_write_ev=2] [L412] RET update_channels() [L413] CALL init_threads() [L237] COND TRUE (int )p_dw_i == 1 [L238] p_dw_st = 0 VAL [a_t=0, c_dr_i=1, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, p_dw_i=1, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=1, q_read_ev=2, q_req_up=0, q_write_ev=2] [L242] COND TRUE (int )c_dr_i == 1 [L243] c_dr_st = 0 VAL [a_t=0, c_dr_i=1, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, p_dw_i=1, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=1, q_read_ev=2, q_req_up=0, q_write_ev=2] [L413] RET init_threads() [L414] CALL fire_delta_events() [L275] COND FALSE !((int )q_read_ev == 0) VAL [a_t=0, c_dr_i=1, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, p_dw_i=1, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=1, q_read_ev=2, q_req_up=0, q_write_ev=2] [L280] COND FALSE !((int )q_write_ev == 0) VAL [a_t=0, c_dr_i=1, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, p_dw_i=1, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=1, q_read_ev=2, q_req_up=0, q_write_ev=2] [L414] RET fire_delta_events() [L415] CALL activate_threads() [L308] int tmp ; [L309] int tmp___0 ; [L313] CALL, EXPR is_do_write_p_triggered() [L62] int __retres1 ; VAL [a_t=0, c_dr_i=1, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, p_dw_i=1, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=1, q_read_ev=2, q_req_up=0, q_write_ev=2] [L65] COND FALSE !((int )p_dw_pc == 1) VAL [a_t=0, c_dr_i=1, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, p_dw_i=1, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=1, q_read_ev=2, q_req_up=0, q_write_ev=2] [L75] __retres1 = 0 VAL [__retres1=0, a_t=0, c_dr_i=1, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, p_dw_i=1, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=1, q_read_ev=2, q_req_up=0, q_write_ev=2] [L77] return (__retres1); VAL [\result=0, __retres1=0, a_t=0, c_dr_i=1, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, p_dw_i=1, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=1, q_read_ev=2, q_req_up=0, q_write_ev=2] [L313] RET, EXPR is_do_write_p_triggered() [L313] tmp = is_do_write_p_triggered() [L315] COND FALSE !(\read(tmp)) VAL [a_t=0, c_dr_i=1, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, p_dw_i=1, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=1, q_read_ev=2, q_req_up=0, q_write_ev=2, tmp=0] [L321] CALL, EXPR is_do_read_c_triggered() [L81] int __retres1 ; VAL [a_t=0, c_dr_i=1, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, p_dw_i=1, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=1, q_read_ev=2, q_req_up=0, q_write_ev=2] [L84] COND FALSE !((int )c_dr_pc == 1) VAL [a_t=0, c_dr_i=1, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, p_dw_i=1, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=1, q_read_ev=2, q_req_up=0, q_write_ev=2] [L94] __retres1 = 0 VAL [__retres1=0, a_t=0, c_dr_i=1, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, p_dw_i=1, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=1, q_read_ev=2, q_req_up=0, q_write_ev=2] [L96] return (__retres1); VAL [\result=0, __retres1=0, a_t=0, c_dr_i=1, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, p_dw_i=1, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=1, q_read_ev=2, q_req_up=0, q_write_ev=2] [L321] RET, EXPR is_do_read_c_triggered() [L321] tmp___0 = is_do_read_c_triggered() [L323] COND FALSE !(\read(tmp___0)) VAL [a_t=0, c_dr_i=1, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, p_dw_i=1, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=1, q_read_ev=2, q_req_up=0, q_write_ev=2, tmp=0, tmp___0=0] [L415] RET activate_threads() [L416] CALL reset_delta_events() [L293] COND FALSE !((int )q_read_ev == 1) VAL [a_t=0, c_dr_i=1, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, p_dw_i=1, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=1, q_read_ev=2, q_req_up=0, q_write_ev=2] [L298] COND FALSE !((int )q_write_ev == 1) VAL [a_t=0, c_dr_i=1, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, p_dw_i=1, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=1, q_read_ev=2, q_req_up=0, q_write_ev=2] [L416] RET reset_delta_events() [L419] COND TRUE 1 VAL [a_t=0, c_dr_i=1, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, kernel_st=0, p_dw_i=1, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=1, q_read_ev=2, q_req_up=0, q_write_ev=2] [L422] kernel_st = 1 [L423] CALL eval() [L333] int tmp ; [L334] int tmp___0 ; [L335] int tmp___1 ; VAL [a_t=0, c_dr_i=1, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, p_dw_i=1, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=1, q_read_ev=2, q_req_up=0, q_write_ev=2] [L339] COND TRUE 1 VAL [a_t=0, c_dr_i=1, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, p_dw_i=1, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=1, q_read_ev=2, q_req_up=0, q_write_ev=2] [L342] CALL, EXPR exists_runnable_thread() [L252] int __retres1 ; VAL [a_t=0, c_dr_i=1, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, p_dw_i=1, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=1, q_read_ev=2, q_req_up=0, q_write_ev=2] [L255] COND TRUE (int )p_dw_st == 0 [L256] __retres1 = 1 VAL [__retres1=1, a_t=0, c_dr_i=1, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, p_dw_i=1, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=1, q_read_ev=2, q_req_up=0, q_write_ev=2] [L268] return (__retres1); VAL [\result=1, __retres1=1, a_t=0, c_dr_i=1, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, p_dw_i=1, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=1, q_read_ev=2, q_req_up=0, q_write_ev=2] [L342] RET, EXPR exists_runnable_thread() [L342] tmp___1 = exists_runnable_thread() [L344] COND TRUE \read(tmp___1) VAL [a_t=0, c_dr_i=1, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, p_dw_i=1, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=1, q_read_ev=2, q_req_up=0, q_write_ev=2, tmp___1=1] [L349] COND TRUE (int )p_dw_st == 0 [L351] tmp = __VERIFIER_nondet_int() [L353] COND TRUE \read(tmp) [L355] p_dw_st = 1 [L356] CALL do_write_p() [L128] COND TRUE (int )p_dw_pc == 0 VAL [a_t=0, c_dr_i=1, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, p_dw_i=1, p_dw_pc=0, p_dw_st=1, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=1, q_read_ev=2, q_req_up=0, q_write_ev=2] [L139] COND TRUE 1 VAL [a_t=0, c_dr_i=1, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, p_dw_i=1, p_dw_pc=0, p_dw_st=1, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=1, q_read_ev=2, q_req_up=0, q_write_ev=2] [L141] COND FALSE !((int )q_free == 0) VAL [a_t=0, c_dr_i=1, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, p_dw_i=1, p_dw_pc=0, p_dw_st=1, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=1, q_read_ev=2, q_req_up=0, q_write_ev=2] [L151] q_buf_0 = __VERIFIER_nondet_int() [L152] p_last_write = q_buf_0 [L153] p_num_write += 1 [L154] q_free = 0 [L155] q_req_up = 1 VAL [a_t=0, c_dr_i=1, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, p_dw_i=1, p_dw_pc=0, p_dw_st=1, p_last_write=5, p_num_write=1, q_buf_0=5, q_ev=0, q_free=0, q_read_ev=2, q_req_up=1, q_write_ev=2] [L139] COND TRUE 1 VAL [a_t=0, c_dr_i=1, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, p_dw_i=1, p_dw_pc=0, p_dw_st=1, p_last_write=5, p_num_write=1, q_buf_0=5, q_ev=0, q_free=0, q_read_ev=2, q_req_up=1, q_write_ev=2] [L141] COND TRUE (int )q_free == 0 [L142] p_dw_st = 2 [L143] p_dw_pc = 1 VAL [a_t=0, c_dr_i=1, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, p_dw_i=1, p_dw_pc=1, p_dw_st=2, p_last_write=5, p_num_write=1, q_buf_0=5, q_ev=0, q_free=0, q_read_ev=2, q_req_up=1, q_write_ev=2] [L356] RET do_write_p() Loop: [L364] COND TRUE (int )c_dr_st == 0 [L366] tmp___0 = __VERIFIER_nondet_int() [L368] COND FALSE !(\read(tmp___0)) [L339] COND TRUE 1 [L342] CALL, EXPR exists_runnable_thread() [L252] int __retres1 ; [L255] COND FALSE !((int )p_dw_st == 0) [L259] COND TRUE (int )c_dr_st == 0 [L260] __retres1 = 1 [L268] return (__retres1); [L342] RET, EXPR exists_runnable_thread() [L342] tmp___1 = exists_runnable_thread() [L344] COND TRUE \read(tmp___1) [L349] COND FALSE !((int )p_dw_st == 0) End of lasso representation. - StatisticsResult: NonterminationArgumentStatistics Fixpoint - NonterminatingLassoResult [Line: 364]: Nonterminating execution Found a nonterminating execution for the following lasso shaped sequence of statements. Stem: [L25] int q_buf_0 ; [L26] int q_free ; [L27] int q_read_ev ; [L28] int q_write_ev ; [L29] int q_req_up ; [L30] int q_ev ; [L51] int p_num_write ; [L52] int p_last_write ; [L53] int p_dw_st ; [L54] int p_dw_pc ; [L55] int p_dw_i ; [L56] int c_num_read ; [L57] int c_last_read ; [L58] int c_dr_st ; [L59] int c_dr_pc ; [L60] int c_dr_i ; [L164] static int a_t ; VAL [a_t=0, c_dr_i=0, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, p_dw_i=0, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=0, q_read_ev=0, q_req_up=0, q_write_ev=0] [L466] int __retres1 ; [L470] CALL init_model() [L452] q_free = 1 [L453] q_write_ev = 2 [L454] q_read_ev = q_write_ev [L455] p_num_write = 0 [L456] p_dw_pc = 0 [L457] p_dw_i = 1 [L458] c_num_read = 0 [L459] c_dr_pc = 0 [L460] c_dr_i = 1 VAL [a_t=0, c_dr_i=1, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, p_dw_i=1, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=1, q_read_ev=2, q_req_up=0, q_write_ev=2] [L470] RET init_model() [L471] CALL start_simulation() [L406] int kernel_st ; [L407] int tmp ; [L411] kernel_st = 0 [L412] CALL update_channels() [L222] COND FALSE !((int )q_req_up == 1) VAL [a_t=0, c_dr_i=1, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, p_dw_i=1, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=1, q_read_ev=2, q_req_up=0, q_write_ev=2] [L412] RET update_channels() [L413] CALL init_threads() [L237] COND TRUE (int )p_dw_i == 1 [L238] p_dw_st = 0 VAL [a_t=0, c_dr_i=1, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, p_dw_i=1, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=1, q_read_ev=2, q_req_up=0, q_write_ev=2] [L242] COND TRUE (int )c_dr_i == 1 [L243] c_dr_st = 0 VAL [a_t=0, c_dr_i=1, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, p_dw_i=1, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=1, q_read_ev=2, q_req_up=0, q_write_ev=2] [L413] RET init_threads() [L414] CALL fire_delta_events() [L275] COND FALSE !((int )q_read_ev == 0) VAL [a_t=0, c_dr_i=1, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, p_dw_i=1, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=1, q_read_ev=2, q_req_up=0, q_write_ev=2] [L280] COND FALSE !((int )q_write_ev == 0) VAL [a_t=0, c_dr_i=1, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, p_dw_i=1, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=1, q_read_ev=2, q_req_up=0, q_write_ev=2] [L414] RET fire_delta_events() [L415] CALL activate_threads() [L308] int tmp ; [L309] int tmp___0 ; [L313] CALL, EXPR is_do_write_p_triggered() [L62] int __retres1 ; VAL [a_t=0, c_dr_i=1, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, p_dw_i=1, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=1, q_read_ev=2, q_req_up=0, q_write_ev=2] [L65] COND FALSE !((int )p_dw_pc == 1) VAL [a_t=0, c_dr_i=1, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, p_dw_i=1, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=1, q_read_ev=2, q_req_up=0, q_write_ev=2] [L75] __retres1 = 0 VAL [__retres1=0, a_t=0, c_dr_i=1, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, p_dw_i=1, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=1, q_read_ev=2, q_req_up=0, q_write_ev=2] [L77] return (__retres1); VAL [\result=0, __retres1=0, a_t=0, c_dr_i=1, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, p_dw_i=1, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=1, q_read_ev=2, q_req_up=0, q_write_ev=2] [L313] RET, EXPR is_do_write_p_triggered() [L313] tmp = is_do_write_p_triggered() [L315] COND FALSE !(\read(tmp)) VAL [a_t=0, c_dr_i=1, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, p_dw_i=1, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=1, q_read_ev=2, q_req_up=0, q_write_ev=2, tmp=0] [L321] CALL, EXPR is_do_read_c_triggered() [L81] int __retres1 ; VAL [a_t=0, c_dr_i=1, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, p_dw_i=1, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=1, q_read_ev=2, q_req_up=0, q_write_ev=2] [L84] COND FALSE !((int )c_dr_pc == 1) VAL [a_t=0, c_dr_i=1, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, p_dw_i=1, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=1, q_read_ev=2, q_req_up=0, q_write_ev=2] [L94] __retres1 = 0 VAL [__retres1=0, a_t=0, c_dr_i=1, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, p_dw_i=1, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=1, q_read_ev=2, q_req_up=0, q_write_ev=2] [L96] return (__retres1); VAL [\result=0, __retres1=0, a_t=0, c_dr_i=1, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, p_dw_i=1, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=1, q_read_ev=2, q_req_up=0, q_write_ev=2] [L321] RET, EXPR is_do_read_c_triggered() [L321] tmp___0 = is_do_read_c_triggered() [L323] COND FALSE !(\read(tmp___0)) VAL [a_t=0, c_dr_i=1, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, p_dw_i=1, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=1, q_read_ev=2, q_req_up=0, q_write_ev=2, tmp=0, tmp___0=0] [L415] RET activate_threads() [L416] CALL reset_delta_events() [L293] COND FALSE !((int )q_read_ev == 1) VAL [a_t=0, c_dr_i=1, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, p_dw_i=1, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=1, q_read_ev=2, q_req_up=0, q_write_ev=2] [L298] COND FALSE !((int )q_write_ev == 1) VAL [a_t=0, c_dr_i=1, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, p_dw_i=1, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=1, q_read_ev=2, q_req_up=0, q_write_ev=2] [L416] RET reset_delta_events() [L419] COND TRUE 1 VAL [a_t=0, c_dr_i=1, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, kernel_st=0, p_dw_i=1, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=1, q_read_ev=2, q_req_up=0, q_write_ev=2] [L422] kernel_st = 1 [L423] CALL eval() [L333] int tmp ; [L334] int tmp___0 ; [L335] int tmp___1 ; VAL [a_t=0, c_dr_i=1, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, p_dw_i=1, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=1, q_read_ev=2, q_req_up=0, q_write_ev=2] [L339] COND TRUE 1 VAL [a_t=0, c_dr_i=1, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, p_dw_i=1, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=1, q_read_ev=2, q_req_up=0, q_write_ev=2] [L342] CALL, EXPR exists_runnable_thread() [L252] int __retres1 ; VAL [a_t=0, c_dr_i=1, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, p_dw_i=1, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=1, q_read_ev=2, q_req_up=0, q_write_ev=2] [L255] COND TRUE (int )p_dw_st == 0 [L256] __retres1 = 1 VAL [__retres1=1, a_t=0, c_dr_i=1, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, p_dw_i=1, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=1, q_read_ev=2, q_req_up=0, q_write_ev=2] [L268] return (__retres1); VAL [\result=1, __retres1=1, a_t=0, c_dr_i=1, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, p_dw_i=1, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=1, q_read_ev=2, q_req_up=0, q_write_ev=2] [L342] RET, EXPR exists_runnable_thread() [L342] tmp___1 = exists_runnable_thread() [L344] COND TRUE \read(tmp___1) VAL [a_t=0, c_dr_i=1, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, p_dw_i=1, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=1, q_read_ev=2, q_req_up=0, q_write_ev=2, tmp___1=1] [L349] COND TRUE (int )p_dw_st == 0 [L351] tmp = __VERIFIER_nondet_int() [L353] COND TRUE \read(tmp) [L355] p_dw_st = 1 [L356] CALL do_write_p() [L128] COND TRUE (int )p_dw_pc == 0 VAL [a_t=0, c_dr_i=1, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, p_dw_i=1, p_dw_pc=0, p_dw_st=1, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=1, q_read_ev=2, q_req_up=0, q_write_ev=2] [L139] COND TRUE 1 VAL [a_t=0, c_dr_i=1, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, p_dw_i=1, p_dw_pc=0, p_dw_st=1, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=1, q_read_ev=2, q_req_up=0, q_write_ev=2] [L141] COND FALSE !((int )q_free == 0) VAL [a_t=0, c_dr_i=1, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, p_dw_i=1, p_dw_pc=0, p_dw_st=1, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=1, q_read_ev=2, q_req_up=0, q_write_ev=2] [L151] q_buf_0 = __VERIFIER_nondet_int() [L152] p_last_write = q_buf_0 [L153] p_num_write += 1 [L154] q_free = 0 [L155] q_req_up = 1 VAL [a_t=0, c_dr_i=1, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, p_dw_i=1, p_dw_pc=0, p_dw_st=1, p_last_write=5, p_num_write=1, q_buf_0=5, q_ev=0, q_free=0, q_read_ev=2, q_req_up=1, q_write_ev=2] [L139] COND TRUE 1 VAL [a_t=0, c_dr_i=1, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, p_dw_i=1, p_dw_pc=0, p_dw_st=1, p_last_write=5, p_num_write=1, q_buf_0=5, q_ev=0, q_free=0, q_read_ev=2, q_req_up=1, q_write_ev=2] [L141] COND TRUE (int )q_free == 0 [L142] p_dw_st = 2 [L143] p_dw_pc = 1 VAL [a_t=0, c_dr_i=1, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, p_dw_i=1, p_dw_pc=1, p_dw_st=2, p_last_write=5, p_num_write=1, q_buf_0=5, q_ev=0, q_free=0, q_read_ev=2, q_req_up=1, q_write_ev=2] [L356] RET do_write_p() Loop: [L364] COND TRUE (int )c_dr_st == 0 [L366] tmp___0 = __VERIFIER_nondet_int() [L368] COND FALSE !(\read(tmp___0)) [L339] COND TRUE 1 [L342] CALL, EXPR exists_runnable_thread() [L252] int __retres1 ; [L255] COND FALSE !((int )p_dw_st == 0) [L259] COND TRUE (int )c_dr_st == 0 [L260] __retres1 = 1 [L268] return (__retres1); [L342] RET, EXPR exists_runnable_thread() [L342] tmp___1 = exists_runnable_thread() [L344] COND TRUE \read(tmp___1) [L349] COND FALSE !((int )p_dw_st == 0) End of lasso representation. RESULT: Ultimate proved your program to be incorrect! [2023-11-19 07:48:57,547 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4334fb4b-5faa-4749-a3d0-a7ded1eaf4de/bin/uautomizer-verify-uCwYo4JHxu/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (1)] Ended with exit code 0 Received shutdown request... --- End real Ultimate output --- Execution finished normally Writing output log to file Ultimate.log Writing human readable error path to file UltimateCounterExample.errorpath Result: FALSE(TERM)