./Ultimate.py --spec ../../sv-benchmarks/c/properties/termination.prp --file ../../sv-benchmarks/c/array-examples/sanfoundry_24-1.i --full-output --architecture 32bit -------------------------------------------------------------------------------- Checking for termination Using default analysis Version 9bd2c7ff Calling Ultimate with: /usr/lib/jvm/java-11-openjdk-amd64/bin/java -Dosgi.configuration.area=/tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7bf958de-f854-47fc-9acd-69b8dc140d51/bin/uautomizer-verify-uCwYo4JHxu/data/config -Xmx15G -Xms4m -jar /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7bf958de-f854-47fc-9acd-69b8dc140d51/bin/uautomizer-verify-uCwYo4JHxu/plugins/org.eclipse.equinox.launcher_1.5.800.v20200727-1323.jar -data @noDefault -ultimatedata /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7bf958de-f854-47fc-9acd-69b8dc140d51/bin/uautomizer-verify-uCwYo4JHxu/data -tc /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7bf958de-f854-47fc-9acd-69b8dc140d51/bin/uautomizer-verify-uCwYo4JHxu/config/AutomizerTermination.xml -i ../../sv-benchmarks/c/array-examples/sanfoundry_24-1.i -s /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7bf958de-f854-47fc-9acd-69b8dc140d51/bin/uautomizer-verify-uCwYo4JHxu/config/svcomp-Termination-32bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7bf958de-f854-47fc-9acd-69b8dc140d51/bin/uautomizer-verify-uCwYo4JHxu --witnessprinter.witness.filename witness --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(F end) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 32bit --witnessprinter.graph.data.programhash e0a16588b251f5de7b3febde43795c7086835cc989637b8bd82aa8d6af355c6b --- Real Ultimate output --- This is Ultimate 0.2.3-dev-9bd2c7f [2023-11-19 07:58:50,986 INFO L188 SettingsManager]: Resetting all preferences to default values... [2023-11-19 07:58:51,052 INFO L114 SettingsManager]: Loading settings from /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7bf958de-f854-47fc-9acd-69b8dc140d51/bin/uautomizer-verify-uCwYo4JHxu/config/svcomp-Termination-32bit-Automizer_Default.epf [2023-11-19 07:58:51,057 WARN L101 SettingsManager]: Preference file contains the following unknown settings: [2023-11-19 07:58:51,058 WARN L103 SettingsManager]: * de.uni_freiburg.informatik.ultimate.core.Log level for class [2023-11-19 07:58:51,085 INFO L130 SettingsManager]: Preferences different from defaults after loading the file: [2023-11-19 07:58:51,086 INFO L151 SettingsManager]: Preferences of UltimateCore differ from their defaults: [2023-11-19 07:58:51,086 INFO L153 SettingsManager]: * Log level for class=de.uni_freiburg.informatik.ultimate.lib.smtlibutils.quantifier.QuantifierPusher=ERROR; [2023-11-19 07:58:51,087 INFO L151 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2023-11-19 07:58:51,088 INFO L153 SettingsManager]: * Create parallel compositions if possible=false [2023-11-19 07:58:51,089 INFO L153 SettingsManager]: * Use SBE=true [2023-11-19 07:58:51,089 INFO L151 SettingsManager]: Preferences of BuchiAutomizer differ from their defaults: [2023-11-19 07:58:51,090 INFO L153 SettingsManager]: * NCSB implementation=INTSET_LAZY3 [2023-11-19 07:58:51,091 INFO L153 SettingsManager]: * Use old map elimination=false [2023-11-19 07:58:51,091 INFO L153 SettingsManager]: * Use external solver (rank synthesis)=false [2023-11-19 07:58:51,092 INFO L153 SettingsManager]: * Use only trivial implications for array writes=true [2023-11-19 07:58:51,092 INFO L153 SettingsManager]: * Rank analysis=LINEAR_WITH_GUESSES [2023-11-19 07:58:51,093 INFO L151 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2023-11-19 07:58:51,093 INFO L153 SettingsManager]: * Pointer base address is valid at dereference=ASSUME [2023-11-19 07:58:51,094 INFO L153 SettingsManager]: * sizeof long=4 [2023-11-19 07:58:51,095 INFO L153 SettingsManager]: * Overapproximate operations on floating types=true [2023-11-19 07:58:51,095 INFO L153 SettingsManager]: * sizeof POINTER=4 [2023-11-19 07:58:51,096 INFO L153 SettingsManager]: * Check division by zero=IGNORE [2023-11-19 07:58:51,096 INFO L153 SettingsManager]: * Pointer to allocated memory at dereference=ASSUME [2023-11-19 07:58:51,097 INFO L153 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=ASSUME [2023-11-19 07:58:51,098 INFO L153 SettingsManager]: * Check array bounds for arrays that are off heap=ASSUME [2023-11-19 07:58:51,098 INFO L153 SettingsManager]: * Check unreachability of reach_error function=false [2023-11-19 07:58:51,099 INFO L153 SettingsManager]: * sizeof long double=12 [2023-11-19 07:58:51,099 INFO L153 SettingsManager]: * Check if freed pointer was valid=false [2023-11-19 07:58:51,100 INFO L153 SettingsManager]: * Assume nondeterminstic values are in range=false [2023-11-19 07:58:51,100 INFO L153 SettingsManager]: * Use constant arrays=true [2023-11-19 07:58:51,101 INFO L151 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2023-11-19 07:58:51,102 INFO L153 SettingsManager]: * Size of a code block=SequenceOfStatements [2023-11-19 07:58:51,102 INFO L151 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2023-11-19 07:58:51,103 INFO L153 SettingsManager]: * Trace refinement strategy=CAMEL [2023-11-19 07:58:51,104 INFO L151 SettingsManager]: Preferences of IcfgTransformer differ from their defaults: [2023-11-19 07:58:51,104 INFO L153 SettingsManager]: * TransformationType=MODULO_NEIGHBOR WARNING: An illegal reflective access operation has occurred WARNING: Illegal reflective access by com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 (file:/tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7bf958de-f854-47fc-9acd-69b8dc140d51/bin/uautomizer-verify-uCwYo4JHxu/plugins/com.sun.xml.bind_2.2.0.v201505121915.jar) to method java.lang.ClassLoader.defineClass(java.lang.String,byte[],int,int) WARNING: Please consider reporting this to the maintainers of com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 WARNING: Use --illegal-access=warn to enable warnings of further illegal reflective access operations WARNING: All illegal access operations will be denied in a future release Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7bf958de-f854-47fc-9acd-69b8dc140d51/bin/uautomizer-verify-uCwYo4JHxu Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(F end) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 32bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> e0a16588b251f5de7b3febde43795c7086835cc989637b8bd82aa8d6af355c6b [2023-11-19 07:58:51,384 INFO L75 nceAwareModelManager]: Repository-Root is: /tmp [2023-11-19 07:58:51,424 INFO L261 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2023-11-19 07:58:51,427 INFO L217 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2023-11-19 07:58:51,428 INFO L270 PluginConnector]: Initializing CDTParser... [2023-11-19 07:58:51,429 INFO L274 PluginConnector]: CDTParser initialized [2023-11-19 07:58:51,430 INFO L431 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7bf958de-f854-47fc-9acd-69b8dc140d51/bin/uautomizer-verify-uCwYo4JHxu/../../sv-benchmarks/c/array-examples/sanfoundry_24-1.i [2023-11-19 07:58:54,567 INFO L533 CDTParser]: Created temporary CDT project at NULL [2023-11-19 07:58:54,787 INFO L384 CDTParser]: Found 1 translation units. [2023-11-19 07:58:54,788 INFO L180 CDTParser]: Scanning /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7bf958de-f854-47fc-9acd-69b8dc140d51/sv-benchmarks/c/array-examples/sanfoundry_24-1.i [2023-11-19 07:58:54,797 INFO L427 CDTParser]: About to delete temporary CDT project at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7bf958de-f854-47fc-9acd-69b8dc140d51/bin/uautomizer-verify-uCwYo4JHxu/data/76eb55e27/f44409c8ab5445a1bc9f7dc950dfbefd/FLAGaaa38d034 [2023-11-19 07:58:54,818 INFO L435 CDTParser]: Successfully deleted /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7bf958de-f854-47fc-9acd-69b8dc140d51/bin/uautomizer-verify-uCwYo4JHxu/data/76eb55e27/f44409c8ab5445a1bc9f7dc950dfbefd [2023-11-19 07:58:54,827 INFO L299 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2023-11-19 07:58:54,832 INFO L133 ToolchainWalker]: Walking toolchain with 6 elements. [2023-11-19 07:58:54,834 INFO L112 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2023-11-19 07:58:54,835 INFO L270 PluginConnector]: Initializing CACSL2BoogieTranslator... [2023-11-19 07:58:54,841 INFO L274 PluginConnector]: CACSL2BoogieTranslator initialized [2023-11-19 07:58:54,842 INFO L184 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 19.11 07:58:54" (1/1) ... [2023-11-19 07:58:54,843 INFO L204 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@ef121e9 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 19.11 07:58:54, skipping insertion in model container [2023-11-19 07:58:54,843 INFO L184 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 19.11 07:58:54" (1/1) ... [2023-11-19 07:58:54,871 INFO L177 MainTranslator]: Built tables and reachable declarations [2023-11-19 07:58:55,084 INFO L209 PostProcessor]: Analyzing one entry point: main [2023-11-19 07:58:55,101 INFO L202 MainTranslator]: Completed pre-run [2023-11-19 07:58:55,118 INFO L209 PostProcessor]: Analyzing one entry point: main [2023-11-19 07:58:55,133 INFO L206 MainTranslator]: Completed translation [2023-11-19 07:58:55,133 INFO L201 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 19.11 07:58:55 WrapperNode [2023-11-19 07:58:55,133 INFO L131 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2023-11-19 07:58:55,135 INFO L112 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2023-11-19 07:58:55,135 INFO L270 PluginConnector]: Initializing Boogie Procedure Inliner... [2023-11-19 07:58:55,135 INFO L274 PluginConnector]: Boogie Procedure Inliner initialized [2023-11-19 07:58:55,143 INFO L184 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 19.11 07:58:55" (1/1) ... [2023-11-19 07:58:55,152 INFO L184 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 19.11 07:58:55" (1/1) ... [2023-11-19 07:58:55,178 INFO L138 Inliner]: procedures = 18, calls = 19, calls flagged for inlining = 7, calls inlined = 8, statements flattened = 80 [2023-11-19 07:58:55,178 INFO L131 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2023-11-19 07:58:55,179 INFO L112 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2023-11-19 07:58:55,179 INFO L270 PluginConnector]: Initializing Boogie Preprocessor... [2023-11-19 07:58:55,179 INFO L274 PluginConnector]: Boogie Preprocessor initialized [2023-11-19 07:58:55,188 INFO L184 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 19.11 07:58:55" (1/1) ... [2023-11-19 07:58:55,189 INFO L184 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 19.11 07:58:55" (1/1) ... [2023-11-19 07:58:55,191 INFO L184 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 19.11 07:58:55" (1/1) ... [2023-11-19 07:58:55,192 INFO L184 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 19.11 07:58:55" (1/1) ... [2023-11-19 07:58:55,198 INFO L184 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 19.11 07:58:55" (1/1) ... [2023-11-19 07:58:55,202 INFO L184 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 19.11 07:58:55" (1/1) ... [2023-11-19 07:58:55,203 INFO L184 PluginConnector]: Executing the observer LTLStepAnnotator from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 19.11 07:58:55" (1/1) ... [2023-11-19 07:58:55,204 INFO L184 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 19.11 07:58:55" (1/1) ... [2023-11-19 07:58:55,207 INFO L131 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2023-11-19 07:58:55,208 INFO L112 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2023-11-19 07:58:55,208 INFO L270 PluginConnector]: Initializing RCFGBuilder... [2023-11-19 07:58:55,208 INFO L274 PluginConnector]: RCFGBuilder initialized [2023-11-19 07:58:55,209 INFO L184 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 19.11 07:58:55" (1/1) ... [2023-11-19 07:58:55,215 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2023-11-19 07:58:55,231 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7bf958de-f854-47fc-9acd-69b8dc140d51/bin/uautomizer-verify-uCwYo4JHxu/z3 [2023-11-19 07:58:55,245 INFO L229 MonitoredProcess]: Starting monitored process 1 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7bf958de-f854-47fc-9acd-69b8dc140d51/bin/uautomizer-verify-uCwYo4JHxu/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2023-11-19 07:58:55,273 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7bf958de-f854-47fc-9acd-69b8dc140d51/bin/uautomizer-verify-uCwYo4JHxu/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (1)] Waiting until timeout for monitored process [2023-11-19 07:58:55,299 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocInit [2023-11-19 07:58:55,300 INFO L130 BoogieDeclarations]: Found specification of procedure write~init~int [2023-11-19 07:58:55,300 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocOnStack [2023-11-19 07:58:55,301 INFO L130 BoogieDeclarations]: Found specification of procedure write~int [2023-11-19 07:58:55,302 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2023-11-19 07:58:55,302 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2023-11-19 07:58:55,303 INFO L130 BoogieDeclarations]: Found specification of procedure read~int [2023-11-19 07:58:55,303 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.dealloc [2023-11-19 07:58:55,373 INFO L236 CfgBuilder]: Building ICFG [2023-11-19 07:58:55,375 INFO L262 CfgBuilder]: Building CFG for each procedure with an implementation [2023-11-19 07:58:55,606 INFO L277 CfgBuilder]: Performing block encoding [2023-11-19 07:58:55,619 INFO L297 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2023-11-19 07:58:55,619 INFO L302 CfgBuilder]: Removed 3 assume(true) statements. [2023-11-19 07:58:55,623 INFO L201 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 19.11 07:58:55 BoogieIcfgContainer [2023-11-19 07:58:55,623 INFO L131 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2023-11-19 07:58:55,624 INFO L112 PluginConnector]: ------------------------BuchiAutomizer---------------------------- [2023-11-19 07:58:55,625 INFO L270 PluginConnector]: Initializing BuchiAutomizer... [2023-11-19 07:58:55,629 INFO L274 PluginConnector]: BuchiAutomizer initialized [2023-11-19 07:58:55,630 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2023-11-19 07:58:55,630 INFO L184 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "CDTParser AST 19.11 07:58:54" (1/3) ... [2023-11-19 07:58:55,631 INFO L204 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@6c3e398a and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 19.11 07:58:55, skipping insertion in model container [2023-11-19 07:58:55,631 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2023-11-19 07:58:55,632 INFO L184 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 19.11 07:58:55" (2/3) ... [2023-11-19 07:58:55,632 INFO L204 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@6c3e398a and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 19.11 07:58:55, skipping insertion in model container [2023-11-19 07:58:55,632 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2023-11-19 07:58:55,633 INFO L184 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 19.11 07:58:55" (3/3) ... [2023-11-19 07:58:55,634 INFO L332 chiAutomizerObserver]: Analyzing ICFG sanfoundry_24-1.i [2023-11-19 07:58:55,702 INFO L303 stractBuchiCegarLoop]: Interprodecural is true [2023-11-19 07:58:55,703 INFO L304 stractBuchiCegarLoop]: Hoare is false [2023-11-19 07:58:55,703 INFO L305 stractBuchiCegarLoop]: Compute interpolants for ForwardPredicates [2023-11-19 07:58:55,703 INFO L306 stractBuchiCegarLoop]: Backedges is STRAIGHT_LINE [2023-11-19 07:58:55,703 INFO L307 stractBuchiCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2023-11-19 07:58:55,704 INFO L308 stractBuchiCegarLoop]: Difference is false [2023-11-19 07:58:55,704 INFO L309 stractBuchiCegarLoop]: Minimize is MINIMIZE_SEVPA [2023-11-19 07:58:55,704 INFO L313 stractBuchiCegarLoop]: ======== Iteration 0 == of CEGAR loop == BuchiAutomatonCegarLoop ======== [2023-11-19 07:58:55,709 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 28 states, 27 states have (on average 1.4444444444444444) internal successors, (39), 27 states have internal predecessors, (39), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-19 07:58:55,729 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 20 [2023-11-19 07:58:55,729 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-19 07:58:55,729 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-19 07:58:55,735 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1] [2023-11-19 07:58:55,735 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1] [2023-11-19 07:58:55,736 INFO L335 stractBuchiCegarLoop]: ======== Iteration 1 ============ [2023-11-19 07:58:55,736 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 28 states, 27 states have (on average 1.4444444444444444) internal successors, (39), 27 states have internal predecessors, (39), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-19 07:58:55,739 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 20 [2023-11-19 07:58:55,739 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-19 07:58:55,739 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-19 07:58:55,739 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1] [2023-11-19 07:58:55,740 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1] [2023-11-19 07:58:55,748 INFO L748 eck$LassoCheckResult]: Stem: 27#$Ultimate##0true assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(18, 2); 4#L-1true assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet1#1, main_#t~nondet3#1, main_#t~post2#1, main_#t~mem5#1, main_#t~mem6#1, main_#t~post4#1, main_#t~mem8#1, main_#t~mem9#1, main_#t~post7#1, main_~#array~0#1.base, main_~#array~0#1.offset, main_~i~0#1, main_~num~0#1;call main_~#array~0#1.base, main_~#array~0#1.offset := #Ultimate.allocOnStack(400000);havoc main_~i~0#1;havoc main_#t~nondet1#1;main_~num~0#1 := main_#t~nondet1#1;havoc main_#t~nondet1#1;main_~i~0#1 := 0; 28#L27-3true [2023-11-19 07:58:55,748 INFO L750 eck$LassoCheckResult]: Loop: 28#L27-3true assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 5#L27-2true main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 28#L27-3true [2023-11-19 07:58:55,754 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-19 07:58:55,754 INFO L85 PathProgramCache]: Analyzing trace with hash 963, now seen corresponding path program 1 times [2023-11-19 07:58:55,765 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-19 07:58:55,765 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1485156488] [2023-11-19 07:58:55,766 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-19 07:58:55,766 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-19 07:58:55,877 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-19 07:58:55,878 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-19 07:58:55,892 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-19 07:58:55,920 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-19 07:58:55,925 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-19 07:58:55,926 INFO L85 PathProgramCache]: Analyzing trace with hash 1283, now seen corresponding path program 1 times [2023-11-19 07:58:55,926 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-19 07:58:55,926 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1856281245] [2023-11-19 07:58:55,927 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-19 07:58:55,927 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-19 07:58:55,956 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-19 07:58:55,957 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-19 07:58:55,978 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-19 07:58:55,985 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-19 07:58:55,988 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-19 07:58:55,988 INFO L85 PathProgramCache]: Analyzing trace with hash 925765, now seen corresponding path program 1 times [2023-11-19 07:58:55,988 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-19 07:58:55,988 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [247280601] [2023-11-19 07:58:55,989 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-19 07:58:55,989 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-19 07:58:56,034 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-19 07:58:56,034 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-19 07:58:56,083 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-19 07:58:56,087 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-19 07:58:56,504 INFO L210 LassoAnalysis]: Preferences: [2023-11-19 07:58:56,505 INFO L126 ssoRankerPreferences]: Compute integeral hull: false [2023-11-19 07:58:56,505 INFO L127 ssoRankerPreferences]: Enable LassoPartitioneer: true [2023-11-19 07:58:56,506 INFO L128 ssoRankerPreferences]: Term annotations enabled: false [2023-11-19 07:58:56,506 INFO L129 ssoRankerPreferences]: Use exernal solver: false [2023-11-19 07:58:56,506 INFO L130 ssoRankerPreferences]: SMT solver command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2023-11-19 07:58:56,506 INFO L131 ssoRankerPreferences]: Dump SMT script to file: false [2023-11-19 07:58:56,507 INFO L132 ssoRankerPreferences]: Path of dumped script: [2023-11-19 07:58:56,507 INFO L133 ssoRankerPreferences]: Filename of dumped script: sanfoundry_24-1.i_Iteration1_Lasso [2023-11-19 07:58:56,507 INFO L134 ssoRankerPreferences]: MapElimAlgo: Frank [2023-11-19 07:58:56,507 INFO L276 LassoAnalysis]: Starting lasso preprocessing... [2023-11-19 07:58:56,527 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-19 07:58:56,537 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-19 07:58:56,542 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-19 07:58:56,545 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-19 07:58:56,549 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-19 07:58:56,553 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-19 07:58:56,556 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-19 07:58:56,560 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-19 07:58:56,813 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-19 07:58:56,816 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-19 07:58:56,819 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-19 07:58:57,088 INFO L294 LassoAnalysis]: Preprocessing complete. [2023-11-19 07:58:57,093 INFO L490 LassoAnalysis]: Using template 'affine'. [2023-11-19 07:58:57,095 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2023-11-19 07:58:57,096 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7bf958de-f854-47fc-9acd-69b8dc140d51/bin/uautomizer-verify-uCwYo4JHxu/z3 [2023-11-19 07:58:57,101 INFO L229 MonitoredProcess]: Starting monitored process 2 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7bf958de-f854-47fc-9acd-69b8dc140d51/bin/uautomizer-verify-uCwYo4JHxu/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2023-11-19 07:58:57,106 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2023-11-19 07:58:57,119 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2023-11-19 07:58:57,119 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2023-11-19 07:58:57,120 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2023-11-19 07:58:57,120 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2023-11-19 07:58:57,120 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2023-11-19 07:58:57,122 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2023-11-19 07:58:57,122 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2023-11-19 07:58:57,124 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7bf958de-f854-47fc-9acd-69b8dc140d51/bin/uautomizer-verify-uCwYo4JHxu/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (2)] Waiting until timeout for monitored process [2023-11-19 07:58:57,132 INFO L527 LassoAnalysis]: Proving termination failed for this template and these settings. [2023-11-19 07:58:57,149 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7bf958de-f854-47fc-9acd-69b8dc140d51/bin/uautomizer-verify-uCwYo4JHxu/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (2)] Forceful destruction successful, exit code 0 [2023-11-19 07:58:57,150 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2023-11-19 07:58:57,150 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7bf958de-f854-47fc-9acd-69b8dc140d51/bin/uautomizer-verify-uCwYo4JHxu/z3 [2023-11-19 07:58:57,152 INFO L229 MonitoredProcess]: Starting monitored process 3 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7bf958de-f854-47fc-9acd-69b8dc140d51/bin/uautomizer-verify-uCwYo4JHxu/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2023-11-19 07:58:57,165 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2023-11-19 07:58:57,170 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7bf958de-f854-47fc-9acd-69b8dc140d51/bin/uautomizer-verify-uCwYo4JHxu/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (3)] Waiting until timeout for monitored process [2023-11-19 07:58:57,176 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2023-11-19 07:58:57,177 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2023-11-19 07:58:57,177 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2023-11-19 07:58:57,177 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2023-11-19 07:58:57,177 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2023-11-19 07:58:57,178 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2023-11-19 07:58:57,178 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2023-11-19 07:58:57,187 INFO L527 LassoAnalysis]: Proving termination failed for this template and these settings. [2023-11-19 07:58:57,211 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7bf958de-f854-47fc-9acd-69b8dc140d51/bin/uautomizer-verify-uCwYo4JHxu/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (3)] Forceful destruction successful, exit code 0 [2023-11-19 07:58:57,212 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2023-11-19 07:58:57,212 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7bf958de-f854-47fc-9acd-69b8dc140d51/bin/uautomizer-verify-uCwYo4JHxu/z3 [2023-11-19 07:58:57,213 INFO L229 MonitoredProcess]: Starting monitored process 4 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7bf958de-f854-47fc-9acd-69b8dc140d51/bin/uautomizer-verify-uCwYo4JHxu/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2023-11-19 07:58:57,216 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7bf958de-f854-47fc-9acd-69b8dc140d51/bin/uautomizer-verify-uCwYo4JHxu/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (4)] Waiting until timeout for monitored process [2023-11-19 07:58:57,216 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2023-11-19 07:58:57,226 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2023-11-19 07:58:57,227 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2023-11-19 07:58:57,227 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2023-11-19 07:58:57,227 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2023-11-19 07:58:57,227 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2023-11-19 07:58:57,228 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2023-11-19 07:58:57,228 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2023-11-19 07:58:57,239 INFO L527 LassoAnalysis]: Proving termination failed for this template and these settings. [2023-11-19 07:58:57,256 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7bf958de-f854-47fc-9acd-69b8dc140d51/bin/uautomizer-verify-uCwYo4JHxu/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (4)] Forceful destruction successful, exit code 0 [2023-11-19 07:58:57,257 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2023-11-19 07:58:57,257 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7bf958de-f854-47fc-9acd-69b8dc140d51/bin/uautomizer-verify-uCwYo4JHxu/z3 [2023-11-19 07:58:57,258 INFO L229 MonitoredProcess]: Starting monitored process 5 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7bf958de-f854-47fc-9acd-69b8dc140d51/bin/uautomizer-verify-uCwYo4JHxu/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2023-11-19 07:58:57,260 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7bf958de-f854-47fc-9acd-69b8dc140d51/bin/uautomizer-verify-uCwYo4JHxu/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (5)] Waiting until timeout for monitored process [2023-11-19 07:58:57,261 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2023-11-19 07:58:57,271 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2023-11-19 07:58:57,272 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2023-11-19 07:58:57,272 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2023-11-19 07:58:57,272 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2023-11-19 07:58:57,272 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2023-11-19 07:58:57,273 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2023-11-19 07:58:57,273 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2023-11-19 07:58:57,283 INFO L527 LassoAnalysis]: Proving termination failed for this template and these settings. [2023-11-19 07:58:57,298 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7bf958de-f854-47fc-9acd-69b8dc140d51/bin/uautomizer-verify-uCwYo4JHxu/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (5)] Ended with exit code 0 [2023-11-19 07:58:57,298 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2023-11-19 07:58:57,298 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7bf958de-f854-47fc-9acd-69b8dc140d51/bin/uautomizer-verify-uCwYo4JHxu/z3 [2023-11-19 07:58:57,300 INFO L229 MonitoredProcess]: Starting monitored process 6 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7bf958de-f854-47fc-9acd-69b8dc140d51/bin/uautomizer-verify-uCwYo4JHxu/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2023-11-19 07:58:57,333 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2023-11-19 07:58:57,335 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7bf958de-f854-47fc-9acd-69b8dc140d51/bin/uautomizer-verify-uCwYo4JHxu/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (6)] Waiting until timeout for monitored process [2023-11-19 07:58:57,348 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2023-11-19 07:58:57,349 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2023-11-19 07:58:57,349 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2023-11-19 07:58:57,349 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2023-11-19 07:58:57,349 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2023-11-19 07:58:57,350 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2023-11-19 07:58:57,350 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2023-11-19 07:58:57,360 INFO L527 LassoAnalysis]: Proving termination failed for this template and these settings. [2023-11-19 07:58:57,376 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7bf958de-f854-47fc-9acd-69b8dc140d51/bin/uautomizer-verify-uCwYo4JHxu/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (6)] Forceful destruction successful, exit code 0 [2023-11-19 07:58:57,376 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2023-11-19 07:58:57,377 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7bf958de-f854-47fc-9acd-69b8dc140d51/bin/uautomizer-verify-uCwYo4JHxu/z3 [2023-11-19 07:58:57,378 INFO L229 MonitoredProcess]: Starting monitored process 7 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7bf958de-f854-47fc-9acd-69b8dc140d51/bin/uautomizer-verify-uCwYo4JHxu/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2023-11-19 07:58:57,379 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7bf958de-f854-47fc-9acd-69b8dc140d51/bin/uautomizer-verify-uCwYo4JHxu/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (7)] Waiting until timeout for monitored process [2023-11-19 07:58:57,381 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2023-11-19 07:58:57,392 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2023-11-19 07:58:57,392 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2023-11-19 07:58:57,392 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2023-11-19 07:58:57,392 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2023-11-19 07:58:57,392 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2023-11-19 07:58:57,393 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2023-11-19 07:58:57,393 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2023-11-19 07:58:57,400 INFO L527 LassoAnalysis]: Proving termination failed for this template and these settings. [2023-11-19 07:58:57,428 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7bf958de-f854-47fc-9acd-69b8dc140d51/bin/uautomizer-verify-uCwYo4JHxu/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (7)] Forceful destruction successful, exit code 0 [2023-11-19 07:58:57,428 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2023-11-19 07:58:57,428 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7bf958de-f854-47fc-9acd-69b8dc140d51/bin/uautomizer-verify-uCwYo4JHxu/z3 [2023-11-19 07:58:57,429 INFO L229 MonitoredProcess]: Starting monitored process 8 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7bf958de-f854-47fc-9acd-69b8dc140d51/bin/uautomizer-verify-uCwYo4JHxu/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2023-11-19 07:58:57,431 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7bf958de-f854-47fc-9acd-69b8dc140d51/bin/uautomizer-verify-uCwYo4JHxu/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (8)] Waiting until timeout for monitored process [2023-11-19 07:58:57,432 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2023-11-19 07:58:57,442 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2023-11-19 07:58:57,442 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2023-11-19 07:58:57,442 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2023-11-19 07:58:57,442 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2023-11-19 07:58:57,442 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2023-11-19 07:58:57,443 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2023-11-19 07:58:57,443 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2023-11-19 07:58:57,452 INFO L527 LassoAnalysis]: Proving termination failed for this template and these settings. [2023-11-19 07:58:57,468 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7bf958de-f854-47fc-9acd-69b8dc140d51/bin/uautomizer-verify-uCwYo4JHxu/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (8)] Forceful destruction successful, exit code 0 [2023-11-19 07:58:57,469 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2023-11-19 07:58:57,469 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7bf958de-f854-47fc-9acd-69b8dc140d51/bin/uautomizer-verify-uCwYo4JHxu/z3 [2023-11-19 07:58:57,470 INFO L229 MonitoredProcess]: Starting monitored process 9 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7bf958de-f854-47fc-9acd-69b8dc140d51/bin/uautomizer-verify-uCwYo4JHxu/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2023-11-19 07:58:57,471 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7bf958de-f854-47fc-9acd-69b8dc140d51/bin/uautomizer-verify-uCwYo4JHxu/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (9)] Waiting until timeout for monitored process [2023-11-19 07:58:57,474 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2023-11-19 07:58:57,485 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2023-11-19 07:58:57,485 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2023-11-19 07:58:57,485 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2023-11-19 07:58:57,485 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2023-11-19 07:58:57,489 INFO L401 nArgumentSynthesizer]: We have 6 Motzkin's Theorem applications. [2023-11-19 07:58:57,489 INFO L402 nArgumentSynthesizer]: A total of 2 supporting invariants were added. [2023-11-19 07:58:57,516 INFO L527 LassoAnalysis]: Proving termination failed for this template and these settings. [2023-11-19 07:58:57,540 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7bf958de-f854-47fc-9acd-69b8dc140d51/bin/uautomizer-verify-uCwYo4JHxu/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (9)] Forceful destruction successful, exit code 0 [2023-11-19 07:58:57,540 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2023-11-19 07:58:57,541 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7bf958de-f854-47fc-9acd-69b8dc140d51/bin/uautomizer-verify-uCwYo4JHxu/z3 [2023-11-19 07:58:57,542 INFO L229 MonitoredProcess]: Starting monitored process 10 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7bf958de-f854-47fc-9acd-69b8dc140d51/bin/uautomizer-verify-uCwYo4JHxu/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2023-11-19 07:58:57,549 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2023-11-19 07:58:57,562 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2023-11-19 07:58:57,562 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2023-11-19 07:58:57,562 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2023-11-19 07:58:57,562 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2023-11-19 07:58:57,566 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7bf958de-f854-47fc-9acd-69b8dc140d51/bin/uautomizer-verify-uCwYo4JHxu/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (10)] Waiting until timeout for monitored process [2023-11-19 07:58:57,579 INFO L401 nArgumentSynthesizer]: We have 6 Motzkin's Theorem applications. [2023-11-19 07:58:57,579 INFO L402 nArgumentSynthesizer]: A total of 2 supporting invariants were added. [2023-11-19 07:58:57,604 INFO L420 nArgumentSynthesizer]: Found a termination argument, trying to simplify. [2023-11-19 07:58:57,658 INFO L443 ModelExtractionUtils]: Simplification made 14 calls to the SMT solver. [2023-11-19 07:58:57,658 INFO L444 ModelExtractionUtils]: 2 out of 16 variables were initially zero. Simplification set additionally 11 variables to zero. [2023-11-19 07:58:57,660 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2023-11-19 07:58:57,660 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7bf958de-f854-47fc-9acd-69b8dc140d51/bin/uautomizer-verify-uCwYo4JHxu/z3 [2023-11-19 07:58:57,685 INFO L229 MonitoredProcess]: Starting monitored process 11 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7bf958de-f854-47fc-9acd-69b8dc140d51/bin/uautomizer-verify-uCwYo4JHxu/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2023-11-19 07:58:57,705 INFO L435 nArgumentSynthesizer]: Simplifying supporting invariants... [2023-11-19 07:58:57,717 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7bf958de-f854-47fc-9acd-69b8dc140d51/bin/uautomizer-verify-uCwYo4JHxu/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (11)] Waiting until timeout for monitored process [2023-11-19 07:58:57,725 INFO L438 nArgumentSynthesizer]: Removed 2 redundant supporting invariants from a total of 2. [2023-11-19 07:58:57,726 INFO L513 LassoAnalysis]: Proved termination. [2023-11-19 07:58:57,726 INFO L515 LassoAnalysis]: Termination argument consisting of: Ranking function f(ULTIMATE.start_main_~i~0#1, ULTIMATE.start_main_~num~0#1) = -1*ULTIMATE.start_main_~i~0#1 + 1*ULTIMATE.start_main_~num~0#1 Supporting invariants [] [2023-11-19 07:58:57,748 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7bf958de-f854-47fc-9acd-69b8dc140d51/bin/uautomizer-verify-uCwYo4JHxu/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (10)] Forceful destruction successful, exit code 0 [2023-11-19 07:58:57,772 INFO L156 tatePredicateManager]: 5 out of 5 supporting invariants were superfluous and have been removed [2023-11-19 07:58:57,794 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-19 07:58:57,808 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-19 07:58:57,810 INFO L262 TraceCheckSpWp]: Trace formula consists of 31 conjuncts, 2 conjunts are in the unsatisfiable core [2023-11-19 07:58:57,812 INFO L285 TraceCheckSpWp]: Computing forward predicates... [2023-11-19 07:58:57,854 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-19 07:58:57,855 INFO L262 TraceCheckSpWp]: Trace formula consists of 13 conjuncts, 4 conjunts are in the unsatisfiable core [2023-11-19 07:58:57,856 INFO L285 TraceCheckSpWp]: Computing forward predicates... [2023-11-19 07:58:57,873 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-19 07:58:57,920 INFO L141 lantAutomatonBouncer]: Defining deterministic Buchi interpolant automaton with honda bouncer for stem and without honda bouncer for loop.1 stem predicates 2 loop predicates [2023-11-19 07:58:57,922 INFO L71 iDifferenceNCSBLazy3]: Start buchiDifferenceNCSBLazy3. First operand has 28 states, 27 states have (on average 1.4444444444444444) internal successors, (39), 27 states have internal predecessors, (39), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand has 3 states, 3 states have (on average 1.3333333333333333) internal successors, (4), 3 states have internal predecessors, (4), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-19 07:58:57,994 INFO L75 iDifferenceNCSBLazy3]: Finished buchiDifferenceNCSBLazy3. First operand has 28 states, 27 states have (on average 1.4444444444444444) internal successors, (39), 27 states have internal predecessors, (39), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0). Second operand has 3 states, 3 states have (on average 1.3333333333333333) internal successors, (4), 3 states have internal predecessors, (4), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Result 55 states and 79 transitions. Complement of second has 8 states. [2023-11-19 07:58:58,001 INFO L141 InterpolantAutomaton]: Switched to read-only mode: Buchi interpolant automaton has 5 states 1 stem states 2 non-accepting loop states 1 accepting loop states [2023-11-19 07:58:58,007 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 3 states, 3 states have (on average 1.3333333333333333) internal successors, (4), 3 states have internal predecessors, (4), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-19 07:58:58,008 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 5 states to 5 states and 39 transitions. [2023-11-19 07:58:58,010 INFO L84 BuchiAccepts]: Start buchiAccepts Operand 5 states and 39 transitions. Stem has 2 letters. Loop has 2 letters. [2023-11-19 07:58:58,010 INFO L116 BuchiAccepts]: Finished buchiAccepts. [2023-11-19 07:58:58,010 INFO L84 BuchiAccepts]: Start buchiAccepts Operand 5 states and 39 transitions. Stem has 4 letters. Loop has 2 letters. [2023-11-19 07:58:58,010 INFO L116 BuchiAccepts]: Finished buchiAccepts. [2023-11-19 07:58:58,011 INFO L84 BuchiAccepts]: Start buchiAccepts Operand 5 states and 39 transitions. Stem has 2 letters. Loop has 4 letters. [2023-11-19 07:58:58,011 INFO L116 BuchiAccepts]: Finished buchiAccepts. [2023-11-19 07:58:58,012 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 55 states and 79 transitions. [2023-11-19 07:58:58,024 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 18 [2023-11-19 07:58:58,030 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 55 states to 25 states and 35 transitions. [2023-11-19 07:58:58,031 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 22 [2023-11-19 07:58:58,031 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 23 [2023-11-19 07:58:58,032 INFO L73 IsDeterministic]: Start isDeterministic. Operand 25 states and 35 transitions. [2023-11-19 07:58:58,032 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-19 07:58:58,032 INFO L218 hiAutomatonCegarLoop]: Abstraction has 25 states and 35 transitions. [2023-11-19 07:58:58,046 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 25 states and 35 transitions. [2023-11-19 07:58:58,053 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 25 to 25. [2023-11-19 07:58:58,053 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 25 states, 25 states have (on average 1.4) internal successors, (35), 24 states have internal predecessors, (35), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-19 07:58:58,054 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 25 states to 25 states and 35 transitions. [2023-11-19 07:58:58,055 INFO L240 hiAutomatonCegarLoop]: Abstraction has 25 states and 35 transitions. [2023-11-19 07:58:58,055 INFO L428 stractBuchiCegarLoop]: Abstraction has 25 states and 35 transitions. [2023-11-19 07:58:58,056 INFO L335 stractBuchiCegarLoop]: ======== Iteration 2 ============ [2023-11-19 07:58:58,056 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 25 states and 35 transitions. [2023-11-19 07:58:58,056 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 18 [2023-11-19 07:58:58,057 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-19 07:58:58,057 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-19 07:58:58,057 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1] [2023-11-19 07:58:58,057 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1] [2023-11-19 07:58:58,057 INFO L748 eck$LassoCheckResult]: Stem: 165#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(18, 2); 153#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet1#1, main_#t~nondet3#1, main_#t~post2#1, main_#t~mem5#1, main_#t~mem6#1, main_#t~post4#1, main_#t~mem8#1, main_#t~mem9#1, main_#t~post7#1, main_~#array~0#1.base, main_~#array~0#1.offset, main_~i~0#1, main_~num~0#1;call main_~#array~0#1.base, main_~#array~0#1.offset := #Ultimate.allocOnStack(400000);havoc main_~i~0#1;havoc main_#t~nondet1#1;main_~num~0#1 := main_#t~nondet1#1;havoc main_#t~nondet1#1;main_~i~0#1 := 0; 154#L27-3 assume !(main_~i~0#1 < main_~num~0#1); 157#L27-4 main_~i~0#1 := 0; 158#L32-3 [2023-11-19 07:58:58,058 INFO L750 eck$LassoCheckResult]: Loop: 158#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 163#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 152#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 158#L32-3 [2023-11-19 07:58:58,058 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-19 07:58:58,058 INFO L85 PathProgramCache]: Analyzing trace with hash 925707, now seen corresponding path program 1 times [2023-11-19 07:58:58,059 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-19 07:58:58,059 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1088192814] [2023-11-19 07:58:58,059 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-19 07:58:58,059 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-19 07:58:58,069 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-19 07:58:58,070 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-19 07:58:58,076 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-19 07:58:58,079 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-19 07:58:58,079 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-19 07:58:58,079 INFO L85 PathProgramCache]: Analyzing trace with hash 54361, now seen corresponding path program 1 times [2023-11-19 07:58:58,080 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-19 07:58:58,080 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [462581824] [2023-11-19 07:58:58,080 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-19 07:58:58,080 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-19 07:58:58,091 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-19 07:58:58,091 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-19 07:58:58,098 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-19 07:58:58,100 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-19 07:58:58,101 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-19 07:58:58,101 INFO L85 PathProgramCache]: Analyzing trace with hash 1807958031, now seen corresponding path program 1 times [2023-11-19 07:58:58,101 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-19 07:58:58,101 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2041860679] [2023-11-19 07:58:58,101 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-19 07:58:58,102 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-19 07:58:58,115 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-19 07:58:58,213 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-19 07:58:58,213 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-19 07:58:58,214 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2041860679] [2023-11-19 07:58:58,214 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2041860679] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-19 07:58:58,214 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-19 07:58:58,215 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2023-11-19 07:58:58,215 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1989168666] [2023-11-19 07:58:58,216 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-19 07:58:58,270 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-19 07:58:58,272 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2023-11-19 07:58:58,273 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2023-11-19 07:58:58,274 INFO L87 Difference]: Start difference. First operand 25 states and 35 transitions. cyclomatic complexity: 13 Second operand has 5 states, 5 states have (on average 1.4) internal successors, (7), 5 states have internal predecessors, (7), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-19 07:58:58,368 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-19 07:58:58,368 INFO L93 Difference]: Finished difference Result 44 states and 51 transitions. [2023-11-19 07:58:58,368 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 44 states and 51 transitions. [2023-11-19 07:58:58,370 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 12 [2023-11-19 07:58:58,371 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 44 states to 32 states and 38 transitions. [2023-11-19 07:58:58,371 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 29 [2023-11-19 07:58:58,372 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 29 [2023-11-19 07:58:58,372 INFO L73 IsDeterministic]: Start isDeterministic. Operand 32 states and 38 transitions. [2023-11-19 07:58:58,372 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-19 07:58:58,372 INFO L218 hiAutomatonCegarLoop]: Abstraction has 32 states and 38 transitions. [2023-11-19 07:58:58,373 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 32 states and 38 transitions. [2023-11-19 07:58:58,374 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 32 to 20. [2023-11-19 07:58:58,374 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 20 states, 20 states have (on average 1.2) internal successors, (24), 19 states have internal predecessors, (24), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-19 07:58:58,375 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 20 states to 20 states and 24 transitions. [2023-11-19 07:58:58,375 INFO L240 hiAutomatonCegarLoop]: Abstraction has 20 states and 24 transitions. [2023-11-19 07:58:58,376 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2023-11-19 07:58:58,377 INFO L428 stractBuchiCegarLoop]: Abstraction has 20 states and 24 transitions. [2023-11-19 07:58:58,377 INFO L335 stractBuchiCegarLoop]: ======== Iteration 3 ============ [2023-11-19 07:58:58,377 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 20 states and 24 transitions. [2023-11-19 07:58:58,378 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 12 [2023-11-19 07:58:58,379 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-19 07:58:58,379 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-19 07:58:58,379 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1] [2023-11-19 07:58:58,380 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1] [2023-11-19 07:58:58,380 INFO L748 eck$LassoCheckResult]: Stem: 239#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(18, 2); 227#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet1#1, main_#t~nondet3#1, main_#t~post2#1, main_#t~mem5#1, main_#t~mem6#1, main_#t~post4#1, main_#t~mem8#1, main_#t~mem9#1, main_#t~post7#1, main_~#array~0#1.base, main_~#array~0#1.offset, main_~i~0#1, main_~num~0#1;call main_~#array~0#1.base, main_~#array~0#1.offset := #Ultimate.allocOnStack(400000);havoc main_~i~0#1;havoc main_#t~nondet1#1;main_~num~0#1 := main_#t~nondet1#1;havoc main_#t~nondet1#1;main_~i~0#1 := 0; 228#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 231#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 232#L27-3 assume !(main_~i~0#1 < main_~num~0#1); 233#L27-4 main_~i~0#1 := 0; 234#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 238#L34 [2023-11-19 07:58:58,380 INFO L750 eck$LassoCheckResult]: Loop: 238#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 226#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 235#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 238#L34 [2023-11-19 07:58:58,381 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-19 07:58:58,381 INFO L85 PathProgramCache]: Analyzing trace with hash 1809669547, now seen corresponding path program 1 times [2023-11-19 07:58:58,381 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-19 07:58:58,382 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2055832137] [2023-11-19 07:58:58,382 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-19 07:58:58,382 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-19 07:58:58,407 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-19 07:58:58,408 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-19 07:58:58,427 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-19 07:58:58,430 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-19 07:58:58,430 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-19 07:58:58,431 INFO L85 PathProgramCache]: Analyzing trace with hash 76501, now seen corresponding path program 2 times [2023-11-19 07:58:58,431 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-19 07:58:58,431 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [339191803] [2023-11-19 07:58:58,431 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-19 07:58:58,431 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-19 07:58:58,437 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-19 07:58:58,437 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-19 07:58:58,455 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-19 07:58:58,457 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-19 07:58:58,458 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-19 07:58:58,458 INFO L85 PathProgramCache]: Analyzing trace with hash 1436021995, now seen corresponding path program 1 times [2023-11-19 07:58:58,458 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-19 07:58:58,458 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [561572255] [2023-11-19 07:58:58,458 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-19 07:58:58,459 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-19 07:58:58,485 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-19 07:58:58,640 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-19 07:58:58,640 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-19 07:58:58,642 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [561572255] [2023-11-19 07:58:58,643 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [561572255] provided 0 perfect and 1 imperfect interpolant sequences [2023-11-19 07:58:58,643 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1888302005] [2023-11-19 07:58:58,643 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-19 07:58:58,643 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2023-11-19 07:58:58,644 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7bf958de-f854-47fc-9acd-69b8dc140d51/bin/uautomizer-verify-uCwYo4JHxu/z3 [2023-11-19 07:58:58,657 INFO L229 MonitoredProcess]: Starting monitored process 12 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7bf958de-f854-47fc-9acd-69b8dc140d51/bin/uautomizer-verify-uCwYo4JHxu/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2023-11-19 07:58:58,684 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7bf958de-f854-47fc-9acd-69b8dc140d51/bin/uautomizer-verify-uCwYo4JHxu/z3 -smt2 -in SMTLIB2_COMPLIANT=true (12)] Waiting until timeout for monitored process [2023-11-19 07:58:58,716 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-19 07:58:58,717 INFO L262 TraceCheckSpWp]: Trace formula consists of 62 conjuncts, 6 conjunts are in the unsatisfiable core [2023-11-19 07:58:58,718 INFO L285 TraceCheckSpWp]: Computing forward predicates... [2023-11-19 07:58:58,806 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 1 proven. 1 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-19 07:58:58,806 INFO L327 TraceCheckSpWp]: Computing backward predicates... [2023-11-19 07:58:58,862 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 1 proven. 1 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-19 07:58:58,862 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1888302005] provided 0 perfect and 2 imperfect interpolant sequences [2023-11-19 07:58:58,863 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2023-11-19 07:58:58,863 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [6, 6, 6] total 10 [2023-11-19 07:58:58,863 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1605564360] [2023-11-19 07:58:58,863 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2023-11-19 07:58:58,925 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-19 07:58:58,926 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 11 interpolants. [2023-11-19 07:58:58,927 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=35, Invalid=75, Unknown=0, NotChecked=0, Total=110 [2023-11-19 07:58:58,927 INFO L87 Difference]: Start difference. First operand 20 states and 24 transitions. cyclomatic complexity: 7 Second operand has 11 states, 10 states have (on average 2.2) internal successors, (22), 11 states have internal predecessors, (22), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-19 07:58:59,091 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-19 07:58:59,091 INFO L93 Difference]: Finished difference Result 63 states and 74 transitions. [2023-11-19 07:58:59,091 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 63 states and 74 transitions. [2023-11-19 07:58:59,099 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 12 [2023-11-19 07:58:59,100 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 63 states to 46 states and 54 transitions. [2023-11-19 07:58:59,100 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 41 [2023-11-19 07:58:59,101 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 41 [2023-11-19 07:58:59,101 INFO L73 IsDeterministic]: Start isDeterministic. Operand 46 states and 54 transitions. [2023-11-19 07:58:59,101 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-19 07:58:59,102 INFO L218 hiAutomatonCegarLoop]: Abstraction has 46 states and 54 transitions. [2023-11-19 07:58:59,102 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 46 states and 54 transitions. [2023-11-19 07:58:59,106 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 46 to 28. [2023-11-19 07:58:59,107 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 28 states, 28 states have (on average 1.1785714285714286) internal successors, (33), 27 states have internal predecessors, (33), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-19 07:58:59,109 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 28 states to 28 states and 33 transitions. [2023-11-19 07:58:59,110 INFO L240 hiAutomatonCegarLoop]: Abstraction has 28 states and 33 transitions. [2023-11-19 07:58:59,113 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 8 states. [2023-11-19 07:58:59,115 INFO L428 stractBuchiCegarLoop]: Abstraction has 28 states and 33 transitions. [2023-11-19 07:58:59,115 INFO L335 stractBuchiCegarLoop]: ======== Iteration 4 ============ [2023-11-19 07:58:59,115 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 28 states and 33 transitions. [2023-11-19 07:58:59,116 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 12 [2023-11-19 07:58:59,116 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-19 07:58:59,116 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-19 07:58:59,117 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [2, 2, 2, 1, 1, 1, 1, 1, 1] [2023-11-19 07:58:59,117 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1] [2023-11-19 07:58:59,121 INFO L748 eck$LassoCheckResult]: Stem: 399#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(18, 2); 384#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet1#1, main_#t~nondet3#1, main_#t~post2#1, main_#t~mem5#1, main_#t~mem6#1, main_#t~post4#1, main_#t~mem8#1, main_#t~mem9#1, main_#t~post7#1, main_~#array~0#1.base, main_~#array~0#1.offset, main_~i~0#1, main_~num~0#1;call main_~#array~0#1.base, main_~#array~0#1.offset := #Ultimate.allocOnStack(400000);havoc main_~i~0#1;havoc main_#t~nondet1#1;main_~num~0#1 := main_#t~nondet1#1;havoc main_#t~nondet1#1;main_~i~0#1 := 0; 385#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 397#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 398#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 390#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 391#L27-3 assume !(main_~i~0#1 < main_~num~0#1); 388#L27-4 main_~i~0#1 := 0; 389#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 403#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 392#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 393#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 396#L34 [2023-11-19 07:58:59,121 INFO L750 eck$LassoCheckResult]: Loop: 396#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 383#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 401#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 396#L34 [2023-11-19 07:58:59,122 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-19 07:58:59,122 INFO L85 PathProgramCache]: Analyzing trace with hash 780824429, now seen corresponding path program 2 times [2023-11-19 07:58:59,122 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-19 07:58:59,122 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [185783683] [2023-11-19 07:58:59,123 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-19 07:58:59,123 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-19 07:58:59,158 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-19 07:58:59,158 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-19 07:58:59,183 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-19 07:58:59,191 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-19 07:58:59,195 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-19 07:58:59,196 INFO L85 PathProgramCache]: Analyzing trace with hash 76501, now seen corresponding path program 3 times [2023-11-19 07:58:59,196 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-19 07:58:59,196 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1618333870] [2023-11-19 07:58:59,196 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-19 07:58:59,197 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-19 07:58:59,202 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-19 07:58:59,202 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-19 07:58:59,208 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-19 07:58:59,211 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-19 07:58:59,212 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-19 07:58:59,212 INFO L85 PathProgramCache]: Analyzing trace with hash -2264087, now seen corresponding path program 3 times [2023-11-19 07:58:59,212 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-19 07:58:59,212 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [449677220] [2023-11-19 07:58:59,213 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-19 07:58:59,213 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-19 07:58:59,239 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-19 07:58:59,389 INFO L134 CoverageAnalysis]: Checked inductivity of 9 backedges. 1 proven. 8 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-19 07:58:59,389 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-19 07:58:59,390 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [449677220] [2023-11-19 07:58:59,390 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [449677220] provided 0 perfect and 1 imperfect interpolant sequences [2023-11-19 07:58:59,390 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1919784962] [2023-11-19 07:58:59,390 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 [2023-11-19 07:58:59,391 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2023-11-19 07:58:59,391 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7bf958de-f854-47fc-9acd-69b8dc140d51/bin/uautomizer-verify-uCwYo4JHxu/z3 [2023-11-19 07:58:59,396 INFO L229 MonitoredProcess]: Starting monitored process 13 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7bf958de-f854-47fc-9acd-69b8dc140d51/bin/uautomizer-verify-uCwYo4JHxu/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2023-11-19 07:58:59,420 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7bf958de-f854-47fc-9acd-69b8dc140d51/bin/uautomizer-verify-uCwYo4JHxu/z3 -smt2 -in SMTLIB2_COMPLIANT=true (13)] Waiting until timeout for monitored process [2023-11-19 07:58:59,467 INFO L228 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 3 check-sat command(s) [2023-11-19 07:58:59,467 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2023-11-19 07:58:59,469 INFO L262 TraceCheckSpWp]: Trace formula consists of 83 conjuncts, 8 conjunts are in the unsatisfiable core [2023-11-19 07:58:59,471 INFO L285 TraceCheckSpWp]: Computing forward predicates... [2023-11-19 07:58:59,570 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7bf958de-f854-47fc-9acd-69b8dc140d51/bin/uautomizer-verify-uCwYo4JHxu/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (11)] Forceful destruction successful, exit code 0 [2023-11-19 07:58:59,605 INFO L134 CoverageAnalysis]: Checked inductivity of 9 backedges. 5 proven. 4 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-19 07:58:59,605 INFO L327 TraceCheckSpWp]: Computing backward predicates... [2023-11-19 07:58:59,670 INFO L134 CoverageAnalysis]: Checked inductivity of 9 backedges. 5 proven. 4 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-19 07:58:59,670 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1919784962] provided 0 perfect and 2 imperfect interpolant sequences [2023-11-19 07:58:59,671 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2023-11-19 07:58:59,671 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [8, 8, 8] total 13 [2023-11-19 07:58:59,671 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [225288318] [2023-11-19 07:58:59,671 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2023-11-19 07:58:59,731 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-19 07:58:59,731 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 14 interpolants. [2023-11-19 07:58:59,732 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=53, Invalid=129, Unknown=0, NotChecked=0, Total=182 [2023-11-19 07:58:59,732 INFO L87 Difference]: Start difference. First operand 28 states and 33 transitions. cyclomatic complexity: 8 Second operand has 14 states, 13 states have (on average 2.3076923076923075) internal successors, (30), 14 states have internal predecessors, (30), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-19 07:58:59,924 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-19 07:58:59,925 INFO L93 Difference]: Finished difference Result 89 states and 104 transitions. [2023-11-19 07:58:59,925 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 89 states and 104 transitions. [2023-11-19 07:58:59,927 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 12 [2023-11-19 07:58:59,928 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 89 states to 60 states and 70 transitions. [2023-11-19 07:58:59,928 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 53 [2023-11-19 07:58:59,928 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 53 [2023-11-19 07:58:59,929 INFO L73 IsDeterministic]: Start isDeterministic. Operand 60 states and 70 transitions. [2023-11-19 07:58:59,929 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-19 07:58:59,929 INFO L218 hiAutomatonCegarLoop]: Abstraction has 60 states and 70 transitions. [2023-11-19 07:58:59,930 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 60 states and 70 transitions. [2023-11-19 07:58:59,932 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 60 to 36. [2023-11-19 07:58:59,933 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 36 states, 36 states have (on average 1.1666666666666667) internal successors, (42), 35 states have internal predecessors, (42), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-19 07:58:59,933 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 36 states to 36 states and 42 transitions. [2023-11-19 07:58:59,934 INFO L240 hiAutomatonCegarLoop]: Abstraction has 36 states and 42 transitions. [2023-11-19 07:58:59,934 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 10 states. [2023-11-19 07:58:59,935 INFO L428 stractBuchiCegarLoop]: Abstraction has 36 states and 42 transitions. [2023-11-19 07:58:59,935 INFO L335 stractBuchiCegarLoop]: ======== Iteration 5 ============ [2023-11-19 07:58:59,935 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 36 states and 42 transitions. [2023-11-19 07:58:59,936 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 12 [2023-11-19 07:58:59,936 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-19 07:58:59,937 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-19 07:58:59,937 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [3, 3, 3, 2, 2, 1, 1, 1, 1] [2023-11-19 07:58:59,937 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1] [2023-11-19 07:58:59,938 INFO L748 eck$LassoCheckResult]: Stem: 626#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(18, 2); 610#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet1#1, main_#t~nondet3#1, main_#t~post2#1, main_#t~mem5#1, main_#t~mem6#1, main_#t~post4#1, main_#t~mem8#1, main_#t~mem9#1, main_#t~post7#1, main_~#array~0#1.base, main_~#array~0#1.offset, main_~i~0#1, main_~num~0#1;call main_~#array~0#1.base, main_~#array~0#1.offset := #Ultimate.allocOnStack(400000);havoc main_~i~0#1;havoc main_#t~nondet1#1;main_~num~0#1 := main_#t~nondet1#1;havoc main_#t~nondet1#1;main_~i~0#1 := 0; 611#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 624#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 625#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 614#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 615#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 630#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 629#L27-3 assume !(main_~i~0#1 < main_~num~0#1); 616#L27-4 main_~i~0#1 := 0; 617#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 638#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 618#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 619#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 623#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 632#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 637#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 622#L34 [2023-11-19 07:58:59,938 INFO L750 eck$LassoCheckResult]: Loop: 622#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 609#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 628#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 622#L34 [2023-11-19 07:58:59,938 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-19 07:58:59,938 INFO L85 PathProgramCache]: Analyzing trace with hash -79873369, now seen corresponding path program 4 times [2023-11-19 07:58:59,939 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-19 07:58:59,939 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [428754442] [2023-11-19 07:58:59,939 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-19 07:58:59,939 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-19 07:58:59,960 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-19 07:58:59,960 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-19 07:58:59,981 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-19 07:58:59,986 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-19 07:58:59,987 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-19 07:58:59,987 INFO L85 PathProgramCache]: Analyzing trace with hash 76501, now seen corresponding path program 4 times [2023-11-19 07:58:59,987 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-19 07:58:59,988 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2091341974] [2023-11-19 07:58:59,988 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-19 07:58:59,988 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-19 07:58:59,995 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-19 07:58:59,995 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-19 07:58:59,998 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-19 07:59:00,000 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-19 07:59:00,001 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-19 07:59:00,001 INFO L85 PathProgramCache]: Analyzing trace with hash -95607185, now seen corresponding path program 5 times [2023-11-19 07:59:00,001 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-19 07:59:00,001 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1691256805] [2023-11-19 07:59:00,002 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-19 07:59:00,002 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-19 07:59:00,016 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-19 07:59:00,187 INFO L134 CoverageAnalysis]: Checked inductivity of 21 backedges. 5 proven. 16 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-19 07:59:00,188 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-19 07:59:00,188 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1691256805] [2023-11-19 07:59:00,188 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1691256805] provided 0 perfect and 1 imperfect interpolant sequences [2023-11-19 07:59:00,188 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1765515336] [2023-11-19 07:59:00,189 INFO L93 rtionOrderModulation]: Changing assertion order to INSIDE_LOOP_FIRST1 [2023-11-19 07:59:00,189 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2023-11-19 07:59:00,189 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7bf958de-f854-47fc-9acd-69b8dc140d51/bin/uautomizer-verify-uCwYo4JHxu/z3 [2023-11-19 07:59:00,190 INFO L229 MonitoredProcess]: Starting monitored process 14 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7bf958de-f854-47fc-9acd-69b8dc140d51/bin/uautomizer-verify-uCwYo4JHxu/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2023-11-19 07:59:00,205 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7bf958de-f854-47fc-9acd-69b8dc140d51/bin/uautomizer-verify-uCwYo4JHxu/z3 -smt2 -in SMTLIB2_COMPLIANT=true (14)] Waiting until timeout for monitored process [2023-11-19 07:59:00,268 INFO L228 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 4 check-sat command(s) [2023-11-19 07:59:00,268 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2023-11-19 07:59:00,269 INFO L262 TraceCheckSpWp]: Trace formula consists of 104 conjuncts, 10 conjunts are in the unsatisfiable core [2023-11-19 07:59:00,271 INFO L285 TraceCheckSpWp]: Computing forward predicates... [2023-11-19 07:59:00,400 INFO L134 CoverageAnalysis]: Checked inductivity of 21 backedges. 12 proven. 9 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-19 07:59:00,400 INFO L327 TraceCheckSpWp]: Computing backward predicates... [2023-11-19 07:59:00,502 INFO L134 CoverageAnalysis]: Checked inductivity of 21 backedges. 12 proven. 9 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-19 07:59:00,503 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1765515336] provided 0 perfect and 2 imperfect interpolant sequences [2023-11-19 07:59:00,505 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2023-11-19 07:59:00,505 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [10, 10, 10] total 16 [2023-11-19 07:59:00,508 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [189515537] [2023-11-19 07:59:00,508 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2023-11-19 07:59:00,564 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-19 07:59:00,565 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 17 interpolants. [2023-11-19 07:59:00,565 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=75, Invalid=197, Unknown=0, NotChecked=0, Total=272 [2023-11-19 07:59:00,567 INFO L87 Difference]: Start difference. First operand 36 states and 42 transitions. cyclomatic complexity: 9 Second operand has 17 states, 16 states have (on average 2.375) internal successors, (38), 17 states have internal predecessors, (38), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-19 07:59:00,803 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-19 07:59:00,803 INFO L93 Difference]: Finished difference Result 115 states and 134 transitions. [2023-11-19 07:59:00,803 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 115 states and 134 transitions. [2023-11-19 07:59:00,806 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 12 [2023-11-19 07:59:00,810 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 115 states to 74 states and 86 transitions. [2023-11-19 07:59:00,810 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 65 [2023-11-19 07:59:00,811 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 65 [2023-11-19 07:59:00,811 INFO L73 IsDeterministic]: Start isDeterministic. Operand 74 states and 86 transitions. [2023-11-19 07:59:00,813 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-19 07:59:00,813 INFO L218 hiAutomatonCegarLoop]: Abstraction has 74 states and 86 transitions. [2023-11-19 07:59:00,815 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 74 states and 86 transitions. [2023-11-19 07:59:00,822 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 74 to 44. [2023-11-19 07:59:00,822 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 44 states, 44 states have (on average 1.1590909090909092) internal successors, (51), 43 states have internal predecessors, (51), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-19 07:59:00,824 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 44 states to 44 states and 51 transitions. [2023-11-19 07:59:00,824 INFO L240 hiAutomatonCegarLoop]: Abstraction has 44 states and 51 transitions. [2023-11-19 07:59:00,825 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 12 states. [2023-11-19 07:59:00,827 INFO L428 stractBuchiCegarLoop]: Abstraction has 44 states and 51 transitions. [2023-11-19 07:59:00,827 INFO L335 stractBuchiCegarLoop]: ======== Iteration 6 ============ [2023-11-19 07:59:00,827 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 44 states and 51 transitions. [2023-11-19 07:59:00,828 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 12 [2023-11-19 07:59:00,828 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-19 07:59:00,828 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-19 07:59:00,829 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [4, 4, 4, 3, 3, 1, 1, 1, 1] [2023-11-19 07:59:00,829 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1] [2023-11-19 07:59:00,829 INFO L748 eck$LassoCheckResult]: Stem: 919#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(18, 2); 905#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet1#1, main_#t~nondet3#1, main_#t~post2#1, main_#t~mem5#1, main_#t~mem6#1, main_#t~post4#1, main_#t~mem8#1, main_#t~mem9#1, main_#t~post7#1, main_~#array~0#1.base, main_~#array~0#1.offset, main_~i~0#1, main_~num~0#1;call main_~#array~0#1.base, main_~#array~0#1.offset := #Ultimate.allocOnStack(400000);havoc main_~i~0#1;havoc main_#t~nondet1#1;main_~num~0#1 := main_#t~nondet1#1;havoc main_#t~nondet1#1;main_~i~0#1 := 0; 906#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 920#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 921#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 909#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 910#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 930#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 929#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 926#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 925#L27-3 assume !(main_~i~0#1 < main_~num~0#1); 911#L27-4 main_~i~0#1 := 0; 912#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 917#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 904#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 914#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 940#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 938#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 937#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 934#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 932#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 931#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 924#L34 [2023-11-19 07:59:00,829 INFO L750 eck$LassoCheckResult]: Loop: 924#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 927#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 923#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 924#L34 [2023-11-19 07:59:00,829 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-19 07:59:00,830 INFO L85 PathProgramCache]: Analyzing trace with hash 1712449137, now seen corresponding path program 6 times [2023-11-19 07:59:00,830 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-19 07:59:00,830 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [998200288] [2023-11-19 07:59:00,830 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-19 07:59:00,830 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-19 07:59:00,869 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-19 07:59:00,870 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-19 07:59:00,894 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-19 07:59:00,899 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-19 07:59:00,899 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-19 07:59:00,900 INFO L85 PathProgramCache]: Analyzing trace with hash 76501, now seen corresponding path program 5 times [2023-11-19 07:59:00,900 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-19 07:59:00,900 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [36437086] [2023-11-19 07:59:00,900 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-19 07:59:00,900 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-19 07:59:00,904 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-19 07:59:00,905 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-19 07:59:00,907 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-19 07:59:00,909 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-19 07:59:00,910 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-19 07:59:00,910 INFO L85 PathProgramCache]: Analyzing trace with hash -49254811, now seen corresponding path program 7 times [2023-11-19 07:59:00,910 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-19 07:59:00,910 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2131822476] [2023-11-19 07:59:00,910 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-19 07:59:00,911 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-19 07:59:00,926 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-19 07:59:01,151 INFO L134 CoverageAnalysis]: Checked inductivity of 38 backedges. 12 proven. 26 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-19 07:59:01,153 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-19 07:59:01,154 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2131822476] [2023-11-19 07:59:01,157 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2131822476] provided 0 perfect and 1 imperfect interpolant sequences [2023-11-19 07:59:01,157 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [108013891] [2023-11-19 07:59:01,158 INFO L93 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2023-11-19 07:59:01,158 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2023-11-19 07:59:01,158 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7bf958de-f854-47fc-9acd-69b8dc140d51/bin/uautomizer-verify-uCwYo4JHxu/z3 [2023-11-19 07:59:01,160 INFO L229 MonitoredProcess]: Starting monitored process 15 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7bf958de-f854-47fc-9acd-69b8dc140d51/bin/uautomizer-verify-uCwYo4JHxu/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2023-11-19 07:59:01,163 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7bf958de-f854-47fc-9acd-69b8dc140d51/bin/uautomizer-verify-uCwYo4JHxu/z3 -smt2 -in SMTLIB2_COMPLIANT=true (15)] Waiting until timeout for monitored process [2023-11-19 07:59:01,235 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-19 07:59:01,236 INFO L262 TraceCheckSpWp]: Trace formula consists of 125 conjuncts, 12 conjunts are in the unsatisfiable core [2023-11-19 07:59:01,238 INFO L285 TraceCheckSpWp]: Computing forward predicates... [2023-11-19 07:59:01,394 INFO L134 CoverageAnalysis]: Checked inductivity of 38 backedges. 22 proven. 16 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-19 07:59:01,395 INFO L327 TraceCheckSpWp]: Computing backward predicates... [2023-11-19 07:59:01,504 INFO L134 CoverageAnalysis]: Checked inductivity of 38 backedges. 22 proven. 16 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-19 07:59:01,505 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [108013891] provided 0 perfect and 2 imperfect interpolant sequences [2023-11-19 07:59:01,505 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2023-11-19 07:59:01,505 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [12, 12, 12] total 19 [2023-11-19 07:59:01,505 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [7334600] [2023-11-19 07:59:01,506 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2023-11-19 07:59:01,563 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-19 07:59:01,564 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 20 interpolants. [2023-11-19 07:59:01,565 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=101, Invalid=279, Unknown=0, NotChecked=0, Total=380 [2023-11-19 07:59:01,565 INFO L87 Difference]: Start difference. First operand 44 states and 51 transitions. cyclomatic complexity: 10 Second operand has 20 states, 19 states have (on average 2.4210526315789473) internal successors, (46), 20 states have internal predecessors, (46), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-19 07:59:01,820 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-19 07:59:01,820 INFO L93 Difference]: Finished difference Result 141 states and 164 transitions. [2023-11-19 07:59:01,820 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 141 states and 164 transitions. [2023-11-19 07:59:01,822 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 12 [2023-11-19 07:59:01,825 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 141 states to 88 states and 102 transitions. [2023-11-19 07:59:01,825 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 77 [2023-11-19 07:59:01,826 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 77 [2023-11-19 07:59:01,826 INFO L73 IsDeterministic]: Start isDeterministic. Operand 88 states and 102 transitions. [2023-11-19 07:59:01,832 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-19 07:59:01,832 INFO L218 hiAutomatonCegarLoop]: Abstraction has 88 states and 102 transitions. [2023-11-19 07:59:01,835 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 88 states and 102 transitions. [2023-11-19 07:59:01,840 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 88 to 52. [2023-11-19 07:59:01,841 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 52 states, 52 states have (on average 1.1538461538461537) internal successors, (60), 51 states have internal predecessors, (60), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-19 07:59:01,841 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 52 states to 52 states and 60 transitions. [2023-11-19 07:59:01,841 INFO L240 hiAutomatonCegarLoop]: Abstraction has 52 states and 60 transitions. [2023-11-19 07:59:01,843 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 14 states. [2023-11-19 07:59:01,846 INFO L428 stractBuchiCegarLoop]: Abstraction has 52 states and 60 transitions. [2023-11-19 07:59:01,846 INFO L335 stractBuchiCegarLoop]: ======== Iteration 7 ============ [2023-11-19 07:59:01,846 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 52 states and 60 transitions. [2023-11-19 07:59:01,847 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 12 [2023-11-19 07:59:01,847 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-19 07:59:01,847 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-19 07:59:01,848 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [5, 5, 5, 4, 4, 1, 1, 1, 1] [2023-11-19 07:59:01,848 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1] [2023-11-19 07:59:01,848 INFO L748 eck$LassoCheckResult]: Stem: 1284#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(18, 2); 1269#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet1#1, main_#t~nondet3#1, main_#t~post2#1, main_#t~mem5#1, main_#t~mem6#1, main_#t~post4#1, main_#t~mem8#1, main_#t~mem9#1, main_#t~post7#1, main_~#array~0#1.base, main_~#array~0#1.offset, main_~i~0#1, main_~num~0#1;call main_~#array~0#1.base, main_~#array~0#1.offset := #Ultimate.allocOnStack(400000);havoc main_~i~0#1;havoc main_#t~nondet1#1;main_~num~0#1 := main_#t~nondet1#1;havoc main_#t~nondet1#1;main_~i~0#1 := 0; 1270#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 1285#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 1286#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 1273#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 1274#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 1297#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 1296#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 1295#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 1294#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 1291#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 1290#L27-3 assume !(main_~i~0#1 < main_~num~0#1); 1275#L27-4 main_~i~0#1 := 0; 1276#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 1281#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 1268#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 1278#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 1283#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 1311#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 1310#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 1307#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 1305#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 1304#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 1301#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 1299#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 1298#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 1289#L34 [2023-11-19 07:59:01,849 INFO L750 eck$LassoCheckResult]: Loop: 1289#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 1292#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 1288#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 1289#L34 [2023-11-19 07:59:01,849 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-19 07:59:01,849 INFO L85 PathProgramCache]: Analyzing trace with hash -240296029, now seen corresponding path program 8 times [2023-11-19 07:59:01,849 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-19 07:59:01,849 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1846671671] [2023-11-19 07:59:01,850 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-19 07:59:01,850 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-19 07:59:01,896 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-19 07:59:01,896 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-19 07:59:01,943 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-19 07:59:01,948 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-19 07:59:01,948 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-19 07:59:01,949 INFO L85 PathProgramCache]: Analyzing trace with hash 76501, now seen corresponding path program 6 times [2023-11-19 07:59:01,949 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-19 07:59:01,949 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [519393093] [2023-11-19 07:59:01,949 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-19 07:59:01,949 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-19 07:59:01,953 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-19 07:59:01,953 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-19 07:59:01,955 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-19 07:59:01,956 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-19 07:59:01,957 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-19 07:59:01,957 INFO L85 PathProgramCache]: Analyzing trace with hash 1051529203, now seen corresponding path program 9 times [2023-11-19 07:59:01,957 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-19 07:59:01,957 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [177273501] [2023-11-19 07:59:01,958 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-19 07:59:01,958 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-19 07:59:01,975 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-19 07:59:02,286 INFO L134 CoverageAnalysis]: Checked inductivity of 60 backedges. 22 proven. 38 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-19 07:59:02,286 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-19 07:59:02,287 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [177273501] [2023-11-19 07:59:02,287 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [177273501] provided 0 perfect and 1 imperfect interpolant sequences [2023-11-19 07:59:02,287 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1223942223] [2023-11-19 07:59:02,287 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 [2023-11-19 07:59:02,287 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2023-11-19 07:59:02,288 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7bf958de-f854-47fc-9acd-69b8dc140d51/bin/uautomizer-verify-uCwYo4JHxu/z3 [2023-11-19 07:59:02,292 INFO L229 MonitoredProcess]: Starting monitored process 16 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7bf958de-f854-47fc-9acd-69b8dc140d51/bin/uautomizer-verify-uCwYo4JHxu/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2023-11-19 07:59:02,307 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7bf958de-f854-47fc-9acd-69b8dc140d51/bin/uautomizer-verify-uCwYo4JHxu/z3 -smt2 -in SMTLIB2_COMPLIANT=true (16)] Waiting until timeout for monitored process [2023-11-19 07:59:02,396 INFO L228 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 6 check-sat command(s) [2023-11-19 07:59:02,396 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2023-11-19 07:59:02,398 INFO L262 TraceCheckSpWp]: Trace formula consists of 146 conjuncts, 14 conjunts are in the unsatisfiable core [2023-11-19 07:59:02,400 INFO L285 TraceCheckSpWp]: Computing forward predicates... [2023-11-19 07:59:02,598 INFO L134 CoverageAnalysis]: Checked inductivity of 60 backedges. 35 proven. 25 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-19 07:59:02,598 INFO L327 TraceCheckSpWp]: Computing backward predicates... [2023-11-19 07:59:02,741 INFO L134 CoverageAnalysis]: Checked inductivity of 60 backedges. 35 proven. 25 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-19 07:59:02,741 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1223942223] provided 0 perfect and 2 imperfect interpolant sequences [2023-11-19 07:59:02,741 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2023-11-19 07:59:02,742 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [14, 14, 14] total 22 [2023-11-19 07:59:02,743 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [596158012] [2023-11-19 07:59:02,743 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2023-11-19 07:59:02,792 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-19 07:59:02,793 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 23 interpolants. [2023-11-19 07:59:02,793 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=131, Invalid=375, Unknown=0, NotChecked=0, Total=506 [2023-11-19 07:59:02,794 INFO L87 Difference]: Start difference. First operand 52 states and 60 transitions. cyclomatic complexity: 11 Second operand has 23 states, 22 states have (on average 2.4545454545454546) internal successors, (54), 23 states have internal predecessors, (54), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-19 07:59:03,074 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-19 07:59:03,074 INFO L93 Difference]: Finished difference Result 167 states and 194 transitions. [2023-11-19 07:59:03,074 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 167 states and 194 transitions. [2023-11-19 07:59:03,076 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 12 [2023-11-19 07:59:03,077 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 167 states to 102 states and 118 transitions. [2023-11-19 07:59:03,077 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 89 [2023-11-19 07:59:03,077 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 89 [2023-11-19 07:59:03,078 INFO L73 IsDeterministic]: Start isDeterministic. Operand 102 states and 118 transitions. [2023-11-19 07:59:03,079 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-19 07:59:03,079 INFO L218 hiAutomatonCegarLoop]: Abstraction has 102 states and 118 transitions. [2023-11-19 07:59:03,081 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 102 states and 118 transitions. [2023-11-19 07:59:03,095 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 102 to 60. [2023-11-19 07:59:03,096 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 60 states, 60 states have (on average 1.15) internal successors, (69), 59 states have internal predecessors, (69), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-19 07:59:03,097 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 60 states to 60 states and 69 transitions. [2023-11-19 07:59:03,097 INFO L240 hiAutomatonCegarLoop]: Abstraction has 60 states and 69 transitions. [2023-11-19 07:59:03,098 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 16 states. [2023-11-19 07:59:03,100 INFO L428 stractBuchiCegarLoop]: Abstraction has 60 states and 69 transitions. [2023-11-19 07:59:03,100 INFO L335 stractBuchiCegarLoop]: ======== Iteration 8 ============ [2023-11-19 07:59:03,100 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 60 states and 69 transitions. [2023-11-19 07:59:03,101 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 12 [2023-11-19 07:59:03,101 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-19 07:59:03,101 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-19 07:59:03,103 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [6, 6, 6, 5, 5, 1, 1, 1, 1] [2023-11-19 07:59:03,103 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1] [2023-11-19 07:59:03,103 INFO L748 eck$LassoCheckResult]: Stem: 1718#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(18, 2); 1702#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet1#1, main_#t~nondet3#1, main_#t~post2#1, main_#t~mem5#1, main_#t~mem6#1, main_#t~post4#1, main_#t~mem8#1, main_#t~mem9#1, main_#t~post7#1, main_~#array~0#1.base, main_~#array~0#1.offset, main_~i~0#1, main_~num~0#1;call main_~#array~0#1.base, main_~#array~0#1.offset := #Ultimate.allocOnStack(400000);havoc main_~i~0#1;havoc main_#t~nondet1#1;main_~num~0#1 := main_#t~nondet1#1;havoc main_#t~nondet1#1;main_~i~0#1 := 0; 1703#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 1719#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 1720#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 1708#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 1709#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 1733#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 1732#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 1731#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 1730#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 1729#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 1728#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 1725#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 1724#L27-3 assume !(main_~i~0#1 < main_~num~0#1); 1706#L27-4 main_~i~0#1 := 0; 1707#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 1715#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 1701#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 1712#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 1717#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 1753#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 1751#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 1749#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 1747#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 1745#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 1743#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 1741#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 1739#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 1737#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 1735#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 1734#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 1723#L34 [2023-11-19 07:59:03,104 INFO L750 eck$LassoCheckResult]: Loop: 1723#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 1726#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 1722#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 1723#L34 [2023-11-19 07:59:03,105 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-19 07:59:03,105 INFO L85 PathProgramCache]: Analyzing trace with hash 1967863157, now seen corresponding path program 10 times [2023-11-19 07:59:03,105 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-19 07:59:03,107 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1837946820] [2023-11-19 07:59:03,107 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-19 07:59:03,107 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-19 07:59:03,187 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-19 07:59:03,188 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-19 07:59:03,233 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-19 07:59:03,248 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-19 07:59:03,251 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-19 07:59:03,251 INFO L85 PathProgramCache]: Analyzing trace with hash 76501, now seen corresponding path program 7 times [2023-11-19 07:59:03,251 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-19 07:59:03,252 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1823293318] [2023-11-19 07:59:03,253 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-19 07:59:03,253 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-19 07:59:03,257 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-19 07:59:03,258 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-19 07:59:03,262 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-19 07:59:03,264 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-19 07:59:03,264 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-19 07:59:03,264 INFO L85 PathProgramCache]: Analyzing trace with hash -1692233503, now seen corresponding path program 11 times [2023-11-19 07:59:03,265 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-19 07:59:03,265 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [47347667] [2023-11-19 07:59:03,265 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-19 07:59:03,265 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-19 07:59:03,284 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-19 07:59:03,600 INFO L134 CoverageAnalysis]: Checked inductivity of 87 backedges. 35 proven. 52 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-19 07:59:03,600 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-19 07:59:03,600 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [47347667] [2023-11-19 07:59:03,601 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [47347667] provided 0 perfect and 1 imperfect interpolant sequences [2023-11-19 07:59:03,601 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [982212560] [2023-11-19 07:59:03,601 INFO L93 rtionOrderModulation]: Changing assertion order to INSIDE_LOOP_FIRST1 [2023-11-19 07:59:03,601 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2023-11-19 07:59:03,601 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7bf958de-f854-47fc-9acd-69b8dc140d51/bin/uautomizer-verify-uCwYo4JHxu/z3 [2023-11-19 07:59:03,604 INFO L229 MonitoredProcess]: Starting monitored process 17 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7bf958de-f854-47fc-9acd-69b8dc140d51/bin/uautomizer-verify-uCwYo4JHxu/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2023-11-19 07:59:03,632 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7bf958de-f854-47fc-9acd-69b8dc140d51/bin/uautomizer-verify-uCwYo4JHxu/z3 -smt2 -in SMTLIB2_COMPLIANT=true (17)] Waiting until timeout for monitored process [2023-11-19 07:59:03,749 INFO L228 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 7 check-sat command(s) [2023-11-19 07:59:03,749 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2023-11-19 07:59:03,751 INFO L262 TraceCheckSpWp]: Trace formula consists of 167 conjuncts, 16 conjunts are in the unsatisfiable core [2023-11-19 07:59:03,753 INFO L285 TraceCheckSpWp]: Computing forward predicates... [2023-11-19 07:59:03,986 INFO L134 CoverageAnalysis]: Checked inductivity of 87 backedges. 51 proven. 36 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-19 07:59:03,986 INFO L327 TraceCheckSpWp]: Computing backward predicates... [2023-11-19 07:59:04,162 INFO L134 CoverageAnalysis]: Checked inductivity of 87 backedges. 51 proven. 36 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-19 07:59:04,162 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [982212560] provided 0 perfect and 2 imperfect interpolant sequences [2023-11-19 07:59:04,162 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2023-11-19 07:59:04,162 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [16, 16, 16] total 25 [2023-11-19 07:59:04,163 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1737297743] [2023-11-19 07:59:04,163 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2023-11-19 07:59:04,211 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-19 07:59:04,212 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 26 interpolants. [2023-11-19 07:59:04,212 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=165, Invalid=485, Unknown=0, NotChecked=0, Total=650 [2023-11-19 07:59:04,213 INFO L87 Difference]: Start difference. First operand 60 states and 69 transitions. cyclomatic complexity: 12 Second operand has 26 states, 25 states have (on average 2.48) internal successors, (62), 26 states have internal predecessors, (62), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-19 07:59:04,566 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-19 07:59:04,566 INFO L93 Difference]: Finished difference Result 193 states and 224 transitions. [2023-11-19 07:59:04,566 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 193 states and 224 transitions. [2023-11-19 07:59:04,568 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 12 [2023-11-19 07:59:04,569 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 193 states to 116 states and 134 transitions. [2023-11-19 07:59:04,570 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 101 [2023-11-19 07:59:04,570 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 101 [2023-11-19 07:59:04,570 INFO L73 IsDeterministic]: Start isDeterministic. Operand 116 states and 134 transitions. [2023-11-19 07:59:04,570 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-19 07:59:04,570 INFO L218 hiAutomatonCegarLoop]: Abstraction has 116 states and 134 transitions. [2023-11-19 07:59:04,570 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 116 states and 134 transitions. [2023-11-19 07:59:04,573 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 116 to 68. [2023-11-19 07:59:04,573 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 68 states, 68 states have (on average 1.1470588235294117) internal successors, (78), 67 states have internal predecessors, (78), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-19 07:59:04,574 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 68 states to 68 states and 78 transitions. [2023-11-19 07:59:04,574 INFO L240 hiAutomatonCegarLoop]: Abstraction has 68 states and 78 transitions. [2023-11-19 07:59:04,575 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 18 states. [2023-11-19 07:59:04,576 INFO L428 stractBuchiCegarLoop]: Abstraction has 68 states and 78 transitions. [2023-11-19 07:59:04,576 INFO L335 stractBuchiCegarLoop]: ======== Iteration 9 ============ [2023-11-19 07:59:04,576 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 68 states and 78 transitions. [2023-11-19 07:59:04,577 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 12 [2023-11-19 07:59:04,577 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-19 07:59:04,577 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-19 07:59:04,578 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [7, 7, 7, 6, 6, 1, 1, 1, 1] [2023-11-19 07:59:04,578 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1] [2023-11-19 07:59:04,578 INFO L748 eck$LassoCheckResult]: Stem: 2220#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(18, 2); 2204#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet1#1, main_#t~nondet3#1, main_#t~post2#1, main_#t~mem5#1, main_#t~mem6#1, main_#t~post4#1, main_#t~mem8#1, main_#t~mem9#1, main_#t~post7#1, main_~#array~0#1.base, main_~#array~0#1.offset, main_~i~0#1, main_~num~0#1;call main_~#array~0#1.base, main_~#array~0#1.offset := #Ultimate.allocOnStack(400000);havoc main_~i~0#1;havoc main_#t~nondet1#1;main_~num~0#1 := main_#t~nondet1#1;havoc main_#t~nondet1#1;main_~i~0#1 := 0; 2205#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 2221#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 2222#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 2208#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 2209#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 2237#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 2236#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 2235#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 2234#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 2233#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 2232#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 2231#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 2230#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 2227#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 2226#L27-3 assume !(main_~i~0#1 < main_~num~0#1); 2210#L27-4 main_~i~0#1 := 0; 2211#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 2217#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 2203#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 2214#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 2219#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 2262#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 2261#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 2259#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 2256#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 2255#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 2253#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 2250#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 2249#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 2247#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 2245#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 2244#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 2241#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 2239#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 2238#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 2225#L34 [2023-11-19 07:59:04,579 INFO L750 eck$LassoCheckResult]: Loop: 2225#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 2228#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 2224#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 2225#L34 [2023-11-19 07:59:04,579 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-19 07:59:04,579 INFO L85 PathProgramCache]: Analyzing trace with hash -664171361, now seen corresponding path program 12 times [2023-11-19 07:59:04,579 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-19 07:59:04,580 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [563549303] [2023-11-19 07:59:04,580 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-19 07:59:04,580 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-19 07:59:04,607 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-19 07:59:04,608 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-19 07:59:04,637 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-19 07:59:04,643 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-19 07:59:04,644 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-19 07:59:04,644 INFO L85 PathProgramCache]: Analyzing trace with hash 76501, now seen corresponding path program 8 times [2023-11-19 07:59:04,644 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-19 07:59:04,644 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2023739329] [2023-11-19 07:59:04,644 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-19 07:59:04,645 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-19 07:59:04,648 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-19 07:59:04,648 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-19 07:59:04,650 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-19 07:59:04,651 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-19 07:59:04,652 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-19 07:59:04,652 INFO L85 PathProgramCache]: Analyzing trace with hash 585363831, now seen corresponding path program 13 times [2023-11-19 07:59:04,652 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-19 07:59:04,653 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [548661280] [2023-11-19 07:59:04,653 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-19 07:59:04,653 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-19 07:59:04,695 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-19 07:59:05,071 INFO L134 CoverageAnalysis]: Checked inductivity of 119 backedges. 51 proven. 68 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-19 07:59:05,071 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-19 07:59:05,071 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [548661280] [2023-11-19 07:59:05,072 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [548661280] provided 0 perfect and 1 imperfect interpolant sequences [2023-11-19 07:59:05,072 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [875195724] [2023-11-19 07:59:05,072 INFO L93 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2023-11-19 07:59:05,072 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2023-11-19 07:59:05,072 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7bf958de-f854-47fc-9acd-69b8dc140d51/bin/uautomizer-verify-uCwYo4JHxu/z3 [2023-11-19 07:59:05,074 INFO L229 MonitoredProcess]: Starting monitored process 18 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7bf958de-f854-47fc-9acd-69b8dc140d51/bin/uautomizer-verify-uCwYo4JHxu/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2023-11-19 07:59:05,096 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7bf958de-f854-47fc-9acd-69b8dc140d51/bin/uautomizer-verify-uCwYo4JHxu/z3 -smt2 -in SMTLIB2_COMPLIANT=true (18)] Waiting until timeout for monitored process [2023-11-19 07:59:05,172 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-19 07:59:05,174 INFO L262 TraceCheckSpWp]: Trace formula consists of 188 conjuncts, 18 conjunts are in the unsatisfiable core [2023-11-19 07:59:05,176 INFO L285 TraceCheckSpWp]: Computing forward predicates... [2023-11-19 07:59:05,451 INFO L134 CoverageAnalysis]: Checked inductivity of 119 backedges. 70 proven. 49 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-19 07:59:05,452 INFO L327 TraceCheckSpWp]: Computing backward predicates... [2023-11-19 07:59:05,698 INFO L134 CoverageAnalysis]: Checked inductivity of 119 backedges. 70 proven. 49 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-19 07:59:05,698 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [875195724] provided 0 perfect and 2 imperfect interpolant sequences [2023-11-19 07:59:05,698 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2023-11-19 07:59:05,699 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [18, 18, 18] total 28 [2023-11-19 07:59:05,699 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [679497558] [2023-11-19 07:59:05,699 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2023-11-19 07:59:05,755 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-19 07:59:05,756 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 29 interpolants. [2023-11-19 07:59:05,756 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=203, Invalid=609, Unknown=0, NotChecked=0, Total=812 [2023-11-19 07:59:05,757 INFO L87 Difference]: Start difference. First operand 68 states and 78 transitions. cyclomatic complexity: 13 Second operand has 29 states, 28 states have (on average 2.5) internal successors, (70), 29 states have internal predecessors, (70), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-19 07:59:06,168 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-19 07:59:06,168 INFO L93 Difference]: Finished difference Result 219 states and 254 transitions. [2023-11-19 07:59:06,168 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 219 states and 254 transitions. [2023-11-19 07:59:06,170 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 12 [2023-11-19 07:59:06,171 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 219 states to 130 states and 150 transitions. [2023-11-19 07:59:06,172 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 113 [2023-11-19 07:59:06,172 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 113 [2023-11-19 07:59:06,172 INFO L73 IsDeterministic]: Start isDeterministic. Operand 130 states and 150 transitions. [2023-11-19 07:59:06,172 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-19 07:59:06,172 INFO L218 hiAutomatonCegarLoop]: Abstraction has 130 states and 150 transitions. [2023-11-19 07:59:06,173 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 130 states and 150 transitions. [2023-11-19 07:59:06,175 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 130 to 76. [2023-11-19 07:59:06,177 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 76 states, 76 states have (on average 1.144736842105263) internal successors, (87), 75 states have internal predecessors, (87), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-19 07:59:06,179 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 76 states to 76 states and 87 transitions. [2023-11-19 07:59:06,179 INFO L240 hiAutomatonCegarLoop]: Abstraction has 76 states and 87 transitions. [2023-11-19 07:59:06,179 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 20 states. [2023-11-19 07:59:06,180 INFO L428 stractBuchiCegarLoop]: Abstraction has 76 states and 87 transitions. [2023-11-19 07:59:06,181 INFO L335 stractBuchiCegarLoop]: ======== Iteration 10 ============ [2023-11-19 07:59:06,181 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 76 states and 87 transitions. [2023-11-19 07:59:06,181 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 12 [2023-11-19 07:59:06,182 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-19 07:59:06,182 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-19 07:59:06,184 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [8, 8, 8, 7, 7, 1, 1, 1, 1] [2023-11-19 07:59:06,184 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1] [2023-11-19 07:59:06,185 INFO L748 eck$LassoCheckResult]: Stem: 2791#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(18, 2); 2775#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet1#1, main_#t~nondet3#1, main_#t~post2#1, main_#t~mem5#1, main_#t~mem6#1, main_#t~post4#1, main_#t~mem8#1, main_#t~mem9#1, main_#t~post7#1, main_~#array~0#1.base, main_~#array~0#1.offset, main_~i~0#1, main_~num~0#1;call main_~#array~0#1.base, main_~#array~0#1.offset := #Ultimate.allocOnStack(400000);havoc main_~i~0#1;havoc main_#t~nondet1#1;main_~num~0#1 := main_#t~nondet1#1;havoc main_#t~nondet1#1;main_~i~0#1 := 0; 2776#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 2792#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 2793#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 2779#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 2780#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 2810#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 2809#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 2808#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 2807#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 2806#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 2805#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 2804#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 2803#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 2802#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 2801#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 2798#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 2797#L27-3 assume !(main_~i~0#1 < main_~num~0#1); 2781#L27-4 main_~i~0#1 := 0; 2782#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 2788#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 2774#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 2785#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 2790#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 2841#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 2840#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 2838#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 2835#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 2834#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 2832#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 2829#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 2828#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 2826#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 2823#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 2822#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 2820#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 2818#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 2817#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 2814#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 2812#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 2811#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 2796#L34 [2023-11-19 07:59:06,185 INFO L750 eck$LassoCheckResult]: Loop: 2796#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 2799#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 2795#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 2796#L34 [2023-11-19 07:59:06,185 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-19 07:59:06,185 INFO L85 PathProgramCache]: Analyzing trace with hash -704996231, now seen corresponding path program 14 times [2023-11-19 07:59:06,186 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-19 07:59:06,186 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [762462117] [2023-11-19 07:59:06,186 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-19 07:59:06,186 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-19 07:59:06,243 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-19 07:59:06,243 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-19 07:59:06,280 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-19 07:59:06,287 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-19 07:59:06,287 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-19 07:59:06,288 INFO L85 PathProgramCache]: Analyzing trace with hash 76501, now seen corresponding path program 9 times [2023-11-19 07:59:06,288 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-19 07:59:06,288 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [406199168] [2023-11-19 07:59:06,288 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-19 07:59:06,288 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-19 07:59:06,292 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-19 07:59:06,292 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-19 07:59:06,294 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-19 07:59:06,296 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-19 07:59:06,296 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-19 07:59:06,296 INFO L85 PathProgramCache]: Analyzing trace with hash -152593571, now seen corresponding path program 15 times [2023-11-19 07:59:06,297 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-19 07:59:06,297 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1390735988] [2023-11-19 07:59:06,297 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-19 07:59:06,297 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-19 07:59:06,319 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-19 07:59:06,742 INFO L134 CoverageAnalysis]: Checked inductivity of 156 backedges. 70 proven. 86 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-19 07:59:06,742 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-19 07:59:06,742 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1390735988] [2023-11-19 07:59:06,742 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1390735988] provided 0 perfect and 1 imperfect interpolant sequences [2023-11-19 07:59:06,742 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [24758755] [2023-11-19 07:59:06,743 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 [2023-11-19 07:59:06,743 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2023-11-19 07:59:06,743 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7bf958de-f854-47fc-9acd-69b8dc140d51/bin/uautomizer-verify-uCwYo4JHxu/z3 [2023-11-19 07:59:06,744 INFO L229 MonitoredProcess]: Starting monitored process 19 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7bf958de-f854-47fc-9acd-69b8dc140d51/bin/uautomizer-verify-uCwYo4JHxu/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2023-11-19 07:59:06,746 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7bf958de-f854-47fc-9acd-69b8dc140d51/bin/uautomizer-verify-uCwYo4JHxu/z3 -smt2 -in SMTLIB2_COMPLIANT=true (19)] Waiting until timeout for monitored process [2023-11-19 07:59:06,900 INFO L228 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 9 check-sat command(s) [2023-11-19 07:59:06,900 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2023-11-19 07:59:06,902 INFO L262 TraceCheckSpWp]: Trace formula consists of 209 conjuncts, 20 conjunts are in the unsatisfiable core [2023-11-19 07:59:06,904 INFO L285 TraceCheckSpWp]: Computing forward predicates... [2023-11-19 07:59:07,291 INFO L134 CoverageAnalysis]: Checked inductivity of 156 backedges. 92 proven. 64 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-19 07:59:07,292 INFO L327 TraceCheckSpWp]: Computing backward predicates... [2023-11-19 07:59:07,572 INFO L134 CoverageAnalysis]: Checked inductivity of 156 backedges. 92 proven. 64 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-19 07:59:07,572 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [24758755] provided 0 perfect and 2 imperfect interpolant sequences [2023-11-19 07:59:07,572 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2023-11-19 07:59:07,573 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [20, 20, 20] total 31 [2023-11-19 07:59:07,573 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [662319832] [2023-11-19 07:59:07,573 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2023-11-19 07:59:07,631 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-19 07:59:07,632 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 32 interpolants. [2023-11-19 07:59:07,633 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=245, Invalid=747, Unknown=0, NotChecked=0, Total=992 [2023-11-19 07:59:07,633 INFO L87 Difference]: Start difference. First operand 76 states and 87 transitions. cyclomatic complexity: 14 Second operand has 32 states, 31 states have (on average 2.5161290322580645) internal successors, (78), 32 states have internal predecessors, (78), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-19 07:59:08,140 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-19 07:59:08,140 INFO L93 Difference]: Finished difference Result 245 states and 284 transitions. [2023-11-19 07:59:08,140 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 245 states and 284 transitions. [2023-11-19 07:59:08,143 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 12 [2023-11-19 07:59:08,144 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 245 states to 144 states and 166 transitions. [2023-11-19 07:59:08,144 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 125 [2023-11-19 07:59:08,144 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 125 [2023-11-19 07:59:08,144 INFO L73 IsDeterministic]: Start isDeterministic. Operand 144 states and 166 transitions. [2023-11-19 07:59:08,145 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-19 07:59:08,145 INFO L218 hiAutomatonCegarLoop]: Abstraction has 144 states and 166 transitions. [2023-11-19 07:59:08,145 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 144 states and 166 transitions. [2023-11-19 07:59:08,147 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 144 to 84. [2023-11-19 07:59:08,148 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 84 states, 84 states have (on average 1.1428571428571428) internal successors, (96), 83 states have internal predecessors, (96), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-19 07:59:08,148 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 84 states to 84 states and 96 transitions. [2023-11-19 07:59:08,148 INFO L240 hiAutomatonCegarLoop]: Abstraction has 84 states and 96 transitions. [2023-11-19 07:59:08,149 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 22 states. [2023-11-19 07:59:08,149 INFO L428 stractBuchiCegarLoop]: Abstraction has 84 states and 96 transitions. [2023-11-19 07:59:08,150 INFO L335 stractBuchiCegarLoop]: ======== Iteration 11 ============ [2023-11-19 07:59:08,150 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 84 states and 96 transitions. [2023-11-19 07:59:08,150 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 12 [2023-11-19 07:59:08,151 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-19 07:59:08,151 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-19 07:59:08,152 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [9, 9, 9, 8, 8, 1, 1, 1, 1] [2023-11-19 07:59:08,152 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1] [2023-11-19 07:59:08,152 INFO L748 eck$LassoCheckResult]: Stem: 3431#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(18, 2); 3415#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet1#1, main_#t~nondet3#1, main_#t~post2#1, main_#t~mem5#1, main_#t~mem6#1, main_#t~post4#1, main_#t~mem8#1, main_#t~mem9#1, main_#t~post7#1, main_~#array~0#1.base, main_~#array~0#1.offset, main_~i~0#1, main_~num~0#1;call main_~#array~0#1.base, main_~#array~0#1.offset := #Ultimate.allocOnStack(400000);havoc main_~i~0#1;havoc main_#t~nondet1#1;main_~num~0#1 := main_#t~nondet1#1;havoc main_#t~nondet1#1;main_~i~0#1 := 0; 3416#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 3432#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 3433#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 3419#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 3420#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 3452#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 3451#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 3450#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 3449#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 3448#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 3447#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 3446#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 3445#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 3444#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 3443#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 3442#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 3441#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 3438#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 3437#L27-3 assume !(main_~i~0#1 < main_~num~0#1); 3421#L27-4 main_~i~0#1 := 0; 3422#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 3428#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 3414#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 3425#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 3430#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 3489#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 3488#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 3486#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 3483#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 3482#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 3480#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 3477#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 3476#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 3474#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 3471#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 3470#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 3468#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 3465#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 3464#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 3462#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 3460#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 3459#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 3456#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 3454#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 3453#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 3436#L34 [2023-11-19 07:59:08,152 INFO L750 eck$LassoCheckResult]: Loop: 3436#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 3439#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 3435#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 3436#L34 [2023-11-19 07:59:08,153 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-19 07:59:08,153 INFO L85 PathProgramCache]: Analyzing trace with hash -1850900069, now seen corresponding path program 16 times [2023-11-19 07:59:08,153 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-19 07:59:08,153 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [716409156] [2023-11-19 07:59:08,153 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-19 07:59:08,154 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-19 07:59:08,218 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-19 07:59:08,219 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-19 07:59:08,266 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-19 07:59:08,274 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-19 07:59:08,274 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-19 07:59:08,275 INFO L85 PathProgramCache]: Analyzing trace with hash 76501, now seen corresponding path program 10 times [2023-11-19 07:59:08,275 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-19 07:59:08,275 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1490703409] [2023-11-19 07:59:08,275 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-19 07:59:08,275 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-19 07:59:08,279 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-19 07:59:08,279 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-19 07:59:08,281 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-19 07:59:08,283 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-19 07:59:08,284 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-19 07:59:08,284 INFO L85 PathProgramCache]: Analyzing trace with hash -1373762821, now seen corresponding path program 17 times [2023-11-19 07:59:08,284 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-19 07:59:08,284 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1807405161] [2023-11-19 07:59:08,284 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-19 07:59:08,285 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-19 07:59:08,308 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-19 07:59:08,889 INFO L134 CoverageAnalysis]: Checked inductivity of 198 backedges. 92 proven. 106 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-19 07:59:08,889 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-19 07:59:08,889 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1807405161] [2023-11-19 07:59:08,889 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1807405161] provided 0 perfect and 1 imperfect interpolant sequences [2023-11-19 07:59:08,889 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1897921016] [2023-11-19 07:59:08,889 INFO L93 rtionOrderModulation]: Changing assertion order to INSIDE_LOOP_FIRST1 [2023-11-19 07:59:08,890 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2023-11-19 07:59:08,890 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7bf958de-f854-47fc-9acd-69b8dc140d51/bin/uautomizer-verify-uCwYo4JHxu/z3 [2023-11-19 07:59:08,892 INFO L229 MonitoredProcess]: Starting monitored process 20 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7bf958de-f854-47fc-9acd-69b8dc140d51/bin/uautomizer-verify-uCwYo4JHxu/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2023-11-19 07:59:08,895 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7bf958de-f854-47fc-9acd-69b8dc140d51/bin/uautomizer-verify-uCwYo4JHxu/z3 -smt2 -in SMTLIB2_COMPLIANT=true (20)] Waiting until timeout for monitored process [2023-11-19 07:59:09,098 INFO L228 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 10 check-sat command(s) [2023-11-19 07:59:09,099 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2023-11-19 07:59:09,101 INFO L262 TraceCheckSpWp]: Trace formula consists of 230 conjuncts, 22 conjunts are in the unsatisfiable core [2023-11-19 07:59:09,104 INFO L285 TraceCheckSpWp]: Computing forward predicates... [2023-11-19 07:59:09,466 INFO L134 CoverageAnalysis]: Checked inductivity of 198 backedges. 117 proven. 81 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-19 07:59:09,466 INFO L327 TraceCheckSpWp]: Computing backward predicates... [2023-11-19 07:59:09,764 INFO L134 CoverageAnalysis]: Checked inductivity of 198 backedges. 117 proven. 81 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-19 07:59:09,764 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1897921016] provided 0 perfect and 2 imperfect interpolant sequences [2023-11-19 07:59:09,764 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2023-11-19 07:59:09,764 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [22, 22, 22] total 34 [2023-11-19 07:59:09,764 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1969214056] [2023-11-19 07:59:09,765 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2023-11-19 07:59:09,815 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-19 07:59:09,815 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 35 interpolants. [2023-11-19 07:59:09,816 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=291, Invalid=899, Unknown=0, NotChecked=0, Total=1190 [2023-11-19 07:59:09,816 INFO L87 Difference]: Start difference. First operand 84 states and 96 transitions. cyclomatic complexity: 15 Second operand has 35 states, 34 states have (on average 2.5294117647058822) internal successors, (86), 35 states have internal predecessors, (86), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-19 07:59:10,365 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-19 07:59:10,366 INFO L93 Difference]: Finished difference Result 271 states and 314 transitions. [2023-11-19 07:59:10,366 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 271 states and 314 transitions. [2023-11-19 07:59:10,368 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 12 [2023-11-19 07:59:10,370 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 271 states to 158 states and 182 transitions. [2023-11-19 07:59:10,370 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 137 [2023-11-19 07:59:10,370 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 137 [2023-11-19 07:59:10,371 INFO L73 IsDeterministic]: Start isDeterministic. Operand 158 states and 182 transitions. [2023-11-19 07:59:10,371 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-19 07:59:10,371 INFO L218 hiAutomatonCegarLoop]: Abstraction has 158 states and 182 transitions. [2023-11-19 07:59:10,371 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 158 states and 182 transitions. [2023-11-19 07:59:10,374 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 158 to 92. [2023-11-19 07:59:10,374 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 92 states, 92 states have (on average 1.141304347826087) internal successors, (105), 91 states have internal predecessors, (105), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-19 07:59:10,375 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 92 states to 92 states and 105 transitions. [2023-11-19 07:59:10,375 INFO L240 hiAutomatonCegarLoop]: Abstraction has 92 states and 105 transitions. [2023-11-19 07:59:10,379 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 24 states. [2023-11-19 07:59:10,380 INFO L428 stractBuchiCegarLoop]: Abstraction has 92 states and 105 transitions. [2023-11-19 07:59:10,380 INFO L335 stractBuchiCegarLoop]: ======== Iteration 12 ============ [2023-11-19 07:59:10,380 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 92 states and 105 transitions. [2023-11-19 07:59:10,381 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 12 [2023-11-19 07:59:10,381 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-19 07:59:10,381 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-19 07:59:10,385 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [10, 10, 10, 9, 9, 1, 1, 1, 1] [2023-11-19 07:59:10,386 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1] [2023-11-19 07:59:10,386 INFO L748 eck$LassoCheckResult]: Stem: 4142#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(18, 2); 4124#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet1#1, main_#t~nondet3#1, main_#t~post2#1, main_#t~mem5#1, main_#t~mem6#1, main_#t~post4#1, main_#t~mem8#1, main_#t~mem9#1, main_#t~post7#1, main_~#array~0#1.base, main_~#array~0#1.offset, main_~i~0#1, main_~num~0#1;call main_~#array~0#1.base, main_~#array~0#1.offset := #Ultimate.allocOnStack(400000);havoc main_~i~0#1;havoc main_#t~nondet1#1;main_~num~0#1 := main_#t~nondet1#1;havoc main_#t~nondet1#1;main_~i~0#1 := 0; 4125#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 4140#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 4141#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 4128#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 4129#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 4163#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 4162#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 4161#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 4160#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 4159#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 4158#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 4157#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 4156#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 4155#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 4154#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 4153#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 4152#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 4151#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 4150#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 4147#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 4146#L27-3 assume !(main_~i~0#1 < main_~num~0#1); 4130#L27-4 main_~i~0#1 := 0; 4131#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 4137#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 4123#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 4134#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 4139#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 4206#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 4205#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 4203#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 4200#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 4199#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 4197#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 4194#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 4193#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 4191#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 4188#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 4187#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 4185#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 4182#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 4181#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 4179#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 4176#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 4175#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 4173#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 4171#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 4170#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 4167#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 4165#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 4164#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 4145#L34 [2023-11-19 07:59:10,386 INFO L750 eck$LassoCheckResult]: Loop: 4145#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 4148#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 4144#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 4145#L34 [2023-11-19 07:59:10,386 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-19 07:59:10,387 INFO L85 PathProgramCache]: Analyzing trace with hash -354133123, now seen corresponding path program 18 times [2023-11-19 07:59:10,387 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-19 07:59:10,387 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1819493927] [2023-11-19 07:59:10,387 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-19 07:59:10,388 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-19 07:59:10,498 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-19 07:59:10,502 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-19 07:59:10,581 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-19 07:59:10,595 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-19 07:59:10,596 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-19 07:59:10,596 INFO L85 PathProgramCache]: Analyzing trace with hash 76501, now seen corresponding path program 11 times [2023-11-19 07:59:10,596 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-19 07:59:10,596 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [429543567] [2023-11-19 07:59:10,596 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-19 07:59:10,597 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-19 07:59:10,600 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-19 07:59:10,601 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-19 07:59:10,602 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-19 07:59:10,604 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-19 07:59:10,604 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-19 07:59:10,605 INFO L85 PathProgramCache]: Analyzing trace with hash -1540141607, now seen corresponding path program 19 times [2023-11-19 07:59:10,605 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-19 07:59:10,605 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2070061358] [2023-11-19 07:59:10,605 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-19 07:59:10,606 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-19 07:59:10,652 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-19 07:59:11,234 INFO L134 CoverageAnalysis]: Checked inductivity of 245 backedges. 117 proven. 128 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-19 07:59:11,235 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-19 07:59:11,235 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2070061358] [2023-11-19 07:59:11,235 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2070061358] provided 0 perfect and 1 imperfect interpolant sequences [2023-11-19 07:59:11,235 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [623196780] [2023-11-19 07:59:11,235 INFO L93 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2023-11-19 07:59:11,235 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2023-11-19 07:59:11,235 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7bf958de-f854-47fc-9acd-69b8dc140d51/bin/uautomizer-verify-uCwYo4JHxu/z3 [2023-11-19 07:59:11,240 INFO L229 MonitoredProcess]: Starting monitored process 21 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7bf958de-f854-47fc-9acd-69b8dc140d51/bin/uautomizer-verify-uCwYo4JHxu/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2023-11-19 07:59:11,264 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7bf958de-f854-47fc-9acd-69b8dc140d51/bin/uautomizer-verify-uCwYo4JHxu/z3 -smt2 -in SMTLIB2_COMPLIANT=true (21)] Waiting until timeout for monitored process [2023-11-19 07:59:11,367 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-19 07:59:11,369 INFO L262 TraceCheckSpWp]: Trace formula consists of 251 conjuncts, 24 conjunts are in the unsatisfiable core [2023-11-19 07:59:11,372 INFO L285 TraceCheckSpWp]: Computing forward predicates... [2023-11-19 07:59:11,830 INFO L134 CoverageAnalysis]: Checked inductivity of 245 backedges. 145 proven. 100 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-19 07:59:11,830 INFO L327 TraceCheckSpWp]: Computing backward predicates... [2023-11-19 07:59:12,171 INFO L134 CoverageAnalysis]: Checked inductivity of 245 backedges. 145 proven. 100 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-19 07:59:12,172 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [623196780] provided 0 perfect and 2 imperfect interpolant sequences [2023-11-19 07:59:12,172 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2023-11-19 07:59:12,172 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [24, 24, 24] total 37 [2023-11-19 07:59:12,172 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1060650304] [2023-11-19 07:59:12,172 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2023-11-19 07:59:12,234 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-19 07:59:12,234 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 38 interpolants. [2023-11-19 07:59:12,235 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=341, Invalid=1065, Unknown=0, NotChecked=0, Total=1406 [2023-11-19 07:59:12,235 INFO L87 Difference]: Start difference. First operand 92 states and 105 transitions. cyclomatic complexity: 16 Second operand has 38 states, 37 states have (on average 2.5405405405405403) internal successors, (94), 38 states have internal predecessors, (94), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-19 07:59:12,797 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-19 07:59:12,798 INFO L93 Difference]: Finished difference Result 297 states and 344 transitions. [2023-11-19 07:59:12,798 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 297 states and 344 transitions. [2023-11-19 07:59:12,801 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 12 [2023-11-19 07:59:12,802 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 297 states to 172 states and 198 transitions. [2023-11-19 07:59:12,802 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 149 [2023-11-19 07:59:12,803 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 149 [2023-11-19 07:59:12,803 INFO L73 IsDeterministic]: Start isDeterministic. Operand 172 states and 198 transitions. [2023-11-19 07:59:12,803 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-19 07:59:12,803 INFO L218 hiAutomatonCegarLoop]: Abstraction has 172 states and 198 transitions. [2023-11-19 07:59:12,804 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 172 states and 198 transitions. [2023-11-19 07:59:12,806 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 172 to 100. [2023-11-19 07:59:12,807 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 100 states, 100 states have (on average 1.14) internal successors, (114), 99 states have internal predecessors, (114), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-19 07:59:12,807 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 100 states to 100 states and 114 transitions. [2023-11-19 07:59:12,808 INFO L240 hiAutomatonCegarLoop]: Abstraction has 100 states and 114 transitions. [2023-11-19 07:59:12,810 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 26 states. [2023-11-19 07:59:12,810 INFO L428 stractBuchiCegarLoop]: Abstraction has 100 states and 114 transitions. [2023-11-19 07:59:12,811 INFO L335 stractBuchiCegarLoop]: ======== Iteration 13 ============ [2023-11-19 07:59:12,811 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 100 states and 114 transitions. [2023-11-19 07:59:12,812 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 12 [2023-11-19 07:59:12,812 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-19 07:59:12,812 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-19 07:59:12,813 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [11, 11, 11, 10, 10, 1, 1, 1, 1] [2023-11-19 07:59:12,813 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1] [2023-11-19 07:59:12,813 INFO L748 eck$LassoCheckResult]: Stem: 4918#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(18, 2); 4902#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet1#1, main_#t~nondet3#1, main_#t~post2#1, main_#t~mem5#1, main_#t~mem6#1, main_#t~post4#1, main_#t~mem8#1, main_#t~mem9#1, main_#t~post7#1, main_~#array~0#1.base, main_~#array~0#1.offset, main_~i~0#1, main_~num~0#1;call main_~#array~0#1.base, main_~#array~0#1.offset := #Ultimate.allocOnStack(400000);havoc main_~i~0#1;havoc main_#t~nondet1#1;main_~num~0#1 := main_#t~nondet1#1;havoc main_#t~nondet1#1;main_~i~0#1 := 0; 4903#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 4919#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 4920#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 4906#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 4907#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 4943#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 4942#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 4941#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 4940#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 4939#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 4938#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 4937#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 4936#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 4935#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 4934#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 4933#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 4932#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 4931#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 4930#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 4929#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 4928#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 4925#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 4924#L27-3 assume !(main_~i~0#1 < main_~num~0#1); 4908#L27-4 main_~i~0#1 := 0; 4909#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 4915#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 4901#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 4912#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 4917#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 4992#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 4991#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 4989#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 4986#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 4985#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 4983#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 4980#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 4979#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 4977#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 4974#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 4973#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 4971#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 4968#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 4967#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 4965#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 4962#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 4961#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 4959#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 4956#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 4955#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 4953#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 4951#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 4950#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 4947#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 4945#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 4944#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 4923#L34 [2023-11-19 07:59:12,814 INFO L750 eck$LassoCheckResult]: Loop: 4923#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 4926#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 4922#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 4923#L34 [2023-11-19 07:59:12,814 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-19 07:59:12,814 INFO L85 PathProgramCache]: Analyzing trace with hash -726335849, now seen corresponding path program 20 times [2023-11-19 07:59:12,815 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-19 07:59:12,815 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1380593568] [2023-11-19 07:59:12,815 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-19 07:59:12,815 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-19 07:59:12,869 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-19 07:59:12,870 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-19 07:59:12,915 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-19 07:59:12,923 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-19 07:59:12,924 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-19 07:59:12,924 INFO L85 PathProgramCache]: Analyzing trace with hash 76501, now seen corresponding path program 12 times [2023-11-19 07:59:12,924 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-19 07:59:12,925 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1430267228] [2023-11-19 07:59:12,925 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-19 07:59:12,925 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-19 07:59:12,928 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-19 07:59:12,929 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-19 07:59:12,931 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-19 07:59:12,933 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-19 07:59:12,933 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-19 07:59:12,934 INFO L85 PathProgramCache]: Analyzing trace with hash -225993601, now seen corresponding path program 21 times [2023-11-19 07:59:12,934 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-19 07:59:12,934 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [853285819] [2023-11-19 07:59:12,934 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-19 07:59:12,934 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-19 07:59:12,961 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-19 07:59:13,690 INFO L134 CoverageAnalysis]: Checked inductivity of 297 backedges. 145 proven. 152 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-19 07:59:13,690 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-19 07:59:13,690 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [853285819] [2023-11-19 07:59:13,691 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [853285819] provided 0 perfect and 1 imperfect interpolant sequences [2023-11-19 07:59:13,691 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1558845660] [2023-11-19 07:59:13,691 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 [2023-11-19 07:59:13,691 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2023-11-19 07:59:13,691 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7bf958de-f854-47fc-9acd-69b8dc140d51/bin/uautomizer-verify-uCwYo4JHxu/z3 [2023-11-19 07:59:13,693 INFO L229 MonitoredProcess]: Starting monitored process 22 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7bf958de-f854-47fc-9acd-69b8dc140d51/bin/uautomizer-verify-uCwYo4JHxu/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2023-11-19 07:59:13,716 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7bf958de-f854-47fc-9acd-69b8dc140d51/bin/uautomizer-verify-uCwYo4JHxu/z3 -smt2 -in SMTLIB2_COMPLIANT=true (22)] Waiting until timeout for monitored process [2023-11-19 07:59:14,098 INFO L228 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 12 check-sat command(s) [2023-11-19 07:59:14,098 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2023-11-19 07:59:14,101 INFO L262 TraceCheckSpWp]: Trace formula consists of 272 conjuncts, 26 conjunts are in the unsatisfiable core [2023-11-19 07:59:14,103 INFO L285 TraceCheckSpWp]: Computing forward predicates... [2023-11-19 07:59:14,588 INFO L134 CoverageAnalysis]: Checked inductivity of 297 backedges. 176 proven. 121 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-19 07:59:14,588 INFO L327 TraceCheckSpWp]: Computing backward predicates... [2023-11-19 07:59:14,974 INFO L134 CoverageAnalysis]: Checked inductivity of 297 backedges. 176 proven. 121 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-19 07:59:14,974 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1558845660] provided 0 perfect and 2 imperfect interpolant sequences [2023-11-19 07:59:14,974 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2023-11-19 07:59:14,974 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [26, 26, 26] total 40 [2023-11-19 07:59:14,975 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1668315778] [2023-11-19 07:59:14,975 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2023-11-19 07:59:15,032 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-19 07:59:15,033 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 41 interpolants. [2023-11-19 07:59:15,034 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=395, Invalid=1245, Unknown=0, NotChecked=0, Total=1640 [2023-11-19 07:59:15,034 INFO L87 Difference]: Start difference. First operand 100 states and 114 transitions. cyclomatic complexity: 17 Second operand has 41 states, 40 states have (on average 2.55) internal successors, (102), 41 states have internal predecessors, (102), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-19 07:59:15,688 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-19 07:59:15,688 INFO L93 Difference]: Finished difference Result 323 states and 374 transitions. [2023-11-19 07:59:15,688 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 323 states and 374 transitions. [2023-11-19 07:59:15,691 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 12 [2023-11-19 07:59:15,693 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 323 states to 186 states and 214 transitions. [2023-11-19 07:59:15,693 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 161 [2023-11-19 07:59:15,693 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 161 [2023-11-19 07:59:15,693 INFO L73 IsDeterministic]: Start isDeterministic. Operand 186 states and 214 transitions. [2023-11-19 07:59:15,693 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-19 07:59:15,693 INFO L218 hiAutomatonCegarLoop]: Abstraction has 186 states and 214 transitions. [2023-11-19 07:59:15,694 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 186 states and 214 transitions. [2023-11-19 07:59:15,695 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 186 to 108. [2023-11-19 07:59:15,696 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 108 states, 108 states have (on average 1.1388888888888888) internal successors, (123), 107 states have internal predecessors, (123), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-19 07:59:15,697 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 108 states to 108 states and 123 transitions. [2023-11-19 07:59:15,697 INFO L240 hiAutomatonCegarLoop]: Abstraction has 108 states and 123 transitions. [2023-11-19 07:59:15,697 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 28 states. [2023-11-19 07:59:15,698 INFO L428 stractBuchiCegarLoop]: Abstraction has 108 states and 123 transitions. [2023-11-19 07:59:15,698 INFO L335 stractBuchiCegarLoop]: ======== Iteration 14 ============ [2023-11-19 07:59:15,698 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 108 states and 123 transitions. [2023-11-19 07:59:15,699 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 12 [2023-11-19 07:59:15,699 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-19 07:59:15,699 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-19 07:59:15,700 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [12, 12, 12, 11, 11, 1, 1, 1, 1] [2023-11-19 07:59:15,700 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1] [2023-11-19 07:59:15,700 INFO L748 eck$LassoCheckResult]: Stem: 5765#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(18, 2); 5749#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet1#1, main_#t~nondet3#1, main_#t~post2#1, main_#t~mem5#1, main_#t~mem6#1, main_#t~post4#1, main_#t~mem8#1, main_#t~mem9#1, main_#t~post7#1, main_~#array~0#1.base, main_~#array~0#1.offset, main_~i~0#1, main_~num~0#1;call main_~#array~0#1.base, main_~#array~0#1.offset := #Ultimate.allocOnStack(400000);havoc main_~i~0#1;havoc main_#t~nondet1#1;main_~num~0#1 := main_#t~nondet1#1;havoc main_#t~nondet1#1;main_~i~0#1 := 0; 5750#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 5766#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 5767#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 5753#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 5754#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 5792#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 5791#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 5790#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 5789#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 5788#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 5787#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 5786#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 5785#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 5784#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 5783#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 5782#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 5781#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 5780#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 5779#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 5778#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 5777#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 5776#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 5775#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 5772#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 5771#L27-3 assume !(main_~i~0#1 < main_~num~0#1); 5755#L27-4 main_~i~0#1 := 0; 5756#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 5762#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 5748#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 5759#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 5764#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 5847#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 5846#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 5844#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 5841#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 5840#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 5838#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 5835#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 5834#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 5832#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 5829#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 5828#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 5826#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 5823#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 5822#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 5820#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 5817#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 5816#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 5814#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 5811#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 5810#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 5808#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 5805#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 5804#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 5802#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 5800#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 5799#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 5796#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 5794#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 5793#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 5770#L34 [2023-11-19 07:59:15,701 INFO L750 eck$LassoCheckResult]: Loop: 5770#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 5773#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 5769#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 5770#L34 [2023-11-19 07:59:15,701 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-19 07:59:15,701 INFO L85 PathProgramCache]: Analyzing trace with hash -2083736959, now seen corresponding path program 22 times [2023-11-19 07:59:15,701 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-19 07:59:15,702 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [333014475] [2023-11-19 07:59:15,702 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-19 07:59:15,702 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-19 07:59:15,762 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-19 07:59:15,762 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-19 07:59:15,822 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-19 07:59:15,830 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-19 07:59:15,831 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-19 07:59:15,831 INFO L85 PathProgramCache]: Analyzing trace with hash 76501, now seen corresponding path program 13 times [2023-11-19 07:59:15,831 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-19 07:59:15,831 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1942838914] [2023-11-19 07:59:15,831 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-19 07:59:15,832 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-19 07:59:15,835 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-19 07:59:15,835 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-19 07:59:15,837 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-19 07:59:15,839 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-19 07:59:15,839 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-19 07:59:15,839 INFO L85 PathProgramCache]: Analyzing trace with hash -1445369771, now seen corresponding path program 23 times [2023-11-19 07:59:15,840 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-19 07:59:15,840 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [56984099] [2023-11-19 07:59:15,840 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-19 07:59:15,840 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-19 07:59:15,866 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-19 07:59:16,594 INFO L134 CoverageAnalysis]: Checked inductivity of 354 backedges. 176 proven. 178 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-19 07:59:16,594 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-19 07:59:16,595 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [56984099] [2023-11-19 07:59:16,595 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [56984099] provided 0 perfect and 1 imperfect interpolant sequences [2023-11-19 07:59:16,595 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1175364212] [2023-11-19 07:59:16,595 INFO L93 rtionOrderModulation]: Changing assertion order to INSIDE_LOOP_FIRST1 [2023-11-19 07:59:16,595 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2023-11-19 07:59:16,595 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7bf958de-f854-47fc-9acd-69b8dc140d51/bin/uautomizer-verify-uCwYo4JHxu/z3 [2023-11-19 07:59:16,601 INFO L229 MonitoredProcess]: Starting monitored process 23 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7bf958de-f854-47fc-9acd-69b8dc140d51/bin/uautomizer-verify-uCwYo4JHxu/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2023-11-19 07:59:16,628 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7bf958de-f854-47fc-9acd-69b8dc140d51/bin/uautomizer-verify-uCwYo4JHxu/z3 -smt2 -in SMTLIB2_COMPLIANT=true (23)] Waiting until timeout for monitored process [2023-11-19 07:59:17,110 INFO L228 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 13 check-sat command(s) [2023-11-19 07:59:17,110 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2023-11-19 07:59:17,114 INFO L262 TraceCheckSpWp]: Trace formula consists of 293 conjuncts, 28 conjunts are in the unsatisfiable core [2023-11-19 07:59:17,116 INFO L285 TraceCheckSpWp]: Computing forward predicates... [2023-11-19 07:59:17,675 INFO L134 CoverageAnalysis]: Checked inductivity of 354 backedges. 210 proven. 144 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-19 07:59:17,675 INFO L327 TraceCheckSpWp]: Computing backward predicates... [2023-11-19 07:59:18,146 INFO L134 CoverageAnalysis]: Checked inductivity of 354 backedges. 210 proven. 144 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-19 07:59:18,148 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1175364212] provided 0 perfect and 2 imperfect interpolant sequences [2023-11-19 07:59:18,149 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2023-11-19 07:59:18,149 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [28, 28, 28] total 43 [2023-11-19 07:59:18,149 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1019085800] [2023-11-19 07:59:18,150 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2023-11-19 07:59:18,212 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-19 07:59:18,213 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 44 interpolants. [2023-11-19 07:59:18,214 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=453, Invalid=1439, Unknown=0, NotChecked=0, Total=1892 [2023-11-19 07:59:18,214 INFO L87 Difference]: Start difference. First operand 108 states and 123 transitions. cyclomatic complexity: 18 Second operand has 44 states, 43 states have (on average 2.558139534883721) internal successors, (110), 44 states have internal predecessors, (110), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-19 07:59:18,949 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-19 07:59:18,949 INFO L93 Difference]: Finished difference Result 349 states and 404 transitions. [2023-11-19 07:59:18,949 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 349 states and 404 transitions. [2023-11-19 07:59:18,952 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 12 [2023-11-19 07:59:18,953 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 349 states to 200 states and 230 transitions. [2023-11-19 07:59:18,954 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 173 [2023-11-19 07:59:18,954 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 173 [2023-11-19 07:59:18,954 INFO L73 IsDeterministic]: Start isDeterministic. Operand 200 states and 230 transitions. [2023-11-19 07:59:18,954 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-19 07:59:18,954 INFO L218 hiAutomatonCegarLoop]: Abstraction has 200 states and 230 transitions. [2023-11-19 07:59:18,955 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 200 states and 230 transitions. [2023-11-19 07:59:18,957 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 200 to 116. [2023-11-19 07:59:18,957 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 116 states, 116 states have (on average 1.1379310344827587) internal successors, (132), 115 states have internal predecessors, (132), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-19 07:59:18,958 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 116 states to 116 states and 132 transitions. [2023-11-19 07:59:18,958 INFO L240 hiAutomatonCegarLoop]: Abstraction has 116 states and 132 transitions. [2023-11-19 07:59:18,959 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 30 states. [2023-11-19 07:59:18,959 INFO L428 stractBuchiCegarLoop]: Abstraction has 116 states and 132 transitions. [2023-11-19 07:59:18,960 INFO L335 stractBuchiCegarLoop]: ======== Iteration 15 ============ [2023-11-19 07:59:18,960 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 116 states and 132 transitions. [2023-11-19 07:59:18,961 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 12 [2023-11-19 07:59:18,961 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-19 07:59:18,961 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-19 07:59:18,962 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [13, 13, 13, 12, 12, 1, 1, 1, 1] [2023-11-19 07:59:18,962 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1] [2023-11-19 07:59:18,962 INFO L748 eck$LassoCheckResult]: Stem: 6681#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(18, 2); 6665#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet1#1, main_#t~nondet3#1, main_#t~post2#1, main_#t~mem5#1, main_#t~mem6#1, main_#t~post4#1, main_#t~mem8#1, main_#t~mem9#1, main_#t~post7#1, main_~#array~0#1.base, main_~#array~0#1.offset, main_~i~0#1, main_~num~0#1;call main_~#array~0#1.base, main_~#array~0#1.offset := #Ultimate.allocOnStack(400000);havoc main_~i~0#1;havoc main_#t~nondet1#1;main_~num~0#1 := main_#t~nondet1#1;havoc main_#t~nondet1#1;main_~i~0#1 := 0; 6666#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 6682#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 6683#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 6669#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 6670#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 6710#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 6709#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 6708#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 6707#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 6706#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 6705#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 6704#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 6703#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 6702#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 6701#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 6700#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 6699#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 6698#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 6697#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 6696#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 6695#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 6694#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 6693#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 6692#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 6691#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 6688#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 6687#L27-3 assume !(main_~i~0#1 < main_~num~0#1); 6671#L27-4 main_~i~0#1 := 0; 6672#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 6678#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 6664#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 6675#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 6680#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 6771#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 6770#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 6768#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 6765#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 6764#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 6762#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 6759#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 6758#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 6756#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 6753#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 6752#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 6750#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 6747#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 6746#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 6744#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 6741#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 6740#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 6738#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 6735#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 6734#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 6732#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 6729#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 6728#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 6726#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 6723#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 6722#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 6720#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 6718#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 6717#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 6714#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 6712#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 6711#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 6686#L34 [2023-11-19 07:59:18,963 INFO L750 eck$LassoCheckResult]: Loop: 6686#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 6689#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 6685#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 6686#L34 [2023-11-19 07:59:18,963 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-19 07:59:18,963 INFO L85 PathProgramCache]: Analyzing trace with hash -1447312493, now seen corresponding path program 24 times [2023-11-19 07:59:18,963 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-19 07:59:18,964 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1030951542] [2023-11-19 07:59:18,964 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-19 07:59:18,964 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-19 07:59:19,052 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-19 07:59:19,052 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-19 07:59:19,126 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-19 07:59:19,136 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-19 07:59:19,136 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-19 07:59:19,136 INFO L85 PathProgramCache]: Analyzing trace with hash 76501, now seen corresponding path program 14 times [2023-11-19 07:59:19,137 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-19 07:59:19,137 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [661053918] [2023-11-19 07:59:19,137 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-19 07:59:19,137 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-19 07:59:19,141 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-19 07:59:19,141 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-19 07:59:19,143 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-19 07:59:19,145 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-19 07:59:19,145 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-19 07:59:19,146 INFO L85 PathProgramCache]: Analyzing trace with hash 290252291, now seen corresponding path program 25 times [2023-11-19 07:59:19,146 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-19 07:59:19,146 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [295119503] [2023-11-19 07:59:19,146 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-19 07:59:19,146 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-19 07:59:19,176 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-19 07:59:20,030 INFO L134 CoverageAnalysis]: Checked inductivity of 416 backedges. 210 proven. 206 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-19 07:59:20,030 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-19 07:59:20,031 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [295119503] [2023-11-19 07:59:20,031 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [295119503] provided 0 perfect and 1 imperfect interpolant sequences [2023-11-19 07:59:20,031 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [756905839] [2023-11-19 07:59:20,031 INFO L93 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2023-11-19 07:59:20,031 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2023-11-19 07:59:20,031 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7bf958de-f854-47fc-9acd-69b8dc140d51/bin/uautomizer-verify-uCwYo4JHxu/z3 [2023-11-19 07:59:20,034 INFO L229 MonitoredProcess]: Starting monitored process 24 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7bf958de-f854-47fc-9acd-69b8dc140d51/bin/uautomizer-verify-uCwYo4JHxu/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2023-11-19 07:59:20,040 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7bf958de-f854-47fc-9acd-69b8dc140d51/bin/uautomizer-verify-uCwYo4JHxu/z3 -smt2 -in SMTLIB2_COMPLIANT=true (24)] Waiting until timeout for monitored process [2023-11-19 07:59:20,196 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-19 07:59:20,198 INFO L262 TraceCheckSpWp]: Trace formula consists of 314 conjuncts, 30 conjunts are in the unsatisfiable core [2023-11-19 07:59:20,201 INFO L285 TraceCheckSpWp]: Computing forward predicates... [2023-11-19 07:59:20,767 INFO L134 CoverageAnalysis]: Checked inductivity of 416 backedges. 247 proven. 169 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-19 07:59:20,768 INFO L327 TraceCheckSpWp]: Computing backward predicates... [2023-11-19 07:59:21,225 INFO L134 CoverageAnalysis]: Checked inductivity of 416 backedges. 247 proven. 169 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-19 07:59:21,225 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [756905839] provided 0 perfect and 2 imperfect interpolant sequences [2023-11-19 07:59:21,225 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2023-11-19 07:59:21,225 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [30, 30, 30] total 46 [2023-11-19 07:59:21,226 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [268607529] [2023-11-19 07:59:21,226 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2023-11-19 07:59:21,275 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-19 07:59:21,275 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 47 interpolants. [2023-11-19 07:59:21,276 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=515, Invalid=1647, Unknown=0, NotChecked=0, Total=2162 [2023-11-19 07:59:21,277 INFO L87 Difference]: Start difference. First operand 116 states and 132 transitions. cyclomatic complexity: 19 Second operand has 47 states, 46 states have (on average 2.5652173913043477) internal successors, (118), 47 states have internal predecessors, (118), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-19 07:59:21,968 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-19 07:59:21,968 INFO L93 Difference]: Finished difference Result 375 states and 434 transitions. [2023-11-19 07:59:21,969 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 375 states and 434 transitions. [2023-11-19 07:59:21,974 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 12 [2023-11-19 07:59:21,976 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 375 states to 214 states and 246 transitions. [2023-11-19 07:59:21,976 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 185 [2023-11-19 07:59:21,977 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 185 [2023-11-19 07:59:21,977 INFO L73 IsDeterministic]: Start isDeterministic. Operand 214 states and 246 transitions. [2023-11-19 07:59:21,977 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-19 07:59:21,977 INFO L218 hiAutomatonCegarLoop]: Abstraction has 214 states and 246 transitions. [2023-11-19 07:59:21,978 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 214 states and 246 transitions. [2023-11-19 07:59:21,980 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 214 to 124. [2023-11-19 07:59:21,980 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 124 states, 124 states have (on average 1.1370967741935485) internal successors, (141), 123 states have internal predecessors, (141), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-19 07:59:21,981 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 124 states to 124 states and 141 transitions. [2023-11-19 07:59:21,982 INFO L240 hiAutomatonCegarLoop]: Abstraction has 124 states and 141 transitions. [2023-11-19 07:59:21,984 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 32 states. [2023-11-19 07:59:21,984 INFO L428 stractBuchiCegarLoop]: Abstraction has 124 states and 141 transitions. [2023-11-19 07:59:21,985 INFO L335 stractBuchiCegarLoop]: ======== Iteration 16 ============ [2023-11-19 07:59:21,985 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 124 states and 141 transitions. [2023-11-19 07:59:21,986 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 12 [2023-11-19 07:59:21,986 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-19 07:59:21,986 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-19 07:59:21,987 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [14, 14, 14, 13, 13, 1, 1, 1, 1] [2023-11-19 07:59:21,987 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1] [2023-11-19 07:59:21,987 INFO L748 eck$LassoCheckResult]: Stem: 7666#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(18, 2); 7650#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet1#1, main_#t~nondet3#1, main_#t~post2#1, main_#t~mem5#1, main_#t~mem6#1, main_#t~post4#1, main_#t~mem8#1, main_#t~mem9#1, main_#t~post7#1, main_~#array~0#1.base, main_~#array~0#1.offset, main_~i~0#1, main_~num~0#1;call main_~#array~0#1.base, main_~#array~0#1.offset := #Ultimate.allocOnStack(400000);havoc main_~i~0#1;havoc main_#t~nondet1#1;main_~num~0#1 := main_#t~nondet1#1;havoc main_#t~nondet1#1;main_~i~0#1 := 0; 7651#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 7667#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 7668#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 7654#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 7655#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 7697#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 7696#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 7695#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 7694#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 7693#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 7692#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 7691#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 7690#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 7689#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 7688#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 7687#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 7686#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 7685#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 7684#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 7683#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 7682#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 7681#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 7680#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 7679#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 7678#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 7677#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 7676#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 7673#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 7672#L27-3 assume !(main_~i~0#1 < main_~num~0#1); 7656#L27-4 main_~i~0#1 := 0; 7657#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 7663#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 7649#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 7660#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 7665#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 7764#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 7763#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 7761#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 7758#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 7757#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 7755#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 7752#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 7751#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 7749#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 7746#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 7745#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 7743#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 7740#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 7739#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 7737#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 7734#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 7733#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 7731#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 7728#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 7727#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 7725#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 7722#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 7721#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 7719#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 7716#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 7715#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 7713#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 7710#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 7709#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 7707#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 7705#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 7704#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 7701#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 7699#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 7698#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 7671#L34 [2023-11-19 07:59:21,987 INFO L750 eck$LassoCheckResult]: Loop: 7671#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 7674#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 7670#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 7671#L34 [2023-11-19 07:59:21,988 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-19 07:59:21,988 INFO L85 PathProgramCache]: Analyzing trace with hash 1635246469, now seen corresponding path program 26 times [2023-11-19 07:59:21,988 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-19 07:59:21,988 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1599017754] [2023-11-19 07:59:21,988 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-19 07:59:21,988 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-19 07:59:22,131 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-19 07:59:22,133 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-19 07:59:22,216 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-19 07:59:22,225 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-19 07:59:22,225 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-19 07:59:22,225 INFO L85 PathProgramCache]: Analyzing trace with hash 76501, now seen corresponding path program 15 times [2023-11-19 07:59:22,226 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-19 07:59:22,226 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1529652982] [2023-11-19 07:59:22,226 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-19 07:59:22,226 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-19 07:59:22,229 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-19 07:59:22,230 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-19 07:59:22,231 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-19 07:59:22,233 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-19 07:59:22,234 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-19 07:59:22,234 INFO L85 PathProgramCache]: Analyzing trace with hash 2108533457, now seen corresponding path program 27 times [2023-11-19 07:59:22,234 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-19 07:59:22,235 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2009048537] [2023-11-19 07:59:22,235 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-19 07:59:22,235 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-19 07:59:22,271 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-19 07:59:23,174 INFO L134 CoverageAnalysis]: Checked inductivity of 483 backedges. 247 proven. 236 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-19 07:59:23,174 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-19 07:59:23,174 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2009048537] [2023-11-19 07:59:23,174 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2009048537] provided 0 perfect and 1 imperfect interpolant sequences [2023-11-19 07:59:23,174 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1607821645] [2023-11-19 07:59:23,175 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 [2023-11-19 07:59:23,175 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2023-11-19 07:59:23,175 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7bf958de-f854-47fc-9acd-69b8dc140d51/bin/uautomizer-verify-uCwYo4JHxu/z3 [2023-11-19 07:59:23,180 INFO L229 MonitoredProcess]: Starting monitored process 25 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7bf958de-f854-47fc-9acd-69b8dc140d51/bin/uautomizer-verify-uCwYo4JHxu/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2023-11-19 07:59:23,204 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7bf958de-f854-47fc-9acd-69b8dc140d51/bin/uautomizer-verify-uCwYo4JHxu/z3 -smt2 -in SMTLIB2_COMPLIANT=true (25)] Waiting until timeout for monitored process [2023-11-19 07:59:23,744 INFO L228 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 15 check-sat command(s) [2023-11-19 07:59:23,744 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2023-11-19 07:59:23,748 INFO L262 TraceCheckSpWp]: Trace formula consists of 335 conjuncts, 32 conjunts are in the unsatisfiable core [2023-11-19 07:59:23,749 INFO L285 TraceCheckSpWp]: Computing forward predicates... [2023-11-19 07:59:24,446 INFO L134 CoverageAnalysis]: Checked inductivity of 483 backedges. 287 proven. 196 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-19 07:59:24,447 INFO L327 TraceCheckSpWp]: Computing backward predicates... [2023-11-19 07:59:24,974 INFO L134 CoverageAnalysis]: Checked inductivity of 483 backedges. 287 proven. 196 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-19 07:59:24,975 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1607821645] provided 0 perfect and 2 imperfect interpolant sequences [2023-11-19 07:59:24,975 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2023-11-19 07:59:24,975 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [32, 32, 32] total 49 [2023-11-19 07:59:24,975 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1339644379] [2023-11-19 07:59:24,976 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2023-11-19 07:59:25,030 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-19 07:59:25,031 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 50 interpolants. [2023-11-19 07:59:25,032 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=581, Invalid=1869, Unknown=0, NotChecked=0, Total=2450 [2023-11-19 07:59:25,033 INFO L87 Difference]: Start difference. First operand 124 states and 141 transitions. cyclomatic complexity: 20 Second operand has 50 states, 49 states have (on average 2.5714285714285716) internal successors, (126), 50 states have internal predecessors, (126), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-19 07:59:25,858 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-19 07:59:25,858 INFO L93 Difference]: Finished difference Result 401 states and 464 transitions. [2023-11-19 07:59:25,859 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 401 states and 464 transitions. [2023-11-19 07:59:25,862 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 12 [2023-11-19 07:59:25,864 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 401 states to 228 states and 262 transitions. [2023-11-19 07:59:25,864 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 197 [2023-11-19 07:59:25,864 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 197 [2023-11-19 07:59:25,864 INFO L73 IsDeterministic]: Start isDeterministic. Operand 228 states and 262 transitions. [2023-11-19 07:59:25,865 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-19 07:59:25,865 INFO L218 hiAutomatonCegarLoop]: Abstraction has 228 states and 262 transitions. [2023-11-19 07:59:25,865 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 228 states and 262 transitions. [2023-11-19 07:59:25,868 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 228 to 132. [2023-11-19 07:59:25,868 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 132 states, 132 states have (on average 1.1363636363636365) internal successors, (150), 131 states have internal predecessors, (150), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-19 07:59:25,869 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 132 states to 132 states and 150 transitions. [2023-11-19 07:59:25,869 INFO L240 hiAutomatonCegarLoop]: Abstraction has 132 states and 150 transitions. [2023-11-19 07:59:25,869 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 34 states. [2023-11-19 07:59:25,870 INFO L428 stractBuchiCegarLoop]: Abstraction has 132 states and 150 transitions. [2023-11-19 07:59:25,870 INFO L335 stractBuchiCegarLoop]: ======== Iteration 17 ============ [2023-11-19 07:59:25,870 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 132 states and 150 transitions. [2023-11-19 07:59:25,871 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 12 [2023-11-19 07:59:25,871 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-19 07:59:25,871 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-19 07:59:25,872 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [15, 15, 15, 14, 14, 1, 1, 1, 1] [2023-11-19 07:59:25,872 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1] [2023-11-19 07:59:25,873 INFO L748 eck$LassoCheckResult]: Stem: 8720#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(18, 2); 8704#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet1#1, main_#t~nondet3#1, main_#t~post2#1, main_#t~mem5#1, main_#t~mem6#1, main_#t~post4#1, main_#t~mem8#1, main_#t~mem9#1, main_#t~post7#1, main_~#array~0#1.base, main_~#array~0#1.offset, main_~i~0#1, main_~num~0#1;call main_~#array~0#1.base, main_~#array~0#1.offset := #Ultimate.allocOnStack(400000);havoc main_~i~0#1;havoc main_#t~nondet1#1;main_~num~0#1 := main_#t~nondet1#1;havoc main_#t~nondet1#1;main_~i~0#1 := 0; 8705#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 8721#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 8722#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 8708#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 8709#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 8753#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 8752#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 8751#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 8750#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 8749#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 8748#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 8747#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 8746#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 8745#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 8744#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 8743#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 8742#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 8741#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 8740#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 8739#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 8738#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 8737#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 8736#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 8735#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 8734#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 8733#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 8732#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 8731#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 8730#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 8727#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 8726#L27-3 assume !(main_~i~0#1 < main_~num~0#1); 8710#L27-4 main_~i~0#1 := 0; 8711#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 8717#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 8703#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 8714#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 8719#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 8826#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 8825#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 8823#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 8820#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 8819#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 8817#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 8814#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 8813#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 8811#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 8808#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 8807#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 8805#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 8802#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 8801#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 8799#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 8796#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 8795#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 8793#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 8790#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 8789#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 8787#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 8784#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 8783#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 8781#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 8778#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 8777#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 8775#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 8772#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 8771#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 8769#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 8766#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 8765#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 8763#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 8761#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 8760#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 8757#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 8755#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 8754#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 8725#L34 [2023-11-19 07:59:25,873 INFO L750 eck$LassoCheckResult]: Loop: 8725#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 8728#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 8724#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 8725#L34 [2023-11-19 07:59:25,873 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-19 07:59:25,873 INFO L85 PathProgramCache]: Analyzing trace with hash -436367217, now seen corresponding path program 28 times [2023-11-19 07:59:25,873 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-19 07:59:25,874 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [866599537] [2023-11-19 07:59:25,874 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-19 07:59:25,874 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-19 07:59:25,960 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-19 07:59:25,960 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-19 07:59:26,085 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-19 07:59:26,095 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-19 07:59:26,096 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-19 07:59:26,096 INFO L85 PathProgramCache]: Analyzing trace with hash 76501, now seen corresponding path program 16 times [2023-11-19 07:59:26,097 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-19 07:59:26,097 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1000749870] [2023-11-19 07:59:26,097 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-19 07:59:26,098 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-19 07:59:26,101 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-19 07:59:26,102 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-19 07:59:26,103 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-19 07:59:26,106 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-19 07:59:26,106 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-19 07:59:26,106 INFO L85 PathProgramCache]: Analyzing trace with hash 1050290055, now seen corresponding path program 29 times [2023-11-19 07:59:26,107 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-19 07:59:26,107 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1750926982] [2023-11-19 07:59:26,107 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-19 07:59:26,107 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-19 07:59:26,153 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-19 07:59:27,185 INFO L134 CoverageAnalysis]: Checked inductivity of 555 backedges. 287 proven. 268 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-19 07:59:27,186 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-19 07:59:27,186 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1750926982] [2023-11-19 07:59:27,186 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1750926982] provided 0 perfect and 1 imperfect interpolant sequences [2023-11-19 07:59:27,186 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [695675171] [2023-11-19 07:59:27,187 INFO L93 rtionOrderModulation]: Changing assertion order to INSIDE_LOOP_FIRST1 [2023-11-19 07:59:27,187 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2023-11-19 07:59:27,187 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7bf958de-f854-47fc-9acd-69b8dc140d51/bin/uautomizer-verify-uCwYo4JHxu/z3 [2023-11-19 07:59:27,194 INFO L229 MonitoredProcess]: Starting monitored process 26 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7bf958de-f854-47fc-9acd-69b8dc140d51/bin/uautomizer-verify-uCwYo4JHxu/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2023-11-19 07:59:27,200 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7bf958de-f854-47fc-9acd-69b8dc140d51/bin/uautomizer-verify-uCwYo4JHxu/z3 -smt2 -in SMTLIB2_COMPLIANT=true (26)] Waiting until timeout for monitored process [2023-11-19 07:59:27,781 INFO L228 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 16 check-sat command(s) [2023-11-19 07:59:27,781 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2023-11-19 07:59:27,785 INFO L262 TraceCheckSpWp]: Trace formula consists of 356 conjuncts, 34 conjunts are in the unsatisfiable core [2023-11-19 07:59:27,793 INFO L285 TraceCheckSpWp]: Computing forward predicates... [2023-11-19 07:59:28,747 INFO L134 CoverageAnalysis]: Checked inductivity of 555 backedges. 330 proven. 225 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-19 07:59:28,747 INFO L327 TraceCheckSpWp]: Computing backward predicates... [2023-11-19 07:59:29,358 INFO L134 CoverageAnalysis]: Checked inductivity of 555 backedges. 330 proven. 225 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-19 07:59:29,358 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [695675171] provided 0 perfect and 2 imperfect interpolant sequences [2023-11-19 07:59:29,358 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2023-11-19 07:59:29,359 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [34, 34, 34] total 52 [2023-11-19 07:59:29,359 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [288751684] [2023-11-19 07:59:29,359 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2023-11-19 07:59:29,415 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-19 07:59:29,416 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 53 interpolants. [2023-11-19 07:59:29,417 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=651, Invalid=2105, Unknown=0, NotChecked=0, Total=2756 [2023-11-19 07:59:29,417 INFO L87 Difference]: Start difference. First operand 132 states and 150 transitions. cyclomatic complexity: 21 Second operand has 53 states, 52 states have (on average 2.576923076923077) internal successors, (134), 53 states have internal predecessors, (134), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-19 07:59:30,376 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-19 07:59:30,377 INFO L93 Difference]: Finished difference Result 427 states and 494 transitions. [2023-11-19 07:59:30,377 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 427 states and 494 transitions. [2023-11-19 07:59:30,380 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 12 [2023-11-19 07:59:30,382 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 427 states to 242 states and 278 transitions. [2023-11-19 07:59:30,382 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 209 [2023-11-19 07:59:30,382 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 209 [2023-11-19 07:59:30,382 INFO L73 IsDeterministic]: Start isDeterministic. Operand 242 states and 278 transitions. [2023-11-19 07:59:30,383 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-19 07:59:30,383 INFO L218 hiAutomatonCegarLoop]: Abstraction has 242 states and 278 transitions. [2023-11-19 07:59:30,383 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 242 states and 278 transitions. [2023-11-19 07:59:30,385 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 242 to 140. [2023-11-19 07:59:30,386 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 140 states, 140 states have (on average 1.1357142857142857) internal successors, (159), 139 states have internal predecessors, (159), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-19 07:59:30,386 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 140 states to 140 states and 159 transitions. [2023-11-19 07:59:30,387 INFO L240 hiAutomatonCegarLoop]: Abstraction has 140 states and 159 transitions. [2023-11-19 07:59:30,387 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 36 states. [2023-11-19 07:59:30,388 INFO L428 stractBuchiCegarLoop]: Abstraction has 140 states and 159 transitions. [2023-11-19 07:59:30,388 INFO L335 stractBuchiCegarLoop]: ======== Iteration 18 ============ [2023-11-19 07:59:30,388 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 140 states and 159 transitions. [2023-11-19 07:59:30,389 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 12 [2023-11-19 07:59:30,389 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-19 07:59:30,389 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-19 07:59:30,390 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [16, 16, 16, 15, 15, 1, 1, 1, 1] [2023-11-19 07:59:30,390 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1] [2023-11-19 07:59:30,390 INFO L748 eck$LassoCheckResult]: Stem: 9843#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(18, 2); 9827#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet1#1, main_#t~nondet3#1, main_#t~post2#1, main_#t~mem5#1, main_#t~mem6#1, main_#t~post4#1, main_#t~mem8#1, main_#t~mem9#1, main_#t~post7#1, main_~#array~0#1.base, main_~#array~0#1.offset, main_~i~0#1, main_~num~0#1;call main_~#array~0#1.base, main_~#array~0#1.offset := #Ultimate.allocOnStack(400000);havoc main_~i~0#1;havoc main_#t~nondet1#1;main_~num~0#1 := main_#t~nondet1#1;havoc main_#t~nondet1#1;main_~i~0#1 := 0; 9828#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 9844#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 9845#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 9831#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 9832#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 9878#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 9877#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 9876#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 9875#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 9874#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 9873#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 9872#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 9871#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 9870#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 9869#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 9868#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 9867#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 9866#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 9865#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 9864#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 9863#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 9862#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 9861#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 9860#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 9859#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 9858#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 9857#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 9856#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 9855#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 9854#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 9853#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 9850#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 9849#L27-3 assume !(main_~i~0#1 < main_~num~0#1); 9833#L27-4 main_~i~0#1 := 0; 9834#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 9840#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 9826#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 9837#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 9842#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 9957#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 9956#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 9954#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 9951#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 9950#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 9948#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 9945#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 9944#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 9942#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 9939#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 9938#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 9936#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 9933#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 9932#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 9930#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 9927#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 9926#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 9924#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 9921#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 9920#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 9918#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 9915#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 9914#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 9912#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 9909#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 9908#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 9906#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 9903#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 9902#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 9900#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 9897#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 9896#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 9894#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 9891#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 9890#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 9888#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 9886#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 9885#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 9882#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 9880#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 9879#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 9848#L34 [2023-11-19 07:59:30,391 INFO L750 eck$LassoCheckResult]: Loop: 9848#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 9851#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 9847#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 9848#L34 [2023-11-19 07:59:30,391 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-19 07:59:30,391 INFO L85 PathProgramCache]: Analyzing trace with hash -1180030839, now seen corresponding path program 30 times [2023-11-19 07:59:30,391 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-19 07:59:30,391 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [540104830] [2023-11-19 07:59:30,392 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-19 07:59:30,392 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-19 07:59:30,487 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-19 07:59:30,488 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-19 07:59:30,551 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-19 07:59:30,561 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-19 07:59:30,562 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-19 07:59:30,562 INFO L85 PathProgramCache]: Analyzing trace with hash 76501, now seen corresponding path program 17 times [2023-11-19 07:59:30,562 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-19 07:59:30,562 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1996439910] [2023-11-19 07:59:30,562 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-19 07:59:30,563 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-19 07:59:30,566 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-19 07:59:30,566 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-19 07:59:30,568 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-19 07:59:30,570 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-19 07:59:30,571 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-19 07:59:30,571 INFO L85 PathProgramCache]: Analyzing trace with hash 8639821, now seen corresponding path program 31 times [2023-11-19 07:59:30,571 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-19 07:59:30,571 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [228412629] [2023-11-19 07:59:30,571 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-19 07:59:30,571 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-19 07:59:30,648 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-19 07:59:31,723 INFO L134 CoverageAnalysis]: Checked inductivity of 632 backedges. 330 proven. 302 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-19 07:59:31,723 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-19 07:59:31,723 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [228412629] [2023-11-19 07:59:31,724 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [228412629] provided 0 perfect and 1 imperfect interpolant sequences [2023-11-19 07:59:31,724 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1962025680] [2023-11-19 07:59:31,724 INFO L93 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2023-11-19 07:59:31,724 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2023-11-19 07:59:31,724 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7bf958de-f854-47fc-9acd-69b8dc140d51/bin/uautomizer-verify-uCwYo4JHxu/z3 [2023-11-19 07:59:31,726 INFO L229 MonitoredProcess]: Starting monitored process 27 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7bf958de-f854-47fc-9acd-69b8dc140d51/bin/uautomizer-verify-uCwYo4JHxu/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2023-11-19 07:59:31,738 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7bf958de-f854-47fc-9acd-69b8dc140d51/bin/uautomizer-verify-uCwYo4JHxu/z3 -smt2 -in SMTLIB2_COMPLIANT=true (27)] Waiting until timeout for monitored process [2023-11-19 07:59:31,907 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-19 07:59:31,909 INFO L262 TraceCheckSpWp]: Trace formula consists of 377 conjuncts, 36 conjunts are in the unsatisfiable core [2023-11-19 07:59:31,912 INFO L285 TraceCheckSpWp]: Computing forward predicates... [2023-11-19 07:59:32,767 INFO L134 CoverageAnalysis]: Checked inductivity of 632 backedges. 376 proven. 256 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-19 07:59:32,767 INFO L327 TraceCheckSpWp]: Computing backward predicates... [2023-11-19 07:59:33,346 INFO L134 CoverageAnalysis]: Checked inductivity of 632 backedges. 376 proven. 256 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-19 07:59:33,347 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1962025680] provided 0 perfect and 2 imperfect interpolant sequences [2023-11-19 07:59:33,347 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2023-11-19 07:59:33,347 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [36, 36, 36] total 55 [2023-11-19 07:59:33,347 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1482483959] [2023-11-19 07:59:33,347 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2023-11-19 07:59:33,403 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-19 07:59:33,404 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 56 interpolants. [2023-11-19 07:59:33,405 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=725, Invalid=2355, Unknown=0, NotChecked=0, Total=3080 [2023-11-19 07:59:33,406 INFO L87 Difference]: Start difference. First operand 140 states and 159 transitions. cyclomatic complexity: 22 Second operand has 56 states, 55 states have (on average 2.581818181818182) internal successors, (142), 56 states have internal predecessors, (142), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-19 07:59:34,312 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-19 07:59:34,312 INFO L93 Difference]: Finished difference Result 453 states and 524 transitions. [2023-11-19 07:59:34,312 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 453 states and 524 transitions. [2023-11-19 07:59:34,315 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 12 [2023-11-19 07:59:34,317 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 453 states to 256 states and 294 transitions. [2023-11-19 07:59:34,318 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 221 [2023-11-19 07:59:34,318 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 221 [2023-11-19 07:59:34,318 INFO L73 IsDeterministic]: Start isDeterministic. Operand 256 states and 294 transitions. [2023-11-19 07:59:34,318 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-19 07:59:34,319 INFO L218 hiAutomatonCegarLoop]: Abstraction has 256 states and 294 transitions. [2023-11-19 07:59:34,319 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 256 states and 294 transitions. [2023-11-19 07:59:34,321 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 256 to 148. [2023-11-19 07:59:34,322 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 148 states, 148 states have (on average 1.135135135135135) internal successors, (168), 147 states have internal predecessors, (168), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-19 07:59:34,322 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 148 states to 148 states and 168 transitions. [2023-11-19 07:59:34,323 INFO L240 hiAutomatonCegarLoop]: Abstraction has 148 states and 168 transitions. [2023-11-19 07:59:34,323 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 38 states. [2023-11-19 07:59:34,324 INFO L428 stractBuchiCegarLoop]: Abstraction has 148 states and 168 transitions. [2023-11-19 07:59:34,324 INFO L335 stractBuchiCegarLoop]: ======== Iteration 19 ============ [2023-11-19 07:59:34,324 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 148 states and 168 transitions. [2023-11-19 07:59:34,325 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 12 [2023-11-19 07:59:34,325 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-19 07:59:34,325 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-19 07:59:34,326 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [17, 17, 17, 16, 16, 1, 1, 1, 1] [2023-11-19 07:59:34,326 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1] [2023-11-19 07:59:34,326 INFO L748 eck$LassoCheckResult]: Stem: 11035#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(18, 2); 11019#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet1#1, main_#t~nondet3#1, main_#t~post2#1, main_#t~mem5#1, main_#t~mem6#1, main_#t~post4#1, main_#t~mem8#1, main_#t~mem9#1, main_#t~post7#1, main_~#array~0#1.base, main_~#array~0#1.offset, main_~i~0#1, main_~num~0#1;call main_~#array~0#1.base, main_~#array~0#1.offset := #Ultimate.allocOnStack(400000);havoc main_~i~0#1;havoc main_#t~nondet1#1;main_~num~0#1 := main_#t~nondet1#1;havoc main_#t~nondet1#1;main_~i~0#1 := 0; 11020#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 11036#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 11037#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 11023#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 11024#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 11072#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 11071#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 11070#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 11069#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 11068#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 11067#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 11066#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 11065#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 11064#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 11063#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 11062#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 11061#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 11060#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 11059#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 11058#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 11057#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 11056#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 11055#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 11054#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 11053#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 11052#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 11051#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 11050#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 11049#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 11048#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 11047#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 11046#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 11045#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 11042#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 11041#L27-3 assume !(main_~i~0#1 < main_~num~0#1); 11025#L27-4 main_~i~0#1 := 0; 11026#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 11032#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 11018#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 11029#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 11034#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 11157#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 11156#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 11154#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 11151#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 11150#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 11148#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 11145#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 11144#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 11142#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 11139#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 11138#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 11136#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 11133#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 11132#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 11130#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 11127#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 11126#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 11124#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 11121#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 11120#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 11118#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 11115#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 11114#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 11112#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 11109#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 11108#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 11106#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 11103#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 11102#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 11100#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 11097#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 11096#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 11094#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 11091#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 11090#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 11088#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 11085#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 11084#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 11082#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 11080#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 11079#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 11076#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 11074#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 11073#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 11040#L34 [2023-11-19 07:59:34,327 INFO L750 eck$LassoCheckResult]: Loop: 11040#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 11043#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 11039#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 11040#L34 [2023-11-19 07:59:34,327 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-19 07:59:34,327 INFO L85 PathProgramCache]: Analyzing trace with hash -1481235061, now seen corresponding path program 32 times [2023-11-19 07:59:34,327 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-19 07:59:34,328 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [822501304] [2023-11-19 07:59:34,328 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-19 07:59:34,328 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-19 07:59:34,438 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-19 07:59:34,438 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-19 07:59:34,520 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-19 07:59:34,531 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-19 07:59:34,531 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-19 07:59:34,531 INFO L85 PathProgramCache]: Analyzing trace with hash 76501, now seen corresponding path program 18 times [2023-11-19 07:59:34,532 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-19 07:59:34,532 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [528825408] [2023-11-19 07:59:34,532 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-19 07:59:34,532 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-19 07:59:34,536 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-19 07:59:34,536 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-19 07:59:34,538 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-19 07:59:34,540 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-19 07:59:34,541 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-19 07:59:34,541 INFO L85 PathProgramCache]: Analyzing trace with hash -979656437, now seen corresponding path program 33 times [2023-11-19 07:59:34,541 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-19 07:59:34,541 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2008418429] [2023-11-19 07:59:34,541 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-19 07:59:34,542 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-19 07:59:34,576 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-19 07:59:35,885 INFO L134 CoverageAnalysis]: Checked inductivity of 714 backedges. 376 proven. 338 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-19 07:59:35,885 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-19 07:59:35,885 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2008418429] [2023-11-19 07:59:35,885 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2008418429] provided 0 perfect and 1 imperfect interpolant sequences [2023-11-19 07:59:35,885 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [2073297699] [2023-11-19 07:59:35,886 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 [2023-11-19 07:59:35,886 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2023-11-19 07:59:35,886 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7bf958de-f854-47fc-9acd-69b8dc140d51/bin/uautomizer-verify-uCwYo4JHxu/z3 [2023-11-19 07:59:35,887 INFO L229 MonitoredProcess]: Starting monitored process 28 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7bf958de-f854-47fc-9acd-69b8dc140d51/bin/uautomizer-verify-uCwYo4JHxu/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2023-11-19 07:59:35,889 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7bf958de-f854-47fc-9acd-69b8dc140d51/bin/uautomizer-verify-uCwYo4JHxu/z3 -smt2 -in SMTLIB2_COMPLIANT=true (28)] Waiting until timeout for monitored process [2023-11-19 07:59:36,842 INFO L228 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 18 check-sat command(s) [2023-11-19 07:59:36,843 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2023-11-19 07:59:36,848 INFO L262 TraceCheckSpWp]: Trace formula consists of 398 conjuncts, 38 conjunts are in the unsatisfiable core [2023-11-19 07:59:36,852 INFO L285 TraceCheckSpWp]: Computing forward predicates... [2023-11-19 07:59:37,869 INFO L134 CoverageAnalysis]: Checked inductivity of 714 backedges. 425 proven. 289 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-19 07:59:37,869 INFO L327 TraceCheckSpWp]: Computing backward predicates... [2023-11-19 07:59:38,537 INFO L134 CoverageAnalysis]: Checked inductivity of 714 backedges. 425 proven. 289 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-19 07:59:38,538 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [2073297699] provided 0 perfect and 2 imperfect interpolant sequences [2023-11-19 07:59:38,538 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2023-11-19 07:59:38,538 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [38, 38, 38] total 58 [2023-11-19 07:59:38,538 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1852667492] [2023-11-19 07:59:38,538 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2023-11-19 07:59:38,586 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-19 07:59:38,587 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 59 interpolants. [2023-11-19 07:59:38,588 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=803, Invalid=2619, Unknown=0, NotChecked=0, Total=3422 [2023-11-19 07:59:38,589 INFO L87 Difference]: Start difference. First operand 148 states and 168 transitions. cyclomatic complexity: 23 Second operand has 59 states, 58 states have (on average 2.586206896551724) internal successors, (150), 59 states have internal predecessors, (150), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0)